WO2022156047A1 - 一种半导体外延结构及其制作方法、led芯片 - Google Patents

一种半导体外延结构及其制作方法、led芯片 Download PDF

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WO2022156047A1
WO2022156047A1 PCT/CN2021/079039 CN2021079039W WO2022156047A1 WO 2022156047 A1 WO2022156047 A1 WO 2022156047A1 CN 2021079039 W CN2021079039 W CN 2021079039W WO 2022156047 A1 WO2022156047 A1 WO 2022156047A1
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layer
layers
sub
energy
energy band
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French (fr)
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林志伟
陈凯轩
蔡建九
卓祥景
程伟
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厦门乾照光电股份有限公司
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Priority to US18/219,035 priority Critical patent/US20230361245A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • the invention relates to the field of light-emitting diodes, and in particular, to a semiconductor epitaxial structure and a manufacturing method thereof, and an LED chip.
  • Light Emitting Diode (English: Light Emitting Diode, referred to as: LED) is a semiconductor electronic component that can emit light. LED has the advantages of high efficiency, long life, small size, low power consumption, etc., and can be used in indoor and outdoor white light lighting, screen display, backlight and other fields.
  • gallium nitride (GaN)-based materials are typical representatives of V-III compound semiconductors, and improving the optoelectronic properties of GaN-based LEDs has become the key to the semiconductor lighting industry.
  • Epitaxial wafers are the primary finished products in the LED fabrication process.
  • the existing GaN-based LED epitaxial wafer includes a substrate, an N-type semiconductor layer, an active region and a P-type semiconductor layer.
  • the substrate is used to provide a growth surface for the epitaxial material
  • the N-type semiconductor layer is used to provide electrons for recombination emission
  • the P-type semiconductor layer is used to provide holes for recombination emission
  • the active region is used to radiate electrons and holes Compound luminescence.
  • the active region includes a plurality of well layers and a plurality of barrier layers, and the plurality of well layers and the plurality of barrier layers are alternately stacked, and the barrier layers confine the electrons and holes injected into the active region in the well layers for composite light emission.
  • the material of the well layer is indium gallium nitride (InGaN) with a high indium composition
  • the material of the barrier layer is gallium nitride (GaN). Since the lattice constant of gallium nitride is 3.181 and the lattice constant of indium nitride is 3.538, there is a large lattice mismatch between the well layer and the barrier layer, as well as between the well layer and the N-type semiconductor layer. Larger lattice mismatch, resulting in the stress caused by the accumulation of lattice mismatch will seriously affect the recombination efficiency of electrons and holes in space, resulting in low luminous efficiency of LEDs.
  • the inventor specially designed a semiconductor epitaxial structure, a method for manufacturing the same, and an LED chip, and this case came into being.
  • the purpose of the present invention is to provide a semiconductor epitaxial structure, a manufacturing method thereof, and an LED chip to solve the problem of large lattice mismatch between the well layer and the barrier layer, and the There is a large lattice mismatch, which leads to the problem that the stress generated by the accumulation of lattice mismatch will seriously affect the recombination efficiency of electrons and holes in space.
  • a semiconductor epitaxial structure comprising:
  • the active region includes n quantum layers stacked in sequence along the first direction, each of the quantum layers includes a potential barrier layer and a potential well layer, and a stress release layer is provided between at least one adjacent two quantum layers ; wherein, n is a positive integer; the first direction is perpendicular to the substrate, and points to the first-type semiconductor layer from the substrate.
  • the energy band of the stress release layer is not smaller than the energy band of the active region, and the lattice constant of the stress release layer is not larger than the lattice constant of the active region.
  • the stress relief layer includes a plurality of sub-stress relief layers stacked in sequence along the first direction, and each of the sub-stress relief layers is presented in a periodic structure.
  • the lattice constants of the sub-stress relief layers with different periodic structures increase along the first direction, and the lattice constants of each of the sub-stress relief layers are not greater than the lattice constant of the active region; different periods The energy bands of the sub stress release layers of the structure decrease along the first direction, and the energy bands of each of the sub stress release layers are not smaller than the energy bands of the active region.
  • the energy bands of each of the sub-stress release layers in the same periodic structure are the same or decrease along the first direction.
  • the lattice constants of each of the sub-stress relief layers in the same periodic structure are the same or increase along the first direction.
  • each of the sub-stress release layers is constituted by alternating cycles of high and low energy band material layers.
  • the lattice constant of each of the low-energy band material layers along the first direction gradually increases; and the energy band of each of the low-energy band material layers along the first direction gradually decreases.
  • each of the sub-stress relief layers includes Al x Ga y In 1-xy N, and the high and low energy band material layers and their corresponding lattice constants and energy band relationships are adjusted by adjusting the composition of Al and or Ga and obtain; wherein, 0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1.
  • the stress release layer is disposed at a boundary between the first quantum layer and the third quantum layer of the active region along the first direction.
  • the stress release layer includes 3 groups of sub-stress release layers presented in a first period and 5 groups of sub-stress relief layers presented in a second period.
  • the energy bands of the low-energy-band material layers in the first period are the same or decrease along the first direction
  • the energy bands of the low-energy-band material layers in the second period are the same or decrease along the first direction.
  • the first direction decreases, and the energy band of any one low-energy band material layer in the first period is greater than the energy band of any one low-energy band material layer in the second period.
  • the present invention also provides a method for fabricating a semiconductor epitaxial structure, the fabrication method comprising the following steps:
  • Step S01 providing a substrate
  • Step S02 growing a first-type semiconductor layer, an active region, and a second-type semiconductor layer on the surface of the substrate in sequence;
  • the active region includes n quantum layers stacked in sequence along the first direction, each of the quantum layers includes a potential barrier layer and a potential well layer, and a stress release layer is provided between at least one adjacent two quantum layers ; wherein, n is a positive integer; the first direction is perpendicular to the substrate, and points to the first-type semiconductor layer from the substrate;
  • the stress release layer is formed by a temperature-variable growth method, the stress release layer includes a plurality of sub-stress release layers stacked in sequence along the first direction, and each of the sub-stress release layers is presented in a periodic structure;
  • the lattice constants of the sub-stress release layers with different periodic structures increase along the first direction; the energy bands of the sub-stress release layers with different periodic structures decrease along the first direction, and the The energy bands are all higher than the energy bands of the active region;
  • the energy bands of each of the sub-stress release layers in the same periodic structure are the same or decrease along the first direction.
  • each of the sub-stress release layers is constituted by alternating high and low energy band material layers; the lattice constant of each of the low energy band material layers along the first direction gradually increases; along the first direction The energy band of each of the low-energy-band material layers gradually decreases;
  • each of the sub-stress release layers includes Al x Ga y In 1-xy N, and the high and low energy band material layers and their corresponding lattice constants and energy band relationships are adjusted by adjusting the composition of Al and or Ga. obtained; wherein, 0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1.
  • the present invention also provides an LED chip, comprising;
  • the N-type electrode forms ohmic contact with the N-type semiconductor layer
  • a P-type electrode which forms an ohmic contact with the P-type semiconductor layer.
  • the semiconductor epitaxial structure provided by the present invention includes a first-type semiconductor layer, an active region, and a second-type semiconductor layer sequentially stacked on the surface of the substrate, and the active region includes n edges.
  • the energy band of the stress release layer is higher than the energy band of the active region, and the lattice constant of the stress release layer is lower than the lattice constant of the active region.
  • the stress release layer includes a plurality of sub stress release layers stacked in sequence along the first direction, and each of the sub stress release layers is presented in a periodic structure; preferably, the crystallites of the sub stress release layers with different periodic structures are The lattice constant increases along the first direction; the energy bands of the sub stress release layers with different periodic structures decrease along the first direction, and the energy bands of each of the sub stress release layers are higher than the energy of the active region band; the energy band of each of the sub-stress release layers in the same periodic structure is the same or decreases along the first direction.
  • the lattice matching between the potential well layer, the barrier layer and the first-type semiconductor layer is more sufficient, so that the recombination efficiency of electrons and holes in the active region in space can be effectively improved, and the inhibition is obtained.
  • the stress release layer at the boundary between the first quantum layer and the third quantum layer in the active region along the first direction, the lattice matching of the stress release layer is ensured.
  • the dislocation between the active region and the first-type semiconductor layer can be suppressed more effectively.
  • the manufacturing method of the semiconductor epitaxial structure provided by the present invention achieves the beneficial effects of the above semiconductor epitaxial structure, and at the same time, the manufacturing process is simple and convenient, and it is convenient for production.
  • the LED chip provided by the present invention is obtained on the basis of the above-mentioned semiconductor epitaxial structure. Therefore, while having the beneficial effects of the above-mentioned semiconductor epitaxial structure, the process is simple and convenient, and is convenient for production.
  • FIG. 1 is a schematic structural diagram of a semiconductor epitaxial structure provided by an embodiment of the present invention
  • FIG. 2 is a schematic diagram of the energy band relationship between a stress release layer and an active region quantum layer provided by an embodiment of the present invention
  • FIG. 3 is a schematic diagram of the relationship between the lattice constants of the stress release layer and the quantum layer of the active region according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of the energy band relationship between a stress release layer and an active region quantum layer provided by another embodiment of the present invention.
  • FIG. 5 is a schematic diagram of the relationship between the lattice constants of the stress relief layer and the active region quantum layer provided by another embodiment of the present invention.
  • a semiconductor epitaxial structure includes:
  • the active region 3 includes n quantum layers stacked in sequence along the first direction, each quantum layer includes a barrier layer 3.1 and a potential well layer 3.2, and at least a stress release layer 4 is arranged between two adjacent quantum layers. ; wherein, n is a positive integer; the first direction is perpendicular to the substrate 1 and points to the first-type semiconductor layer 2 from the substrate 1 .
  • the type of the substrate 1 is not limited in the semiconductor epitaxial structure of this embodiment.
  • the substrate 1 may be, but not limited to, a sapphire substrate, a silicon substrate, and the like.
  • the specific material types of the first-type semiconductor layer 2, the active region 3, and the second-type semiconductor layer 5 may not be limited in the semiconductor epitaxial structure of this embodiment.
  • the first-type semiconductor layer may be but not limited to The gallium nitride layer
  • the second type semiconductor layer may be, but not limited to, a gallium nitride layer.
  • the energy band of the stress release layer 4 is not smaller than the energy band of the active region 3
  • the lattice constant of the stress release layer 4 is not larger than the lattice constant of the active region 3 .
  • the stress relief layer 4 includes a plurality of sub stress relief layers 4 stacked in sequence along the first direction, and each sub stress relief layer 4 is presented in a periodic structure.
  • the lattice constants of the sub-stress relief layers 4 with different periodic structures increase along the first direction, and the lattice constants of each sub-stress relief layer 4 are not greater than the lattice constant of the active region 3;
  • the energy bands of the sub stress release layers 4 of the structure decrease along the first direction, and the energy bands of each sub stress release layer 4 are not smaller than the energy bands of the active region 3 .
  • the energy bands of each sub-stress release layer 4 in the same periodic structure are the same or decrease along the first direction.
  • the lattice constants of the sub-stress relief layers 4 in the same periodic structure are the same or increase along the first direction.
  • each sub-stress release layer 4 is constituted by alternating high and low energy band material layers.
  • the lattice constant of each low-energy band material layer along the first direction gradually increases; the energy band of each low-energy band material layer along the first direction gradually decreases.
  • each sub-stress release layer 4 includes Al x Ga y In 1-xy N, and the high and low energy band material layers and their corresponding lattice constants and energy band relationships are adjusted by adjusting the composition of Al and or Ga and obtain; wherein, 0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1.
  • the stress release layer 4 is disposed at the boundary between the first quantum layer and the third quantum layer of the active region 3 along the first direction.
  • the stress release layer 4 includes 3 groups of sub-stress release layers 4 presented in a first period and 5 groups of sub-stress relief layers 4 presented in a second period.
  • FIG. 2 shows a schematic diagram of the energy band relationship between the stress release layer and the quantum layer in the active region provided by the embodiment of the present invention. It is only an example of stress release layers presented with two periodic structures. The energy band of each of the sub-stress release layers in the same periodic structure decreases along the first direction; this is not a limitation of the present invention.
  • FIG. 3 is a schematic diagram showing the relationship between the lattice constants of the stress release layer and the quantum layer in the active region provided by the embodiment of the present invention, which is only an example of the stress release layer presented with two periodic structures.
  • the lattice constants of each of the sub-stress relief layers in the same periodic structure increase along the first direction, which is not a limitation of the present invention.
  • FIG. 4 is a schematic diagram showing the energy band relationship between the stress release layer and the quantum layer in the active region provided by other embodiments of the present invention.
  • the energy bands of each of the sub-stress release layers are the same; it is not a limitation of the present invention.
  • FIG. 5 is a schematic diagram showing the relationship between the lattice constants of the stress release layer and the quantum layer in the active region provided by other embodiments of the present invention, which is only an example to illustrate the stress release layer with two periodic structures, the same periodic structure
  • the lattice constants of each of the sub-stress relief layers within are the same; it is not a limitation of the present invention.
  • FIG. 2 to FIG. 5 only illustrate that the energy bands of the barrier layer 3.1 of the active region 3 and the high-energy band material layers of the stress release layer 4 are always the same.
  • the stress The energy band of each high-energy band material layer of the release layer 4 can be graded, which is not specifically limited in the present invention.
  • the energy bands of each low-energy-band material layer in the first cycle are the same or decrease along the first direction, and the energy bands of each low-energy-band material layer in the second cycle are the same Or decreasing along the first direction, and the energy band of any one low-energy band material layer in the first period is greater than the energy band of any one low-energy band material layer in the second period.
  • the embodiment of the present invention also provides a method for fabricating a semiconductor epitaxial structure, and the fabrication method includes the following steps:
  • Step S01 providing a substrate 1;
  • Step S02 growing a first-type semiconductor layer 2, an active region 3, and a second-type semiconductor layer 5 on the surface of the substrate 1 in sequence;
  • the active region 3 includes n quantum layers stacked in sequence along the first direction, each quantum layer includes a barrier layer 3.1 and a potential well layer 3.2, and at least a stress release layer 4 is arranged between two adjacent quantum layers. ; wherein, n is a positive integer; the first direction is perpendicular to the substrate 1, and the substrate 1 points to the first-type semiconductor layer 2;
  • the stress-releasing layer 4 is formed by a temperature-changing growth method, and the stress-releasing layer 4 includes a plurality of sub-stress-releasing layers 4 stacked in sequence along the first direction, and each sub-stress-releasing layer 4 is presented in a periodic structure;
  • the lattice constants of the sub-stress release layers 4 with different periodic structures increase along the first direction; the energy bands of the sub-stress release layers 4 with different periodic structures decrease along the first direction, and the energy bands of the sub-stress release layers 4 are equal to each other. higher than the energy band of active region 3;
  • the energy bands of the sub-stress release layers 4 in the same periodic structure are the same or decrease along the first direction.
  • each sub-stress release layer 4 is constituted by alternating high and low energy band material layers; the lattice constant of each low energy band material layer along the first direction gradually increases; each low energy band along the first direction The energy band of the material layer gradually decreases;
  • each sub-stress release layer 4 includes Al x Ga y In 1-xy N, and the high and low energy band material layers and their corresponding lattice constants and energy band relationships are obtained by adjusting the composition of Al and or Ga; wherein , 0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1.
  • Embodiments of the present invention also provide an LED chip, comprising:
  • N-type electrode which forms ohmic contact with the N-type semiconductor layer
  • the P-type electrode forms an ohmic contact with the P-type semiconductor layer.
  • the semiconductor epitaxial structure provided by the embodiment of the present invention includes a first-type semiconductor layer 2, an active region 3, and a second-type semiconductor layer 5 stacked on the surface of the substrate 1 in sequence, and the active region 3 includes n quantum layers stacked in sequence along the first direction, each quantum layer includes a potential barrier layer 3.1 and a potential well layer 3.2, and a stress release layer 4 is provided between at least one adjacent two quantum layers to solve the problem of potential
  • the energy band of the stress release layer 4 is higher than that of the active region 3 , and the lattice constant of the stress release layer 4 is lower than that of the active region 3 .
  • the stress release layer 4 includes a plurality of sub stress release layers 4 stacked in sequence along the first direction, and each sub stress release layer 4 is presented in a periodic structure; preferably, the lattice constants of the sub stress release layers 4 with different periodic structures It increases along the first direction; the energy bands of the sub stress release layers 4 with different periodic structures decrease along the first direction, and the energy bands of each sub stress release layer 4 are higher than the energy band of the active region 3; The energy band of each sub-stress release layer 4 is the same or decreases along the first direction.
  • the lattice matching between the potential well layer 3.2, the barrier layer 3.1 and the first-type semiconductor layer 2 is more sufficient, so that the recombination efficiency of electrons and holes in the active region 3 can be effectively improved, And a high-quality first-type semiconductor layer 2 in which the occurrence of dislocations is suppressed is obtained.
  • the stress release layer 4 at the boundary between the first quantum layer and the third quantum layer in the first direction of the active region 3, while ensuring the beneficial effect of lattice matching of the stress release layer 4, The dislocation between the active region 3 and the first-type semiconductor layer 2 can be suppressed more effectively.
  • the manufacturing method of the semiconductor epitaxial structure provided by the embodiment of the present invention achieves the beneficial effects of the above semiconductor epitaxial structure, and at the same time, the process is simple and convenient to manufacture, and is convenient for production.
  • the LED chip provided by the embodiment of the present invention is obtained on the basis of the above-mentioned semiconductor epitaxial structure. Therefore, while having the beneficial effects of the above-mentioned semiconductor epitaxial structure, the manufacturing process thereof is simple and convenient, which is convenient for production. .

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Abstract

本发明提供了一种半导体外延结构及其制作方法、LED芯片，包括在所述衬底表面依次堆叠的第一型半导体层、有源区、第二型半导体层，所述有源区包括n个沿第一方向依次层叠的量子层，各所述量子层包括势垒层和势阱层，且至少在一相邻的两个量子层之间设有应力释放层，以解决因势阱层和势垒层之间、以及势阱层与第一型半导体层之间所同时存在的晶格失配问题，从而避免因累加的晶格失配所产生的应力对电子和空穴在空间的复合效率的影响。

Description

一种半导体外延结构及其制作方法、LED芯片
本申请要求于2021年01月21日提交中国专利局、申请号为202110079258.5、发明创造名称为“一种半导体外延结构及其制作方法、LED芯片”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及发光二极管领域，尤其涉及一种半导体外延结构及其制作方法、LED芯片。
背景技术
发光二极管(英文：Light Emitting Diode，简称：LED)是一种能发光的半导体电子元件。LED具有效率高、寿命长、体积小、功耗低等优点，可以应用于室内外白光照明、屏幕显示、背光源等领域。在LED产业的发展中，氮化镓(GaN)基材料是V-III族化合物半导体的典型代表，提高GaN基LED的光电性能已成为半导体照明产业的关键。
外延片是LED制备过程中的初级成品。现有的GaN基LED外延片包括衬底、N型半导体层、有源区和P型半导体层。衬底用于为外延材料提供生长表面，N型半导体层用于提供进行复合发光的电子，P型半导体层用于提供进行复合发光的空穴，有源区用于进行电子和空穴的辐射复合发光。
有源区包括多个阱层和多个垒层，多个阱层和多个垒层交替层叠设置，垒层将注入有源区的电子和空穴限定在阱层中进行复合发光。通常阱层的材料采用高铟组分的氮化铟镓(InGaN)，垒层的材料采用氮化镓(GaN)。由于氮化镓的晶格常数为3.181，氮化铟的晶格常数为3.538，因此阱层和垒层之间存在较大的晶格失配，以及阱层与N型半导体层之间亦存在较大的晶格失配，导致因晶格失配累加产生的应力会严重影响电子和空穴在空间的复合效率，使LED的发光效率较低。
有鉴于此，本发明人专门设计了一种半导体外延结构及其制作方法、LED芯片，本案由此产生。
发明内容
本发明的目的在于提供一种半导体外延结构及其制作方法、LED芯片，以解决因阱层和垒层之间存在较大的晶格失配，以及阱层与第一型半导体层之间亦存在较大的晶格失配，导致因晶格失配累加产生的应力会严重影响电子和空穴在空间的复合效率的问题。
为了实现上述目的，本发明采用的技术方案如下：
一种半导体外延结构，包括：
衬底；
在所述衬底表面依次堆叠的第一型半导体层、有源区、第二型半导体层；
所述有源区包括n个沿第一方向依次层叠的量子层，各所述量子层包括势垒层和势阱层，且至少在一相邻的两个量子层之间设有应力释放层；其中，n为正整数；所述第一方向垂直于所述衬底，并由所述衬底指向所述第一型半导体层。
优选地，所述应力释放层的能带不小于所述有源区的能带，且所述应力释放层的晶格常数不大于所述有源区的晶格常数。
优选地，所述应力释放层包括若干个沿所述第一方向依次堆叠的子应力释放层，且各所述子应力释放层以周期结构呈现。
优选地，不同周期结构的子应力释放层的晶格常数沿所述第一方向递增，且各所述子应力释放层的晶格常数均不大于所述有源区的晶格常数；不同周期结构的子应力释放层的能带沿所述第一方向递减，且各所述子应力释放层的能带均不小于所述有源区的能带。
优选地，同一周期结构内的各所述子应力释放层的能带相同或沿所述第一方向递减。
优选地，同一周期结构内的各所述子应力释放层的晶格常数相同或沿所述第一方向递增。
优选地，各所述子应力释放层通过交替循环的高、低能带材料层构成。
优选地，沿所述第一方向的各所述低能带材料层的晶格常数逐渐增大；沿所述第一方向的各所述低能带材料层的能带逐渐减小。
优选地，各所述子应力释放层包括Al xGa yIn 1-x-yN，且所述高、低能带材料层及其对应的晶格常数与能带关系通过调节Al和或Ga的组分而获得；其中，0≤x＜1，0<y≤1。
优选地，所述应力释放层设置于所述有源区沿所述第一方向的第一量子层至第三量子层之间的交界处。
优选地，所述应力释放层包括3组以第一周期呈现的子应力释放层及5组以第二周期呈现的子应力释放层。
优选地，所述第一周期内的各所述低能带材料层的能带相同或沿所述第一方向递减，所述第二周期内的各所述低能带材料层的能带相同或沿所述第一方向递减，且所述第一周期内的任意一低能带材料层的能带大于所述第二周期内的任意一低能带材料层的能带。
本发明还提供了一种半导体外延结构的制作方法，所述制作方法包括如下步骤：
步骤S01、提供一衬底；
步骤S02、在所述衬底表面依次生长第一型半导体层、有源区、第二型半导体层；
所述有源区包括n个沿第一方向依次层叠的量子层，各所述量子层包括势垒层和势阱层，且至少在一相邻的两个量子层之间设有应力释放层；其中，n为正整数；所述第一方向垂直于所述衬底，并由所述衬底指向所述第一型半导体层；
通过变温的生长方式形成所述应力释放层，所述应力释放层包括若干个沿所述第一方向依次堆叠的子应力释放层，且各所述子应力释放层以周期结构呈现；
其中，不同周期结构的子应力释放层的晶格常数沿所述第一方向递增；不同周期结构的子应力释放层的能带沿所述第一方向递减，且各所述子应力释放层的能带均高于所述有源区的能带；
同一周期结构内的各所述子应力释放层的能带相同或沿所述第一方向递减。
优选地，各所述子应力释放层通过交替循环的高、低能带材料层构成；沿所述第一方向的各所述低能带材料层的晶格常数逐渐增大；沿所述第一方向的各所述低能带材料层的能带逐渐减小；
其中，各所述子应力释放层包括Al xGa yIn 1-x-yN，且所述高、低能带材料层及其对应的晶格常数与能带关系通过调节Al和或Ga的组分而获得；其中，0≤x＜1，0<y≤1。
本发明还提供了一种LED芯片，包括；
上述任一项所述的半导体外延结构；
N型电极，所述N型电极与所述N型半导体层形成欧姆接触；
P型电极，所述P型电极与所述P型半导体层形成欧姆接触。
经由上述的技术方案可知，本发明提供的半导体外延结构，包括在所述衬底表面依次堆叠的第一型半导体层、有源区、第二型半导体层，所述有源区包括n个沿第一方向依次层叠的量子层，各所述量子层包括势垒层和势阱层，且至少在一相邻的两个量子层之间设有应力释放层，以解决因势阱层和势垒层之间、以及势阱层与第一型半导体层之间所同时存在的晶格失配问题，从而避免因累加的晶格失配所产生的应力对电子和空穴在空间的复合效率的影响。
其次，所述应力释放层的能带高于所述有源区的能带，且所述应力释放层的晶格常数低于所述有源区的晶格常数。其中，所述应力释放层包括若干个沿所述第一方向依次堆叠的子应力释放层，且各所述子应力释放层以周期结构呈现；优选地，不同周期结构的子应力释放层的晶格常数沿所述第一方向递增；不同周期结构的子应力释放层的能带沿所述第一方向递减，且各所述子应力释放层的能带均高于所述有源区的能带；同一周期结构内的各所述子应力释放层的能带相同或沿所述第一方向递减。进一步地使势阱层与势垒层及第一型半导体层三者之间的晶格匹配更加充分，从而可以有效地提高有源区的电子和空穴在空间的复合效率，并获得抑制了位错发生的高品质的第一型半导体层。
然后，通过将所述应力释放层设置于所述有源区沿所述第一方向的第一量子层至第三量子层之间的交界处，在保证所述应力释放层的晶格匹配的有益效果的同时，可更加有效地抑制有源区与第一型半导体层的位错。
经由上述的技术方案可知，本发明提供的半导体外延结构的制作方法，在实现上述半导体外延结构的有益效果的同时，其工艺制作简单便捷，便于生产化。
经由上述的技术方案可知，本发明提供的LED芯片，通过在上述的半导体外延结构的基础上获得，因此其具有上述半导体外延结构的有益效果的同时，其工艺制作简单便捷，便于生产化。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为本发明实施例所提供的半导体外延结构的结构示意图；
图2为本发明实施例所提供的应力释放层与有源区量子层的能带关系示意图；
图3为本发明实施例所提供的应力释放层与有源区量子层的晶格常数关系示意图；
图4为本发明另一实施例所提供的应力释放层与有源区量子层的能带关系示意图；
图5为本发明另一实施例所提供的应力释放层与有源区量子层的晶格常数关系示意图；
图中符号说明：1、衬底，2、第一型半导体层，3、有源区，3.1、势垒层，3.2、势阱层，4、应力释放层，5、第二型半导体层。
具体实施方式
为使本发明的内容更加清晰，下面结合附图对本发明的内容作进一步 说明。本发明不局限于该具体实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
如图1所示，一种半导体外延结构，包括：
衬底1；
在衬底1表面依次堆叠的第一型半导体层2、有源区3、第二型半导体层5；
有源区3包括n个沿第一方向依次层叠的量子层，各量子层包括势垒层3.1和势阱层3.2，且至少在一相邻的两个量子层之间设有应力释放层4；其中，n为正整数；第一方向垂直于衬底1，并由衬底1指向第一型半导体层2。
值得一提的是，衬底1的类型在本实施例的半导体外延结构不受限制，例如，衬底1可以是但不限于蓝宝石衬底、硅衬底等。另外，第一型半导体层2、有源区3、第二型半导体层5的具体材料类型在本实施例的半导体外延结构也可以不受限制，例如，第一型半导体层可以是但不限于氮化镓层，相应地，第二型半导体层可以是但不限于氮化镓层。
本发明实施例中，应力释放层4的能带不小于有源区3的能带，且应力释放层4的晶格常数不大于有源区3的晶格常数。
本发明实施例中，应力释放层4包括若干个沿第一方向依次堆叠的子应力释放层4，且各子应力释放层4以周期结构呈现。
本发明实施例中，不同周期结构的子应力释放层4的晶格常数沿第一方向递增，且各子应力释放层4的晶格常数均不大于有源区3的晶格常数；不同周期结构的子应力释放层4的能带沿第一方向递减，且各子应力释放层4的能带均不小于有源区3的能带。
本发明实施例中，同一周期结构内的各子应力释放层4的能带相同或沿第一方向递减。
本发明实施例中，同一周期结构内的各子应力释放层4的晶格常数相同或沿第一方向递增。
本发明实施例中，各子应力释放层4通过交替循环的高、低能带材料 层构成。
本发明实施例中，沿第一方向的各低能带材料层的晶格常数逐渐增大；沿第一方向的各低能带材料层的能带逐渐减小。
本发明实施例中，各子应力释放层4包括Al xGa yIn 1-x-yN，且高、低能带材料层及其对应的晶格常数与能带关系通过调节Al和或Ga的组分而获得；其中，0≤x＜1，0<y≤1。
本发明实施例中，应力释放层4设置于有源区3沿第一方向的第一量子层至第三量子层之间的交界处。
本发明实施例中，如图2所示，应力释放层4包括3组以第一周期呈现的子应力释放层4及5组以第二周期呈现的子应力释放层4。
需要说明的是，图2所示为本发明实施例所提供的应力释放层与有源区量子层的能带关系示意图，其仅是举例示意了以两种周期结构呈现的应力释放层时，同一周期结构内的各所述子应力释放层的能带沿所述第一方向递减；并非对本发明的限制。
需要说明的是，图3所示为本发明实施例所提供的应力释放层与有源区量子层的晶格常数关系示意图，其仅是举例示意了以两种周期结构呈现的应力释放层时，同一周期结构内的各所述子应力释放层的晶格常数沿所述第一方向递增，并非对本发明的限制。
图4所示为本发明其他实施例所提供的应力释放层与有源区量子层的能带关系示意图，其仅是举例示意了以两种周期结构呈现的应力释放层时，同一周期结构内的各所述子应力释放层的能带相同；并非对本发明的限制。
图5所示为本发明其他实施例所提供的应力释放层与有源区量子层的晶格常数关系示意图，其仅是举例示意了以两种周期结构呈现的应力释放层时，同一周期结构内的各所述子应力释放层的晶格常数相同；并非对本发明的限制。
需要说明的是，图2至图5仅举例示意了有源区3的势垒层3.1与应力释放层4的各高能带材料层的能带始终持平，在本发明的其他实施例中，应力释放层4的各高能带材料层的能带可渐变，本发明不对此做具体限定。
本发明实施例中，如图2、图4所示，第一周期内的各低能带材料层 的能带相同或沿第一方向递减，第二周期内的各低能带材料层的能带相同或沿第一方向递减，且第一周期内的任意一低能带材料层的能带大于第二周期内的任意一低能带材料层的能带。
本发明实施例还提供了一种半导体外延结构的制作方法，制作方法包括如下步骤：
步骤S01、提供一衬底1；
步骤S02、在衬底1表面依次生长第一型半导体层2、有源区3、第二型半导体层5；
有源区3包括n个沿第一方向依次层叠的量子层，各量子层包括势垒层3.1和势阱层3.2，且至少在一相邻的两个量子层之间设有应力释放层4；其中，n为正整数；第一方向垂直于衬底1，并由衬底1指向第一型半导体层2；
通过变温的生长方式形成应力释放层4，应力释放层4包括若干个沿第一方向依次堆叠的子应力释放层4，且各子应力释放层4以周期结构呈现；
其中，不同周期结构的子应力释放层4的晶格常数沿第一方向递增；不同周期结构的子应力释放层4的能带沿第一方向递减，且各子应力释放层4的能带均高于有源区3的能带；
同一周期结构内的各子应力释放层4的能带相同或沿第一方向递减。
本发明实施例中，各子应力释放层4通过交替循环的高、低能带材料层构成；沿第一方向的各低能带材料层的晶格常数逐渐增大；沿第一方向的各低能带材料层的能带逐渐减小；
其中，各子应力释放层4包括Al xGa yIn 1-x-yN，且高、低能带材料层及其对应的晶格常数与能带关系通过调节Al和或Ga的组分而获得；其中，0≤x＜1，0<y≤1。
本发明实施例还提供了一种LED芯片，包括；
上述任一项的半导体外延结构；
N型电极，N型电极与N型半导体层形成欧姆接触；
P型电极，P型电极与P型半导体层形成欧姆接触。
经由上述的技术方案可知，本发明实施例提供的半导体外延结构，包括在衬底1表面依次堆叠的第一型半导体层2、有源区3、第二型半导体层5，有源区3包括n个沿第一方向依次层叠的量子层，各量子层包括势垒层3.1和势阱层3.2，且至少在一相邻的两个量子层之间设有应力释放层4，以解决因势阱层3.2和势垒层3.1之间、以及势阱层3.2与第一型半导体层2之间所同时存在的晶格失配问题，从而避免因累加的晶格失配所产生的应力对电子和空穴在空间的复合效率的影响。
其次，应力释放层4的能带高于有源区3的能带，且应力释放层4的晶格常数低于有源区3的晶格常数。其中，应力释放层4包括若干个沿第一方向依次堆叠的子应力释放层4，且各子应力释放层4以周期结构呈现；优选地，不同周期结构的子应力释放层4的晶格常数沿第一方向递增；不同周期结构的子应力释放层4的能带沿第一方向递减，且各子应力释放层4的能带均高于有源区3的能带；同一周期结构内的各子应力释放层4的能带相同或沿第一方向递减。进一步地使势阱层3.2与势垒层3.1及第一型半导体层2三者之间的晶格匹配更加充分，从而可以有效地提高有源区3的电子和空穴在空间的复合效率，并获得抑制了位错发生的高品质的第一型半导体层2。
然后，通过将应力释放层4设置于有源区3沿第一方向的第一量子层至第三量子层之间的交界处，在保证应力释放层4的晶格匹配的有益效果的同时，可更加有效地抑制有源区3与第一型半导体层2的位错。
经由上述的技术方案可知，本发明实施例提供的半导体外延结构的制作方法，在实现上述半导体外延结构的有益效果的同时，其工艺制作简单便捷，便于生产化。
经由上述的技术方案可知，本发明实施例提供的LED芯片，通过在上述的半导体外延结构的基础上获得，因此其具有上述半导体外延结构的有益效果的同时，其工艺制作简单便捷，便于生产化。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。
还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括上述要素的物品或者设备中还存在另外的相同要素。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其它实施例中实现。因此，本申请将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (14)

  1. 一种半导体外延结构，其特征在于，包括：
    衬底；
    在所述衬底表面依次堆叠的第一型半导体层、有源区、第二型半导体层；
    所述有源区包括n个沿第一方向依次层叠的量子层，各所述量子层包括势垒层和势阱层，且至少在一相邻的两个量子层之间设有应力释放层；其中，n为正整数；所述第一方向垂直于所述衬底，并由所述衬底指向所述第一型半导体层。
  2. 根据权利要求1所述的半导体外延结构，其特征在于，所述应力释放层的能带不小于所述有源区的能带，且所述应力释放层的晶格常数不大于所述有源区的晶格常数。
  3. 根据权利要求1所述的半导体外延结构，其特征在于，所述应力释放层包括若干个沿所述第一方向依次堆叠的子应力释放层，且各所述子应力释放层以周期结构呈现。
  4. 根据权利要求3所述的半导体外延结构，其特征在于，不同周期结构的子应力释放层的晶格常数沿所述第一方向递增，且各所述子应力释放层的晶格常数均不大于所述有源区的晶格常数；不同周期结构的子应力释放层的能带沿所述第一方向递减，且各所述子应力释放层的能带均不小于所述有源区的能带。
  5. 根据权利要求3所述的半导体外延结构，其特征在于，同一周期结构内的各所述子应力释放层的能带相同或沿所述第一方向递减。
  6. 根据权利要求3所述的半导体外延结构，其特征在于，各所述子应力释放层通过交替循环的高、低能带材料层构成。
  7. 根据权利要求6所述的半导体外延结构，其特征在于，沿所述第一方向的各所述低能带材料层的晶格常数逐渐增大；沿所述第一方向的各所述低能带材料层的能带逐渐减小。
  8. 根据权利要求6所述的半导体外延结构，其特征在于，各所述子应力 释放层包括Al xGa yIn 1-x-yN，且所述高、低能带材料层及其对应的晶格常数与能带关系通过调节Al和或Ga的组分而获得；其中，0≤x＜1，0<y≤1。
  9. 根据权利要求1所述的半导体外延结构，其特征在于，所述应力释放层设置于所述有源区沿所述第一方向的第一量子层至第三量子层之间的交界处。
  10. 根据权利要求8所述的半导体外延结构，其特征在于，所述应力释放层包括3组以第一周期呈现的子应力释放层及5组以第二周期呈现的子应力释放层。
  11. 根据权利要求10所述的半导体外延结构，其特征在于，所述第一周期内的各所述低能带材料层的能带相同或沿所述第一方向递减，所述第二周期内的各所述低能带材料层的能带相同或沿所述第一方向递减，且所述第一周期内的任意一低能带材料层的能带大于所述第二周期内的任意一低能带材料层的能带。
  12. 一种半导体外延结构的制作方法，其特征在于，所述制作方法包括如下步骤：
    步骤S01、提供一衬底；
    步骤S02、在所述衬底表面依次生长第一型半导体层、有源区、第二型半导体层；
    所述有源区包括n个沿第一方向依次层叠的量子层，各所述量子层包括势垒层和势阱层，且至少在一相邻的两个量子层之间设有应力释放层；其中，n为正整数；所述第一方向垂直于所述衬底，并由所述衬底指向所述第一型半导体层；
    通过变温的生长方式形成所述应力释放层，所述应力释放层包括若干个沿所述第一方向依次堆叠的子应力释放层，且各所述子应力释放层以周期结构呈现；
    其中，不同周期结构的子应力释放层的晶格常数沿所述第一方向递增；不同周期结构的子应力释放层的能带沿所述第一方向递减，且各所述子应力释放 层的能带均高于所述有源区的能带；
    同一周期结构内的各所述子应力释放层的能带相同或沿所述第一方向递减。
  13. 根据权利要求12所述的半导体外延结构的制作方法，其特征在于，各所述子应力释放层通过交替循环的高、低能带材料层构成；沿所述第一方向的各所述低能带材料层的晶格常数逐渐增大；沿所述第一方向的各所述低能带材料层的能带逐渐减小；
    其中，各所述子应力释放层包括Al xGa yIn 1-x-yN，且所述高、低能带材料层及其对应的晶格常数与能带关系通过调节Al和或Ga的组分而获得；其中，0≤x＜1，0<y≤1。
  14. 一种LED芯片，其特征在于，包括；
    权利要求1-11任一项所述的半导体外延结构；
    N型电极，所述N型电极与所述N型半导体层形成欧姆接触；
    P型电极，所述P型电极与所述P型半导体层形成欧姆接触。
PCT/CN2021/079039 2021-01-21 2021-03-04 一种半导体外延结构及其制作方法、led芯片 WO2022156047A1 (zh)

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