WO2023273361A1 - 存储单元及其制备方法、存储器及其制备方法 - Google Patents

存储单元及其制备方法、存储器及其制备方法 Download PDF

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Publication number
WO2023273361A1
WO2023273361A1 PCT/CN2022/076315 CN2022076315W WO2023273361A1 WO 2023273361 A1 WO2023273361 A1 WO 2023273361A1 CN 2022076315 W CN2022076315 W CN 2022076315W WO 2023273361 A1 WO2023273361 A1 WO 2023273361A1
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Prior art keywords
transistor
layer
dielectric layer
memory
gate
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PCT/CN2022/076315
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English (en)
French (fr)
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肖德元
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长鑫存储技术有限公司
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Priority to KR1020227027303A priority Critical patent/KR20230006631A/ko
Priority to JP2022549941A priority patent/JP2023535101A/ja
Priority to EP22743699.5A priority patent/EP4138135A4/en
Priority to US17/664,052 priority patent/US20230005911A1/en
Publication of WO2023273361A1 publication Critical patent/WO2023273361A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

Definitions

  • the present disclosure relates to the technical field of semiconductors, and in particular to a storage unit and a manufacturing method thereof, a memory and a manufacturing method thereof.
  • Dynamic random access memory (Dynamic random access memory, referred to as DRAM) is a semiconductor memory that writes and reads data at high speed and randomly, and is widely used in data storage devices or devices.
  • DRAM usually includes a substrate and a memory cell array and peripheral circuits composed of a plurality of repeated memory cells arranged on the substrate.
  • the plurality of memory cells are arranged at intervals along a direction parallel to the substrate, wherein each memory cell usually includes a capacitor structure and a transistor. , the gate of the transistor is connected to the word line in the memory cell array, the drain is connected to the bit line in the memory cell array, and the source is connected to the capacitor structure.
  • a first aspect of an embodiment of the present disclosure provides a method for manufacturing a storage unit, which includes:
  • a second transistor located in a second dielectric layer, the second dielectric layer being located above the first dielectric layer;
  • connecting wire located in the first dielectric layer and the second dielectric layer, one end of the connecting wire is connected to the first transistor, and the other end is connected to the second transistor;
  • the first transistor and the second transistor are metal oxide thin film transistors.
  • a second aspect of an embodiment of the present disclosure provides a memory, including:
  • the surface of the substrate is provided with peripheral circuits
  • a plurality of storage units as described above are located above the peripheral circuit;
  • the data line is used to connect the peripheral circuit and each of the storage units.
  • a plurality of the storage units are stacked along a direction perpendicular to the substrate to form a vertical array.
  • a third aspect of the embodiments of the present disclosure provides a method for manufacturing a storage unit, including the following steps:
  • the first transistor being a metal oxide thin film transistor
  • connection wire forming a part of a connection wire in the first dielectric layer, one end of the connection wire is connected to the first transistor;
  • Another part of the connecting wire is formed in the second dielectric layer, and one end of the connecting wire close to the first dielectric layer is connected to the connecting wire formed in the first dielectric layer;
  • a second transistor is formed in the second dielectric layer, the second transistor is connected to an end of the connection wire away from the first dielectric layer, and the second transistor is a metal oxide thin film transistor.
  • a fourth aspect of the embodiments of the present disclosure provides a method for manufacturing a memory, including the following steps:
  • a plurality of storage units are sequentially formed on the substrate, and the plurality of storage units are arranged in a direction parallel to the substrate to form a horizontal array, and/or, a plurality of the storage units are arranged in a direction perpendicular to the substrate direction stacking to form a vertical array; wherein, the storage unit is prepared by the above storage unit preparation method;
  • a data line is formed, and the data line is used to connect the peripheral circuit and each of the storage units.
  • FIG. 1 is a schematic structural diagram of a storage unit provided by Embodiment 1 of the present disclosure
  • FIG. 2 is a schematic structural diagram of a memory provided by Embodiment 2 of the present disclosure.
  • FIG. 3 is a circuit diagram of a memory provided in Embodiment 2 of the present disclosure.
  • FIG. 4 is a process flow diagram of a method for preparing a storage unit provided in Embodiment 3 of the present disclosure
  • FIG. 5 is a schematic structural diagram of an active layer formed in the method for manufacturing a memory cell provided in Embodiment 3 of the present disclosure
  • FIG. 6 is a schematic structural diagram of forming a first transistor in the method for manufacturing a memory cell provided in Embodiment 3 of the present disclosure
  • FIG. 7 is a schematic structural diagram of forming a second insulating layer in the method for manufacturing a memory cell provided in Embodiment 3 of the present disclosure.
  • FIG. 8 is a schematic structural diagram of forming a first contact portion and a metal line in the method for manufacturing a memory cell provided in Embodiment 3 of the present disclosure
  • FIG. 9 is a schematic structural diagram of forming a second contact portion and an active layer in the method for manufacturing a memory cell provided in Embodiment 3 of the present disclosure.
  • FIG. 10 is a schematic structural diagram of forming a second transistor in the method for manufacturing a memory cell provided in Embodiment 3 of the present disclosure.
  • each storage unit usually includes a plurality of repeated storage units, which are arranged at intervals along a direction parallel to the substrate, wherein each storage unit includes a capacitor and a transistor, so that the memory has a larger volume, as the DRAM
  • each storage unit still uses the above-mentioned one transistor and one capacitor (1 Transistor 1 Capacitor, referred to as 1T1C).
  • 1T1C Transistor 1 Capacitor
  • the embodiments of the present disclosure provide a memory cell and its manufacturing method, a memory cell and its manufacturing method.
  • the parasitic capacitance of the storage element is used as a storage element to replace the capacitor in the related art, which can reduce the volume occupied by the storage unit, improve the integration degree of the storage unit, and provide guarantee for the development of the storage unit in the direction of integration.
  • both the first transistor and the second transistor are metal oxide thin film transistors, so that the memory can have a higher retention time, and while reducing the volume of the memory, the performance of the memory can also be improved.
  • an embodiment of the present disclosure provides a storage unit 100, which may include a first dielectric layer 120 and a second dielectric layer 140 disposed on the first dielectric layer 120.
  • the first dielectric layer 120 The first transistor 110 is arranged in the second dielectric layer 140, and the second transistor 130 is arranged in the second dielectric layer 140.
  • the first transistor 110 and the second transistor 130 are connected by the connecting wire 150 arranged in the first dielectric layer 120 and the second dielectric layer 140.
  • the first transistor 110 and the second transistor 130 may be metal oxide thin film transistors.
  • the storage unit 100 involved in this embodiment includes a stacked first transistor 110 and a second transistor 130, using the parasitic capacitance in the first transistor 110 or the second transistor 130 as a storage element to replace the capacitor in the related art, which can Reducing the volume occupied by the storage unit 100 provides guarantee for the development of the storage unit 100 towards integration.
  • both the first transistor 110 and the second transistor 130 are metal oxide thin film transistors, which can make the memory have a higher retention time, and can improve the performance of the memory while reducing the volume of the memory.
  • first transistor 110 and the second transistor 130 are the same.
  • first transistor 110 as an example to describe the structure of the first transistor 110 .
  • the first transistor 110 includes an active layer 111, a gate oxide layer 112, and a gate 113, wherein the active layer 111 includes a channel region and a source and a drain positioned on both sides of the channel region
  • the gate oxide layer 112 and the gate 113 are sequentially stacked on the active layer 111, and the projection of the gate 113 on the active layer 111 covers the channel region, so that the gap between the gate 113 and the active layer 111 is There is an overlapping area, so that when a voltage difference is formed between the active layer 111 and the gate 113, a capacitance will be formed between the gate 113 and the active layer 111, and the capacitance will be used as a storage element of the memory cell to realize data storage. read or write.
  • the material of the active layer 111 may include InGaZnO, which has higher carrier mobility, which can greatly improve the sensitivity of the first transistor and reduce the power consumption.
  • the material of the gate oxide layer 112 may include silicon oxide and/or aluminum oxide, and the material of the gate 113 may include one of titanium nitride, tantalum nitride, aluminum and tungsten.
  • the projection of the gate 113 on the active layer 111 covers the channel region. It can be understood that the projected area of the gate 113 on the active layer 111 is equal to the area of the channel region , it can also be understood that the projected area of the gate 113 on the active layer 111 is smaller than the area of the channel region.
  • the first transistor 110 further includes a protective layer 114, which is located on the sides of the gate 113 and the gate oxide layer 112, and the electrical isolation between the gate and other devices is realized by setting the protective layer 114.
  • connection wire 150 may be connected to the gate of the first transistor 110, and the other end may be connected to the source or drain of the second transistor 130, and the second transistor 130 may connect to the source or drain of the second transistor 130.
  • An electrical signal is used to control the first transistor 110 to be turned on or off.
  • the shape of the connecting wire 150 can be selected in various ways, for example, the connecting wire 150 can be a straight line, and for example, the connecting wire 150 can also be a broken line.
  • the connecting wire 150 includes a first contact portion 151, a metal wire 152, and a second contact portion 153, wherein both the first contact portion 151 and the second contact portion 153 extend along a vertical direction, that is, the first contact The part 151 and the second contact part 153 are arranged along the direction perpendicular to the first dielectric layer 120, the metal wire 152 extends along the horizontal direction, and one end of the metal wire 152 is connected with the first contact part 151, and one end of the metal wire 152 is connected with the second The contacts 153 are connected.
  • the first contact portion 151 is connected to the gate 113 of the first transistor 110
  • the second contact portion 153 is connected to the source or the drain of the second transistor 130 .
  • one end of the metal wire 152 is connected to the first contact portion 151. It can be understood that one end of the metal wire 152 is connected to the middle position of the first contact portion 151. It can also be understood that one end of the metal wire 152 is connected to the middle position of the first contact portion 151. Ends of the first contact portion 151 are connected.
  • one end of the metal line 152 may be connected to the end of the first contact portion 151 away from the gate 113 of the first transistor 110, and the other end of the metal line 152 may be connected to the end of the second contact portion 153 away from the second transistor 130. .
  • the first contact portion 151 and the metal wire 152 can be located in the first dielectric layer 120, and the second contact portion 153 can be located in the second dielectric layer 140, but the above-mentioned method is only one way of connecting the wire 150
  • the connecting wires 150 can also be entirely arranged in the first dielectric layer 120 or can be entirely arranged in the second dielectric layer 140 .
  • a barrier layer 160 is also provided between the first dielectric layer 120 and the second dielectric layer 140, and the barrier layer 160 is located above the metal line 152 , the second contact portion 153 passes through the barrier layer 160 and is connected to the metal line 152 .
  • the material of the barrier layer 160 includes insulating materials such as silicon oxynitride.
  • an embodiment of the present disclosure also provides a memory 200 , which includes: a substrate 210 , a memory unit 100 and a data line 220 .
  • the substrate 210 is used as a supporting component of the memory for supporting other components disposed thereon, wherein the substrate 210 can be made of a semiconductor material, and the semiconductor material can be one of silicon, germanium, a silicon-germanium compound, and a silicon-carbon compound. one or more species.
  • a peripheral circuit 211 is disposed on the surface of the substrate 210, and the peripheral circuit 211 may include a logic circuit or a processing circuit.
  • a plurality of storage units 100 are disposed above the peripheral circuit 211 , and each storage unit 100 is connected to the peripheral circuit 211 through a data line 220 .
  • the peripheral circuit by arranging the peripheral circuit under the storage unit, compared with the technical solution in the related art where the peripheral circuit is arranged on both sides of the storage unit along the horizontal direction, the area of the memory can be reduced, and the development of the memory towards integration can be provided. Assure.
  • the data lines 220 include a read word line 221 , a read bit line 222 , a write word line 223 and a write bit line 224 .
  • the write word line 223 and the write bit line 224 can be arranged in the second dielectric layer 140, the write word line 223 extends in the first direction and connects the gates of the second transistors 130 in the plurality of memory cells 100, and the write The input bit line 224 extends in the second direction and is connected to the sources or drains of the second transistors 130 in the plurality of memory cells 100 , and is not at the same end as the connecting wire 150 .
  • connection wire 150 is connected to the source of the second transistor 130 , then the write bit line 224 is connected to the drain of the second transistor 130 .
  • the read word line 221 and the read bit line 222 can be arranged in the first dielectric layer 120, and the read word line 221 extends in the third direction and connects the sources or drains of the first transistors 110 in the plurality of memory cells 100 , the read bit line 222 extends in the fourth direction and is connected to the sources or drains of the first transistors 110 in the plurality of memory cells 100 , and is not the same end as the read word line.
  • the read word line 221 is connected to the source of the first transistor 110 , correspondingly, the read bit line 222 is connected to the drain of the first transistor 110 .
  • the projections of the first direction and the second direction on a plane parallel to or perpendicular to the base have a first included angle
  • the projections of the third direction and the fourth direction on a plane parallel to or perpendicular to the base have a second included angle
  • both the first included angle and the second included angle are non-zero, that is, the write word line and the write bit line are intersected, and the read word line and the read bit line are also intersected.
  • the high level can control the gate of the second transistor 130 to be turned on, and a voltage difference is generated between the source and the drain of the second transistor 130, The source and drain of the second transistor are turned on, the voltage on the write bit line 224 will act on the gate of the first transistor 110, and the data on the write bit line 224 will be written into the first transistor , to achieve data writing.
  • the gate of the first transistor 110 will be opened, so that the source and the drain of the first transistor will be opened. At this time, the data in the first transistor 110 will be read by The bit line 222 transmits the data to the peripheral circuit 211, and the peripheral circuit 211 processes the data to realize the memory reading function.
  • a plurality of storage units 100 are arranged in a direction parallel to the base 210 to form a horizontal array, that is, a plurality of storage units 100 are arranged in sequence along the horizontal direction, while a plurality of storage units 100 are arranged in a direction perpendicular to the base 210 Stacking forms a vertical array.
  • a plurality of storage units 100 are stacked in a direction perpendicular to the substrate 210 to form a vertical array, which can reduce the number of storage units 100 arranged in sequence along the horizontal direction and reduce the number of storage units 100.
  • the occupied area increases the integration degree of the storage unit, which provides a guarantee for the development of the storage in the direction of integration.
  • multiple storage units 100 are stacked along the direction perpendicular to the substrate 210 to form a vertical array.
  • the height of the memory can be increased to reduce the The width of the memory along the horizontal direction further reduces the volume of the memory and improves the integration degree of the memory unit.
  • a peripheral dielectric layer 230 is disposed on the substrate 210 , and the peripheral dielectric layer 230 covers the peripheral circuit 211 to realize electrical isolation between units in the peripheral circuit 211 .
  • the material of the peripheral dielectric layer 230 may include silicon oxide.
  • peripheral barrier layer 240 between the peripheral dielectric layer 230 and the first dielectric layer 120 of the memory unit 100 .
  • the peripheral barrier layer 240 is used to prevent the conductive material in the first dielectric layer from affecting the performance of peripheral circuits.
  • the data line 220 needs to pass through the peripheral barrier layer 240 and the peripheral dielectric layer 230 before being connected to the peripheral circuit 211 .
  • the embodiment of the present disclosure also provides a method for preparing a storage unit, including the following steps:
  • Step S100 forming a first transistor in the first dielectric layer, the first transistor being a metal oxide thin film transistor.
  • the first dielectric layer 120 can be the carrier body of the first transistor 110 , or can be used as an insulating medium between the first transistor 110 and other devices, and the material of the first dielectric layer 120 can include silicon oxide or silicon nitride.
  • the manufacturing process of the first transistor 110 may be performed in the following manner, for example:
  • Step a providing a first insulating layer.
  • first insulating layer 121 is a part of the above-mentioned first dielectric layer 120 .
  • Step b forming an active layer on the first insulating layer, where the material of the active layer includes InGaZnO.
  • the active layer 111 may be formed on the first insulating layer 121 by a deposition process, wherein the deposition process may be one of a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process .
  • Step c forming a channel region in the active layer, and a source and a drain respectively located on both sides of the channel region.
  • a photoresist layer may be formed on the active layer 111, and the photoresist layer may be patterned to form an opening in the photoresist layer, which may expose a portion of the active layer 111, and then, using The ion implantation process implants dopant ions into the opening to form a source in the active layer 111 .
  • the drain is formed in the active layer 111 by using the above-mentioned process.
  • Step d forming a gate oxide layer on the active layer, the length of the gate oxide layer being shorter than that of the active layer.
  • a certain thickness of silicon oxide or aluminum oxide is deposited on the active layer 111 through a deposition process, and the silicon oxide or aluminum oxide constitutes the gate oxide layer 112 .
  • Step e forming a gate on the gate oxide layer, and the projection of the gate on the active layer covers the channel region.
  • the material of the gate 113 may include one of titanium nitride, tantalum nitride, aluminum and tungsten.
  • Step f forming a protective layer on the active layer, the protective layer is wrapped around the sides of the gate and the gate oxide layer, and its structure is shown in FIG. 6 .
  • An initial protection layer can be formed on the active layer by a deposition process, and the initial protection layer covers the sides of the gate oxide layer and the top and side surfaces of the gate, and then the top surface of the gate is removed by using etching gas or etching solution.
  • the initial protection layer on the surface, the initial protection layer remaining on the sides of the gate and the gate oxide layer constitute the protection layer 116 .
  • Step g Form a second insulating layer covering the active layer, gate oxide layer, gate and protective layer on the first insulating layer, the second insulating layer and the first insulating layer constitute the first dielectric layer, and its structure is shown in Figure 7 shown.
  • Step S200 forming a part of a connection wire in the first dielectric layer, one end of the connection wire is connected to the first transistor.
  • a first contact portion 151 and a metal line 152 connected to the first contact portion 151 are formed in the second insulating layer 122 , the first contact portion 151 extends in a vertical direction, and is connected to the first contact portion 151 .
  • the gate 113 of the transistor 110 is connected, the metal line 152 extends in the horizontal direction, and the first contact portion 151 and the metal line 152 constitute a part of the connecting wire.
  • the first contact portion 151 and the metal wire 152 are formed by a double damascene process, and may also be formed by a single damascene process twice.
  • one end of the connecting wire can be understood as the end of the first contact portion away from the metal wire.
  • Step S300 forming a second dielectric layer on the first dielectric layer.
  • the barrier layer 160 can be formed on the first dielectric layer 120, that is to say, the barrier layer 160 can be formed on the second insulating layer 122 first, and the barrier layer can be used to prevent Conductive materials interdiffuse.
  • the material of the second dielectric layer and the first dielectric layer may be the same, both may include silicon oxide, wherein the second dielectric layer 140 may include a third insulating layer 141 and a fourth insulating layer 142 stacked in sequence, the third insulating layer Layer 141 is disposed on barrier layer 160 .
  • Step S400 forming another part of the connection wire in the second dielectric layer, and the end of the connection wire close to the first dielectric layer is connected to the connection wire formed in the first dielectric layer.
  • a filling groove can be formed in the second dielectric layer, the filling groove exposes a part of the metal line 152, and then a conductive material is formed in the filling groove by using a deposition process, and the conductive material constitutes the second contact portion 153, the second The contact portion 153 is connected to the metal wire 152 , so that the first contact portion 151 , the second contact portion 153 and the metal wire 152 constitute a connection wire.
  • Step S500 forming a second transistor in the second dielectric layer, the second transistor is connected to an end of the connecting wire away from the first dielectric layer, wherein the second transistor is a metal oxide thin film transistor.
  • a third insulating layer 141 is formed on the first dielectric layer 120 .
  • the active layer 111 can be formed on the third insulating layer 141 by a deposition process, and the material of the active layer 111 includes InGaZnO.
  • the step of forming the active layer on the third insulating layer is the same as the step of forming the active layer on the first insulating layer, and will not be repeated here in this embodiment.
  • Step c to step f are repeated to form the second transistor 130 on the third insulating layer 141 , the structure of which is shown in FIG. 10 .
  • a fourth insulating layer 142 covering the active layer, gate oxide layer, gate and protective layer is formed on the third insulating layer 141, and the fourth insulating layer 142 and the third insulating layer 141 constitute the first insulating layer 141.
  • Two dielectric layers 140 are formed on the third insulating layer 141, and the fourth insulating layer 142 and the third insulating layer 141 constitute the first insulating layer 141.
  • the first transistor and the second transistor are stacked to form the first transistor and the second transistor through the above steps, and the first transistor or the second transistor is used as the storage device of the storage unit to replace the capacitor in the related art, which can reduce the cost of the storage unit. Occupies less volume, improves the integration of storage units, and provides guarantee for the development of storage units in the direction of integration.
  • An embodiment of the present disclosure provides a method for preparing a memory, including the following steps:
  • Step S10 providing a substrate, the surface of which is provided with peripheral circuits.
  • the peripheral circuit can be prepared by the preparation method in the prior art, and this embodiment will not repeat it here.
  • a peripheral dielectric layer 230 covering the peripheral circuit can be formed on the substrate.
  • a peripheral barrier layer 240 is formed on the peripheral dielectric layer 230 by a deposition process.
  • Step S20 sequentially forming a plurality of storage units on the substrate, the plurality of storage units are arranged in a direction parallel to the substrate to form a horizontal array, and/or, a plurality of storage units are stacked in a direction perpendicular to the substrate to form a vertical array.
  • the storage unit is manufactured through the method for preparing the storage unit in the above-mentioned embodiments, and details are not repeated in this embodiment.
  • Step S30 forming a data line, which is used to connect the peripheral circuit and each memory unit.
  • the formation of the data line can be divided into two steps, one step can be completed before the step of forming the first transistor, and the other step can be completed after the step of forming the second transistor.
  • a read word line 221 and a read bit line 222 that are insulated from each other can be formed in the first dielectric layer 120, and the read word line 221 is used to connect a plurality of memory cells
  • the read word line 221 is used to connect a plurality of memory cells
  • the source or drain of the first transistor 110 in 100, the read bit line 222 is used to connect the source or drain of the first transistor 110 in a plurality of memory cells 100, and is not connected to the connection end of the read word line 221 for the same end.
  • the first transistor 110 can be formed in the first dielectric layer 120, the second dielectric layer 140 can be formed on the first dielectric layer 120, and the second dielectric layer 140 can be formed on the second dielectric layer.
  • the second transistor 130 is formed in 140 .
  • a write word line 223 and a write bit line 224 can be formed in the second dielectric layer 140, and the write word line 223 is used to connect the gates of the second transistor 130 in the plurality of memory cells 100.
  • the writing bit line 224 is used to connect the source or drain of the second transistor 130 in the plurality of memory cells 100 , and is not the same end as the connecting end of the connecting wire 150 .
  • the read word line, the read bit line, the write word line and the write bit line can all be prepared by a double damascene process.
  • the area occupied by the plurality of storage units can be reduced, and the memory capacity can be reduced.
  • the size of the storage unit is improved.
  • the peripheral circuit is arranged under the memory cell, compared with the technical solution in the related art where the peripheral circuit is arranged outside the memory cell array, the size of the memory can be further reduced and the integration degree can be improved.

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Abstract

本公开提供一种存储单元及其制备方法、存储器及其制备方法，涉及半导体技术领域，该存储单元包括层叠设置的第一介质层和第二介质层，其中第一介质层内设置有第一晶体管，第二介质层内设置有第二晶体管，第一晶体管与第二晶体管之间利用连接导线连接。本公开通过利用第一晶体管或者第二晶体管中的寄生电容作为存储元件，来替换相关技术中的电容器，可以降低存储单元所占的体积，为存储单元向集成化方向发展提供保障。另外，第一晶体管和第二晶体管均为金属氧化物薄膜晶体管，可以使得存储器可以具有较高的保留时间，在降低存储器在体积的同时，也能提高存储器的性能。

Description

存储单元及其制备方法、存储器及其制备方法
本公开要求于2021年07月02日提交中国专利局、申请号为202110753695.0、申请名称为“存储单元及其制备方法、存储器及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体技术领域，尤其涉及一种存储单元及其制备方法、存储器及其制备方法。
背景技术
动态随机存储器(Dynamic random access memory，简称DRAM)是一种高速地、随机地写入和读取数据的半导体存储器，被广泛地应用到数据存储设备或装置中。
DRAM通常包括基底以及设置在基底上的多个重复的存储单元组成的存储单元阵列和外围电路，多个存储单元沿平行于基底的方向间隔设置，其中，每个存储单元通常包括电容结构和晶体管，晶体管的栅极与存储单元阵列中的字线相连、漏极与存储单元阵列中的位线相连、源极与电容结构相连。
但是，上述结构无法适应小尺寸的存储器的制备。
发明内容
本公开实施例的第一方面提供一种存储单元的制备方法，其包括：
第一晶体管，位于第一介质层内；
第二晶体管，位于第二介质层内，所述第二介质层位于所述第一介质层上方；
连接导线，位于所述第一介质层和第二介质层中，所述连接导线的一端与所述第一晶体管连接，另一端与所述第二晶体管连接；
其中，所述第一晶体管和所述第二晶体管为金属氧化物薄膜晶体管。
本公开实施例的第二方面提供一种存储器，包括：
基底，所述基底表面设置有外围电路；
多个如上所述的存储单元，位于所述外围电路的上方；
数据线，用于连接所述外围电路与各所述存储单元。
如上所述的存储器，其中，多个所述存储单元在沿平行于所述基底的方向排列形成水平阵列；
和/或，多个所述存储单元在沿垂直于所述基底的方向堆叠形成垂直阵列。
本公开实施例的第三方面提供一种存储单元的制备方法，包括如下步骤：
在所述第一介质层内形成第一晶体管，所述第一晶体管为金属氧化物薄膜晶体管；
在所述第一介质层内形成连接导线的一部分，该连接导线的一端与所述第一晶体管连接；
在所述第一介质层上形成第二介质层；
在所述第二介质层内形成连接导线另一部分，该连接导线靠近所述第一介质层的一端与形成在第一介质层内的连接导线连接；
在所述第二介质层内形成第二晶体管，所述第二晶体管与所述连接导线背离所述第一介质层的一端连接，所述第二晶体管为金属氧化物薄膜晶体管。
本公开实施例的第四方面提供一种存储器的制备方法，包括如下的步骤：
提供基底，所述基底的表面设置有外围电路；
在所述基底上依次形成多个存储单元，多个所述存储单元在沿平行于所述基底的方向排列形成水平阵列，和/或，多个所述存储单元在沿垂直于所述基底的方向堆叠形成垂直阵列；其中，所述存储单元通过如上所述存储单元的制备方法制得；
形成数据线，所述数据线用于连接所述外围电路与各所述存储单元。
除了上面所描述的本公开实施例解决的技术问题、构成技术方案的技术特征以及由这些技术方案的技术特征所带来的有益效果外，本公开实施 例提供的存储单元及其制备方法、存储器及其制备方法所能解决的其他技术问题、技术方案中包含的其他技术特征以及这些技术特征带来的有益效果，将在具体实施方式中作出进一步详细的说明。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例一提供的存储单元的结构示意图；
图2为本公开实施例二提供的存储器的结构示意图；
图3为本公开实施例二提供的存储器的电路图；
图4为本公开实施例三提供的存储单元的制备方法的工艺流程图；
图5为本公开实施例三提供的存储单元的制备方法中形成有源层的结构示意图；
图6为本公开实施例三提供的存储单元的制备方法中形成第一晶体管的结构示意图；
图7为本公开实施例三提供的存储单元的制备方法中形成第二绝缘层的结构示意图；
图8为本公开实施例三提供的存储单元的制备方法中形成第一接触部和金属线的结构示意图；
图9为本公开实施例三提供的存储单元的制备方法中形成第二接触部和有源层的结构示意图；
图10为本公开实施例三提供的存储单元的制备方法中形成第二晶体管的结构示意图。
具体实施方式
动态随机存储器通常包括多个重复存储单元，多个重复储存单元沿平行于基底的方向间隔设置，其中，每个存储单元都包括电容器和晶体管，使得存储器具有较大的体积，随着动态随机存储器向集成化的方向发展，每个存储单元仍然采用上述一个晶体管和一个电容器(1 Transistor 1  Capacitor，简称1T1C)，其中，特别是电容器受到尺寸微缩的限制，难以保证存储单元中电荷的存储量以及保留时间，进而降低存储器的性能。
基于上述的技术问题，本公开实施例提供了一种存储单元及其制备方法、存储器及其制备方法，存储单元包括层叠设置的第一晶体管和第二晶体管，利用第一晶体管或者第二晶体管中的寄生电容作为存储元件，来替换相关技术中的电容器，可以降低存储单元所占的体积，提高存储单元的集成度，为存储单元向集成化方向发展提供保障。
另外，第一晶体管和第二晶体管均为金属氧化物薄膜晶体管，可以使得存储器可以具有较高的保留时间，在降低存储器在体积的同时，也能提高存储器的性能。
为了使本公开实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本公开保护的范围。
实施例一
如图1所示，本公开实施例提供了一种存储单元100，该存储单元100可以包括第一介质层120以及设置在第一介质层120上的第二介质层140，第一介质层120内设置有第一晶体管110，第二介质层140内设置有第二晶体管130，第一晶体管110和第二晶体管130通过设置在第一介质层120和第二介质层140内的连接导线150连接，其中，第一晶体管110和第二晶体管130可以为金属氧化物薄膜晶体管。
本实施例中涉及的存储单元100包括层叠设置的第一晶体管110和第二晶体管130，利用第一晶体管110或者第二晶体管130中的寄生电容作为存储元件，来替换相关技术中的电容器，可以降低存储单元100所占的体积，为存储单元100向集成化方向发展提供保障。
另外，第一晶体管110和第二晶体管130均为金属氧化物薄膜晶体管，可以使得存储器具有较高的保留时间，在降低存储器在体积的同时，也能提高存储器的性能。
需要说明的是，第一晶体管110和第二晶体管130的结构相同，为了便于描述，以下的实施例均以第一晶体管110为例，对第一晶体管110的结构进行描述。
示例性地，继续参考图1，第一晶体管110包括有源层111、栅氧化层112以及栅极113，其中，有源层111包括沟道区以及位于沟道区两侧的源极和漏极，栅氧化层112和栅极113依次层叠设置在有源层111上，且栅极113在有源层111上的投影覆盖在沟道区上，使得栅极113与有源层111之间具有重叠区域，这样当有源层111与栅极113之间形成电压差时，栅极113与有源层111之间会形成电容，该电容会作为存储单元的存储元件，以实现对数据的读取或者写入。
此外，在本实施例中有源层111的材质可以包括铟镓锌氧化物，铟镓锌氧化物具有较高的载流子迁移率，可以大大提高第一晶体管的灵敏度，降低了存储单元的功耗。
栅氧化层112的材质可以包括氧化硅和/或氧化铝，栅极113的材质可以包括氮化钛、氮化钽、铝和钨中一种。
需要说明的是，在本实施例中栅极113在有源层上111投影覆盖在沟道区上，可以理解为，栅极113在有源层111上的投影面积与沟道区的面积相等，也可以理解为，栅极113在有源层111上的投影面积小于沟道区的面积。
进一步地，第一晶体管110还包括保护层114，保护层114位于栅极113和栅氧化层112的侧面，通过保护层114的设置实现栅极与其他器件之间电器隔离。
在一些实施例中，连接导线150的一端可以与第一晶体管110的栅极连接，另一端可以与第二晶体管130的源极或者漏极连接，通过第二晶体管130的源极或者漏极上电信号，来控制第一晶体管110的打开或者关闭。
需要说明的是，连接导线150的形状可以多种选择，比如，连接导线150可以为直线，又比如，连接导线150也可以为折线。
示例性地，连接导线150包括第一接触部151、金属线152以及第二接触部153，其中，第一接触部151和第二接触部153均沿垂直方向延伸，也就是说，第一接触部151和第二接触部153均沿垂直于第一介质层120的方向设置，金属线152沿水平方向延伸，且金属线152的一端与第一接 触部151连接，金属线152一端与第二接触部153连接。
第一接触部151与第一晶体管110的栅极113连接，第二接触部153与第二晶体管130的源极或漏极连接。
在本实施例中，金属线152的一端与第一接触部151连接，可以理解为，金属线152的一端与第一接触部151的中间位置连接，也可以理解为，金属线152的一端与第一接触部151的端部连接。
比如，金属线152的一端可以与第一接触部151背离第一晶体管110的栅极113的端部连接，金属线152的另一端可以与第二接触部153背离第二晶体管130的端部连接。
在一些实施例中，第一接触部151和金属线152可以位于第一介质层120内，第二接触部153可以位于第二介质层140内，但是，上述的方式仅是连接导线150的一种设置方式，连接导线150还可以全部设置的第一介质层120内或者可以全部设置在第二介质层140内。
为了防止第一介质层120和第二介质层140内的导电材料相互扩散，第一介质层120与第二介质层140之间还设置有阻挡层160，且阻挡层160位于金属线152的上方，第二接触部153贯穿阻挡层160后与金属线152连接。
其中，阻挡层160的材质包括氮氧化硅等绝缘材质。
实施例二
如图2所示，本公开实施例还提供了一种存储器200，其包括：基底210、存储单元100以及数据线220。
其中，基底210作为存储器的支撑部件，用于支撑设在其上的其他部件，其中，基底210可以由半导体材料制成，半导体材料可以为硅、锗、硅锗化合物以及硅碳化合物中的一种或者多种。
基底210的表面上设置有外围电路211，外围电路211可以包括逻辑电路或者处理电路。
多个存储单元100设置在外围电路211的上方，且各个存储单元100通过数据线220与外围电路211连接。
本实施例通过将外围电路设置在存储单元的下方，与相关技术中，外围电路设置在存储单元沿水平方向的两侧的技术方案相比，可以降低存储 器的面积，为存储器向集成化发展提供保障。
进一步地，如图2所示，数据线220包括读取字线221、读取位线222、写入字线223和写入位线224。
写入字线223和写入位线224可以设置在第二介质层140内，写入字线223在第一方向上延伸并连接多个存储单元100中的第二晶体管130的栅极，写入位线224在第二方向上延伸并连接多个存储单元100中第二晶体管130的源极或漏极，且与连接导线150连接端不为同一端。
也就是说，若连接导线150与第二晶体管130的源极连接，那么写入位线224就与第二晶体管130的漏极连接。
读取字线221和读取位线222可以设置在第一介质层120内，读取字线221在第三方向上延伸并连接多个存储单元100中的第一晶体管110的源极或漏极，读取位线222在第四方向上延伸并连接多个存储单元100中第一晶体管110的源极或漏极，且与读取字线的连接端不为同一端。
也就是说，如果读取字线221连接第一晶体管110的源极，相应地，读取位线222连接第一晶体管110的漏极。
第一方向和第二方向在平行于或垂直于基底的平面上的投影具有第一夹角，第三方向和第四方向在平行于或垂直于基底的平面上的投影具有第二夹角，其中，第一夹角和第二夹角均不为零，即，写入字线与写入位线是交叉设置的，读取字线与读取位线也为交叉设置的。
如图3所示，当给写入字线223上施加高电平时，该高电平可以控制第二晶体管130的栅极打开，第二晶体管130的源极和漏极之间产生电压差，使得第二晶体管的源极和漏极之间导通，写入位线224上的电压会作用在第一晶体管110的栅极上，将写入位线224上的数据写入第一晶体管内，实现数据的写入。
若是需要读取第一晶体管内的数据时，第一晶体管110的栅极会打开，使得第一晶体管的源极与漏极之间打开，此时，第一晶体管110内的数据会通过读取位线222，传递至外围电路211内，外围电路211会对该数据进行处理，以实现存储器读取功能。
在一些实施例中，多个存储单元100在沿平行于基底210的方向排列形成水平阵列，即多个存储单元100沿着水平方向依次设置，同时多个存储单元100沿垂直于基底210的方向堆叠形成垂直阵列，本实施例通过多 个存储单元100在沿垂直于基底210的方向堆叠形成垂直阵列，可以减少沿水平方向上依次排布的存储单元100的个数，降低了多个存储单元所占用的面积，提高存储单元的集成度，为存储器向集成化方向发展提供了保障。
此外，多个存储单元100在沿垂直于基底210的方向堆叠形成垂直阵列，与现有技术中，多个存储单元沿着水平方向分布的技术方案相比，可以通过增加存储器的高度，来降低存储器的沿水平方向的宽度，进而降低存储器的体积，提高存储单元的集成度。
在一些实施例中，基底210上设置有外围介质层230，外围介质层230覆盖外围电路211，实现外围电路211中各个单元之间的电气隔离。
其中，外围介质层230的材质可以包括氧化硅。
进一步地，外围介质层230与存储单元100的第一介质层120之间还具有外围阻挡层240，利用外围阻挡层240的设置，防止第一介质层内的导电材质影响外围电路的性能。
当外围介质层230与第一介质层120之间设置有外围阻挡层240时，数据线220需要穿过外围阻挡层240和外围介质层230后，与外围电路211连接。
实施例三
如图4所示，本公开实施例还提供了一种存储单元的制备方法，包括如下步骤：
步骤S100：在第一介质层内形成第一晶体管，第一晶体管为金属氧化物薄膜晶体管。
第一介质层120可以为作为第一晶体管110的承载主体，也可以作为第一晶体管110与其他器件之间的绝缘介质，第一介质层120的材质可以包括氧化硅或者氮化硅。
第一晶体管110的制备工艺可以采用如下的方式进行，示例性地：
步骤a：提供第一绝缘层。
需要说明的是，第一绝缘层121为上述第一介质层120的一部分。
步骤b：在第一绝缘层上形成有源层，有源层的材质包括铟镓锌氧化物。
示例性地，如图5所示，可以采用沉积工艺在第一绝缘层121上形成有源层111，其中，沉积工艺可以为物理气相沉积工艺、化学气相沉积工艺或者原子层沉积工艺的一种。
步骤c：在有源层内形成沟道区，以及分别位于沟道区两侧的源极和漏极。
在此步骤中，可以在有源层111上形成光刻胶层，图形化光刻胶层，以在光刻胶层内形成开口，该开口可以暴露出有源层111的部分，然后，利用离子注入工艺向开口内注入掺杂离子，以在有源层111内形成源极。
然后再利用上述的工艺，在有源层111内形成漏极。
步骤d：在有源层上形成栅氧化层，栅氧化层的长度小于有源层的长度。
通过沉积工艺在有源层111上沉积一定厚度的氧化硅或者氧化铝，该氧化硅或者氧化铝构成栅氧化层112。
步骤e：在栅氧化层上形成栅极，栅极在有源层上的投影覆盖沟道区上。
继续采用沉积工艺在栅氧化层112上形成栅极113，其中，栅极113的材质可以包括氮化钛、氮化钽、铝和钨中一种。
步骤f：在有源层上形成保护层，保护层包裹在栅极和栅氧化层的侧面，其结构如图6所示。
可以通过沉积工艺在有源层上形成初始保护层，该初始保护层覆盖在栅氧化层的侧面和栅极的顶面及侧面上，然后利用刻蚀气体或者刻蚀液去除位于栅极的顶面上的初始保护层，保留在栅极和栅氧化层的侧面的初始保护层构成保护层116。
步骤g：在第一绝缘层上形成覆盖有源层、栅氧化层、栅极以及保护层的第二绝缘层，第二绝缘层和第一绝缘层构成第一介质层，其结构如图7所示。
步骤S200：在第一介质层内形成连接导线的一部分，该连接导线的一端与第一晶体管连接。
示例性地，如图8所示，在第二绝缘层122内形成第一接触部151以及与第一接触部151连接的金属线152，第一接触部151沿垂直方向延伸，并与第一晶体管110的栅极113连接，金属线152沿水平方向延伸，第一 接触部151和金属线152构成连接导线的一部分。
在此步骤中，第一接触部151和金属线152采用双大马士革工艺形成的，也可以采用两次单大马士革工艺形成的。
需要说明的是，在本实施例中连接导线的一端可以理解为第一接触部背离金属线的一端。
步骤S300：在第一介质层上形成第二介质层。
示例性地，可以在第一介质层120上形成阻挡层160，也就是说，可以先在第二绝缘层122上形成阻挡层160，利用阻挡层防止第一介质层和第二介质层内的导电材料相互扩散。
其中，第二介质层和第一介质层的材质可以相同，均可以包括氧化硅，其中，第二介质层140可以包括依次层叠设置的第三绝缘层141和第四绝缘层142，第三绝缘层141设置在阻挡层160上。
步骤S400：在第二介质层内形成连接导线另一部分，该连接导线靠近第一介质层的一端与形成在第一介质层内的连接导线连接。
示例性地，可以在第二介质层内形成填充槽，该填充槽暴露出金属线152的部分，然后利用沉积工艺在填充槽内形成导电材质，该导电材质构成第二接触部153，第二接触部153与金属线152连接，使得第一接触部151、第二接触部153以及金属线152构成连接导线。
步骤S500：在第二介质层内形成第二晶体管，第二晶体管与连接导线背离第一介质层的一端连接，其中，第二晶体管为金属氧化物薄膜晶体管。
示例性地，如图9所示，在第一介质层120上形成第三绝缘层141。
待形成第三绝缘层141之后，可以利用沉积工艺在第三绝缘层141上形成有源层111，有源层111的材质包括铟镓锌氧化物。
需要说明的是，在第三绝缘层上形成有源层的步骤，与在第一绝缘层上形成有源层的步骤相同，本实施例在此不再多加赘述。
重复步骤c至步骤f，以在第三绝缘层141上形成第二晶体管130，其结构如图10所示。
待形成第二晶体管130之后，在第三绝缘层141上形成覆盖有源层、栅氧化层、栅极以及保护层的第四绝缘层142，第四绝缘层142和第三绝缘层141构成第二介质层140。
本公开实施例通过上述的步骤，形成层叠设置的第一晶体管和第二晶 体管，并使第一晶体管或者第二晶体管作为存储单元的存储器件，来替换相关技术中的电容器，可以降低存储单元所占的体积，提高存储单元的集成度，为存储单元向集成化方向发展提供保障。
实施例四
本公开实施例提供了一种存储器的制备方法，包括如下的步骤：
步骤S10：提供基底，基底的表面设置有外围电路。
在本步骤中，外围电路可以通过现有技术中的制备方式进行制备，本实施例在此不再多加赘述。
待形成外围电路之后，可以在基底上形成覆盖外围电路的外围介质层230。
之后，再利用沉积工艺在外围介质层230上形成外围阻挡层240。
步骤S20：在基底上依次形成多个存储单元，多个存储单元在沿平行于基底的方向排列形成水平阵列，和/或，多个存储单元在沿垂直于基底的方向堆叠形成垂直阵列。
存储单元是通过上述的实施例中存储单元的制备方法制得的，本实施例不再多加赘述。
步骤S30：形成数据线，数据线用于连接外围电路与各存储单元。
需要说明的是，数据线的形成可以分为两步制备，其中一步可以在形成第一晶体管的步骤之前完成，另一步可以在形成第二晶体管之后完成。
示例性地，待形成第一介质层120之后，可以在第一介质层120内形成相互绝缘设置的读取字线221和读取位线222，读取字线221用于连接多个存储单元100中的第一晶体管110的源极或漏极，读取位线222用于连接多个存储单元100中第一晶体管110的源极或漏极，且与读取字线221的连接端不为同一端。
待形成读取字线221和读取位线222之后，可以继续在第一介质层120内形成第一晶体管110、在第一介质层120上形成第二介质层140，以及在第二介质层140内形成第二晶体管130。
待形成第二晶体管130之后，可以在第二介质层140内形成写入字线223和写入位线224，写入字线223用于连接多个存储单元100中的第二晶体管130的栅极，写入位线224用于连接多个存储单元100中第二晶体管 130的源极或漏极，且与连接导线150的连接端不为同一端。
在此步骤中，读取字线、读取位线、写入字线以及写入位线均可以采用双大马士革工艺制备。
在本实施例中，通过将多个存储单元沿垂直方向层叠设置，与相关技术多个存储单元沿水平方向依次设置的技术方案相比，可以降低多个存储单元所占的面积，降低了存储器的尺寸，提高存储单元的集成度。
此外，本实施例中外围电路设置存储单元的下方，与相关技术中外围电路设置的存储单元阵列的外侧的技术方案相比，可以进一步地缩小存储器的尺寸，提高集成度。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。

Claims (20)

  1. 一种存储单元，包括：
    第一晶体管，位于第一介质层内；
    第二晶体管，位于第二介质层内，所述第二介质层位于所述第一介质层上方；
    连接导线，位于所述第一介质层和第二介质层中，所述连接导线的一端与所述第一晶体管连接，另一端与所述第二晶体管连接；
    其中，所述第一晶体管和所述第二晶体管为金属氧化物薄膜晶体管。
  2. 根据权利要求1所述的存储单元，其中，所述第一晶体管和所述第二晶体管包括：
    有源层，所述有源层的材质包括铟镓锌氧化物，其中，所述有源层包括沟道区以及分别位于所述沟道区两侧的源极和漏极；
    栅氧化层，所述栅氧化层设置在所述有源层上；
    栅极，所述栅极设置在所述栅氧化层上，且所述栅极在所述有源层上投影覆盖在所述沟道区上。
  3. 根据权利要求2所述的存储单元，其中，所述第一晶体管和所述第二晶体管还包括保护层，所述保护层位于所述栅极和所述栅氧化层的侧面。
  4. 根据权利要求2所述的存储单元，其中，所述连接导线的一端与所述第一晶体管的栅极连接，另一端与所述第二晶体管的源极或漏极连接。
  5. 根据权利要求4所述的存储单元，其中，所述连接导线包括垂直设置的第一接触部和第二接触部，以及水平设置的金属线；
    所述第一接触部与所述第一晶体管的栅极连接，所述第二接触部与所述第二晶体管的源极或漏极连接，所述金属线连接所述第一接触部和所述第二接触部。
  6. 根据权利要求5所述的存储单元，其中，所述第一接触部和所述金属线位于所述第一介质层中，所述第二接触部位于所述第二介质层中。
  7. 根据权利要求5或6所述的存储单元，其中，所述第一介质层与所述第二介质层之间设置有阻挡层，所述阻挡层位于所述金属线上方，所述第二接触部贯穿所述阻挡层后与所述金属线连接。
  8. 一种存储器，包括：
    基底，所述基底表面设置有外围电路；
    多个如权利要求1-7任一项所述的存储单元，位于所述外围电路的上方；
    数据线，用于连接所述外围电路与各所述存储单元。
  9. 根据权利要求8所述的存储器，其中，多个所述存储单元在沿平行于所述基底的方向排列形成水平阵列；
    和/或，多个所述存储单元在沿垂直于所述基底的方向堆叠形成垂直阵列。
  10. 根据权利要求8所述的存储器，其中，所述数据线包括写入字线、写入位线、读取字线和读取位线；
    其中，所述写入字线在第一方向上延伸并连接多个所述存储单元中的第二晶体管的栅极，所述写入位线在第二方向上延伸并连接多个所述存储单元中第二晶体管的源极或漏极，且与所述连接导线连接端不为同一端，所述读取字线在第三方向上延伸并连接多个所述存储单元中的第一晶体管的源极或漏极，所述读取位线在第四方向上延伸并连接多个所述存储单元中第一晶体管的源极或漏极，且与所述读取字线的连接端不为同一端。
  11. 根据权利要求10所述的存储器，其中，所述第一方向和所述第二方向在平行于或垂直于所述基底的平面上的投影具有第一夹角，所述第三方向和所述第四方向在平行于或垂直于所述基底的平面上的投影具有第二夹角；其中，所述第一夹角和所述第二夹角均不为零。
  12. 根据权利要求8所述的存储器，其中，所述基底上设置有外围介质层，所述外围介质层覆盖所述外围电路；
    所述外围介质层与所述存储单元的第一介质层之间还具有外围阻挡层。
  13. 根据权利要求12任一项所述的存储器，其中，所述数据线穿过所述外围阻挡层和所述外围介质层，与所述外围电路连接。
  14. 一种存储单元的制备方法，包括如下步骤：
    在第一介质层内形成第一晶体管，所述第一晶体管为金属氧化物薄膜晶体管；
    在所述第一介质层内形成连接导线的一部分，该连接导线的一端与所述第一晶体管连接；
    在所述第一介质层上形成第二介质层；
    在所述第二介质层内形成连接导线另一部分，该连接导线靠近所述第一介质层的一端与形成在所述第一介质层内的连接导线连接；
    在所述第二介质层内形成第二晶体管，所述第二晶体管与所述连接导线背离所述第一介质层的一端连接，所述第二晶体管为金属氧化物薄膜晶体管。
  15. 根据权利要求14所述的存储单元的制备方法，其中，在所述第一介质层内形成第一晶体管的步骤中，包括：
    步骤a：提供第一绝缘层；
    步骤b：在所述第一绝缘层上形成有源层，所述有源层的材质包括铟镓锌氧化物；
    步骤c：在所述有源层内形成沟道区，以及分别位于所述沟道区两侧的源极和漏极；
    步骤d：在所述有源层上形成栅氧化层，所述栅氧化层的长度小于所述有源层的长度；
    步骤e：在所述栅氧化层上形成栅极，所述栅极在所述有源层上的投影覆盖所述沟道区上；
    步骤f：在所述有源层上形成保护层，所述保护层包裹在所述栅极和所述栅氧化层的侧面；
    步骤g：在所述第一绝缘层上形成覆盖所述有源层、所述栅氧化层、所述栅极以及所述保护层的第二绝缘层，所述第二绝缘层和所述第一绝缘层构成所述第一介质层。
  16. 根据权利要求15所述的存储单元的制备方法，其中，在所述第一介质层内形成连接导线的一部分，该连接导线的一端与所述第一晶体管连接的步骤中，包括：
    在所述第二绝缘层内形成第一接触部以及与第一接触部连接的金属线，所述第一接触部沿垂直方向延伸，并与所述第一晶体管的栅极连接，所述金属线沿水平方向延伸。
  17. 根据权利要求16所述的存储单元的制备方法，其中，在所述第二介质层内形成第二晶体管的步骤中，包括：
    在所述第一介质层上形成第三绝缘层；
    在所述第三绝缘层上形成有源层，所述有源层的材质包括铟镓锌氧化 物；
    重复步骤c至步骤f，以在第三绝缘层上形成第二晶体管；
    在所述第三绝缘层上形成覆盖所述有源层、所述栅氧化层、所述栅极以及所述保护层的第四绝缘层，所述第四绝缘层和所述第三绝缘层构成所述第二介质层。
  18. 根据权利要求15-17任一项所述的存储单元的制备方法，其中，在所述第二绝缘层内形成第一接触部的步骤之后，在所述第二介质层内形成第二接触部的步骤之前，所述制备方法还包括：
    在所述第二绝缘层上形成阻挡层。
  19. 一种存储器的制备方法，包括如下的步骤：
    提供基底，所述基底的表面设置有外围电路；
    在所述基底上依次形成多个存储单元，多个所述存储单元在沿平行于所述基底的方向排列形成水平阵列，和/或，多个所述存储单元在沿垂直于所述基底的方向堆叠形成垂直阵列；其中，所述存储单元通过如权利要求14-18任一项所述存储单元的制备方法制得；
    形成数据线，所述数据线用于连接所述外围电路与各所述存储单元。
  20. 根据权利要求19所述的存储器的制备方法，其中，形成数据线的步骤中包括：
    在第一介质层内形成相互绝缘设置的读取字线和读取位线，所述读取字线用于连接多个所述存储单元中的第一晶体管的源极或漏极，所述读取位线用于连接多个所述存储单元中第一晶体管的源极或漏极，且与所述读取字线的连接端不为同一端；
    在所述第二介质层内形成写入字线和写入位线，所述写入字线用于连接多个所述存储单元中的第二晶体管的栅极，所述写入位线用于连接多个所述存储单元中第二晶体管的源极或漏极，且与所述连接导线连接端不为同一端。
PCT/CN2022/076315 2021-07-02 2022-02-15 存储单元及其制备方法、存储器及其制备方法 WO2023273361A1 (zh)

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