WO2023273140A1 - 一种信号传输装置、方法、计算机设备及存储介质 - Google Patents

一种信号传输装置、方法、计算机设备及存储介质 Download PDF

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Publication number
WO2023273140A1
WO2023273140A1 PCT/CN2021/134325 CN2021134325W WO2023273140A1 WO 2023273140 A1 WO2023273140 A1 WO 2023273140A1 CN 2021134325 W CN2021134325 W CN 2021134325W WO 2023273140 A1 WO2023273140 A1 WO 2023273140A1
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signal
data
port
interface connector
target
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PCT/CN2021/134325
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English (en)
French (fr)
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黄炎坡
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深圳市商汤科技有限公司
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Publication of WO2023273140A1 publication Critical patent/WO2023273140A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Definitions

  • the present disclosure relates to the field of computer technology, and in particular, to a signal transmission device, method, computer equipment, and storage medium.
  • edge servers have a very large number of applications.
  • Edge servers are sensitive to conditions such as deployment cost, power consumption, and area, and the hard disk connected to the PCIE (Peripheral Component Interconnect Express) interface is usually small in size, so when setting the hard disk interface of the edge server, it is usually Select the PCIE interface.
  • PCIE Peripheral Component Interconnect Express
  • hard disks that can be connected to the PCIE interface include SATA hard disks that perform data exchange with SATA (Serial Advanced Technology Attachment) signals, and NVME (Non Volatile Memory Express) hard disks that perform data exchange with PCIE signals. .
  • SATA Serial Advanced Technology Attachment
  • NVME Non Volatile Memory Express
  • the CPU only supports SATA signals
  • the PCIE interface when the PCIE interface is connected to an NVME hard disk, it is also necessary to convert the PCIE signal in the NVME hard disk into a SATA signal before exchanging data with the CPU.
  • the external conversion tool used may not match the area-sensitive edge server.
  • the hard disk for an edge server only the hard disk corresponding to the signal type supported by the CPU of the edge server can be selected, and the selection type is limited.
  • Embodiments of the present disclosure at least provide a signal transmission device, method, computer equipment, and storage medium.
  • an embodiment of the present disclosure provides a signal transmission device, including two first data selectors, a signal conversion controller, an interface connector, and a conversion auxiliary module;
  • Any first data selector is connected with the central processing unit or the interface connector; the two first data selectors are respectively directly connected through their respective ports and connected through the signal conversion controller; the conversion auxiliary module connected with the two first data selectors and the interface connector, wherein:
  • the conversion auxiliary module is used to provide port gating signals for the two first data selectors in response to the detection result of the interface connector;
  • the two first data selectors are configured to connect to the selected target port in response to the port gating signal sent by the conversion auxiliary module to form a data transmission channel;
  • the signal conversion controller is configured to complete the conversion between the first data signal and the second data signal in response to receiving any signal sent by the first data selector.
  • a signal transmission device is constructed by using two first data selectors, signal conversion controllers, interface connectors, and conversion auxiliary modules, which can realize the judgment of the signal type of the solid-state hard disk according to the detection results of the interface connectors, and A corresponding port strobe signal is provided for the first data selector, and a data transmission channel matching the signal type of the solid state disk is constructed. Therefore, signal self-adaptation is achieved according to the signal type of the solid-state hard disk connected to the interface connector, so that when selecting a hard disk for an edge server, the optional type is no longer single.
  • the conversion auxiliary module when the conversion auxiliary module provides port gating signals for the two first data selectors in response to the detection result of the interface connector, it is configured to:
  • the first data signal is a SATA signal
  • the second data signal is a PCIE signal
  • the first data selector includes a first port, a second port, a third port, and a gate port;
  • the first data selector is connected to the CPU or the interface connector through the first port, connected to other first data selectors through the second port, and connected to the signal conversion through the third port
  • the controller is connected; the first data selector is connected to the conversion auxiliary module through a gate port;
  • the gate port is used to receive the port gate signal sent by the conversion auxiliary module, so that the first data selector determines the target port from the second port and the third port, and selects the The target port communicates with the first port.
  • the port gating signal includes an identifier of the target port to be connected
  • the conversion auxiliary module when providing a port gating signal for the data selector according to the target state value, is used for:
  • the port strobe signal corresponding to the target state value is searched for.
  • the port strobe signal containing the identification of the target port is sent, so that the transmission of signals on different data paths can be realized by switching between ports , so that the signal transmission device can adapt to hard disks of different signal types.
  • the two first data selectors form the data transmission channel through a connection between the second ports.
  • the PCIE signal does not need to pass through an additional device during transmission, thereby reducing the delay during data transmission.
  • the conversion auxiliary module includes a complex programmable logic device, a power supply module, and a clock buffer;
  • the complex programmable logic device is connected to the two first data selectors, an interface connector, a clock buffer, a signal conversion controller, and a power supply module;
  • the complex programmable logic device is configured to send a power enable signal to the power supply module when the target state value is a preset state value, so as to instruct the power supply module to supply power to the signal conversion controller ,as well as,
  • a port gate signal is sent to the two first data selectors.
  • the signal converter is powered by the conversion auxiliary module, and the signal conversion controller is provided with a reset signal and a clock signal, so that the signal conversion controller can have a working environment, thereby realizing signal conversion.
  • the data path formed by the two first data selectors is used as the first data path, and the signal transmission device further includes a second data path; the second data path includes two Two data selectors;
  • any second data selector is connected with the CPU or the interface connector; the second data selector connected with the CPU is respectively selected through different ports and the second data selector connected with the interface connector and connected to the signal conversion controller in the first data path; the conversion auxiliary module is connected to the two second data selectors;
  • the signal conversion is performed by the signal conversion controller, and the converted SATA signal is sent to the first PCIE signal.
  • a first data selector connected to the interface connector in a data path, and the SATA signal is sent to the interface connector through the first data selector.
  • the data transmission speed can be increased through more data paths.
  • a third data path is also included, and in the third data path, the CPU is directly connected to the interface connector; when the CPU sends a PCIE signal, it directly passes through the third data path Three data lanes send the second PCIE signal to the interface connector.
  • the data transmission speed can be increased through more data paths.
  • the embodiment of the present disclosure also provides a signal transmission method applied to the conversion auxiliary module, including:
  • the target state value represents the signal type of the solid-state hard disk connected with the interface connector
  • the port gating signal is used to control the first data selector to connect the target port from a plurality of ports to be selected; the target ports of the two first data selectors are connected to each other connected to form a data transmission channel for realizing data transmission between the central processing unit CPU and the interface connector;
  • control signal conversion controller When the signal type of the solid-state hard disk is the first data signal, the control signal conversion controller performs the conversion between the first data signal and the second data signal on the data transmitted between the CPU and the interface connector. convert.
  • the port gating signal includes an identifier of the target port to be connected
  • the determining the port gate signal corresponding to the target state value includes:
  • the port strobe signal corresponding to the target state value is searched for.
  • the conversion auxiliary module includes a complex programmable logic device, a power supply module, and a clock buffer;
  • the complex programmable logic device is connected to the two first data selectors, an interface connector, a clock buffer, a signal conversion controller, and a power supply module;
  • the complex programmable logic device is configured to send a power enable signal to the power supply module when the target state value is a preset state value, so as to instruct the power supply module to supply power to the signal conversion controller ,as well as,
  • a port gate signal is sent to the two first data selectors.
  • an embodiment of the present disclosure further provides a signal transmission device, which is applied to the conversion auxiliary module, including:
  • a detection unit configured to detect a target state value of a target pin of the interface connector; wherein the target state value represents a signal type of a solid-state hard disk connected to the interface connector;
  • a determining unit configured to determine a port gating signal corresponding to the target state value; the port gating signal is used to control the data selector to connect to the target port from a plurality of ports to be selected; the target ports of the multiple data selectors interconnected to form a data transmission channel for realizing data transmission between the CPU and the interface connector;
  • control signal conversion controller carries out the data between CPU and described interface connector to carry out between PCIE signal and SATA signal Format conversion.
  • an embodiment of the present disclosure further provides a board, including: the signal transmission device provided in the first aspect and any implementation manner thereof.
  • the embodiment of the present disclosure further provides a computer device, including: a processor, a memory, and a bus, the memory stores machine-readable instructions executable by the processor, and when the computer device is running, the processing The processor communicates with the memory through a bus, and when the machine-readable instructions are executed by the processor, the steps in the above-mentioned second aspect are performed.
  • a computer device including: a processor, a memory, and a bus
  • the memory stores machine-readable instructions executable by the processor, and when the computer device is running, the processing
  • the processor communicates with the memory through a bus, and when the machine-readable instructions are executed by the processor, the steps in the above-mentioned second aspect are performed.
  • the embodiments of the present disclosure further provide a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is run by a processor, the steps in the above-mentioned second aspect are executed.
  • FIG. 1 shows a schematic diagram of an adapter card for converting SATA signals into PCIE signals provided by an embodiment of the present disclosure
  • FIG. 2 shows a schematic structural diagram of a signal transmission device provided by an embodiment of the present disclosure
  • FIG. 3A shows a system block diagram of a signal transmission device provided by an embodiment of the present disclosure
  • FIG. 3B shows an equivalent block diagram of a signal transmission device provided by an embodiment of the present disclosure
  • FIG. 3C shows an equivalent block diagram of another signal transmission device provided by an embodiment of the present disclosure
  • FIG. 3D shows a schematic diagram of a signal transmission device provided by an embodiment of the present disclosure when data is uplink
  • FIG. 3E shows a system block diagram of another signal transmission device provided by an embodiment of the present disclosure.
  • FIG. 4 shows a flowchart of a signal transmission method provided by an embodiment of the present disclosure
  • FIG. 5 shows a schematic structural diagram of a signal transmission device applied to a conversion auxiliary module provided by an embodiment of the present disclosure
  • FIG. 6 shows a schematic structural diagram of a computer device provided by an embodiment of the present disclosure.
  • the hard disks that can be connected to the PCIE interface include SATA hard disks that use SATA signals for data exchange, and NVME hard disks that use PCIE signals for data exchange. And if the CPU of the edge server does not support the SATA signal, even if the SATA hard disk is connected through the PCIE interface, data exchange cannot be performed.
  • an external conversion tool such as an adapter card to convert the SATA signal in the SATA hard disk into a PCIE signal before exchanging data with the CPU; on the other hand, if the CPU only supports SATA signals, when the PCIE interface is connected In the case of NVME hard disk, it is also necessary to convert the PCIE signal in the NVME hard disk into a SATA signal before exchanging data with the CPU.
  • the external conversion tool used may not match the area-sensitive edge server. As a result, when selecting a hard disk for an edge server, only the hard disk corresponding to the signal type supported by the CPU of the edge server can be selected, and the selection type is limited.
  • FIG. 1 a schematic diagram of using an adapter card to convert SATA signals in a SATA hard disk into PCIE signals may be shown in FIG. 1 .
  • the CPU may represent a motherboard carrying the CPU, and the M.2 connector is connected to a SATA hard disk.
  • the PCIE signal output by the CPU passes through the PCIE-to-SATA controller mounted on the adapter card to convert the PCIE signal into a SATA signal, so that the CPU can exchange data with the SATA hard disk.
  • the component below the PCIE-to-SATA controller is a conversion auxiliary module on the riser card, and the conversion auxiliary module provides work support for the PCIE-to-SATA controller.
  • an adapter card In the case of using an adapter card, on the one hand, it needs to occupy valuable internal space in the edge server, and on the other hand, it also limits the type of solid-state hard disk connected, and can only connect SATA hard disks whose signal type is SATA signal.
  • a signal transmission device is constructed by using two first data selectors, a signal conversion controller, an interface connector, and a conversion auxiliary module, which can realize the signal type selection of the solid state disk according to the target state value of the target pin of the interface connector judge, and provide a corresponding port strobe signal for the first data selector to construct a data transmission channel matching the signal type of the solid state disk. Therefore, signal self-adaptation is achieved according to the signal type of the solid-state hard disk connected to the interface connector, so that when selecting a hard disk for an edge server, the optional type is no longer single.
  • the signal transmission device can be deployed on computer equipment with computing capabilities.
  • the signal transmission device can be used in an area-sensitive environment such as an edge server, and is connected to the CPU and the solid-state hard disk respectively during deployment to ensure normal data transmission between the CPU and the solid-state hard disk.
  • the signal transmission device may be integrated on the main board of the edge server, or the signal transmission device may be packaged into a board and installed on the main board of the edge server.
  • the signal transmission device is composed of a first data selector, a signal conversion controller, an interface connector, and a conversion auxiliary module.
  • FIG. 2 it is a schematic structural diagram of a signal transmission device provided by an embodiment of the present disclosure, including a conversion auxiliary module 11, a first data selector 12, a signal conversion controller 13, and an interface connector 14; "the conversion auxiliary module 11" is hereinafter referred to as “conversion auxiliary module”; “first data selector 12” is hereinafter referred to as “first data selector”; “signal conversion controller 13” is hereinafter referred to as “signal conversion controller”; “interface connection Connector 14" is hereinafter referred to as "interface connector”.
  • the signal transmission device is connected to the solid-state hard disk through the interface connector, and the data transmission between the CPU and the solid-state hard disk can be realized through the interface connector; the specific connection relationship of each component in the signal transmission device is described as follows:
  • Any first data selector is connected with the central processing unit CPU or the interface connector; the two first data selectors are respectively directly connected through respective ports and connected through the signal conversion controller; the conversion auxiliary A module is connected to the two first data selectors and the interface connector, wherein:
  • a switching auxiliary module configured to provide a port gating signal for the two first data selectors in response to the detection result of the interface connector
  • the detection result of the interface connector may refer to the detection result of the level signal of the target pin of the interface connector.
  • the different level information of the target pins is used to indicate different types of solid state disks connected to the interface connector.
  • the conversion auxiliary module when it provides port strobe signals for the two first data selectors in response to the detection result of the interface connector, it can detect the target pin of the interface connector A target state value of the target state value, and provide a port gating signal for the first data selector according to the target state value; wherein, the target state value represents the signal type of the solid state disk connected to the interface connector.
  • the target state value is 1, it means that the solid-state hard disk connected to the interface connector is a PCIE hard disk, and if the value of the target state is 0, it means that the solid-state hard disk connected to the interface connector is SATA hard disk.
  • the first data selector is used to respond to the port gating signal sent by the conversion auxiliary module, connect the gating target port to form a data transmission channel, and is used to realize the data transmission between the CPU and the interface connector ;
  • the target ports of the two first data selectors are connected through a signal conversion controller;
  • the signal conversion controller is configured to complete the conversion between the first data signal and the second data signal in response to receiving any signal sent by the first data selector.
  • the first data signal and the second data signal are two different types of data signals.
  • the first data signal may be a SATA signal
  • the second data signal may be a PCIE signal
  • the first data information may be a PCIE signal
  • the second data signal may be a SATA signal.
  • the following will introduce the signal transmission device by taking the first data signal as a SATA signal and the second data signal as a PCIE signal as an example.
  • the first data selector includes a first port, a second port, a third port, and a gate port;
  • the first data selector is connected to the CPU or the interface connector through the first port (the first port is shown as port Y in Figure 3A), and is connected to other first data selectors through the second port.
  • the selector is connected (the second port is as port A in Figure 3A), and is connected with the signal conversion controller through the third port (the third port is as port B in Figure 3A);
  • a data selector is connected with the conversion auxiliary module through a gate port (the gate port is such as the gate port in Figure 3A);
  • the gate port is used to receive the port gate signal sent by the conversion auxiliary module, so that the first data selector determines the target port from the second port and the third port, and selects the The target port communicates with the first port.
  • the two first data selectors are directly connected through their respective ports, which can be understood as the direct connection between the two first data selectors through the second ports of the two first data selectors.
  • the port identifiers of the second ports of the two first data selectors are the same, for example, both may be port A in FIG. 3A , that is, the two first data selectors are connected through port A.
  • the conversion auxiliary module includes a complex programmable logic device, a power supply module, and a clock buffer;
  • the complex programmable logic device is connected to the first data selector, interface connector, clock buffer, signal conversion controller, and power supply module;
  • the complex programmable logic device is configured to send a power enable signal to the power supply module when the target state value is a preset state value, so as to instruct the power supply module to supply power to the signal conversion controller and, sending a clock enable signal to the clock buffer to instruct the clock buffer to provide a clock signal for the signal conversion controller; and sending a port gating signal to the two first data selectors .
  • the preset state value may be understood as a state value used to represent different types of the solid state disk connected to the CPU and the interface connector.
  • the preset state value may be a signal value indicating that the solid-state hard disk connected to the interface connector is a SATA hard disk; if the signal transmitted by the CPU If it is a SATA signal, the preset state value may be a signal value indicating that the solid-state hard disk connected to the interface connector is a PCIE hard disk.
  • the data path formed by the two first data selectors is used as the first data path (the first data path may, for example, be shown by a thick solid line in FIG. 3E ).
  • the signal transmission device also includes a second data path (the second data path may be shown by a thick dashed line in FIG. 3E, for example); the second data path includes two second data selectors;
  • any second data selector is connected with the CPU or the interface connector (as shown in Figure 3E, the second data selector 1 is connected with the CPU, and the second data selector 2 is connected with the interface connector);
  • the second data selector connected to the CPU and the second data selector connected to the interface connector are respectively connected through the same port identification, for example, between the second data selector 1 and the second data selector 2 through Two ports with the same port identification (port A) are connected; and the second data selector (ie, the second data selector 1) connected to the CPU is connected to the signal conversion controller in the first data path;
  • the conversion auxiliary module is connected with the two second data selectors;
  • the second data selector connected to the CPU may send the first PCIE signal to the signal conversion controller.
  • the signal conversion is performed by the signal conversion controller, and the signal conversion controller can send the converted SATA signal to the first data selector connected to the interface connector in the first data path, and The SATA signal is sent to the interface connector through the first data selector.
  • a third data path is further included.
  • the CPU is directly connected to the interface connector; when the CPU sends the PCIE signal, the second PCIE signal is directly sent to the interface connector through the third data path .
  • FIG. 3A it is a system block diagram of a signal transmission device provided by an embodiment of the present disclosure, wherein:
  • the interface connector is an M.2 interface connector, which is used to connect the solid-state hard disk with a new generation interface M.2 interface;
  • the conversion auxiliary module includes complex programmable logic device (Complex Programmable Logic Device, CPLD), power supply module, clock buffer (Clock Buffer);
  • the first data selector is a Multiplexer that includes two optional ports (for example, port A and port B), for receiving the port gating signal sent by the CPLD, and according to the port gating signal (ie gating port input signal), select the target port from port A (i.e. the second port) and port B (i.e. the third port) to communicate with port Y (i.e. the first port) to form a data path;
  • the signal conversion controller is a PCIE to SATA controller, which is used to complete the data conversion between the first PCIE signal and the SATA signal after receiving any signal sent by the first data selector, including converting the first PCIE signal Converting to a SATA signal, and converting the SATA signal into a first PCIE signal;
  • the CPU sends and receives PCIE signals.
  • the PCIE lane0 connected by the solid line represents a data lane lane0 in the physical lane of the PCIE bus.
  • the above-mentioned components are included on the data transmission channel where lane0 is located, so that SATA signals or PCIE signals can be transmitted on the data transmission channel of lane0.
  • PCIE lane1, PCIE lane2, and PCIE lane3 connected by dotted lines indicate that the CPU supports data transmission through multiple PCIE lanes.
  • PCIE lane1, PCIE lane2, and PCIE lane3 can be connected to M.2 connectors, PCIE lane1, PCIE lane2, and PCIE lane3 cannot transmit SATA signals. Therefore, the corresponding pins of the M.2 connectors are in a floating state, so they are represented by dotted lines.
  • the state values of the PEDET pins of the M.2 connector are different when connecting different types of solid-state drives, so the PEDET pin can be connected to Pin is used as the target pin, and the level truth table of the PEDET pin can be as shown in Table 1:
  • the conversion control module can determine the type of the solid state drive connected to the M.2 connector according to the corresponding relationship between the signal level of the PEDET pin and the type of solid state drive, that is, determine The signal type of the solid-state drive connected to the M.2 connector, and then output the corresponding control signal to control the data transmission on the data transmission channel where lane0 is located.
  • control signal includes a port gate signal.
  • the port gating signal includes an identifier of the target port to be connected.
  • the conversion auxiliary module when providing a port gate signal to the first data selector according to the target state value, can search for the target state value based on the preset correspondence between the state value and the gate signal. Corresponding port strobe signal.
  • the control signal output by the CPLD can be as shown in Table 2 below:
  • the signal of the PEDET pin when the signal of the PEDET pin is high, it indicates that the solid-state hard disk connected to the M.2 connector is an NVME hard disk supporting PCIE signals, the port strobe signal is high, and the strobe signal indicates the target port A
  • the high-speed signal in FIG. 3A is a PCIE signal. Since the signal type sent and received by the CPU is also a PCIE signal, there is no need for signal conversion. Therefore, the signal conversion controller does not need to work, that is, the power enable signal is disabled, the clock enable signal is disabled, and no reset signal is provided.
  • FIG. 3B An equivalent block diagram of the signal transmission device at this time may be shown in FIG. 3B . In FIG.
  • the PCIE-to-SATA controller does not exist because there is no working environment.
  • the data transmission channel where lane0 is located is connected with ports A of two first data selectors, and carries out data transmission with PCIE signals, that is, when the signal type of the solid-state hard disk is the PCIE signal, the two a direct connection between target ports of the first data selector;
  • the signal of the PEDET pin when the signal of the PEDET pin is low, it indicates that the solid-state hard disk connected to the M.2 connector is a SATA hard disk that supports SATA signals, the port strobe signal is low, and the strobe signal indicates the target port B The signal that communicates with port Y.
  • the high-speed signal in Figure 3A is a SATA signal. Since the signal type sent and received by the CPU is a PCIE signal, there is a need for signal conversion. It is necessary to provide a working environment for the clock buffer, power supply module, and PCIE to SATA controller. That is, the power enable signal is enabled, the clock enable signal is enabled, and a reset signal is provided.
  • the CPLD in the conversion auxiliary module supplies power for the PCIE to SATA controller, and for the PCIE to SATA control
  • the device provides reset signal and clock signal.
  • the PCIE to SATA controller can work normally, converting the received signal from the PCIE signal to the SATA signal.
  • the equivalent block diagram of the signal transmission device at this time can be as shown in Figure 3C.
  • the PCIE to SATA controller has a working environment, and the data transmission channel where lane0 is located is: a port B of the first data selector - PCIE to SATA controller - another connected first data selector port B is connected in sequence, so that the data exchange between the CPU and the SATA hard disk can be realized through the conversion function of the PCIE to SATA controller.
  • FIG. 3D The system block diagram when data is uplinked can be shown in FIG. 3D .
  • the difference between FIG. 3D and FIG. 3A is that the direction of the arrow is different, and other content included in FIG. 3D will not be repeated here.
  • the transmission logic TX and the reception logic RX on the data path lane0, that is, the data is bidirectional during transmission (data exchange); correspondingly, the PCIE to SATA controller can After receiving the first PCIE signal sent by the CPU side, convert the first PCIE signal into a SATA signal, and after receiving the SATA signal sent by the M.2 connector side, convert the SATA signal It is the first PCIE signal.
  • the CPU when the CPU performs data exchange with the NVME hard disk connected to the M.2 connector, in addition to performing data transmission on lane0 with the first PCIE signal, it can also perform data transmission on lane1 (second data path), Data transmission is performed on lane2 (third data path) and lane3 (fourth data path) with the second PCIE signal.
  • the first PCIE signal and the second PCIE signal are PCIE signals under the same standard (such as the PCIE signal of the PCIE3.0 standard), and the difference is only whether the data selector (comprising the first data) has passed through the data selector when the signal is transmitted. selector and second data selector). For example, in FIG.
  • the PCIE signal transmitted by the first data selector is the first PCIE signal (such as the PCIE signal on lane0 in FIG. 3A ), and the PCIE signal not transmitted by the first data selector
  • the signal is the second PCIE signal (for example, the PCIE signals on lane1, lane2, and lane3 in FIG. 3A).
  • the CPU is connected to ports corresponding to lane1, lane2, and lane3 in the physical path.
  • Step 1 When the CPLD in the conversion auxiliary module detects that the signal of the PEDET pin is low, it provides a port strobe signal for all the first data selectors in PCIE lane0, indicates that port B is the target port, and controls PCIE to SATA
  • the device provides reset signal, PCIE 100M clock signal and power supply;
  • Step 2 the CPU sends the PCIE signal from the corresponding PCIE interface, sends it to the port Y of the first data selector connected to the CPU, and sends the PCIE signal to the PCIE switch through the target port B of the first data selector SATA controller;
  • Step 3 PCIE turns SATA controller after receiving PCIE signal, described PCIE signal is converted into SATA signal, and described SATA signal is sent to the port B of the first data selector that is connected with M.2 connector;
  • Step 4 After receiving the SATA signal, port B of the first data selector connected to the M.2 connector sends a SATA signal to the M.2 connector through port Y, so that the SATA hard disk connected to the M.2 connector The SATA signal can be received, and corresponding operations are performed according to the SATA signal.
  • the interface connector is an M.2 interface connector, used for M.2 interface solid-state hard drives;
  • the conversion auxiliary module includes a complex programmable logic device (Complex Programmable logic device, CPLD), a power supply module, and a clock buffer;
  • the first data selection Both the device and the second data selector are Multiplexers that include two optional ports (for example, port A and port B), and are used to receive the port gating signal sent by the CPLD, and according to the port gating signal, from Select the target port in port A and port B to communicate with port Y;
  • the signal conversion controller is a PCIE to SATA controller, which is used to complete the conversion between the first PCIE signal and the SATA signal after receiving the signal sent by any data selector.
  • PCIE lane0 and lane1 connected by solid lines represent two data lanes lane0 and lane1 in the physical path of PCIE bus, and the above-mentioned components are included on the data transmission channel where lane0 is located,
  • the SATA signal or PCIE signal can be transmitted on the data transmission channel of lane0; and the data transmission channel where lane1 is located contains two second data selectors, which can enable the transmission of PCIE on the data transmission channel of lane1 Signal;
  • PCIE lane2 and PCIE lane3 connected by dotted lines indicate that the CPU supports data transmission through multiple PCIE lanes.
  • PCIE lane2 and PCIE lane3 can be connected to the M.2 connector, PCIE lane2 and PCIE lane3 cannot transmit SATA signals, so The pins of the corresponding M.2 connectors are in a floating state, so they are indicated by dotted lines.
  • the data path where lane0 is located is the first data path
  • the data selectors in the first data path are the first data selectors, which are respectively the first data selector 1 and the first data selector 2;
  • the target ports (port B) of the two first data selectors are connected by a PCIE to SATA controller.
  • the data path where lane1 is located is the second data path, and the data selectors in the second data path are the second data selectors, which are respectively the second data selector 1 and the second data selector 2;
  • the second Data selector 1 is connected with described PCIE to SATA controller, under the situation that the signal type of described solid-state disk is described SATA signal, described second data selector 1 receives the first PCIE that described CPU sends After the signal is converted, the signal is converted through the PCIE to SATA controller, and the converted SATA signal is sent to the M.2 connector through the first data selector 2 .
  • control signal output by the CPLD may also be as shown in Table 2 above.
  • the first data path in FIG. 3E is exactly the same as the data transmission channel where lane0 in the above-mentioned FIG. 3A is performing data exchange. No more details here, so the following will describe in detail the specific content executed by the second data path during data exchange:
  • the signal of the PEDET pin When the signal of the PEDET pin is high, it indicates that the solid-state hard disk connected to the M.2 connector is an NVME hard disk supporting PCIE signals, the port strobe signal is high, and the strobe signal indicates that the target port A and Signal for port Y to connect.
  • the high-speed signal in Figure 3E is a PCIE signal, and the second data selector on the second data path is connected through port A, and the connection sequence of the entire second data path is: CPU-port of the second data selector 1 A-port of the second data selector 2 A-M.2 connector;
  • the signal of the PEDET pin when the signal of the PEDET pin is low, it indicates that the solid-state hard disk connected to the M.2 connector is a SATA hard disk supporting SATA signals at this time, the port strobe signal is low, and the strobe signal indicates the target port The signal that B communicates with port Y.
  • the high-speed signal on the first data path is a SATA signal
  • the second data path is blocked (not connected to the second data selector 2), so the high-speed information on the second data path is not exist.
  • the second data selector 1 receives the first PCIE signal sent by the CPU, it converts the signal through the PCIE to SATA controller, and sends the SATA signal obtained after conversion to the first data selector 2.
  • the M.2 connector realizes the data exchange between the CPU and the SATA hard disk.
  • the CPU when the CPU performs data exchange with the NVME hard disk connected to the M.2 connector, in addition to performing data transmission on lane0 and lane1 with the first PCIE signal, it can also perform data transmission on lane2 and lane3 Data transmission is performed with the second PCIE signal.
  • Relevant settings may be made according to actual needs, which is not limited in this embodiment of the present disclosure.
  • the data transmission channels where lane2 and lane3 are located can be replaced with the same structure as the second data channel where lane1 is located, that is, between lane2 and Two data selectors are also deployed on lane3, so that the PCIE signal can be transmitted on the corresponding data path; and when the M.2 connector is connected to the SATA hard disk, the corresponding pins on the M.2 connector Physical disconnection avoids the loss of relevant pins during signal transmission, and can also improve the service life of the M.2 connector and the availability of the entire signal transmission device in an edge computing environment.
  • the deployment cost during deployment will also be lower; in addition, during deployment, in order to save the area during deployment, also Various components in the signal transmission device can be integrated on the main board to realize the functions of signal transmission and conversion in a board-mounted manner. Regarding which type of signal transmission device provided by the embodiment of the present disclosure is selected for a specific deployment, it can be selected according to actual needs, which is not limited by the embodiment of the present disclosure.
  • the CPU can also only send and receive SATA signals.
  • the system block diagram in this case is similar to that in Figure 3A. Since the bandwidth of the SATA signal is small, only one data path can be used for transmission. Therefore, the three PCIE data paths indicated by the dotted lines can be directly deleted.
  • control signal output by the CPLD can be shown in Table 3 below:
  • Step 1 the CPLD in the conversion auxiliary module detects that the signal of the PEDET pin is high, provides a port strobe signal for all first data selectors in the SATA transmission channel, indicates that port B is the target port, and converts PCIE to SATA
  • the controller provides reset signal, PCIE 100M clock signal and power supply;
  • Step 2 the CPU sends the SATA signal from the corresponding SATA interface, sends it to the port Y of the first data selector connected to the CPU, and sends the SATA signal to the PCIE converter through the target port B of the first data selector.
  • SATA controller ;
  • Step 3 PCIE turns SATA controller after receiving SATA signal, described SATA signal is converted into PCIE signal, and described PCIE signal is sent to the port B of the first data selector that is connected with M.2 connector;
  • Step 4 After receiving the PCIE signal, port B of the first data selector connected to the M.2 connector sends a PCIE signal to the M.2 connector through port Y, so that the NVME hard disk connected to the M.2 connector A PCIE signal can be received, and a corresponding operation is performed according to the PCIE signal.
  • the execution body of the signal transmission method is a conversion auxiliary module, and the method includes steps S401-S403.
  • S401 Detect the target state value of the target pin of the interface connector; wherein, the target state value represents the signal type of the solid state disk connected to the interface connector;
  • S402 Determine the port gating signal corresponding to the target state value; the port gating signal is used to control the first data selector to connect the target port from a plurality of ports to be selected; the targets of the two first data selectors The ports are connected to each other to form a data transmission channel for realizing data transmission between the central processing unit CPU and the interface connector;
  • control signal conversion controller converts the data transmitted between the CPU and the interface connector between the first data signal and the second data signal. Format conversion between.
  • the port gating signal includes an identifier of the target port to be connected
  • the determining the port gate signal corresponding to the target state value includes:
  • the port strobe signal corresponding to the target state value is searched for.
  • the conversion auxiliary module includes a complex programmable logic device, a power supply module, and a clock buffer;
  • the complex programmable logic device is connected to the first data selector, interface connector, clock buffer, signal conversion controller, and power supply module;
  • the complex programmable logic device is configured to send a power enable signal to the power supply module when the target state value is a preset state value, so as to instruct the power supply module to supply power to the signal conversion controller ;as well as,
  • a port gate signal is sent to the two first data selectors.
  • a signal transmission device is constructed by using two first data selectors, a signal conversion controller, an interface connector, and a conversion auxiliary module.
  • the target state value realizes the judgment of the signal type of the solid-state hard disk, and provides a corresponding port strobe signal for the first data selector to construct a data transmission channel matching the signal type of the solid-state hard disk. Therefore, signal self-adaptation is achieved according to the signal type of the solid-state hard disk connected to the interface connector, so that when selecting a hard disk for an edge server, the optional type is no longer single.
  • integrating the signal conversion controller on the main board of the server can reduce the area occupied by the signal conversion controller and adapt to the area-sensitive feature of the edge server.
  • the writing order of each step does not mean a strict execution order and constitutes any limitation on the implementation process.
  • the specific execution order of each step should be based on its function and possible
  • the inner logic is OK.
  • embodiments of the present disclosure also provide a signal transmission device corresponding to the signal transmission method. Since the problem-solving principle of the device in the embodiment of the present disclosure is similar to the above-mentioned signal transmission method in the embodiment of the present disclosure, the implementation of the device can refer to the implementation of the method, and repeated descriptions will not be repeated.
  • FIG. 5 it is a schematic structural diagram of a signal transmission device provided by an embodiment of the present disclosure, which is applied to a conversion auxiliary module.
  • the device includes: a detection unit 501, a determination unit 502, and a control unit 503; wherein,
  • a detection unit 501 configured to detect a target state value of a target pin of the interface connector; wherein the target state value represents a signal type of a solid-state hard disk connected to the interface connector;
  • the determining unit 502 is configured to determine a port gating signal corresponding to the target state value; the port gating signal is used to control the data selector to connect to the target port from a plurality of ports to be selected; the target of the multiple data selectors The ports are connected to each other to form a data transmission channel for realizing data transmission between the CPU and the interface connector;
  • the control unit 503 is used to control the signal conversion controller to perform format conversion between the PCIE signal and the SATA signal to the data transmitted between the CPU and the interface connector when the signal type of the solid-state hard disk is a SATA signal .
  • the signal transmission device applied to the conversion auxiliary module provided by the embodiment of the present disclosure can realize the judgment of the signal type of the solid state disk according to the target state value of the target pin of the interface connector, and provide the corresponding port selection for the data selector. Through the signal, build a data transmission channel that matches the signal type of the solid state drive. Therefore, signal self-adaptation is achieved according to the signal type of the solid-state hard disk connected to the interface connector, so that when selecting a hard disk for an edge server, the optional type is no longer single.
  • FIG. 6 it is a schematic structural diagram of a computer device 600 provided by an embodiment of the present disclosure, including a processor 601 , a memory 602 , and a bus 603 .
  • the memory 602 is used to store execution instructions, including a memory 6021 and an external memory 6022; the memory 6021 here is also called an internal memory, and is used to temporarily store calculation data in the processor 601 and exchange data with an external memory 6022 such as a hard disk.
  • the processor 601 exchanges data with the external memory 6022 through the memory 6021.
  • the processor 601 communicates with the memory 602 through the bus 603, so that the processor 601 executes the following instructions:
  • the target state value represents the signal type of the solid-state hard disk connected to the interface connector
  • the port gating signal is used to control the first data selector to connect the target port from a plurality of ports to be selected; the target ports of the two first data selectors are connected to each other connected to form a data transmission channel for realizing data transmission between the central processing unit CPU and the interface connector;
  • control signal conversion controller When the signal type of the solid-state hard disk is the first data signal, the control signal conversion controller performs the conversion between the first data signal and the second data signal on the data transmitted between the CPU and the interface connector. convert.
  • An embodiment of the present disclosure further provides a board, including the signal transmission device provided in any one of the foregoing embodiments.
  • the signal transmission device can be implemented as a small card circuit, which can be inserted into the main board to complete the circuit conversion.
  • Embodiments of the present disclosure further provide a computer-readable storage medium, on which a computer program is stored, and when the computer program is run by a processor, the steps of the signal transmission method described in the foregoing method embodiments are executed.
  • the storage medium may be a volatile or non-volatile computer-readable storage medium.
  • the embodiment of the present disclosure also provides a computer program product, the computer program product carries a program code, and the instructions included in the program code can be used to execute the steps of the signal transmission method described in the above method embodiment, for details, please refer to the above method The embodiment will not be repeated here.
  • the above-mentioned computer program product may be specifically implemented by means of hardware, software or a combination thereof.
  • the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK) etc. Wait.
  • the disclosed devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • multiple units or components can be combined.
  • some features can be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some communication interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium executable by a processor.
  • the technical solution of the present disclosure is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in various embodiments of the present disclosure.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disc and other media that can store program codes. .

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Abstract

本公开提供了一种信号传输装置、方法、计算机设备及存储介质，该方法包括：检测接口连接器的目标管脚的目标状态值；其中，所述目标状态值表示与所述接口连接器连接的固态硬盘的信号类型；确定与所述目标状态值对应的端口选通信号；所述端口选通信号用于控制第一数据选择器从多个待选择端口中连通目标端口；两个第一数据选择器的目标端口相互连接，构成数据传输通道，用于实现中央处理器与所述接口连接器之间的数据传输；在所述固态硬盘的信号类型为第一数据信号的情况下，控制信号转换控制器对所述中央处理器与所述接口连接器之间传输的数据进行第一数据信号与第二数据信号之间的格式转换。

Description

一种信号传输装置、方法、计算机设备及存储介质
相关申请的交叉引用
本专利申请要求于2021年6月28日提交的、申请号为202110720426.4、发明名称为“一种信号传输装置、方法、计算机设备及存储介质”的中国专利申请的优先权，该申请以引用的方式并入文本中。
技术领域
本公开涉及计算机技术领域，具体而言，涉及一种信号传输装置、方法、计算机设备及存储介质。
背景技术
随着边缘计算的兴起，边缘服务器有非常大量的应用。边缘服务器对于部署成本、功耗、面积等条件较为敏感，而PCIE(高速串行计算机扩展总线标准，Peripheral Component Interconnect Express)接口连接的硬盘体积通常较小，因此在设置边缘服务器的硬盘接口时通常选择PCIE接口。
相关技术中，PCIE接口所能连接的硬盘包括以SATA(串行高级技术附件，Serial Advanced Technology Attachment)信号进行数据交换的SATA硬盘，以及以PCIE信号进行数据交换的NVME(Non Volatile Memory Express)硬盘。而若在边缘服务器的CPU不支持SATA信号的情况下，即使通过PCIE接口连接上了SATA硬盘，也无法进行数据交换。此时需要通过转接卡等外接转换工具，将SATA硬盘中的SATA信号转换为PCIE信号之后，才能与CPU进行数据交换。另一方面，若CPU只支持SATA信号的情况下，当PCIE接口连接NVME硬盘时，也需要通过将NVME硬盘中的PCIE信号转换为SATA信号之后，才能与CPU进行数据交换。而使用到的外接转换工具，可能与对面积敏感的边缘服务器不匹配，从而使得在为边缘服务器选择硬盘时，只能选择边缘服务器的CPU所支持的信号类型对应的硬盘，选择类型受限。
发明内容
本公开实施例至少提供一种信号传输装置、方法、计算机设备及存储介质。
第一方面，本公开实施例提供了一种信号传输装置，包括两个第一数据选择器、信号转换控制器、接口连接器、转换辅助模块；
任一第一数据选择器与中央处理器或所述接口连接器连接；所述两个第一数据选择器分别通过各自的端口直接连接以及通过所述信号转换控制器连接；所述转换辅助模块与所述两个第一数据选择器以及所述接口连接器连接，其中：
所述转换辅助模块，用于响应于对所述接口连接器的检测结果，为所述两个第一 数据选择器提供端口选通信号；
所述两个第一数据选择器，用于响应转换辅助模块发送的所述端口选通信号，连通选通的目标端口，构成数据传输通道；
所述信号转换控制器，用于响应于接收到任一第一数据选择器发送的信号，完成第一数据信号与第二数据信号之间的转换。
这样，采用两个第一数据选择器、信号转换控制器、接口连接器、转换辅助模块构建了一个信号传输装置，可以根据接口连接器的检测结果，实现对于固态硬盘的信号类型的判断，并为第一数据选择器提供对应的端口选通信号，构建与固态硬盘的信号类型相匹配的数据传输通道。因此实现根据接口连接器连接的固态硬盘的信号类型做到信号自适应，使得在为边缘服务器选择硬盘时，可选类型不再单一。
一种可能的实施方式中，所述转换辅助模块，在响应于对所述接口连接器的检测结果，为所述两个第一数据选择器提供端口选通信号时，用于：
检测所述接口连接器的目标管脚的目标状态值，并根据所述目标状态值为所述两个第一数据选择器提供端口选通信号；其中，所述目标状态值表示与所述接口连接器连接的固态硬盘的信号类型。
一种可能的实施方式中，所述第一数据信号为SATA信号，所述第二数据信号为PCIE信号。
一种可能的实施方式中，针对所述两个第一数据选择器中的每一个：该第一数据选择器包含第一端口、第二端口、第三端口以及选通端口；
该第一数据选择器通过所述第一端口与所述CPU或所述接口连接器连接，通过所述第二端口与其他第一数据选择器连接，通过所述第三端口与所述信号转换控制器连接；该第一数据选择器通过选通端口与所述转换辅助模块连接；
其中，所述选通端口，用于接收所述转换辅助模块发送的端口选通信号，以使该第一数据选择器从所述第二端口和第三端口中确定目标端口，并将所述目标端口与所述第一端口进行连通。
一种可能的实施方式中，所述端口选通信号中包括需要连通的所述目标端口的标识；
所述转换辅助模块，在根据所述目标状态值为数据选择器提供端口选通信号时，用于：
基于预先设置的状态值与选通信号之间的对应关系，查找与所述目标状态值对应的端口选通信号。
这样，根据预先设置状态值与选通信号之间的对应关系，发送包含有所述目标端口的标识的端口选通信号，从而可以通过端口之间的切换，实现信号在不同数据通路上的传输，使得信号传输装置可以适应不同的不同信号类型的硬盘。
一种可能的实施方式中，在固态硬盘的信号类型为PCIE信号的情况下，所述两个第一数据选择器通过第二端口之间的连接构成所述数据传输通道。
这样，可以使得PCIE信号在传输时无需经过额外的器件，从而减小了数据传输时的延迟。
一种可能的实施方式中，所述转换辅助模块包含复杂可编程逻辑器件、供电模块以及时钟缓冲器；
所述复杂可编程逻辑器件与所述两个第一数据选择器、接口连接器、时钟缓冲器、信号转换控制器、供电模块连接；
所述复杂可编程逻辑器件，用于在所述目标状态值为预设状态值的情况下，向所述供电模块发送电源使能信号，以指示所述供电模块为所述信号转换控制器供电，以及，
向所述时钟缓冲器发送时钟使能信号，以指示所述时钟缓冲器为所述信号转换控制器提供时钟信号，以及，
向所述两个第一数据选择器发送端口选通信号。
这样，通过所述转换辅助模块为信号转换器供电，以及为所述信号转换控制器提供复位信号和时钟信号，从而使得信号转换控制器能有工作环境，从而可以实现信号的转换。
一种可能的实施方式中，将所述两个第一数据选择器构成的数据通路作为第一数据通路，所述信号传输装置还包括第二数据通路；所述第二数据通路包括两个第二数据选择器；
其中，任一第二数据选择器与所述CPU或所述接口连接器连接；与所述CPU连接的第二数据选择器分别通过不同的端口和与所述接口连接器连接的第二数据选择器连接，以及和所述第一数据通路中的信号转换控制器连接；所述转换辅助模块与所述两个第二数据选择器连接；
响应于与所述CPU连接的第二数据选择器接收到所述CPU发送的第一PCIE信号，通过所述信号转换控制器进行信号转换，并将转换后得到的SATA信号，发送至所述第一数据通路中与所述接口连接器连接的第一数据选择器，并通过该第一数据选择器将所述SATA信号发送到所述接口连接器。
这样，可以通过更多的数据通路提高数据传输速度。
一种可能的实施方式中，还包括第三数据通路，在所述第三数据通路中，所述CPU与所述接口连接器直接连接；所述CPU在发送PCIE信号时，直接通过所述第三数据通路将第二PCIE信号发送至所述接口连接器。
这样，可以通过更多的数据通路提高数据传输速度。
第二方面，本公开实施例还提供一种信号传输方法，应用于转换辅助模块，包括：
检测接口连接器的目标管脚的目标状态值；其中，所述目标状态值表示与所述接 口连接器连接的固态硬盘的信号类型；
确定与所述目标状态值对应的端口选通信号；所述端口选通信号用于控制第一数据选择器从多个待选择端口中连通目标端口；两个第一数据选择器的目标端口相互连接，构成数据传输通道，用于实现中央处理器CPU与所述接口连接器之间的数据传输；
在所述固态硬盘的信号类型为第一数据信号的情况下，控制信号转换控制器对所述CPU与所述接口连接器之间传输的数据进行第一数据信号与第二数据信号之间的转换。
一种可能的实施方式中，所述端口选通信号中包括需要连通的所述目标端口的标识；
所述确定与所述目标状态值对应的端口选通信号，包括：
基于预先设置的状态值与选通信号之间的对应关系，查找与所述目标状态值对应的端口选通信号。
一种可能的实施方式中，所述转换辅助模块包含复杂可编程逻辑器件、供电模块以及时钟缓冲器；
所述复杂可编程逻辑器件与所述两个第一数据选择器、接口连接器、时钟缓冲器、信号转换控制器、供电模块连接；
所述复杂可编程逻辑器件，用于在所述目标状态值为预设状态值的情况下，向所述供电模块发送电源使能信号，以指示所述供电模块为所述信号转换控制器供电，以及，
向所述时钟缓冲器发送时钟使能信号，以指示所述时钟缓冲器为所述信号转换控制器提供时钟信号，以及，
向所述两个第一数据选择器发送端口选通信号。
第三方面，对应于第二方面中的所述信号传输方法，本公开实施例还提供一种信号传输装置，应用于转换辅助模块，包括：
检测单元，用于检测所述接口连接器的目标管脚的目标状态值；其中，所述目标状态值表示与所述接口连接器连接的固态硬盘的信号类型；
确定单元，用于确定与所述目标状态值对应的端口选通信号；所述端口选通信号用于控制数据选择器从多个待选择端口中连通目标端口；多个数据选择器的目标端口相互连接，构成数据传输通道，用于实现所述CPU与所述接口连接器之间的数据传输；
控制单元，在所述固态硬盘的信号类型为串行高级技术附件SATA信号的情况下，控制信号转换控制器对CPU与所述接口连接器之间传输的数据进行PCIE信号与SATA信号之间的格式转换。
第四方面，本公开实施例还提供一种板卡，包括：第一方面及其任一实施方式提供的信号传输装置。
第五方面，本公开实施例还提供一种计算机设备，包括：处理器、存储器和总线，所述存储器存储有所述处理器可执行的机器可读指令，当计算机设备运行时，所述处理器与所述存储器之间通过总线通信，所述机器可读指令被所述处理器执行时执行上述第二方面中的步骤。
第六方面，本公开实施例还提供一种计算机可读存储介质，该计算机可读存储介质上存储有计算机程序，该计算机程序被处理器运行时执行上述第二方面中的步骤。
关于上述信号传输方法、计算机设备、及计算机可读存储介质的效果描述参见上述第一方面中的信号传输装置的说明，这里不再赘述。
为使本公开的上述目的、特征和优点能更明显易懂，下文特举较佳实施例，并配合所附附图，作详细说明如下。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，此处的附图被并入说明书中并构成本说明书中的一部分，这些附图示出了符合本公开的实施例，并与说明书一起用于说明本公开的技术方案。应当理解，以下附图仅示出了本公开的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1示出了本公开实施例所提供的一种将SATA信号转换为PCIE信号的转接卡的示意图；
图2示出了本公开实施例所提供的一种信号传输装置的架构示意图；
图3A示出了本公开实施例提供的一种信号传输装置的系统框图；
图3B示出了本公开实施例提供的一种信号传输装置的等效框图；
图3C示出了本公开实施例提供的另一种信号传输装置等效框图；
图3D示出了本公开实施例提供的信号传输装置在数据上行时的示意图；
图3E示出了本公开实施例提供的另一种信号传输装置的系统框图；
图4示出了本公开实施例所提供的一种信号传输方法的流程图；
图5示出了本公开实施例所提供的一种应用于转换辅助模块的信号传输装置的架构示意图；
图6示出了本公开实施例所提供的一种计算机设备的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例 中附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本公开实施例的组件可以以各种不同的配置来布置和设计。因此，以下对在附图中提供的本公开的实施例的详细描述并非旨在限制要求保护的本公开的范围，而是仅仅表示本公开的选定实施例。基于本公开的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
本文中术语“和/或”，仅仅是描述一种关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中术语“至少一种”表示多种中的任意一种或多种中的至少两种的任意组合，例如，包括A、B、C中的至少一种，可以表示包括从A、B和C构成的集合中选择的任意一个或多个元素。
经研究发现，PCIE接口所能连接的硬盘包括以SATA信号进行数据交换的SATA硬盘，以及以PCIE信号进行数据交换的NVME硬盘。而若在边缘服务器的CPU不支持SATA信号的情况下，即使通过PCIE接口连接上了SATA硬盘，也无法进行数据交换。此时需要通过转接卡等外接转换工具，将SATA硬盘中的SATA信号转换为PCIE信号之后，才能与CPU进行数据交换；另一方面，若CPU只支持SATA信号的情况下，当PCIE接口连接NVME硬盘时，也需要通过将NVME硬盘中的PCIE信号转换为SATA信号之后，才能与CPU进行数据交换。而使用到的外接转换工具，可能与对面积敏感的边缘服务器不匹配，从而使得在为边缘服务器选择硬盘时，只能选择边缘服务器的CPU所支持的信号类型对应的硬盘，选择类型受限。
示例性的，使用转接卡将SATA硬盘中的SATA信号转换为PCIE信号的示意图可以如图1所示。图1中，CPU可以表示搭载CPU的主板，M.2连接器连接SATA硬盘。CPU输出的PCIE信号经过转接卡上搭载的PCIE转SATA控制器，将PCIE信号转换为SATA信号，从而使得CPU能够与SATA硬盘进行数据交换。PCIE转SATA控制器下方的部件为所述转接卡上的转换辅助模块，所述转换辅助模块为所述PCIE转SATA控制器提供工作支持。在使用转接卡的情况下，一方面需要占用边缘服务器中宝贵的内部空间，另一方面也限制了连接的固态硬盘的类型，只能连接信号类型为SATA信号的SATA硬盘。
基于上述研究，本公开提供了一种信号传输装置、方法、计算机设备及存储介质。采用两个第一数据选择器、信号转换控制器、接口连接器、转换辅助模块构建了一个信号传输装置，可以根据接口连接器的目标管脚的目标状态值，实现对于固态硬盘的信号类型的判断，并为第一数据选择器提供对应的端口选通信号，构建与固态硬盘的信号类型相匹配的数据传输通道。因此实现根据接口连接器连接的固态硬盘的信号类型做到信号自适应，使得在为边缘服务器选择硬盘时，可选类型不再单一。
为便于对本实施例进行理解，首先对本公开实施例所公开的信号传输装置的架构 进行详细介绍。所述信号传输装置可以部署于具有计算能力的计算机设备上。示例性的，所述信号传输装置可用于边缘服务器等对面积较为敏感的环境中，在部署时分别与CPU和固态硬盘连接，以确保所述CPU与固态硬盘之间的数据传输正常进行。在具体部署时可以将所述信号传输装置集成在所述边缘服务器的主板上，或者也可以将所述信号传输装置封装成板卡安装在所述边缘服务器的主板上。
所述信号传输装置由第一数据选择器、信号转换控制器、接口连接器、转换辅助模块组成。参见图2所示，为本公开实施例提供的一种信号传输装置的架构示意图，包括转换辅助模块11、第一数据选择器12、信号转换控制器13、接口连接器14；“转换辅助模块11”下文中简称“转换辅助模块”；“第一数据选择器12”下文中简称“第一数据选择器”；“信号转换控制器13”下文中简称“信号转换控制器”；“接口连接器14”下文中简称“接口连接器”。
所述信号传输装置通过所述接口连接器连接固态硬盘，通过所述接口连接器，可以实现CPU与固态硬盘之间的数据传输；所述信号传输装置内的各个部件的具体连接关系描述如下：
任一第一数据选择器与中央处理器CPU或所述接口连接器连接；所述两个第一数据选择器分别通过各自的端口直接连接以及通过所述信号转换控制器连接；所述转换辅助模块与所述两个第一数据选择器以及所述接口连接器连接，其中：
转换辅助模块，用于响应于对所述接口连接器的检测结果，为所述两个第一数据选择器提供端口选通信号；
这里，所述对接口连接器的检测结果，可以是指对接口连接器的目标管脚的电平信号的检测结果。所述目标管脚的不同电平信息用于表示所述接口连接器连接的不同类型的固态硬盘。
具体的，所述转换辅助模块，在响应于对所述接口连接器的检测结果，为所述两个第一数据选择器提供端口选通信号时，可以检测所述接口连接器的目标管脚的目标状态值，并根据所述目标状态值为所述第一数据选择器提供端口选通信号；其中，所述目标状态值表示与所述接口连接器连接的固态硬盘的信号类型。
示例性的，若所述目标状态值为1，表示与所述接口连接器连接的固态硬盘为PCIE硬盘，若与所述目标状态值为0，表示与所述接口连接器连接的固态硬盘为SATA硬盘。
第一数据选择器，用于响应转换辅助模块发送的所述端口选通信号，连通选通的目标端口，构成数据传输通道，用于实现所述CPU与所述接口连接器之间的数据传输；其中，在所述固态硬盘的信号类型与所述CPU对应的信号类型不一致的情况下，所述两个第一数据选择器的目标端口通过信号转换控制器连接；
信号转换控制器，用于响应于接收到任一第一数据选择器发送的信号，完成第一数据信号与第二数据信号之间的转换。
其中，所述第一数据信号与所述第二数据信号为两种类型不同的数据信号。比如， 所述第一数据信号可以是SATA信号，所述第二数据信号可以是PCIE信号；或者第一数据信息可以是PCIE信号，第二数据信号可以是SATA信号。下面将以所述第一数据信号是SATA信号，所述第二数据信号是PCIE信号为例，对所述信号传输装置展开介绍。
一种可能的实施方式中，所述第一数据选择器包含第一端口、第二端口、第三端口以及选通端口；
所述第一数据选择器通过所述第一端口与所述CPU或所述接口连接器连接(所述第一端口如图3A中的端口Y)，通过所述第二端口与其他第一数据选择器连接(所述第二端口如图3A中的端口A)，通过所述第三端口与所述信号转换控制器连接(所述第三端口如图3A中的端口B)；所述第一数据选择器通过选通端口与所述转换辅助模块连接(所述选通端口如图3A中的选通端口)；
其中，所述选通端口，用于接收所述转换辅助模块发送的端口选通信号，以使所述第一数据选择器从所述第二端口和第三端口中确定目标端口，并将所述目标端口与所述第一端口进行连通。
所述两个第一数据选择器分别通过各自的端口直接连接，可以理解为所述两个第一数据选择器之间通过所述两个第一数据选择器的第二端口进行直接连接。其中，所述两个第一数据选择器的第二端口的端口标识相同，例如可以均为图3A中的端口A，也即两个第一数据选择器之间通过端口A进行连接。
一种可能的实施方式中，如图3A所示，所述转换辅助模块包含复杂可编程逻辑器件、供电模块以及时钟缓冲器；
所述复杂可编程逻辑器件与所述第一数据选择器、接口连接器、时钟缓冲器、信号转换控制器、供电模块连接；
所述复杂可编程逻辑器件，用于在所述目标状态值为预设状态值的情况下，向所述供电模块发送电源使能信号，以指示所述供电模块为所述信号转换控制器供电；以及，向所述时钟缓冲器发送时钟使能信号，以指示所述时钟缓冲器为所述信号转换控制器提供时钟信号；以及，向所述两个第一数据选择器发送端口选通信号。
这里，所述预设状态值可以理解为，用于表征所述CPU与所述接口连接器连接的固态硬盘的类型不同的状态值。示例性的，若所述CPU传输的信号为PCIE信号，则所述预设状态值可以为用于表示所述接口连接器连接的固态硬盘为SATA硬盘的信号值；若所述CPU传输的信号为SATA信号，则所述预设状态值可以为用于表示所述接口连接器连接的固态硬盘为PCIE硬盘的信号值。
一种可能的实施方式中，将所述两个第一数据选择器构成的数据通路作为第一数据通路(所述第一数据通路例如可以为图3E中的粗实线所示)。所述信号传输装置还包括第二数据通路(所述第二数据通路例如可以为图3E中的粗虚线所示)；所述第二数据通路包括两个第二数据选择器；
其中，任一第二数据选择器与所述CPU或所述接口连接器连接(如图3E中第二数据选择器1与CPU连接，第二数据选择器2与接口连接器连接)；与所述CPU连接的第二数据选择器和与所述接口连接器连接的第二数据选择器分别通过端口标识相同的端口连接，例如，第二数据选择器1和第二数据选择器2之间通过端口标识相同(端口A)的两个端口连接；以及与所述CPU连接的第二数据选择器(即第二数据选择器1)和所述第一数据通路中的信号转换控制器连接；所述转换辅助模块与所述两个第二数据选择器连接；
响应于与所述CPU连接的第二数据选择器接收到所述CPU发送的第一PCIE信号，与所述CPU连接的第二数据选择器可以将第一PCIE信号发送至信号转换控制器。通过所述信号转换控制器进行信号转换，所述信号转换控制器可以将转换后得到的SATA信号，发送至所述第一数据通路中与所述接口连接器连接的第一数据选择器，并通过该第一数据选择器将所述SATA信号发送到所述接口连接器。
一种可能的实施方式中，还包括第三数据通路。在所述第三数据通路中，所述CPU与所述接口连接器直接连接；所述CPU在发送PCIE信号时，直接通过所述第三数据通路将第二PCIE信号发送至所述接口连接器。
下面将结合具体的实施场景，对上述信号传输装置展开详细介绍。
以CPU向接口连接器发送PCIE信号为例，如图3A所示，为本公开实施例提供的一种信号传输装置的系统框图，其中：
接口连接器为M.2接口连接器，用于连接新一代接口M.2接口的固态硬盘；
转换辅助模块包括复杂可编程逻辑器件(Complex Programmable Logic Device，CPLD)、供电模块、时钟缓冲器(Clock Buffer)；
第一数据选择器为包含两个可选端口(例如，端口A和端口B)的Multiplexer，用于接收所述CPLD发送的端口选通信号，并根据所述端口选通信号(即选通端口输入的信号)，从端口A(即第二端口)和端口B(即第三端口)中选择目标端口与端口Y(即第一端口)进行连通，构成数据通路；
信号转换控制器为PCIE转SATA控制器，用于在接收到任一第一数据选择器发送的信号之后，完成第一PCIE信号与SATA信号之间的数据转换，包括将所述第一PCIE信号转换为SATA信号，以及将所述SATA信号转换为第一PCIE信号；
CPU发送并接收PCIE信号。实线连接的PCIE lane0表示在PCIE总线的物理通路中的一个数据通路lane0。在lane0所在的数据传输通道上包含了上述部件，可以使得在lane0这条数据传输通道上可以传输SATA信号或者PCIE信号。虚线连接的PCIE lane1、PCIE lane2、PCIE lane3表示CPU支持通过多个PCIE lane进行数据传输。PCIE lane1、PCIE lane2、PCIE lane3虽然可以连接在M.2连接器上，但PCIE lane1、PCIE lane2、PCIE lane3无法传输SATA信号。因此其分别对应的M.2连接器的管脚为悬空状态，故用虚线表示。
实际应用中，所述M.2连接器在与固态硬盘进行连接时，M.2连接器的PEDET管脚在连接不同类型的固态硬盘时的状态值是不同的，因此可以将所述PEDET管脚作为所述目标管脚，所述PEDET管脚的电平真值表可以如表1所示：
表1
PEDET信号电平 高 低
固态硬盘类型 NVME硬盘 SATA硬盘
其中，当所述M.2连接器连接的固态硬盘为支持PCIE信号的NVME硬盘时，所述PEDET管脚的信号电平为高；当所述M.2连接器连接的固态硬盘为支持SATA信号的SATA硬盘时，所述PEDET管脚的信号电平为低。因此转换控制模块可以在检测到PEDET管脚的信号电平后，根据所述PEDET管脚的信号电平与固态硬盘类型的对应关系，确定与M.2连接器连接的固态硬盘类型，即确定与M.2连接器连接的固态硬盘的信号类型，再输出对应的控制信号，以控制lane0所在的数据传输通道上的数据传输。
这里，所述控制信号包括端口选通信号。所述端口选通信号中包括需要连通的所述目标端口的标识。所述转换辅助模块，在根据所述目标状态值为第一数据选择器提供端口选通信号时，可以基于预先设置的状态值与选通信号之间的对应关系，查找与所述目标状态值对应的端口选通信号。所述CPLD输出的控制信号可以如下表2所示：
表2
PEDET信号 端口选通信号 高速信号 电源使能信号 时钟使能信号 复位信号
高 高(端口A) PCIE信号 不使能 不使能 不提供
低 低(端口B) SATA信号 使能 使能 提供
其中，当所述PEDET管脚的信号为高时，表征M.2连接器连接的固态硬盘为支持PCIE信号的NVME硬盘，端口选通信号为高电平，选通信号则为指示目标端口A与端口Y进行连通的信号。此时图3A中的高速信号为PCIE信号，由于CPU发送和接收的信号类型也为PCIE信号，因此没有信号转换的需求。因此信号转换控制器无需工作，也即所述电源使能信号为不使能、时钟使能信号为不使能、不提供复位信号。此时的信号传输装置的等效框图可以如图3B所示。图3B中，PCIE转SATA控制器由于没有工作环境，相当于不存在。而lane0所在的数据传输通道是以两个第一数据选择器的端口A相连，并以PCIE信号进行数据传输，也即在所述固态硬盘的信号类型为所述PCIE信号的情况下，两个第一数据选择器的目标端口之间直接连接；
此外，当所述PEDET管脚的信号为低时，表征M.2连接器连接的固态硬盘为支持SATA信号的SATA硬盘，端口选通信号为低电平，选通信号则为指示目标端口B与端口Y进行连通的信号。此时图3A中的高速信号为SATA信号，由于CPU发送和接收的信号类型为PCIE信号，因此有信号转换的需求，需要为时钟缓冲器、供电模块以及PCIE转SATA控制器提供工作环境，也即所述电源使能信号为使能、时钟使能信号为使能、提供复位信号。也即在所述目标状态值为预设状态值(PEDET管脚的信号为低) 的情况下，转换辅助模块中的CPLD为所述PCIE转SATA控制器供电，以及为所述PCIE转SATA控制器提供复位信号和时钟信号。
进一步的，在有了复位信号、PCIE 100M时钟信号、以及供电模块提供的电源的情况下，所述PCIE转SATA控制器便可以正常工作，将接收到的信号从PCIE信号转换为SATA信号。此时的信号传输装置的等效框图可以如图3C所示，图3C中，PCIE转SATA控制器具备了工作环境，而lane0所在的数据传输通道是以：一个第一数据选择器的端口B-PCIE转SATA控制器-另一个相连的第一数据选择器的端口B的顺序进行连接，从而通过PCIE转SATA控制器的转换功能，即可实现CPU与SATA硬盘的数据交换。
需要说明的是，在lane0所在的数据传输通道上使用了单箭头对各个部件进行连接，是为了表示CPU和M.2连接器的上下位关系，CPU为上位组件，而M.2连接器为下位组件，数据交换时的下行即为从上位组件CPU传输到下位组件M.2连接器。同时也是为了跟所述转换辅助模块中的单向箭头保持一致，从而使得整个框图协调一致，简洁美观。数据上行时的系统框图可以如图3D所示，图3D与图3A的区别为箭头方向不同，图3D中所包含的其他内容在此不再赘述。
而在实际使用中，数据通路lane0上有发送逻辑TX和接收逻辑RX这两个数据传输逻辑，也即数据在传输时(数据交换时)是双向的；对应的，PCIE转SATA控制器除了可以在接收到CPU一侧发送的第一PCIE信号之后，将所述第一PCIE信号转换为SATA信号，还可以在接收到M.2连接器一侧发送的SATA信号之后，将所述SATA信号转换为第一PCIE信号。
此外，所述CPU在与所述M.2连接器连接的NVME硬盘进行数据交换时，除了可以在lane0上以第一PCIE信号进行数据传输之外，还可以在lane1(第二数据通路)、lane2(第三数据通路)、lane3(第四数据通路)上以第二PCIE信号进行数据传输。所述第一PCIE信号和第二PCIE信号为相同标准下的PCIE信号(比如均为PCIE3.0标准的PCIE信号)，区别仅为在信号传输时，是否经过了数据选择器(包括第一数据选择器和第二数据选择器)。例如，在图3A中，经过了第一数据选择器传输的PCIE信号为所述第一PCIE信号(比如图3A中的lane0上的PCIE信号)，未经过所述第一数据选择器传输的PCIE信号为所述第二PCIE信号(比如图3A中的lane1、lane2、lane3上的PCIE信号)。其中，在经过lane1、lane2、lane3进行第二PCIE信号传输时，CPU与物理通路中的lane1、lane2、lane3所对应的端口连接。
这样，在所述CPU支持多个PCIE lane，并使用PCIE信号进行数据交换时，可以通过更多的数据通路提高数据传输速度。
以信号传输为从CPU传输至SATA硬盘为例，可以通过以下步骤完成：
步骤1、转换辅助模块中的CPLD在检测到PEDET管脚的信号为低，为PCIE lane0中的所有第一数据选择器提供端口选通信号，指示端口B为目标端口，并为PCIE转SATA控制器提供复位信号、PCIE 100M时钟信号以及供电；
步骤2、CPU将PCIE信号从对应的PCIE接口发出，发送至与CPU连接的第一数据选择器的端口Y，并通过第一数据选择器的目标端口B，将PCIE信号发送至所述PCIE转SATA控制器；
步骤3、PCIE转SATA控制器在接收到PCIE信号之后，将所述PCIE信号转换为SATA信号，并将所述SATA信号发送至与M.2连接器连接的第一数据选择器的端口B；
步骤4、与M.2连接器连接的第一数据选择器的端口B在接收到SATA信号之后，通过端口Y向M.2连接器发送SATA信号，以使M.2连接器连接的SATA硬盘能够接收到SATA信号，并按照所述SATA信号执行对应的操作。
关于上述步骤的具体内容参见上文相关内容，在此不再赘述。
一种可能的实施方式中，如图3E所示，为本公开实施例提供的另一种信号传输装置的系统框图。接口连接器为M.2接口连接器，用于M.2接口的固态硬盘；转换辅助模块包括复杂可编程逻辑器件(Complex Programmable logic device，CPLD)、供电模块、时钟缓冲器；第一数据选择器和第二数据选择器均为包含两个可选端口(例如，端口A和端口B)的Multiplexer，用于接收所述CPLD发送的端口选通信号，并根据所述端口选通信号，从端口A和端口B中选择目标端口与端口Y进行连通；信号转换控制器为PCIE转SATA控制器，用于在接收到任一数据选择器发送的信号之后，完成第一PCIE信号与SATA信号之间的数据转换；CPU发送并接收PCIE信号，实线连接的PCIE lane0和lane1表示在PCIE总线的物理通路中的两个数据通路lane0和lane1，在lane0所在的数据传输通道上包含了上述部件，可以使得在lane0这条数据传输通道上传输SATA信号或者PCIE信号；而在lane1所在的数据传输通道上包含了两个所述第二数据选择器，可以使得在lane1这条数据传输通道上传输PCIE信号；虚线连接的PCIE lane2和PCIE lane3表示CPU支持通过多个PCIE lane进行数据传输，PCIE lane2和PCIE lane3虽然可以连接在M.2连接器上，但PCIE lane2和PCIE lane3无法传输SATA信号，因此其分别对应的M.2连接器的管脚为悬空状态，故用虚线表示。
这里，lane0所在的数据通路为第一数据通路，在所述第一数据通路中的数据选择器为第一数据选择器，分别为第一数据选择器1和第一数据选择器2；在所述固态硬盘的信号类型为所述SATA信号的情况下，所述两个第一数据选择器的目标端口(端口B)通过PCIE转SATA控制器连接。
lane1所在的数据通路为第二数据通路，在所述第二数据通路中的数据选择器为第二数据选择器，分别为第二数据选择器1和第二数据选择器2；所述第二数据选择器1与所述PCIE转SATA控制器连接，在所述固态硬盘的信号类型为所述SATA信号的情况下，所述第二数据选择器1在接收到所述CPU发送的第一PCIE信号后，通过所述PCIE转SATA控制器进行信号转换，并将转换后得到的SATA信号，通过所述第一数据选择器2发送到所述M.2连接器。
具体的，所述CPLD输出的控制信号也可以如上表2所示，图3E中的第一数据通路，与上述图3A中的lane0所在的数据传输通道，进行数据交换时的执行内容完全一 致，在此不再赘述，因此下面将详细描述第二数据通路在进行数据交换时所执行的具体内容：
当所述PEDET管脚的信号为高时，表征此时M.2连接器连接的固态硬盘为支持PCIE信号的NVME硬盘，端口选通信号为高电平，选通信号为指示目标端口A与端口Y进行连通的信号。此时图3E中的高速信号为PCIE信号，在第二数据通路上的第二数据选择器通过端口A进行连接，整个第二数据通路的连接顺序为：CPU-第二数据选择器1的端口A-第二数据选择器2的端口A-M.2连接器；
此外，当所述PEDET管脚的信号为低时，表征此时M.2连接器连接的固态硬盘为支持SATA信号的SATA硬盘，端口选通信号为低电平，选通信号为指示目标端口B与端口Y进行连通的信号。此时图3E中，第一数据通路上的高速信号为SATA信号，而第二数据通路是不通的(并未连接到第二数据选择器2)，因此第二数据通路上的高速信息并不存在。第二数据选择器1在接收到所述CPU发送的第一PCIE信号后，通过所述PCIE转SATA控制器进行信号转换，并将转换后得到的SATA信号，通过第一数据选择器2发送到所述M.2连接器，从而实现CPU与SATA硬盘的数据交换。
具体实施中，所述CPU在与所述M.2连接器连接的NVME硬盘进行数据交换时，除了可以在lane0和lane1上以第一PCIE信号进行数据传输之外，还可以在lane2和lane3上以第二PCIE信号进行数据传输。可以根据实际需要进行相关设置，本公开实施例对此不做限定。
实际应用中，如图3E所示的信号传输装置和如图3A所示的信号传输装置，在信号传输速度上没有什么差别。区别仅为图3E所示的信号传输装置中多了两个第二数据选择器，从而在第二数据通路上可以传输PCIE信号；且在M.2连接器连接SATA硬盘时，对所述M.2连接器上与第二数据通路对应的管脚进行物理断开，从而避免了信号传输时对相关管脚的损耗，提高了M.2连接器的使用寿命，提高了在边缘计算的环境下，整个信号传输装置的可用性。
进一步的，与图3A至图3E的改进相似，可以在图3E的基础上，再将lane2和lane3所在的数据传输通道替换为与lane1所在的第二数据通路相同的结构，也即在lane2和lane3上也分别部署两个数据选择器，从而可以使得在对应的数据通路上可以传输PCIE信号；且在M.2连接器连接SATA硬盘时，对所述M.2连接器上对应的管脚进行物理断开，从而避免了信号传输时对相关管脚的损耗，同样可以起到提高M.2连接器的使用寿命，以及在边缘计算的环境下，整个信号传输装置的可用性的作用。
需要说明的是，在图3A所示的信号传输装置中，由于减少了数据选择器的使用，因此在部署时的部署成本也会更低；此外在部署时，为了节约部署时的面积，也可以将所述信号传输装置中各个部件集成在主板上，通过板载的方式实现信号传输和转换的功能。关于具体部署时选用本公开实施例所提供的何种类型的信号传输装置，可以根据实际需要进行选择，本公开实施例对此不做限定。
此外，CPU除了可以发送并接收PCIE信号，还可以只发送并接收SATA信号。在 这种情况下的系统框图与图3A类似，由于SATA信号的带宽较小，只通过一个数据通路进行传输即可，因此虚线表示的三条PCIE数据通路则可以直接删除。
在这种情况下，CPLD输出的控制信号可以如下表3所示：
表3
PEDET信号 端口选通信号 高速信号 电源使能信号 时钟使能信号 复位信号
高 低(端口B) PCIE信号 使能 使能 提供
低 高(端口A) SATA信号 不使能 不使能 不提供
其中，表3对应的具体内容可以参照上文表2的相关描述，在此不再赘述。
在这种情况下，以信号传输为从CPU传输至NVME硬盘为例，可以通过以下步骤完成：
步骤1、转换辅助模块中的CPLD在检测到PEDET管脚的信号为高，为SATA传输通道中的所有第一数据选择器提供端口选通信号，指示端口B为目标端口，并为PCIE转SATA控制器提供复位信号、PCIE 100M时钟信号以及供电；
步骤2、CPU将SATA信号从对应的SATA接口发出，发送至与CPU连接的第一数据选择器的端口Y，并通过第一数据选择器的目标端口B，将SATA信号发送至所述PCIE转SATA控制器；
步骤3、PCIE转SATA控制器在接收到SATA信号之后，将所述SATA信号转换为PCIE信号，并将所述PCIE信号发送至与M.2连接器连接的第一数据选择器的端口B；
步骤4、与M.2连接器连接的第一数据选择器的端口B在接收到PCIE信号之后，通过端口Y向M.2连接器发送PCIE信号，以使M.2连接器连接的NVME硬盘能够接收到PCIE信号，并按照所述PCIE信号执行对应的操作。
关于上述步骤的具体内容参见上文相关内容，在此不再赘述。
参见图4所示，为本公开实施例提供的信号传输方法的流程图，所述信号传输方法的执行主体为转换辅助模块，所述方法包括步骤S401～S403。
S401：检测接口连接器的目标管脚的目标状态值；其中，所述目标状态值表示与所述接口连接器连接的固态硬盘的信号类型；
S402：确定与所述目标状态值对应的端口选通信号；所述端口选通信号用于控制第一数据选择器从多个待选择端口中连通目标端口；两个第一数据选择器的目标端口相互连接，构成数据传输通道，用于实现中央处理器CPU与所述接口连接器之间的数据传输；
S403：在所述固态硬盘的信号类型为第一数据信号的情况下，控制信号转换控制器对所述CPU与所述接口连接器之间传输的数据进行第一数据信号与第二数据信号之间的格式转换。
一种可能的实施方式中，所述端口选通信号中包括需要连通的所述目标端口的标识；
所述确定与所述目标状态值对应的端口选通信号，包括：
基于预先设置的状态值与选通信号之间的对应关系，查找与所述目标状态值对应的端口选通信号。
一种可能的实施方式中，所述转换辅助模块包含复杂可编程逻辑器件、供电模块以及时钟缓冲器；
所述复杂可编程逻辑器件与所述第一数据选择器、接口连接器、时钟缓冲器、信号转换控制器、供电模块连接；
所述复杂可编程逻辑器件，用于在所述目标状态值为预设状态值的情况下，向所述供电模块发送电源使能信号，以指示所述供电模块为所述信号转换控制器供电；以及，
向所述时钟缓冲器发送时钟使能信号，以指示所述时钟缓冲器为所述信号转换控制器提供时钟信号；以及，
向所述两个第一数据选择器发送端口选通信号。
这里，关于本公开实施例提供的信号传输方法的具体内容，可以参照上文中所述转换辅助模块在信号传输装置运行时的相关描述，在此不再赘述。
本公开实施例提供的信号传输装置及方法，采用两个第一数据选择器、信号转换控制器、接口连接器、转换辅助模块构建了一个信号传输装置，可以根据接口连接器的目标管脚的目标状态值，实现对于固态硬盘的信号类型的判断，并为第一数据选择器提供对应的端口选通信号，构建与固态硬盘的信号类型相匹配的数据传输通道。因此实现根据接口连接器连接的固态硬盘的信号类型做到信号自适应，使得在为边缘服务器选择硬盘时，可选类型不再单一。另外，将信号转换控制器集成到服务器的主板上，可以缩小信号转换控制器所占用的面积，适应边缘服务器对于面积敏感的特点。
本领域技术人员可以理解，在具体实施方式的上述方法中，各步骤的撰写顺序并不意味着严格的执行顺序而对实施过程构成任何限定，各步骤的具体执行顺序应当以其功能和可能的内在逻辑确定。
基于同一发明构思，本公开实施例中还提供了与信号传输方法对应的信号传输装置。由于本公开实施例中的装置解决问题的原理与本公开实施例上述信号传输方法相似，因此装置的实施可以参见方法的实施，重复之处不再赘述。
参照图5所示，为本公开实施例提供的一种信号传输装置的架构示意图，应用于转换辅助模块。所述装置包括：检测单元501、确定单元502、控制单元503；其中，
检测单元501，用于检测所述接口连接器的目标管脚的目标状态值；其中，所述目标状态值表示与所述接口连接器连接的固态硬盘的信号类型；
确定单元502，用于确定与所述目标状态值对应的端口选通信号；所述端口选通信 号用于控制数据选择器从多个待选择端口中连通目标端口；多个数据选择器的目标端口相互连接，构成数据传输通道，用于实现所述CPU与所述接口连接器之间的数据传输；
控制单元503，用于在所述固态硬盘的信号类型为SATA信号的情况下，控制信号转换控制器对CPU与所述接口连接器之间传输的数据进行PCIE信号与SATA信号之间的格式转换。
本公开实施例提供的应用于转换辅助模块的信号传输装置，可以根据接口连接器的目标管脚的目标状态值，实现对于固态硬盘的信号类型的判断，并为数据选择器提供对应的端口选通信号，构建与固态硬盘的信号类型相匹配的数据传输通道。因此实现根据接口连接器连接的固态硬盘的信号类型做到信号自适应，使得在为边缘服务器选择硬盘时，可选类型不再单一。
关于装置中的各模块的处理流程、以及各模块之间的交互流程的描述可以参照上述方法实施例中的相关说明，这里不再详述。
基于同一技术构思，本公开实施例还提供了一种计算机设备。参照图6所示，为本公开实施例提供的计算机设备600的结构示意图，包括处理器601、存储器602、和总线603。其中，存储器602用于存储执行指令，包括内存6021和外部存储器6022；这里的内存6021也称内存储器，用于暂时存放处理器601中的运算数据，以及与硬盘等外部存储器6022交换的数据，处理器601通过内存6021与外部存储器6022进行数据交换，当计算机设备600运行时，处理器601与存储器602之间通过总线603通信，使得处理器601在执行以下指令：
检测接口连接器的目标管脚的目标状态值；其中，所述目标状态值表示与所述接口连接器连接的固态硬盘的信号类型；
确定与所述目标状态值对应的端口选通信号；所述端口选通信号用于控制第一数据选择器从多个待选择端口中连通目标端口；两个第一数据选择器的目标端口相互连接，构成数据传输通道，用于实现中央处理器CPU与所述接口连接器之间的数据传输；
在所述固态硬盘的信号类型为第一数据信号的情况下，控制信号转换控制器对所述CPU与所述接口连接器之间传输的数据进行第一数据信号与第二数据信号之间的转换。
本公开实施例还提供一种板卡，包括上述任一实施例提供的信号传输装置。实施时可以将信号传输装置实施为小卡电路，插入主板完成电路转换。
本公开实施例还提供一种计算机可读存储介质，该计算机可读存储介质上存储有计算机程序，该计算机程序被处理器运行时执行上述方法实施例中所述的信号传输方法的步骤。其中，该存储介质可以是易失性或非易失的计算机可读取存储介质。
本公开实施例还提供一种计算机程序产品，该计算机程序产品承载有程序代码，所述程序代码包括的指令可用于执行上述方法实施例中所述的信号传输方法的步骤，具体可参见上述方法实施例，在此不再赘述。
其中，上述计算机程序产品可以具体通过硬件、软件或其结合的方式实现。在一个可选实施例中，所述计算机程序产品具体体现为计算机存储介质，在另一个可选实施例中，计算机程序产品具体体现为软件产品，例如软件开发包(Software Development Kit，SDK)等等。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述装置的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。在本公开所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，又例如，多个单元或组件可以结合，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些通信接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本公开各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个处理器可执行的非易失的计算机可读取存储介质中。基于这样的理解，本公开的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本公开各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是：以上所述实施例，仅为本公开的具体实施方式，用以说明本公开的技术方案，而非对其限制，本公开的保护范围并不局限于此，尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，其依然可以对前述实施例所记载的技术方案进行修改或可轻易想到变化，或者对其中部分技术特征进行等同替换；而这些修改、变化或者替换，并不使相应技术方案的本质脱离本公开实施例技术方案的精神和范围，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应所述以权利要求的保护范围为准。

Claims (15)

  1. 一种信号传输装置，包括两个第一数据选择器、信号转换控制器、接口连接器、转换辅助模块；
    任一第一数据选择器与中央处理器或所述接口连接器连接；所述两个第一数据选择器分别通过各自的端口直接连接，以及通过所述信号转换控制器连接；所述转换辅助模块与所述两个第一数据选择器以及所述接口连接器连接，其中：
    所述转换辅助模块，用于响应于对所述接口连接器的检测结果，为所述两个第一数据选择器提供端口选通信号；
    所述两个第一数据选择器，用于响应转换辅助模块发送的所述端口选通信号，连通选通的目标端口，构成数据传输通道；
    所述信号转换控制器，用于响应于接收到任一第一数据选择器发送的信号，完成第一数据信号与第二数据信号之间的转换。
  2. 根据权利要求1所述的信号传输装置，其特征在于，所述转换辅助模块，在响应于对所述接口连接器的检测结果，为所述两个第一数据选择器提供端口选通信号时，用于：
    检测所述接口连接器的目标管脚的目标状态值，并根据所述目标状态值为所述两个第一数据选择器提供端口选通信号；其中，所述目标状态值表示与所述接口连接器连接的固态硬盘的信号类型。
  3. 根据权利要求1所述的信号传输装置，其特征在于，所述第一数据信号为SATA信号，所述第二数据信号为PCIE信号。
  4. 根据权利要求1所述的信号传输装置，其特征在于，针对所述两个第一数据选择器中的每一个：
    该第一数据选择器包含第一端口、第二端口、第三端口以及选通端口；
    该第一数据选择器通过所述第一端口与所述中央处理器或所述接口连接器连接，通过所述第二端口与其他第一数据选择器连接，通过所述第三端口与所述信号转换控制器连接；该第一数据选择器通过选通端口与所述转换辅助模块连接；
    其中，所述选通端口，用于接收所述转换辅助模块发送的端口选通信号，以使该第一数据选择器从所述第二端口和第三端口中确定目标端口，并将所述目标端口与所述第一端口进行连通。
  5. 根据权利要求2所述的信号传输装置，其特征在于，所述端口选通信号中包括需要连通的所述目标端口的标识；
    所述转换辅助模块，在根据所述目标状态值为数据选择器提供端口选通信号时，用于：
    基于预先设置的状态值与选通信号之间的对应关系，查找与所述目标状态值对应的端口选通信号。
  6. 根据权利要求3所述的信号传输装置，其特征在于，在固态硬盘的信号类型为PCIE信号的情况下，所述两个第一数据选择器通过第二端口之间的连接构成所述数据传输通道。
  7. 根据权利要求2所述的信号传输装置，其特征在于，所述转换辅助模块包含复杂可编程逻辑器件、供电模块以及时钟缓冲器；
    所述复杂可编程逻辑器件与所述两个第一数据选择器、接口连接器、时钟缓冲器、信号转换控制器、供电模块连接；
    所述复杂可编程逻辑器件，用于在所述目标状态值为预设状态值的情况下，向所述供电模块发送电源使能信号，以指示所述供电模块为所述信号转换控制器供电；以及，
    向所述时钟缓冲器发送时钟使能信号，以指示所述时钟缓冲器为所述信号转换控制器提供时钟信号；以及，
    向所述两个第一数据选择器发送端口选通信号。
  8. 根据权利要求1至7任一所述的信号传输装置，其特征在于，将所述两个第一数据选择器构成的数据通路作为第一数据通路，所述信号传输装置还包括第二数据通路；所述第二数据通路包括两个第二数据选择器；
    其中，任一第二数据选择器与所述中央处理器或所述接口连接器连接；与所述中央处理器连接的第二数据选择器分别通过不同的端口和与所述接口连接器连接的第二数据选择器连接，以及和所述第一数据通路中的信号转换控制器连接；所述转换辅助模块与所述两个第二数据选择器连接；
    响应于与所述中央处理器连接的第二数据选择器接收到所述中央处理器发送的第一PCIE信号，通过所述信号转换控制器进行信号转换，并将转换后得到的SATA信号，发送至所述第一数据通路中与所述接口连接器连接的第一数据选择器，并通过该第一数据选择器将所述SATA信号发送到所述接口连接器。
  9. 根据权利要求3所述的信号传输装置，其特征在于，还包括第三数据通路，在所述第三数据通路中，所述中央处理器与所述接口连接器直接连接；所述中央处理器在发送PCIE信号时，直接通过所述第三数据通路将第二PCIE信号发送至所述接口连接器。
  10. 一种信号传输方法，应用于转换辅助模块，包括：
    检测接口连接器的目标管脚的目标状态值；其中，所述目标状态值表示与所述接口连接器连接的固态硬盘的信号类型；
    确定与所述目标状态值对应的端口选通信号；所述端口选通信号用于控制第一数据 选择器从多个待选择端口中连通目标端口；两个第一数据选择器的目标端口相互连接，构成数据传输通道，用于实现中央处理器与所述接口连接器之间的数据传输；
    在所述固态硬盘的信号类型为第一数据信号的情况下，控制信号转换控制器对所述中央处理器与所述接口连接器之间传输的数据进行第一数据信号与第二数据信号之间的转换。
  11. 根据权利要求10所述的方法，其特征在于，所述端口选通信号中包括需要连通的所述目标端口的标识；确定与所述目标状态值对应的端口选通信号，包括：基于预先设置的状态值与选通信号之间的对应关系，查找与所述目标状态值对应的端口选通信号。
  12. 根据权利要求10所述的方法，其特征在于，所述转换辅助模块包括复杂可编程逻辑器件、供电模块以及时钟缓冲器；所述复杂可编程逻辑器件与所述两个第一数据选择器、接口连接器、时钟缓冲器、信号转换控制器、供电模块连接；所述方法包括：
    在所述目标状态值为预设状态值的情况下，
    所述复杂可编程逻辑器件向所述供电模块发送电源使能信号，以指示所述供电模块为所述信号转换控制器供电；
    向所述时钟缓冲器发送时钟使能信号，以指示所述时钟缓冲器为所述信号转换控制器提供时钟信号；以及，
    向所述两个第一数据选择器发送端口选通信号。
  13. 一种板卡，包括：如权利要求1至9任一项所述的装置。
  14. 一种计算机设备，包括：处理器、存储器和总线，所述存储器存储有所述处理器可执行的机器可读指令，当计算机设备运行时，所述处理器与所述存储器之间通过总线通信，所述机器可读指令被所述处理器执行时执行如权利要求10至12任一项所述的信号传输方法的步骤；或者处理器、存储器、总线、以及如权利要求13所述的板卡。
  15. 一种计算机可读存储介质，该计算机可读存储介质上存储有计算机程序，该计算机程序被处理器运行时执行如权利要求10至12任一项所述的信号传输方法的步骤。
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