WO2023246612A1 - 一种超薄型芯片制造封装方法 - Google Patents
一种超薄型芯片制造封装方法 Download PDFInfo
- Publication number
- WO2023246612A1 WO2023246612A1 PCT/CN2023/100400 CN2023100400W WO2023246612A1 WO 2023246612 A1 WO2023246612 A1 WO 2023246612A1 CN 2023100400 W CN2023100400 W CN 2023100400W WO 2023246612 A1 WO2023246612 A1 WO 2023246612A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- chip
- flip
- colloid
- ultra
- thickness
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 38
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000000084 colloidal system Substances 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000012790 adhesive layer Substances 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims abstract description 16
- 239000000463 material Substances 0.000 claims description 13
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 239000000843 powder Substances 0.000 claims description 9
- 238000005516 engineering process Methods 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 229910003460 diamond Inorganic materials 0.000 claims description 4
- 239000010432 diamond Substances 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910052582 BN Inorganic materials 0.000 claims description 3
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 3
- INAHAJYZKVIDIZ-UHFFFAOYSA-N boron carbide Chemical compound B12B3B4C32B41 INAHAJYZKVIDIZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052580 B4C Inorganic materials 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 229920001296 polysiloxane Polymers 0.000 claims 1
- 238000000227 grinding Methods 0.000 abstract description 18
- 238000005520 cutting process Methods 0.000 abstract description 7
- 239000002390 adhesive tape Substances 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 29
- 229910052594 sapphire Inorganic materials 0.000 description 10
- 239000010980 sapphire Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 239000000741 silica gel Substances 0.000 description 5
- 229910002027 silica gel Inorganic materials 0.000 description 5
- 239000012467 final product Substances 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 239000012530 fluid Substances 0.000 description 3
- 230000005693 optoelectronics Effects 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
Definitions
- the invention belongs to the field of chip technology, and specifically relates to an ultra-thin chip manufacturing and packaging method.
- chip developers designed a flip-chip structure, that is, turning the main chip upside down. Since the substrate is peeled off and the chip material is transparent, the light excited by the luminescent layer can be directly It is emitted from the other side of the electrode. At the same time, a structure is designed for flip-chip to facilitate wire bonding in the LED packaging factory. Therefore, the entire chip is called a flip chip. This structure is often used in high-power chips.
- Flip chip has the following advantages: first, it does not dissipate heat through sapphire and can be used with large currents; second, the size can be smaller and the optics are easier to match; third, the heat dissipation function is improved, which improves the life of the chip; fourth The first is to improve the anti-static ability; the fifth is to lay the foundation for the development of subsequent packaging processes.
- the difficulty in wafer thinning is that it is a hard and brittle material.
- the larger the wafer area the lower the stability of the grinding and polishing process and the higher the breakage rate. This results in the packaging thickness of these semiconductors being limited. Since silicon wafers are easier to process than sapphire, silicon chips can be packaged to a thickness as low as 30 microns using the manufacturing process and packaging method of the present invention.
- the present invention discloses an ultra-thin chip manufacturing and packaging method.
- the thin chip manufacturing and packaging method of the present invention includes the following steps:
- Step 3 Fill the gaps between the chips in the flip-chip array with the first colloid, so that the first colloid covers all sides of the flip-chip, or the thicker first colloid covers five sides;
- Step 4 After the colloid coating is solidified, the top surface of the flip chip is ground and thinned twice. The overall thickness of the secondary thinned chip obtained by the second thinning is reduced to 20 ⁇ m ⁇ 70 ⁇ m;
- Step 6 Cut the packaged single flip-chip.
- the step 2 is performed using crystal bonding machine equipment.
- the first colloid and/or the second colloid is silica gel.
- the specific method for coating the flip-chip with the first colloid in step 3 is a spot injection method or a prefabricated mold is used to cover the flip-chip and then the first colloid is poured.
- the abrasive powder material used for the secondary thinning in step 4 is any one of silicon carbide, boron carbide, cubic boron nitride, and diamond powder.
- the grain thinning intensity can be increased.
- the thickness after packaging of the grain can be less than 100 Micron chips (up to 40 microns).
- the IC semiconductor silicon wafer is packaged using the packaging method of the present invention. Since silicon wafers are easier to process than sapphire, packaging using the packaging method of the present invention can achieve a lower thickness of 30 microns.
- Step 3 Fill the gaps between the chips in the flip-chip array with the first colloid, so that the first colloid covers all sides of the flip-chip. If the amount of the first colloid is large, it may cover five sides of the flip-chip; however, It does not affect subsequent processes, and the first colloid on the top can be removed by grinding in subsequent steps.
- Step 3 can use the spot injection method: use a device to inject the colloid by extruding it as a spot injection, or you can use machinery and equipment to perform extrusion and spot injection; you can also use a prefabricated mold to cover the flip chip and then pour it.
- the second colloid can be made of the same material as the first colloid, or it can be other colloids. Two colloids with different optical properties can realize more diversified light-emitting components.
- the thinned flip-chip is cut into single FC ICs (length and width range from 100um to 1000um); the above steps have been completed in the IC factory.
- Anapex Technology Co., Ltd. Anapex of Taiwan is used in this case.
- the single die of IC is 540x590um in length and width and 150um in thickness.
- the thickness of the second colloid can be 20 to 50um
- Step 1 Purchase the flip-chip LED chip wafer from the manufacturer New Century Optoelectronics Technology Co., Ltd. (Taiwan, China). The manufacturer has initially ground the sapphire substrate layer to initially reduce the thickness of the flip-chip LED chip wafer to 100 ⁇ m, and will The initially thinned wafer is cut into a single flip chip; its length and width are respectively 200 ⁇ 500um single die.
- Step 2 Arrange single flip-chips on the carrier board in an array form, with the spacing between individual chips being 0.2-0.5 mm, and the electrode surface facing the carrier board; Step 2 uses LEDs produced by Shenzhen Xinyichang Technology Co., Ltd. The flip-chip LED die-bonding machine produced by the die-bonding machine is used.
- a single flip-chip chip is arranged on the double-sided adhesive layer and is bonded and fixed by the adhesive layer;
- Step 3 Use the first colloid as silica gel to fill the gaps between the chips in the flip-chip array, so that the first colloid covers all sides of the flip-chip. If the amount of the first colloid is large, it may cover five sides of the flip-chip. ; But it does not affect the subsequent process.
- the first colloid on the top can be removed by grinding in subsequent steps.
- the first colloid is silica gel, its main functions are: (1) fixing the flip-chip to avoid sapphire displacement during grinding; (2) shock absorption: avoiding chip cracking or defects during grinding; (3) can be used according to lighting requirements
- the first colloid is mixed into the filter medium to adjust the light color or brightness of the LED chip.
- Step 4 After the colloid coating is solidified, the top surface of the flip chip is ground and thinned twice with a fully automatic wafer grinding machine (Wafer Grinding, GDM300 Hengpeng). Different samples are thinned twice to obtain the secondary thinning results. The overall thickness of the thin chip is reduced to 20 ⁇ m, 40 ⁇ m, and 70 ⁇ m respectively, and the polishing in the polishing fluid
- the powder material is silicon carbide (SiC).
- Step 5 Cover a layer of second colloid (silica gel) directly above the flip-chip to complete the final packaging.
- the thickness of the second colloid is 20 ⁇ m;
- a chip arrangement machine can be used to arrange the independent flip-chips neatly on the SPV224 blue film to complete the package.
- the electrodes are attached to the blue film, or an automatic placement machine can be used to install the independent flip-chips on the chip roll.
- the rigid substrate can be basically repeated until it becomes defective or damaged, or it can be discarded after a single use.
- the relevant data of the overall thickness of the chip after secondary thinning of different thicknesses in step 4 of this embodiment are listed in Table 1. It can be seen that the thinner the actual size of the product (the more grinding, the greater the degree of thinning), the yield rate will be The lower it is, the yield rate can exceed 75%.
- the actual size thickness of the final product has a great relationship with the thickness accuracy of the second colloid, resulting in a certain difference in the thickness of the final product.
- Step 1 Flip-chip IC uses a single die from Taiwan's Anapex FC IC. After the manufacturer completes the semiconductor integrated circuit, metal circuit and protection processes on the silicon wafer, in order to reduce the thickness of the IC, Wafer grinding silicon substrate material to reduce the wafer thickness to 150 ⁇ m;
- Step 2 The manufacturer cuts the thinned flip-chip chips into single flip-chip ICs (length and width are 540x590um;
- Step 3 Arrange the single flip-chip IC matrix on the carrier board (the gap between flip-chip ICs is 0.2 ⁇ 1mm.
- the carrier board is composed of a flat hard substrate and double-sided tape.
- the hard substrate is a metal sheet.
- the thickness of the hard substrate is 0.5mm
- one side of the double-sided tape is attached to the hard substrate, and the other side is attached to the electrodes of the flip-chip IC arranged in a matrix;
- Step 4 Use the spot injection method to fill the gaps between the matrix-arranged grains with the first colloid, so that the first colloid
- the colloid coats the periphery of the crystal grain. Sometimes too much dosing causes the fifth surface (the top surface) to be also coated with colloid. This does not matter and does not affect the subsequent process;
- Step 6 Cover the top surface of the flip chip with a layer of second colloid for final packaging.
- the thickness of the second colloid is 20 ⁇ m;
- Step 7 The material cutting is completed, that is, the thin flip-chip IC package is completed.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Led Device Packages (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
一种超薄型芯片制造工艺与封装方法,包括如下步骤:步骤1.将倒装芯片晶圆初步研磨衬底层;步骤2.将单颗倒装芯片以阵列形式排列于载板上;载板包括一个硬质基板及贴合在硬质基板一侧的双面胶层;步骤3.以第一胶体填满倒装芯片阵列中芯片之间的空隙;步骤4.将倒装芯片顶面研磨二次减薄;步骤5.倒装芯片正上方铺盖一层第二胶体,完成最后封装;步骤6.切割得到封装好的单颗倒装芯片。采用本发明所述的薄型芯片制造封装方法,通过改变工艺流程,增加载板和弹性胶层,晶粒可增大减薄力度,实现晶粒封装后的厚度小于100微米的芯片,最低可达30微米。
Description
本发明属于芯片技术领域,具体涉及一种超薄型芯片制造封装方法。
目前LED芯片最常见的是正装结构,还有垂直结构和倒装结构。正装结构由于p,n电极在LED同一侧,容易出现电流拥挤现象,而且热阻较高,而垂直结构则可以很好的解决这两个问题,可以达到很高的电流密度和均匀度。这也导致垂直结构通常用于大功率LED应用领域,而正装技术一般应用于中小功率LED。
倒装结构技术也可以细分为两类,一类是在蓝宝石芯片基础上倒装,蓝宝石衬底保留,利于散热,但是电流密度提升并不明显;另一类是倒装结构并剥离了衬底材料,可以大幅度提升电流密度。
为了避免正装芯片中因电极挤占发光面积从而影响发光效率,芯片研发人员设计了倒装结构,即把正装芯片倒置,由于衬底被剥去而芯片材料透明,可使发光层激发出的光直接从电极的另一面发出,同时,针对倒装设计出方便LED封装厂焊线的结构,从而,整个芯片称为倒装芯片(Flip Chip),该结构在大功率芯片较多用到。
倒装芯片具有以下优点:一是没有通过蓝宝石散热,可通大电流使用;二是尺寸可以做到更小,光学更容易匹配;三是散热功能的提升,使芯片的寿命得到了提升;四是抗静电能力的提升;五是为后续封装工艺发展打下基础。
随着光电组件与集成电路技术发展,薄型化晶圆的需求,对晶圆越薄减
薄加工的良率越低的限制,半导体晶圆的减薄后常见的厚度约150~250μm,小于80μm的厚度即面临量产可行的问题,更薄的厚度将会增加成本以及良率的损失,导致目前并没有相关产品在市场上。
晶圆减薄的困难点在于本身为硬脆材料,晶圆面积尺寸越大研磨抛光过程稳定性越低且破片率越高,因而导致这些半导体的封装厚度受到局限。由于硅晶圆比蓝宝石更易加工,用本发明所述制造工艺与封装方法对硅芯片进行封装可以达到30微米的更低厚度。
发明内容
为克服现有技术存在的缺陷,本发明公开了一种超薄型芯片制造封装方法。
本发明所述薄型芯片制造封装方法,包括如下步骤:
步骤1.将倒装芯片晶圆初步研磨衬底层,使倒装芯片晶圆厚度初步减薄至80~150μm,将初步减薄后的晶圆经过切割为单颗倒装芯片;
步骤2.将单颗倒装芯片以阵列形式排列于载板上;载板包括一个硬质基板及贴合在硬质基板一侧的双面胶层,单颗倒装芯片排列在双面胶层上并被胶层粘接固定,电极面贴向载板;
步骤3.以第一胶体填满倒装芯片阵列中芯片之间的空隙,使第一胶体包覆倒装芯片四周,或较厚第一胶体五面包覆;
步骤4.胶体包覆固化后将倒装芯片顶面研磨二次减薄,二次减薄得到的二次减薄芯片整体厚度降低至20μm~70μm;
步骤5.倒装芯片正上方铺盖一层第二胶体,完成最后封装,第二胶体的厚度为20~80μm,封装后的倒装芯片厚度约40~100μm;
步骤6.切割得到封装好的单颗倒装芯片。
优选的,步骤1的初步减薄采用CMP技术减薄厚度。
优选的,所述步骤2利用固晶机设备进行。
优选的,所述第一胶体和/或第二胶体为硅胶。
优选的,步骤3中以第一胶体包覆倒装芯片的具体方法为点注法或用预制模具盖住倒装芯片后灌注第一胶体。
优选的,所述步骤4中二次减薄采用的研磨粉材料为碳化硅、碳化硼、立方氮化硼、钻石微粉中的任意一种。
采用本发明所述的薄型芯片制造封装方法,通过改变工艺流程,增加载板和弹性胶层,晶粒可增大减薄力度,对于蓝宝石衬底芯片,可实现晶粒封装后的厚度小于100微米的芯片(可达40微米)。利用本发明所述封装方法对IC半导体硅晶圆进行封装。由于硅晶圆比蓝宝石更易加工,用本发明所述封装方法进行封装可以达到30微米的更低厚度。
图1为本发明一种具体实施方式示意图;
图中附图标记名称为:1-倒装式芯片晶圆,2-单颗倒装芯片,3-双面胶层,4-基板,5-第一胶体,6-二次减薄芯片,7-第二胶体。
下面对本发明的具体实施方式作进一步的详细说明。
具体实施方式1,以倒装式LED芯片为例:
倒装结构尤其适用于LED芯片,以LED芯片为例,本发明所述薄型芯片制造封装方法,包括如下步骤:
步骤1.将倒装式LED芯片晶圆(Flip chip LED或FC LED),初步研磨衬底层,例如蓝宝石衬底层,使倒装式LED芯片晶圆厚度初步减薄至80~150um,将初步减薄后的晶圆经过切割为单颗倒装芯片;
所谓晶圆是集成排列有大量单颗倒装芯片的圆形芯片;切割工具可以采
用芯片切割机进行;初步减薄可采用常规CMP(Chemical Mechanical Polishing,化学机械抛光)技术减薄厚度。上述步骤从厂家新世纪光电科技有限公司(中国台湾)制作完成,购入倒装式LED芯片,其长和宽分别为200×500um的单颗晶粒(厚度为100um)。
步骤2.将单颗倒装芯片以阵列形式排列于载板上,其中单颗芯片的间距可取0.2-0.5毫米,电极面贴向载板;步骤2通常利用固晶机设备来进行。
载板包括一个硬质基板及贴合在硬质基板一侧的双面胶层,硬质基板厚度0.6mm,双面打磨光滑的金属片,双面胶功能为一面可粘着固定单颗芯片的电极面,另一面可以粘着于固定于硬质基板,最好选择两面黏着度不一样的双面胶,一面黏着度较高,一面黏着度较低。黏着度较低的面贴在硬质基板,黏着度较高的面用于固定单颗芯片。
单颗倒装芯片排列在双面胶层上并被胶层粘接固定;
步骤3.以第一胶体填满倒装芯片阵列中芯片之间的空隙,使第一胶体包覆倒装芯片四周,如果第一胶体量较大,可能对倒装芯片五面包覆;但不影响后续的制程,顶部的第一胶体可以在后续步骤中研磨去除。
第一胶体可以选择硅胶,其功能主要有:(1)固定倒装芯片,研磨时可以避免蓝宝石位移;(2)减震:避免研磨时晶粒崩裂或产生缺陷;(3)可根据发光需求在第一胶体混入滤光介质,调整LED芯片光色或亮度等。
步骤3可以利用点注法:利用器具以挤出作胶体为点注来注入胶体,也可用机器设备来进行挤出点注;也可以用预制模具盖住倒装芯片后进行灌注。
步骤4.胶体包覆固化后将倒装芯片顶面研磨二次减薄,二次减薄得到的二次减薄芯片整体厚度降低至20um~70um,研磨液中的研磨粉材料为碳化硅(SiC)、碳化硼(B4C)、立方氮化硼(CBN)、钻石微粉等。
步骤5.倒装芯片正上方铺盖一层第二胶体,完成最后封装,第二胶体的厚度为20~80um,封装后的倒装芯片厚度约40~100um;
此处第二胶体可以和第一种胶体可以选择相同材料,也可以是其它胶体,不同光学性能的两种胶体可以实现更多样化的发光组件。
步骤6.切割得到封装好的单颗倒装芯片;
切割第一胶体和第二胶体后,将单颗倒装芯片从硬质基板剥离,得到单颗倒装芯片;
最后可采用排片机将独立的倒装芯片在SPV224蓝膜上排列整齐即完成封装,一般来说电极都是贴在蓝膜上,或利用自动贴片机将独立的倒装芯片装在芯片卷盘的载卷上,而硬质基板基本可以重复直到有缺陷或损毁,或是单次使用后即可抛弃。
具体实施方式2,以倒装式IC芯片为例:
1.倒装式IC(Flip chip IC),于硅晶圆完成半导体集成电路、金属线路及保护制程后,为了降低IC的厚度会将晶圆研磨硅基底材料,使其晶圆厚度减薄至50~250um;
2.减薄后的倒装芯片经过切割为单颗的FC IC(长度和宽度的范围在100um~1000um);上述步骤已于IC厂制作完成,本案使用中国台湾安沛科技公司(Anapex)FC IC的单颗晶粒,长宽540x590um,厚度150um。
3.将单颗的FC IC矩阵排列于载板(FC IC之间隙0.2~1mm,其载板由一平整的硬质基板及双面胶所组成,硬质基板可为金属片或是玻璃片,硬质基板厚度0.3~1mm,双面胶其一面贴合硬质基板,另一面贴合矩阵排列之FC IC的电极;
4.使用第一胶体填满矩阵排列晶粒之间的空隙,使第一胶体包覆晶粒四周;
5.胶体包覆且固化后,将倒装芯片顶面研磨减薄至10~50um;
6.倒装芯片顶面上方再铺盖一层第二胶体进行最后的封装,第二胶体厚度可为20~50um;
7.材料切割完成,即完成可小于100um薄型FC IC封装。
具体实施例3:以普通LED芯片为例:
步骤1.从厂家新世纪光电科技有限公司(中国台湾)购入倒装式LED芯片晶圆,厂家已初步研磨蓝宝石衬底层,使倒装式LED芯片晶圆厚度初步减薄至100μm,并将初步减薄后的晶圆经过切割为单颗倒装芯片;其长和宽分别为200×500um的单颗晶粒。
步骤2.将单颗倒装芯片以阵列形式排列于载板上,其中单颗芯片的间距取0.2-0.5毫米,电极面贴向载板;步骤2利用由深圳新益昌科技股份有限公司LED固晶机生产的倒装LED固晶机来进行。
载板包括一个硬质基板及贴合在硬质基板一侧的双面胶层,硬质基板厚度0.8mm的玻璃片,双面胶功能为一面可粘着固定单颗芯片的电极面,另一面可以粘着于固定于硬质基板,选择两面黏着度不一样的双面胶,一面黏着度较高,一面黏着度较低。黏着度较低的面贴在硬质基板,黏着度较高的面用于固定单颗芯片。
单颗倒装芯片排列在双面胶层上并被胶层粘接固定;
步骤3.以第一胶体为硅胶填满倒装芯片阵列中芯片之间的空隙,使第一胶体包覆倒装芯片四周,如果第一胶体量较大,可能对倒装芯片五面包覆;但不影响后续的制程,顶部的第一胶体可以在后续步骤中研磨去除。
第一胶体为硅胶,其功能主要有:(1)固定倒装芯片,研磨时可以避免蓝宝石位移;(2)减震:避免研磨时晶粒崩裂或产生缺陷;(3)可根据发光需求在第一胶体混入滤光介质,调整LED芯片光色或亮度等。
步骤3利用点注法:利用注射器具以挤出作胶体为点注来注入胶体。
步骤4.胶体包覆固化后将倒装芯片顶面以全自动晶圆研磨机(Wafer Grinding,GDM300衡鹏)研磨二次减薄,将不同试样分别经二次减薄得到的二次减薄芯片整体厚度分别降低至20μm、40μm、70μm,研磨液中的研磨
粉材料为碳化硅(SiC)。
步骤5.倒装芯片正上方铺盖一层第二胶体(硅胶),完成最后封装,第二胶体的厚度为20μm;
步骤6.切割得到封装好的单颗倒装芯片;
切割第一胶体和第二胶体后,将单颗倒装芯片从硬质基板剥离,得到单颗倒装芯片;
最后可采用排片机将独立的倒装芯片在SPV224蓝膜上排列整齐即完成封装,一般来说电极都是贴在蓝膜上,或利用自动贴片机将独立的倒装芯片装在芯片卷盘的载卷上,而硬质基板基本可以重复直到有缺陷或损毁,或是单次使用后即可抛弃。
本实施例步骤4中二次减薄不同厚度后芯片整体厚度的相关数据列于表1,可以得知,产品最实际尺寸厚度愈薄(研磨愈多,减薄程度愈多)其良率就愈低,但是其良率都能超过75%以上。最终产品实际尺寸厚度与第二胶体的厚度精度有很大关系,导致其最终产品的厚度会有一定的差异性。
具体实施例4:以普通IC芯片为例:
步骤1.倒装式IC,使用中国台湾安沛科技公司(Anapex)FC IC的单颗晶粒,厂家于硅晶圆完成半导体集成电路、金属线路及保护制程后,为了降低IC的厚度会将晶圆研磨硅衬底材料,使其晶圆厚度减薄至150μm;
步骤2.厂商将减薄后的倒装式芯片经过切割为单颗的倒装式IC(长度和宽度为540x590um;
步骤3.将单颗的倒装式IC矩阵排列于载板(倒装式IC之间隙0.2~1mm,其载板由一平整的硬质基板及双面胶所组成,硬质基板为金属片,硬质基板厚度0.5mm,双面胶其一面贴合硬质基板,另一面贴合矩阵排列的倒装式IC的电极;
步骤4.使用点注法将第一胶体填满矩阵排列晶粒之间的空隙,使第一
胶体包覆晶粒四周,有时点注量过多导致第五面(最上方的面)也被胶体包覆,发生这种情况没有关系,并不影响后续的制程;
步骤5.胶体包覆且固化后,将倒装芯片顶面以全自动晶圆研磨机(Wafer Grinding,GDM300衡鹏)分别研磨二次减薄至10μm、30μm、60μm;研磨液中的研磨粉材料为钻石微粉。
步骤6.倒装芯片顶面上方再铺盖一层第二胶体进行最后的封装,第二胶体厚度为20μm;
步骤7.材料切割完成,即完成薄型倒装式IC封装。
本实施例步骤5中二次减薄不同厚度后的相关数据列于表1,可以得知,产品最实际尺寸厚度愈薄(研磨愈多,减薄程度愈多)其良率就愈低,但是其良率都能超过70%以上。最终产品实际尺寸厚度与第二胶体的厚度精度有很大关系,导致其最终产品的厚度会有一定的差异性。
表一
采用本发明所述的薄型芯片制造封装方法,通过改变工艺流程,增加载板和弹性胶层,晶粒可增大减薄力度,实现晶粒封装后的厚度小于100微米的芯片。
前文所述的为本发明的各个优选实施例,各个优选实施例中的优选实施方式如果不是明显自相矛盾或以某一优选实施方式为前提,各个优选实施方
式都可以任意叠加组合使用,所述实施例以及实施例中的具体参数仅是为了清楚表述发明人的发明验证过程,并非用以限制本发明的专利保护范围,本发明的专利保护范围仍然以其权利要求书为准,凡是运用本发明的说明书及附图内容所作的等同结构变化,同理均应包含在本发明的保护范围内。
Claims (7)
- 一种超薄型芯片制造封装方法,包括如下步骤:步骤1.将倒装芯片晶圆初步研磨衬底层,使倒装芯片晶圆厚度初步减薄至80~150μm,将初步减薄后的晶圆经过切割为单颗倒装芯片;步骤2.将单颗倒装芯片以阵列形式排列于载板上;载板包括一个硬质基板及贴合在硬质基板一侧的双面胶层,单颗倒装芯片排列在双面胶层上并被胶层粘接固定,电极面贴向载板;步骤3.以第一胶体填满倒装芯片阵列中芯片之间的空隙,使第一胶体包覆倒装芯片四周,或较厚第一胶体五面包覆;步骤4.胶体包覆固化后将倒装芯片顶面研磨二次减薄,二次减薄得到的二次减薄芯片整体厚度降低至20μm~70μm;步骤5.倒装芯片正上方铺盖一层第二胶体,完成最后封装,第二胶体的厚度为20~80μm,封装后的倒装芯片厚度约40~100μm;步骤6.切割得到封装好的单颗倒装芯片。
- 如权利要求1所述的超薄型芯片制造封装方法,其特征在于,步骤1的初步减薄采用CMP技术减薄厚度。
- 如权利要求1所述的超薄型芯片制造封装方法,其特征在于,所述步骤2利用固晶机设备进行。
- 如权利要求1所述的超薄型芯片制造封装方法,其特征在于,所述第一胶体和/或第二胶体为硅胶。
- 如权利要求1所述的超薄型芯片制造封装方法,其特征在于,步骤3中以第一胶体包覆倒装芯片的具体方法为点注法或用预制模具盖住倒装芯片后灌注第一胶体。
- 如权利要求1所述的超薄型芯片制造封装方法,其特征在于,所述步骤4中二次减薄采用的研磨粉材料为碳化硅、碳化硼、立方氮化硼、钻石微粉中的任意一种。
- 如权利要求1所述的超薄型芯片制造封装方法,其特征在于,所述倒装芯片为LED芯片或IC芯片。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202210695064.2A CN114975734A (zh) | 2022-06-20 | 2022-06-20 | 一种超薄型芯片制造封装方法 |
CN202210695064.2 | 2022-06-20 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2023246612A1 true WO2023246612A1 (zh) | 2023-12-28 |
Family
ID=82963935
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2023/100400 WO2023246612A1 (zh) | 2022-06-20 | 2023-06-15 | 一种超薄型芯片制造封装方法 |
Country Status (3)
Country | Link |
---|---|
CN (1) | CN114975734A (zh) |
TW (1) | TW202403904A (zh) |
WO (1) | WO2023246612A1 (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114975734A (zh) * | 2022-06-20 | 2022-08-30 | 四川轻化工大学 | 一种超薄型芯片制造封装方法 |
CN115881862A (zh) * | 2023-02-16 | 2023-03-31 | 江西兆驰半导体有限公司 | 一种mini LED芯片减薄方法及mini LED |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070202623A1 (en) * | 2005-10-28 | 2007-08-30 | Gelcore Llc | Wafer level package for very small footprint and low profile white LED devices |
CN104037132A (zh) * | 2014-06-25 | 2014-09-10 | 山东华芯半导体有限公司 | 一种封装方法 |
CN104979447A (zh) * | 2015-07-16 | 2015-10-14 | 华天科技(昆山)电子有限公司 | 倒装led封装结构及制作方法 |
CN109972204A (zh) * | 2017-12-28 | 2019-07-05 | 济南晶正电子科技有限公司 | 超薄超平晶片和制备该超薄超平晶片的方法 |
CN114975734A (zh) * | 2022-06-20 | 2022-08-30 | 四川轻化工大学 | 一种超薄型芯片制造封装方法 |
-
2022
- 2022-06-20 CN CN202210695064.2A patent/CN114975734A/zh active Pending
-
2023
- 2023-06-14 TW TW112122278A patent/TW202403904A/zh unknown
- 2023-06-15 WO PCT/CN2023/100400 patent/WO2023246612A1/zh unknown
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070202623A1 (en) * | 2005-10-28 | 2007-08-30 | Gelcore Llc | Wafer level package for very small footprint and low profile white LED devices |
CN104037132A (zh) * | 2014-06-25 | 2014-09-10 | 山东华芯半导体有限公司 | 一种封装方法 |
CN104979447A (zh) * | 2015-07-16 | 2015-10-14 | 华天科技(昆山)电子有限公司 | 倒装led封装结构及制作方法 |
CN109972204A (zh) * | 2017-12-28 | 2019-07-05 | 济南晶正电子科技有限公司 | 超薄超平晶片和制备该超薄超平晶片的方法 |
CN114975734A (zh) * | 2022-06-20 | 2022-08-30 | 四川轻化工大学 | 一种超薄型芯片制造封装方法 |
Also Published As
Publication number | Publication date |
---|---|
TW202403904A (zh) | 2024-01-16 |
CN114975734A (zh) | 2022-08-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2023246612A1 (zh) | 一种超薄型芯片制造封装方法 | |
WO2016150069A1 (zh) | 发光器件的芯片级封装方法及结构 | |
US7476565B2 (en) | Method for forming filling paste structure of WL package | |
KR100517075B1 (ko) | 반도체 소자 제조 방법 | |
JP5851888B2 (ja) | 半導体装置の製造方法および半導体装置 | |
TWI492422B (zh) | 具有螢光粉層之發光二極體晶片的製作方法 | |
JP2013251417A (ja) | 発光装置 | |
JP2012039013A (ja) | 発光装置の製造方法 | |
CN109545910A (zh) | 一种具备高热稳定性的直接白光led芯片制造方法 | |
CN105895540A (zh) | 晶圆背面印胶的封装方法 | |
JP2018061027A (ja) | 発光装置の製造方法 | |
CN108281531A (zh) | 一种csp led封装方法 | |
CN107579045A (zh) | 晶圆切割方法 | |
WO2023142203A1 (zh) | 一种彩色Micro LED显示芯片模组的制造方法 | |
CN105161436B (zh) | 倒装芯片的封装方法 | |
TW201042720A (en) | A wafer-level CSP processing method and thereof a thin-chip SMT-type light emitting diode | |
JP2002299546A (ja) | チップ状電子部品及びその製造方法、並びにその製造に用いる疑似ウエーハ及びその製造方法 | |
CN100392810C (zh) | 蓝宝石衬底减薄工序中的粘片方法 | |
CN104659187B (zh) | 一种垂直结构的白光led芯片及其制造方法 | |
CN114284400A (zh) | 汽车前大灯制备方法 | |
CN206774575U (zh) | 无衬底芯片封装led | |
TWI712185B (zh) | 發光裝置、應用其的背光模組、光源模組及其製備方法 | |
JP6215769B2 (ja) | ウェハーレベル光半導体デバイス用部材の製造方法、及び光半導体デバイスの製造方法 | |
CN206322685U (zh) | 一种GaAs基LED芯片减薄工艺中的贴片工装 | |
TWI404189B (zh) | 複晶式發光二極體元件及其製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 23826261 Country of ref document: EP Kind code of ref document: A1 |