WO2023246608A1 - 电路板及终端 - Google Patents

电路板及终端 Download PDF

Info

Publication number
WO2023246608A1
WO2023246608A1 PCT/CN2023/100346 CN2023100346W WO2023246608A1 WO 2023246608 A1 WO2023246608 A1 WO 2023246608A1 CN 2023100346 W CN2023100346 W CN 2023100346W WO 2023246608 A1 WO2023246608 A1 WO 2023246608A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit board
interference
electrical signal
substrate
wiring layer
Prior art date
Application number
PCT/CN2023/100346
Other languages
English (en)
French (fr)
Inventor
周俭军
狄伟
王天鹏
舒余飞
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2023246608A1 publication Critical patent/WO2023246608A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details

Definitions

  • the present application relates to the field of power electronics technology, and in particular, to a circuit board and a terminal using the circuit board.
  • Terminal products such as mobile phones, computers, etc.
  • Terminal products are gradually developing towards miniaturization, thinness, and diversification of functions, which requires higher and higher stability and accuracy requirements for each hardware module in the terminal products.
  • the camera module establishes electrical connections with other functional modules in the terminal product through multiple ports of the electrical connector.
  • the working signal in the camera module is a high-frequency signal.
  • the port used to transmit high-frequency signals in the electrical connector has high impedance to ground and weak anti-interference ability, which can easily lead to camera module screen blur.
  • a first aspect of this application provides a circuit board, including:
  • a ground layer located on one side of the substrate, the ground layer is used to provide a reference potential for the second electrical signal
  • An anti-interference structure is used to form a parasitic capacitance to provide a reference potential for the first electrical signal.
  • the above-mentioned circuit board includes a wiring layer.
  • the wiring layer is used to transmit a first electrical signal and a second electrical signal.
  • the frequency of the first electrical signal is higher than that of the second electrical signal.
  • the ground layer provides a reference potential for the second electrical signal.
  • the above-mentioned circuit board is provided with an anti-interference structure, and the anti-interference structure provides a reference potential for the first electrical signal by forming a parasitic capacitance, which is conducive to reducing the ground impedance of the first electrical signal, thereby increasing the transmission frequency on the electrical connector. Higher immunity to first electrical signals at the port. Therefore, the above-mentioned circuit board solves the problem of weak anti-interference ability of the electrical connector without changing the structure of the electrical connector. At the same time, it can avoid increasing the physical size of the electrical connector, making the application of the electrical connector When used in terminals, it meets the requirements for miniaturization and thinness of terminals.
  • the anti-interference structure and the ground layer form a parasitic capacitance to provide the first electrical signal with reference potential.
  • the anti-interference structure is located on the surface of the substrate on which the wiring layer is formed.
  • the wiring layer and the anti-interference structure can be formed in the same process.
  • the anti-interference structure is not used to transmit the second electrical signal, and there is no need to consider shortening the transmission path of the second electrical signal.
  • the position and structural design of the anti-interference structure are more flexible.
  • the anti-interference structure includes a first anti-interference part and a second anti-interference part that are electrically insulated from each other.
  • the first anti-interference part is electrically connected to the wiring layer, and the second anti-interference part Grounded, the first anti-interference part and the second anti-interference part have opposite areas to form the parasitic capacitance.
  • the anti-interference structure and the wiring layer form a parasitic capacitance to provide a reference potential for the first electrical signal.
  • a ground layer located on one side of the substrate, the ground layer is used to provide a reference potential for the second electrical signal
  • the above-mentioned terminal also includes a grounded conductive structure, and an anti-interference structure is provided in the first circuit board, so that the anti-interference structure and the conductive structure provide a reference potential for the first electrical signal by forming a parasitic capacitance, which is beneficial to reducing the first electrical signal.
  • the ground impedance of the signal is thereby improved at the port of the electrical connector used to transmit the first electrical signal with a higher frequency. Therefore, the above-mentioned terminal solves the problem of weak anti-interference ability of the electrical connector without changing the structure of the electrical connector. At the same time, it can avoid increasing the physical size of the electrical connector, making the terminal comply with miniaturization and Thin and light requirements.
  • Figure 4 is a schematic structural diagram of the first circuit board in the terminal according to Embodiment 1 of the present application.
  • Figure 5 is a schematic diagram of the connection relationship between the first circuit board, the second circuit board and the electrical connector without an anti-interference structure.
  • Figure 7 shows the circuit structure of the first circuit board, the second circuit board and the electrical connector when transmitting low-frequency signals in Embodiment 1 of the present application.
  • FIG. 9 is a graph showing a ratio and the change of impedance over time in the terminal according to Embodiment 1 of the present application.
  • Figure 10 is a schematic structural diagram of the first circuit board in the terminal according to Embodiment 2 of the present application.
  • FIG. 11 is a schematic structural diagram of the first circuit board in the terminal according to Embodiment 3 of the present application.
  • Figure 12 is a schematic structural diagram of the first circuit board in the terminal according to Embodiment 4 of the present application.
  • Figure 13 is a schematic structural diagram of the first circuit board in the terminal according to Embodiment 5 of the present application.
  • the terminal 1 includes a first circuit board 10 , a second circuit board 20 and an electrical connector 30 .
  • the electrical connector 30 includes a first connection part 31 and a second connection part 32 .
  • the first connection part 31 is electrically connected to the first circuit board 10
  • the second connection part 32 is electrically connected to the second circuit board 20
  • the first connection part 31 and the second connection part 32 are engaged (or plugged) with each other to establish
  • the electrical connection between the first circuit board 10 and the second circuit board 20 enables electrical signals to be transmitted between the first circuit board 10 and the second circuit board 20 .
  • the first circuit board 10 is the main board of the terminal 1
  • the second circuit board 20 is the sub-board of the functional module (such as the camera module) in the terminal 1
  • the first connection part 31 is the female seat of the electrical connector 30
  • the second connection part 32 is the male socket of the electrical connector 30 .
  • the first circuit board 10 can be a secondary board
  • the second circuit board 20 can be a main board
  • the first connecting portion 31 can be a male socket
  • the second connecting portion 32 can be a female socket.
  • the first connection part 31 is fixed on the first circuit board 10 by welding: a plurality of soldering pads (not shown) are reserved at the transmission port (not shown) on the first circuit board 10 to The signal ports on the first connection portion 31 of the electrical connector 30 are soldered to the above-mentioned pads in a one-to-one correspondence.
  • the second connection part 32 is fixed on the second circuit board 20 by welding: a plurality of pads (not shown) are reserved at the transmission port (not shown) on the second circuit board 20 so that the electrical The signal ports on the second connection part 32 of the connector 30 are soldered in one-to-one correspondence with the above-mentioned pads.
  • This application does not limit the fixing method between the electrical connector 30 and the first circuit board 10 and the second circuit board 20 .
  • the electrical connector 30 includes multiple signal ports.
  • FIG. 3 is a schematic distribution diagram of each signal port (numbered 1-28) of the electrical connector 30 in this embodiment.
  • the electrical connector 30 of this embodiment includes multiple types of signal ports, and different types of signal ports transmit different signal types. For example, signal ports 25-28 are used to transmit power signals, signal ports 3-8, 10, 12, and 14 are used to transmit high-frequency signals, signal ports 11, 13, 19, 21, and 24 are used to transmit low-frequency signals, and signal ports 1-2, 9, 15-16, 22-23 are used to connect to the reference ground.
  • the number of signal ports connected to the reference ground in the electrical connector 30 is limited. For high-frequency signals, it lacks a good signal reference and has a large impedance to the ground, so the anti-interference ability is weak, which makes the electrical connector 30 Radio frequency signal interference is prone to occur at the signal port used for transmitting high-frequency signals, that is, the signal port used for transmitting high-frequency signals of the electrical connector 30 has weak anti-interference capability.
  • the radio frequency signal interference is likely to affect the second circuit board 20 electrically connected to the electrical connector 30, thereby affecting the functional implementation of the functional module connected to the second circuit board 20 (for example, causing the camera module to have a blurry screen problem).
  • the anti-interference structures on the first circuit board 10 and the second circuit board 20 are similar.
  • the anti-interference structure on the first circuit board 10 will be used as an example below.
  • the first circuit board 10 is a printed circuit board, and the substrate 11 is a sheet-shaped insulating material.
  • the wiring layer 12 is formed with a conductive pattern.
  • the conductive pattern includes a plurality of wirings (only one wiring 121 is shown in FIG. 4). Each wiring is used to transmit electrical signals, and some of the wirings are used to transmit the first electrical signal. , part of the wiring is used to transmit the second electrical signal.
  • the first electrical signal includes a high-frequency signal
  • the second electrical signal includes a low-frequency signal.
  • the trace 121 shown in FIG. 4 is used to transmit the second electrical signal, that is, to transmit the power signal or the low-frequency signal.
  • the ground layer 13 is a sheet-shaped conductive structure with substantially the same potential everywhere, and is used to provide a reference potential (ie, reference ground) for the second electrical signal transmitted by the wiring layer 12 .
  • the state of the parasitic capacitance C is equivalent to an open circuit. This makes the circuit structure of the first circuit board 10 and the second circuit board 20 when the anti-interference structure 14 is provided and when the anti-interference structure 14 is not provided. Then the transmission path of low-frequency signals will not be affected.
  • the state of the parasitic capacitance C is equivalent to a short circuit, and the anti-interference structure 14 is grounded. The high-frequency signal can use the nearest anti-interference structure 14 as the reference ground without reference to the farther one.
  • the abscissa can also reflect the distance of the electrical signal transmission, so that the location of the impedance mutation can be calculated based on the value of the abscissa, thereby confirming which location in the terminal has the impedance. Larger, lower immunity.
  • the locations where sudden impedance increases occur are at the signal ports where the connector transmits high-frequency signals. It can be clearly seen from Figure 9 that the impedance of the signal port of the connector of this embodiment for transmitting high-frequency signals is lower than the impedance of the signal port of the connector for transmitting high-frequency signals in the comparative example.
  • the connector of this embodiment transmits
  • the signal port of the high-frequency signal has higher noise immunity than the signal port of the connector in the comparative example that transmits the high-frequency signal. Therefore, the terminal 1, the first circuit board 10 and the second circuit board 20 of this embodiment are beneficial to improving the immunity of the signal port of the electrical connector 30 that transmits high-frequency signals.
  • the first circuit board 10 is a multi-layer printed circuit board. Compared with the structure illustrated in Figure 4, the first circuit board 10 of this embodiment can also include a larger number of substrates 11, wiring layers 12 and ground layers 13. In Figure 4, the substrate 11, wiring layers 12 and ground layers are The structural relationships between layers 13 are only examples. When the first circuit board 10 includes multiple substrates 11 , wiring layers 12 and ground layers 13 , a substrate 11 is provided between adjacent wiring layers 12 and between adjacent wiring layers 12 and ground layers 13 . Electrical connections can be established between the wiring layers 12 on both sides of the substrate 11 or between the wiring layers 12 and the ground layer 13 by opening through holes on the substrate 11 .
  • the electrical connector 30 is a board-to-aboard (BTB) connector.
  • the electrical connector 30 may also be a zero insertion force (Zero Insertion Force, ZIF) connector, a Type C connector, etc.
  • ZIF Zero Insertion Force
  • the main difference between the terminal provided in this embodiment and the terminal 1 in Embodiment 1 lies in the location of the anti-interference structure.
  • the shape and structure of the anti-interference structure 24 in this embodiment is basically the same as that of the anti-interference structure 14 in Embodiment 1.
  • the main difference lies in that the anti-interference structure 24 in this embodiment is electrically connected to the end of the trace 121 .
  • the connecting wire 40 One end is directly electrically connected to the trace 121 and extends along the through hole 111 to the signal transmission port of the first circuit board 10 .
  • the power signal or low-frequency signal is transmitted to the transmission port through the wiring 121 and the connecting wire 40 to be transmitted to the electrical connector 30 .
  • the power signal or low-frequency signal does not pass through the anti-interference structure 14 .
  • the anti-interference structure 14 has a facing area with the ground layer 13 and can form a parasitic capacitance with the ground layer 13 .
  • the layout design of the traces used to transmit electrical signals needs to meet the requirement of the shortest path.
  • the power signal or low-frequency signal that is, the electrical signal
  • the anti-interference structure 24 The position and shape of 24 have a high degree of design freedom.
  • this embodiment can achieve all the beneficial effects as described in Embodiment 1. On this basis, it is also beneficial to improve the design freedom of the position and shape of the anti-interference structure 24 .
  • the first circuit board 10 includes a stacked first substrate 310 and a second substrate 320 .
  • the second substrate 320 is located between the first substrate 310 and the ground layer 13 .
  • the wiring layer 12 is located on the surface of the first substrate 310 close to the second substrate 320
  • the anti-interference structure 34 is located on the surface of the second substrate 320 away from the first substrate 310 . That is, in this embodiment, the anti-interference structure 34 and the wiring layer 12 are respectively located on the surfaces of different substrates. In other words, in this embodiment, the anti-interference structure 34 and the wiring layer 12 are arranged in different layers.
  • the wiring 121 on the first substrate 310 can electrically connect to the anti-interference structure 34 on the second substrate 320 through the connecting wire 50 and the through hole 311. connect.
  • the trace 121 can be electrically connected to the signal transmission port of the first circuit board 10 through the second through hole 321 and the connecting wire 40 .
  • the power signal and low-frequency signal are transmitted to the transmission port through the wiring 121 and the connecting wire 40, and the anti-interference structure 34 is not used to transmit the power signal or low-frequency signal.
  • This embodiment can achieve all the beneficial effects described in Embodiment 1 and Embodiment 2. On this basis, in this embodiment, since the anti-interference structure 34 and the wiring layer 12 are disposed on different substrate surfaces, it is beneficial to release the area of the wiring layer 12 so that the wiring layer 12 can arrange a greater number of traces. Wire.
  • the main difference between the terminal provided in this embodiment and the terminals in Embodiments 1 to 3 lies in the position and structure of the anti-interference structure.
  • the anti-interference structure 44 is located on the surface of the substrate 11 on which the wiring layer 12 is formed, and is electrically connected to the wiring 121 .
  • the anti-interference structure 44 includes a first anti-interference part 441 and a second anti-interference part 442 .
  • the first anti-interference part 441 is electrically connected to the trace 121, and the second anti-interference part 442 is grounded.
  • the first noise immunity part 441 is electrically insulated from the second noise immunity part 442 .
  • the first anti-interference part 441 and the second anti-interference part 442 are comb-shaped.
  • the first anti-interference part 441 includes a main body part 4411 and a plurality of elongated parallel extending parts 4412 protruding from one side of the main body part.
  • the second anti-interference part 442 includes a main body part 4421 and a plurality of elongated parallel extension parts 4422 protruding from one side of the main body part 4421.
  • the plurality of extension portions 4412 and the plurality of extension portions 4422 are arranged at staggered intervals in sequence.
  • the portion 442 has a facing area and can form a parasitic capacitance C.
  • the anti-interference structure 44 in this embodiment can also be applied to the position of the anti-interference structure described in Embodiment 2 and Embodiment 3. That is, the anti-interference structure 44 in this embodiment can be used to transmit power signals or low-frequency signals together with the traces 121 as described in the first embodiment; the anti-interference structure 44 can also be connected to the traces as described in the second embodiment. The end of the line 121 does not participate in transmitting power signals or low-frequency signals; the anti-interference structure 44 can also be located on a different substrate surface from the wiring layer 12 as described in Embodiment 3.
  • This embodiment can achieve all the beneficial effects described in Embodiments 1-3.
  • the main difference between the terminal in this embodiment and the terminals in Embodiments 1 to 4 lies in the position and structure of the anti-interference structure.
  • the first circuit board 10 includes a substrate 11 , a wiring layer 12 , a buried capacitance layer 51 and a high dielectric layer 52 .
  • the buried capacitance layer 51 is located on the side of the substrate 11 where the wiring layer 12 is formed, and the high dielectric layer 52 is located between the buried capacitance layer 51 and the wiring layer 12 .
  • the anti-interference structure 54 is embedded in the buried capacitance layer 51 .
  • the anti-interference structure 54 overlaps with the projection of the wiring 121 that transmits power signals or low-frequency signals on the substrate 11 , that is, the anti-interference structure 54 and the wiring 121 have a facing area, so the anti-interference structure 54 and the wiring 121 may form a parasitic capacitance.
  • the anti-interference structure 54 and the wiring 21 are also located on different layers.
  • this embodiment can achieve all the beneficial effects described in Embodiment 1 and Embodiment 3.
  • the anti-interference structure may also form a parasitic capacitance with other grounded conductive structures in the terminal other than the first circuit board 10 and the second circuit board 20 .
  • the electrical connector 30 is fixed by a bracket (not shown).
  • the bracket can be made of conductive material and grounded, then the anti-interference structures 14, 24, 34 can be set to have an area directly facing the bracket, so that the anti-interference structures 14, 24, 34 can form a connection with the bracket. parasitic capacitance.
  • a conductive structure (such as a stainless steel metal plate) can be fixed with conductive glue on one side of the first circuit board 10 and/or the second circuit board 20 , and the conductive structure can be grounded, so that the conductive structure can be grounded.
  • the conductive structure and the anti-interference structure 14 form a parasitic capacitance C.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

本申请提供一种电路板，包括：基板；位于所述基板一表面的走线层，所述走线层用于传输第一电信号和第二电信号，所述第一电信号的频率高于所述第二电信号的频率；接地层，位于所述基板的一侧，所述接地层用于为所述第二电信号提供参考电位；以及抗扰结构，用于形成寄生电容以为所述第一电信号提供参考电位。本申请还提供一种终端。

Description

电路板及终端
相关申请的交叉引用
本申请要求在2022年6月24日提交中国专利局、申请号为202210738709.6、申请名称为“电路板及终端”的中国专利的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电力电子技术领域，尤其涉及一种电路板、应用该电路板的终端。
背景技术
终端产品(例如手机、电脑等)逐渐向小型化、轻薄化、功能多样化发展，这使得对终端产品中各个硬件模块的稳定性和精度要求越来越高。
以终端产品中相机模块为例，相机模块通过电连接器的多个端口与终端产品中其他功能模块建立电连接。随着相机模块的帧频的提升，相机模块中工作信号为高频信号。而电连接器中用于传输高频信号的端口对地阻抗较高，抗干扰能力较弱，容易导致相机模块花屏的问题。
一种解决上述问题的方案为增加电连接器中接地端口的数量，但该种方案会导致电连接器的体积增大，当电连接器应用于终端产品时，难以符合终端产品的小型化和轻薄化要求。
发明内容
本申请第一方面提供一种电路板，包括：
基板；
位于所述基板一表面的走线层，所述走线层用于传输第一电信号和第二电信号，所述第一电信号的频率高于所述第二电信号的频率；
接地层，位于所述基板的一侧，所述接地层用于为所述第二电信号提供参考电位；以及
抗扰结构，用于形成寄生电容以为所述第一电信号提供参考电位。
上述电路板包括走线层，走线层用于传输第一电信号和第二电信号，其中第一电信号的频率高于第二电信号，通过接地层为第二电信号提供参考电位。当电路板电连接电连接器时，走线层中传输第一电信号和第二电信号至电连接器的各个信号端口。而电连接器上的接地端口数量是有限的，这造成电连接器上用于传输频率较高的第一电信号时缺乏良好的电位参考，导致频率较高的第一电信号接地阻抗较大，从而使得电连接器上用于传输第一电信号的端口处的抗扰度较低。而上述电路板通过设置抗扰结构，并且抗扰结构通过形成寄生电容的方式为第一电信号提供参考电位，有利于降低第一电信号的接地阻抗，从而提升电连接器上用于传输频率较高的第一电信号的端口处的抗扰度。从而，上述电路板实现了在不改变电连接器的结构的基础上，解决了电连接器抗干扰能力较弱的问题，同时也可避免增大电连接器的物理尺寸，使得电连接器应用于终端时，符合终端的小型化、轻薄化的要求。
于一些实施例中，所述抗扰结构与所述接地层形成寄生电容，以为所述第一电信号提供 参考电位。
于一些实施例中，所述抗扰结构位于所述基板形成有所述走线层的表面上。
于一些实施例中，所述抗扰结构电连接所述走线层。
如此，所述走线层与所述抗扰结构可在同一制程中形成。
于一些实施例中，所述抗扰结构用于与所述走线层共同传输所述第二电信号。
于一些实施例中，所述走线层包括至少一传输所述第二电信号的走线，所述抗扰结构电连接于所述走线的末端。
如此，所述抗扰结构不用于传输第二电信号，无需考虑缩短第二电信号的传输路径，抗扰结构的位置和结构设计更加灵活。
于一些实施例中，所述电路板包括第一基板和第二基板，所述走线层位于所述第一基板的表面上，所述抗扰结构位于所述第二基板的表面上且电连接所述走线层。
如此，走线层与抗扰结构位于不同层，可以释放走线层的空间，可以排布更多走线。
于一些实施例中，所述抗扰结构自身形成寄生电容，以为所述第一电信号提供参考电位。
于一些实施例中，所述抗扰结构包括相互电绝缘的第一抗扰部和第二抗扰部，所述第一抗扰部电连接所述走线层，所述第二抗扰部接地，所述第一抗扰部和所述第二抗扰部具有正对面积，以形成所述寄生电容。
于一些实施例中，所述第一抗扰部和所述第二抗扰部都包括主体部和由所述主体部一侧延伸出的多个延伸部，所述第一抗扰部上的延伸部与所述第二抗扰部上的延伸部一一交错排列，以形成所述寄生电容。
于一些实施例中，所述抗扰结构与所述走线层形成寄生电容，以为所述第一电信号提供参考电位。
于一些实施例中，还包括埋容层和高介电介质层，所述高介电介质层位于所述埋容层与所述基板之间，所述抗扰结构埋设于所述埋容层中。
于一些实施例中，所述抗扰部与所述走线层为相同的材料。
如此，所述走线层与所述抗扰结构可在同一制程中形成。
于一些实施例中，所述电路板为多层的印刷电路板。
本申请第二方面提供一种终端，包括：
第一电路和电连接所述第一电路板的电连接器；
所述第一电路板如上述任一项所述。
上述终端包括相互电连接的第一电路板和电连接器，第一电路板包括走线层，走线层用于传输第一电信号和第二电信号，其中第一电信号的频率高于第二电信号，通过接地层为第二电信号提供参考电位。当电路板电连接电连接器时，走线层中传输第一电信号和第二电信号至电连接器的各个信号端口。而电连接器上的接地端口数量是有限的，这造成电连接器上用于传输频率较高的第一电信号时缺乏良好的电位参考，导致频率较高的第一电信号接地阻抗较大，从而使得电连接器上用于传输第一电信号的端口处的抗扰度较低。而上述终端通过在第一电路板中设置抗扰结构，使得抗扰结构通过形成寄生电容的方式为第一电信号提供参考电位，有利于降低第一电信号的接地阻抗，从而提升电连接器上用于传输频率较高的第一电信号的端口处的抗扰度。从而，上述终端实现了在不改变电连接器的结构的基础上，解决了电连接器抗干扰能力较弱的问题，同时也可避免增大电连接器的物理尺寸，使得终端符合的小型化、轻薄化的要求。
本申请第三方面提供一种终端，包括：
第一电路；
电连接器，所述电连接器电连接所述第一电路板；以及
导电结构，所述导电结构接地；
所述第一电路板包括：
基板；
位于所述基板一表面的走线层，所述走线层用于传输第一电信号和第二电信号，所述第一电信号的频率高于所述第二电信号的频率；
接地层，位于所述基板的一侧，所述接地层用于为所述第二电信号提供参考电位；以及
抗扰结构，所述抗扰结构与所述导电结构形成寄生电容，以为所述第一电信号提供参考电位。
上述终端包括相互电连接的第一电路板和电连接器，第一电路板包括走线层，走线层用于传输第一电信号和第二电信号，其中第一电信号的频率高于第二电信号，通过接地层为第二电信号提供参考电位。当电路板电连接电连接器时，走线层中传输第一电信号和第二电信号至电连接器的各个信号端口。而电连接器上的接地端口数量是有限的，这造成电连接器上用于传输频率较高的第一电信号时缺乏良好的电位参考，导致频率较高的第一电信号接地阻抗较大，从而使得电连接器上用于传输第一电信号的端口处的抗扰度较低。而上述终端还包括接地的导电结构，并在第一电路板中设置抗扰结构，使得抗扰结构与导电结构通过形成寄生电容的方式为第一电信号提供参考电位，有利于降低第一电信号的接地阻抗，从而提升电连接器上用于传输频率较高的第一电信号的端口处的抗扰度。从而，上述终端实现了在不改变电连接器的结构的基础上，解决了电连接器抗干扰能力较弱的问题，同时也可避免增大电连接器的物理尺寸，使得终端符合小型化、轻薄化的要求。
附图说明
图1为本申请实施例一的终端的立体结构示意图。
图2为本申请实施例一的终端的模块结构示意图。
图3为本申请实施例一的终端中电连接器的信号端口分布示意图。
图4为本申请实施例一的终端中第一电路板的结构示意图。
图5为未设置抗扰结构的第一电路板、第二电路板及电连接器之间的连接关系示意图。
图6为本申请实施例一的第一电路板、第二电路板及电连接器之间的连接关系示意图。
图7为本申请实施例一中传输低频信号时第一电路板、第二电路板及电连接器的电路结构。
图8为本申请实施例一中传输高频信号时第一电路板、第二电路板及电连接器的电路结构。
图9为一对比例和本申请实施例一的终端中阻抗随时间变化的曲线图。
图10为本申请实施例二的终端中第一电路板的结构示意图。
图11为本申请实施例三的终端中第一电路板的结构示意图。
图12为本申请实施例四的终端中第一电路板的结构示意图。
图13为本申请实施例五的终端中第一电路板的结构示意图。
具体实施方式
下面结合本申请实施例中的附图对本申请实施例进行描述。
实施例一
本实施例的终端1如图1所示。终端1可以为智能手机、平板电脑、电视、显示器、车载等。本实施例中以终端1为智能手机进行举例说明。
请参阅图2，终端1包括第一电路板10、第二电路板20及电连接器30。电连接器30包括第一连接部31和第二连接部32。第一连接部31与第一电路板10电连接，第二连接部32与第二电路板20电连接，第一连接部31与第二连接部32相互扣合(或称插接)以建立第一电路板10与第二电路板20之间的电连接，使得第一电路板10与第二电路板20之间可传输电信号。
本实施例中，第一电路板10为终端1的主板，第二电路板20为终端1内功能模块(例如摄像头模块)的副板，第一连接部31为电连接器30的母座，第二连接部32为电连接器30的公座。于其他实施例中，第一电路板10可为副板，第二电路板20可为主板，第一连接部31可为公座，第二连接部32可为母座。
本实施例中，第一连接部31通过焊接方式固定于第一电路板10上：第一电路板10上的传输端口(图未示)处预留多个焊盘(图未示)，以使得电连接器30的第一连接部31上的信号端口与上述焊盘一一对应地焊接。类似的，第二连接部32通过焊接方式固定于第二电路板20上：第二电路板20上的传输端口(图未示)处预留多个焊盘(图未示)，以使得电连接器30第二连接部32上的信号端口与上述焊盘一一对应地焊接。本申请不限定电连接器30与第一电路板10和第二电路板20之间的固定方式。
本实施例中，电连接器30包括多个信号端口。图3为本实施例中电连接器30的各个信号端口(编号为1-28)的分布示意图。根据图3可知，本实施例的电连接器30包括多种类型的信号端口，不同类型的信号端口传输的信号类型不同。例如信号端口25-28用于传输电源信号，信号端口3-8、10、12、14用于传输高频信号，信号端口11、13、19、21、24用于传输低频信号，而信号端口1-2、9、15-16、22-23用于接参考地。
本实施例中，低频信号定义为频率小于等于10MHz的信号，例如复位信号、检测信号等；高频信号定义为频率大于10MHz的信号，例如移动产业处理器接口(Mobile Industry Processor  Interface，MIPI)数据信号、时钟信号。
由图3可知，电连接器30中连接参考地的信号端口数量有限，对于高频信号，其缺乏良好的信号参考，对地阻抗较大，因此抗干扰能力较弱，这使得电连接器30用于传输高频信号的信号端口处易发生射频信号干扰，也即，电连接器30用于传输高频信号的信号端口处抗干扰能力较弱。该射频信号干扰易影响到与电连接器30电连接的第二电路板20，从而影响第二电路板20所连接的功能模组的功能实现(例如使得摄像头模组出现花屏的问题)。本实施例中，通过在第一电路板10和/或第二电路板20中设置抗扰结构，以在不改变电连接器30的结构的基础上，解决上述电连接器30抗干扰能力较弱的问题，同时也可避免增大电连接器30的物理尺寸，使得电连接器30应用于终端1时，符合终端1的小型化、轻薄化要求。
本实施例中，第一电路板10和第二电路板20中抗扰结构是类似的，以下将以第一电路板10上的抗扰结构进行举例说明。
请参阅图4，本实施例中，第一电路板10包括基板11、走线层12及接地层13。基板11用于承载走线层12。走线层12位于基板11的一表面。接地层13位于基板11设置有走线层12的一侧。也即，走线层12位于基板11与接地层13之间。
本实施例中，第一电路板10为印刷电路板，基板11为片状的绝缘材料。走线层12形成有导电图案，导电图案包括多条走线(图4中仅示出一条走线121)，每条走线用于传输电信号，其中部分走线用于传输第一电信号，部分走线用于传输第二电信号。本实施例中，第一电信号包括高频信号，第二电信号包括低频信号。例如图4示出的走线121用于传输第二电信号，也即用于传输电源信号或低频信号。接地层13为片状的导电结构，各处具有基本相同的电位，用于为走线层12传输的第二电信号提供参考电位(也即参考地)。
第一电路板10还包括抗扰结构14，抗扰结构用于为第一电信号提供参考电位(也即参考地)。本实施例中，抗扰结构14位于基板11上形成有走线层12的表面。也即，本实施例中，抗扰结构14与走线层12同层设置。本实施例中，抗扰结构14为一图案连续的、片状的矩形导电块。也即，抗扰结构14在基板11上的正投影为矩形。本实施例中，抗扰结构14与走线121电连接，走线121和抗扰结构14共同作为传输电源信号或低频信号的传输路径。也即，电源信号或低频信号经过走线121和抗扰结构14。本实施例中，抗扰结构14与走线层12的都为金属且材料相同，以在同一蚀刻制程中形成。本实施例中，抗扰结构14与接地层13具有正对面积，也即抗扰结构14在接地层13所在平面的正投影与接地层13重叠，这使得抗扰结构14与接地层13可形成寄生电容C。
本实施例中，走线层12中的各条走线通过连接线40或直接连接至第一电路板10的信号的传输端口，以电连接传输端口处的相应焊盘，通过焊接至焊盘的电连接器30传输电信号至第二电路板20。本实施例中，基板11上开设有通孔111，抗扰结构14覆盖通孔111，连接线40一端与抗扰结构14电接触，并沿着通孔111延伸至第一电路板10的信号的传输端口。
本实施例中，走线121为与传输高频信号的走线相邻的走线。于其他实施例中，走线层12中包括多条用于传输电源信号或低频信号的走线，在每条传输电源信号或低频信号的走线处都分别设置一抗扰结构14，使得每个抗扰结构14都分别与接地层13形成寄生电容C。
未设置抗扰结构14的第一电路板、第二电路板及电连接器之间的连接关系可参阅图5，本实施例中第一电路板10、第二电路板20及电连接器30之间的连接关系可参阅图6，图6与图5所示连接关系主要区别在于，本实施例中，在第一电路板10和第二电路板20中传输电源信号和低频信号的走线处设置抗扰结构14，形成寄生电容C。
请参阅图7，对于低频信号，寄生电容C的状态相当于开路，这使得第一电路板10和第二电路板20设置抗扰结构14时与不设置抗扰结构14时电路结构基本相同，则低频信号的传输路径不受到影响。而对于高频信号，请参阅图8，寄生电容C的状态相当于短路，则抗扰结构14接地，高频信号可以以最临近的抗扰结构14作为参考地，而无需参考距离较远的参考地，这有利于降低高频信号的接地阻抗，因此有利于提升电连接器30传输高频信号的信号端口处(也即第一电路板10和第二电路板20传输高频信号的走线所连接的信号的传输端口处)的抗扰度。
以下通过实验验证本实施例中抗扰结构14对抗扰度的改善效果。
请参阅图9，图9中横坐标表示时间，纵坐标表示阻抗，虚线表示对比例中阻抗随时间的变化曲线，实线表示本实施例中阻抗随时间的变化曲线。根据图9可知，在对比例中，阻抗具有两处突变X和Y，在本实施例中，阻抗也具有两次突变X’和Y’。在X、Y、X’、Y’处阻抗突然增大，这表示X、Y、X’、Y’处对应的时间抗扰度减小。而由于横坐标表示的时间与电信号的传输时间呈正比，因此横坐标还可侧面反应电信号传输的距离，从而可根据横坐标的值推算发生阻抗突变的位置，从而确认终端中哪个位置阻抗较大、抗扰度较低。经计算，在对比例和本实施例中，发生阻抗突增的位置都是连接器传输高频信号的信号端口处。而从图9可明显看出，本实施例的连接器传输高频信号的信号端口的阻抗要低于对比例中连接器传输高频信号的信号端口的阻抗，则本实施例的连接器传输高频信号的信号端口的抗扰度要高于对比例中的连接器传输高频信号的信号端口的抗扰度。因此，本实施例的终端1、第一电路板10及第二电路板20有利于提升电连接器30的传输高频信号的信号端口的抗扰度。
本实施例中，第一电路板10为多层的印刷电路板。相较于图4示例出的结构，本实施例的第一电路板10还可包括更多数量的基板11、走线层12和接地层13，图4中基板11、走线层12及接地层13之间的结构关系仅作示例。当第一电路板10包括多个基板11、走线层12和接地层13时，相邻走线层12之间、相邻的走线层12与接地层13之间都设置有一基板11。可通过在基板11上开设通孔的方式，使得基板11两侧的走线层12之间、或走线层12与接地层13之间通过通孔建立电连接。第一电路板10包括多个基板11时，可以在每个基板11表面上皆设置抗扰结构14，也可以在其中一些基板11的表面上设置抗扰结构14。本实施例中，每个抗扰结构14与距离其最近的接地层13形成寄生电容。
于本申请其他实施例中，第一电路板10也可为单层的印刷电路板或双层的印刷电路板。
本实施例中，电连接器30为板对板(Board to aboard，BTB)连接器。于其他实施例中，电连接器30还可为零插入力(Zero Insertion Force，ZIF)连接器、Type C连接器等。
本实施例的终端1、第一电路板10及第二电路板20，通过在传输电源信号和/或低频信号的走线所连接的信号的传输端口处增设抗扰结构14，可使得抗扰结构14与接地层13形成寄生电容C，对于高频信号，寄生电容C相当于短路的状态，则抗扰结构14接地，可作为高频信号的参考地。由于抗扰结构14位于传输高频信号的走线的相邻走线所连接的传输端口处，有利于减小高频信号的接地阻抗，提升电连接器30用于传输高速信号的信号端口处的抗扰度。
实施例二
本实施例提供的终端与实施例一中终端1的主要区别在于抗扰结构的位置不同。
请参阅图10，本实施例中抗扰结构24与实施例一中抗扰结构14的形状结构基本相同，区别主要在于，本实施例中抗扰结构24电连接于走线121的末端。本实施例中，连接线40 一端与走线121直接电连接，并沿着通孔111延伸至第一电路板10的信号的传输端口。电源信号或低频信号经走线121和连接线40传输至传输端口，以传输至电连接器30，电源信号或低频信号并不经过抗扰结构14。抗扰结构14与接地层13具有正对面积，可与接地层13形成寄生电容。
通常，用于传输电信号的走线的布局设计需要满足路径最短的要求，本实施例中，由于电源信号或低频信号(也即电信号)并不经过抗扰结构24传输，则抗扰结构24的位置和形状的设计自由度较高。
因此，本实施例可以实现如实施例一中所述的所有有益效果，在此基础上，还有利于提升抗扰结构24的位置和形状的设计自由度。
实施例三
本实施例提供的终端与实施例一和实施例二中的终端的主要区别在于抗扰结构的位置不同。
请参阅图11，本实施例中，第一电路板10包括层叠设置的第一基板310和第二基板320。第二基板320位于第一基板310与接地层13之间。走线层12位于第一基板310靠近第二基板320的表面上，抗扰结构34位于第二基板320远离第一基板310的表面上。也即，本实施例中，抗扰结构34与走线层12分别位于不同的基板的表面上。换句话说，本实施例中，抗扰结构34与走线层12不同层设置。
本实施例中，通过在第一基板310上开设第一通孔311，使得第一基板310上的走线121可通过连接线50和通孔311与第二基板320上的抗扰结构34电连接。通过在第二基板320上开设第二通孔321，使得走线121可通过第二通孔321和连接线40电连接至第一电路板10的信号的传输端口。本实施例中，电源信号和低频信号经走线121和连接线40传输至传输端口，抗扰结构34不用于传输电源信号或低频信号。
本实施例可以实现如实施例一和实施例二中所述的所有有益效果。在此基础上，由于本实施例中抗扰结构34与走线层12设置于不同的基板表面上，有利于释放走线层12的面积，使得走线层12可以排布更多数量的走线。
实施例四
本实施例提供的终端与实施例一至三中的终端的主要区别在于抗扰结构的位置和结构。
请参阅图12，本实施例中，抗扰结构44位于基板11形成有走线层12的表面上，与走线121电连接。抗扰结构44包括第一抗扰部441和第二抗扰部442。第一抗扰部441与走线121电连接，第二抗扰部442接地。第一抗扰部441与第二抗扰部442电绝缘。本实施例中，第一抗扰部441与第二抗扰部442为梳状。也即，第一抗扰部441包括主体部4411和由主体部一侧凸伸出的多个长条形的平行排列的延伸部4412。类似的，第二抗扰部442包括主体部4421和由主体部4421一侧凸伸出的多个长条形的平行排列的延伸部4422。多个延伸部4412和多个延伸部4422依次交错间隔排列。也即，每相邻的两个延伸部4412之间具有一延伸部4422，每相邻的两个延伸部4422之间具有一延伸部4412，以使得第一抗扰部441与第二抗扰部442具有正对面积，可形成寄生电容C。
本实施例中的抗扰结构44，同样可应用于实施例二和实施例三中所述的抗扰结构的位置。也即，本实施例中的抗扰结构44可以如实施例一中所述用于与走线121共同传输电源信号或低频信号；抗扰结构44也可以如实施例二中所述连接于走线121的末端，不参与传输电源信号或低频信号；抗扰结构44还可以如实施例三中所述与走线层12位于不同的基板表面上。
本实施例可以实现如实施例一-三中所述的所有有益效果。
实施例五
本实施例的终端与实施例一至四中的终端的主要区别在于抗扰结构的位置和结构。
本实施例中，采用埋容技术在第一电路板10中形成抗扰结构54。请参阅图13，本实施例中，第一电路板10包括基板11、走线层12、埋容层51及高介电介质层52。埋容层51位于基板11上形成有走线层12的一侧，高介电介质层52位于埋容层51与走线层12之间。埋容层51内埋设有抗扰结构54。抗扰结构54与传输电源信号或低频信号的走线121在基板11上的投影重叠，也即抗扰结构54与走线121具有正对面积，则抗扰结构54与走线121可形成寄生电容。本实施例中，抗扰结构54与走线21也位于不同层。
因此，本实施例可以实现如实施例一和实施例三中所述的所有有益效果。
于本申请其他的实施例中，抗扰结构也可与终端中除第一电路板10和第二电路板20之外的其他接地的导电结构形成寄生电容。
例如于一些实施例中，电连接器30通过支架(图未示)固定。在该实施例中，可将支架设置为导电材料并使其接地，则抗扰结构14、24、34可设置为与支架具有正对面积，使得抗扰结构14、24、34可与支架形成寄生电容。
例如于另一些实施例中，可以在第一电路板10和/或第二电路板20的一侧用导电胶固定一导电结构(例如不锈钢金属板)，并设置该导电结构接地，以使得该导电结构与抗扰结构14形成寄生电容C。
上述的其他实施例，同样可以实现如实施例一-实施例三中所述的所有有益效果。
本技术领域的普通技术人员应当认识到，以上的实施方式仅是用来说明本发明，而并非用作为对本发明的限定，只要在本发明的实质精神范围之内，对以上实施例所作的适当改变和变化都落在本发明要求保护的范围之内。

Claims (16)

  1. 一种电路板，其特征在于，包括：
    基板；
    位于所述基板一表面的走线层，所述走线层用于传输第一电信号和第二电信号，所述第一电信号的频率高于所述第二电信号的频率；
    接地层，位于所述基板的一侧，所述接地层用于为所述第二电信号提供参考电位；以及
    抗扰结构，用于形成寄生电容以为所述第一电信号提供参考电位。
  2. 如权利要求1所述的电路板，其特征在于，所述抗扰结构与所述接地层形成寄生电容，以为所述第一电信号提供参考电位。
  3. 如权利要求2所述的电路板，其特征在于，所述抗扰结构位于所述基板形成有所述走线层的表面上。
  4. 如权利要求3所述的电路板，其特征在于，所述抗扰结构电连接所述走线层。
  5. 如权利要求4所述的电路板，其特征在于，所述抗扰结构用于与所述走线层共同传输所述第二电信号。
  6. 如权利要求4所述的电路板，其特征在于，所述走线层包括至少一传输所述第二电信号的走线，所述抗扰结构电连接于所述走线的末端。
  7. 如权利要求2所述的电路板，其特征在于，所述电路板包括第一基板和第二基板，所述走线层位于所述第一基板的表面上，所述抗扰结构位于所述第二基板的表面上且电连接所述走线层。
  8. 如权利要求1所述的电路板，其特征在于，所述抗扰结构自身形成寄生电容，以为所述第一电信号提供参考电位。
  9. 如权利要求8所述的电路板，其特征在于，所述抗扰结构包括相互电绝缘的第一抗扰部和第二抗扰部，所述第一抗扰部电连接所述走线层，所述第二抗扰部接地，所述第一抗扰部和所述第二抗扰部具有正对面积，以形成所述寄生电容。
  10. 如权利要求9所述的电路板，其特征在于，所述第一抗扰部和所述第二抗扰部都包括主体部和由所述主体部一侧延伸出的多个延伸部，所述第一抗扰部上的延伸部与所述第二抗扰部上的延伸部一一交错排列，以形成所述寄生电容。
  11. 如权利要求1所述的电路板，其特征在于，所述抗扰结构与所述走线层共同形成寄生电容，以为所述第一电信号提供参考电位。
  12. 如权利要求11所述的电路板，其特征在于，还包括埋容层和高介电介质层，所述高介电介质层位于所述埋容层与所述基板之间，所述抗扰结构埋设于所述埋容层中。
  13. 如权利要求1-6任一项所述的电路板，其特征在于，所述抗扰部与所述走线层为相同的材料。
  14. 如权利要求1-13任一项所述的电路板，其特征在于，所述电路板为多层的印刷电路板。
  15. 一种终端，其特征在于，包括：
    第一电路板和电连接所述第一电路板的电连接器；
    所述第一电路板如权利要求1-14任一项所述。
  16. 一种终端，其特征在于，包括：
    第一电路；
    电连接器，电连接所述第一电路板；以及
    导电结构，所述导电结构接地；
    所述第一电路板包括：
    基板；
    位于所述基板一表面的走线层，所述走线层用于传输第一电信号和第二电信号，所述第一电信号的频率高于所述第二电信号的频率；
    接地层，位于所述基板的一侧，所述接地层用于为所述第二电信号提供参考电位；以及
    抗扰结构，与所述导电结构共同形成寄生电容，以为所述第一电信号提供参考电位。
PCT/CN2023/100346 2022-06-24 2023-06-15 电路板及终端 WO2023246608A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210738709.6 2022-06-24
CN202210738709.6A CN117320254A (zh) 2022-06-24 2022-06-24 电路板及终端

Publications (1)

Publication Number Publication Date
WO2023246608A1 true WO2023246608A1 (zh) 2023-12-28

Family

ID=89283658

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/100346 WO2023246608A1 (zh) 2022-06-24 2023-06-15 电路板及终端

Country Status (2)

Country Link
CN (1) CN117320254A (zh)
WO (1) WO2023246608A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118075984A (zh) * 2024-04-25 2024-05-24 荣耀终端有限公司 电路板及终端设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008252804A (ja) * 2007-03-30 2008-10-16 Kyocera Corp 整合回路、送信器、受信器、送受信器およびレーダ装置
US20120125665A1 (en) * 2010-11-19 2012-05-24 Kabushiki Kaisha Toshiba High-frequency device
JP2013055476A (ja) * 2011-09-02 2013-03-21 Toshiba Corp 高周波デバイス
CN105592624A (zh) * 2015-12-17 2016-05-18 广东顺德中山大学卡内基梅隆大学国际联合研究院 高效抑制边沿辐射的高密度pcb板及边沿辐射抑制方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008252804A (ja) * 2007-03-30 2008-10-16 Kyocera Corp 整合回路、送信器、受信器、送受信器およびレーダ装置
US20120125665A1 (en) * 2010-11-19 2012-05-24 Kabushiki Kaisha Toshiba High-frequency device
JP2013055476A (ja) * 2011-09-02 2013-03-21 Toshiba Corp 高周波デバイス
CN105592624A (zh) * 2015-12-17 2016-05-18 广东顺德中山大学卡内基梅隆大学国际联合研究院 高效抑制边沿辐射的高密度pcb板及边沿辐射抑制方法

Also Published As

Publication number Publication date
CN117320254A (zh) 2023-12-29

Similar Documents

Publication Publication Date Title
US7245503B2 (en) Circuit board having signal lines adapted to transmit high speed signals
US8242374B2 (en) Flexible-circuit-board cable with positioning structure for insertion
JP4929329B2 (ja) 回路基板の挿入位置決めコネクタ
WO2023246608A1 (zh) 电路板及终端
US11419212B2 (en) Flexible printed circuit and manufacturing method thereof, electronic device module and electronic device
JP2013026601A (ja) プリント配線板、プリント配線板モジュール、光通信モジュール、光通信装置、および演算処理装置
JP6151794B2 (ja) 回路基板、電子部品収納用パッケージおよび電子装置
KR20190053462A (ko) 플렉시블 케이블 및 이를 구비하는 전자 장치
WO2023071545A9 (zh) 电路板和电子设备
WO2023273757A1 (zh) 印刷电路板和电子设备
US20070194434A1 (en) Differential signal transmission structure, wiring board, and chip package
US20120063787A1 (en) Connector and optical transmission apparatus
WO2020156595A9 (zh) 柔性电路板及制作方法、显示装置、电路板结构及其显示面板
CN109951951B (zh) 印刷电路板及显示装置
WO2022206632A1 (zh) 连接器单体、连接器、电路板、电子设备及电子系统
US20230369257A1 (en) Semiconductor device
TW201526392A (zh) 連接器
CN113678574B (zh) 一种共模抑制的封装装置和印制电路板
US20200170109A1 (en) Circuit board structure incorporated with resin-based conductive adhesive layer
US20140179162A1 (en) Apparatus for Differential Far-End Crosstalk Reduction
CN219919251U (zh) 印制电路板及电子设备
JP7302869B2 (ja) 通信モジュール、及び通信回路
CN213241112U (zh) 触控面板及电子设备
CN219678775U (zh) 印制电路板及电子设备
US11784383B2 (en) Transmission line and electronic device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23826257

Country of ref document: EP

Kind code of ref document: A1