WO2023245729A1 - 一种阻抗校准电路、阻抗校准方法和存储器 - Google Patents

一种阻抗校准电路、阻抗校准方法和存储器 Download PDF

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Publication number
WO2023245729A1
WO2023245729A1 PCT/CN2022/103676 CN2022103676W WO2023245729A1 WO 2023245729 A1 WO2023245729 A1 WO 2023245729A1 CN 2022103676 W CN2022103676 W CN 2022103676W WO 2023245729 A1 WO2023245729 A1 WO 2023245729A1
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Prior art keywords
signal
calibration
impedance
pull
impedance calibration
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PCT/CN2022/103676
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English (en)
French (fr)
Inventor
张志强
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长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to KR1020227031287A priority Critical patent/KR20220133300A/ko
Priority to EP22782653.4A priority patent/EP4318473A1/en
Priority to US17/952,850 priority patent/US20230015113A1/en
Publication of WO2023245729A1 publication Critical patent/WO2023245729A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B33/00—Constructional parts, details or accessories not provided for in the other groups of this subclass
    • G11B33/14—Reducing influence of physical parameters, e.g. temperature change, moisture, dust
    • G11B33/1406—Reducing the influence of the temperature
    • G11B33/144—Reducing the influence of the temperature by detection, control, regulation of the temperature
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B33/00—Constructional parts, details or accessories not provided for in the other groups of this subclass
    • G11B33/14—Reducing influence of physical parameters, e.g. temperature change, moisture, dust
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Definitions

  • the present disclosure relates to the technical field of semiconductor memories, and in particular to an impedance calibration circuit, an impedance calibration method and a memory.
  • DRAM Dynamic Random Access Memory
  • the present disclosure provides an impedance calibration circuit, an impedance calibration method and a memory, which can reduce the power consumption and time of impedance calibration and improve the performance of the memory.
  • inventions of the present disclosure provide an impedance calibration circuit.
  • the impedance calibration circuit includes a parameter module, an initial value generation module and a calibration module; wherein the parameter module is configured to perform environment detection processing and output environmental parameters. signal; the initial value generation module is configured to receive the environmental parameter signal, and when receiving the calibration instruction signal, output an initial calibration value based on the environmental parameter signal; the calibration module is configured to receive the initial calibration value, and when receiving the calibration instruction signal, perform impedance calibration processing based on the initial calibration value.
  • the environmental parameter signal at least includes a temperature parameter signal;
  • the parameter module includes a temperature sensor and a decoding module; wherein the temperature sensor is configured to measure the temperature of the environment where the impedance calibration circuit is located. Detect and output a temperature signal; the decoding module is configured to receive the temperature signal, decode the temperature signal, and output the temperature parameter signal.
  • the initial calibration value includes a first initial calibration value and a second initial calibration value; the calibration module is specifically configured to determine the first initial calibration value as the initial value of the first impedance calibration code. , determine the second initial calibration value as the initial value of the second impedance calibration code; and adjust the first impedance calibration code to achieve the calibration of the pull-up impedance; after the pull-up impedance calibration is completed, The second impedance calibration code is adjusted to achieve calibration of the pull-down impedance.
  • the calibration module includes a first counting module, a first comparator and a resistance module, the resistance module includes a first pull-up resistor unit, and the first pull-up resistor unit is connected to a standard resistor;
  • the resistance module is configured to receive the first impedance calibration code, control the resistance of the first pull-up resistor unit based on the first impedance calibration code, and output a first voltage signal;
  • a comparator configured to receive the first voltage signal and the first reference signal, compare the first voltage signal with the first reference signal, and output a first indication signal;
  • the first counting module is configured In order to receive the first indication signal and the first counting clock signal, when the first indication signal is in the first level state, each time a pulse of the first counting clock signal is detected, the first impedance is The calibration code performs addition processing; when the first indication signal is in the second level state, each time a pulse of the first counting clock signal is detected, the first impedance calibration code is subtracted to achieve the above. Calibration processing of pull impedance.
  • the calibration module further includes a second counting module and a second comparator.
  • the resistance module further includes a second pull-up resistor unit and a pull-down resistor unit.
  • the resistance of the second pull-up resistor unit is It is controlled by the first impedance calibration code, and the second pull-up resistor unit and the pull-down resistor unit are connected; wherein, the resistance module is also configured to, after the pull-up impedance calibration is completed, based on the second The impedance calibration code controls the resistance of the pull-down resistor unit and outputs a second voltage signal; wherein, after the pull-up impedance calibration is completed, the resistance of the second pull-up resistor unit is adjusted by the first impedance calibration code.
  • the second comparator is configured to receive the second voltage signal and a second reference signal, compare the second voltage signal with the second reference signal, and output a second indication signal ;
  • the second counting module is configured to receive the second indication signal and a second counting clock signal, and when the second indication signal is in a third level state, each time the second counting clock signal is detected One pulse, the second impedance calibration code is added; when the second indication signal is in the fourth level state, each time a pulse of the second counting clock signal is detected, the second impedance is added The calibration code is subtracted to achieve the calibration process of the pull-down impedance.
  • the control end of the first pull-up resistor unit receives the first impedance calibration code, the first end of the first pull-up resistor unit is connected to the power signal, and the first pull-up resistor The second end of the unit is connected to the first end of the standard resistor, and the second end of the standard resistor is connected to the ground signal; the control end of the second pull-up resistor unit receives the first impedance calibration code, so The first end of the second pull-up resistor unit is connected to the power signal, the second end of the second pull-up resistor unit is connected to the first end of the pull-down resistor unit, and the second end of the pull-down resistor unit is connected to Ground signal connection.
  • the calibration module further includes an oscillation module and a control module; the first counting module is integrated with a first detection module, and the second counting module is integrated with a second detection module; wherein, the oscillation module , configured to receive the calibration instruction signal, and output a clock signal based on the calibration instruction signal; the control module is configured to receive the clock signal; based on the clock signal, output the clock signal to the first counting module a first counting clock signal; the first detection module is configured to record the change of the first indication signal; if the change of the first indication signal meets the first preset condition, send a signal to the control The module outputs a first termination signal; the control module is further configured to, upon receiving the first termination signal, stop outputting the first counting clock signal; and based on the clock signal, send a signal to the second The counting module outputs the second counting clock signal; the second detection module is configured to record changes in the second indication signal; if the changes in the first indication signal meet the second preset condition, Then output a second termination signal to the control module;
  • control module is further configured to output an internal stop signal to the oscillation module upon receiving the second termination signal; the oscillation module is further configured to receive the internal stop signal. signal, based on the internal stop signal, stops outputting the clock signal.
  • the first preset condition refers to that during three consecutive adjustments of the first impedance calibration code, the first indication signal continues to change from the second value after changing from the first value to the second value. is the first value; the second preset condition means that during the three consecutive adjustments of the second impedance calibration code, the second indication signal continues to change from the second value to first value.
  • the first counting module is further configured to receive a latch signal and latch the first impedance calibration code based on the latch signal; the second counting module is also configured to The latch signal is received, and the second impedance calibration code is latched based on the latch signal.
  • embodiments of the present disclosure provide an impedance calibration method, which is applied to an impedance calibration circuit.
  • the method includes:
  • an impedance calibration process is performed based on the initial calibration value.
  • the environmental parameter signal at least includes a temperature parameter signal; and determining the environmental parameter signal through environmental detection processing includes:
  • the temperature of the environment in which the impedance calibration circuit is located is detected to obtain a temperature signal; the temperature signal is decoded to obtain the temperature parameter signal.
  • the initial calibration value includes a first initial calibration value and a second initial calibration value; the impedance calibration process based on the initial calibration value includes:
  • the impedance calibration circuit includes a first pull-up resistor unit, and the first pull-up resistor unit is connected to a standard resistor, and the first impedance calibration code is adjusted to achieve the pull-up Impedance calibration processing, including:
  • the impedance calibration circuit further includes a second pull-up resistor unit and a pull-down resistor unit, the resistance of the second pull-up resistor unit is controlled by the first impedance calibration code, and the second pull-up resistor unit is controlled by the first impedance calibration code.
  • the pull-up resistor unit is connected to the pull-down resistor unit, and the adjustment of the second impedance calibration code to realize the calibration process of the pull-down impedance includes:
  • the resistance value of the pull-down resistor unit is adjusted based on the second impedance calibration code to output a second voltage signal; wherein, after the pull-up impedance calibration is completed, the resistance value of the second pull-up resistor unit is adjusted by the
  • the first impedance calibration code is calibrated to a standard resistance value; the second voltage signal is compared with the second reference signal, and a second indication signal is output; when the second indication signal is in the third level state, each time it is detected One pulse of the second counting clock signal is added to the second impedance calibration code; when the second indication signal is in the fourth level state, every time a pulse of the counting clock signal is detected, the second impedance calibration code is added.
  • the second impedance calibration code is subtracted; when the change of the second indication signal meets the second preset condition, the output of the second counting clock signal is stopped, and the calibration process of the pull-down impedance is ended.
  • the method further includes: when receiving a latch signal, latching the first impedance calibration code and the second impedance calibration code.
  • an embodiment of the present disclosure provides a memory including the impedance calibration circuit described in the first aspect.
  • Embodiments of the present disclosure provide an impedance calibration circuit, an impedance calibration method, and a memory.
  • the impedance calibration circuit includes a parameter module, an initial value generation module, and a calibration module; wherein the parameter module is configured to perform environment detection processing and output environmental parameter signals. ;
  • the initial value generation module is configured to receive the environmental parameter signal, and when receiving the calibration instruction signal, output the initial calibration value based on the environmental parameter signal;
  • the calibration module is configured to receive the initial calibration value, and when receiving the calibration instruction signal, The impedance calibration process is performed based on the initial calibration value. In this way, using the initial calibration value adapted to the current working environment for impedance calibration processing can reduce the power consumption and time of impedance calibration and improve the performance of the memory.
  • Figure 1 is a schematic structural diagram of an impedance calibration circuit provided by an embodiment of the present disclosure
  • FIG. 2 is a detailed structural schematic diagram of an impedance calibration circuit provided by an embodiment of the present disclosure
  • Figure 3 is a signal timing diagram of impedance calibration
  • Figure 4 is a schematic structural diagram of an impedance calibration circuit provided by related technologies
  • Figure 5 is a schematic diagram of the effect of the impedance calibration circuit provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic flow chart of an impedance calibration method provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a memory provided by an embodiment of the present disclosure.
  • first ⁇ second ⁇ third involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understandable that "first ⁇ second ⁇ third” Where permitted, the specific order or sequence may be interchanged so that the embodiments of the disclosure described herein can be practiced in an order other than that illustrated or described herein.
  • the resistance of these resistors needs to be calibrated to match the actual application scenario.
  • the above impedance calibration process is also called ZQ calibration.
  • the signal used to control the resistor resistance is called impedance calibration. code (also called ZQ calibration code). That is to say, during the impedance calibration process, the resistance value of the resistor is adjusted by adjusting the size of the impedance calibration code until the resistance value of the resistor meets the requirements.
  • the impedance calibration code needs to be changed from a fixed initial value. As a result, impedance calibration takes up excessive power consumption and system time, and reduces memory performance.
  • the impedance calibration circuit includes a parameter module, an initial value generation module and a calibration module; wherein, the parameter module is configured to perform environment detection processing and output environmental parameter signals; the initial value The generation module is configured to receive the environmental parameter signal, and when receiving the calibration instruction signal, output an initial calibration value based on the environmental parameter signal; the calibration module is configured to receive the initial calibration value, and when receiving the calibration instruction signal, output the initial calibration value based on the initial calibration value. value for impedance calibration processing.
  • using the initial calibration value adapted to the current working environment for impedance calibration processing can reduce the power consumption and time of impedance calibration and improve the performance of the memory.
  • FIG. 1 shows a schematic structural diagram of an impedance calibration circuit 10 provided by an embodiment of the present disclosure.
  • the impedance calibration circuit 10 may include a parameter module 11, an initial value generation module 12 and a calibration module 13; wherein,
  • the parameter module 11 is configured to perform environment detection processing and output environmental parameter signals
  • the initial value generation module 12 is configured to receive an environmental parameter signal, and when receiving a calibration instruction signal, output an initial calibration value based on the environmental parameter signal;
  • the calibration module 13 is configured to receive an initial calibration value, and when receiving a calibration instruction signal, perform an impedance calibration process based on the initial calibration value.
  • impedance calibration circuit 10 of the embodiment of the present disclosure is applied to various types of memories, such as DRAM and Synchronous Dynamic Random-Access Memory.
  • the embodiment of the present disclosure provides an impedance calibration circuit 10 with a new architecture.
  • the parameter module 11 and the initial value generation module 12 can generate an initial calibration value adapted to the current working environment, thereby using the initial calibration value as a
  • the starting point of the entire impedance calibration process can be adjusted to the ideal state faster, which can reduce the power consumption and time of impedance calibration, while providing a better time margin for the latch of the calibration results and improving the performance of the memory.
  • the calibration instruction signal indicates the start of the impedance calibration process, and the calibration instruction signal is received from the outside (or called the system).
  • the environmental parameter signal includes at least one of the following signals: temperature parameter signal and voltage parameter signal.
  • the environmental parameter signal at least includes a temperature parameter signal;
  • the parameter module 11 includes a temperature sensor 111 and a decoding module 112; wherein,
  • the temperature sensor 111 is configured to detect the temperature of the environment where the impedance calibration circuit 10 is located and obtain a temperature signal;
  • the decoding module 112 is configured to receive a temperature signal, decode the temperature signal, and output a temperature parameter signal.
  • the essence of the temperature parameter signal is the impedance calibration code used to adjust the resistor impedance.
  • the decoding module 112 is configured to preliminarily decode the temperature signal into a temperature parameter signal for subsequent determination of the initial calibration value.
  • the impedance calibration of the memory involves the calibration of the pull-up impedance (used to output the signal) and the calibration of the pull-down impedance (used to terminate the signal). Therefore, in some embodiments, as shown in Figure 2, in some embodiments, the initial calibration value includes a first initial calibration value TO_Pcode ⁇ 5:0> and a second initial calibration value TO_Ncode ⁇ 5:0>;
  • the calibration module 13 is specifically configured to determine the first initial calibration value TO_Pcode ⁇ 5:0> as the initial value of the first impedance calibration code Pcode ⁇ 5:0> when receiving the calibration instruction signal, and determine the second initial calibration value TO_Pcode ⁇ 5:0>.
  • TO_Ncode ⁇ 5:0> is determined as the initial value of the second impedance calibration code Ncode ⁇ 5:0>;
  • the first impedance calibration code/second impedance calibration code/first calibration initial value/second calibration initial value are composed of 6 sub-signals, expressed as ⁇ 5:0>, but this It does not constitute a specific limitation.
  • the respective initial values of the first impedance calibration code and the second impedance calibration code are fixed default values.
  • the initial values of the first impedance calibration code and the second impedance calibration code are determined based on the current working environment, which can be adjusted to the ideal state faster and can reduce the power consumption and power consumption of the impedance calibration. time, while providing a better time margin for the latch of the calibration results and improving memory performance.
  • the calibration module 13 includes a first counting module 131 , a first comparator 132 and a resistance module 133 .
  • the resistance module 133 includes a first pull-up resistor unit 201 , and the first pull-up resistor Unit 201 is connected to standard resistor 204; where,
  • the resistance module 133 is configured to receive the first impedance calibration code Pcode ⁇ 5:0>, control the resistance of the first pull-up resistor unit 201 based on the first impedance calibration code Pcode ⁇ 5:0>, and output the first voltage signal. ;
  • the first comparator 132 is configured to receive the first voltage signal and the first reference signal Vref1, compare the first voltage signal with the first reference signal Vref1, and output the first indication signal;
  • the first counting module 131 is configured to receive the first indication signal and the first counting clock signal pclk. When the first indication signal is in the first level state, each time a pulse of the first counting clock signal pclk is detected, the first counting module 131 The impedance calibration code Pcode ⁇ 5:0> is added; when the first indication signal is in the second level state, every time a pulse of the first counting clock signal pclk is detected, the first impedance calibration code Pcode ⁇ 5:0 >Perform subtraction processing to achieve calibration processing of pull-up impedance.
  • the first voltage signal can indicate the difference between the resistance value of the first pull-up resistor unit and the standard resistance value, thereby determining the adjustment direction of the first impedance calibration code Pcode ⁇ 5:0>, forming a feedback adjustment loop.
  • the specific relationship between the first impedance calibration code Pcode ⁇ 5:0> and the resistance value of the first pull-up resistor unit needs to depend on the actual application scenario.
  • the first level state and the second level state are different, and their specific settings also need to be determined according to the actual application scenario.
  • the positive input terminal of the first comparator 132 receives the first reference signal Vref1
  • the negative input terminal of the first comparator 132 receives the first voltage signal.
  • the specific connection relationship is It also needs to be determined based on the actual application scenario. In other words, as long as it conforms to a self-consistent circuit adjustment logic, the control details of the pull-up impedance can be determined in a variety of flexible ways.
  • Code Pcode ⁇ 5:0> is subtracted, and the resistance of the first pull-up resistor unit 201 increases; conversely, when the resistance of the first pull-up resistor unit 201 is greater than the standard resistor, the voltage of the first voltage signal is less than the first reference voltage, at this time the first indication signal is in a high level state, so the first impedance calibration codes Pcode ⁇ 5:0> are added, and the resistance of the first pull-up resistor unit 201 is reduced.
  • subtraction processing can be minus one, minus two...and so on
  • addition processing can be plus one, plus two...and so on, depending on the actual application scenario.
  • the calibration module 13 also includes a second counting module 134 and a second comparator 135, and the resistance module 133 also includes a second pull-up resistor unit 202 and a pull-down resistor unit 203,
  • the resistance of the second pull-up resistor unit 202 is controlled by the first impedance calibration code Pcode ⁇ 5:0>, and the second pull-up resistor unit 202 and the pull-down resistor unit 203 are connected;
  • the resistance module 133 is configured to control the resistance of the pull-down resistor unit 203 based on the second impedance calibration code Ncode ⁇ 5:0> after the pull-up impedance calibration is completed, and output a second voltage signal; wherein, during the pull-up After the impedance calibration is completed, the resistance value of the second pull-up resistor unit 202 is calibrated to the standard resistance value by the first impedance calibration code Pcode ⁇ 5:0>;
  • the second comparator 135 is configured to receive the second voltage signal and the second reference signal Vref2, compare the second voltage signal with the second reference signal Vref2, and output a second indication signal;
  • the second counting module 134 is configured to receive the second indication signal and the second counting clock signal nclk, and when the second indication signal is in the third level state, each time a pulse of the second counting clock signal nclk is detected, the second counting module 134
  • the impedance calibration code Ncode ⁇ 5:0> is added; when the second indication signal is in the fourth level state, every time a pulse of the second counting clock signal nclk is detected, the second impedance calibration code Ncode ⁇ 5:0 >Perform subtraction processing to achieve calibration processing of pull-down impedance.
  • the second pull-up resistor unit 202 and the first pull-up resistor unit 201 can be regarded as having the same structure, and their resistance values have the same change. Therefore, after the pull-up impedance calibration is completed, the calibrated first impedance calibration code Pcode ⁇ 5:0> can also calibrate the second pull-up resistor unit 202 to the standard resistance value.
  • the first pull-up resistor unit 201 and the standard resistor 204 are first used to form a path, and the first pull-up resistor unit is determined based on the voltage division between the first pull-up resistor unit 201 and the standard resistor. 201, thereby adjusting the first impedance calibration code Pcode ⁇ 5:0> until the resistance of the first pull-up resistor unit 201 reaches the standard resistance.
  • the second pull-up resistor unit 202 and the pull-down resistor unit 203 are used to form a path.
  • the second pull-up resistor unit 202 can be regarded as a standard resistor.
  • the second pull-up resistor unit 202 and the pull-down resistor unit determines the resistance of the pull-down resistor unit 203, thereby adjusting the second impedance calibration code Ncode ⁇ 5:0> until the resistance of the pull-down resistor unit 203 reaches the standard resistance value.
  • the second pull-up resistor unit 202 and the first pull-up resistor unit 201 may receive the first impedance calibration code Pcode ⁇ 5:0> at the same time. Please note that during the calibration process of the pull-up impedance, since the pull-down resistor unit 203 is not turned on, although the second pull-up resistor unit 202 is controlled by the first impedance calibration code Pcode ⁇ 5:0>, it is actually not connected. Connect the ground terminal to avoid power consumption issues.
  • the second pull-up resistor unit 202 and the first pull-up resistor unit 201 may not receive the first impedance calibration code Pcode ⁇ 5:0> at the same time, that is, after the calibration of the pull-up impedance is completed, the An impedance calibration code Pcode ⁇ 5:0> is sent to the second pull-up resistor unit 202.
  • the specific relationship between the second voltage signal and the resistance value of the pull-down resistor unit (that is, a positive proportional relationship or a negative proportional relationship) also depends on the actual application scenario.
  • the second voltage signal can indicate the difference between the pull-down resistor and the standard resistance value, thereby determining the adjustment direction of the second impedance calibration code Ncode ⁇ 5:0>, forming a feedback adjustment loop.
  • the control details of the pull-down impedance can be determined in a variety of flexible ways.
  • the second indication signal is in a high level state, so that the second impedance calibration code Ncode ⁇ 5: 0>Perform subtraction processing, and the resistance value of the pull-down resistor unit 203 increases; conversely, when the resistance value of the pull-down resistor unit 203 is greater than the standard resistance, the voltage of the second voltage signal is greater than the second reference voltage, and at this time the second indication The signal is in a low level state, so the second impedance calibration code Ncode ⁇ 5:0> is added, and the resistance of the pull-down resistor unit 203 is reduced.
  • the control terminal of the first pull-up resistor unit 201 receives the first impedance calibration code Pcode ⁇ 5:0>, and the first terminal of the first pull-up resistor unit 201 Connected to the power signal, the second end of the first pull-up resistor unit 201 is connected to the first end of the standard resistor 204, and the second end of the standard resistor 204 is connected to the ground signal;
  • the control end of the second pull-up resistor unit 202 receives the first impedance calibration code Pcode ⁇ 5:0>, the first end of the second pull-up resistor unit 202 is connected to the power signal, and the second end of the second pull-up resistor unit 202 It is connected to the first end of the pull-down resistor unit 203, and the second end of the pull-down resistor unit 203 is connected to the ground signal.
  • the resistance value of the second pull-up resistor unit 202 is the standard resistance value, which is equivalent to the standard resistor and the pull-down resistor unit 203 being connected in series, and the standard resistor is closer to the power supply end.
  • the adjustment of the first impedance calibration code Pcode ⁇ 5:0> and the second impedance calibration code Ncode ⁇ 5:0> can be realized, and the impedance calibration process of the memory is completed.
  • the first impedance calibration code Pcode ⁇ 5:0> is adjusted from the first initial calibration value adapted to the current environment
  • the second impedance calibration code Ncode ⁇ 5:0> is adjusted from the second initial calibration value adapted to the current environment.
  • the initial calibration value is adjusted to be closer to the calibration result, so the impedance calibration is faster, saving power consumption and system time, and improving memory performance.
  • the calibration module 13 also includes an oscillation module 136 and a control module 137, the first counting module 131 is integrated with a first detection module, and the second counting module 134 is integrated with a second detection module; wherein,
  • the oscillation module 136 is configured to receive the calibration command signal ZQ start, and output the clock signal clk0 based on the calibration command signal ZQ start;
  • the control module 137 is configured to receive the clock signal clk0, and output the first counting clock signal pclk to the first counting module 131 based on the clock signal clk0;
  • the first detection module is configured to record the change of the first indication signal; if the change of the first indication signal meets the first preset condition, output the first termination signal Internal stop-1 to the control module 137;
  • the control module 137 is also configured to stop outputting the first counting clock signal pclk when receiving the first termination signal Internal stop-1; and based on the clock signal clk0, output the second counting clock signal nclk to the second counting module;
  • the second detection module is configured to record the change of the second indication signal; if the change of the first indication signal meets the second preset condition, output the second termination signal Internal stop-2 to the control module 137;
  • the control module 137 is also configured to stop outputting the second counting clock signal nclk when receiving the second termination signal Internal stop-2.
  • the first counting clock signal pclk and the second counting clock signal nclk can be determined through the oscillation module 136 and the control module 137 to serve as the counting clock for the impedance calibration process.
  • the first preset condition means that during three consecutive adjustments of the first impedance calibration code Pcode ⁇ 5:0>, the first indication signal continues to change from the first value to the second value.
  • the second value changes to the first value;
  • the second preset condition refers to that during the three consecutive adjustments of the second impedance calibration code Ncode ⁇ 5:0>, the second indication signal changes from the first value to the first value. After the second value, it continues to change from the second value to the first value.
  • the first value and the second value are different.
  • the first indication signal has a waveform change of 101, it means that the first voltage signal has been found.
  • the first impedance calibration code Pcode ⁇ 5:0> has been calibrated to the standard resistance value, thereby stopping the output of the first counting clock signal pclk, and the first impedance calibration code Pcode ⁇ 5: 0> no longer changes; similarly, during the adjustment process of the second impedance calibration code Ncode ⁇ 5:0>, if the second indication signal changes in waveform by 101, it can be considered that the pull-down impedance has been calibrated to the standard resistance value, so that Stop outputting the second counting clock signal pclk, and the second impedance calibration code Ncode ⁇ 5:0> no longer changes.
  • control module 137 is further configured to output the internal stop signal Internal stop to the oscillation module 136 upon receiving the second stop signal Internal stop-2;
  • the oscillation module 136 is also configured to receive an internal stop signal Internal stop and stop outputting the clock signal clk0 based on the internal stop signal Internal stop.
  • the oscillation module 136 is controlled to stop working through the internal termination signal Internal stop.
  • the first counting module 131 is also configured to receive the latch signal ZQ latch, and latch the first impedance calibration code Pcode ⁇ 5:0> based on the latch signal ZQ latch. ;
  • the second counting module 134 is also configured to receive the latch signal ZQ latch, and latch the second impedance calibration code Ncode ⁇ 5:0> based on the latch signal ZQ latch.
  • the calibration command signal ZQ start and the latch signal ZQ latch are received from the outside (hereinafter referred to as the system).
  • Figure 3 shows a signal timing diagram of impedance calibration.
  • the calibration control circuit 10 After the system sends the calibration command signal ZQ start, the calibration control circuit 10 generates the initial value of the first impedance calibration code Internal Pcode (fixed to 100000 in the related art, in the embodiment of the present disclosure to adapt to the current environment), start adjusting from the initial value of the first impedance calibration code until the calibration of the pull-up impedance is completed; after the pull-up impedance calibration is completed, the initial value of the second impedance calibration code Internal ncode (in the relevant is fixed at 100000 in technology, and in the embodiment of the present disclosure is the second initial calibration value adapted to the current environment), start adjusting from the initial value of the second impedance calibration code until the calibration of the pull-down impedance is completed; finally, after receiving the system sent After the latch signal ZQ latch, the first impedance calibration code Pcode ⁇
  • the calibration control circuit 10 may not be able to complete the calibration within the standard time, causing the calibration to fail and affecting the performance of the memory.
  • the first impedance calibration code Pcode ⁇ 5:0> and the second impedance calibration code Ncode ⁇ 5:0> are adjusted from the initial values adapted to the current environment, and the calibration takes less time. This can provide more time margin for the latch process.
  • the impedance calibration circuit 30 may include a first counting module, a first comparator, a second counting module, a second comparator, a plurality of resistors, an oscillation module and a control module.
  • the first impedance calibration code Pcode ⁇ 5:0> 100000
  • the codes start to change from a fixed initial value until the ideal impedance calibration effect is achieved.
  • the embodiment of the present disclosure provides an impedance calibration circuit 10 with a completely new architecture.
  • ZQ calibration i.e., the aforementioned impedance calibration
  • a corresponding initial calibration value is generated based on the actual temperature condition, so that the impedance calibration code is loaded into the initial calibration value serves as the starting point for the entire ZQ calibration process.
  • FIG. 5 shows a schematic diagram of the effect of the impedance calibration circuit provided by an embodiment of the present disclosure.
  • the horizontal axis (X-axis) refers to the temperature of the memory
  • the vertical axis (Y-axis) refers to the value of the impedance calibration code (taking the first impedance calibration code Pcode ⁇ 5:0> as an example).
  • Curve A is Refers to the change of the first impedance calibration code with temperature
  • curve B refers to the change of the first initial calibration value with temperature.
  • embodiments of the present disclosure provide an impedance calibration circuit that can generate an initial calibration value adapted to the current working environment, and uses the initial calibration value as the starting point of the entire calibration process, reducing the power consumption and time of impedance calibration. , while providing a better time margin for the latching of calibration results, improving memory performance.
  • FIG. 6 shows a schematic flow chart of an impedance calibration method provided by an embodiment of the present disclosure.
  • the method may include:
  • the impedance calibration method provided by the embodiment of the present disclosure is applied to the aforementioned impedance calibration circuit 10 .
  • the initial calibration value adapted to the current working environment is used as the starting point of the entire calibration process, which reduces the power consumption and time of impedance calibration and improves the performance of the memory.
  • the environmental parameter signal includes at least a temperature parameter signal. Determining environmental parameter signals through environmental detection processing includes:
  • the temperature of the environment where the impedance calibration circuit is located is detected to obtain a temperature signal; the temperature signal is decoded to obtain a temperature parameter signal.
  • the initial calibration value includes a first initial calibration value and a second initial calibration value; performing an impedance calibration process based on the initial calibration value includes:
  • the impedance calibration circuit includes a first pull-up resistor unit, and the first pull-up resistor unit is connected to a standard resistor. Accordingly, the adjustment of the first impedance calibration code to implement the calibration process of the pull-up impedance includes:
  • the impedance calibration circuit further includes a second pull-up resistor unit and a pull-down resistor unit, the resistance of the second pull-up resistor unit is controlled by the first impedance calibration code, and the second pull-up resistor unit and the pull-down resistor unit connect.
  • the adjustment of the second impedance calibration code to realize the calibration process of the pull-down impedance includes:
  • the resistance value of the pull-down resistor unit is adjusted based on the second impedance calibration code to output a second voltage signal; wherein, after the pull-up impedance calibration is completed, the resistance value of the second pull-up resistor unit is adjusted by the
  • the first impedance calibration code is calibrated to a standard resistance value; the second voltage signal is compared with the second reference signal to output a second indication signal; when the second indication signal is in the third level state, each time the second counting clock is detected One pulse of the signal, the second impedance calibration code is added; when the second indication signal is in the fourth level state, each pulse of the counting clock signal is detected, the second impedance calibration code is subtracted; When the change of the second indication signal meets the second preset condition, the output of the second counting clock signal is stopped, and the calibration process of the pull-down impedance is ended.
  • the method further includes: when receiving the latch signal, latching the first impedance calibration code and the second impedance calibration code.
  • the adjustment of the first impedance calibration code and the second impedance calibration code can be realized, and the impedance calibration process of the memory is completed.
  • the speed of impedance calibration is faster. Fast, saving power consumption and system time, and improving memory performance.
  • the embodiment of the present disclosure provides an impedance calibration method that can generate an initial calibration value adapted to the current working environment, and uses the initial calibration value as the starting point of the entire calibration process, reducing the power consumption and time of impedance calibration, and at the same time providing calibration results
  • the latch provides better time margin and improves memory performance.
  • FIG. 7 shows a schematic structural diagram of a memory 50 provided by an embodiment of the present disclosure.
  • the memory 50 includes the aforementioned impedance calibration circuit 10 .
  • the memory 50 since the memory 50 includes the aforementioned impedance calibration circuit 10, it can generate an initial calibration value adapted to the current working environment, and use the initial calibration value as the starting point of the entire calibration process, thereby reducing the power consumption and time of the impedance calibration, and at the same time providing the calibration result. Latches provide better time margins, improving memory performance.
  • Embodiments of the present disclosure provide an impedance calibration circuit, an impedance calibration method, and a memory.
  • the impedance calibration circuit includes a parameter module, an initial value generation module, and a calibration module; wherein the parameter module is configured to perform environment detection processing and output environmental parameter signals. ;
  • the initial value generation module is configured to receive the environmental parameter signal, and when receiving the calibration instruction signal, output the initial calibration value based on the environmental parameter signal;
  • the calibration module is configured to receive the initial calibration value, and when receiving the calibration instruction signal, The impedance calibration process is performed based on the initial calibration value. In this way, using the initial calibration value adapted to the current working environment for impedance calibration processing can reduce the power consumption and time of impedance calibration and improve the performance of the memory.

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Abstract

本公开实施例提供了一种阻抗校准电路、阻抗校准方法和存储器，该阻抗校准电路包括参数模块、初始值产生模块和校准模块；其中，参数模块，配置为执行环境检测处理，输出环境参数信号；初始值产生模块，配置为接收环境参数信号，并在接收到校准指令信号时，基于环境参数信号输出初始校准值；校准模块，配置为接收初始校准值，并在接收到校准指令信号时，基于初始校准值进行阻抗校准处理。

Description

一种阻抗校准电路、阻抗校准方法和存储器
相关申请的交叉引用
本公开基于申请号为202210714132.5、申请日为2022年06月22日、发明名称为“一种阻抗校准电路、阻抗校准方法和存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体存储器技术领域，尤其涉及一种阻抗校准电路、阻抗校准方法和存储器。
背景技术
在动态随机存取存储器(Dynamic Random Access Memory，DRAM)的工作过程中，需要通过一些电阻实现信号的输出驱动或者终结处理。应理解，由于电阻的阻值会随着环境参数(例如温度)的变化发生改变，所以存储器需要对相关电阻的阻值进行校准，以上称为ZQ校准。然而，目前的ZQ校准会占用过多的功耗和系统时间，降低了存储器的性能。
发明内容
本公开提供了一种阻抗校准电路、阻抗校准方法和存储器，能够减少阻抗校准的功耗和时间，提高存储器的性能。
本公开的技术方案是这样实现的：
第一方面，本公开实施例提供了一种阻抗校准电路，所述阻抗校准电路包括参数模块、初始值产生模块和校准模块；其中，所述参数模块，配置为执行环境检测处理，输出环境参数信号；所述初始值产生模块，配置为接收所述环境参数信号，并在接收到校准指令信号时，基于所述环境参数信号输出初始校准值；所述校准模块，配置为接收所述初始校准值，并在接收到所述校准指令信号时，基于所述初始校准值进行阻抗校准处理。
在一些实施例中，所述环境参数信号至少包括温度参数信号；所述参数模块包括温度传感器和译码模块；其中，所述温度传感器，配置为对所述阻抗校准电路所处的环境进行温度检测，输出温度信号；所述译码模块，配置为接收所述温度信号，对所述温度信号进行译码处理，输出所述温度参数信号。
在一些实施例中，所述初始校准值包括第一初始校准值和第二初始校准值；所述校准模块，具体配置为将所述第一初始校准值确定为第一阻抗校准码的初始值，将所述第二初始校准值确定为第二阻抗校准码的初始值；以及，对所述第一阻抗校准码进行调整，以实现上拉阻抗的校准；在上拉阻抗校准完成后，对所述第二阻抗校准码进行调整，以实现下拉阻抗的校准。
在一些实施例中，所述校准模块包括第一计数模块、第一比较器和电阻模块，所述电阻模块包括第一上拉电阻单元，且所述第一上拉电阻单元与标准电阻连接；其中，所述电阻模块，配置为接收所述第一阻抗校准码，基于所述第一阻抗校准码对所述第一上拉电阻单元的阻值进行控制，输出第一电压信号；所述第一比较器，配置为接收所述第一电压信号和第一参考信号，对所述第一电压信号与所述第一参考信号进行比较，输出第一指示信号；所述第一计数模块，配置为接收所述第一指示信号和第一计数时钟信号，在所述第一指示信号处于第一电平状态时，每检测到所述第一计数时钟信号的一个脉冲，对所述第一阻抗校准码进行加法处理；在所述第一指示信号处于第二电平状态时，每检测到所述第一计数时钟信号的一个脉冲，对所述第一阻抗校准码进行减法处理，以实现上拉阻抗的校准处理。
在一些实施例中，所述校准模块还包括第二计数模块和第二比较器，所述电阻模块还包括第二上拉电阻单元和下拉电阻单元，所述第二上拉电阻单元的阻值由所述第一阻抗校准码控制，且所述第二上拉电阻单元和所述下拉电阻单元连接；其中，所述电阻模块，还配置为在上拉阻抗校准完成后，基于所述第二阻抗校准码对所述下拉电阻单元的阻值进行控制，输出第二电压信号；其中，在上拉阻抗校准完成后，所述第二上拉电阻单元的阻值被所述第一阻抗校准码校准为标准阻值；所述第二比较器，配置为接收所述第二电压信号和第二参考信号，将所述第二电压信号与所述第二参考信号进行比较，输出第二指示信号；所述第二计数模块，配置为接收所述第二指示信号和第二计数时钟信号，在所述第二指示信号处于第三电平状态时，每检测到所述第二计数时钟信号的一个脉冲，对所述第二阻抗校准码进行加法处理；在所述第二指示信号处于第四电平状态时，每检测到所述第二计数时钟信号的一个脉冲，对所述第二阻抗校准码进行减法处理，以实现下拉阻抗的校准处理。
在一些实施例中，所述第一上拉电阻单元的控制端接收所述第一阻抗校准码，所述第一上拉电阻单元的第一端与电源信号连接，所述第一上拉电阻单元的第二端与所述标准电阻的第一端连接，所述标准电阻的第二端与地信号连接；所述第二上拉电阻单元的控制端接收所述第一阻抗校准码，所述第二上拉电阻单元的第一端与电源信号连接，所述第二上拉电阻单元的第二端与所述下拉电阻单元的第一端连接，所述下拉电阻单元的第二端与地信号连接。
在一些实施例中，所述校准模块还包括振荡模块和控制模块；所述第一计数模块集成有第一检测模块，所述第二计数模块集成有第二检测模块；其中，所述振荡模块，配置为接收所述校准指令信号，基于所述校准指令信号，输出时钟信号；所述控制模块，配置为接收所述时钟信号；基于所述时钟信号，向所述第一计数模块输出所述第一计数时钟信号；所述第一检测模块，配置为对所述第一指示信号的变化情况进行记录；若所述第一指示信号的变化情况符合第一预设条件，则向所述控制模块输出第一终止信号；所述控制模块，还配置为在接收到所述第一终止信号的情况下，停止输出所述第一计数时钟信号；以及基于所述时钟信号，向所述第二计数模块输出所述第二计数时钟信号；所述第二检测模块，配置为对所述第二指示信号的变化情况进行记录；若所述第一指示信号的变化情况符合第二预设条件，则向所述控制模块输出第二终止信号；所述控制模块，还配置为在接收到所述第二终止信号的情况下，停止输出所述第二计数时钟信号。
在一些实施例中，所述控制模块，还配置为在接收到所述第二终止信号的情况下，向所述振荡模块输出内部停止信号；所述振荡模块，还配置为接收所述内部停止信号，基于所述内部停止信号，停止输出所述时钟信号。
在一些实施例中，所述第一预设条件是指在第一阻抗校准码的连续3次调整过程中，第一指示信号在由第一值变化为第二值后继续由第二值变化为第一值；所述第二预设条件是指在第二阻抗校准码的连续3次调整过程中，第二指示信号在由第一值变化为第二值后继续由第二值变化为第一值。
在一些实施例中，所述第一计数模块，还配置为接收锁存信号，基于所述锁存信号，对所述第一阻抗校准码进行锁存；所述第二计数模块，还配置为接收所述锁存信号，基于所述锁存信号，对所述第二阻抗校准码进行锁存。
第二方面，本公开实施例提供了一种阻抗校准方法，应用于阻抗校准电路，所述方法包括：
通过环境检测处理，确定环境参数信号；
基于所述环境参数信号，确定初始校准值；
在接收到校准指令信号时，基于所述初始校准值进行阻抗校准处理。
在一些实施例中，所述环境参数信号至少包括温度参数信号；所述通过环境检测处理，确定环境参数信号，包括：
对所述阻抗校准电路所处的环境进行温度检测，得到温度信号；对所述温度信号进行译码处理，得到所述温度参数信号。
在一些实施例中，所述初始校准值包括第一初始校准值和第二初始校准值；所述基于所述初始校准值进行阻抗校准处理，包括：
将所述第一初始校准值确定为第一阻抗校准码的初始值，将所述第二 初始校准值确定为第二阻抗校准码的初始值；对所述第一阻抗校准码进行调整，以实现上拉阻抗的校准处理；在上拉阻抗校准完成后，对所述第二阻抗校准码进行调整，以实现下拉阻抗的校准处理。
在一些实施例中，所述阻抗校准电路包括第一上拉电阻单元，且所述第一上拉电阻单元与标准电阻连接，所述对所述第一阻抗校准码进行调整，以实现上拉阻抗的校准处理，包括：
基于所述第一阻抗校准码对所述第一上拉电阻单元的阻值进行调整，确定第一电压信号；将所述第一电压信号与第一参考信号进行比较，输出第一指示信号；在所述第一指示信号处于第一电平状态时，每检测到第一计数时钟信号的一个脉冲，对所述第一阻抗校准码进行加法处理；在所述第一指示信号处于第二电平状态时，每检测到所述第一计数时钟信号的一个脉冲，对所述第一阻抗校准码进行减法处理；在所述第一指示信号的变化情况符合第一预设条件的情况下，停止输出所述第一计数时钟信号，结束上拉阻抗的校准过程。
在一些实施例中，所述阻抗校准电路还包括第二上拉电阻单元和下拉电阻单元，所述第二上拉电阻单元的阻值由所述第一阻抗校准码控制，且所述第二上拉电阻单元和所述下拉电阻单元连接，所述对所述第二阻抗校准码进行调整，以实现下拉阻抗的校准处理，包括：
基于所述第二阻抗校准码对所述下拉电阻单元的阻值进行调整，输出第二电压信号；其中，在上拉阻抗校准完成后，所述第二上拉电阻单元的阻值被所述第一阻抗校准码校准为标准阻值；将所述第二电压信号与第二参考信号进行比较，输出第二指示信号；在所述第二指示信号处于第三电平状态时，每检测到第二计数时钟信号的一个脉冲，对所述第二阻抗校准码进行加法处理；在所述第二指示信号处于第四电平状态时，每检测到所述计数时钟信号的一个脉冲，对所述第二阻抗校准码进行减法处理；在所述第二指示信号的变化情况符合第二预设条件的情况下，停止输出所述第二计数时钟信号，结束下拉阻抗的校准过程。
在一些实施例中，所述方法还包括：在接收到锁存信号时，对所述第一阻抗校准码和所述第二阻抗校准码进行锁存。
第三方面，本公开实施例提供了一种存储器，该存储器包括如第一方面所述的阻抗校准电路。
本公开实施例提供了一种阻抗校准电路、阻抗校准方法和存储器，该阻抗校准电路包括参数模块、初始值产生模块和校准模块；其中，参数模块，配置为执行环境检测处理，输出环境参数信号；初始值产生模块，配置为接收环境参数信号，并在接收到校准指令信号时，基于环境参数信号输出初始校准值；校准模块，配置为接收初始校准值，并在接收到校准指令信号时，基于初始校准值进行阻抗校准处理。这样，利用适应于当前工作环境的初始校准值进行阻抗校准处理，能够减少阻抗校准的功耗和时间， 提高存储器的性能。
附图说明
图1为本公开实施例提供的一种阻抗校准电路的结构示意图；
图2为本公开实施例提供的一种阻抗校准电路的详细结构示意图；
图3为一种阻抗校准的信号时序示意图；
图4为相关技术提供的一种阻抗校准电路的结构示意图；
图5为本公开实施例提供的阻抗校准电路的效果示意图；
图6为本公开实施例提供的一种阻抗校准方法的流程示意图；
图7为本公开实施例提供的一种存储器的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅仅用于解释相关申请，而非对该申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关申请相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅是用于区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
以下为本公开实施例中涉及到的专业名词解释以及部分名词的对应关系：
存储器中存在一些用于输出驱动以及信号终结的电阻，这些电阻的阻值需要进行校准以匹配实际应用场景，以上阻抗校准过程也称为ZQ校准，用于控制电阻阻值的信号称为阻抗校准码(也可以称为ZQ校准码)。也就是说，在阻抗校准的过程中，通过调整阻抗校准码的大小来调整电阻的阻值，直至电阻的阻值符合要求。目前，在阻抗校准开始的时候，阻抗校准码需要从固定的初始值开始改变，导致阻抗校准会占用过多的功耗和系统时间，降低了存储器的性能。
基于此，本公开实施例提供了一种阻抗校准电路，该阻抗校准电路包括参数模块、初始值产生模块和校准模块；其中，参数模块，配置为执行 环境检测处理，输出环境参数信号；初始值产生模块，配置为接收环境参数信号，并在接收到校准指令信号时，基于环境参数信号输出初始校准值；校准模块，配置为接收初始校准值，并在接收到校准指令信号时，基于初始校准值进行阻抗校准处理。这样，利用适应于当前工作环境的初始校准值进行阻抗校准处理，能够减少阻抗校准的功耗和时间，提高存储器的性能。
下面将结合附图对本公开各实施例进行详细说明。
在本公开的一实施例中，参见图1，其示出了本公开实施例提供的一种阻抗校准电路10的组成结构示意图。如图1所示，该阻抗校准电路10可以包括参数模块11、初始值产生模块12和校准模块13；其中，
参数模块11，配置为执行环境检测处理，输出环境参数信号；
初始值产生模块12，配置为接收环境参数信号，并在接收到校准指令信号时，基于环境参数信号输出初始校准值；
校准模块13，配置为接收初始校准值，并在接收到校准指令信号时，基于初始校准值进行阻抗校准处理。
需要说明的是，本公开实施例的阻抗校准电路10应用于多种类型的存储器，例如DRAM、同步动态随机存取存储器(Synchronous Dynamic Random-Access Memory。
本公开实施例提供了一种全新架构的阻抗校准电路10，在阻抗校准开始时，通过参数模块11和初始值产生模块12能够产生适应于当前工作环境的初始校准值，从而利用初始校准值作为整个阻抗校准过程的起点，可以更快的调整到理想状态，能够减少阻抗校准的功耗和时间，同时为校准结果的锁存提供更好的时间裕度，提高存储器的性能。
在这里，校准指令信号指示开始执行阻抗校准过程，校准指令信号是从外部(或称为系统)接收的。环境参数信号包括以下信号的至少一种：温度参数信号、电压参数信号。
在一种具体的实施例中，如图2所示，环境参数信号至少包括温度参数信号；参数模块11包括温度传感器111和译码模块112；其中，
温度传感器111，配置为对阻抗校准电路10所处的环境进行温度检测，得到温度信号；
译码模块112，配置为接收温度信号，对温度信号进行译码处理，输出温度参数信号。
在这里，温度参数信号的本质是用于调整电阻阻抗的阻抗校准码。换句话说，译码模块112配置为将温度信号初步译码为温度参数信号，以便后续确定初始校准值。
需要说明的是，存储器的阻抗校准涉及到上拉阻抗(用于对信号进行输出驱动)的校准和下拉阻抗(用于对信号进行终结处理)的校准。因此，在一些实施例中，如图2所示，在一些实施例中，初始校准值包括第一初 始校准值TO_Pcode<5:0>和第二初始校准值TO_Ncode<5:0>，；
校准模块13，具体配置为在接收到校准指令信号时，将第一初始校准值TO_Pcode<5:0>确定为第一阻抗校准码Pcode<5:0>的初始值，将第二初始校准值TO_Ncode<5:0>确定为第二阻抗校准码Ncode<5:0>的初始值；以及，
对第一阻抗校准码Pcode<5:0>进行调整以实现上拉阻抗的校准处理；在上拉阻抗校准完成后，对第二阻抗校准码Ncode<5:0>进行调整，以实现下拉阻抗的校准处理。
需要说明的是，在图2中，第一阻抗校准码/第二阻抗校准码/第一校准初始值/第二校准初始值均由6个子信号构成，表示为<5:0>，但这并不构成具体限定。
也就是说，在相关技术中，第一阻抗校准码和第二阻抗校准码各自的初始值是固定不变的默认值。然而，在本公开实施例中，第一阻抗校准码和第二阻抗校准码各自的初始值均是基于当前工作环境确定的，可以更快的调整到理想状态，能够减少阻抗校准的功耗和时间，同时为校准结果的锁存提供更好的时间裕度，提高存储器的性能。
以下对上拉阻抗的校准处理和下拉阻抗的校准处理进行分别说明。
在一些实施例中，如图2所示，校准模块13包括第一计数模块131、第一比较器132和电阻模块133，电阻模块133包括第一上拉电阻单元201，且第一上拉电阻单元201与标准电阻204连接；其中，
电阻模块133，配置为接收第一阻抗校准码Pcode<5:0>，基于第一阻抗校准码Pcode<5:0>对第一上拉电阻单元201的阻值进行控制，输出第一电压信号；
第一比较器132，配置为接收第一电压信号和第一参考信号Vref1，对第一电压信号与第一参考信号Vref1进行比较，输出第一指示信号；
第一计数模块131，配置为接收第一指示信号和第一计数时钟信号pclk，在第一指示信号处于第一电平状态时，每检测到第一计数时钟信号pclk的一个脉冲，对第一阻抗校准码Pcode<5:0>进行加法处理；在第一指示信号处于第二电平状态时，每检测到第一计数时钟信号pclk的一个脉冲，对第一阻抗校准码Pcode<5:0>进行减法处理，以实现上拉阻抗的校准处理。
这样，第一电压信号能够指示第一上拉电阻单元的阻值与标准阻值之间的差异，从而决定第一阻抗校准码Pcode<5:0>的调整方向，构成反馈调整的回路。
需要说明的是，第一阻抗校准码Pcode<5:0>和第一上拉电阻单元的阻值之间的具体关系(即正比例关系或者负比例关系)需要取决于实际应用场景。第一电平状态和第二电平状态不同，其具体设定同样需要根据实际应用场景确定。在图2中，第一比较器132的正相输入端接收第一参考信号Vref1，第一比较器132的负相输入端接收第一电压信号，但这并不构成 具体限定，其具体连接关系同样需要根据实际应用场景确定。换句话说，只要符合一个自洽的电路调整逻辑，上拉阻抗的控制细节可以具有多种灵活的确定方式。
以下提供一种可行的控制细节：第一阻抗校准码Pcode<5:0>越大，第一上拉电阻单元201的阻值越小，同时第一电压信号越高；第一电平状态为高电平状态，第二电平状态为低电平状态。此时，在第一上拉电阻单元201的阻值小于标准电阻的情况下，第一电压信号的电压大于第一参考电压，此时第一指示信号处于低电平状态，从而第一阻抗校准码Pcode<5:0>进行减法处理，第一上拉电阻单元201的阻值升高；反之，在第一上拉电阻单元201的阻值大于标准电阻的情况下，第一电压信号的电压小于第一参考电压，此时第一指示信号处于高电平状态，从而第一阻抗校准码Pcode<5:0>进行加法处理，第一上拉电阻单元201的阻值降低。在这里，减法处理可以是减一、减二……等等，加法处理可以是加一、加二……等等，具体取决于实际应用场景。
类似地，在一些实施例中，如图2所示，校准模块13还包括第二计数模块134和第二比较器135，电阻模块133还包括第二上拉电阻单元202和下拉电阻单元203，第二上拉电阻单元202的阻值由第一阻抗校准码Pcode<5:0>控制，且第二上拉电阻单元202和下拉电阻单元203连接；其中，
电阻模块133，配置为在上拉阻抗校准完成后，基于所述第二阻抗校准码Ncode<5:0>对下拉电阻单元203的阻值进行控制，输出第二电压信号；其中，在上拉阻抗校准完成后，第二上拉电阻单元202的阻值被所述第一阻抗校准码Pcode<5:0>校准为标准阻值；
第二比较器135，配置为接收第二电压信号和第二参考信号Vref2，将第二电压信号与第二参考信号Vref2进行比较，输出第二指示信号；
第二计数模块134，配置为接收第二指示信号和第二计数时钟信号nclk，在第二指示信号处于第三电平状态时，每检测到第二计数时钟信号nclk的一个脉冲，对第二阻抗校准码Ncode<5:0>进行加法处理；在第二指示信号处于第四电平状态时，每检测到第二计数时钟信号nclk的一个脉冲，对第二阻抗校准码Ncode<5:0>进行减法处理，以实现下拉阻抗的校准处理。
需要说明的是，第二上拉电阻单元202和第一上拉电阻单元201可以视为具有相同的结构，其阻值具有相同的变化。所以，在上拉阻抗校准完成后，校准好的第一阻抗校准码Pcode<5:0>也可以将第二上拉电阻单元202校准到标准阻值。
也就是说，在阻抗校准的过程中，先利用第一上拉电阻单元201和标准电阻204形成通路，根据第一上拉电阻单元201和标准电阻之间的分压判断第一上拉电阻单元201的阻值大小，从而调整第一阻抗校准码Pcode<5:0>直至第一上拉电阻单元201的阻值为标准阻值。在上拉阻抗校准完成后，再利用第二上拉电阻单元202和下拉电阻单元203形成通路，此 时第二上拉电阻单元202可视为标准电阻，根据第二上拉电阻单元202和下拉电阻单元203之间的分压判断下拉电阻单元203的阻值大小，从而调整第二阻抗校准码Ncode<5:0>直至下拉电阻单元203的阻值为标准阻值。
在这里，第二上拉电阻单元202和第一上拉电阻单元201可以同时接收第一阻抗校准码Pcode<5:0>。请注意，在上拉阻抗的校准过程中，由于下拉电阻单元203不接通的，第二上拉电阻单元202虽然受到第一阻抗校准码Pcode<5:0>的控制，但是实际上也是不接通地端，避免功耗问题。除此之外，第二上拉电阻单元202和第一上拉电阻单元201也可以并非同时接收第一阻抗校准码Pcode<5:0>，即在上拉阻抗的校准完成之后，再将第一阻抗校准码Pcode<5:0>发送给第二上拉电阻单元202。
另外，与上拉阻抗的校准类似，在下拉阻抗的校准过程中，第二电压信号和下拉电阻单元的阻值的具体关系(即正比例关系或者负比例关系)同样取决于实际应用场景。第二电压信号能够指示下拉电阻与标准阻值之间的差异，从而决定第二阻抗校准码Ncode<5:0>的调整方向，构成反馈调整的回路。同样的，只要符合一个自洽的电路调整逻辑，下拉阻抗的控制细节可以具有多种灵活的确定方式。
以下提供一种可行的控制细节：第二阻抗校准码Ncode<5:0>越大，下拉电阻单元203的阻值越小，同时第二电压信号越低；第三电平状态为低电平状态，第四电平状态为高电平状态。此时，在下拉电阻单元203的阻值小于标准电阻的情况下，第二电压信号的电压小于第二参考电压，第二指示信号处于高电平状态，从而第二阻抗校准码Ncode<5:0>进行减法处理，下拉电阻单元203的阻值升高；反之，在下拉电阻单元203的阻值大于标准电阻的情况下，第二电压信号的电压大于第二参考电压，此时第二指示信号处于低电平状态，从而第二阻抗校准码Ncode<5:0>进行加法处理，下拉电阻单元203的阻值降低。
在一种具体的实施例中，如图2所示，第一上拉电阻单元201的控制端接收第一阻抗校准码Pcode<5:0>，且第一上拉电阻单元201的第一端与电源信号连接，第一上拉电阻单元201的第二端与标准电阻204的第一端连接，标准电阻204的第二端与地信号连接；
第二上拉电阻单元202的控制端接收第一阻抗校准码Pcode<5:0>，第二上拉电阻单元202的第一端与电源信号连接，第二上拉电阻单元202的第二端与下拉电阻单元203的第一端连接，下拉电阻单元203的第二端与地信号连接。
这样，由于标准电阻204和第一上拉电阻单元201串联，且第一上拉电阻单元201更加靠近电源端，如果第一上拉电阻单元201的阻值较大，此时第一上拉电阻单元201的分压越大，因此第一电压信号的电平值越低。类似地，在进行下拉电阻的校准时，可以认为第二上拉电阻单元202的阻值为标准阻值，相当于标准电阻和下拉电阻单元203串联，且标准电阻更 加靠近电源端，此时如果下拉电阻单元203的阻值加大，此时下拉电阻单元203的分压越大，因此第二电压信号的电平值越高。
这样，通过以上闭环校准逻辑，可以实现第一阻抗校准码Pcode<5:0>和第二阻抗校准码Ncode<5:0>的调整，完成存储器的阻抗校准处理。同时，由于第一阻抗校准码Pcode<5:0>是从适应于当前环境的第一初始校准值开始调整的，第二阻抗校准码Ncode<5:0>是从适应于当前环境的第二初始校准值开始调整的，更加接近于校准结果，因此阻抗校准的速度更快，节省了功耗和系统时间，提高存储器的性能。
在一些实施例中，校准模块13还包括振荡模块136和控制模块137，第一计数模块131集成有第一检测模块，第二计数模块134集成有第二检测模块；其中，
振荡模块136，配置为接收校准指令信号ZQ start，基于校准指令信号ZQ start，输出时钟信号clk0；
控制模块137，配置为接收时钟信号clk0，基于时钟信号clk0，向第一计数模块131输出第一计数时钟信号pclk；
第一检测模块，配置为对第一指示信号的变化情况进行记录；若第一指示信号的变化情况符合第一预设条件，则向控制模块137输出第一终止信号Internal stop-1；
控制模块137，还配置为在接收到第一终止信号Internal stop-1的情况下，停止输出第一计数时钟信号pclk；以及基于时钟信号clk0，向第二计数模块输出第二计数时钟信号nclk；
第二检测模块，配置为对第二指示信号的变化情况进行记录；若第一指示信号的变化情况符合第二预设条件，则向控制模块137输出第二终止信号Internal stop-2；
控制模块137，还配置为在接收到第二终止信号Internal stop-2的情况下，停止输出第二计数时钟信号nclk。
这样，通过振荡模块136和控制模块137可以确定第一计数时钟信号pclk和第二计数时钟信号nclk，以作为阻抗校准处理的计数时钟。
示例性的，所述第一预设条件是指在第一阻抗校准码Pcode<5:0>的连续3次调整过程中，第一指示信号在由第一值变化为第二值后继续由第二值变化为第一值；所述第二预设条件是指在第二阻抗校准码Ncode<5:0>的连续3次调整过程中，第二指示信号在由第一值变化为第二值后继续由第二值变化为第一值。在这里，第一值和第二值不同。
以第一值为1，第二值为0为例，在第一阻抗校准码Pcode<5:0>的调整过程中，如果第一指示信号出现101的波形变化，说明已经找到第一电压信号和第一参考信号相同的临界点，可以认为第一阻抗校准码Pcode<5:0>已经被校准为标准阻值，从而停止输出第一计数时钟信号pclk，第一阻抗校准码Pcode<5:0>不再变化；类似地，在第二阻抗校准码Ncode<5:0>的调 整过程中，如果第二指示信号出现101的波形变化，可以认为下拉阻抗已经被校准为标准阻值，从而停止输出第二计数时钟信号pclk，第二阻抗校准码Ncode<5:0>不再变化。
在一些实施例中，控制模块137，还配置为在接收到第二终止信号Internal stop-2的情况下，向振荡模块136输出内部终止信号Internal stop；
振荡模块136，还配置为接收内部终止信号Internal stop，基于内部终止信号Internal stop，停止输出时钟信号clk0。
这样，在下拉阻抗结束之后，不再需要时钟信号clk0，所以通过内部终止信号Internal stop控制振荡模块136停止工作。
在一些实施例中，所述第一计数模块131，还配置为接收锁存信号ZQ latch，基于所述锁存信号ZQ latch，对所述第一阻抗校准码Pcode<5:0>进行锁存；
所述第二计数模块134，还配置为接收所述锁存信号ZQ latch，基于所述锁存信号ZQ latch，对所述第二阻抗校准码Ncode<5:0>进行锁存。
在这里，校准指令信号ZQ start和锁存信号ZQ latch均是从外部(下成为系统)接收的。参见图3，其示出了一种阻抗校准的信号时序示意图。如图3所示，系统在发送校准指令信号ZQ start后，校准控制电路10产生第一阻抗校准码的初始值Internal Pcode(在相关技术中固定为100000，在本公开实施例中为适应于当前环境的第一初始校准值)，从第一阻抗校准码的初始值开始调整直至完成上拉阻抗的校准；在上拉阻抗校准完成后，产生第二阻抗校准码的初始值Internal ncode(在相关技术中固定为100000，在本公开实施例中为适应于当前环境的第二初始校准值)，从第二阻抗校准码的初始值开始调整直至完成下拉阻抗的校准；最后，在接收到系统发送的锁存信号ZQ latch之后，对第一阻抗校准码Pcode<5:0>和第二阻抗校准码Ncode<5:0>进行锁存。
一般来说，在系统发送校准指令信号ZQ start之后，必须完成校准以后才能发送锁存信号ZQ latch，然而校准的时间根据设计要求是不可以超过某一标准值的。也就是说，如果阻抗校准耗时较长，那么校准控制电路10可能无法在标准时间内完成校准，导致校准失败，影响存储器的性能。在本公开实施例中，第一阻抗校准码Pcode<5:0>和第二阻抗校准码Ncode<5:0>均是从适应于当前环境的初始值开始调整的，校准耗时更小，因此可以为锁存过程提供更多的时间裕量。
参见图4，其示出了相关技术中提供的一种阻抗校准电路30的结构示意图。如图4所示，阻抗校准电路30可以包括第一计数模块、第一比较器、第二计数模块、第二比较器、多个电阻、振荡模块和控制模块。在相关技术中，在ZQ校准开始时，第一阻抗校准码Pcode<5:0>＝100000，第二阻抗校准码Ncode<5:0>＝100000，即第一阻抗校准码和第二阻抗校准码均从固定的初始值开始改变，直至达到理想的阻抗校准效果。相对的，本公开实施 例提供了一种全新架构的阻抗校准电路10，在ZQ校准(即前述的阻抗校准)开始时，基于实际温度情况产生对应的初始校准值，从而阻抗校准码加载初始校准值作为整个ZQ校准过程的起点。在保证ZQ校准的功能和性能的前提下，减少ZQ校准时间，同时为阻抗校准码的锁存提供足够的时间裕量。
具体来说，参见图5，其示出了本公开实施例提供的阻抗校准电路的效果示意图。在图5中，水平轴(X轴)是指存储器的温度，垂直轴(Y轴)是指阻抗校准码(以第一阻抗校准码Pcode<5:0>为例)的数值，曲线A是指第一阻抗校准码随温度的变化情况，曲线B是指第一初始校准值随温度的变化情况。如图5所示，假设在校准指令信号到来时，存储器的当前温度为t0，那么对于相关技术中的阻抗校准电路30，其需要从Pcode<5:0>＝10000开始调整至目标值ZQ_Pcode，耗时为T1，对于本公开实施例中的阻抗校准电路10，仅需要从Pcode<5:0>＝TO_Pcode<5:0>调整至目标值ZQ_Pcode，耗时为T2。因此，本公开实施例中的阻抗校准电路10的阻抗校准过程的耗时更短，同时功耗更低。
综上所述，本公开实施例提供了一种阻抗校准电，能够产生适应于当前工作环境的初始校准值，并利用初始校准值作为整个校准过程的起点，减少了阻抗校准的功耗和时间，同时为校准结果的锁存提供更好的时间裕度，提高了存储器的性能。
在本公开的另一实施例中，参见图6，其示出了本公开实施例提供的一种阻抗校准方法的流程示意图。如图6所示，该方法可以包括：
S401：通过环境检测处理，确定环境参数信号。
S402：基于环境参数信号，确定初始校准值。
S403：在接收到校准指令信号时，基于初始校准值进行阻抗校准处理。
需要说明的是，本公开实施例提供的阻抗校准方法应用于前述的阻抗校准电路10。这样，在本公开实施例提供的阻抗校准方法中，利用适应于当前工作环境的初始校准值作为整个校准过程的起点，减少了阻抗校准的功耗和时间，提高了存储器的性能。
在一些实施例中，环境参数信号至少包括温度参数信号。所述通过环境检测处理，确定环境参数信号，包括：
对阻抗校准电路所处的环境进行温度检测，得到温度信号；对温度信号进行译码处理，得到温度参数信号。
在一些实施例中，所述初始校准值包括第一初始校准值和第二初始校准值；基于初始校准值进行阻抗校准处理，包括：
将第一初始校准值确定为第一阻抗校准码的初始值，将第二初始校准值确定为第二阻抗校准码的初始值；对第一阻抗校准码进行调整，以实现上拉阻抗的校准处理；在上拉阻抗校准完成后，对第二阻抗校准码进行调整，以实现下拉阻抗的校准处理。
在一些实施例中，阻抗校准电路包括第一上拉电阻单元，且第一上拉电阻单元与标准电阻连接。相应地，所述对第一阻抗校准码进行调整，以实现上拉阻抗的校准处理，包括：
基于第一阻抗校准码对第一上拉电阻单元的阻值进行调整，确定第一电压信号；将第一电压信号与第一参考信号进行比较，输出第一指示信号；在第一指示信号处于第一电平状态时，每检测到第一计数时钟信号的一个脉冲，对第一阻抗校准码进行加法处理；在第一指示信号处于第二电平状态时，每检测到第一计数时钟信号的一个脉冲，对第一阻抗校准码进行减法处理；在第一指示信号的变化情况符合第一预设条件的情况下，停止输出第一计数时钟信号，结束上拉阻抗的校准过程。
在一些实施例中，阻抗校准电路还包括第二上拉电阻单元和下拉电阻单元，第二上拉电阻单元的阻值由第一阻抗校准码控制，且第二上拉电阻单元和下拉电阻单元连接。相应的，所述对第二阻抗校准码进行调整，以实现下拉阻抗的校准处理，包括：
基于所述第二阻抗校准码对所述下拉电阻单元的阻值进行调整，输出第二电压信号；其中，在上拉阻抗校准完成后，所述第二上拉电阻单元的阻值被所述第一阻抗校准码校准为标准阻值；将第二电压信号与第二参考信号进行比较，输出第二指示信号；在第二指示信号处于第三电平状态时，每检测到第二计数时钟信号的一个脉冲，对第二阻抗校准码进行加法处理；在第二指示信号处于第四电平状态时，每检测到计数时钟信号的一个脉冲，对第二阻抗校准码进行减法处理；在第二指示信号的变化情况符合第二预设条件的情况下，停止输出第二计数时钟信号，结束下拉阻抗的校准过程。
在一些实施例中，该方法还包括：在接收到锁存信号时，对第一阻抗校准码和第二阻抗校准码进行锁存。
这样，通过以上闭环校准逻辑，可以实现第一阻抗校准码和第二阻抗校准码的调整，完成存储器的阻抗校准处理。同时，由于第一阻抗校准码是从应用于当前环境的第一初始校准值开始调整的，第二阻抗校准码是从应用于当前环境的第二初始校准值开始调整的，阻抗校准的速度更快，节省了功耗和系统时间，提高了存储器的性能。
本公开实施例提供了一种阻抗校准方法，能够产生适应于当前工作环境的初始校准值，并利用初始校准值作为整个校准过程的起点，减少了阻抗校准的功耗和时间，同时为校准结果的锁存提供更好的时间裕度度，提高了存储器的性能。
在本公开的又一实施例中，参见图7，其示出了本公开实施例提供的一种存储器50的组成结构示意图。如图7所示，该存储器50包括前述的阻抗校准电路10。
由于存储器50包括前述的阻抗校准电路10，能够产生适应于当前工作环境的初始校准值，并利用初始校准值作为整个校准过程的起点，减少了 阻抗校准的功耗和时间，同时为校准结果的锁存提供更好的时间裕度，提高了存储器的性能。
以上，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围。需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种阻抗校准电路、阻抗校准方法和存储器，该阻抗校准电路包括参数模块、初始值产生模块和校准模块；其中，参数模块，配置为执行环境检测处理，输出环境参数信号；初始值产生模块，配置为接收环境参数信号，并在接收到校准指令信号时，基于环境参数信号输出初始校准值；校准模块，配置为接收初始校准值，并在接收到校准指令信号时，基于初始校准值进行阻抗校准处理。这样，利用适应于当前工作环境的初始校准值进行阻抗校准处理，能够减少阻抗校准的功耗和时间，提高存储器的性能。

Claims (17)

  1. 一种阻抗校准电路，所述阻抗校准电路包括参数模块、初始值产生模块和校准模块；其中，
    所述参数模块，配置为执行环境检测处理，输出环境参数信号；
    所述初始值产生模块，配置为接收所述环境参数信号，并在接收到校准指令信号时，基于所述环境参数信号输出初始校准值；
    所述校准模块，配置为接收所述初始校准值，并在接收到所述校准指令信号时，基于所述初始校准值进行阻抗校准处理。
  2. 根据权利要求1所述的阻抗校准电路，其中，所述环境参数信号至少包括温度参数信号；所述参数模块包括温度传感器和译码模块；其中，
    所述温度传感器，配置为对所述阻抗校准电路所处的环境进行温度检测，输出温度信号；
    所述译码模块，配置为接收所述温度信号，对所述温度信号进行译码处理，输出所述温度参数信号。
  3. 根据权利要求1所述的阻抗校准电路，其中，所述初始校准值包括第一初始校准值和第二初始校准值；
    所述校准模块，具体配置为将所述第一初始校准值确定为第一阻抗校准码的初始值，将所述第二初始校准值确定为第二阻抗校准码的初始值；以及，
    对所述第一阻抗校准码进行调整，以实现上拉阻抗的校准；在上拉阻抗校准完成后，对所述第二阻抗校准码进行调整，以实现下拉阻抗的校准。
  4. 根据权利要求3所述的阻抗校准电路，其中，所述校准模块包括第一计数模块、第一比较器和电阻模块，所述电阻模块包括第一上拉电阻单元，且所述第一上拉电阻单元与标准电阻连接；其中，
    所述电阻模块，配置为接收所述第一阻抗校准码，基于所述第一阻抗校准码对所述第一上拉电阻单元的阻值进行控制，输出第一电压信号；
    所述第一比较器，配置为接收所述第一电压信号和第一参考信号，对所述第一电压信号与所述第一参考信号进行比较，输出第一指示信号；
    所述第一计数模块，配置为接收所述第一指示信号和第一计数时钟信号，在所述第一指示信号处于第一电平状态时，每检测到所述第一计数时钟信号的一个脉冲，对所述第一阻抗校准码进行加法处理；在所述第一指示信号处于第二电平状态时，每检测到所述第一计数时钟信号的一个脉冲，对所述第一阻抗校准码进行减法处理，以实现上拉阻抗的校准处理。
  5. 根据权利要求4所述的阻抗校准电路，其中，所述校准模块还包括第二计数模块和第二比较器，所述电阻模块还包括第二上拉电阻单元和下拉电阻单元，所述第二上拉电阻单元的阻值由所述第一阻抗校准码控制，且 所述第二上拉电阻单元和所述下拉电阻单元连接；其中，
    所述电阻模块，还配置为在上拉阻抗校准完成后，基于所述第二阻抗校准码对所述下拉电阻单元的阻值进行控制，输出第二电压信号；其中，在上拉阻抗校准完成后，所述第二上拉电阻单元的阻值被所述第一阻抗校准码校准为标准阻值；
    所述第二比较器，配置为接收所述第二电压信号和第二参考信号，将所述第二电压信号与所述第二参考信号进行比较，输出第二指示信号；
    所述第二计数模块，配置为接收所述第二指示信号和第二计数时钟信号，在所述第二指示信号处于第三电平状态时，每检测到所述第二计数时钟信号的一个脉冲，对所述第二阻抗校准码进行加法处理；在所述第二指示信号处于第四电平状态时，每检测到所述第二计数时钟信号的一个脉冲，对所述第二阻抗校准码进行减法处理，以实现下拉阻抗的校准处理。
  6. 根据权利要求5所述的阻抗校准电路，其中，所述第一上拉电阻单元的控制端接收所述第一阻抗校准码，所述第一上拉电阻单元的第一端与电源信号连接，所述第一上拉电阻单元的第二端与所述标准电阻的第一端连接，所述标准电阻的第二端与地信号连接；
    所述第二上拉电阻单元的控制端接收所述第一阻抗校准码，所述第二上拉电阻单元的第一端与电源信号连接，所述第二上拉电阻单元的第二端与所述下拉电阻单元的第一端连接，所述下拉电阻单元的第二端与地信号连接。
  7. 根据权利要求5所述的阻抗校准电路，其中，所述校准模块还包括振荡模块和控制模块；所述第一计数模块集成有第一检测模块，所述第二计数模块集成有第二检测模块；其中，
    所述振荡模块，配置为接收所述校准指令信号，基于所述校准指令信号，输出时钟信号；
    所述控制模块，配置为接收所述时钟信号；基于所述时钟信号，向所述第一计数模块输出所述第一计数时钟信号；
    所述第一检测模块，配置为对所述第一指示信号的变化情况进行记录；若所述第一指示信号的变化情况符合第一预设条件，则向所述控制模块输出第一终止信号；
    所述控制模块，还配置为在接收到所述第一终止信号的情况下，停止输出所述第一计数时钟信号；以及基于所述时钟信号，向所述第二计数模块输出所述第二计数时钟信号；
    所述第二检测模块，配置为对所述第二指示信号的变化情况进行记录；若所述第一指示信号的变化情况符合第二预设条件，则向所述控制模块输出第二终止信号；
    所述控制模块，还配置为在接收到所述第二终止信号的情况下，停止输出所述第二计数时钟信号。
  8. 根据权利要求7所述的阻抗校准电路，其中，
    所述控制模块，还配置为在接收到所述第二终止信号的情况下，向所述振荡模块输出内部停止信号；
    所述振荡模块，还配置为接收所述内部停止信号，基于所述内部停止信号，停止输出所述时钟信号。
  9. 根据权利要求7所述的阻抗校准电路，其中，
    所述第一预设条件是指在第一阻抗校准码的连续3次调整过程中，第一指示信号在由第一值变化为第二值后继续由第二值变化为第一值；
    所述第二预设条件是指在第二阻抗校准码的连续3次调整过程中，第二指示信号在由第一值变化为第二值后继续由第二值变化为第一值。
  10. 根据权利要求5-9任一项所述的阻抗校准电路，其中，
    所述第一计数模块，还配置为接收锁存信号，基于所述锁存信号，对所述第一阻抗校准码进行锁存；
    所述第二计数模块，还配置为接收所述锁存信号，基于所述锁存信号，对所述第二阻抗校准码进行锁存。
  11. 一种阻抗校准方法，应用于阻抗校准电路，所述方法包括：
    通过环境检测处理，确定环境参数信号；
    基于所述环境参数信号，确定初始校准值；
    在接收到校准指令信号时，基于所述初始校准值进行阻抗校准处理。
  12. 根据权利要求11所述的阻抗校准方法，其中，所述环境参数信号至少包括温度参数信号；所述通过环境检测处理，确定环境参数信号，包括：
    对所述阻抗校准电路所处的环境进行温度检测，得到温度信号；
    对所述温度信号进行译码处理，得到所述温度参数信号。
  13. 根据权利要求11所述的阻抗校准方法，其中，所述初始校准值包括第一初始校准值和第二初始校准值；所述基于所述初始校准值进行阻抗校准处理，包括：
    将所述第一初始校准值确定为第一阻抗校准码的初始值，将所述第二初始校准值确定为第二阻抗校准码的初始值；
    对所述第一阻抗校准码进行调整，以实现上拉阻抗的校准处理；
    在上拉阻抗校准完成后，对所述第二阻抗校准码进行调整，以实现下拉阻抗的校准处理。
  14. 根据权利要求13所述的阻抗校准方法，其中，所述阻抗校准电路包括第一上拉电阻单元，且所述第一上拉电阻单元与标准电阻连接，所述对所述第一阻抗校准码进行调整，以实现上拉阻抗的校准处理，包括：
    基于所述第一阻抗校准码对所述第一上拉电阻单元的阻值进行调整，确定第一电压信号；
    将所述第一电压信号与第一参考信号进行比较，输出第一指示信号；
    在所述第一指示信号处于第一电平状态时，每检测到第一计数时钟信 号的一个脉冲，对所述第一阻抗校准码进行加法处理；在所述第一指示信号处于第二电平状态时，每检测到所述第一计数时钟信号的一个脉冲，对所述第一阻抗校准码进行减法处理；
    在所述第一指示信号的变化情况符合第一预设条件的情况下，停止输出所述第一计数时钟信号，结束上拉阻抗的校准过程。
  15. 根据权利要求13所述的阻抗校准方法，其中，所述阻抗校准电路还包括第二上拉电阻单元和下拉电阻单元，所述第二上拉电阻单元的阻值由所述第一阻抗校准码控制，且所述第二上拉电阻单元和所述下拉电阻单元连接，所述对所述第二阻抗校准码进行调整，以实现下拉阻抗的校准处理，包括：
    基于所述第二阻抗校准码对所述下拉电阻单元的阻值进行调整，输出第二电压信号；其中，在上拉阻抗校准完成后，所述第二上拉电阻单元的阻值被所述第一阻抗校准码校准为标准阻值；
    将所述第二电压信号与第二参考信号进行比较，输出第二指示信号；
    在所述第二指示信号处于第三电平状态时，每检测到第二计数时钟信号的一个脉冲，对所述第二阻抗校准码进行加法处理；在所述第二指示信号处于第四电平状态时，每检测到所述计数时钟信号的一个脉冲，对所述第二阻抗校准码进行减法处理；
    在所述第二指示信号的变化情况符合第二预设条件的情况下，停止输出所述第二计数时钟信号，结束下拉阻抗的校准过程。
  16. 根据权利要求13所述的阻抗校准方法，其中，所述方法还包括：
    在接收到锁存信号时，对所述第一阻抗校准码和所述第二阻抗校准码进行锁存。
  17. 一种半导体存储器，所述半导体存储器包括如权利要求1至10任一项所述的阻抗校准电路。
PCT/CN2022/103676 2022-06-22 2022-07-04 一种阻抗校准电路、阻抗校准方法和存储器 WO2023245729A1 (zh)

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