WO2023245508A1 - 像素电路，其驱动方法及显示装置 - Google Patents

像素电路，其驱动方法及显示装置 Download PDF

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Publication number
WO2023245508A1
WO2023245508A1 PCT/CN2022/100510 CN2022100510W WO2023245508A1 WO 2023245508 A1 WO2023245508 A1 WO 2023245508A1 CN 2022100510 W CN2022100510 W CN 2022100510W WO 2023245508 A1 WO2023245508 A1 WO 2023245508A1
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Prior art keywords
terminal
signal
control
input
circuit
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PCT/CN2022/100510
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English (en)
French (fr)
Inventor
丛宁
玄明花
张粲
王灿
牛晋飞
张晶晶
韩承佑
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280001851.0A priority Critical patent/CN117813643A/zh
Priority to PCT/CN2022/100510 priority patent/WO2023245508A1/zh
Publication of WO2023245508A1 publication Critical patent/WO2023245508A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present disclosure relates to the field of display technology, and in particular to pixel circuits, driving methods thereof and display devices.
  • micro light-emitting diode technology due to the sub-millimeter light-emitting diode (Mini Light Emitting Diode, Mini LED) (size is about 100-300 ⁇ m), the micro light-emitting diode (Micro Light Emitting Diode, Micro LED) (size is less than 100 ⁇ m) , has the characteristics of high luminous efficiency, high brightness, high resolution and fast response speed, and has been widely used in display devices.
  • Mini LED sub-millimeter light-emitting diode
  • Micro LED Micro Light Emitting Diode, Micro LED
  • the input circuit is respectively coupled to the first data signal terminal, 2 N -1 first scanning signal terminals and 2 N -1 input nodes, and the 2 N -1 first scanning signal terminals are connected to the 2 N -1 first scanning signal terminals.
  • -1 input nodes correspond one to one; the input circuit is configured to respond to the signals loaded in the 2 N -1 first scan signal terminals and input the data signals loaded on the first data signal terminals into the corresponding Input node;
  • N is an integer greater than 1;
  • control circuit respectively coupled to 2 N -1 input nodes; the control circuit is configured to respond to signals from at least two input nodes among the 2 N -1 input nodes, respectively control the 2 N control nodes signal of;
  • the output circuit is respectively coupled to the 2 N control nodes, the 2 N selection control signal terminals and the output node, and the 2 N control nodes correspond to the 2 N selection control signal terminals one by one;
  • the output circuit is configured to provide a signal of the m-th selection control signal terminal among the 2 N selection control signal terminals to the output node in response to a signal of the m-th control node among the 2 N control nodes. ;1 ⁇ m ⁇ 2 N , and m is an integer;
  • the light-emitting driving circuit is respectively coupled to the output node and the device to be driven; the light-emitting driving circuit is configured to drive the device to be driven to operate in response to a signal from the output node.
  • the input circuit includes: 2 N -1 input sub-circuits; the k-th input sub-circuit among the 2 N -1 input sub-circuits is connected to the 2 N -1 input sub-circuits respectively.
  • the k-th first scan signal terminal among the first scan signal terminals is coupled to the k-th input node among the 2 N -1 input nodes;
  • the k-th input sub-circuit is configured to input the data signal loaded on the first data signal terminal into the k-th input node in response to the signal loaded on the k-th first scan signal terminal; 1 ⁇ k ⁇ 2 N -1, and k is an integer.
  • the k-th input sub-circuit includes a k-th first transistor
  • the control terminal of the k-th first transistor is coupled to the k-th first scan signal terminal, and the first terminal of the k-th first transistor is coupled to the first data signal terminal.
  • the second terminal of the k-th first transistor is coupled to the k-th input node.
  • control circuit includes: 2 N -1 control sub-circuits, and the input terminals of the 2 N -1 control sub-circuits are coupled to the 2 N -1 input nodes in a one-to-one correspondence. catch;
  • the 2 N -1 control sub-circuits are defined as the first-level control sub-circuit to the N-th level control sub-circuit; wherein each of the N-th level control sub-circuit and two of the 2 N control nodes control The nodes correspond one to one, and the input end of the N-th level control sub-circuit is coupled to the corresponding one of the two control nodes, and the output end of the N-th level control sub-circuit is connected to the corresponding one of the two control nodes. the other of the two control nodes is coupled;
  • Each q-1th level control sub-circuit corresponds to two q-th level control sub-circuits, and the control end of one q-th level control sub-circuit among the two q-th level control sub-circuits is connected to the corresponding q-th level control sub-circuit.
  • the output end of the 1st level control subcircuit is coupled, and the control end of another qth level control subcircuit is coupled with the corresponding input end of the q-1th level control subcircuit;
  • the qth level control subcircuit is Configured to provide a signal at the input terminal to its output terminal in response to a signal loaded on its control terminal; 2 ⁇ q ⁇ N, and q is an integer.
  • the first-level control subcircuit includes a first latch
  • the input terminal of the first latch serves as the input terminal of the first-level control sub-circuit
  • the output terminal of the first latch serves as the output terminal of the first-level control sub-circuit
  • the first latch includes: a first inverter and a second inverter;
  • the input terminal of the first inverter serves as the input terminal of the first latch, and the output terminal of the first inverter serves as the output terminal of the first latch;
  • the input terminal of the second inverter is coupled to the output terminal of the first inverter, and the output terminal of the second inverter is coupled to the input terminal of the first inverter.
  • the qth-level control subcircuit includes: a second latch
  • the control end of the second latch serves as the control end of the q-th level control sub-circuit, and the input end of the second latch serves as the input end of the q-th level control sub-circuit.
  • the output terminal of the latch serves as the output terminal of the q-th stage control sub-circuit.
  • the second latch includes: a first three-state gate and a second three-state gate;
  • the control end of the first three-state gate serves as the control end of the second latch
  • the input end of the first three-state gate serves as the input end of the second latch
  • the first three-state gate The output terminal of the gate serves as the output terminal of the second latch
  • the control terminal of the second three-state gate is coupled to the control terminal of the first three-state gate, and the input terminal of the second three-state gate is coupled to the output terminal of the first three-state gate.
  • the output terminal of the second three-state gate is coupled to the input terminal of the first three-state gate.
  • the output circuit includes: 2 N output sub-circuits; the m-th output sub-circuit among the 2 N output sub-circuits is connected with the m-th control node, the m-th selection The control signal terminal is coupled to the output node;
  • the mth output sub-circuit is configured to provide the signal of the mth selection control signal terminal to the output node in response to the signal of the mth control node.
  • the m-th output sub-circuit includes an m-th second transistor
  • the control terminal of the m-th second transistor is coupled to the m-th control node, the first terminal of the m-th second transistor is coupled to the m-th selection control signal terminal, and the m-th second transistor is coupled to the m-th selection control signal terminal.
  • the second terminals of the m second transistors are coupled to the output node.
  • the light-emitting driving circuit includes: a light-emitting control subcircuit
  • the lighting control sub-circuit is coupled to the output node, the lighting control signal terminal and the device to be driven respectively; the lighting control sub-circuit is configured to respond to signals from the lighting control signal terminal and the output node , driving the device to be driven to work.
  • the lighting control sub-circuit includes a third transistor; the control terminal of the third transistor is coupled to the lighting control signal terminal, and the first terminal of the third transistor is connected to the output The node is coupled, and the second terminal of the third transistor is coupled with the first terminal of the device to be driven;
  • the second terminal of the device to be driven is coupled to the first reference power terminal.
  • the light emission control sub-circuit is also coupled to the second scan signal terminal, the second data signal terminal, and the reset signal terminal;
  • the lighting control sub-circuit is configured to respond to the signal of the lighting control signal terminal, the signal of the output node, the signal loaded on the second scan signal terminal, the data signal loaded on the second data signal terminal, the The signal loaded on the reset signal terminal drives the device to be driven to work.
  • the light emission control sub-circuit includes: a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a storage capacitor and a driving transistor;
  • the control terminal of the fourth transistor is coupled to the light-emitting control signal terminal, the first terminal of the fourth transistor is coupled to the output node, and the second terminal of the fourth transistor is coupled to the fifth transistor.
  • the control terminal is coupled;
  • the first end of the fifth transistor is coupled to the second end of the driving transistor, and the first end of the fifth transistor is coupled to the first end of the device to be driven;
  • the control terminal of the sixth transistor is coupled to the second scan signal terminal, the first terminal of the sixth transistor is coupled to the reset signal terminal, and the second terminal of the sixth transistor is coupled to the driving signal terminal.
  • the second terminal of the transistor is coupled;
  • the control terminal of the seventh transistor is coupled to the second scan signal terminal, the first terminal of the seventh transistor is coupled to the second data signal terminal, and the second terminal of the seventh transistor is coupled to the second scan signal terminal.
  • the control terminal of the driving transistor is coupled;
  • the second terminal of the device to be driven is coupled to the first reference power terminal.
  • a display device provided by an embodiment of the present disclosure includes a plurality of the above-mentioned pixel circuits.
  • Embodiments of the present disclosure provide a driving method for a pixel circuit, wherein the driving method is used to drive the above-mentioned pixel circuit, and the driving method includes:
  • a valid level signal is loaded on one of the 2 N -1 first scanning signal terminals, an invalid level signal is loaded on the remaining first scanning signal terminals, and the first data signal terminal is loaded with a valid level signal.
  • the loaded data signal input corresponds to the input node of the first scanning signal end loaded with the effective level;
  • the control circuit responds to the signals of at least two input nodes among the 2 N -1 input nodes, and controls the signals of the 2 N control nodes respectively;
  • the output circuit responds to the signal of the m-th control node among the 2 N control nodes and provides the signal of the m-th selection control signal terminal among the 2 N selection control signal terminals to the output node;
  • the light-emitting driving circuit drives the device to be driven to operate in response to the signal from the output node.
  • the voltage amplitude of the signal loaded on each of the selection control signal terminals is different.
  • the duty cycle of the signal loaded on each of the selection control signal terminals is different.
  • the signal loaded on each of the 2 N selection control signal terminals is a DC voltage signal or a pulse width modulation signal.
  • Figure 1 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure
  • Figure 3 is another structural schematic diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic diagram of some specific structures of a pixel circuit provided by an embodiment of the present disclosure.
  • Figure 5 is some flowcharts of driving methods for pixel circuits provided by embodiments of the present disclosure.
  • Figure 6 is some signal timing diagrams provided by embodiments of the present disclosure.
  • Figure 7 is some level diagrams provided by embodiments of the present disclosure.
  • Figure 8a is another signal timing diagram provided by an embodiment of the present disclosure.
  • Figure 8b is some further signal timing diagrams provided by embodiments of the present disclosure.
  • Figure 9 is another level diagram provided by an embodiment of the present disclosure.
  • Figure 10 is another specific structural schematic diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • Figure 11 is some further signal timing diagrams provided by embodiments of the present disclosure.
  • a display device includes a plurality of pixel units arranged in an array.
  • each pixel unit is provided with at least one light-emitting device and a pixel circuit coupled to each light-emitting device.
  • the pixel circuit is used to provide voltage to the coupled light-emitting device to Control the light emitting device to emit light, thereby realizing the display of images.
  • each pixel unit is provided with a light-emitting device and a pixel circuit coupled to the light-emitting device.
  • the structure of the pixel circuit in the light-emitting device display panel in the related art is relatively complex.
  • the pixel circuit provided by the embodiment of the present disclosure includes: an input circuit 10 , a control circuit 20 , an output circuit 30 and a light-emitting driving circuit 40 .
  • the input circuit 10 is respectively connected with the first data signal terminal DA1, 2 N -1 first scanning signal terminals (such as GA1_1, GA1_2,... GA1_2 N -1) and 2 N -1 input nodes (such as N1_1, N1_2 ,...N1_2 N -1) coupling.
  • the control circuit 20 is coupled to 2 N -1 input nodes (such as N1_1, N1_2,...N1_2 N -1) respectively.
  • the output circuit 30 is coupled to 2 N control nodes (such as N2_1, N2_2,... N1_2 N ), 2 N selection control signal terminals (such as CX_1, CX_2,... CX_2 N ) and the output node N3 respectively.
  • the light-emitting driving circuit 40 is coupled to the output node N3 and the device to be driven respectively.
  • 2 N -1 first scanning signal terminals (such as GA1_1, GA1_2,... GA1_2 N -1) correspond to 2 N -1 input nodes (such as N1_1, N1_2,...
  • the input circuit 10 is configured to input the data signal loaded on the first data signal terminal DA1 in response to the signals loaded on the 2 N -1 first scan signal terminals (such as GA1_1, GA1_2,... GA1_2 N -1).
  • Corresponding input nodes (such as N1_1, N1_2,...N1_2 N -1).
  • the control circuit 20 is configured to respectively control 2 N control nodes (such as N2_1, N2_2) in response to signals from at least two input nodes among the 2 N -1 input nodes (such as N1_1, N1_2, ... N1_2 N -1) ,...N2_2 N ) signal.
  • the output circuit 30 is configured to respond to the signal of the mth control node N2_m among the 2 N control nodes (such as N2_1, N2_2,... N2_2N ), and switch the 2 N selection control signal terminals (such as CX_1, CX_2,... ...CX_2 N )
  • the signal of the m-th selection control signal terminal CX_m is provided to the output node N3.
  • the light emitting driving circuit 40 is configured to drive the device to be driven to operate in response to the signal of the output node N3.
  • N is an integer greater than 1. 1 ⁇ m ⁇ 2 N
  • m is an integer.
  • the device to be driven may be a light-emitting device L.
  • the light-emitting device L may be at least one of Micro LED and Mini LED.
  • the display device can be suitable for application scenarios that require a small number of grayscales to be displayed.
  • the display device may be a smart watch.
  • the specific implementation of the display device can be determined according to the requirements of the actual application, and is not limited here.
  • N can also be set to 4, 5, 6 or more, which is not limited here.
  • the input circuit includes: 2 N -1 input sub-circuits; the k-th input sub-circuit among the 2 N -1 input sub-circuits is respectively connected to the 2 N -1 first scanning signal terminals.
  • the k-th first scanning signal terminal is coupled to the k-th input node among the 2 N -1 input nodes; the k-th input sub-circuit is configured to respond to the signal loaded at the k-th first scanning signal terminal, Input the k-th data signal loaded at the first data signal terminal into the k-th input node; 1 ⁇ k ⁇ 2 N -1, and k is an integer.
  • the input circuit 10 includes three input sub-circuits, including three first scanning signal terminals and three input nodes. These three input sub-circuits are respectively: the first input sub-circuit 11_1, the second input sub-circuit 11_2, and the third input sub-circuit 11_3.
  • the three first scanning signal terminals are respectively: the first first scanning signal terminal GA_1, the second first scanning signal terminal GA_2, and the third first scanning signal terminal GA_3.
  • These three input nodes are: the first input node N1_1, the second input node N1_2, and the third input node N1_3.
  • the first input sub-circuit 11_1 is coupled to the first first scanning signal terminal GA_1 and the first input node N1_1, and the first input sub-circuit 11_1 is configured as In response to the signal loaded on the first first scanning signal terminal GA_1, the data signal loaded on the first data signal terminal DA1 is input to the first input node N1_1.
  • the first input sub-circuit 11_1 includes the first first transistor M1_1.
  • the effective level of the signal loaded on the first first scanning signal terminal GA_1 is high level and the inactive level is low level.
  • the first first transistor M1_1 is a P-type transistor, then the effective level of the signal loaded on the first first scanning signal terminal GA_1 is low level and the inactive level is high level.
  • the second input sub-circuit 11_2 is coupled to the second first scanning signal terminal GA_2 and the second input node N1_2, and the second input sub-circuit 11_2 is configured as In response to the signal loaded on the second first scanning signal terminal GA_2, the data signal loaded on the first data signal terminal DA1 is input to the second input node N1_2.
  • the second input sub-circuit 11_2 includes a second first transistor M1_2.
  • the second first transistor M1_2 is an N-type transistor, then the effective level of the signal loaded on the second first scanning signal terminal GA_2 is high level and the inactive level is low level. Or, if the second first transistor M1_2 is a P-type transistor, then the effective level of the signal loaded on the second first scanning signal terminal GA_2 is low level, and the invalid level is high level.
  • the third input sub-circuit 11_3 is coupled to the third first scanning signal terminal GA_3 and the third input node N1_3, and the third input sub-circuit 11_3 is configured as In response to the signal loaded on the third first scanning signal terminal GA_3, the data signal loaded on the first data signal terminal DA1 is input to the third input node N1_3.
  • the third input sub-circuit 11_3 includes a third first transistor M1_3.
  • the control terminal of the third first transistor M1_3 is coupled to the third first scan signal terminal GA_3, the first terminal of the third first transistor M1_3 is coupled to the first data signal terminal DA1, and the third first transistor M1_3 is coupled to the first data signal terminal DA1.
  • a second terminal of a transistor M1_3 is coupled to the third input node N1_3.
  • the third first transistor M1_3 is turned on when the signal loaded on the third first scanning signal terminal GA_3 is at a valid level, and is turned off when the signal loaded on the third first scanning signal terminal GA_3 is at an invalid level.
  • the third first transistor M1_3 is an N-type transistor, then the effective level of the signal loaded on the third first scanning signal terminal GA_3 is high level and the invalid level is low level. Or, if the third first transistor M1_3 is a P-type transistor, then the effective level of the signal loaded on the third first scanning signal terminal GA_3 is low level, and the invalid level is high level.
  • the control circuit 20 includes: 2 N -1 control sub-circuits, the input terminals of the 2 N -1 control sub-circuits are coupled to the 2 N -1 input nodes in a one-to-one correspondence; 2 N - 1 control subcircuit is defined as the 1st level control subcircuit to the Nth level control subcircuit; among them, each Nth level control subcircuit has a one-to-one correspondence with two of the 2 N control nodes, and the Nth level The input end of the control sub-circuit is coupled to one of the corresponding two control nodes, and the output end of the N-th level control sub-circuit is coupled to the other of the corresponding two control nodes; each q-th -1 level control sub-circuit corresponds to two q-th level control sub-circuits, the control end of one q-th level control sub-circuit of the two q-th level control sub-circuits and the corresponding output end of the q-1 level control sub-cir
  • the control circuit 20 includes three control sub-circuits and four control nodes. These three control sub-circuits are respectively: the first control sub-circuit 21_1, the second control sub-circuit 21_2, and the third control sub-circuit 21_3.
  • the first control sub-circuit 21_1 is defined as the first-level control sub-circuit
  • the second control sub-circuit 21_2 and the third control sub-circuit 21_3 are defined as the second-level control sub-circuit, that is, the first control sub-circuit 21_1 corresponds to the second-level control sub-circuit.
  • the second control sub-circuit 21_2 and the third control sub-circuit 21_3 are both configured to respond to the signal loaded on their control terminals, provide the signals at the input terminals to their output terminals, and latch the input signals.
  • these four control nodes are respectively: the first control node N2_1, the second control node N2_2, the third control node N2_3, and the fourth control node N2_4.
  • the second control sub-circuit 21_2 corresponds to the first control node N2_1 and the second control node N2_2, and the third control sub-circuit 21_3 corresponds to the third control node N2_3 and the fourth control node N2_4.
  • the input end of the first control sub-circuit 21_1 is coupled to the first input node N1_1.
  • the first control sub-circuit 21_1 is configured to invert the signal input to its input terminal and provide it to its output terminal, and to latch the input signal.
  • the first level control sub-circuit that is, the first control sub-circuit, includes a first latch S1.
  • the input terminal of the first latch S1 serves as the input terminal of the first-level control sub-circuit
  • the output terminal of the first latch S1 serves as the output terminal of the first-level control sub-circuit.
  • the first latch S1 includes: a first inverter ND1 and a second inverter ND2.
  • the input terminal of the first inverter ND1 serves as the input terminal of the first latch S1
  • the output terminal of the first inverter ND1 serves as the output terminal of the first latch S1.
  • the input terminal of the second inverter ND2 is coupled to the output terminal of the first inverter ND1
  • the output terminal of the second inverter ND2 is coupled to the input terminal of the first inverter ND1.
  • the control terminal of the second control sub-circuit 21_2 is coupled to the output terminal of the first control sub-circuit 21_1, and the input terminal of the second control sub-circuit 21_2 is coupled to the second control sub-circuit 21_2.
  • the first input node N1_2 is coupled
  • the output terminal of the second control sub-circuit 21_2 is coupled to the first control node N2_1
  • the input terminal of the second control sub-circuit 21_2 is coupled to the second control node N2_2.
  • the second control sub-circuit 21_2 includes: a second latch S2_1.
  • the control terminal of the second latch S2_1 serves as the control terminal of the second control sub-circuit 21_2, and the input terminal of the second latch S2_1 serves as the input terminal of the second control sub-circuit 21_2.
  • the second latch S2_1 The output terminal is used as the output terminal of the second control sub-circuit 21_2.
  • the control terminal of the second latch S2_1 when the control terminal of the second latch S2_1 is at a valid level, the signal input to its input terminal can be inverted and then output to its output terminal, and the input signal can be latched.
  • the control terminal of the second latch S2_1 is at an inactive level, its input terminal and its output terminal are disconnected.
  • the effective level of the control terminal of the second latch S2_1 may be low level, and the invalid level may be high level.
  • the effective level of the control terminal of the second latch S2_1 may also be high level, and the inactive level may be low level.
  • the second latch S2_1 in the second control sub-circuit 21_2 includes: a first three-state gate TS1_1 and a second three-state gate TS2_1.
  • the control terminal of the first three-state gate TS1_1 serves as the control terminal of the second latch S2
  • the input terminal of the first three-state gate TS1_1 serves as the input terminal of the second latch S2
  • the output of the first three-state gate TS1_1 The terminal serves as the output terminal of the second latch S2.
  • the control terminal of the second three-state gate TS2_1 is coupled with the control terminal of the first three-state gate TS1_1.
  • the input terminal of the second three-state gate TS2_1 is coupled with the output terminal of the first three-state gate TS1_1.
  • the second three-state gate TS2_1 The output terminal of is coupled with the input terminal of the first three-state gate TS1_1.
  • the signals input to their input terminals can be inverted and then output to their output terminals, and the input signals can be locked. live.
  • the effective level of the control terminals of the first three-state gate TS1_1 and the second three-state gate TS2_1 may be low level, and the invalid level may be high level.
  • the effective level of the control terminals of the first three-state gate TS1_1 and the second three-state gate TS2_1 may also be high level, and the invalid level may be low level.
  • the control terminal of the third control sub-circuit 21_3 is coupled to the input terminal of the first control sub-circuit 21_1, and the input terminal of the third control sub-circuit 21_3 is coupled to the input terminal of the third control sub-circuit 21_3.
  • the first input node N1_3 is coupled
  • the output terminal of the third control sub-circuit 21_3 is coupled to the third control node N2_3
  • the input terminal of the third control sub-circuit 21_3 is coupled to the fourth control node N2_4.
  • the third control sub-circuit 21_3 includes: a second latch S2_2.
  • the control terminal of the second latch S2_2 serves as the control terminal of the third control sub-circuit 21_3, and the input terminal of the second latch S2_2 serves as the input terminal of the third control sub-circuit 21_3.
  • the second latch S2_2 The output terminal is used as the output terminal of the third control sub-circuit 21_3.
  • the control terminal of the second latch S2_2 is at a valid level, the signal input to its input terminal can be inverted and then output to its output terminal, and the input signal can be latched.
  • the control terminal of the second latch S2_2 is at an invalid level, its input terminal and its output terminal are disconnected.
  • the effective level of the control terminal of the second latch S2_2 may be low level, and the invalid level may be high level.
  • the effective level of the control terminal of the second latch S2_2 may also be high level, and the inactive level may be low level.
  • the second latch S2_2 in the third control sub-circuit 21_3 includes: a first three-state gate TS1_2 and a second three-state gate TS2_2.
  • the control terminal of the first three-state gate TS1_2 serves as the control terminal of the second latch S2_2
  • the input terminal of the first three-state gate TS1_2 serves as the input terminal of the second latch S2_2
  • the output of the first three-state gate TS1_2 The terminal serves as the output terminal of the second latch S2_2.
  • the control terminal of the second three-state gate TS2_2 is coupled with the control terminal of the first three-state gate TS1_2.
  • the input terminal of the second three-state gate TS2_2 is coupled with the output terminal of the first three-state gate TS1_2.
  • the second three-state gate TS2_2 The output terminal of is coupled with the input terminal of the first three-state gate TS1_2.
  • the signals input to their input terminals can be inverted and then output to their output terminals, and the input signals can be locked. live.
  • the effective level of the control terminals of the first three-state gate TS1_2 and the second three-state gate TS2_2 may be low level, and the invalid level may be high level.
  • the effective level of the control terminals of the first three-state gate TS1_2 and the second three-state gate TS2_2 may also be high level, and the invalid level may be low level.
  • the output circuit 30 includes: 2 N output sub-circuits; the m-th output sub-circuit among the 2 N output sub-circuits, the m-th control node, the m-th selection control signal terminal and the output Node N3 is coupled.
  • These four output sub-circuits are respectively: the first output sub-circuit 31_1, the second output sub-circuit 31_2, the third output sub-circuit 31_3, and the fourth output sub-circuit 31_4.
  • These four selection control signal terminals are respectively the first selection control signal terminal CX_1, the second selection control signal terminal CX_2, the third selection control signal terminal CX_3, and the fourth selection control signal terminal CX_4.
  • the first output sub-circuit 31_1 is coupled to the first control node N2_1, the first selection control signal terminal CX_1 and the output node N3 respectively. Furthermore, the first output sub-circuit 31_1 is configured to provide the signal of the first selection control signal terminal CX_1 to the output node N3 in response to the signal of the first control node N2_1. For example, as shown in FIG. 4 , the first output sub-circuit 31_1 includes the first second transistor M2_1.
  • the control terminal of the first second transistor M2_1 is coupled to the first control node N2_1, the first terminal of the first second transistor M2_1 is coupled to the first selection control signal terminal CX_1, and the first second transistor M2_1 is coupled to the first selection control signal terminal CX_1.
  • the second terminal of the transistor M2_1 is coupled to the output node N3.
  • the first second transistor M2_1 is turned on when the signal of the first control node N2_1 is at a valid level, and is turned off when the signal of the first control node N2_1 is at an inactive level.
  • the effective level of the signal of the first control node N2_1 is high level and the inactive level is low level.
  • the first second transistor M2_1 is a P-type transistor, then the effective level of the signal of the first control node N2_1 is low level and the inactive level is high level.
  • the second output sub-circuit 31_2 is coupled to the second control node N2_2, the second selection control signal terminal CX_2 and the output node N3 respectively. Furthermore, the second output sub-circuit 31_2 is configured to provide the signal of the second selection control signal terminal CX_2 to the output node N3 in response to the signal of the second control node N2_2.
  • the second output sub-circuit 31_2 includes a second second transistor M2_2.
  • the control terminal of the second second transistor M2_2 is coupled to the second control node N2_2, the first terminal of the second second transistor M2_2 is coupled to the second selection control signal terminal CX_2, and the second second transistor M2_2 is coupled to the second selection control signal terminal CX_2.
  • the second terminal of the transistor M2_2 is coupled to the output node N3.
  • the second second transistor M2_2 is turned on when the signal of the second control node N2_2 is at a valid level, and is turned off when the signal of the second control node N2_2 is at an inactive level.
  • the second second transistor M2_2 is an N-type transistor, then the effective level of the signal of the second control node N2_2 is high level and the inactive level is low level. Or, if the second second transistor M2_2 is a P-type transistor, then the effective level of the signal of the second control node N2_2 is low level and the inactive level is high level.
  • the third output sub-circuit 31_3 is coupled to the third control node N2_3, the third selection control signal terminal CX_3 and the output node N3 respectively. Furthermore, the third output sub-circuit 31_3 is configured to provide the signal of the third selection control signal terminal CX_3 to the output node N3 in response to the signal of the third control node N2_3.
  • the third output sub-circuit 31_3 includes a third second transistor M2_3.
  • the control terminal of the third second transistor M2_3 is coupled to the third control node N2_3, the first terminal of the third second transistor M2_3 is coupled to the third selection control signal terminal CX_3, and the third second transistor M2_3 is coupled to the third selection control signal terminal CX_3.
  • the second terminal of the transistor M2_3 is coupled to the output node N3.
  • the third second transistor M2_3 is turned on when the signal of the third control node N2_3 is at a valid level, and is turned off when the signal of the third control node N2_3 is at an inactive level.
  • the third second transistor M2_3 is an N-type transistor, then the effective level of the signal of the third control node N2_3 is high level and the inactive level is low level. Or, if the third second transistor M2_3 is a P-type transistor, then the effective level of the signal of the third control node N2_3 is low level and the inactive level is high level.
  • control nodes and some input nodes are shared.
  • the second input node N1_2 and the second control node N2_2 are shared, that is, the second input node N1_2 and the second control node N2_2 are the same node.
  • the third input node N1_3 and the fourth control node N2_4 are shared, that is, the third input node N1_3 and the fourth control node N2_4 are the same node.
  • the light emitting driving circuit 40 includes: a light emitting control subcircuit 41 .
  • the light emission control sub-circuit 41 is coupled to the output node N3, the light emission control signal terminal EM and the device to be driven respectively.
  • the light emission control sub-circuit 41 is configured to drive the device to be driven to operate in response to signals from the light emission control signal terminal EM and the output node N3.
  • the lighting control sub-circuit 41 includes a third transistor M3; the control terminal of the third transistor M3 is coupled to the lighting control signal terminal EM, and the first terminal of the third transistor M3 is coupled to the output node N3.
  • the second terminal of the third transistor M3 is coupled to the first terminal of the device to be driven, and the second terminal of the device to be driven is coupled to the first reference power supply terminal VSS.
  • the third transistor M3 is turned on when the signal of the light-emitting control signal terminal EM is at a valid level, and is turned off when the signal of the light-emitting control signal terminal EM is at an inactive level.
  • the third transistor M3 is an N-type transistor, the effective level of the signal at the light emission control signal terminal EM is high level, and the inactive level is low level.
  • the third transistor M3 is a P-type transistor, then the effective level of the signal at the light emission control signal terminal EM is low level and the inactive level is high level.
  • control terminal of the above-mentioned transistor may be its gate, the first terminal may be its source, and the second terminal may be its drain.
  • control terminal of the above-mentioned transistor can be its gate, the first terminal can be its drain, and the second terminal can be its source.
  • the voltage of the first reference power terminal may be 0V or a negative value. Select the voltage at the control signal terminal to be positive. Furthermore, the lowest voltage of the selection control signal terminal may be the same as the voltage of the first reference power supply terminal, or the lowest voltage of the selection control signal terminal may be higher than the voltage of the first reference power supply terminal and less than the sum of the voltage of the first reference power supply terminal and the luminescence threshold voltage, or, The lowest voltage at the control signal terminal is selected to be higher than the sum of the voltage at the first reference power supply terminal and the luminescence threshold voltage. Wherein, luminescence is achieved when the voltage between the first terminal and the second terminal of the device to be driven is greater than the luminescence threshold voltage.
  • the device to be driven may be a light-emitting device L.
  • the positive electrode of the light-emitting device L may be the first terminal of the device to be driven, and the negative electrode may be the second terminal of the device to be driven.
  • the light-emitting device L can be a Micro LED, then the positive terminal of the Micro LED is the first terminal of the device to be driven, and the negative terminal of the Micro LED is the second terminal of the device to be driven.
  • the light-emitting device L can also be a Mini LED.
  • the positive terminal of the Mini LED is the first terminal of the device to be driven, and the negative terminal of the Mini LED is the second terminal of the device to be driven.
  • the latch can statically store signals, by setting the first latch and the second latch, the functions of each control sub-circuit are realized, and the efficiency of the signals transmitted in each control sub-circuit can be improved. Anti-interference ability.
  • the pixel circuit in the embodiment of the present disclosure can be fabricated on a silicon-based substrate, and the Micro LED can be fabricated on other substrates (for example, wafers). After that, the Micro LED on other substrates is transferred to the silicon-based substrate on which the pixel circuit in the embodiment of the present application is fabricated, and the Micro LED is electrically connected to the pixel circuit using a bonding method.
  • the pixel circuit is made on a silicon-based substrate, the area of the pixel circuit can be greatly reduced, so that more pixel circuits can be installed on the silicon-based substrate with the same area, and thus more Micro LEDs can be installed, that is, more Micro LEDs can be installed. More pixel units can increase PPI.
  • Embodiments of the present disclosure provide a driving method for a pixel circuit, as shown in Figure 5, including:
  • the control circuit responds to the signals of at least two input nodes among the 2 N -1 input nodes, and controls the signals of the 2 N control nodes respectively.
  • the output circuit responds to the signal of the m-th control node among the 2 N control nodes, and provides the signal of the m-th selection control signal terminal among the 2 N selection control signal terminals to the output node.
  • the light-emitting driving circuit responds to the signal of the output node and drives the device to be driven to work.
  • the selection control signal of each of the 2 N selection control signal terminals is different. Since the signals at each selection control signal terminal are different, at any time, by controlling the signal of one control node to be an effective level and the signals of the other control nodes to be an inactive level, it is possible to control the levels of different control nodes at different times. effective level.
  • the output sub-circuit is controlled through the control node at the active level, and different selection control signals are provided to the light-emitting driving circuit, thereby enabling the pixel unit to achieve multi-grayscale display.
  • the signal loaded on each of the 2 N selection control signal terminals is a DC voltage signal.
  • the voltage amplitude of the signal loaded on each selection control signal terminal is different.
  • the voltage amplitude of the signal loaded on the selection control signal terminal increases sequentially.
  • the voltage amplitude of the selection control signal cx_1 of the first selection control signal terminal CX_1 is V11
  • the voltage of the selection control signal cx_2 of the second selection control signal terminal CX_2 The amplitude is V12
  • the voltage amplitude of the selection control signal cx_3 of the third selection control signal terminal CX_3 is V13
  • the voltage amplitude of the selection control signal cx_4 of the fourth selection control signal terminal CX_4 is V14
  • V11 ⁇ V12 ⁇ V13 ⁇ V14 For example, V14 is 12V
  • V13 is 8V
  • V12 is 6V
  • V11 is 4V.
  • the voltage amplitude of the signal loaded on the selection control signal terminal can also be reduced sequentially.
  • the duty cycle of the signal loaded on each selection control signal terminal is different.
  • the signal loaded on the selection control signal terminal is a DC voltage signal
  • its duty cycle refers to: in a display frame, the duration of the signal when the corresponding voltage amplitude is loaded on the selection control signal terminal.
  • the duty cycle of the signal loaded on the selection control signal terminal increases in sequence. That is, the maintenance duration of the signal when the corresponding voltage amplitude is loaded on the selected control signal end increases in sequence. For example, when the voltage amplitude V11 of the selection control signal at the first selection control signal terminal is loaded, the corresponding sustaining time is W11.
  • the corresponding maintenance time is W12.
  • the corresponding maintenance time is W13.
  • the corresponding maintenance time is W14.
  • the voltage amplitude of the signal loaded on the selection control signal terminal decreases in sequence. That is, the maintenance duration of the signal when the corresponding voltage amplitude is loaded on the selected control signal end is gradually reduced.
  • the corresponding sustaining time is W21.
  • the corresponding maintenance time is W22.
  • the corresponding maintenance time is W23.
  • the corresponding maintenance time is W24.
  • the duty cycle of the signal loaded on each selection control signal terminal can also be the same. That is, in a display frame, when the corresponding voltage amplitude is loaded on the selected control signal terminal, the signal maintenance time is the same.
  • the signals cx_1 ⁇ cx_4 are DC signals, and the voltage amplitude of the signal cx_1 is V11, the voltage amplitude of the signal cx_2 is V12, the voltage amplitude of the signal cx_3 is V13, the voltage amplitude of the signal cx_4 is V14, and V11 ⁇ V12 ⁇ V13 ⁇ V14.
  • the voltage V13 of the signal cx_3 of the third selection control signal terminal CX_3 can be provided to the anode of the light-emitting device L.
  • the specific process is as follows: high-level signals appear in the signals ga1_1, ga1_2, and ga1_3 in sequence, and the low-level Vda1 ⁇ Vda3 are sequentially input to the first input node N1_1 to the third input node N1_3, so that the first input node N1_1 to The signals of the third input node N1_3 are all low level.
  • the data signal Vda1 can be latched through the action of the first latch S1, and the signal of node A is a high level signal.
  • the second latch S2S2_1 disconnects its input terminal and output terminal, and the first control node N2_1 does not input a signal, so the first second transistor M2_1 will not be turned on. Since the signal of the second input node N1_2 is low level, and the second input node N1_2 and the second control node N2_2 are shared, the signal of the second control node N2_2 is low level, so the second Transistor M2_2 is turned off.
  • the signal of the third input node N1_3 is low level, and the third input node N1_3 and the fourth control node N2_4 are shared, the signal of the fourth control node N2_4 is low level, so the fourth second Transistor M2_4 is turned off. Since the signal of the first input node N1_1 is low level, the second latch S2S2_2 is turned on, inverts the low level signal of the third input node N1_3 and outputs it to the third control node N2_3, so that The level of the third control node N2_3 is high level, controlling the third second transistor M2_3 to turn on.
  • the second latch S2S2_1 disconnects its input terminal and output terminal, and the first control node N2_1 does not input a signal, so the first second transistor M2_1 will not be turned on. Since the signal of the second input node N1_2 is low level, and the second input node N1_2 and the second control node N2_2 are shared, the signal of the second control node N2_2 is low level, so the second Transistor M2_2 is turned off.
  • the second latch S2S2_2 Since the signal of the first input node N1_1 is low level, the second latch S2S2_2 is turned on, inverts the high level signal of the third input node N1_3 and outputs it to the third control node N2_3, so that The level of the third control node N2_3 is low level, controlling the third second transistor M2_3 to turn off. Since the signal of the third input node N1_3 is high level, and the third input node N1_3 and the fourth control node N2_4 are shared, the signal of the fourth control node N2_4 is high level, so the fourth second Transistor M2_4 is turned on.
  • the fourth second transistor M2_4 that is turned on provides the signal cx_4 of the fourth selection control signal terminal CX_4 to the third transistor M3.
  • the third transistor M3 is controlled to be turned on to provide the signal cx_4 of the fourth selection control signal terminal CX_4 to the positive electrode of the light-emitting device L, so that the voltage V14 is input to the positive electrode of the light-emitting device L to drive light emission.
  • Device L emits light.
  • the voltage V11 of the signal cx_1 of the first selection control signal terminal CX_1 can be provided to the anode of the light emitting device L.
  • the specific process is as follows: high-level signals appear in the signals ga1_1, ga1_2, and ga1_3 in sequence, and the high-level Vda1 and low-level Vda2 ⁇ Vda3 are sequentially input to the first input node N1_1 to the third input node N1_3, so that the The signal of one input node N1_1 is high level, and the signals of the second input node N1_2 and the third input node N1_3 are both low level.
  • the signal of the first input node N1_1 is a high level
  • the data signal Vda1 can be latched
  • the signal of the node A is a low level signal
  • the second latch S2S2_1 inverts the low level of the second input node N1_2 and provides it to the first control node N2_1, so that the signal of the first control node N2_1 is high level, and controls the first second transistor M2_1 to turn on.
  • the first second transistor M2_1 that is turned on provides the signal cx_1 of the first selection control signal terminal CX_1 to the third transistor M3.
  • the voltage V12 of the signal cx_2 of the second selection control signal terminal CX_2 can be provided to the anode of the light emitting device L.
  • the specific process is as follows: high-level signals appear in the signals ga1_1, ga1_2, and ga1_3 in sequence, and the high-level Vda1 ⁇ Vda2 and low-level Vda3 are sequentially input to the first input node N1_1 to the third input node N1_3, so that the The signals of the first input node N1_1 and the second input node N1_2 are high level, and the signal of the third input node N1_3 is low level.
  • the signal of the first input node N1_1 is a high level
  • the data signal Vda1 can be latched
  • the signal of the node A is a low level signal
  • the second latch S2S2_1 inverts the high level of the second input node N1_2 and provides it to the first control node N2_1, making the signal of the first control node N2_1 low level and controlling the first second transistor M2_1 to turn off.
  • the signal of the second input node N1_2 is high level, and the second input node N1_2 and the second control node N2_2 are shared, the signal of the second control node N2_2 is high level, so the second Transistor M2_2 is turned on.
  • the second second transistor M2_2 that is turned on provides the signal cx_2 of the second selection control signal terminal CX_2 to the third transistor M3.
  • the third transistor M3 is controlled to be turned on to provide the signal cx_2 of the second selection control signal terminal CX_2 to the positive electrode of the light-emitting device L, so that the voltage V12 is input to the positive electrode of the light-emitting device L to drive the light.
  • Device L emits light. Since the signal of the first input node N1_1 is high level, the second latch S2S2_2 disconnects its input terminal and the output terminal, and the third control node N2_3 does not input a signal, then the third second transistor M2_3 does not Will conduct. Since the signal of the third input node N1_3 is low level, and the third input node N1_3 and the fourth control node N2_4 are shared, the signal of the fourth control node N2_4 is low level, so the fourth second Transistor M2_4 is turned off.
  • the second latch S2S2_2 Since the signal of the first input node N1_1 is low level, the second latch S2S2_2 is turned on, inverts the low level signal of the third input node N1_3 and outputs it to the third control node N2_3, so that The level of the third control node N2_3 is high level, controlling the third second transistor M2_3 to turn on.
  • the third second transistor M2_3 that is turned on provides the signal cx_3 of the third selection control signal terminal CX_3 to the third transistor M3.
  • the third transistor M3 When the signal em is at a high level, the third transistor M3 is controlled to be turned on to provide the signal cx_3 of the third selection control signal terminal CX_3 to the positive electrode of the light-emitting device L, so that the voltage V13 is input to the positive electrode of the light-emitting device L to drive the light.
  • Device L emits light.
  • the data signal Vda1 is low level
  • the data signal Vda3 is high level
  • the voltage V14 of the signal cx_4 of the fourth selection control signal terminal CX_4 can be provided to the positive electrode of the light-emitting device L.
  • the specific process is as follows: the signals ga1_1 and ga1_3 appear high-level signals in sequence, then the low-level Vda1 is input to the first input node N1_1, and the high-level Vda3 is input to the third input node N1_3, so that the first input node N1_1 The signal of is low level, and the signal of the third input node N1_3 is high level.
  • the data signal Vda1 can be latched through the action of the first latch S1, and the signal of node A is a high level signal.
  • the second latch S2S2_1 disconnects its input terminal and output terminal, and the first control node N2_1 does not input a signal, so the first second transistor M2_1 will not be turned on.
  • the second latch S2S2_2 Since the signal of the first input node N1_1 is low level, the second latch S2S2_2 is turned on, inverts the high level signal of the third input node N1_3 and outputs it to the third control node N2_3, so that The level of the third control node N2_3 is low level, controlling the third second transistor M2_3 to turn off. Since the signal of the third input node N1_3 is high level, and the third input node N1_3 and the fourth control node N2_4 are shared, the signal of the fourth control node N2_4 is high level, so the fourth second Transistor M2_4 is turned on.
  • the fourth second transistor M2_4 that is turned on provides the signal cx_4 of the fourth selection control signal terminal CX_4 to the third transistor M3.
  • the third transistor M3 is controlled to be turned on to provide the signal cx_4 of the fourth selection control signal terminal CX_4 to the positive electrode of the light-emitting device L, so that the voltage V14 is input to the positive electrode of the light-emitting device L to drive light emission.
  • Device L emits light.
  • the data signal Vda1 is high level
  • the data signal Vda2 is low level
  • the voltage V11 of the signal cx_1 of the first selection control signal terminal CX_1 can be provided. to the positive electrode of the light-emitting device L.
  • the specific process is as follows: the signals ga1_1 and ga1_3 appear high-level signals in sequence, then the high-level Vda1 and low-level Vda2 are input to the first input node N1_1 and the second input node N1_2 in sequence, so that the first input node The signal of N1_1 is high level, and the signal of the second input node N1_2 is low level.
  • the signal of the first input node N1_1 is a high level
  • the data signal Vda1 can be latched
  • the signal of the node A is a low level signal
  • the second latch S2S2_1 inverts the low level of the second input node N1_2 and provides it to the first control node N2_1, so that the signal of the first control node N2_1 is high level, and controls the first second transistor M2_1 to turn on.
  • the first second transistor M2_1 that is turned on provides the signal cx_1 of the first selection control signal terminal CX_1 to the third transistor M3.
  • the third transistor M3 When the signal em is at a high level, the third transistor M3 is controlled to be turned on to provide the signal cx_1 of the first selection control signal terminal CX_1 to the positive electrode of the light-emitting device L, so that the voltage V11 is input to the positive electrode of the light-emitting device L to drive light emission.
  • Device L emits light. Since the signal of the second input node N1_2 is low level, and the second input node N1_2 and the second control node N2_2 are shared, the signal of the second control node N2_2 is low level, so the second Transistor M2_2 is turned off.
  • the second latch S2S2_2 disconnects its input terminal and the output terminal, and the third control node N2_3 does not input a signal, then the third second transistor M2_3 does not Will conduct.
  • the data signals Vda1 ⁇ Vda2 are all high level, and when the data signal Vda3 is not input, the voltage V12 of the signal cx_2 of the second selection control signal terminal CX_2 can be provided to the light-emitting device L. positive electrode.
  • the specific process is as follows: high-level signals appear in the signals ga1_1 and ga1_3 in sequence, and the high-level Vda1 ⁇ Vda2 are input to the first input node N1_1 and the second input node N1_2 in sequence, so that the first input node N1_1 and the second The signals of each input node N1_2 are all high level.
  • the signal of the first input node N1_1 is a high level
  • the data signal Vda1 can be latched
  • the signal of the node A is a low level signal
  • the second latch S2S2_1 inverts the high level of the second input node N1_2 and provides it to the first control node N2_1, making the signal of the first control node N2_1 low level and controlling the first second transistor M2_1 to turn off.
  • the signal of the second input node N1_2 is high level, and the second input node N1_2 and the second control node N2_2 are shared, the signal of the second control node N2_2 is high level, so the second Transistor M2_2 is turned on.
  • the second second transistor M2_2 that is turned on provides the signal cx_2 of the second selection control signal terminal CX_2 to the third transistor M3.
  • the third transistor M3 is controlled to be turned on to provide the signal cx_2 of the second selection control signal terminal CX_2 to the positive electrode of the light-emitting device L, so that the voltage V12 is input to the positive electrode of the light-emitting device L to drive the light.
  • Device L emits light. Since the signal of the first input node N1_1 is high level, the second latch S2S2_2 disconnects its input terminal and the output terminal, and the third control node N2_3 does not input a signal, then the third second transistor M2_3 does not Will conduct.
  • Embodiments of the present disclosure provide other structural schematic diagrams of pixel circuits.
  • For the structural schematic diagram refer to FIG. 10 . It is modified from the implementation in the above-mentioned embodiment. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.
  • the light-emitting control sub-circuit 41 is also coupled to the second scan signal terminal GA2, the second data signal terminal DA2, and the reset signal terminal RE, and the light-emitting control sub-circuit 41 is configured to respond
  • the signal at the light-emitting control signal terminal EM, the signal at the output node N3, the signal loaded at the second scan signal terminal GA2, the data signal loaded at the second data signal terminal DA2, and the signal loaded at the reset signal terminal RE drive the device to be driven to work.
  • the lighting control sub-circuit 41 includes: a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, a storage capacitor CST and a driving transistor M0; the control end of the fourth transistor M4 and the lighting control signal
  • the terminal EM is coupled, the first terminal of the fourth transistor M4 is coupled with the output node N3, the second terminal of the fourth transistor M4 is coupled with the control terminal of the fifth transistor M5; the first terminal of the fifth transistor M5 is coupled with the driving transistor
  • the second terminal of M0 is coupled, the first terminal of the fifth transistor M5 is coupled with the first terminal of the device to be driven (such as the light-emitting device L); the control terminal of the sixth transistor M6 is coupled with the second scanning signal terminal GA2,
  • the first terminal of the sixth transistor M6 is coupled to the reset signal terminal RE, the second terminal of the sixth transistor M6 is coupled to the second terminal of the driving transistor M0; the control terminal of the seventh transistor M7 is coupled to the second scan signal terminal GA2.
  • the first terminal of the seventh transistor M7 is coupled to the second data signal terminal DA2, the second terminal of the seventh transistor M7 is coupled to the control terminal of the driving transistor M0; the first terminal of the driving transistor M0 is coupled to the second reference power supply terminal; the second terminal of the device to be driven (such as the light-emitting device L) is coupled to the first reference power terminal VSS.
  • the fourth transistor M4 is turned on when the signal of the light-emitting control signal terminal EM is at a valid level, and is turned off when the signal of the light-emitting control signal terminal EM is at an inactive level.
  • the fourth transistor M4 is an N-type transistor, the effective level of the signal at the light emission control signal terminal EM is high level, and the inactive level is low level.
  • the fourth transistor M4 is a P-type transistor, then the effective level of the signal at the light emission control signal terminal EM is low level and the inactive level is high level.
  • the fifth transistor M5 is turned on when the signal at its control terminal is at a valid level, and is turned off when the signal at its control terminal is at an inactive level.
  • the fifth transistor M5 is an N-type transistor, the effective level of the signal at its control terminal is high level, and the inactive level is low level.
  • the fifth transistor M5 is a P-type transistor, the effective level of the signal at its control terminal is low level and the inactive level is high level.
  • the sixth transistor M6 is turned on when the signal at the second scanning signal terminal GA2 is at a valid level, and is turned off when the signal at the second scanning signal terminal GA2 is at an inactive level.
  • the sixth transistor M6 is an N-type transistor, the effective level of the signal at the second scanning signal terminal GA2 is high level, and the inactive level is low level.
  • the sixth transistor M6 is a P-type transistor, so the effective level of the signal at the second scanning signal terminal GA2 is low level and the inactive level is high level.
  • the seventh transistor M7 is turned on when the signal at the second scanning signal terminal GA2 is at a valid level, and is turned off when the signal at the seventh scanning signal terminal is at an invalid level.
  • the seventh transistor M7 is an N-type transistor, the effective level of the signal at the second scanning signal terminal GA2 is high level and the inactive level is low level.
  • the seventh transistor M7 is a P-type transistor, so the effective level of the signal at the second scanning signal terminal GA2 is low level and the inactive level is high level.
  • the voltage of the second reference power terminal is a positive value.
  • the driving transistor M0 can generate a driving current. After the driving current is input to the light-emitting device L, the light-emitting device L can be driven to emit light.
  • the signal loaded on each of the 2 N selection control signal terminals is a pulse width modulation signal.
  • the duty cycle of the signal loaded on each selection control signal terminal is different.
  • the duty cycle refers to: in a display frame, the duration when the selected control signal end is loaded with a valid level.
  • the duty cycle of the signal loaded on the selection control signal terminal increases in sequence. That is, the maintenance time when the selection control signal terminal is loaded with a valid level increases in sequence. For example, as shown in FIG. 11 , the maintenance time corresponding to the effective level of the selection control signal cx_1 of the first selection control signal terminal CX_1 is 0.
  • the maintenance time corresponding to the effective level of the selection control signal cx_2 of the second selection control signal terminal CX_2 is W22.
  • the maintenance time corresponding to the effective level of the selection control signal cx_3 of the third selection control signal terminal CX_3 is W23.
  • the maintenance time corresponding to the effective level of the selection control signal cx_4 of the fourth selection control signal terminal CX_4 is W24. And 0 ⁇ W22 ⁇ W23 ⁇ W24. Or, among the 2 N selection control signal terminals, the duty cycle of the signal loaded on the selection control signal terminal decreases in sequence.
  • ga2 represents the signal of the second scanning signal terminal GA2
  • ga1_1 represents the signal of the first first scanning signal terminal GA_1
  • ga1_2 represents the signal of the second first scanning signal terminal GA_2
  • ga1_3 represents the third first scanning signal terminal GA_2.
  • the signal of the scanning signal terminal GA_3, em represents the signal of the lighting control signal terminal EM
  • da1 represents the signal of the first data signal terminal DA1
  • da2 represents the signal of the second data signal terminal DA2
  • cx_1 represents the signal of the first selection control signal terminal CX_1 signal
  • cx_2 represents the signal of the second selection control signal terminal CX_2
  • cx_3 represents the signal of the third selection control signal terminal CX_3
  • cx_4 represents the signal of the fourth selection control signal terminal CX_4.
  • the seventh transistor M7 when the signal ga2 is high level, the seventh transistor M7 is turned on, and the data signal Vda0 of the second data signal terminal DA2 is input to the control terminal of the driving transistor M0, so that the control terminal voltage of the driving transistor M0 is the data signal Vda0.
  • the sixth transistor M6 is turned on, and the reset signal from the reset signal terminal RE is input to the second terminal of the driving transistor M0 to reset the second terminal of the driving transistor M0.
  • the signal cx_3 of the third selection control signal terminal CX_3 can be provided to the fourth transistor M4.
  • the fourth transistor M4 When the signal em is high level, the fourth transistor M4 is controlled to be turned on to provide the signal cx_3 of the third selection control signal terminal CX_3 to the control terminal of the fifth transistor M5.
  • the fifth transistor M4 When the signal cx_3 is high level, the fifth transistor M4 is controlled to be turned on.
  • the transistor M5 is turned on, and the driving transistor M0 can generate a driving current I_3 according to the voltage of its control terminal and the second reference power terminal.
  • the driving current I_3 is input to the anode of the light-emitting device L, and drives the light-emitting device L to emit light.
  • the seventh transistor M7 when the signal ga2 is high level, the seventh transistor M7 is turned on, and the data signal Vda0 of the second data signal terminal DA2 is input to the control terminal of the driving transistor M0, so that the control terminal voltage of the driving transistor M0 is the data signal.
  • the voltage of Vda0 is V04.
  • the sixth transistor M6 is turned on, and the reset signal from the reset signal terminal RE is input to the second terminal of the driving transistor M0, thereby resetting the second terminal of the driving transistor M0.
  • the signal cx_4 of the fourth selection control signal terminal CX_4 can be provided to the fourth transistor M4.
  • the fourth transistor M4 When the signal em is high level, the fourth transistor M4 is controlled to be turned on to provide the signal cx_4 of the fourth selection control signal terminal CX_4 to the control terminal of the fifth transistor M5.
  • the fifth transistor M4 When the signal cx_4 is high level, the fifth transistor M4 is controlled to be turned on.
  • the transistor M5 is turned on, and the driving transistor M0 can generate a driving current I_4 according to the voltage of its control terminal and the second reference power terminal.
  • the driving current I_4 is input to the anode of the light-emitting device L, and drives the light-emitting device L to emit light.
  • the seventh transistor M7 when the signal ga2 is high level, the seventh transistor M7 is turned on, and the data signal Vda0 of the second data signal terminal DA2 is input to the control terminal of the driving transistor M0, so that the voltage of the control terminal of the driving transistor M0 is the data signal.
  • the voltage of Vda0 is V01.
  • the sixth transistor M6 is turned on, and the reset signal from the reset signal terminal RE is input to the second terminal of the driving transistor M0 to reset the second terminal of the driving transistor M0.
  • the signal cx_1 of the first selection control signal terminal CX_1 can be provided to the fourth transistor M4.
  • the fourth transistor M4 When the signal em is high level, the fourth transistor M4 is controlled to be turned on to provide the signal cx_1 of the first selection control signal terminal CX_1 to the control terminal of the fifth transistor M5. Since the duty cycle of the signal cx_1 is 0, then It is always at a low level, so the fifth transistor M5 is controlled to be turned off.
  • the driving transistor M0 can generate a driving current I_1 according to the voltage of its control terminal and the second reference power terminal. This driving current I_1 cannot be input to the light-emitting device L, and the light-emitting device L is dark. state.
  • the seventh transistor M7 when the signal ga2 is high level, the seventh transistor M7 is turned on, and the data signal Vda0 of the second data signal terminal DA2 is input to the control terminal of the driving transistor M0, so that the voltage of the control terminal of the driving transistor M0 is the data signal.
  • the voltage V02 of Vda0 Furthermore, the sixth transistor M6 is turned on, and the reset signal from the reset signal terminal RE is input to the second terminal of the driving transistor M0 to reset the second terminal of the driving transistor M0.
  • the signal cx_2 of the second selection control signal terminal CX_2 can be provided to the fourth transistor M4.
  • the fourth transistor M4 When the signal em is high level, the fourth transistor M4 is controlled to be turned on to provide the signal cx_2 of the second selection control signal terminal CX_2 to the control terminal of the fifth transistor M5.
  • the fifth transistor M4 When the signal cx_2 is high level, the fifth transistor M4 is controlled to be turned on.
  • the transistor M5 is turned on, and the driving transistor M0 can generate a driving current I_2 according to the voltage of its control terminal and the second reference power terminal.
  • the driving current I_2 is input to the light-emitting device L and drives the light-emitting device L to emit light.
  • the light-emitting device L can be controlled to realize 4 by controlling the duty ratios of the signals cx_1 to cx_4 of the first selection control signal terminal CX_1 to the fourth selection control signal terminal CX_4 to be different. different brightness.
  • the voltages V01 to V04 of Vda0 can also be made different, so that the driving currents I_1 to I_4 can be controlled to be different, and the signals cx_1 to cx_4 of the first selection control signal terminal CX_1 to the fourth selection control signal terminal CX_4 can be controlled.
  • the duty cycle is different, and the light-emitting device L is further controlled to achieve multiple different brightnesses.
  • the light-emitting device L does not emit light at this time and is in a dark state, so it can be realized The L dark state of the light-emitting device is darker.
  • the signal cx_4 of the fourth selection control signal terminal CX_4 since the duty cycle of the signal cx_4 of the fourth selection control signal terminal CX_4 is the largest, the light-emitting device L is the brightest at this time, that is, the maximum gray-scale brightness can be achieved.
  • the voltages V02 ⁇ V04 of Vda0 can be controlled to be different, thereby further affecting the light emitting device L.
  • the brightness is subdivided, so that the light-emitting device L can display more gray levels, effectively improving the brightness uniformity of low gray levels.

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Abstract

像素电路，其驱动方法及显示装置，其中，像素电路包括：输入电路（10），被配置为响应于2 N-1个第一扫描信号端（GA1_1,GA1_2,……GA1_2 N-1）中加载的信号，将第一数据信号端（DA1）加载的数据信号输入对应的输入节点（N1_1,N1_2,……N1_2 N-1）；控制电路（20），被配置为响应于2 N-1个输入节点（N1_1,N1_2,……N1_2 N-1）中的至少两个输入节点的信号，分别控制2 N个控制节点（N2_1,N2_2,……N2_2 N）的信号；输出电路（30），被配置为响应于2 N个控制节点（N2_1,N2_2,……N2_2 N）中的第m个控制节点（N2_m）的信号，将2 N个选择控制信号端（CX_1, CX _2,……CX _2 N）中的第m个选择控制信号端（CX_m）的信号提供给输出节点（N3）；发光驱动电路（40），被配置为响应于输出节点（N3）的信号，驱动待驱动器件工作。

Description

像素电路，其驱动方法及显示装置 技术领域
本公开涉及显示技术领域，特别涉及像素电路，其驱动方法及显示装置。
背景技术
随着微型发光二极管技术的发展，由于次毫米发光二极管(Mini Light Emitting Diode，Mini LED)(尺寸约为100-300μm)，微型发光二极管(Micro Light Emitting Diode，Micro LED)(尺寸为100μm以下)，具有发光效率高、亮度高、解析度高和反应速度快等特点，在显示装置中得到了广泛的应用。
发明内容
本公开实施例提供的像素电路，包括：
输入电路，分别与第一数据信号端、2 N-1个第一扫描信号端以及2 N-1个输入节点耦接，且所述2 N-1个第一扫描信号端与所述2 N-1个输入节点一一对应；所述输入电路被配置为响应于所述2 N-1个第一扫描信号端中加载的信号，将所述第一数据信号端加载的数据信号输入对应的输入节点；N为大于1的整数；
控制电路，分别与2 N-1个输入节点耦接；所述控制电路被配置为响应于所述2 N-1个输入节点中的至少两个输入节点的信号，分别控制2 N个控制节点的信号；
输出电路，分别与所述2 N个控制节点、2 N个选择控制信号端以及输出节点耦接，且所述2 N个控制节点与所述2 N个选择控制信号端一一对应；所述输出电路被配置为响应于所述2 N个控制节点中的第m个控制节点的信号，将所述2 N个选择控制信号端中的第m个选择控制信号端的信号提供给所述输出节点；1≤m≤2 N，且m为整数；
发光驱动电路，分别与所述输出节点以及待驱动器件耦接；所述发光驱 动电路被配置为响应于所述输出节点的信号，驱动所述待驱动器件工作。
在一些可能的实施方式中，所述输入电路包括：2 N-1个输入子电路；所述2 N-1个输入子电路中的第k个输入子电路分别与所述2 N-1个第一扫描信号端中的第k个第一扫描信号端以及所述2 N-1个输入节点中的第k个输入节点耦接；
所述第k个输入子电路被配置为响应于所述第k个第一扫描信号端加载的信号，将所述第一数据信号端加载的数据信号输入所述第k个输入节点；1≤k≤2 N-1，且k为整数。
在一些可能的实施方式中，所述第k个输入子电路包括第k个第一晶体管；
所述第k个第一晶体管的控制端与所述第k个第一扫描信号端耦接，所述第k个第一晶体管的第一端与所述第一数据信号端耦接，所述第k个第一晶体管的第二端与所述第k个输入节点耦接。
在一些可能的实施方式中，所述控制电路包括：2 N-1个控制子电路，所述2 N-1个控制子电路的输入端与所述2 N-1个输入节点一一对应耦接；
所述2 N-1个控制子电路定义为第1级控制子电路至第N级控制子电路；其中，各所述第N级控制子电路与所述2 N个控制节点中的两个控制节点一一对应，且所述第N级控制子电路的输入端与对应的所述两个控制节点中的一个控制节点耦接，所述第N级控制子电路的输出端与对应的所述两个控制节点中的另一个控制节点耦接；
每一个第q-1级控制子电路对应两个第q级控制子电路，所述两个第q级控制子电路中的一个第q级控制子电路的控制端与对应的所述第q-1级控制子电路的输出端耦接，另一个第q级控制子电路的控制端与对应的所述第q-1级控制子电路的输入端耦接；所述第q级控制子电路被配置为响应于加载到其控制端上的信号，将输入端的信号提供给其输出端；2≤q≤N，且q为整数。
在一些可能的实施方式中，所述第1级控制子电路包括第一锁存器；
所述第一锁存器的输入端作为所述第1级控制子电路的输入端，所述第 一锁存器的输出端作为所述第1级控制子电路的输出端。
在一些可能的实施方式中，所述第一锁存器包括：第一反相器和第二反相器；
所述第一反相器的输入端作为所述第一锁存器的输入端，所述第一反相器的输出端作为所述第一锁存器的输出端；
所述第二反相器的输入端与所述第一反相器的输出端耦接，所述第二反相器的输出端与所述第一反相器的输入端耦接。
在一些可能的实施方式中，所述第q级控制子电路包括：第二锁存器；
所述第二锁存器的控制端作为所述第q级控制子电路的控制端，所述第二锁存器的输入端作为所述第q级控制子电路的输入端，所述第二锁存器的输出端作为所述第q级控制子电路的输出端。
在一些可能的实施方式中，所述第二锁存器包括：第一三态门和第二三态门；
所述第一三态门的控制端作为所述第二锁存器的控制端，所述第一三态门的输入端作为所述第二锁存器的输入端，所述第一三态门的输出端作为所述第二锁存器的输出端；
所述第二三态门的控制端与所述第一三态门的控制端耦接，所述第二三态门的输入端与所述第一三态门的输出端耦接，所述第二三态门的输出端与所述第一三态门的输入端耦接。
在一些可能的实施方式中，所述输出电路包括：2 N个输出子电路；所述2 N个输出子电路中的第m个输出子电路与所述第m个控制节点、第m个选择控制信号端以及所述输出节点耦接；
所述第m个输出子电路被配置为响应于所述第m个控制节点的信号，将所述第m个选择控制信号端的信号提供给所述输出节点。
在一些可能的实施方式中，所述第m个输出子电路包括第m个第二晶体管；
所述第m个第二晶体管的控制端与所述第m个控制节点耦接，所述第m 个第二晶体管的第一端与所述第m个选择控制信号端耦接，所述第m个第二晶体管的第二端与所述输出节点耦接。
在一些可能的实施方式中，所述发光驱动电路包括：发光控制子电路；
所述发光控制子电路分别与所述输出节点、发光控制信号端以及所述待驱动器件耦接；所述发光控制子电路被配置为响应于所述发光控制信号端和所述输出节点的信号，驱动所述待驱动器件工作。
在一些可能的实施方式中，所述发光控制子电路包括第三晶体管；所述第三晶体管的控制端与所述发光控制信号端耦接，所述第三晶体管的第一端与所述输出节点耦接，所述第三晶体管的第二端与所述待驱动器件的第一端耦接；
所述待驱动器件的第二端与第一参考电源端耦接。
在一些可能的实施方式中，所述发光控制子电路还与第二扫描信号端、第二数据信号端、复位信号端耦接；
所述发光控制子电路被配置为响应于所述发光控制信号端的信号、所述输出节点的信号、所述第二扫描信号端加载的信号、所述第二数据信号端加载的数据信号、所述复位信号端加载的信号，驱动所述待驱动器件工作。
在一些可能的实施方式中，所述发光控制子电路包括：第四晶体管、第五晶体管、第六晶体管、第七晶体管、存储电容以及驱动晶体管；
所述第四晶体管的控制端与所述发光控制信号端耦接，所述第四晶体管的第一端与所述输出节点耦接，所述第四晶体管的第二端与所述第五晶体管的控制端耦接；
所述第五晶体管的第一端与所述驱动晶体管的第二端耦接，所述第五晶体管的第一端与所述待驱动器件的第一端耦接；
所述第六晶体管的控制端与所述第二扫描信号端耦接，所述第六晶体管的第一端与所述复位信号端耦接，所述第六晶体管的第二端与所述驱动晶体管的第二端耦接；
所述第七晶体管的控制端与所述第二扫描信号端耦接，所述第七晶体管 的第一端与所述第二数据信号端耦接，所述第七晶体管的第二端与所述驱动晶体管的控制端耦接；
所述驱动晶体管的第一端与第二参考电源端；
所述待驱动器件的第二端与第一参考电源端耦接。
本公开实施例提供的显示装置，包括多个上述的像素电路。
本公开实施例提供的像素电路的驱动方法，其中，所述驱动方法用于驱动上述的像素电路，所述驱动方法包括：
对所述2 N-1个第一扫描信号端中的一个第一扫描信号端加载有效电平的信号，对其余第一扫描信号端加载无效电平的信号，将所述第一数据信号端加载的数据信号输入对应加载所述有效电平的第一扫描信号端的输入节点；
所述控制电路响应于所述2 N-1个输入节点中的至少两个输入节点的信号，分别控制2 N个控制节点的信号；
所述输出电路响应于所述2 N个控制节点中的第m个控制节点的信号，将所述2 N个选择控制信号端中的第m个选择控制信号端的信号提供给所述输出节点；
发光驱动电路响应于所述输出节点的信号，驱动所述待驱动器件工作。
在一些可能的实施方式中，所述2 N个选择控制信号端中，各所述选择控制信号端加载的信号的电压幅值不同。
在一些可能的实施方式中，所述2 N个选择控制信号端中，各所述选择控制信号端加载的信号的占空比不同。
在一些可能的实施方式中，所述2 N个选择控制信号端中的每一个选择控制信号端加载的信号均为直流电压信号或脉宽调制信号。
附图说明
图1为本公开实施例提供的显示装置的一些结构示意图；
图2为本公开实施例提供的像素电路的一些结构示意图；
图3为本公开实施例提供的像素电路的另一些结构示意图；
图4为本公开实施例提供的像素电路的一些具体结构示意图；
图5为本公开实施例提供的像素电路的驱动方法的一些流程图；
图6为本公开实施例提供的一些信号时序图；
图7为本公开实施例提供的一些电平示意图；
图8a为本公开实施例提供的另一些信号时序图；
图8b为本公开实施例提供的又一些信号时序图；
图9为本公开实施例提供的另一些电平示意图；
图10为本公开实施例提供的像素电路的另一些具体结构示意图；
图11为本公开实施例提供的又一些信号时序图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
如图1所示，显示装置包括多个像素单元，该多个像素单元呈阵列排布。将该微型发光二极管技术应用在显示面板中时，每个像素单元中设置至少一个发光器件和与每一个发光器件耦接的像素电路，该像素电路用于为耦接的发光器件提供电压，以控制发光器件发光，进而实现图像的显示。示例性地，每个像素单元中设置一个发光器件和与该发光器件耦接的像素电路。然而，相关技术中的发光器件显示面板中的像素电路的结构均较复杂。
如图2所示，本公开实施例提供的像素电路，包括：输入电路10、控制电路20、输出电路30以及发光驱动电路40。其中，输入电路10分别与第一数据信号端DA1、2 N-1个第一扫描信号端(如GA1_1、GA1_2、……GA1_2 N-1)以及2 N-1个输入节点(如N1_1、N1_2、……N1_2 N-1)耦接。控制电路20分别与2 N-1个输入节点(如N1_1、N1_2、……N1_2 N-1)耦接。输出电路30分别与2 N个控制节点(如N2_1、N2_2、……N1_2 N)、2N个选择控制信号端(如CX_1、CX_2、……CX_2 N)以及输出节点N3耦接。发光驱动电路40分别与输出节点N3以及待驱动器件耦接。并且，2 N-1个第一扫描信号端(如GA1_1、GA1_2、……GA1_2 N-1)与2 N-1个输入节点(如N1_1、N1_2、……N1_2 N-1)一一对应，2 N个控制节点(如N2_1、N2_2、……N2_2 N)与2 N个选择控制信号端(如CX_1、CX_2、……CX_2 N)一一对应。以及，输入电路10被配置为响应于2 N-1个第一扫描信号端(如GA1_1、GA1_2、……GA1_2 N-1)中加载的信号，将第一数据信号端DA1加载的数据信号输入对应的输入节点(如N1_1、N1_2、……N1_2 N-1)。控制电路20被配置为响应于2 N-1个输入节点(如N1_1、N1_2、……N1_2 N-1)中的至少两个输入节点的信号，分别控制2 N个控制节点(如N2_1、N2_2、……N2_2 N)的信号。输出电路30被配置为响应于2 N个控制节点(如N2_1、N2_2、……N2_2 N)中的第m个控制节点N2_m的信号，将2 N个选择控制信号端(如CX_1、CX_2、……CX_2 N)中的第m个选择控制信号端CX_m的信号提供给输出节点N3。发光驱动电路40被配置为响应于输出节点N3的信号，驱动待驱动器件工作。N为大于1的整数。1≤m≤2 N，且m为整数。
本公开实施例提供的上述像素电路，通过输入电路响应于2 N-1个第一扫描信号端中加载的信号，可以将第一数据信号端加载的数据信号输入对应的输入节点。控制电路响应于2 N-1个输入节点中的至少两个输入节点的信号，可以分别控制2 N个控制节点的信号。输出电路响应于2 N个控制节点中的第m个控制节点的信号，可以将2 N个选择控制信号端中的第m个选择控制信号端的信号提供给输出节点。发光驱动电路响应于输出节点的信号，驱动待驱动器件工作。因此，可以通过输入电路、控制电路、输出电路以及发光驱动电路相互配合，可以使一个像素电路，实现多个输入并从多个不同的选择控制信号端中选取一个选择控制信号端的信号提供给发光驱动电路，以使发光驱动电路可以驱动待驱动器件工作。相较于相关技术，提高了像素电路中器件的利用率，降低了像素电路的结构复杂度。
本公开实施例提供的像素电路，应用于显示装置中时，待驱动器件可以为发光器件L。例如，发光器件L可以为Micro LED和Mini LED中的至少一种。该显示装置可以适用于所需显示的灰阶数较少的应用场景。示例性地，该显示装置可以为智能手表。当然，在实际应用中，可以根据实际应用的需求确定显示装置的具体实施方式，在此不作限定。
示例性地，可以使N＝2，则m可以为1、2、3、4。也可以使N＝3，则m可以为1、2、3、4、5、6、7、8。当然，也可以使N＝4、5、6或更多，在此不作限定。
在本公开一些实施例中，输入电路包括：2 N-1个输入子电路；2 N-1个输入子电路中的第k个输入子电路分别与2 N-1个第一扫描信号端中的第k个第一扫描信号端以及2 N-1个输入节点中的第k个输入节点耦接；第k个输入子电路被配置为响应于第k个第一扫描信号端加载的信号，将第一数据信号端加载的第k个数据信号输入第k个输入节点；1≤k≤2 N-1，且k为整数。示例性地，如图3所示，以N＝2为例，则k可以为1、2、3。即，输入电路10包括3个输入子电路，第一扫描信号端为3个，输入节点也为3个。这3个输入子电路分别为：第1个输入子电路11_1、第2个输入子电路11_2、第3个 输入子电路11_3。这3个第一扫描信号端分别为：第1个第一扫描信号端GA_1、第2个第一扫描信号端GA_2、第3个第一扫描信号端GA_3。这3个输入节点分别为：第1个输入节点N1_1、第2个输入节点N1_2、第3个输入节点N1_3。
在本公开一些示例中，如图3所示，第1个输入子电路11_1与第1个第一扫描信号端GA_1以及第1个输入节点N1_1耦接，第1个输入子电路11_1被配置为响应于第1个第一扫描信号端GA_1加载的信号，将第一数据信号端DA1加载的数据信号输入第1个输入节点N1_1。示例性地，如图4所示，第1个输入子电路11_1包括第1个第一晶体管M1_1。其中，第1个第一晶体管M1_1的控制端与第1个第一扫描信号端GA_1耦接，第1个第一晶体管M1_1的第一端与第一数据信号端DA1耦接，第1个第一晶体管M1_1的第二端与第1个输入节点N1_1耦接。可选地，第1个第一晶体管M1_1在第1个第一扫描信号端GA_1加载的信号为有效电平时导通，在第1个第一扫描信号端GA_1加载的信号为无效电平时截止。例如，第1个第一晶体管M1_1为N型晶体管，则第1个第一扫描信号端GA_1加载的信号的有效电平为高电平，无效电平为低电平。或者，第1个第一晶体管M1_1为P型晶体管，则第1个第一扫描信号端GA_1加载的信号的有效电平为低电平，无效电平为高电平。
在本公开一些示例中，如图3所示，第2个输入子电路11_2与第2个第一扫描信号端GA_2以及第2个输入节点N1_2耦接，第2个输入子电路11_2被配置为响应于第2个第一扫描信号端GA_2加载的信号，将第一数据信号端DA1加载的数据信号输入第2个输入节点N1_2。示例性地，如图4所示，第2个输入子电路11_2包括第2个第一晶体管M1_2。其中，第2个第一晶体管M1_2的控制端与第2个第一扫描信号端GA_2耦接，第2个第一晶体管M1_2的第一端与第一数据信号端DA1耦接，第2个第一晶体管M1_2的第二端与第2个输入节点N1_2耦接。可选地，第2个第一晶体管M1_2在第2个第一扫描信号端GA_2加载的信号为有效电平时导通，在第2个第一扫描 信号端GA_2加载的信号为无效电平时截止。例如，第2个第一晶体管M1_2为N型晶体管，则第2个第一扫描信号端GA_2加载的信号的有效电平为高电平，无效电平为低电平。或者，第2个第一晶体管M1_2为P型晶体管，则第2个第一扫描信号端GA_2加载的信号的有效电平为低电平，无效电平为高电平。
在本公开一些示例中，如图3所示，第3个输入子电路11_3与第3个第一扫描信号端GA_3以及第3个输入节点N1_3耦接，第3个输入子电路11_3被配置为响应于第3个第一扫描信号端GA_3加载的信号，将第一数据信号端DA1加载的数据信号输入第3个输入节点N1_3。示例性地，如图4所示，第3个输入子电路11_3包括第3个第一晶体管M1_3。其中，第3个第一晶体管M1_3的控制端与第3个第一扫描信号端GA_3耦接，第3个第一晶体管M1_3的第一端与第一数据信号端DA1耦接，第3个第一晶体管M1_3的第二端与第3个输入节点N1_3耦接。可选地，第3个第一晶体管M1_3在第3个第一扫描信号端GA_3加载的信号为有效电平时导通，在第3个第一扫描信号端GA_3加载的信号为无效电平时截止。例如，第3个第一晶体管M1_3为N型晶体管，则第3个第一扫描信号端GA_3加载的信号的有效电平为高电平，无效电平为低电平。或者，第3个第一晶体管M1_3为P型晶体管，则第3个第一扫描信号端GA_3加载的信号的有效电平为低电平，无效电平为高电平。
在本公开一些实施例中，控制电路20包括：2 N-1个控制子电路，2 N-1个控制子电路的输入端与2 N-1个输入节点一一对应耦接；2 N-1个控制子电路定义为第1级控制子电路至第N级控制子电路；其中，各第N级控制子电路与2 N个控制节点中的两个控制节点一一对应，且第N级控制子电路的输入端与对应的两个控制节点中的一个控制节点耦接，第N级控制子电路的输出端与对应的两个控制节点中的另一个控制节点耦接；每一个第q-1级控制子电路对应两个第q级控制子电路，两个第q级控制子电路中的一个第q级控制子电路的控制端与对应的第q-1级控制子电路的输出端耦接，另一个第q级控制子 电路的控制端与对应的第q-1级控制子电路的输入端耦接；第q级控制子电路被配置为响应于加载到其控制端上的信号，将输入端的信号提供给其输出端；2≤q≤N，且q为整数。示例性地，如图3所示，以N＝2为例，则q为2。即控制电路20包括3个控制子电路，控制节点为4个。这3个控制子电路分别为：第1个控制子电路21_1、第2个控制子电路21_2、第3个控制子电路21_3。第1个控制子电路21_1定义为第1级控制子电路，第2个控制子电路21_2和第3个控制子电路21_3定义为第2级控制子电路，即第1个控制子电路21_1对应第2个控制子电路21_2和第3个控制子电路21_3，且第3个控制子电路21_3的控制端与第1个控制子电路21_1的输入端耦接。以及，第2个控制子电路21_2和第3个控制子电路21_3均被配置为响应于加载到其控制端上的信号，将输入端的信号提供给其输出端，并将输入的信号进行锁存。并且，这4个控制节点分别为：第1个控制节点N2_1、第2个控制节点N2_2、第3个控制节点N2_3、第4个控制节点N2_4。第2个控制子电路21_2与第1个控制节点N2_1和第2个控制节点N2_2对应，第3个控制子电路21_3与第3个控制节点N2_3和第4个控制节点N2_4对应。
在本公开一些示例中，如图3所示，第1个控制子电路21_1的输入端与第1个输入节点N1_1耦接。第1个控制子电路21_1被配置为将输入其输入端的信号进行反相后提供给其输出端，并将输入的信号进行锁存。示例性地，如图4所示，第1级控制子电路即第1个控制子电路，包括第一锁存器S1。其中，第一锁存器S1的输入端作为第1级控制子电路的输入端，第一锁存器S1的输出端作为第1级控制子电路的输出端。可选地，第一锁存器S1包括：第一反相器ND1和第二反相器ND2。其中，第一反相器ND1的输入端作为第一锁存器S1的输入端，第一反相器ND1的输出端作为第一锁存器S1的输出端。第二反相器ND2的输入端与第一反相器ND1的输出端耦接，第二反相器ND2的输出端与第一反相器ND1的输入端耦接。
在本公开一些示例中，如图3所示，第2个控制子电路21_2的控制端与第1个控制子电路21_1的输出端耦接，第2个控制子电路21_2的输入端与 第2个输入节点N1_2耦接，第2个控制子电路21_2的输出端与第1个控制节点N2_1耦接，第2个控制子电路21_2的输入端与第2个控制节点N2_2耦接。示例性地，如图4所示，第2个控制子电路21_2包括：第二锁存器S2_1。其中，第二锁存器S2_1的控制端作为第2个控制子电路21_2的控制端，第二锁存器S2_1的输入端作为第2个控制子电路21_2的输入端，第二锁存器S2_1的输出端作为第2个控制子电路21_2的输出端。可选地，在第二锁存器S2_1的控制端为有效电平时，可以将输入其输入端的信号进行反相后输出给其输出端，并将输入的信号进行锁存。在第二锁存器S2_1的控制端为无效电平时，将其输入端和其输出端断开。例如，第二锁存器S2_1的控制端的有效电平可以为低电平，无效电平为高电平。或者，第二锁存器S2_1的控制端的有效电平也可以为高电平，无效电平为低电平。
示例性地，如图4所示，第2个控制子电路21_2中的第二锁存器S2_1包括：第一三态门TS1_1和第二三态门TS2_1。其中，第一三态门TS1_1的控制端作为第二锁存器S2的控制端，第一三态门TS1_1的输入端作为第二锁存器S2的输入端，第一三态门TS1_1的输出端作为第二锁存器S2的输出端。第二三态门TS2_1的控制端与第一三态门TS1_1的控制端耦接，第二三态门TS2_1的输入端与第一三态门TS1_1的输出端耦接，第二三态门TS2_1的输出端与第一三态门TS1_1的输入端耦接。可选地，第一三态门TS1_1和第二三态门TS2_1在其控制端为有效电平时，可以将输入其输入端的信号进行反相后输出给其输出端，并将输入的信号进行锁存。例如，第一三态门TS1_1和第二三态门TS2_1的控制端的有效电平可以为低电平，无效电平为高电平。或者，第一三态门TS1_1和第二三态门TS2_1的控制端的有效电平也可以为高电平，无效电平为低电平。
在本公开一些示例中，如图3所示，第3个控制子电路21_3的控制端与第1个控制子电路21_1的输入端耦接，第3个控制子电路21_3的输入端与第3个输入节点N1_3耦接，第3个控制子电路21_3的输出端与第3个控制节点N2_3耦接，第3个控制子电路21_3的输入端与第4个控制节点N2_4 耦接。示例性地，如图4所示，第3个控制子电路21_3包括：第二锁存器S2_2。其中，第二锁存器S2_2的控制端作为第3个控制子电路21_3的控制端，第二锁存器S2_2的输入端作为第3个控制子电路21_3的输入端，第二锁存器S2_2的输出端作为第3个控制子电路21_3的输出端。可选地，在第二锁存器S2_2的控制端为有效电平时，可以将输入其输入端的信号进行反相后输出给其输出端，并将输入的信号进行锁存。在第二锁存器S2_2的控制端为无效电平时，将其输入端和其输出端断开。例如，第二锁存器S2_2的控制端的有效电平可以为低电平，无效电平为高电平。或者，第二锁存器S2_2的控制端的有效电平也可以为高电平，无效电平为低电平。
示例性地，如图4所示，第3个控制子电路21_3中的第二锁存器S2_2包括：第一三态门TS1_2和第二三态门TS2_2。其中，第一三态门TS1_2的控制端作为第二锁存器S2_2的控制端，第一三态门TS1_2的输入端作为第二锁存器S2_2的输入端，第一三态门TS1_2的输出端作为第二锁存器S2_2的输出端。第二三态门TS2_2的控制端与第一三态门TS1_2的控制端耦接，第二三态门TS2_2的输入端与第一三态门TS1_2的输出端耦接，第二三态门TS2_2的输出端与第一三态门TS1_2的输入端耦接。可选地，第一三态门TS1_2和第二三态门TS2_2在其控制端为有效电平时，可以将输入其输入端的信号进行反相后输出给其输出端，并将输入的信号进行锁存。例如，第一三态门TS1_2和第二三态门TS2_2的控制端的有效电平可以为低电平，无效电平为高电平。或者，第一三态门TS1_2和第二三态门TS2_2的控制端的有效电平也可以为高电平，无效电平为低电平。
在本公开一些实施例中，输出电路30包括：2 N个输出子电路；2 N个输出子电路中的第m个输出子电路与第m个控制节点、第m个选择控制信号端以及输出节点N3耦接。第m个输出子电路被配置为响应于第m个控制节点的信号，将第m个选择控制信号端的信号提供给输出节点N3。示例性地，如图3所示，以N＝2为例，则m为1、2、3、4。即，输出电路30包括4个输出子电路。选择控制信号端为4个。这4个输出子电路分别为：第1个输出子 电路31_1、第2个输出子电路31_2、第3个输出子电路31_3、第4个输出子电路31_4。且这4个选择控制信号端分别为第1个选择控制信号端CX_1、第2个选择控制信号端CX_2、第3个选择控制信号端CX_3、第4个选择控制信号端CX_4。
在本公开一些示例中，如图3所示，第1个输出子电路31_1分别与第1个控制节点N2_1、第1个选择控制信号端CX_1以及输出节点N3耦接。并且，第1个输出子电路31_1被配置为响应于第1个控制节点N2_1的信号，将第1个选择控制信号端CX_1的信号提供给输出节点N3。示例性地，如图4所示，第1个输出子电路31_1包括第1个第二晶体管M2_1。其中，第1个第二晶体管M2_1的控制端与第1个控制节点N2_1耦接，第1个第二晶体管M2_1的第一端与第1个选择控制信号端CX_1耦接，第1个第二晶体管M2_1的第二端与输出节点N3耦接。可选地，第1个第二晶体管M2_1在第1个控制节点N2_1的信号为有效电平时导通，在第1个控制节点N2_1的信号为无效电平时截止。例如，第1个第二晶体管M2_1为N型晶体管，则第1个控制节点N2_1的信号的有效电平为高电平，无效电平为低电平。或者，第1个第二晶体管M2_1为P型晶体管，则第1个控制节点N2_1的信号的有效电平为低电平，无效电平为高电平。
在本公开一些示例中，如图3所示，第2个输出子电路31_2分别与第2个控制节点N2_2、第2个选择控制信号端CX_2以及输出节点N3耦接。并且，第2个输出子电路31_2被配置为响应于第2个控制节点N2_2的信号，将第2个选择控制信号端CX_2的信号提供给输出节点N3。示例性地，如图4所示，第2个输出子电路31_2包括第2个第二晶体管M2_2。其中，第2个第二晶体管M2_2的控制端与第2个控制节点N2_2耦接，第2个第二晶体管M2_2的第一端与第2个选择控制信号端CX_2耦接，第2个第二晶体管M2_2的第二端与输出节点N3耦接。可选地，第2个第二晶体管M2_2在第2个控制节点N2_2的信号为有效电平时导通，在第2个控制节点N2_2的信号为无效电平时截止。例如，第2个第二晶体管M2_2为N型晶体管，则第2 个控制节点N2_2的信号的有效电平为高电平，无效电平为低电平。或者，第2个第二晶体管M2_2为P型晶体管，则第2个控制节点N2_2的信号的有效电平为低电平，无效电平为高电平。
在本公开一些示例中，如图3所示，第3个输出子电路31_3分别与第3个控制节点N2_3、第3个选择控制信号端CX_3以及输出节点N3耦接。并且，第3个输出子电路31_3被配置为响应于第3个控制节点N2_3的信号，将第3个选择控制信号端CX_3的信号提供给输出节点N3。示例性地，如图4所示，第3个输出子电路31_3包括第3个第二晶体管M2_3。其中，第3个第二晶体管M2_3的控制端与第3个控制节点N2_3耦接，第3个第二晶体管M2_3的第一端与第3个选择控制信号端CX_3耦接，第3个第二晶体管M2_3的第二端与输出节点N3耦接。可选地，第3个第二晶体管M2_3在第3个控制节点N2_3的信号为有效电平时导通，在第3个控制节点N2_3的信号为无效电平时截止。例如，第3个第二晶体管M2_3为N型晶体管，则第3个控制节点N2_3的信号的有效电平为高电平，无效电平为低电平。或者，第3个第二晶体管M2_3为P型晶体管，则第3个控制节点N2_3的信号的有效电平为低电平，无效电平为高电平。
需要说明的是，部分控制节点和部分输入节点共用。例如，如图4所示，第2个输入节点N1_2和第2个控制节点N2_2共用，即第2个输入节点N1_2和第2个控制节点N2_2为同一个节点。第3个输入节点N1_3和第4个控制节点N2_4共用，即第3个输入节点N1_3和第4个控制节点N2_4为同一个节点。
在本公开一些实施例中，如图3所示，发光驱动电路40包括：发光控制子电路41。其中，发光控制子电路41分别与输出节点N3、发光控制信号端EM以及待驱动器件耦接。发光控制子电路41被配置为响应于发光控制信号端EM和输出节点N3的信号，驱动待驱动器件工作。示例性地，如图4所示，发光控制子电路41包括第三晶体管M3；第三晶体管M3的控制端与发光控制信号端EM耦接，第三晶体管M3的第一端与输出节点N3耦接，第三晶体 管M3的第二端与待驱动器件的第一端耦接，待驱动器件的第二端与第一参考电源端VSS耦接。可选地，第三晶体管M3在发光控制信号端EM的信号为有效电平时导通，在发光控制信号端EM的信号为无效电平时截止。例如，第三晶体管M3为N型晶体管，则发光控制信号端EM的信号的有效电平为高电平，无效电平为低电平。或者，第三晶体管M3为P型晶体管，则发光控制信号端EM的信号的有效电平为低电平，无效电平为高电平。
在本公开实施例中，上述晶体管的控制端可以为其栅极，第一端可以为其源极，第二端可以为其漏极。或者，上述晶体管的控制端可以为其栅极，第一端可以为其漏极，第二端可以为其源极。
在本公开实施例中，第一参考电源端的电压可以为0V或负值。选择控制信号端的电压为正极。并且，选择控制信号端的最低电压可以与第一参考电源端的电压相同，或者选择控制信号端的最低电压高于第一参考电源端的电压且小于第一参考电源端的电压与发光阈值电压之和，或者，选择控制信号端的最低电压高于第一参考电源端的电压与发光阈值电压之和。其中，在待驱动器件的第一端和第二端之间的电压大于发光阈值电压时实现发光。
示例性地，待驱动器件可以为发光器件L。发光器件L的正极可以为待驱动器件的第一端，负极可以为待驱动器件的第二端。例如，发光器件L可以为Micro LED，则Micro LED的正极为待驱动器件的第一端，Micro LED的负极为待驱动器件的第二端。发光器件L也可以为Mini LED，则Mini LED的正极为待驱动器件的第一端，Mini LED的负极为待驱动器件的第二端。
本公开实施例中，由于锁存器能够对信号进行静态存储，通过设置第一锁存器和第二锁存器，实现各个控制子电路的功能，可以提高各个控制子电路中传输的信号的抗干扰能力。
本公开实施例中，不需要设置存储电容CST和驱动晶体管M0，节省了存储电容CST对应的制备工艺，以及节省了制备存储电容CST所以的掩膜板(Mask)，从而可以节约成本，降低工艺流程复杂度。以及，还可以降低存储电容CST充放电带来的功耗问题。
在实际应用中，以Micro LED为例，玻璃基Micro LED由于薄膜晶体管(Thin Film Transistor，TFT)的尺寸限制，导致像素电路的面积不能进一步缩小，无法实现高PPI显示。本公开实施例中的像素电路可以制作在硅基衬底上，Micro LED可以制作在其他衬底(例如，晶圆)上。之后，将其他衬底上的Micro LED转移到制作有本申请实施例中的像素电路的硅基衬底上，并采用邦定方式将Micro LED与像素电路进行电连接。由于将像素电路制作在硅基衬底上，可以大幅度缩小像素电路面积，从而可以使相同面积下的硅基衬底能够设置更多的像素电路，从而设置更多的Micro LED，即设置更多的像素单元，进而可以提高PPI。
本公开实施例提供了像素电路的驱动方法，如图5所示，包括：
S10、对2 N-1个第一扫描信号端中的一个第一扫描信号端加载有效电平的信号，对其余第一扫描信号端加载无效电平的信号，将第一数据信号端加载的数据信号输入对应加载有效电平的第一扫描信号端的输入节点。
S20、控制电路响应于2 N-1个输入节点中的至少两个输入节点的信号，分别控制2 N个控制节点的信号。
S30、输出电路响应于2 N个控制节点中的第m个控制节点的信号，将2 N个选择控制信号端中的第m个选择控制信号端的信号提供给输出节点。
S40、发光驱动电路响应于输出节点的信号，驱动待驱动器件工作。
在本公开一些实施例中，2 N个选择控制信号端中的每一个选择控制信号端的选择控制信号均不同。由于每一个选择控制信号端的信号不同，在任一时刻，通过控制一个控制节点的信号为有效电平，其余控制节点的信号为无效电平，可以实现在不同时刻控制不同的控制节点的电平处于有效电平。并通过该处于有效电平的控制节点控制输出子电路，向发光驱动电路提供不同的选择控制信号，进而使像素单元实现多灰阶显示。
在本公开一些实施例中，2 N个选择控制信号端中的每一个选择控制信号端加载的信号均为直流电压信号。示例性地，2 N个选择控制信号端中，各选择控制信号端加载的信号的电压幅值不同。可选地，2 N个选择控制信号端中， 选择控制信号端加载的信号的电压幅值依次升高。例如，以M＝3为例，如图6所示，第1个选择控制信号端CX_1的选择控制信号cx_1的电压幅值为V11，第2个选择控制信号端CX_2的选择控制信号cx_2的电压幅值为V12，第3个选择控制信号端CX_3的选择控制信号cx_3的电压幅值为V13，第4个选择控制信号端CX_4的选择控制信号cx_4的电压幅值为V14，且V11<V12<V13<V14。例如，V14为12V，V13为8V，V12为6V，V11为4V。当然，2 N个选择控制信号端中，选择控制信号端加载的信号的电压幅值也可以依次降低。
示例性地，2 N个选择控制信号端中，各选择控制信号端加载的信号的占空比不同。在选择控制信号端加载的信号为直流电压信号时，其占空比指的是：在一个显示帧中，选择控制信号端加载对应电压幅值时的信号的维持时长。可选地，2 N个选择控制信号端中，选择控制信号端加载的信号的占空比依次升高。即，选择控制信号端加载对应电压幅值时的信号的维持时长依次升高。例如，第1个选择控制信号端的选择控制信号的电压幅值V11加载时，对应的维持时长为W11。第2个选择控制信号端的选择控制信号的电压幅值V12加载时，对应的维持时长为W12。第3个选择控制信号端的选择控制信号的电压幅值V13加载时，对应的维持时长为W13。第4个选择控制信号端的选择控制信号的电压幅值V14加载时，对应的维持时长为W14。且W11<W12<W13<W14。或者，2 N个选择控制信号端中，选择控制信号端加载的信号的电压幅值依次降低。即，选择控制信号端加载对应电压幅值时的信号的维持时长依次降低。例如，第1个选择控制信号端的选择控制信号的电压幅值V11加载时，对应的维持时长为W21。第2个选择控制信号端的选择控制信号的电压幅值V12加载时，对应的维持时长为W22。第3个选择控制信号端的选择控制信号的电压幅值V13加载时，对应的维持时长为W23。第4个选择控制信号端的选择控制信号的电压幅值V14加载时，对应的维持时长为W24。且W11>W12>W13>W14。
当然，也可以使2 N个选择控制信号端中，各选择控制信号端加载的信号 的占空比相同。即在一个显示帧中，选择控制信号端加载对应电压幅值时的信号的维持时长均相同。
下面以图4所示的像素电路的结构为例，结合图6所示的信号时序图，以及图7所示的电平示意图，对本公开实施例提供的像素电路在一个显示帧内的工作过程进行说明。下面以上述信号的有效电平为高电平为例进行说明。
图6中，ga1_1代表第1个第一扫描信号端GA_1的信号，ga1_2代表第2个第一扫描信号端GA_2的信号，ga1_3代表第3个第一扫描信号端GA_3的信号，em代表发光控制信号端EM的信号，da1代表第一数据信号端DA1的信号，cx_1代表第1个选择控制信号端CX_1的信号，cx_2代表第2个选择控制信号端CX_2的信号，cx_3代表第3个选择控制信号端CX_3的信号，cx_4代表第4个选择控制信号端CX_4的信号。并且，信号cx_1～cx_4是直流信号，且信号cx_1的电压幅值为V11，信号cx_2的电压幅值为V12，信号cx_3的电压幅值为V13，信号cx_4的电压幅值为V14，且V11<V12<V13<V14。
图7中，“0”代表数据信号Vda1～Vda3中的任一个为低电平，“1”代表数据信号Vda1～Vda3中的任一个为高电平。
在一些示例中，数据信号Vda1～Vda3均为低电平时，可以将第3个选择控制信号端CX_3的信号cx_3的电压V13提供给发光器件L的正极。具体过程如下：信号ga1_1、ga1_2、ga1_3依次出现高电平信号，则低电平的Vda1～Vda3依次输入第1个输入节点N1_1至第3个输入节点N1_3，以使第1个输入节点N1_1至第3个输入节点N1_3的信号均为低电平。由于第1个输入节点N1_1的信号为低电平，通过第一锁存器S1的作用，可以将数据信号Vda1进行锁存，并使节点A的信号为高电平信号，第二锁存器S2S2_1将其输入端和输出端断开，第1个控制节点N2_1不输入信号，则第1个第二晶体管M2_1不会导通。由于第2个输入节点N1_2的信号为低电平，且第2个输入节点N1_2和第2个控制节点N2_2共用，则第2个控制节点N2_2的信号为低电平，因此第2个第二晶体管M2_2截止。由于第3个输入节点N1_3的信号为低电平，且第3个输入节点N1_3和第4个控制节点N2_4共用，则 第4个控制节点N2_4的信号为低电平，因此第4个第二晶体管M2_4截止。由于第1个输入节点N1_1的信号为低电平，则第二锁存器S2S2_2导通，将第3个输入节点N1_3的低电平信号进行反相后输出给第3个控制节点N2_3，使第3个控制节点N2_3的电平为高电平，控制第3个第二晶体管M2_3导通。导通的第3个第二晶体管M2_3将第3个选择控制信号端CX_3的信号cx_3提供给第三晶体管M3。在信号em为高电平时，控制第三晶体管M3导通，以将第3个选择控制信号端CX_3的信号cx_3提供给发光器件L的正极，从而使电压V13输入发光器件L的正极，驱动发光器件L发光。
在另一些示例中，数据信号Vda1～Vda2均为低电平，数据信号Vda3为高电平时，可以将第4个选择控制信号端CX_4的信号cx_4的电压V14提供给发光器件L的正极。具体过程如下：信号ga1_1、ga1_2、ga1_3依次出现高电平信号，则低电平的Vda1～Vda2以及高电平的Vda3依次输入第1个输入节点N1_1至第3个输入节点N1_3，以使第1个输入节点N1_1和第2个输入节点N1_2的信号均为低电平，第3个输入节点N1_3的信号为高电平。由于第1个输入节点N1_1的信号为低电平，通过第一锁存器S1的作用，可以将数据信号Vda1进行锁存，并使节点A的信号为高电平信号，第二锁存器S2S2_1将其输入端和输出端断开，第1个控制节点N2_1不输入信号，则第1个第二晶体管M2_1不会导通。由于第2个输入节点N1_2的信号为低电平，且第2个输入节点N1_2和第2个控制节点N2_2共用，则第2个控制节点N2_2的信号为低电平，因此第2个第二晶体管M2_2截止。由于第1个输入节点N1_1的信号为低电平，则第二锁存器S2S2_2导通，将第3个输入节点N1_3的高电平信号进行反相后输出给第3个控制节点N2_3，使第3个控制节点N2_3的电平为低电平，控制第3个第二晶体管M2_3截止。由于第3个输入节点N1_3的信号为高电平，且第3个输入节点N1_3和第4个控制节点N2_4共用，则第4个控制节点N2_4的信号为高电平，因此第4个第二晶体管M2_4导通。导通的第4个第二晶体管M2_4将第4个选择控制信号端CX_4的信号cx_4提供给第三晶体管M3。在信号em为高电平时，控制第三晶体管 M3导通，以将第4个选择控制信号端CX_4的信号cx_4提供给发光器件L的正极，从而使电压V14输入发光器件L的正极，驱动发光器件L发光。
在又一些示例中，数据信号Vda2～Vda3均为低电平，数据信号Vda1为高电平时，可以将第1个选择控制信号端CX_1的信号cx_1的电压V11提供给发光器件L的正极。具体过程如下：信号ga1_1、ga1_2、ga1_3依次出现高电平信号，则高电平的Vda1以及低电平的Vda2～Vda3依次输入第1个输入节点N1_1至第3个输入节点N1_3，以使第1个输入节点N1_1的信号为高电平，第2个输入节点N1_2和第3个输入节点N1_3的信号均为低电平。由于第1个输入节点N1_1的信号为高电平，通过第一锁存器S1的作用，可以将数据信号Vda1进行锁存，并使节点A的信号为低电平信号，第二锁存器S2S2_1将第2个输入节点N1_2的低电平进行反相后提供给第1个控制节点N2_1，使第1个控制节点N2_1的信号为高电平，控制第1个第二晶体管M2_1导通。导通的第1个第二晶体管M2_1将第1个选择控制信号端CX_1的信号cx_1提供给第三晶体管M3。在信号em为高电平时，控制第三晶体管M3导通，以将第1个选择控制信号端CX_1的信号cx_1提供给发光器件L的正极，从而使电压V11输入发光器件L的正极，驱动发光器件L发光。由于第2个输入节点N1_2的信号为低电平，且第2个输入节点N1_2和第2个控制节点N2_2共用，则第2个控制节点N2_2的信号为低电平，因此第2个第二晶体管M2_2截止。由于第1个输入节点N1_1的信号为高电平，则第二锁存器S2S2_2将其输入端和输出端断开，第3个控制节点N2_3不输入信号，则第3个第二晶体管M2_3不会导通。由于第3个输入节点N1_3的信号为低电平，且第3个输入节点N1_3和第4个控制节点N2_4共用，则第4个控制节点N2_4的信号为低电平，因此第4个第二晶体管M2_4截止。
在又一些示例中，数据信号Vda1～Vda2均为高电平，数据信号Vda3为低电平时，可以将第2个选择控制信号端CX_2的信号cx_2的电压V12提供给发光器件L的正极。具体过程如下：信号ga1_1、ga1_2、ga1_3依次出现高电平信号，则高电平的Vda1～Vda2以及低电平的Vda3依次输入第1个输 入节点N1_1至第3个输入节点N1_3，以使第1个输入节点N1_1和第2个输入节点N1_2的信号为高电平，第3个输入节点N1_3的信号为低电平。由于第1个输入节点N1_1的信号为高电平，通过第一锁存器S1的作用，可以将数据信号Vda1进行锁存，并使节点A的信号为低电平信号，第二锁存器S2S2_1将第2个输入节点N1_2的高电平进行反相后提供给第1个控制节点N2_1，使第1个控制节点N2_1的信号为低电平，控制第1个第二晶体管M2_1截止。由于第2个输入节点N1_2的信号为高电平，且第2个输入节点N1_2和第2个控制节点N2_2共用，则第2个控制节点N2_2的信号为高电平，因此第2个第二晶体管M2_2导通。导通的第2个第二晶体管M2_2将第2个选择控制信号端CX_2的信号cx_2提供给第三晶体管M3。在信号em为高电平时，控制第三晶体管M3导通，以将第2个选择控制信号端CX_2的信号cx_2提供给发光器件L的正极，从而使电压V12输入发光器件L的正极，驱动发光器件L发光。由于第1个输入节点N1_1的信号为高电平，则第二锁存器S2S2_2将其输入端和输出端断开，第3个控制节点N2_3不输入信号，则第3个第二晶体管M2_3不会导通。由于第3个输入节点N1_3的信号为低电平，且第3个输入节点N1_3和第4个控制节点N2_4共用，则第4个控制节点N2_4的信号为低电平，因此第4个第二晶体管M2_4截止。
下面以图4所示的像素电路的结构为例，结合图8a与图8b所示的信号时序图，以及图9所示的电平示意图，对本公开实施例提供的像素电路在一个显示帧内的工作过程进行说明。下面以上述信号的有效电平为高电平为例进行说明。
图8a与图8b中，ga1_1代表第1个第一扫描信号端GA_1的信号，ga1_2代表第2个第一扫描信号端GA_2的信号，ga1_3代表第3个第一扫描信号端GA_3的信号，em代表发光控制信号端EM的信号，da1代表第一数据信号端DA1的信号，cx_1代表第1个选择控制信号端CX_1的信号，cx_2代表第2个选择控制信号端CX_2的信号，cx_3代表第3个选择控制信号端CX_3的信号，cx_4代表第4个选择控制信号端CX_4的信号。并且，信号cx_1～cx_4 是直流信号，且信号cx_1的电压幅值为V11，信号cx_2的电压幅值为V12，信号cx_3的电压幅值为V13，信号cx_4的电压幅值为V14，且V11<V12<V13<V14。其中，结合图8a，信号ga1_2为低电平，则第2个第一晶体管M1_2截止。第2个输入节点N1_2不输入信号，因此第2个第二晶体管M2_2不会导通。结合图8b，信号ga1_3为低电平，则第3个第一晶体管M1_3截止。第3个输入节点N1_3不输入信号，因此第4个第二晶体管M2_4不会导通。
图9中，“0”代表数据信号Vda1～Vda3中的任一个为低电平，“1”代表数据信号Vda1～Vda3中的任一个为高电平。“-”代表未输入信号。
在一些示例中，结合图8a，数据信号Vda1和Vda3均为低电平，Vda2不输入信号时，可以将第3个选择控制信号端CX_3的信号cx_3的电压V13提供给发光器件L的正极。具体过程如下：信号ga1_1、ga1_3依次出现高电平信号，信号ga1_2为低电平，则低电平的Vda1和Vda3依次输入第1个输入节点N1_1和第3个输入节点N1_3，以使第1个输入节点N1_1和第3个输入节点N1_3的信号均为低电平。由于第1个输入节点N1_1的信号为低电平，通过第一锁存器S1的作用，可以将数据信号Vda1进行锁存，并使节点A的信号为高电平信号，第二锁存器S2S2_1将其输入端和输出端断开，第1个控制节点N2_1不输入信号，则第1个第二晶体管M2_1不会导通。由于第3个输入节点N1_3的信号为低电平，且第3个输入节点N1_3和第4个控制节点N2_4共用，则第4个控制节点N2_4的信号为低电平，因此第4个第二晶体管M2_4截止。由于第1个输入节点N1_1的信号为低电平，则第二锁存器S2S2_2导通，将第3个输入节点N1_3的低电平信号进行反相后输出给第3个控制节点N2_3，使第3个控制节点N2_3的电平为高电平，控制第3个第二晶体管M2_3导通。导通的第3个第二晶体管M2_3将第3个选择控制信号端CX_3的信号cx_3提供给第三晶体管M3。在信号em为高电平时，控制第三晶体管M3导通，以将第3个选择控制信号端CX_3的信号cx_3提供给发光器件L的正极，从而使电压V13输入发光器件L的正极，驱动发光器件L发光。
在另一些示例中，结合图8a，数据信号Vda1为低电平，数据信号Vda3为高电平，数据信号Vda2不输入时，可以将第4个选择控制信号端CX_4的信号cx_4的电压V14提供给发光器件L的正极。具体过程如下：信号ga1_1、ga1_3依次出现高电平信号，则低电平的Vda1输入第1个输入节点N1_1，高电平的Vda3输入第3个输入节点N1_3，以使第1个输入节点N1_1的信号为低电平，第3个输入节点N1_3的信号为高电平。由于第1个输入节点N1_1的信号为低电平，通过第一锁存器S1的作用，可以将数据信号Vda1进行锁存，并使节点A的信号为高电平信号，第二锁存器S2S2_1将其输入端和输出端断开，第1个控制节点N2_1不输入信号，则第1个第二晶体管M2_1不会导通。由于第1个输入节点N1_1的信号为低电平，则第二锁存器S2S2_2导通，将第3个输入节点N1_3的高电平信号进行反相后输出给第3个控制节点N2_3，使第3个控制节点N2_3的电平为低电平，控制第3个第二晶体管M2_3截止。由于第3个输入节点N1_3的信号为高电平，且第3个输入节点N1_3和第4个控制节点N2_4共用，则第4个控制节点N2_4的信号为高电平，因此第4个第二晶体管M2_4导通。导通的第4个第二晶体管M2_4将第4个选择控制信号端CX_4的信号cx_4提供给第三晶体管M3。在信号em为高电平时，控制第三晶体管M3导通，以将第4个选择控制信号端CX_4的信号cx_4提供给发光器件L的正极，从而使电压V14输入发光器件L的正极，驱动发光器件L发光。
在又一些示例中，结合图8b，数据信号Vda1为高电平，数据信号Vda2为低电平，数据信号Vda3不输入时，可以将第1个选择控制信号端CX_1的信号cx_1的电压V11提供给发光器件L的正极。具体过程如下：信号ga1_1、ga1_3依次出现高电平信号，则高电平的Vda1以及低电平的Vda2依次输入第1个输入节点N1_1和第2个输入节点N1_2，以使第1个输入节点N1_1的信号为高电平，第2个输入节点N1_2的信号为低电平。由于第1个输入节点N1_1的信号为高电平，通过第一锁存器S1的作用，可以将数据信号Vda1进行锁存，并使节点A的信号为低电平信号，第二锁存器S2S2_1将第2个输 入节点N1_2的低电平进行反相后提供给第1个控制节点N2_1，使第1个控制节点N2_1的信号为高电平，控制第1个第二晶体管M2_1导通。导通的第1个第二晶体管M2_1将第1个选择控制信号端CX_1的信号cx_1提供给第三晶体管M3。在信号em为高电平时，控制第三晶体管M3导通，以将第1个选择控制信号端CX_1的信号cx_1提供给发光器件L的正极，从而使电压V11输入发光器件L的正极，驱动发光器件L发光。由于第2个输入节点N1_2的信号为低电平，且第2个输入节点N1_2和第2个控制节点N2_2共用，则第2个控制节点N2_2的信号为低电平，因此第2个第二晶体管M2_2截止。由于第1个输入节点N1_1的信号为高电平，则第二锁存器S2S2_2将其输入端和输出端断开，第3个控制节点N2_3不输入信号，则第3个第二晶体管M2_3不会导通。
在又一些示例中，结合图8b，数据信号Vda1～Vda2均为高电平，数据信号Vda3不输入时，可以将第2个选择控制信号端CX_2的信号cx_2的电压V12提供给发光器件L的正极。具体过程如下：信号ga1_1、ga1_3依次出现高电平信号，则高电平的Vda1～Vda2依次输入第1个输入节点N1_1和第2个输入节点N1_2，以使第1个输入节点N1_1和第2个输入节点N1_2的信号均为高电平。由于第1个输入节点N1_1的信号为高电平，通过第一锁存器S1的作用，可以将数据信号Vda1进行锁存，并使节点A的信号为低电平信号，第二锁存器S2S2_1将第2个输入节点N1_2的高电平进行反相后提供给第1个控制节点N2_1，使第1个控制节点N2_1的信号为低电平，控制第1个第二晶体管M2_1截止。由于第2个输入节点N1_2的信号为高电平，且第2个输入节点N1_2和第2个控制节点N2_2共用，则第2个控制节点N2_2的信号为高电平，因此第2个第二晶体管M2_2导通。导通的第2个第二晶体管M2_2将第2个选择控制信号端CX_2的信号cx_2提供给第三晶体管M3。在信号em为高电平时，控制第三晶体管M3导通，以将第2个选择控制信号端CX_2的信号cx_2提供给发光器件L的正极，从而使电压V12输入发光器件L的正极，驱动发光器件L发光。由于第1个输入节点N1_1的信号为高 电平，则第二锁存器S2S2_2将其输入端和输出端断开，第3个控制节点N2_3不输入信号，则第3个第二晶体管M2_3不会导通。
本公开实施例提供了像素电路的另一些结构示意图，其结构示意图参照图10。其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在本公开实施例中，如图10所示，发光控制子电路41还与第二扫描信号端GA2、第二数据信号端DA2、复位信号端RE耦接，发光控制子电路41被配置为响应于发光控制信号端EM的信号、输出节点N3的信号、第二扫描信号端GA2加载的信号、第二数据信号端DA2加载的数据信号、复位信号端RE加载的信号，驱动待驱动器件工作。示例性地，发光控制子电路41包括：第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、存储电容CST以及驱动晶体管M0；第四晶体管M4的控制端与发光控制信号端EM耦接，第四晶体管M4的第一端与输出节点N3耦接，第四晶体管M4的第二端与第五晶体管M5的控制端耦接；第五晶体管M5的第一端与驱动晶体管M0的第二端耦接，第五晶体管M5的第一端与待驱动器件(如发光器件L)的第一端耦接；第六晶体管M6的控制端与第二扫描信号端GA2耦接，第六晶体管M6的第一端与复位信号端RE耦接，第六晶体管M6的第二端与驱动晶体管M0的第二端耦接；第七晶体管M7的控制端与第二扫描信号端GA2耦接，第七晶体管M7的第一端与第二数据信号端DA2耦接，第七晶体管M7的第二端与驱动晶体管M0的控制端耦接；驱动晶体管M0的第一端与第二参考电源端；待驱动器件(如发光器件L)的第二端与第一参考电源端VSS耦接。
示例性地，第四晶体管M4在发光控制信号端EM的信号为有效电平时导通，在发光控制信号端EM的信号为无效电平时截止。例如，第四晶体管M4为N型晶体管，则发光控制信号端EM的信号的有效电平为高电平，无效电平为低电平。或者，第四晶体管M4为P型晶体管，则发光控制信号端EM的信号的有效电平为低电平，无效电平为高电平。
示例性地，第五晶体管M5在其控制端的信号为有效电平时导通，在其控制端的信号为无效电平时截止。例如，第五晶体管M5为N型晶体管，则其控制端的信号的有效电平为高电平，无效电平为低电平。或者，第五晶体管M5为P型晶体管，则其控制端的信号的有效电平为低电平，无效电平为高电平。
示例性地，第六晶体管M6在第二扫描信号端GA2的信号为有效电平时导通，在第二扫描信号端GA2的信号为无效电平时截止。例如，第六晶体管M6为N型晶体管，则第二扫描信号端GA2的信号的有效电平为高电平，无效电平为低电平。或者，第六晶体管M6为P型晶体管，则第二扫描信号端GA2的信号的有效电平为低电平，无效电平为高电平。
示例性地，第七晶体管M7在第二扫描信号端GA2的信号为有效电平时导通，在第七扫描信号端的信号为无效电平时截止。例如，第七晶体管M7为N型晶体管，则第二扫描信号端GA2的信号的有效电平为高电平，无效电平为低电平。或者，第七晶体管M7为P型晶体管，则第二扫描信号端GA2的信号的有效电平为低电平，无效电平为高电平。
示例性地，第二参考电源端的电压为正值。驱动晶体管M0可以产生驱动电流，该驱动电流输入发光器件L后，可以驱动发光器件L发光。
在本公开一些实施例中，2 N个选择控制信号端中的每一个选择控制信号端加载的信号均为脉宽调制信号。
示例性地，2 N个选择控制信号端中，各选择控制信号端加载的信号的占空比不同。其占空比指的是：在一个显示帧中，选择控制信号端加载有效电平时的维持时长。可选地，2 N个选择控制信号端中，选择控制信号端加载的信号的占空比依次升高。即，选择控制信号端加载有效电平时的维持时长依次升高。例如，如图11所示，第1个选择控制信号端CX_1的选择控制信号cx_1的有效电平对应的维持时长为0。第2个选择控制信号端CX_2的选择控制信号cx_2的有效电平对应的维持时长为W22。第3个选择控制信号端CX_3的选择控制信号cx_3的有效电平对应的维持时长为W23。第4个选择控制信 号端CX_4的选择控制信号cx_4的有效电平对应的维持时长为W24。且0<W22<W23<W24。或者，2 N个选择控制信号端中，选择控制信号端加载的信号的占空比依次降低。
下面以图4所示的像素电路的结构为例，结合图11所示的信号时序图，以及图7所示的电平示意图，对本公开实施例提供的像素电路在一个显示帧内的工作过程进行说明。下面以上述信号的有效电平为高电平为例进行说明。
图11中，ga2代表第二扫描信号端GA2的信号，ga1_1代表第1个第一扫描信号端GA_1的信号，ga1_2代表第2个第一扫描信号端GA_2的信号，ga1_3代表第3个第一扫描信号端GA_3的信号，em代表发光控制信号端EM的信号，da1代表第一数据信号端DA1的信号，da2代表第二数据信号端DA2的信号，cx_1代表第1个选择控制信号端CX_1的信号，cx_2代表第2个选择控制信号端CX_2的信号，cx_3代表第3个选择控制信号端CX_3的信号，cx_4代表第4个选择控制信号端CX_4的信号。
在一些示例中，信号ga2为高电平时，第七晶体管M7导通，第二数据信号端DA2的数据信号Vda0输入驱动晶体管M0的控制端，以使驱动晶体管M0的控制端电压为数据信号Vda0的电压V03。并且，第六晶体管M6导通，复位信号端RE的复位信号输入驱动晶体管M0的第二端，对驱动晶体管M0的第二端复位。数据信号Vda1～Vda3均为低电平时，可以将第3个选择控制信号端CX_3的信号cx_3提供给第四晶体管M4。在信号em为高电平时，控制第四晶体管M4导通，以将第3个选择控制信号端CX_3的信号cx_3提供给第五晶体管M5的控制端，在信号cx_3为高电平时，控制第五晶体管M5导通，驱动晶体管M0根据其控制端和第二参考电源端的电压可以产生驱动电流I_3，该驱动电流I_3输入发光器件L的正极，驱动发光器件L发光。
在另一些示例中，信号ga2为高电平时，第七晶体管M7导通，第二数据信号端DA2的数据信号Vda0输入驱动晶体管M0的控制端，以使驱动晶体管M0的控制端电压为数据信号Vda0的电压V04。并且，第六晶体管M6导通，复位信号端RE的复位信号输入驱动晶体管M0的第二端，对驱动晶体管 M0的第二端复位。数据信号Vda1～Vda2均为低电平，数据信号Vda3为高电平时，可以将第4个选择控制信号端CX_4的信号cx_4提供给第四晶体管M4。在信号em为高电平时，控制第四晶体管M4导通，以将第4个选择控制信号端CX_4的信号cx_4提供给第五晶体管M5的控制端，在信号cx_4为高电平时，控制第五晶体管M5导通，驱动晶体管M0根据其控制端和第二参考电源端的电压可以产生驱动电流I_4，该驱动电流I_4输入发光器件L的正极，驱动发光器件L发光。
在又一些示例中，信号ga2为高电平时，第七晶体管M7导通，第二数据信号端DA2的数据信号Vda0输入驱动晶体管M0的控制端，以使驱动晶体管M0的控制端电压为数据信号Vda0的电压V01。并且，第六晶体管M6导通，复位信号端RE的复位信号输入驱动晶体管M0的第二端，对驱动晶体管M0的第二端复位。数据信号Vda2～Vda3均为低电平，数据信号Vda1为高电平时，可以将第1个选择控制信号端CX_1的信号cx_1提供给第四晶体管M4。在信号em为高电平时，控制第四晶体管M4导通，以将第1个选择控制信号端CX_1的信号cx_1提供给第五晶体管M5的控制端，由于信号cx_1的占空比为0，则其一直处于低电平，因此控制第五晶体管M5截止，驱动晶体管M0根据其控制端和第二参考电源端的电压可以产生驱动电流I_1，该驱动电流I_1不能输入发光器件L，发光器件L为暗态。
在又一些示例中，信号ga2为高电平时，第七晶体管M7导通，第二数据信号端DA2的数据信号Vda0输入驱动晶体管M0的控制端，以使驱动晶体管M0的控制端电压为数据信号Vda0的电压V02。并且，第六晶体管M6导通，复位信号端RE的复位信号输入驱动晶体管M0的第二端，对驱动晶体管M0的第二端复位。数据信号Vda1～Vda2均为高电平，数据信号Vda3为低电平时，可以将第2个选择控制信号端CX_2的信号cx_2提供给第四晶体管M4。在信号em为高电平时，控制第四晶体管M4导通，以将第2个选择控制信号端CX_2的信号cx_2提供给第五晶体管M5的控制端，在信号cx_2为高电平时，控制第五晶体管M5导通，驱动晶体管M0根据其控制端和第二参 考电源端的电压可以产生驱动电流I_2，该驱动电流I_2输入发光器件L，驱动发光器件L发光。
需要说明的是，根据人眼视觉的积分效应，当发光时间越长时，人眼感知的亮度越亮，通过控制第1个选择控制信号端CX_1至第4个选择控制信号端CX_4的信号cx_1～cx_4的占空比不同，可以对发光器件L的发光时长进行控制，使人眼根据该发光时长感知不同的发光亮度，进而使像素单元实现2 N个灰阶的显示。例如，在Vda0的电压V01～V04相同时，可以通过控制第1个选择控制信号端CX_1至第4个选择控制信号端CX_4的信号cx_1～cx_4的占空比不同，来控制发光器件L实现4个不同的亮度。进一步地，也可以使Vda0的电压V01～V04不同，这样可以通过控制驱动电流I_1～I_4不同，并结合控制第1个选择控制信号端CX_1至第4个选择控制信号端CX_4的信号cx_1～cx_4的占空比不同，进一步来控制发光器件L实现多个不同的亮度。并且，在第1个选择控制信号端CX_1的信号cx_1输出时，由于第1个选择控制信号端CX_1的信号cx_1占空比为0，此时发光器件L不发光，为暗态，因此可以实现发光器件L暗态较暗的效果。在第4个选择控制信号端CX_4的信号cx_4输出时，由于第4个选择控制信号端CX_4的信号cx_4占空比最大，此时发光器件L最亮，即可以实现最大灰阶的亮度。进一步地，在第2个选择控制信号端CX_2至第4个选择控制信号端CX_4的信号cx_2～cx_4中的任一个输出时，可以控制Vda0的电压V02～V04不同，从而进一步对发光器件L的亮度进行细分，进而使发光器件L可以实现更多的灰阶的显示，有效的提高了低灰阶的亮度均一性。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些 改动和变型在内。

Claims (19)

  1. 一种像素电路，包括：
    输入电路，分别与第一数据信号端、2 N-1个第一扫描信号端以及2 N-1个输入节点耦接，且所述2 N-1个第一扫描信号端与所述2 N-1个输入节点一一对应；所述输入电路被配置为响应于所述2 N-1个第一扫描信号端中加载的信号，将所述第一数据信号端加载的数据信号输入对应的输入节点；N为大于1的整数；
    控制电路，分别与2 N-1个输入节点耦接；所述控制电路被配置为响应于所述2 N-1个输入节点中的至少两个输入节点的信号，分别控制2 N个控制节点的信号；
    输出电路，分别与所述2 N个控制节点、2 N个选择控制信号端以及输出节点耦接，且所述2 N个控制节点与所述2 N个选择控制信号端一一对应；所述输出电路被配置为响应于所述2 N个控制节点中的第m个控制节点的信号，将所述2 N个选择控制信号端中的第m个选择控制信号端的信号提供给所述输出节点；1≤m≤2 N，且m为整数；
    发光驱动电路，分别与所述输出节点以及待驱动器件耦接；所述发光驱动电路被配置为响应于所述输出节点的信号，驱动所述待驱动器件工作。
  2. 如权利要求1所述的像素电路，其中，所述输入电路包括：2 N-1个输入子电路；所述2 N-1个输入子电路中的第k个输入子电路分别与所述2 N-1个第一扫描信号端中的第k个第一扫描信号端以及所述2 N-1个输入节点中的第k个输入节点耦接；
    所述第k个输入子电路被配置为响应于所述第k个第一扫描信号端加载的信号，将所述第一数据信号端加载的数据信号输入所述第k个输入节点；1≤k≤2 N-1，且k为整数。
  3. 如权利要求2所述的像素电路，其中，所述第k个输入子电路包括第k个第一晶体管；
    所述第k个第一晶体管的控制端与所述第k个第一扫描信号端耦接，所述第k个第一晶体管的第一端与所述第一数据信号端耦接，所述第k个第一晶体管的第二端与所述第k个输入节点耦接。
  4. 如权利要求1-3任一项所述的像素电路，其中，所述控制电路包括：2 N-1个控制子电路，所述2 N-1个控制子电路的输入端与所述2 N-1个输入节点一一对应耦接；
    所述2 N-1个控制子电路定义为第1级控制子电路至第N级控制子电路；其中，各所述第N级控制子电路与所述2 N个控制节点中的两个控制节点一一对应，且所述第N级控制子电路的输入端与对应的所述两个控制节点中的一个控制节点耦接，所述第N级控制子电路的输出端与对应的所述两个控制节点中的另一个控制节点耦接；
    每一个第q-1级控制子电路对应两个第q级控制子电路，所述两个第q级控制子电路中的一个第q级控制子电路的控制端与对应的所述第q-1级控制子电路的输出端耦接，另一个第q级控制子电路的控制端与对应的所述第q-1级控制子电路的输入端耦接；所述第q级控制子电路被配置为响应于加载到其控制端上的信号，将输入端的信号提供给其输出端；2≤q≤N，且q为整数。
  5. 如权利要求4所述的像素电路，其中，所述第1级控制子电路包括第一锁存器；
    所述第一锁存器的输入端作为所述第1级控制子电路的输入端，所述第一锁存器的输出端作为所述第1级控制子电路的输出端。
  6. 如权利要求5所述的像素电路，其中，所述第一锁存器包括：第一反相器和第二反相器；
    所述第一反相器的输入端作为所述第一锁存器的输入端，所述第一反相器的输出端作为所述第一锁存器的输出端；
    所述第二反相器的输入端与所述第一反相器的输出端耦接，所述第二反相器的输出端与所述第一反相器的输入端耦接。
  7. 如权利要求4-6任一项所述的像素电路，其中，所述第q级控制子电 路包括：第二锁存器；
    所述第二锁存器的控制端作为所述第q级控制子电路的控制端，所述第二锁存器的输入端作为所述第q级控制子电路的输入端，所述第二锁存器的输出端作为所述第q级控制子电路的输出端。
  8. 如权利要求7所述的像素电路，其中，所述第二锁存器包括：第一三态门和第二三态门；
    所述第一三态门的控制端作为所述第二锁存器的控制端，所述第一三态门的输入端作为所述第二锁存器的输入端，所述第一三态门的输出端作为所述第二锁存器的输出端；
    所述第二三态门的控制端与所述第一三态门的控制端耦接，所述第二三态门的输入端与所述第一三态门的输出端耦接，所述第二三态门的输出端与所述第一三态门的输入端耦接。
  9. 如权利要求1-8任一项所述的像素电路，其中，所述输出电路包括：2 N个输出子电路；所述2 N个输出子电路中的第m个输出子电路与所述第m个控制节点、第m个选择控制信号端以及所述输出节点耦接；
    所述第m个输出子电路被配置为响应于所述第m个控制节点的信号，将所述第m个选择控制信号端的信号提供给所述输出节点。
  10. 如权利要求9所述的像素电路，其中，所述第m个输出子电路包括第m个第二晶体管；
    所述第m个第二晶体管的控制端与所述第m个控制节点耦接，所述第m个第二晶体管的第一端与所述第m个选择控制信号端耦接，所述第m个第二晶体管的第二端与所述输出节点耦接。
  11. 如权利要求1-10任一项所述的像素电路，其中，所述发光驱动电路包括：发光控制子电路；
    所述发光控制子电路分别与所述输出节点、发光控制信号端以及所述待驱动器件耦接；所述发光控制子电路被配置为响应于所述发光控制信号端和所述输出节点的信号，驱动所述待驱动器件工作。
  12. 如权利要求11所述的像素电路，其中，所述发光控制子电路包括第三晶体管；所述第三晶体管的控制端与所述发光控制信号端耦接，所述第三晶体管的第一端与所述输出节点耦接，所述第三晶体管的第二端与所述待驱动器件的第一端耦接，
    所述待驱动器件的第二端与第一参考电源端耦接。
  13. 如权利要求12所述的像素电路，其中，所述发光控制子电路还与第二扫描信号端、第二数据信号端、复位信号端耦接；
    所述发光控制子电路被配置为响应于所述发光控制信号端的信号、所述输出节点的信号、所述第二扫描信号端加载的信号、所述第二数据信号端加载的数据信号、所述复位信号端加载的信号，驱动所述待驱动器件工作。
  14. 如权利要求13所述的像素电路，其中，所述发光控制子电路包括：第四晶体管、第五晶体管、第六晶体管、第七晶体管、存储电容以及驱动晶体管；
    所述第四晶体管的控制端与所述发光控制信号端耦接，所述第四晶体管的第一端与所述输出节点耦接，所述第四晶体管的第二端与所述第五晶体管的控制端耦接；
    所述第五晶体管的第一端与所述驱动晶体管的第二端耦接，所述第五晶体管的第一端与所述待驱动器件的第一端耦接；
    所述第六晶体管的控制端与所述第二扫描信号端耦接，所述第六晶体管的第一端与所述复位信号端耦接，所述第六晶体管的第二端与所述驱动晶体管的第二端耦接；
    所述第七晶体管的控制端与所述第二扫描信号端耦接，所述第七晶体管的第一端与所述第二数据信号端耦接，所述第七晶体管的第二端与所述驱动晶体管的控制端耦接；
    所述驱动晶体管的第一端与第二参考电源端；
    所述待驱动器件的第二端与第一参考电源端耦接。
  15. 一种显示装置，包括多个如权利要求1-14任一项所述的像素电路。
  16. 一种像素电路的驱动方法，其中，所述驱动方法用于驱动如权利要求1-14任一项所述的像素电路，所述驱动方法包括：
    对所述2 N-1个第一扫描信号端中的一个第一扫描信号端加载有效电平的信号，对其余第一扫描信号端加载无效电平的信号，将所述第一数据信号端加载的数据信号输入对应加载所述有效电平的第一扫描信号端的输入节点；
    所述控制电路响应于所述2 N-1个输入节点中的至少两个输入节点的信号，分别控制2 N个控制节点的信号；
    所述输出电路响应于所述2 N个控制节点中的第m个控制节点的信号，将所述2 N个选择控制信号端中的第m个选择控制信号端的信号提供给所述输出节点；
    发光驱动电路响应于所述输出节点的信号，驱动所述待驱动器件工作。
  17. 如权利要求16所述的驱动方法，其中，所述2 N个选择控制信号端中，各所述选择控制信号端加载的信号的电压幅值不同。
  18. 如权利要求16或17所述的驱动方法，其中，所述2 N个选择控制信号端中，各所述选择控制信号端加载的信号的占空比不同。
  19. 如权利要求16-18任一项所述的驱动方法，其中，所述2 N个选择控制信号端中的每一个选择控制信号端加载的信号均为直流电压信号或脉宽调制信号。
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