WO2023242991A1 - 電力用半導体装置 - Google Patents

電力用半導体装置 Download PDF

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Publication number
WO2023242991A1
WO2023242991A1 PCT/JP2022/023945 JP2022023945W WO2023242991A1 WO 2023242991 A1 WO2023242991 A1 WO 2023242991A1 JP 2022023945 W JP2022023945 W JP 2022023945W WO 2023242991 A1 WO2023242991 A1 WO 2023242991A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor
region
active region
semiconductor region
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/023945
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English (en)
French (fr)
Japanese (ja)
Inventor
博也 ▲濱▼田
毅 大佐賀
留依 小西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to DE112022007374.8T priority Critical patent/DE112022007374T5/de
Priority to JP2024527986A priority patent/JPWO2023242991A1/ja
Priority to CN202280096984.0A priority patent/CN119384878A/zh
Priority to US18/855,922 priority patent/US20250287624A1/en
Priority to PCT/JP2022/023945 priority patent/WO2023242991A1/ja
Publication of WO2023242991A1 publication Critical patent/WO2023242991A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/10—Arrangements for heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/415—Insulated-gate bipolar transistors [IGBT] having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/076—Connecting or disconnecting of strap connectors
    • H10W72/07651—Connecting or disconnecting of strap connectors characterised by changes in properties of the strap connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • the present disclosure relates to a power semiconductor device, and more particularly, to a power semiconductor device in which the maximum junction temperature of a semiconductor substrate is lowered.
  • Patent Document 1 discloses a technique for suppressing TjMAX by making the current carrying capacity of a cell structure in the center of a semiconductor substrate smaller than that of a cell structure in the outer periphery.
  • This technology suppresses TjMAX by reducing heat generation in the central part of the semiconductor substrate, which has poor heat dissipation. However, if the area with low current carrying capacity is too wide, energy loss will increase, which may actually increase TjMAX. There is sex.
  • Patent Document 1 in order to lower TjMAX, the current carrying capacity of the cell structure in the central part of the semiconductor substrate, which has low heat dissipation, is made smaller than that of the cell structure in the outer periphery. If the area of the structure is made too large, the energy loss increases, so some kind of condition setting is required, but Patent Document 1 does not sufficiently disclose this.
  • the present disclosure has been made to solve the above problems, and aims to provide a power semiconductor device that can reliably suppress TjMAX.
  • a power semiconductor device is a power semiconductor device in which a main current flows in the thickness direction of a semiconductor substrate, wherein the semiconductor substrate is provided in a central portion of the semiconductor substrate, and a first and a second active region provided outside the first active region, the power semiconductor device includes a second active region provided outside the first and second active regions.
  • the first active region has two opposing sides and a second two opposing sides in a second direction perpendicular to the first direction, and the first active region has a distance from the center of the semiconductor substrate.
  • the distance is set to less than 1/4 of the length of either of the lengths, and the first current carrying capacity of the first active region is the same as that of the second active region. is set lower than the second current carrying capacity.
  • heat generation can be suppressed in the central portion of the semiconductor substrate, and the maximum junction temperature can be reliably suppressed.
  • FIG. 1 is a schematic cross-sectional view of a power semiconductor device according to a first embodiment of the present disclosure.
  • 1 is a plan view of a semiconductor substrate of a power semiconductor device according to a first embodiment of the present disclosure
  • FIG. 3 is a diagram showing the dependence of the maximum junction temperature of the semiconductor substrate on the area of the active region of the power semiconductor device of Embodiment 1 according to the present disclosure.
  • FIG. 2 is a partial cross-sectional view showing the configuration of a power semiconductor device according to a second embodiment of the present disclosure.
  • FIG. 7 is a partial cross-sectional view showing the configuration of a power semiconductor device according to a third embodiment of the present disclosure.
  • FIG. 4 is a partial cross-sectional view showing the configuration of a power semiconductor device according to a fourth embodiment of the present disclosure. 7 is a partial cross-sectional view showing the configuration of a power semiconductor device according to a fifth embodiment of the present disclosure.
  • top, bottom, side, front, or back that mean a specific position and direction may be used, but these terms are It is used for convenience in order to facilitate understanding of the content of the embodiment, and has no relation to the direction in which it will be actually implemented.
  • outside is a direction toward the outer periphery of the semiconductor substrate, and “inside” is a direction opposite to “outside”.
  • n and p indicate the conductivity type of the semiconductor, and in the present disclosure, the first conductivity type is described as n type and the second conductivity type as p type, but the first conductivity type is p type and the second conductivity type is can also be of n-type.
  • n ⁇ type indicates that the impurity concentration is lower than that of n type
  • n + type indicates that the impurity concentration is higher than that of n type.
  • p ⁇ type indicates that the impurity concentration is lower than that of p type
  • p + type indicates that the impurity concentration is higher than that of p type.
  • FIG. 1 is a schematic cross-sectional view of a power semiconductor device according to a first embodiment of the present disclosure.
  • the power semiconductor device may be any of a power IGBT, a power MOSFET, and a power diode, but will be described as a power IGBT 100 as an example.
  • a semiconductor substrate 11 is bonded onto a heat sink 132 via a conductive bonding layer 12b (second bonding layer) such as a solder layer.
  • a collector electrode (not shown) is provided on the lower surface (second main surface) of the semiconductor substrate 11, and a heat sink 132 is directly bonded to the collector electrode via the bonding layer 12b.
  • an insulating sheet 14 is provided on the lower surface of the heat sink 132.
  • a conductor plate 131 is bonded to the upper surface (first main surface) of the semiconductor substrate 11 via a conductive bonding layer 12a (first bonding layer) such as a solder layer.
  • An emitter electrode (not shown) is provided on the upper surface of the semiconductor substrate 11, and a conductor plate 131 is directly bonded to the emitter electrode via a bonding layer 12b.
  • the semiconductor substrate 11 includes an active region 11b (first active region) provided at the center of the substrate, an active region 11a (second active region) surrounding the active region 11b, and an active region through which a main current flows. It has a terminal region 11c outside the region 11a.
  • the active region 11b is an active region whose current carrying capacity (collector current) per unit area is lower than that of the active region 11a.
  • the power IGBT 100 is housed in a resin case, the insulating sheet 14 on the bottom surface of the heat sink 132 is exposed from the bottom surface of the resin case, and there is a seal (not shown) inside the resin case. Filled with stopper resin.
  • the power IGBT 100 resin-sealed in the resin case as described above can increase its cooling capacity by being mounted on a heat dissipation member such as a heat sink. Note that it is also possible to provide a conductor plate under the insulating sheet 14 and expose the conductor plate from the bottom surface of the resin case.
  • the bonding layer 12a is provided only in a region excluding the region where a structure for inputting a gate signal such as a gate wiring and a gate pad (not shown) is provided, that is, only on an emitter electrode (not shown), whereas the bonding layer 12b is It is provided over the entire surface of a collector electrode (not shown) provided on the entire lower surface (second main surface) of the semiconductor substrate 11 . Therefore, the heat dissipation performance of the semiconductor substrate 11 can be ensured.
  • FIG. 2 is a plan view of the semiconductor substrate 11 in FIG. 1 viewed from above, and the bonding layer 12a and the conductor plate 131 are omitted for convenience.
  • the active region 11b is provided as a circular region, the radius of which is indicated as "d". Furthermore, the radius d of the active region 11b is set to d ⁇ X/4.
  • X is the length between two long sides, and can be said to be the first length between the first two sides facing each other in the first direction.
  • Y is the length between the two short sides, and can be said to be the second length between the second two sides facing each other in the second direction orthogonal to the first direction.
  • the shape of the active region 11b in plan view is not limited to a circle; in the case of FIG. You can also.
  • the shape of the active region 11a in plan view is a rectangle in which the relationship between horizontal length Y and vertical length X in plan view is X ⁇ Y; however, X ⁇ Y Any shape is acceptable, and the shape in plan view may be square.
  • the gate pad 4 is provided at the center of the lower side of the semiconductor substrate 11, but the position of the gate pad 4 is not limited to this. Further, a gate wiring (not shown) is connected to the gate pad 4, but the gate wiring can be provided along the periphery of the active region 11a.
  • the horizontal axis shows the distance (d) from the center of the semiconductor substrate corresponding to the radius d of the active region 11b, and the vertical axis shows TjMAX (° C.).
  • TjMAX is constant at about 112.6°C regardless of the radius d from the center of the semiconductor substrate.
  • the current carrying capacity of the active region 11b becomes smaller than that of the active region 11a, it changes depending on the radius d from the center of the semiconductor substrate, that is, the area of the active region 11b.
  • TjMAX when the current carrying capacity ratio of the active region 11b is 0.8, TjMAX is 112° C. near the radius d of X/4, and thereafter TjMAX increases rapidly as the radius d approaches X/4.
  • This characteristic is the same for other current carrying capacity ratios, and has a characteristic that reaches its minimum value at a temperature close to 112°C.
  • the current carrying capacity ratio of the active region 11b is set to be less than 1
  • the radius d of the active region 11b from the center of the semiconductor substrate 11 is set to 1/ of the length X of the vertical side of the active region 11a of the semiconductor substrate 11. If it is within the range of less than 4, TjMAX can be lowered than when the current carrying capacity ratio of the active region 11b is 1. Note that if the radius d is made too small, TjMAX will increase, so it is desirable that the radius d not be made smaller than X/8.
  • the power IGBT 100 have a structure in which heat is radiated through the bonding layer 12a on the front side in addition to the structure in which heat is radiated to the bonding layer 12b on the back side. That is, in the power IGBT 100, the conductor plate 131 is directly bonded to the semiconductor substrate 11 via the bonding layer 12a by DLB (Direct Lead Bonding), so that This is because heat can be radiated to a metal frame or the like with high heat dissipation.
  • DLB Direct Lead Bonding
  • TjMAX increases if the active region 11b is made too wide, such as by making the radius d of the active region 11b from the center of the semiconductor substrate 11 equal to or larger than X/4.
  • FIG. 4 is a cross-sectional view showing the configuration of a power IGBT 200 according to a second embodiment of the present disclosure, and is a partial cross-sectional view of the semiconductor substrate 11 near the boundary region between the active region 11a and the active region 11b. Note that the overall cross-sectional view of the power IGBT 200 is the same as the power IGBT 100 shown in FIG. 1, and the same components are denoted by the same reference numerals and redundant explanations will be omitted.
  • FIG. 4 shows a cross-sectional configuration of the cell structure of the power IGBT 200, and is a cross-sectional view taken along line AA in the plan view of the semiconductor substrate 11 shown in FIG.
  • a p + type collector region 38 (first semiconductor region) is provided on the back side of the semiconductor substrate 11, and an n ⁇ type drift region 34 (second semiconductor region) is provided on the collector region 38.
  • a p-type body region 33 (third semiconductor region) is provided on the drift region 34 .
  • a plurality of n + type source (emitter) regions 37a and 37b are selectively provided in the upper layer of the body region 33. Further, a plurality of trenches 35 are provided from the outermost surface of the body region 33 to penetrate the body region 33 and reach into the drift region 34 .
  • the arrangement interval 31a and the arrangement interval 31b of the trenches 35 in the active region 11a and the active region 11b are the same.
  • the inner wall of the trench 35 is covered with a gate insulating film 36, and the inside of the gate insulating film 36 is filled with a gate electrode 39.
  • the gate electrodes 39 are individually covered with insulating films 32, and the upper surface of the semiconductor substrate 11 including the insulating films 32 is covered with an emitter electrode 31. Note that a collector electrode is provided on the opposite side of the emitter electrode 31 across the semiconductor substrate 11, but is not shown for convenience.
  • each of the source regions 37a and 37b is provided so as to be in contact with the side of the trench 35, that is, the side of the gate insulating film 36.
  • the source region 37b is provided in the active region 11b, and the source region 37a is provided in the active region 11a, but the impurity concentration of the n-type impurity in the source region 37b is higher than the impurity concentration of the n-type impurity in the source region 37a. is also set low. By setting in this way, the amount of carriers in the active region 11b decreases, and the current carrying capacity of the active region 11b becomes lower than that of the active region 11a.
  • the impurity concentration of the source region 37b may be made lower than that of the source region 37a. If it is lowered by 50%, the current carrying capacity can be lowered by 12%.
  • the source regions 37a and 37b are formed separately by performing an impurity implantation process twice in the manufacturing process using an impurity implantation mask for forming the source region 37a and an impurity implantation mask for forming the source region 37b. realizable.
  • FIG. 5 is a cross-sectional view showing the configuration of a power IGBT 300 according to a third embodiment of the present disclosure, and is a partial cross-sectional view of the semiconductor substrate 11 near the boundary region between the active region 11a and the active region 11b.
  • the same components as the power IGBT 200 described using FIG. 4 are denoted by the same reference numerals, and redundant explanation will be omitted.
  • the source region 37b is provided in the active region 11b, and the source region 37a is provided in the active region 11a.
  • the width of the source region 37b that is, the extension of the gate electrode 39 of the source region 37b is The length along the direction in which the gate electrode 39 extends is shorter than the width of the source region 37a, that is, the length of the source region 37a in the direction in which the gate electrode 39 extends.
  • the width of the source region 37b may be made shorter than that of the source region 37a.
  • the width of the source region 37b may be made shorter than that of the source region 37a. If the length is also shortened by 50%, the current carrying capacity can be lowered by 10%.
  • the source regions 37a and 37b can be formed separately by using impurity implantation masks with different implantation opening lengths in the impurity implantation masks for forming the source regions 37a and 37b in the manufacturing process. This can be achieved with a single impurity implantation process.
  • FIG. 6 is a cross-sectional view showing the configuration of a power IGBT 400 according to a fourth embodiment of the present disclosure, and is a partial cross-sectional view of the semiconductor substrate 11 near the boundary region between the active region 11a and the active region 11b.
  • the same components as the power IGBT 200 described using FIG. 4 are denoted by the same reference numerals, and redundant explanation will be omitted.
  • the spacing 31b between the trenches 35 in the active region 11b is set wider than the spacing 31a between the trenches 35 in the active region 11a.
  • the carrier accumulation effect is an effect of lowering the on-resistance and suppressing the on-voltage by accumulating carriers in the drift region 34, and by widening the arrangement interval 31b of the trenches 35 in the active region 11b, carriers are accumulated.
  • the ability to conduct electricity decreases, and the ability to conduct electricity decreases.
  • the spacing 31b between the trenches 35 in the active region 11b may be made wider than the spacing 31a between the trenches 35 in the active region 11a. For example, if the arrangement interval 31b is made 50% wider than the arrangement interval 31a, the current carrying capacity can be lowered by 3%.
  • the arrangement intervals 31a and 31b of the trenches 35 are created separately by etching the active regions 11a and 11b with different opening intervals in the etching mask for forming the trenches 35 in the manufacturing process. This can be achieved by etching using a mask.
  • FIG. 7 is a cross-sectional view showing the configuration of a power IGBT 500 according to a fifth embodiment of the present disclosure, and is a partial cross-sectional view of the semiconductor substrate 11 near the boundary region between the active region 11a and the active region 11b. Note that in FIG. 7, the same components as those of the power IGBT 200 described using FIG. 4 are denoted by the same reference numerals, and redundant explanation will be omitted.
  • the collector regions are formed with different impurity concentrations in the active region 11a and the active region 11b, with the active region 11a being a collector region 38a and the active region 11b being a collector region 38b.
  • the p + type impurity concentration of the collector region 38b of the active region 11b is set lower than the impurity concentration of the collector region 38a of the active region 11a.
  • the impurity concentration of the collector region 38b may be made lower than the impurity concentration of the collector region 38a. By making it 50% lower than the region 38a, the current carrying capacity can be lowered by 26%.
  • the collector regions 38a and 38b are formed separately by performing an impurity implantation process twice in the manufacturing process using an impurity implantation mask for forming the collector region 38a and an impurity implantation mask for forming the collector region 38b. realizable.
  • the current carrying capacity ratio of the active region 11b to the active region 11a shown in FIG. 3 can be adjusted to 0.9, 0.8, 0.7, or 0.6 by combining a plurality of parameters. For example, by making the width of the source region 37b about 50% shorter than that of the source region 37a, the current carrying capacity ratio can be adjusted to about 0.9. Furthermore, if the width of the source region 37b is made approximately 50% shorter than that of the source region 37a, and the impurity concentration of the source region 37b is made approximately 50% lower than that of the source region 37a, the current carrying capacity ratio can be adjusted to approximately 0.8. can.
  • the spacing 31b between the trenches 35 in the active region 11b is made about 50% wider than the spacing 31a between the trenches 35 in the active region 11a, and the impurity concentration in the collector region 38b is made about 50% larger than that in the collector region 38a. If it is lowered, the current carrying capacity ratio can be adjusted to about 0.7. Further, the width of the source region 37b is made about 50% shorter than that of the source region 37a, the impurity concentration of the source region 37b is made about 50% lower than that of the source region 37a, and the impurity concentration of the collector region 38b is made about 50% shorter than that of the source region 37a. By making it about 50% lower than the region 38a, the current carrying capacity ratio can be adjusted to about 0.6.

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
PCT/JP2022/023945 2022-06-15 2022-06-15 電力用半導体装置 Ceased WO2023242991A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE112022007374.8T DE112022007374T5 (de) 2022-06-15 2022-06-15 Leistungshalbleitervorrichtung
JP2024527986A JPWO2023242991A1 (https=) 2022-06-15 2022-06-15
CN202280096984.0A CN119384878A (zh) 2022-06-15 2022-06-15 功率用半导体装置
US18/855,922 US20250287624A1 (en) 2022-06-15 2022-06-15 Power semiconductor device
PCT/JP2022/023945 WO2023242991A1 (ja) 2022-06-15 2022-06-15 電力用半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2022/023945 WO2023242991A1 (ja) 2022-06-15 2022-06-15 電力用半導体装置

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WO2023242991A1 true WO2023242991A1 (ja) 2023-12-21

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JP (1) JPWO2023242991A1 (https=)
CN (1) CN119384878A (https=)
DE (1) DE112022007374T5 (https=)
WO (1) WO2023242991A1 (https=)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004363327A (ja) * 2003-06-04 2004-12-24 Fuji Electric Device Technology Co Ltd 半導体装置
JP2010004003A (ja) * 2008-05-20 2010-01-07 Mitsubishi Electric Corp パワー半導体装置
JP2010123873A (ja) * 2008-11-21 2010-06-03 Sanyo Electric Co Ltd 絶縁ゲート型半導体装置
JP2017147433A (ja) * 2015-12-16 2017-08-24 ローム株式会社 半導体装置
WO2019078131A1 (ja) * 2017-10-18 2019-04-25 富士電機株式会社 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004363327A (ja) * 2003-06-04 2004-12-24 Fuji Electric Device Technology Co Ltd 半導体装置
JP2010004003A (ja) * 2008-05-20 2010-01-07 Mitsubishi Electric Corp パワー半導体装置
JP2010123873A (ja) * 2008-11-21 2010-06-03 Sanyo Electric Co Ltd 絶縁ゲート型半導体装置
JP2017147433A (ja) * 2015-12-16 2017-08-24 ローム株式会社 半導体装置
WO2019078131A1 (ja) * 2017-10-18 2019-04-25 富士電機株式会社 半導体装置

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DE112022007374T5 (de) 2025-04-10
JPWO2023242991A1 (https=) 2023-12-21
CN119384878A (zh) 2025-01-28

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