WO2023240706A1 - 显示模组、驱动方法及显示装置 - Google Patents

显示模组、驱动方法及显示装置 Download PDF

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Publication number
WO2023240706A1
WO2023240706A1 PCT/CN2022/103045 CN2022103045W WO2023240706A1 WO 2023240706 A1 WO2023240706 A1 WO 2023240706A1 CN 2022103045 W CN2022103045 W CN 2022103045W WO 2023240706 A1 WO2023240706 A1 WO 2023240706A1
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sub
thin film
electrically connected
data lines
power consumption
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PCT/CN2022/103045
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English (en)
French (fr)
Inventor
龚强
许作远
戴荣磊
郭军辉
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武汉华星光电技术有限公司
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Priority to KR1020227030045A priority Critical patent/KR20230173572A/ko
Publication of WO2023240706A1 publication Critical patent/WO2023240706A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of display technology, and specifically to a display module, a driving method, and a display device.
  • the sub-pixels arranged in an array are usually lit row by row, that is, each The row sub-pixels are turned on in response to the corresponding scan line, and are charged by the corresponding data line to be lit, thereby displaying a complete frame of the picture.
  • the voltage on the data line constantly changes between high level and low level according to the display needs of each row of sub-pixels, resulting in high power consumption of the display panel.
  • Embodiments of the present application provide a display panel, a driving method and a display device, which can improve the technical problem of high power consumption of the display panel.
  • An embodiment of the present application provides a display module, including a display panel.
  • the display panel includes a display area and a non-display area surrounding at least one side of the display area.
  • the display panel includes: a plurality of data lines along a column. extending in the row direction and at least partially located within the display area; a plurality of scan lines extending along the row direction and at least partially located within the display area to form a plurality of sub-pixel areas with a plurality of the data lines; and Sub-pixels are located in a plurality of sub-pixel regions, and each sub-pixel is electrically connected to the corresponding scanning line and the corresponding data line; wherein the display module further includes a neutralization circuit,
  • the neutralization circuit includes at least one control terminal and at least two coupling terminals. At least one control terminal is used to control on-off between at least two coupling terminals. At least two coupling terminals are electrically connected to At least two of the data lines.
  • the neutralization circuit includes a plurality of thin film transistors, the gate of each thin film transistor serves as the corresponding control terminal, and the source and drain of each thin film transistor serve as the corresponding two terminals.
  • the coupling end is electrically connected to the corresponding two data lines.
  • the data lines electrically connected to two adjacent thin film transistors are different.
  • one of the source electrode and the drain electrode of each thin film transistor is electrically connected to one of the data lines, and the middle of the source electrode and the drain electrode of each thin film transistor is electrically connected to one of the data lines. The other one is electrically connected to the other data line through the corresponding thin film transistor.
  • the other one of the source electrodes and the drain electrodes of the plurality of thin film transistors is grounded.
  • the sub-pixels in the same column have the same polarity
  • the sub-pixels in two adjacent columns have opposite polarities
  • the source and drain of each thin film transistor are respectively connected to Two data lines corresponding to the sub-pixels in two adjacent columns with opposite polarities.
  • the display module further includes a driver chip, a plurality of the data lines are electrically connected to the driver chip, and the gates of the plurality of thin film transistors of the neutralization circuit pass through at least One of the control signal lines is electrically connected to the driver chip.
  • the non-display area includes a first area and a second area located on opposite sides of a plurality of scan lines, and a plurality of data lines are electrically connected to the driver through the first area.
  • a plurality of thin film transistors of the neutralization circuit are located in the second region.
  • At least one of the control signal lines is located in the non-display area, and each of the control signal lines includes a first section located in the second area and extending along the row direction. Two second sections extending from opposite ends of the first section toward the first area along the row direction, and two third sections extending oppositely from both ends of the two second sections, the first section The segments are electrically connected to the gates of the plurality of thin film transistors, and the two third segments are electrically connected to the driver chip.
  • Embodiments of the present application also provide a driving method, applied to the display module as described above, including: comparing the first power consumption and the second power consumption, wherein the first power consumption is the sub-second power consumption from the current row.
  • the power consumption of charging the first voltage on the data line corresponding to the pixel to the second voltage on the data line corresponding to the sub-pixel in the next row, and the second power consumption is from the voltage on the data line corresponding to the sub-pixel in the current row.
  • the third voltage on the data line is charged to the power consumption of the second voltage on the data line corresponding to the sub-pixel in the next row, and the third voltage is generated by at least one of the neutralization circuits.
  • the control terminal is loaded with an effective level so that at least two of the coupling terminals are turned on to neutralize the first voltage on the data line corresponding to the sub-pixel in the current row; according to the comparison result , to send a control signal to at least one control terminal of the neutralization circuit to control the on-off of at least two coupling terminals after the sub-pixels in the current row are turned off and before the sub-pixels in the next row are turned on. .
  • sending the control signal causes the effective level to be loaded to at least one of the control terminals of the neutralization circuit, such that At least two coupling ends are connected.
  • the control signal when the first power consumption is less than or equal to the second power consumption, the control signal is sent so that an invalid level is loaded to at least one of the control terminals of the neutralization circuit, such that At least two coupling terminals are disconnected.
  • An embodiment of the present application also provides a display device, including the display module as described above.
  • the display module driving method and display device provided by the embodiments of the present application, you can choose whether to turn on the neutralization circuit, so that the display module operates in a lower power consumption mode. be driven, which can significantly reduce power consumption.
  • Figure 1 is a schematic top view of a display module provided by an embodiment of the present application.
  • Figure 2 is a schematic top view of the display panel in Figure 1;
  • FIG 3 is a schematic diagram of the driving timing of the display panel in Figure 1;
  • Figure 4 is a schematic top view of a display panel provided by an embodiment of the present application.
  • FIG. 5 is a schematic flowchart of a driving method of a display module provided by an embodiment of the present application.
  • an embodiment of the present application provides a display module 1000 , including a display panel 1 and a circuit board.
  • the circuit board includes a driver chip 8 electrically connected to the display panel 1 .
  • the display panel 1 may be an LCD display panel or an OLED display panel. In this embodiment, the display panel 1 is an LCD display panel.
  • the display panel 1 includes a display area DA and a non-display area NDA.
  • the display area DA may be an area for setting sub-pixels of a display image.
  • the non-display area NDA may be an area used to provide a driving unit such as a gate driving circuit that provides a driving signal to a pixel driving circuit of a sub-pixel, and an area used to provide some traces that provide a signal to the driving unit.
  • a driving unit such as a gate driving circuit that provides a driving signal to a pixel driving circuit of a sub-pixel, and an area used to provide some traces that provide a signal to the driving unit.
  • the non-display area NDA generally no sub-pixels for display are provided.
  • the non-display area NDA may be disposed on at least one side of the display area DA to at least partially surround the display area DA.
  • the non-display area NDA includes opposite first areas NDA1 and second areas NDA2.
  • the display panel 1 includes a plurality of data lines 10 , a plurality of scan lines 11 , a plurality of sub-pixels SPX, and a neutralization circuit 13 .
  • a plurality of data lines 10 extend along the column direction, are at least partially located in the display area DA, and are electrically connected to the driver chip 8 through the demultiplexing circuit MUX in the first area NDA1.
  • the demultiplexing circuit MUX includes a plurality of thin film transistors, which can reduce the number of data terminals of the driving chip.
  • a plurality of scan lines 11 extend along the row direction, are at least partially located in the display area DA, and are electrically connected to the circuit board through a gate driving circuit GDC located in the non-display area NDA.
  • the plurality of scanning lines 11 and the plurality of data lines 10 surround a plurality of sub-pixel areas SPA.
  • a plurality of sub-pixels SPX are located in a plurality of sub-pixel areas SPA.
  • the sub-pixel SPX is the smallest controllable light-emitting unit in the display panel 1 and may include a pixel driving circuit and a liquid crystal cell driven by the pixel driving circuit.
  • the pixel driving circuit is electrically connected to the corresponding scanning line 11 and the corresponding data line 10 .
  • the pixel driving circuit may include at least one thin film transistor.
  • the gate electrode of the thin film transistor is arranged in the same layer as a plurality of the scan lines 11 and has the same material.
  • the source electrode and the drain electrode of the thin film transistor are connected to a plurality of the data.
  • Line 10 is set on the same layer and made of the same material.
  • the sub-pixel SPX may include a pixel driving circuit and an organic light-emitting device driven by the pixel driving circuit.
  • the neutralization circuit 13 is located in the second area NDA2, so that the width of the first area NDA1 (ie, the lower frame) can be reduced.
  • the neutralizing circuit 13 includes a plurality of thin film transistors 130, and the plurality of thin film transistors 130 are arranged on the same layer as the thin film transistors in the display area DA. In this way, the neutralizing circuit 13 can be integrated in the array substrate.
  • each thin film transistor 130 are electrically connected to the two data lines 10 , and are different from the data lines 10 electrically connected to the two adjacent thin film transistors 130 , so that multiple The source and drain of the thin film transistor 130 serve as at least two coupling terminals 138 of the neutralization circuit 13 and are electrically connected to at least two data lines 10 . In this way, the voltages on the two data lines 10 can be neutralized through one thin film transistor 130 .
  • the plurality of sub-pixels SPX are driven in a column inversion manner, so that the sub-pixels SPX in the same column have the same polarity, and the sub-pixels SPX in two adjacent columns have opposite polarities.
  • each thin film transistor 130 The source electrode and the drain electrode of each thin film transistor 130 are respectively connected to the two data lines 10 corresponding to the sub-pixels SPX in two adjacent columns with opposite polarities. In this way, after the voltages of the two data lines 10 corresponding to the sub-pixels SPX in two adjacent columns with opposite polarities are neutralized to obtain an intermediate value, and then charged to the corresponding voltages with opposite polarities, it can be reduced power consumption.
  • the gates of the plurality of thin film transistors 130 serve as at least one control terminal 139 of the neutralization circuit 13 and are electrically connected to the driving chip 8 through at least one control signal line SW to control the operation according to the driving chip 8
  • a control signal is used to control the on-off connection between at least two coupling terminals 138 , thereby controlling the electrical connection between at least two data lines 10 .
  • At least one of the control signal lines SW is located in the non-display area NDA, is arranged on the same layer as the plurality of data lines 10 and has the same material.
  • Each of the control signal lines SW includes a first section SW1 located in the second area NDA2 and extending along the row direction, from opposite ends of the first section SW1 towards the column direction towards the third section SW1.
  • Two second sections SW2 extending from a region NDA1, and two third sections SW3 extending oppositely from both ends of the two second sections SW2, the first section SW1 is electrically connected to a plurality of the thin film transistors 130
  • the gate electrode and the two third sections SW3 are electrically connected to the driver chip 8 . In this way, the function of the control signal line SW can be realized without affecting the settings of other signal lines.
  • the material of the control signal line SW may include molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au) , at least one of nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu) .
  • the control signal line SW may have a single-layer structure or a multi-layer structure.
  • the control signal line SW may be formed in a stacked structure such as Ti/Al/Ti, Mo/Al/Mo, Mo/AlGe/Mo, Ti/Cu, or the like.
  • the driving chip 8 outputs a control signal to the center through at least one of the control signal lines SW. and at least one control terminal 139 of the neutralization circuit 13, so that at least two coupling terminals 138 of the neutralization circuit 13 are connected or disconnected.
  • the driver chip 8 When the driver chip 8 outputs a control signal (such as a VGL signal) to at least one control terminal 139 of the neutralization circuit 13 through at least one of the control signal lines SW, the neutralization circuit 13 At least two of the coupling terminals 138 are disconnected, that is, when the display module 1000 is in the normal driving mode, the first voltage on the data line 10 corresponding to the sub-pixel SPX in the current row is directly charged to the next The second voltage of the data line 10 corresponding to one row of sub-pixels SPX.
  • a control signal such as a VGL signal
  • the driver chip 8 When the driver chip 8 outputs a control signal (such as a VGH signal) to at least one control terminal 139 of the neutralization circuit 13 through at least one of the control signal lines SW, at least two of the couplings of the neutralization circuit 13 Terminal 138 is connected, that is, when the display module 1000 is in the neutral driving mode, the first voltage on the data line 10 corresponding to the sub-pixel SPX in the current row is first neutralized to the third voltage, and then charged to the lower voltage. The second voltage of the data line 10 corresponding to one row of sub-pixels SPX.
  • a control signal such as a VGH signal
  • the display module 1000 can determine the driving mode of the display module 1000 based on various screens and the power consumption of the display module 1000 in these two driving modes to select optimal power consumption conditions, especially in Under heavy loading and other screens, the power consumption can be significantly reduced, and the effect is remarkable.
  • the neutralization circuit 13 is turned on for 0.2 ⁇ s, the potential on the data line 10 can be reduced by more than 90%.
  • each thin film transistor 130 is electrically connected to one of the data lines 10
  • each The other one of the source electrode and the drain electrode of the thin film transistor 130 is electrically connected to the other data line 10 through the corresponding thin film transistor 130 .
  • the plurality of thin film transistors 130 are used to electrically connect the plurality of data lines 10 to each other, so that the voltages on the plurality of data lines 10 can be neutralized.
  • the other one of the source electrode and the drain electrode of the plurality of thin film transistors 130 is connected to the ground line GND.
  • control signal lines SW there may be multiple control signal lines SW, and the thin film transistors 130 connected to the multiple control signal lines SW are different. In this way, the driving speed of the neutralizing circuit by the driving chip 8 can be increased.
  • An embodiment of the present application also provides a driving method applied to the above-mentioned display module 1000.
  • the driving method may be executed by the driver chip 8 of the display module 1000 , or may be executed by a processor of the display device including the display module 1000 , such as a central processing chip.
  • the driving method includes:
  • Step S1 Compare the first power consumption and the second power consumption.
  • the first power consumption is charging from the first voltage on the data line 10 corresponding to the sub-pixel SPX in the current row to the sub-pixel SPX in the next row.
  • the power consumption corresponding to the second voltage of the data line 10 the second power consumption is charging from the third voltage on the data line 10 corresponding to the sub-pixel SPX of the current row to the sub-pixel of the next row.
  • SPX corresponds to the power consumption of the second voltage of the data line 10.
  • the third voltage is obtained by loading an effective level on at least one of the control terminals 139 of the neutralization circuit 13, so that at least two of the The coupling terminal 138 is turned on to neutralize the first voltage on the data line 10 corresponding to the sub-pixel SPX of the current row.
  • the first voltages on the data lines 10 corresponding to the sub-pixels SPX in row G(n) are x 1 , x 2 ...x m respectively, and G(n) after voltage neutralization
  • the third voltages on the data lines 10 corresponding to the sub-pixels SPX in the rows are y 1 , y 2 ...y m respectively, and the data lines corresponding to the sub-pixels SPX in the G(n+1) row
  • the second voltages on 10 are X 1 , X 2 —
  • the second power consumption B in the neutral drive mode (X 1 -y 1 ) 2 +(X 2 -y 2 ) 2 + whil+(X m -y m ) 2 .
  • Step S2 According to the comparison result, after the sub-pixel SPX of the current row is turned off and before the sub-pixel SPX of the next row is turned on, a control signal is sent to at least one control terminal 139 of the neutralization circuit 13 to Control the on and off of at least two coupling terminals 138 .
  • the control signal is sent so that the effective level (for example, VGH signal) is loaded to at least one of the control elements of the neutralization circuit 13 terminal 139, so that at least two coupling terminals 138 of the neutralization circuit 13 are connected, the first voltage on the data line 10 corresponding to the sub-pixel SPX in the G(n) row is first neutralized to the third voltage, and then recharge to the second voltage of the data line 10 corresponding to G(n+1) sub-pixel SPX. Therefore, low power consumption can be achieved.
  • VGH signal the effective level
  • the sub-pixel SPX in row G(n) is turned off.
  • the control signal is sent so that an invalid level (for example, a VGL signal with a potential smaller than the VGH signal) is loaded to the neutralization circuit 13
  • At least one of the control terminals 139 causes at least two coupling terminals 138 of the neutralization circuit 13 to be disconnected, and the first voltage on the data line 10 corresponding to the sub-pixel SPX in row G(n) is directly charged to the second voltage of the data line 10 corresponding to the G(n+1) sub-pixel SPX. Therefore, low power consumption can be achieved.
  • An embodiment of the present application also provides a display device, including the above-mentioned display module 1000, a processor electrically connected to the display module 1000, and a storage device.
  • the storage device is used to store program instructions, and the processor or the driver chip of the display module 1000 is used to execute the program instructions to implement the above driving method.
  • the storage device may be a read-only memory (ROM) and a random access memory (RAM) of the display device, or may be a flash memory of the display module.
  • the display device is a device with a display function.
  • the display device may be a device that displays video or still images, including fixed terminals such as televisions, desktop computers, monitors, and billboards, and may also include mobile terminals such as Mobile phones, tablet computers, mobile communication terminals, electronic notepads, e-books, multimedia players, navigators, laptops, and may also include wearable electronic devices such as smart watches, smart glasses, virtual reality devices, and augmented reality devices.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种显示模组（1000）、驱动方法和显示装置。显示模组（1000）包括显示面板（1），显示面板（1）包括多个数据线（10）；多个扫描线（11）；以及多个子像素（SPX），位于多个扫描线（11）与多个数据线（10）围成的多个子像素区域（SPA）内；显示模组（1000）还包括中和电路（13），中和电路（13）包括控制端（139）和耦接端（138），至少一控制端（139）用于控制至少两耦接端（138）之间的通断，至少两耦接端（138）电性连接于至少两数据线（10）。

Description

显示模组、驱动方法及显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种显示模组、一种驱动方法，以及一种显示装置。
背景技术
在现有的显示面板，如显示面板(LCD，Liquid Crystal Display)或有机发光二极管(OLED，Organic Light-Emitting Diode)显示面板中，阵列排布的子像素通常是被逐行点亮，即每行子像素响应于对应的扫描线被打开，被对应的所述数据线充电以被点亮，从而显示一帧完整的画面。数据线上的电压根据每行子像素的显示需要，不断地在高电平和低电平之间变化，导致显示面板的功耗较大。
技术问题
本申请实施例提供一种显示面板、一种驱动方法及一种显示装置，可以改善显示面板的功耗较大的技术问题。
技术解决方案
本申请的实施例提供一种显示模组，包括显示面板，所述显示面板包括显示区和围绕所述显示区至少一侧的非显示区，所述显示面板包括：多个数据线，沿列方向延伸，且至少部分位于所述显示区内；多个扫描线，沿行方向延伸，且至少部分位于所述显示区内，以与多个所述数据线围成多个子像素区域；以及多个子像素，位于多个所述子像素区域内，每一所述子像素电性连接于对应的所述扫描线以及对应的所述数据线；其中，所述显示模组还包括中和电路，所述中和电路包括至少一控制端和至少两耦接端，至少一所述控制端用于控制至少两所述耦接端之间的通断，至少两所述耦接端电性连接于至少两所述数据线。
在一些实施例中，所述中和电路包括多个薄膜晶体管，每一所述薄膜晶体管的栅极作为对应的所述控制端，每一所述薄膜晶体管的源极和漏极作为对应的两所述耦接端并电性连接于对应的两所述数据线。
在一些实施例中，与相邻的两所述薄膜晶体管电性连接的所述数据线不同。
在一些实施例中，每一所述薄膜晶体管的源极和漏极的中的一个电性连接于一个所述数据线，每一所述薄膜晶体管的所述源极和所述漏极的中的另一个通过对应的所述薄膜晶体管电性连接于另一个所述数据线。
在一些实施例中，多个所述薄膜晶体管的所述源极和所述漏极的中的另一个均接地。
在一些实施例中，同列的所述子像素的极性相同，相邻两列的所述子像素的极性相反，每一所述薄膜晶体管的所述源极和所述漏极分别连接于极性相反的相邻两列的所述子像素对应的两所述数据线。
在一些实施例中，所述显示模组还包括驱动芯片，多个所述数据线电性连接于所述驱动芯片，所述中和电路的多个所述薄膜晶体管的所述栅极通过至少一所述控制信号线电性连接于所述驱动芯片。
在一些实施例中，所述非显示区包括位于多个所述扫描线相对两侧的第一区和第二区，多个所述数据线通过所述第一区电性连接于所述驱动芯片，所述中和电路的多个所述薄膜晶体管位于所述第二区内。
在一些实施例中，至少一所述控制信号线位于所述非显示区内，每一所述控制信号线包括位于所述第二区内且沿所述行方向延伸的第一段，自所述第一段的相对两端沿所述列方向朝向所述第一区延伸的两第二段，以及自两所述第二段的两端相向延伸出的两第三段，所述第一段电性连接于多个所述薄膜晶体管的所述栅极，两所述第三段电性连接于所述驱动芯片。
本申请的实施例还提供一种驱动方法，应用于如上所述的显示模组，包括：比较第一功耗和第二功耗，其中，所述第一功耗为从当前行所述子像素对应的所述数据线上的第一电压充电至下一行所述子像素对应的所述数据线的第二电压的功耗，所述第二功耗为从当前行所述子像素对应的所述数据线上的第三电压充电至下一行所述子像素对应的所述数据线的所述第二电压的功耗，所述第三电压是通过对所述中和电路的至少一所述控制端加载有效电平，使得至少两所述耦接端导通以对当前行所述子像素对应的所述数据线上的所述第一电压进行中和之后而得到的；根据比较结果，以在当前行所述子像素被关闭之后 且在下一行所述子像素被开启之前，发送控制信号至所述中和电路的至少一所述控制端以控制至少两所述耦接端的通断。
在一些实施例中，所述第一功耗和所述第二功耗的计算公式为：A＝(X1-x1)2+(X2-x2)2+……+(Xm-xm)2，B＝(X1-y1)2+(X2-y2)2+……+(Xm-ym)2，其中，A指代所述第一功耗，B指代所述第二功耗，x1、x2……xm指代当前行所述子像素对应的所述数据线上的所述第一电压，y1、y2……ym指代当前行所述子像素对应的所述数据线上的所述第三电压，X1、X2……Xm指代下一行所述子像素对应的所述数据线上的所述第二电压。
在一些实施例中，当所述第一功耗大于所述第二功耗时，发送所述控制信号使得所述有效电平被加载至所述中和电路的至少一所述控制端，使得至少两所述耦接端连通。
在一些实施例中，当所述第一功耗小于或等于所述第二功耗时，发送所述控制信号使得无效电平被加载至所述中和电路的至少一所述控制端，使得至少两所述耦接端断开。
本申请的实施例还提供一种显示装置，包括如上所述的显示模组。
有益效果
相较于现有技术，在本申请的实施例提供的显示模组、驱动方法和显示装置中，可以通过来选择是否打开中和电路，使得所述显示模组在更低的功耗模式下被驱动，从而可以明显降低功耗。
附图说明
图1是本申请实施例提供的显示模组的俯视示意图；
图2是图1中的显示面板的俯视示意图；
图3是图1中的显示面板的驱动时序示意图；
图4是本申请实施例提供的显示面板的俯视示意图；
图5是本申请实施例提供的显示模组的驱动方法的流程示意图。
本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以 解释本申请，并不用于限定本申请。
如图1和图2所示，本申请的实施例提供一种显示模组1000，包括显示面板1以及电路板，所述电路板包括电性连接于所述显示面板1的驱动芯片8。所述显示面板1可以是LCD显示面板，也可以是OLED显示面板。本实施例中，所述显示面板1为LCD显示面板。
所述显示面板1包括显示区DA和非显示区NDA。所述显示区DA可以是用于设置显示图像的子像素的区域。所述非显示区NDA可以是用于设置为子像素的像素驱动电路提供驱动信号的驱动单元如栅极驱动电路，以及用于设置为所述驱动单元提供信号的一些走线的区域。在所述非显示区NDA内，一般没有设置用于显示的子像素。所述非显示区NDA可以设置在所述显示区DA的至少一侧，以至少部分地围绕所述显示区DA。所述非显示区NDA包括相对的第一区NDA1和第二区NDA2。
所述显示面板1包括多个数据线10、多个扫描线11、多个子像素SPX，以及中和电路13。
多个数据线10，沿列方向延伸，至少部分位于所述显示区DA内，且通过所述第一区NDA1内的解复用电路MUX电性连接于所述驱动芯片8。所述解复用电路MUX包括多个薄膜晶体管，可以减少所述驱动芯片的数据端子的数量。
多个扫描线11，沿行方向延伸，至少部分位于所述显示区DA内，且通过位于所述非显示区NDA内的栅极驱动电路GDC电性连接于所述电路板。多个所述扫描线11与多个所述数据线10围成多个子像素区域SPA。
多个子像素SPX，位于多个所述子像素区域SPA内。所述子像素SPX为显示面板1中的最小可控发光单元，可以包括像素驱动电路和由像素驱动电路驱动的液晶盒。所述像素驱动电路电性连接于对应的所述扫描线11以及对应的所述数据线10。所述像素驱动电路可以包括至少一薄膜晶体管，所述薄膜晶体管的栅极与多个所述扫描线11同层设置且材料相同，所述薄膜晶体管的源极和漏极与多个所述数据线10同层设置且材料相同。对于OLED显示面板来说，所述子像素SPX可以包括像素驱动电路和由像素驱动电路驱动的有机发光器件。
所述中和电路13位于所述第二区NDA2内，这样，可以减少第一区NDA1(即下边框)的宽度。所述中和电路13包括多个薄膜晶体管130，多个所述薄膜晶体管130与所述显示区DA内的薄膜晶体管同层设置，这样，可以将所述中 和电路13集成在阵列基板内。
每一所述薄膜晶体管130的源极和漏极电性连接于两所述数据线10，且与相邻的两所述薄膜晶体管130电性连接的所述数据线10不同，使得多个所述薄膜晶体管130的源极和漏极作为所述中和电路13的至少两所述耦接端138，电性连接于至少两所述数据线10。这样，可以通过一个所述薄膜晶体管130实现对两所述数据线10上的电压的中和。示例性地，多个所述子像素SPX采用列反转的方式进行驱动，使得同列的所述子像素SPX的极性相同，相邻两列的所述子像素SPX的极性相反。每一所述薄膜晶体管130的所述源极和所述漏极分别连接于极性相反的相邻两列的所述子像素SPX对应的两所述数据线10。这样，在将极性相反的相邻两列的所述子像素SPX对应的两数据线10的电压进行中和以得到中间值之后，再被分别充电至对应的极性相反的电压，可以减少功耗。
多个所述薄膜晶体管130的栅极作为所述中和电路13的至少一控制端139，通过至少一所述控制信号线SW电性连接于所述驱动芯片8，以根据所述驱动芯片8的控制信号来控制至少两所述耦接端138之间的通断，进而控制至少两所述数据线10之间的电性连接。
至少一所述控制信号线SW位于所述非显示区NDA内，与多个所述数据线10同层设置且材料相同。每一所述控制信号线SW包括位于所述第二区NDA2内且沿所述行方向延伸的第一段SW1，自所述第一段SW1的相对两端沿所述列方向朝向所述第一区NDA1延伸的两第二段SW2，以及自两所述第二段SW2的两端相向延伸出的两第三段SW3，所述第一段SW1电性连接于多个所述薄膜晶体管130的所述栅极，两所述第三段SW3电性连接于所述驱动芯片8。这样，可以实现所述控制信号线SW的功能，且不影响其他信号线的设置。示例性地，所述控制信号线SW的材料可以包括选自钼(Mo)、铝(Al)、铂(Pt)、钯(Pd)、银(Ag)、镁(Mg)、金(Au)、镍(Ni)、钕(Nd)、铱(Ir)、铬(Cr)、钙(Ca)、钛(Ti)、钽(Ta)、钨(W)、铜(Cu)中的至少一种。所述控制信号线SW可以是单层结构或多层结构。例如，所述控制信号线SW可以形成为Ti/Al/Ti、Mo/Al/Mo、Mo/AlGe/Mo、Ti/Cu等层叠结构。
在本实施例中，在当前行所述子像素SPX被关闭之后且在下一行所述子像素SPX被开启之前，所述驱动芯片8通过至少一所述控制信号线SW输出控制信号至所述中和电路13的至少一控制端139，使得所述中和电路13的至少两所述 耦接端138连通或者断开。
请一并参阅图3，当所述驱动芯片8通过至少一所述控制信号线SW输出控制信号(如VGL信号)至所述中和电路13的至少一控制端139，所述中和电路13的至少两所述耦接端138断开，即所述显示模组1000处于常规驱动模式时，当前行所述子像素SPX对应的所述数据线10上的第一电压，直接被充电至下一行所述子像素SPX对应的所述数据线10的第二电压。
当所述驱动芯片8通过至少一所述控制信号线SW输出控制信号(如VGH信号)至所述中和电路13的至少一控制端139，所述中和电路13的至少两所述耦接端138连通，即所述显示模组1000处于中和驱动模式时，当前行所述子像素SPX对应的所述数据线10上的第一电压先被中和至第三电压，再充电至下一行所述子像素SPX对应的所述数据线10的第二电压。
因此，所述显示模组1000可以基于各种画面，根据显示模组1000在这两种驱动方式下的功耗，来决定显示模组1000的驱动方式以选择功耗最优条件，特别是在重载等画面下，可以明显降低功耗，效果显著。通过模拟仿真，当所述中和电路13开启0.2μs，所述数据线10上的电位可降低90％以上。
请参阅图4，在其他实施例中，与上述实施例不同的是：每一所述薄膜晶体管130的源极和漏极的中的一个电性连接于一个所述数据线10，每一所述薄膜晶体管130的所述源极和所述漏极的中的另一个通过对应的所述薄膜晶体管130电性连接于另一个所述数据线10。通过多个所述薄膜晶体管130实现多个所述数据线10的相互电性连接，可以实现多个数据线10上的电压的中和。示例性地，多个所述薄膜晶体管130的所述源极和所述漏极的中的另一个均接地线GND。
在其他实施例中，所述控制信号线SW可以有多路，多路所述控制信号线SW连接的所述薄膜晶体管130不同。这样，可以提升所述驱动芯片8对所述中和电路的驱动速度。
请参阅图5，本申请的实施例还提供一种驱动方法，应用于上述显示模组1000。所述驱动方法可以被显示模组1000的驱动芯片8执行，也可以被包括所述显示模组1000的显示装置的处理器，例如中央处理芯片执行。所述驱动方法包括：
步骤S1，比较第一功耗和第二功耗，所述第一功耗为从当前行所述子像 素SPX对应的所述数据线10上的第一电压充电至下一行所述子像素SPX对应的所述数据线10的第二电压的功耗，所述第二功耗为从当前行所述子像素SPX对应的所述数据线10上的第三电压充电至下一行所述子像素SPX对应的所述数据线10的所述第二电压的功耗，所述第三电压是通过对所述中和电路13的至少一所述控制端139加载有效电平，使得至少两所述耦接端138导通以对当前行所述子像素SPX对应的所述数据线10上的所述第一电压进行中和之后而得到的。
示例性地，G(n)行所述子像素SPX对应的所述数据线10上的所述第一电压分别为x 1、x 2……x m，经过电压中和后的G(n)行所述子像素SPX对应的所述数据线10上的所述第三电压分别为y 1、y 2……y m，G(n+1)行所述子像素SPX对应的所述数据线10上的所述第二电压分别为X 1、X 2……X m，基于功耗与充电电压差的平方成正比，我们可以认为，在常规驱动模式下的所述第一功耗A＝(X 1-x 1) 2+(X 2-x 2) 2+……+(X m-x m) 2，在中和驱动模式下的所述第二功耗B＝(X 1-y 1) 2+(X 2-y 2) 2+……+(X m-y m) 2。通过比较所述第一功耗A和所述第二功耗B的大小，即可得知所述显示模组1000在常规驱动模式和中和驱动模式下的功耗大小。
步骤S2，根据比较结果，以在当前行所述子像素SPX被关闭之后且在下一行所述子像素SPX被开启之前，发送控制信号至所述中和电路13的至少一所述控制端139以控制至少两所述耦接端138的通断。
当所述第一功耗A大于所述第二功耗B，即中和驱动模式下的显示模组1000具有更低的功耗时，在G(n)行所述子像素SPX被关闭之后且在G(n+1)行所述子像素SPX被开启之前，发送所述控制信号使得所述有效电平(例如，VGH信号)被加载至所述中和电路13的至少一所述控制端139，使得所述中和电路13的至少两所述耦接端138连通，G(n)行所述子像素SPX对应的所述数据线10上的第一电压先被中和至第三电压，再充电至G(n+1)所述子像素SPX对应的所述数据线10的第二电压。因此，可以实现低功耗。
当所述第一功耗A小于或等于所述第二功耗B，即常规驱动模式下的显示模组1000具有更低的功耗时，在G(n)行所述子像素SPX被关闭之后且在G(n+1)行所述子像素SPX被开启之前，发送所述控制信号使得无效电平(例 如，电位小于所述VGH信号的VGL信号)被加载至所述中和电路13的至少一所述控制端139，使得所述中和电路13的至少两所述耦接端138断开，G(n)行所述子像素SPX对应的所述数据线10上的第一电压直接被充电至G(n+1)所述子像素SPX对应的所述数据线10的第二电压。因此，可以实现低功耗。
本申请的实施例还提供一种显示装置，包括上述的显示模组1000、电性连接于所述显示模组1000的处理器，以及存储装置。所述存储装置用于存储程序指令，所述处理器或所述显示模组1000的所述驱动芯片用于执行所述程序指令，以实现上述驱动方法。所述存储装置可以是所述显示装置的只读存储器(ROM)和随机存取存储器(RAM)，也可以是显示模组的闪存。
所述显示装置是具有显示功能的装置，示例性地，所述显示装置可以是显示视频或静止图像的装置，包括固定终端诸如电视、台式计算机、监视器、广告牌，也可以包括移动终端诸如移动电话、平板电脑、移动通信终端、电子记事本、电子书、多媒体播放器、导航仪、笔记本电脑，还可以包括穿戴式电子设备诸如智能手表、智能眼镜、虚拟现实设备、增强现实设备。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示模组，其中，包括显示面板，所述显示面板包括显示区和围绕所述显示区至少一侧的非显示区，所述显示面板包括：
    多个数据线，沿列方向延伸，且至少部分位于所述显示区内；
    多个扫描线，沿行方向延伸，且至少部分位于所述显示区内，以与多个所述数据线围成多个子像素区域；以及
    多个子像素，位于多个所述子像素区域内，每一所述子像素电性连接于对应的所述扫描线以及对应的所述数据线；
    其中，所述显示模组还包括中和电路，所述中和电路包括至少一控制端和至少两耦接端，至少一所述控制端用于控制至少两所述耦接端之间的通断，至少两所述耦接端电性连接于至少两所述数据线。
  2. 根据权利要求1所述的显示模组，其中，所述中和电路包括多个薄膜晶体管，每一所述薄膜晶体管的栅极作为对应的所述控制端，每一所述薄膜晶体管的源极和漏极作为对应的两所述耦接端并电性连接于对应的两所述数据线。
  3. 根据权利要求2所述的显示模组，其中，与相邻的两所述薄膜晶体管电性连接的所述数据线不同。
  4. 根据权利要求2所述的显示模组，其中，每一所述薄膜晶体管的源极和漏极的中的一个电性连接于一个所述数据线，每一所述薄膜晶体管的所述源极和所述漏极的中的另一个通过对应的所述薄膜晶体管电性连接于另一个所述数据线。
  5. 根据权利要求4所述的显示模组，其中，多个所述薄膜晶体管的所述源极和所述漏极的中的另一个均接地。
  6. 根据权利要求2所述的显示模组，其中，同列的所述子像素的极性相同，相邻两列的所述子像素的极性相反，每一所述薄膜晶体管的所述源极和所述漏极分别连接于极性相反的相邻两列的所述子像素对应的两所述数据线。
  7. 根据权利要求2所述的显示模组，其中，还包括驱动芯片，多个所述数据线电性连接于所述驱动芯片，所述中和电路的多个所述薄膜晶体管的所述栅极通过至少一所述控制信号线电性连接于所述驱动芯片。
  8. 根据权利要求7所述的显示模组，其中，所述非显示区包括位于多个所 述扫描线相对两侧的第一区和第二区，多个所述数据线通过所述第一区电性连接于所述驱动芯片，所述中和电路的多个所述薄膜晶体管位于所述第二区内。
  9. 根据权利要求8所述的显示模组，其中，至少一所述控制信号线位于所述非显示区内，每一所述控制信号线包括位于所述第二区内且沿所述行方向延伸的第一段，自所述第一段的相对两端沿所述列方向朝向所述第一区延伸的两第二段，以及自两所述第二段的远离所述第一段的两端相向延伸出的两第三段，所述第一段电性连接于多个所述薄膜晶体管的所述栅极，两所述第三段电性连接于所述驱动芯片。
  10. 一种驱动方法，其中，应用于如权利要求1所述的显示模组，包括：
    比较第一功耗和第二功耗，其中，所述第一功耗为从当前行所述子像素对应的所述数据线上的第一电压充电至下一行所述子像素对应的所述数据线的第二电压的功耗，所述第二功耗为从当前行所述子像素对应的所述数据线上的第三电压充电至下一行所述子像素对应的所述数据线的所述第二电压的功耗，所述第三电压是通过对所述中和电路的至少一所述控制端加载有效电平，使得至少两所述耦接端导通以对当前行所述子像素对应的所述数据线上的所述第一电压进行中和之后而得到的；
    根据比较结果，以在当前行所述子像素被关闭之后且在下一行所述子像素被开启之前，发送控制信号至所述中和电路的至少一所述控制端以控制至少两所述耦接端的通断。
  11. 根据权利要求10所述的驱动方法，其中，所述第一功耗和所述第二功耗的计算公式为：A＝(X 1-x 1) 2+(X 2-x 2) 2+……+(X m-x m) 2，B＝(X 1-y 1) 2+(X 2-y 2) 2+……+(X m-y m) 2，其中，A指代所述第一功耗，B指代所述第二功耗，x 1、x 2……x m指代当前行所述子像素对应的所述数据线上的所述第一电压，y 1、y 2……y m指代当前行所述子像素对应的所述数据线上的所述第三电压，X 1、X 2……X m指代下一行所述子像素对应的所述数据线上的所述第二电压。
  12. 根据权利要求10所述的驱动方法，其中，当所述第一功耗大于所述第二功耗时，发送所述控制信号使得所述有效电平被加载至所述中和电路的至少一所述控制端，使得至少两所述耦接端连通。
  13. 根据权利要求10所述的驱动方法，其中，当所述第一功耗小于或等于所述第二功耗时，发送所述控制信号使得无效电平被加载至所述中和电路的至少一所述控制端，使得至少两所述耦接端断开。
  14. 一种显示装置，其中，包括显示模组，所述显示模组包括显示面板，所述显示面板包括显示区和围绕所述显示区至少一侧的非显示区，所述显示面板包括：
    多个数据线，沿列方向延伸，且至少部分位于所述显示区内；
    多个扫描线，沿行方向延伸，且至少部分位于所述显示区内，以与多个所述数据线围成多个子像素区域；以及
    多个子像素，位于多个所述子像素区域内，每一所述子像素电性连接于对应的所述扫描线以及对应的所述数据线；
    其中，所述显示模组还包括中和电路，所述中和电路包括至少一控制端和至少两耦接端，至少一所述控制端用于控制至少两所述耦接端之间的通断，至少两所述耦接端电性连接于至少两所述数据线。
  15. 根据权利要求14所述的显示装置，其中，所述中和电路包括多个薄膜晶体管，每一所述薄膜晶体管的栅极作为对应的所述控制端，每一所述薄膜晶体管的源极和漏极作为对应的两所述耦接端并电性连接于对应的两所述数据线。
  16. 根据权利要求15所述的显示装置，其中，与相邻的两所述薄膜晶体管电性连接的所述数据线不同。
  17. 根据权利要求15所述的显示装置，其中，每一所述薄膜晶体管的源极和漏极的中的一个电性连接于一个所述数据线；每一所述薄膜晶体管的所述源极和所述漏极的中的另一个通过对应的所述薄膜晶体管电性连接于另一个所述数据线，或，多个所述薄膜晶体管的所述源极和所述漏极的中的另一个均接地。
  18. 根据权利要求15所述的显示装置，其中，同列的所述子像素的极性相同，相邻两列的所述子像素的极性相反，每一所述薄膜晶体管的所述源极和所述漏极分别连接于极性相反的相邻两列的所述子像素对应的两所述数据线。
  19. 根据权利要求15所述的显示装置，其中，所述显示模组还包括驱动芯 片，多个所述数据线电性连接于所述驱动芯片，所述中和电路的多个所述薄膜晶体管的所述栅极通过至少一所述控制信号线电性连接于所述驱动芯片。
  20. 根据权利要求19所述的显示装置，其中，所述非显示区包括位于多个所述扫描线相对两侧的第一区和第二区，多个所述数据线通过所述第一区电性连接于所述驱动芯片，所述中和电路的多个所述薄膜晶体管位于所述第二区内。
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