WO2018153082A1 - 一种阵列基板及显示装置 - Google Patents

一种阵列基板及显示装置 Download PDF

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Publication number
WO2018153082A1
WO2018153082A1 PCT/CN2017/102952 CN2017102952W WO2018153082A1 WO 2018153082 A1 WO2018153082 A1 WO 2018153082A1 CN 2017102952 W CN2017102952 W CN 2017102952W WO 2018153082 A1 WO2018153082 A1 WO 2018153082A1
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WIPO (PCT)
Prior art keywords
array substrate
gate line
display device
gate
driving
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PCT/CN2017/102952
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English (en)
French (fr)
Inventor
储浩
石跃
陈传宝
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/776,455 priority Critical patent/US11126048B2/en
Publication of WO2018153082A1 publication Critical patent/WO2018153082A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate and a display device.
  • liquid crystal display technology is widely used in other display devices such as televisions and mobile phones, and people are paying more and more attention to the display effect of liquid crystal display devices.
  • the liquid crystal display device when the liquid crystal display device is driven, if the voltage at the driving start is higher than the voltage at the driving terminal, the display luminance of each pixel unit in the liquid crystal display device is uneven, and the display effect of the liquid crystal display device is poor.
  • the present disclosure has been made in order to provide an array substrate and corresponding display device that overcomes the above problems or at least partially solves the above problems.
  • an array substrate including a gate line formed on a substrate, a data line, and a pixel unit defined by an adjacent gate line and an adjacent data line, the gate line being driven from a driving end to a driving The terminal gradually widens.
  • the driving start ends of the adjacent two gate lines in the array substrate are opposite in direction.
  • the driving start ends of the adjacent two gate lines in the array substrate are the same.
  • the width of the driving terminal side of the gate line is the same as the original gate line width.
  • each of the pixel units is connected to one gate line and one data line.
  • the pixel unit includes a pixel electrode, a common electrode, and a thin film transistor.
  • the thin film transistor is located on the upper left or lower left side or the upper right side or the lower right side of the pixel unit.
  • a gate of the thin film transistor is connected to the gate line, a source of the thin film transistor is connected to the data line, and a drain of the thin film transistor is connected to the pixel electrode.
  • the gate lines are crossed and insulated from the data lines.
  • the material of the pixel electrode and the common electrode is indium tin oxide.
  • a display device including the above array base board.
  • the present disclosure has the following advantages:
  • the array substrate includes gate lines, data lines, and pixel cells defined by adjacent gate lines and adjacent data lines formed on the substrate, the gate lines being driven from the beginning Gradually widen to the drive terminal.
  • the width of the driving start end of the gate line in the array substrate is smaller than the width of the driving terminal, so that the impedance of the driving start end is greater than the impedance of the driving terminal, and the voltage difference between the driving start end and the driving terminal caused by the large RC delay of the driving terminal is reduced, thereby solving
  • the voltage at the beginning of the driving is higher than the voltage of the driving terminal, resulting in uneven display brightness of each pixel unit in the liquid crystal display device, and the display effect of the liquid crystal display device is poor.
  • the non-equal width gate line is used to improve each pixel in the liquid crystal display device.
  • the uniformity of the display brightness of the unit improves the quality and yield of the liquid crystal display device, and improves the display effect of the liquid crystal display device.
  • 1 is a schematic structural view of a conventional array substrate
  • FIG. 2 is a schematic structural view of an array substrate according to the present disclosure
  • FIG. 3 is a schematic view showing the structure of one pixel unit in an array substrate according to the present disclosure.
  • the array substrate includes each row of gate lines, each column of data lines, and pixel units defined by adjacent gate lines and adjacent data lines, and each row of gate lines drives the start end and the drive terminal.
  • the width is the same.
  • the row gate lines include: a gate line 11, a gate line 12, a gate line 13, a gate line 14, a gate line 15, a gate line 16, a gate line 17, and a gate line 18.
  • the data lines of the columns include: a data line 21
  • the data line 22, the data line 23, the data line 24, the data line 25, the data line 26, and the data line 27 are vertically crossed and insulated from each of the column lines, wherein the gate line 11 is surrounded by the data lines.
  • the occluded area is vertically intersected and insulated from each column of data lines, and the gate line 111, the gate line 112, the gate line 113, the gate line 114, the gate line 115, the gate line 116, and the area blocked by the data lines of each column All are part of the gate line 11, and the pixel unit 31 is composed of the gate line 11, the gate line 12 and the data line 21,
  • the data line 22 is defined such that the width d1 of the left side of the gate line 11 is the same as the width d2 of the right side, and the driving start end of the gate line 11 and the width of the driving terminal are the same.
  • the RC delay of the driving terminal is larger than the RC delay of the driving end, the RC delay.
  • the loss of the gate signal corresponding to the gate line is correspondingly increased, causing the voltage at the beginning of the drive to be higher than the voltage at the driving terminal, so that the display brightness of each pixel unit in the liquid crystal display device The display performance of the liquid crystal display device is poor.
  • the present disclosure provides the following array substrate and display device.
  • FIG. 2 a schematic structural view of an array substrate according to the present disclosure is shown.
  • An embodiment of the present disclosure provides an array substrate, including: a substrate, a gate line formed on the substrate, a data line, and a pixel unit defined by the adjacent gate line and the adjacent data line, wherein the width of the gate line driving start is smaller than The width of the drive terminal.
  • the gate line is gradually widened from the beginning of the drive to the drive terminal.
  • the array substrate includes a gate line 41 and a gate line 42, a data line 21 and a data line 22, and a pixel unit 32 defined by the adjacent gate line 41, the gate line 42 and the adjacent data line 21 and the data line 22.
  • the width d1 of the left side of the line 42 is larger than the width d2 of the right side, and the gate line 42 drives the pixel unit from the right to the left, and the width d2 of the start line of the gate line 42 is smaller than the width d1 of the driving terminal.
  • Area A represents a partial schematic view of one pixel unit in the array substrate.
  • a control chip is disposed on each of the left and right sides of the array substrate for providing a gate signal to each of the gate lines.
  • the gate signal is provided for the even-numbered row gate lines
  • the second control chip on the right side of the array substrate is used to supply the gate signals to the odd-numbered gate lines.
  • even rows The gate line drives the pixel unit from left to right, and the odd-numbered gate lines drive the pixel unit from right to left; or, for the first control chip on the left side of the array substrate, for providing gate signals to the odd-numbered gate lines, the array substrate is right
  • the second control chip on the side is used to provide gate signals to the even-numbered row gate lines.
  • the odd-numbered gate lines drive the pixel cells from left to right
  • the even-numbered gate lines drive the pixel cells from right to left.
  • the odd row gate line and the even row gate line respectively drive the pixel unit from both sides to facilitate connection between the control chip on both sides and the gate line.
  • the gate lines are arranged in a row in the array substrate.
  • the gate lines in the array substrate may be arranged in rows or Column arrangement; when the gate lines in the array substrate are arranged in a row, the data lines in the array substrate are arranged in columns, and when the gate lines in the array substrate are arranged in columns, the data lines in the array substrate are arranged in a row.
  • the embodiments of the present disclosure are not limited herein.
  • a control chip is disposed on the left or right side of the array substrate for providing a gate signal to each of the gate lines.
  • the driving start ends of the adjacent two gate lines in the array substrate have the same direction.
  • the present disclosure has the following advantages:
  • the array substrate of the embodiment of the present disclosure includes a gate line formed on the substrate, a data line, and a pixel unit defined by the adjacent gate line and the adjacent data line, the gate line being gradually widened from the driving start end to the driving terminal.
  • the width of the driving start end of the gate line in the array substrate is smaller than the width of the driving terminal, so that the impedance of the driving start end is greater than the impedance of the driving terminal, and the voltage difference between the driving start end and the driving terminal caused by the large RC delay of the driving terminal is reduced, thereby solving
  • the voltage at the beginning of the driving is higher than the voltage of the driving terminal, resulting in uneven display brightness of each pixel unit in the liquid crystal display device, and the display effect of the liquid crystal display device is poor.
  • the non-equal width gate line is used to improve each pixel in the liquid crystal display device.
  • the uniformity of the display brightness of the unit improves the quality and yield of the liquid crystal display device, and improves the display effect of the liquid crystal display device.
  • FIG. 3 a schematic structural view of one pixel unit in an array substrate according to the present disclosure is shown.
  • FIG. 3 is a partially enlarged schematic view of a region A in FIG. 2.
  • An embodiment of the present disclosure provides a pixel unit in an array substrate, wherein each pixel unit 32 is connected to a gate line 42 and a data line 22, and the gate line 42 and the data line 22 are intersected and insulated, and the gate line 42 is The driving start to the driving terminal is gradually widened, wherein the pixel unit 32 includes the pixel electrode 321, the common electrode 322, and the thin film transistor 323.
  • the thin film transistor 323 may be located on the upper left or lower left side or the upper right side or the lower right side of the pixel unit 32 to facilitate connection between the thin film transistor and the corresponding gate line and data line.
  • the embodiments of the present disclosure are not limited herein.
  • the gate of the thin film transistor is connected to the gate line, the source of the thin film transistor is connected to the data line, and the drain of the thin film transistor is connected to the pixel electrode.
  • the gate signal input through the gate line turns on the thin film transistor, and the pixel signal is charged by the data signal input through the data line, thereby finally realizing the screen display of the pixel unit in the liquid crystal display device.
  • the width of the driving terminal side of the gate line is the same as the width of the original gate line, and the original gate line width is the gate line width in the current array substrate, when the width of the driving terminal side of the gate line is the same as the original gate line width
  • the width of the driving start side of the gate line can be reduced without affecting the size of the pixel unit.
  • the material of the pixel electrode and the common electrode is indium tin oxide, and the indium tin oxide has good electrical conductivity and improves the electrical conductivity of the array substrate; the indium tin oxide can also be described as ITO (Indium tin oxide).
  • the pixel electrode is located on the rear glass substrate of the array substrate, and the common electrode is located on the front glass substrate of the array substrate, and the liquid crystal is filled between the front glass substrate and the rear glass substrate.
  • the thin film transistor is turned on by the gate signal in the gate line, the data signal in the data line conducts the data signal to the drain of the thin film transistor through the source of the thin film transistor, and the drain of the thin film transistor is connected to the pixel electrode of the pixel unit
  • the data signal outputted from the drain of the thin film transistor supplies a voltage to the pixel electrode of the pixel unit, and an electric field is generated between the pixel electrode and the common electrode, and the liquid crystal between the pixel electrode and the common electrode is controlled to be sequentially arranged to realize the liquid crystal display device.
  • the display of the pixel unit is controlled to be sequentially arranged to realize the liquid crystal display device.
  • the voltage of the pixel electrode is related to the gate signal and the data signal.
  • the voltage of the pixel electrode is proportional to the magnitude of the gate signal.
  • the gate signal is larger, the degree of opening of the thin film transistor is greater.
  • the difference of the gate signals corresponding to the respective pixel units is smaller, the display brightness of each pixel unit is closer, and the display brightness of each pixel unit in the liquid crystal display device is more uniform.
  • the display brightness of each pixel unit in the liquid crystal display device is more uniform.
  • the present disclosure has the following advantages:
  • each pixel unit in the array substrate of the embodiment of the present disclosure is connected to one gate line and one data line, and the gate line is gradually widened from the driving start end to the driving terminal.
  • the width of the driving start end of the gate line in the array substrate is smaller than the width of the driving terminal, so that the impedance of the driving start end is greater than the impedance of the driving terminal, and the voltage difference between the driving start end and the driving terminal caused by the large RC delay of the driving terminal is reduced, thereby solving
  • the voltage at the beginning of the driving is higher than the voltage of the driving terminal, resulting in uneven display brightness of each pixel unit in the liquid crystal display device, and the display effect of the liquid crystal display device is poor.
  • the non-equal width gate line is used to improve each pixel in the liquid crystal display device.
  • the uniformity of the display brightness of the unit improves the quality and yield of the liquid crystal display device, and improves the display effect of the liquid crystal display device.
  • Embodiments of the present disclosure provide a display device including the above array substrate.
  • the array substrate includes a gate line formed on the substrate, a data line, and a pixel unit defined by the adjacent gate line and the adjacent data line, the gate line being gradually widened from the driving start end to the driving terminal.
  • the driving start ends of the adjacent two gate lines in the array substrate are opposite or the same, and the width of the driving terminal side of the gate lines is the same as the original gate line width.
  • Each pixel unit is connected with a gate line and a data line.
  • the gate line and the data line are crossed and insulated, and the gate line is gradually widened from a driving start end to a driving terminal.
  • the pixel unit includes a pixel electrode, a common electrode and a thin film transistor.
  • the gate of the thin film transistor is connected to the gate line, the source of the thin film transistor is connected to the data line, the drain of the thin film transistor is connected to the pixel electrode, and the thin film transistor is located on the upper left or lower left side or the upper right side or the lower right side of the pixel unit.
  • the material of the pixel electrode and the common electrode is indium tin oxide.
  • the control chip separates the corresponding row driving signal and the column driving signal according to the data input by the motherboard circuit and the clock signal, and outputs to the corresponding gate line according to the row and column arrangement of the gate line and the data line in the array substrate.
  • the data line providing the gate signal and the data signal for the gate line and the data line, turning on the thin film transistor through the gate signal in the gate line, charging the pixel electrode through the data signal of the data line, and making the pixel electrode An electric field is generated between the common electrodes, and the liquid crystal between the pixel electrode and the common electrode is controlled to be sequentially arranged to realize display of the pixel unit in the liquid crystal display device.
  • the display device may be any product or component having a display function, such as a liquid crystal panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a navigator, and the like.
  • a display function such as a liquid crystal panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a navigator, and the like.
  • the present disclosure has the following advantages:
  • a display device includes an array substrate, and a gate line in the array substrate is gradually widened from a driving start end to a driving terminal.
  • the width of the driving start end of the gate line in the array substrate is smaller than the width of the driving terminal, so that the impedance of the driving end is greater than the impedance of the driving terminal, and the driving start end caused by the large RC delay of the driving terminal is reduced.
  • the voltage difference from the driving terminal is solved, thereby solving the problem that the voltage at the driving end is higher than the voltage of the driving terminal, resulting in uneven display brightness of each pixel unit in the liquid crystal display device, and the display effect of the liquid crystal display device is poor, and the non-equal width is adopted.
  • the gate line improves the uniformity of the display brightness of each pixel unit in the liquid crystal display device, improves the quality and yield of the liquid crystal display device, and improves the display effect of the liquid crystal display device.

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Abstract

一种阵列基板及显示装置，涉及显示技术领域。阵列基板包括形成在基板上的栅线（41,42）、数据线（21,22）以及由相邻栅线（41,42）和相邻数据线（21,22）限定的像素单元（32），栅线（41,42）从驱动始端到驱动终端渐进变宽。阵列基板中栅线的驱动始端的宽度（d2）小于驱动终端的宽度（d1），导致驱动始端的阻抗大于驱动终端的阻抗，减小驱动终端的RC delay较大造成的驱动始端与驱动终端的电压差，由此解决了驱动始端的电压高于驱动终端的电压，导致液晶显示装置中各个像素单元的显示亮度不均，液晶显示装置的显示效果差的问题，采用非等宽栅线，提高液晶显示装置中各个像素单元的显示亮度的均一性，提升液晶显示装置的品质与良率，提高液晶显示装置的显示效果。

Description

一种阵列基板及显示装置
交叉引用
本申请要求于2017年2月22日提交的申请号为201710096076.2、名称为“一种阵列基板及显示装置”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，特别是涉及一种阵列基板及显示装置。
背景技术
随着显示技术的不断发展，液晶显示技术广泛应用于电视、手机等其他显示装置中，人们也越来越重视液晶显示装置的显示效果。
但是在驱动液晶显示装置时，如果驱动始端的电压高于驱动终端的电压，会使液晶显示装置中各个像素单元的显示亮度不均，液晶显示装置的显示效果差。
发明内容
鉴于上述问题，提出了本公开以便提供一种克服上述问题或者至少部分地解决上述问题的一种阵列基板及相应的显示装置。
依据本公开的一个方面，提供了一种阵列基板，包括形成在基板上的栅线、数据线以及由相邻栅线和相邻数据线限定的像素单元，所述栅线从驱动始端到驱动终端渐进变宽。
在一个实施方式中，所述阵列基板中相邻两条栅线的驱动始端的方向相反。
在一个实施方式中，所述阵列基板中相邻两条栅线的驱动始端的方向相同。
在一个实施方式中，所述栅线的驱动终端侧的宽度与原始栅线宽度相同。
在一个实施方式中，所述每个像素单元连接一条栅线和一条数据线。
在一个实施方式中，所述像素单元包括像素电极、公共电极和薄膜晶体管。
在一个实施方式中，所述薄膜晶体管位于所述像素单元的左上侧或左下侧或右上侧或右下侧。
在一个实施方式中，所述薄膜晶体管的栅极与所述栅线连接，所述薄膜晶体管的源极与所述数据线连接，所述薄膜晶体管的漏极与所述像素电极连接。
在一个实施方式中，所述栅线与所述数据线之间交叉且绝缘。
在一个实施方式中，所述像素电极和所述公共电极的材料为氧化铟锡。
根据本公开的另一方面，提供了一种显示装置，所述显示装置包括上述的阵列基 板。
相对在先技术，本公开具备如下优点：
根据本公开的一种阵列基板及显示装置，所述阵列基板包括形成在基板上的栅线、数据线以及由相邻栅线和相邻数据线限定的像素单元，所述栅线从驱动始端到驱动终端渐进变宽。阵列基板中栅线的驱动始端的宽度小于驱动终端的宽度，导致驱动始端的阻抗大于驱动终端的阻抗，减小驱动终端的RC delay较大造成的驱动始端与驱动终端的电压差，由此解决了驱动始端的电压高于驱动终端的电压，导致液晶显示装置中各个像素单元的显示亮度不均，液晶显示装置的显示效果差的问题，采用非等宽栅线，提高液晶显示装置中各个像素单元的显示亮度的均一性，提升液晶显示装置的品质与良率，提高液晶显示装置的显示效果。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图说明
通过阅读下文优选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的，而并不认为是对本公开的限制。而且在整个附图中，用相同的参考符号表示相同的部件。在附图中：
图1示出了现有的一种阵列基板的结构示意图；
图2示出了根据本公开的一种阵列基板的结构示意图；
图3示出了根据本公开的一种阵列基板中一个像素单元的结构示意图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施例。虽然附图中显示了本公开的示例性实施例，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
目前，在液晶显示装置中，参照图1所示，阵列基板包括各行栅线、各列数据线以及由相邻栅线和相邻数据线限定的像素单元，各行栅线驱动始端与驱动终端的宽度相同。所述各行栅线包括：栅线11、栅线12、栅线13、栅线14、栅线15、栅线16、栅线17和栅线18，所述各列数据线包括：数据线21、数据线22、数据线23、数据线24、数据线25、数据线26和数据线27，各行栅线与各列数据线之间垂直交叉且绝缘，其中，栅线11被各列数据线遮挡住的区域与各列数据线之间垂直交叉且绝缘，栅线111、栅线112、栅线113、栅线114、栅线115、栅线116，以及被各列数据线遮挡住的区域均为栅线11的一部分，像素单元31由栅线11、栅线12与数据线21、 数据线22限定，栅线11左侧的宽度d1与右侧的宽度d2相同，则栅线11的驱动始端和驱动终端的宽度相同。
在发明人应用在先技术时，发现在先技术对于阵列基板采用等宽栅线实现液晶显示装置的像素单元的驱动时，由于驱动终端的RC delay比驱动始端的RC delay大，所述RC delay也可称为gate delay(栅极延迟)，导致栅线对应的栅极信号的损失会相应增大，造成驱动始端的电压高于驱动终端的电压，使液晶显示装置中各个像素单元的显示亮度不均，液晶显示装置的显示效果差。
为解决在先技术中的问题，本公开提供了以下的阵列基板和显示装置。
实施例一
参照图2，示出了根据本公开的一种阵列基板的结构示意图。
本公开实施例提供了一种阵列基板，包括：基板，形成在基板上的栅线、数据线以及由相邻栅线和相邻数据线限定的像素单元，所述栅线驱动始端的宽度小于驱动终端的宽度。在一种实施方式中，所述栅线从驱动始端到驱动终端渐进变宽。
其中，所述阵列基板包括栅线41和栅线42，数据线21和数据线22，由相邻栅线41、栅线42和相邻数据线21、数据线22限定的像素单元32，栅线42左侧的宽度d1大于右侧的宽度d2，且栅线42从右向左驱动像素单元，则栅线42驱动始端的宽度d2小于驱动终端的宽度d1。区域A表示阵列基板中一个像素单元的局部示意图。
本公开的一种实施例中，在阵列基板的左右两侧分别布置一个控制芯片，用于给每条栅线提供栅极信号。对于阵列基板左侧的第一控制芯片，用于给偶数行栅线提供栅极信号，阵列基板右侧的第二控制芯片，用于给奇数行栅线提供栅极信号，此时，偶数行栅线从左向右驱动像素单元，奇数行栅线从右向左驱动像素单元；或者，对于阵列基板左侧的第一控制芯片，用于给奇数行栅线提供栅极信号，阵列基板右侧的第二控制芯片，用于给偶数行栅线提供栅极信号，此时，奇数行栅线从左向右驱动像素单元，偶数行栅线从右向左驱动像素单元。本公开实施例在此不做限制。
奇数行栅线和偶数行栅线分别从两侧驱动像素单元，方便两侧的控制芯片与栅线之间进行连接。
所述阵列基板中相邻两条栅线的驱动始端的方向相反，目前在阵列基板中栅线为行布置，在本公开实施例中，阵列基板中的栅线可以为行布置，也可以为列布置；当阵列基板中的栅线为行布置时，阵列基板中的数据线为列布置，当阵列基板中的栅线为列布置时，阵列基板中的数据线为行布置。本公开实施例在此不做限制。
本公开的另一种实施例中，在阵列基板的左侧或右侧布置一个控制芯片，用于给每条栅线提供栅极信号。此时，阵列基板中相邻两条栅线的驱动始端的方向相同。当控制芯片位于阵列基板的左侧时，驱动始端位于栅线的左侧，当控制芯片位于阵列基板的右侧时，驱动始端位于栅线的右侧。
相对在先技术，本公开具备如下优点：
本公开实施例的阵列基板包括形成在基板上的栅线、数据线以及由相邻栅线和相邻数据线限定的像素单元，所述栅线从驱动始端到驱动终端渐进变宽。阵列基板中栅线的驱动始端的宽度小于驱动终端的宽度，导致驱动始端的阻抗大于驱动终端的阻抗，减小驱动终端的RC delay较大造成的驱动始端与驱动终端的电压差，由此解决了驱动始端的电压高于驱动终端的电压，导致液晶显示装置中各个像素单元的显示亮度不均，液晶显示装置的显示效果差的问题，采用非等宽栅线，提高液晶显示装置中各个像素单元的显示亮度的均一性，提升液晶显示装置的品质与良率，提高液晶显示装置的显示效果。
实施例二
参照图3，示出了根据本公开的一种阵列基板中一个像素单元的结构示意图。
其中，图3是图2中区域A的局部放大示意图。
本公开实施例提供了一种阵列基板中一个像素单元，所述每个像素单元32连接一条栅线42和一条数据线22，栅线42与数据线22之间交叉且绝缘，栅线42从驱动始端到驱动终端渐进变宽，其中，像素单元32包括像素电极321、公共电极322和薄膜晶体管323。
本公开的实施例中，薄膜晶体管323可以位于像素单元32的左上侧或左下侧或右上侧或右下侧，方便薄膜晶体管与对应的栅线和数据线之间的连接。本公开实施例在此不做限制。
薄膜晶体管的栅极与栅线连接，薄膜晶体管的源极与数据线连接，薄膜晶体管的漏极与像素电极连接。通过栅线输入的栅极信号使薄膜晶体管导通，通过数据线输入的数据信号对像素电极进行充电，最终实现液晶显示装置中像素单元的画面显示。
栅线的驱动终端侧的宽度与原始栅线宽度相同，所述原始栅线宽度为目前现有的阵列基板中的栅线宽度，当栅线的驱动终端侧的宽度与原始栅线宽度相同时，可以实现栅线的驱动始端侧的宽度减小，而不影响像素单元的大小。
像素电极和公共电极的材料为氧化铟锡，氧化铟锡具有良好的导电性能，提高阵列基板的导电性能；所述氧化铟锡也可描述为ITO(Indium tin oxide，氧化铟锡)。
在本公开的实施例中，像素电极位于阵列基板的后玻璃基板上，公共电极位于阵列基板的前玻璃基板上，在前玻璃基板和后玻璃基板之间填充液晶。通过栅线中的栅极信号使薄膜晶体管导通，数据线中的数据信号通过薄膜晶体管的源极将数据信号导通至薄膜晶体管的漏极，薄膜晶体管的漏极与像素单元的像素电极连接，通过薄膜晶体管的漏极输出的数据信号给像素单元的像素电极提供电压，则像素电极与公共电极之间产生电场，控制像素电极与公共电极之间的液晶进行有序排列，实现液晶显示装置中像素单元的显示。
像素电极的电压跟栅极信号和数据信号相关，当数据信号相同时，像素电极的电压跟栅极信号的大小成正比关系。当栅极信号越大时，薄膜晶体管的打开程度越大， 则像素电极的电压越大，对应的像素单元的显示亮度越高；当栅极信号越小时，薄膜晶体管的打开程度越小，则像素电极的电压越小，对应的像素单元的显示亮度越低。当各个像素单元对应的栅极信号的差值越小时，各个像素单元的显示亮度越接近，液晶显示装置中各个像素单元的显示亮度更均一。在一个实施方式中，当各个像素单元对应的栅极信号的大小一致时，液晶显示装置中各个像素单元的显示亮度更一致。
相对在先技术，本公开具备如下优点：
本公开实施例的阵列基板中的像素单元，每个像素单元连接一条栅线和一条数据线，栅线从驱动始端到驱动终端渐进变宽。阵列基板中栅线的驱动始端的宽度小于驱动终端的宽度，导致驱动始端的阻抗大于驱动终端的阻抗，减小驱动终端的RC delay较大造成的驱动始端与驱动终端的电压差，由此解决了驱动始端的电压高于驱动终端的电压，导致液晶显示装置中各个像素单元的显示亮度不均，液晶显示装置的显示效果差的问题，采用非等宽栅线，提高液晶显示装置中各个像素单元的显示亮度的均一性，提升液晶显示装置的品质与良率，提高液晶显示装置的显示效果。
实施例三
本公开实施例提供了一种显示装置，所述显示装置包括上述的阵列基板。
所述阵列基板，包括形成在基板上的栅线、数据线以及由相邻栅线和相邻数据线限定的像素单元，所述栅线从驱动始端到驱动终端渐进变宽。阵列基板中相邻两条栅线的驱动始端的方向相反或相同，栅线的驱动终端侧的宽度与原始栅线宽度相同。
每个像素单元连接一条栅线和一条数据线，栅线与数据线之间交叉且绝缘，栅线从驱动始端到驱动终端渐进变宽，其中，像素单元包括像素电极、公共电极和薄膜晶体管。薄膜晶体管的栅极与栅线连接，薄膜晶体管的源极与数据线连接，薄膜晶体管的漏极与像素电极连接；薄膜晶体管位于像素单元的左上侧或左下侧或右上侧或右下侧。像素电极和公共电极的材料为氧化铟锡。
本公开实施例中，控制芯片根据主板电路输入的数据和时钟信号，分离出相应的行驱动信号和列驱动信号，根据阵列基板中栅线和数据线的行列布置，分别输出到相应的栅线和数据线，为栅线和数据线提供相应的栅极信号和数据信号，通过栅线中的栅极信号使薄膜晶体管导通，通过数据线的数据信号对像素电极进行充电，使像素电极与公共电极之间产生电场，控制像素电极与公共电极之间的液晶进行有序排列，实现液晶显示装置中像素单元的显示。
所述显示装置可以为：液晶面板、手机、平板电脑、电视机、显示器、笔记本电脑、导航仪等任何具有显示功能的产品或部件。
相对在先技术，本公开具备如下优点：
本公开实施例的显示装置，包括阵列基板，所述阵列基板中的栅线从驱动始端到驱动终端渐进变宽。阵列基板中栅线的驱动始端的宽度小于驱动终端的宽度，导致驱动始端的阻抗大于驱动终端的阻抗，减小驱动终端的RC delay较大造成的驱动始端 与驱动终端的电压差，由此解决了驱动始端的电压高于驱动终端的电压，导致液晶显示装置中各个像素单元的显示亮度不均，液晶显示装置的显示效果差的问题，采用非等宽栅线，提高液晶显示装置中各个像素单元的显示亮度的均一性，提升液晶显示装置的品质与良率，提高液晶显示装置的显示效果。
在此提供的算法和显示不与任何特定计算机、虚拟系统或者其它设备固有相关。各种通用系统也可以与基于在此的示教一起使用。根据上面的描述，构造这类系统所要求的结构是显而易见的。此外，本公开也不针对任何特定编程语言。应当明白，可以利用各种编程语言实现在此描述的本公开的内容，并且上面对特定语言所做的描述是为了披露本公开的最佳实施方式。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本公开的实施例可以在没有这些具体细节的情况下实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
类似地，应当理解，为了精简本公开并帮助理解各个发明方面中的一个或多个，在上面对本公开的示例性实施例的描述中，本公开的各个特征有时被一起分组到单个实施例、图、或者对其的描述中。然而，并不应将该公开的方法解释成反映如下意图：即所要求保护的本公开要求比在每个权利要求中所明确记载的特征更多的特征。更确切地说，如下面的权利要求书所反映的那样，发明方面在于少于前面公开的单个实施例的所有特征。因此，遵循具体实施方式的权利要求书由此明确地并入该具体实施方式，其中每个权利要求本身都作为本公开的单独实施例。
以上详细描述了本公开的优选实施方式，但是，本公开并不限于上述实施方式中的具体细节，在本公开的技术构思范围内，可以对本公开的技术方案进行多种简单变型，这些简单变型均属于本公开的保护范围。另外需要说明的是，在上述具体实施方式中所描述的各个具体技术特征，在不矛盾的情况下，可以通过任何合适的方式进行组合，为了避免不必要的重复，本公开对各种可能的组合方式不再另行说明。此外，本公开的各种不同的实施方式之间也可以进行任意组合，只要其不违背本公开的思想，其同样应当视为本公开所公开的内容。
此外，本领域的技术人员能够理解，尽管在此所述的一些实施例包括其它实施例中所包括的某些特征而不是其它特征，但是不同实施例的特征的组合意味着处于本公开的范围之内并且形成不同的实施例。例如，在下面的权利要求书中，所要求保护的实施例的任意之一都可以以任意的组合方式来使用。
应该注意的是上述实施例对本公开进行说明而不是对本公开进行限制，并且本领域技术人员在不脱离所附权利要求的范围的情况下可设计出替换实施例。在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本公开可以借助于包括有若干不同元件的硬件以及借助于 适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。

Claims (11)

  1. 一种阵列基板，包括基板，形成在所述基板上的栅线、数据线以及由相邻栅线和相邻数据线限定的像素单元，所述栅线的驱动始端的宽度小于驱动终端的宽度。
  2. 根据权利要求1所述的阵列基板，其中，所述栅线从驱动始端到驱动终端渐进变宽。
  3. 根据权利要求1所述的阵列基板，其中，所述阵列基板中相邻两条栅线的驱动始端的方向相反。
  4. 根据权利要求1所述的阵列基板，其中，所述阵列基板中相邻两条栅线的驱动始端的方向相同。
  5. 根据权利要求1所述的阵列基板，其中，所述每个像素单元连接一条栅线和一条数据线。
  6. 根据权利要求1所述的阵列基板，其中，所述像素单元包括像素电极、公共电极和薄膜晶体管。
  7. 根据权利要求6所述的阵列基板，其中，所述薄膜晶体管位于所述像素单元的左上侧或左下侧或右上侧或右下侧。
  8. 根据权利要求7所述的阵列基板，其中，所述薄膜晶体管的栅极与所述栅线连接，所述薄膜晶体管的源极与所述数据线连接，所述薄膜晶体管的漏极与所述像素电极连接。
  9. 根据权利要求8所述的阵列基板，其中，所述栅线与所述数据线之间交叉且绝缘。
  10. 根据权利要求6所述的阵列基板，其中，所述像素电极和所述公共电极的材料为氧化铟锡。
  11. 一种显示装置，所述显示装置包括如权利要求1-10任一项所述的阵列基板。
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