WO2023233910A1 - 半導体装置、その用途、およびその製造方法 - Google Patents

半導体装置、その用途、およびその製造方法 Download PDF

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WO2023233910A1
WO2023233910A1 PCT/JP2023/017094 JP2023017094W WO2023233910A1 WO 2023233910 A1 WO2023233910 A1 WO 2023233910A1 JP 2023017094 W JP2023017094 W JP 2023017094W WO 2023233910 A1 WO2023233910 A1 WO 2023233910A1
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crystal
substrate
semiconductor device
plane
semiconductor
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French (fr)
Japanese (ja)
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孝仁 大島
祐一 大島
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National Institute for Materials Science
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National Institute for Materials Science
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C—CHEMISTRY; METALLURGY
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    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/04—Pattern deposit, e.g. by using masks
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C30B25/20—Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/16—Oxides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/01—Manufacture or treatment
    • H10D48/021—Manufacture or treatment of two-electrode devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials

Definitions

  • the present invention relates to a semiconductor device, its uses (particularly a power device having the semiconductor device), and a manufacturing method thereof.
  • this structure is currently formed by processing using anisotropic dry etching (generally also referred to as "reactive ion etching").
  • anisotropic dry etching generally also referred to as "reactive ion etching”
  • dry etching mainly anisotropic dry etching
  • trenches (concave) and fins (convex) in semiconductor devices using ⁇ -Ga 2 O 3 crystals and power devices that include such semiconductor devices.
  • the side wall surfaces (also simply referred to as “side surfaces” in this application) of the formed trenches (concave) and fins (convex) are subject to processing damage. Therefore, after dry etching, it is necessary to remove damage by a wet process using an alkali or acid.
  • the sidewall surface (side surface) formed by dry etching does not reflect the facets of the crystal, and therefore has a high density of dangling bonds. This leads to an increase in the density of crystal surface states and junction interface states, which deteriorates device characteristics.
  • processing by dry etching it is difficult to create narrow and deep trenches that are desirable for device applications, or completely vertical sidewall surfaces (side surfaces). Such a limited processing shape becomes a constraint on device design.
  • the present invention relates to a semiconductor device including a ⁇ -Ga 2 O 3 crystal having the conventional trench or fin structure (specifically, a trench (concave) or a fin (concave) formed by using the conventional dry etching described above).
  • a semiconductor device including a ⁇ -Ga 2 O 3 crystal having the conventional trench or fin structure (specifically, a trench (concave) or a fin (concave) formed by using the conventional dry etching described above).
  • An object of the present invention is to provide a power device that takes advantage of the characteristics of an O 3 crystal semiconductor, and a method for manufacturing the semiconductor device.
  • (Configuration 1) It has a semiconductor layer made of ⁇ -Ga 2 O 3 crystal, The semiconductor layer has a three-dimensional structure of linear protrusions or grooves on the first main surface, A semiconductor device, wherein a side surface of the three-dimensional structure is a (100) facet surface.
  • Configuration 2 The semiconductor device according to Configuration 1, wherein the side surface is perpendicular to a substrate surface of the semiconductor device.
  • (Configuration 3) A semiconductor layer having a three-dimensional structure consisting of linear protrusions or grooves formed on a substrate, The semiconductor layer is made of ⁇ -Ga 2 O 3 crystal, In the semiconductor device, the longitudinal direction of the linear protrusion or groove is parallel to a line of intersection between a substrate surface of the substrate and a (100) plane.
  • (Configuration 4) The semiconductor device according to configuration 3, wherein a side surface of the linear protrusion or groove is perpendicular to the substrate surface.
  • (Configuration 5) 5 The semiconductor device according to configuration 3 or 4, wherein the substrate surface is a (010) plane, and the longitudinal direction is a [001] direction.
  • the shape of the three-dimensional structure is a groove
  • An anode electrode is formed to cover at least a portion of the three-dimensional structure via an insulating film disposed on at least a portion of the side surfaces and a bottom surface of the groove, 8.
  • a power device comprising the semiconductor device according to any one of Structures 1 to 10.
  • (Configuration 12) preparing a semiconductor substrate made of ⁇ -Ga 2 O 3 crystal; forming a linear or striped masking pattern with a longitudinal direction parallel to a line of intersection between the substrate surface of the semiconductor substrate and the (100) plane; A method for manufacturing a semiconductor device, comprising selectively growing a ⁇ -Ga 2 O 3 crystal in an opening of the masking pattern where the ⁇ -Ga 2 O 3 crystal is exposed by a deposition method using a vapor phase. (Configuration 13) 13. The method of manufacturing a semiconductor device according to configuration 12, wherein the deposition method is a vapor phase growth method.
  • the ⁇ -Ga 2 O 3 crystal has little processing damage, suppresses the generation of interface states on the crystal surface and the bonding interface, provides good device characteristics, and is suitable for microfabrication.
  • a semiconductor device having a trench (concave) or fin (convex) structure using ⁇ -Ga 2 O 3 crystalline semiconductor as a semiconductor material, particularly a power device that takes advantage of the characteristics of ⁇ -Ga 2 O 3 crystal semiconductor, and a method for manufacturing the same are provided.
  • FIG. 2 is a cross-sectional view illustrating a fin structure (trench structure) using ⁇ -Ga 2 O 3 crystal according to the present invention.
  • FIG. 3 is a cross-sectional process diagram showing the manufacturing process of a fin structure using ⁇ -Ga 2 O 3 crystal of the present invention. (a) to (f) in the figure show each manufacturing process in the manufacturing process.
  • FIG. 3 is a cross-sectional view showing a manufacturing process of a fin structure according to a conventional manufacturing method. (a) to (e) in the figure show each manufacturing step in the manufacturing process.
  • FIG. 3 is a flowchart showing the manufacturing process of a fin structure using ⁇ -Ga 2 O 3 crystal of the present invention.
  • FIG. 3 is a cross-sectional view showing the manufacturing process of the trench MOSSBD according to the present invention.
  • (a) to (e) in the figure show each manufacturing step in the manufacturing process.
  • FIG. 3 is a cross-sectional view showing the manufacturing process of the trench MOSSBD according to the present invention.
  • (a) to (d) in the figure show each manufacturing step in the manufacturing process.
  • FIG. 2 is an explanatory diagram of a horizontal FinFET element structure.
  • (a) in the figure is a bird's-eye view
  • (b) in the figure is a cross-sectional view.
  • FIG. 2 is a cross-sectional view illustrating the element structure of a vertical FinFET.
  • (a) in the figure is a SEM photo when HCl is added, and (b) in the figure is a SEM photo when it is not added.
  • (a) in the figure is an SEM photo using a substrate with the (001) plane as the substrate surface
  • (b) in the figure is an SEM photo when using the substrate with the (010) plane as the substrate surface. be.
  • FIG. 2 is a schematic cross-sectional view illustrating the shape of a fin made of ⁇ -Ga 2 O 3 crystal produced by a vapor phase growth method.
  • FIG. 1 is a diagram (device configuration explanatory diagram) showing an outline of the configuration of a vapor phase growth apparatus (HVPE apparatus) described in Embodiment 1.
  • FIG. This is an SEM photograph of a fin made of ⁇ -Ga 2 O 3 crystal produced by vapor phase growth using a substrate with the (-102) plane as the substrate surface.
  • (a), (b), and (c) in the figure are SEM photographs of fins made of ⁇ -Ga 2 O 3 crystals produced by vapor phase epitaxy using a substrate with the (-102) plane as the substrate surface. It is. (a) in the figure is an SEM photograph of a cross section of a fin made of ⁇ -Ga 2 O 3 crystal produced by vapor phase epitaxy using a substrate with the (-102) plane as the substrate surface; (b) is a schematic diagram of the cross-sectional shape traced based on the photograph.
  • the orientation of the linear opening is set so that the (100) plane, which has the smallest surface energy and is stable, becomes the side wall surface (side surface) of the trench or fin.
  • a "fin” (sometimes written as “fin (convex)" refers to a crystal with a linear shape surrounded by facets, unless otherwise specified, and a convex shape (three-dimensional structure), and is also simply referred to as a "linear projection" in this application.
  • a “trench” (sometimes referred to as a “trench (concave)”) refers to the presence of two or more linear crystals (fins) surrounded by facets, unless otherwise specified. This refers to a gap that appears between adjacent fins when the fins are closed, has a concave shape (three-dimensional structure), and is also simply referred to as a "groove” in this application.
  • “linear protrusions or grooves” are as described below.
  • the three-dimensional structure of the semiconductor layer made of ⁇ -Ga 2 O 3 crystal has a structure formed by linear protrusions ("fins").
  • the semiconductor layer will be composed of linear protrusions (fins), so it will have a three-dimensional structure made of linear protrusions (i.e., a convex shape). is considered to have the following.
  • grooves appear between adjacent linear protrusions ("fins") (gaps), so if we pay attention to the grooves (trenches), we can see that the semiconductor layer is composed of grooves (trenches). It turns out.
  • the semiconductor layer is considered to have a three-dimensional structure consisting of grooves (ie, a concave shape).
  • the semiconductor layer having the three-dimensional structure of the linear protrusions that is, the convex shape
  • the semiconductor layer having the three-dimensional structure of the grooves that is, the concave shape
  • linear protrusions or grooves refers to the three-dimensional structure of the semiconductor layer made of ⁇ -Ga 2 O 3 crystals, focusing on linear protrusions ("fins") and considering them to consist only of linear protrusions. It also means a case where the gap between adjacent linear protrusions is regarded as a groove, and the groove is focused on and considered to consist only of grooves.
  • the surface having the semiconductor layer made of ⁇ -Ga 2 O 3 crystal is also referred to as the "first main surface".
  • the surface only needs to have a semiconductor layer made of ⁇ -Ga 2 O 3 crystal, and may be, for example, the surface of the substrate or the surface of a layer formed on the substrate.
  • the term "semiconductor device” means what is defined as a semiconductor device in the configuration of the present invention shown above. Specifically, it is a semiconductor device (semiconductor element) manufactured using a semiconductor as a material, and examples of generally well-known semiconductor devices (semiconductor elements) include semiconductor diodes, transistors, ICs, and LSIs. Can be mentioned.
  • the term "power device” means what is defined as a power device in the configuration of the present invention shown above.
  • semiconductor elements used in power converters such as inverters and converters can be mentioned.
  • semiconductor circuits are characterized by a large current flowing within the semiconductor circuit.
  • the sidewall surfaces (side surfaces) of trenches (concave) and fins (convex) produced by crystal growth using this method are formed of the most stable (100) facets, so there are few dangling bonds and the surface state is low. The density is also small.
  • the trench and fin sidewall surfaces which are formed with the most stable (100) facets and have few dangling bonds and a low surface state density
  • the trench and fin sidewall surfaces which are formed with the most stable (100) facets and have few dangling bonds and a low surface state density
  • a trench (concave) with a narrow width and a large depth and a substrate surface with an appropriately controlled off-angle it is easy to create a completely vertical side wall surface (side surface), making it an ideal device. Design becomes possible.
  • the semiconductor device 101 of the first embodiment has ⁇ -Ga 2 O 3 crystal formed on the substrate exposed surface of the opening 13 of the mask 12 formed on the substrate 11 made of ⁇ -Ga 2 O 3 crystal. It has a semiconductor layer 14 made of 2 O 3 crystal. That is, the semiconductor layer 14 has a three-dimensional structure of linear protrusions or grooves on the first main surface, and the side surfaces of the three-dimensional structure are (100) facets.
  • the first main surface is the surface of the substrate 11 that is used for forming the semiconductor layer 14 according to FIG. 1
  • the groove is the surface that is used for forming the semiconductor layer 14.
  • a linear protrusion is a concave three-dimensional structure formed as a gap between the fins 14 made of ⁇ -Ga 2 O 3 crystals.
  • a linear protrusion is a concave three-dimensional structure formed as a gap between the fins 14 made of ⁇ -Ga 2 O 3 crystals.
  • This is a convex three-dimensional structure (that is, the fin 14).
  • the side wall surface (side surface) of the groove is also the side wall surface (side surface) of the linear protrusion.
  • the semiconductor device 101 of the first embodiment includes the semiconductor layer 14 having a three-dimensional structure consisting of linear protrusions or grooves formed on the substrate 11 made of ⁇ -Ga 2 O 3 crystal, and the semiconductor layer 14 has a ⁇ -Ga 2 O 3 crystal.
  • the linear protrusion or groove is made of -Ga 2 O 3 crystal, and the longitudinal direction of the linear protrusion or groove is parallel to the line of intersection between the substrate surface and the (100) plane of the substrate.
  • the substrate surface of the substrate 11 is a (010) plane and the longitudinal direction is the [001] direction, or alternatively, the substrate surface of the substrate 11 is a (001) plane and the longitudinal direction is the [010] direction. It is preferable that
  • the (100) plane which has the lowest surface energy and is stable, becomes the side surface of the three-dimensional structure, that is, the side surface of the fin or trench.
  • the side surfaces of the semiconductor layer 14 made of ⁇ -Ga 2 O 3 crystal having a fin- or trench-like three-dimensional structure formed by the most stable (100) facet plane have few dangling bonds and a low surface state density. Therefore, the semiconductor device of the first embodiment that utilizes the side wall surface (side surface) has excellent electrical characteristics, such as leakage current, mobility, reliability, and breakdown voltage.
  • the side wall surface (side surface) of at least one of the linear protrusions or grooves is a channel of the semiconductor device
  • the channel has few dangling bonds and a low surface state density, so the semiconductor device is susceptible to leakage. Superior current, mobility and reliability.
  • the side wall surface (side surface) of the three-dimensional structure of the semiconductor layer 14 is preferably perpendicular to the substrate surface of the substrate 11 . If the side wall surface (side surface) is perpendicular, an interlayer film covering the semiconductor layer 14, an insulating film such as a gate insulating film, a gate electrode, etc. can be formed symmetrically with respect to the semiconductor layer 14, and the semiconductor layer 14 can be Defects such as voids are less likely to occur in the covering film. When the side wall surface (side surface) is vertical, the usability when using the side wall surface (side surface) for a channel or the like becomes very high.
  • the semiconductor layer 14 formed in the semiconductor layer 14 becomes a three-dimensional structure (fins (linear protrusions), trenches, etc.) made of ⁇ -Ga 2 O 3 crystals with vertical sidewall surfaces.
  • the longitudinal direction of the mask opening 13 in which a three-dimensional structure with a stable shape is formed is the [010] direction, and the longitudinal direction is 13.
  • a three-dimensional structure is formed in a direction tilted by 7°.
  • the substrate 11 made of ⁇ -Ga 2 O 3 crystal the substrate surface is a (001) plane, and an off angle of 13.7° is used, ⁇ - It becomes possible to provide a three-dimensional structure and a semiconductor device having a semiconductor layer 14 made of Ga 2 O 3 crystal.
  • the semiconductor device will be described as a fin structure 101, focusing on a fin (linear protrusion) portion that is a convex pattern. If attention is paid to the trench portion, which is a concave pattern, the semiconductor device can be regarded as a trench structure 101.
  • a substrate (semiconductor substrate) 11 made of ⁇ -Ga 2 O 3 crystal with a (010) or (001) crystal plane is prepared (step S11 in FIG. 4, FIG. 2(a)). ).
  • a masking pattern 12 in the form of a line or stripe (that is, a parallel line) whose longitudinal direction is parallel to the line of intersection between the substrate surface and the (100) plane is formed (step S12). Specifically, a thin film 12a made of SiO 2 or the like is formed on the substrate 11 (FIG. 2(b)), and a resist pattern 15 having linear or striped openings is formed thereon (FIG. 2(c)). )).
  • the thickness of the mask 12 is preferably 1 nm or more and 1000 nm or less. It is preferable that the thickness of the mask 12 be 1 nm or more from the viewpoint of effectively preventing foreign matter originating from Ga 2 O 3 crystals from easily occurring on the mask through film defects or the like.
  • the mask 12 is a dummy item that is not essential for the semiconductor device to be manufactured, and from the viewpoint of suppressing the formation of cracks in the mask, the thickness thereof is preferably 1000 nm or less.
  • ⁇ -Ga 2 O 3 crystals (fins) 14 are selectively grown in the openings 13 of the masking pattern 12 using a vapor phase growth method to form a fin structure (fin structure) using ⁇ -Ga 2 O 3 crystals.
  • a semiconductor device) 101 is manufactured (step S13, FIG. 2(f)).
  • the opening of the mask 12 can be easily microfabricated by using a thin film 12a such as SiO 2 that is easy to process. Therefore, with this method, it is possible to easily manufacture the fin structure 101 using fine ⁇ -Ga 2 O 3 crystals.
  • vapor phase epitaxy examples include halide vapor phase epitaxy (HVPE). , low-pressure chemical vapor deposition, metal organic vapor phase epitaxy, mist CVD cal vapor deposition).
  • HVPE halide vapor phase epitaxy
  • a feature of the vapor phase growth method of the present invention is that ⁇ -Ga 2 O 3 crystals are selectively grown using the exposed surface of the substrate made of ⁇ -Ga 2 O 3 crystals as nuclei, and a mask such as SiO 2 is used to grow ⁇ -Ga 2 O 3 crystals. It is important not to grow ⁇ -Ga 2 O 3 crystals on the surface.
  • the vapor phase growth method of the present invention uses, in addition to a gas consisting of a gallium source gas and an oxygen source gas (that is, a gas for growing ⁇ -Ga 2 O 3 crystals), a gas that has the property of etching Ga 2 O 3 . It is preferable to add a reactive gas having the following properties.
  • FIG. 14 shows a schematic configuration of a vapor phase epitaxy apparatus (HVPE apparatus) 2001 as an example of an apparatus used in the vapor phase epitaxy method.
  • the vapor phase growth apparatus 2001 includes a reaction furnace 1001 that can be heated to a desired temperature by a heater 1012.
  • the reactor 1001 includes a gallium raw material supply source 1002, an oxygen raw material supply source supply pipe 1006, an etching gas supply pipe 1008, and a substrate holder 1010, and the gas supplied to the reactor 1001 is exhausted through an exhaust pipe 1011.
  • the gallium raw material supply source 1002 is provided with gallium metal 1003 therein.
  • the gallium compound gas 1004 supplied to the gallium raw material supply source 1002 reacts with gallium metal, and the gallium raw material gas generated is delivered to the sample placed on the substrate holder 1010 through the gallium raw material gas supply pipe 1005. Supplied.
  • the oxygen source supply pipe 1006 controls and supplies a predetermined amount of oxygen source gas 1007 to the sample placed on the substrate holder 1010 .
  • the etching gas supply pipe 1008 controls and supplies a predetermined amount of etching gas (reducing gas) 1009 to the sample placed on the substrate holder 1010 .
  • the gallium compound gas 1004 is a halogen gas or a hydrogen halide gas, such as Cl 2 and HCl
  • the oxygen source gas 1007 is 1 selected from the group consisting of O 2 , H 2 O, and N 2 O.
  • O 2 can be preferably used.
  • examples of the etching gas 1009 include reducing gases such as HCl, HF, HBr, H 2 , and Cl 2 .
  • HCl can be particularly preferably used because it has low reactivity with quartz and is easy to handle.
  • the halogen compound of gallium and the oxygen source easily react to produce gallium oxide.
  • the Ga halide preferably contains GaCl and/or GaCl3 .
  • these halides are highly reactive and promote the growth of gallium oxide.
  • these gases may be supplied together with a carrier gas that is an inert gas.
  • the inert gas include nitrogen ( N2 ) gas, helium (He) gas, neon (Ne) gas, argon (Ar) gas, and krypton (Kr) gas.
  • a raw material containing a tetravalent element may be supplied.
  • the raw material containing a tetravalent element is a gas, it may be mixed and flowed from the gallium raw material supply source 1002, or a separate raw material supply source may be provided. If the raw material containing a tetravalent element is solid or liquid, it may be placed in the gallium raw material supply source 1002 like gallium metal 1003 .
  • Gallium compound gas 1004, oxygen source gas 1007, and etching gas 1009 are applied to a sample placed on substrate holder 1010 at 700°C or higher and 1300°C or lower, preferably 800°C or higher and 1200°C or lower, and more preferably 950°C or higher.
  • ⁇ -Ga 2 O 3 crystals are grown by supplying in a temperature environment of 1100° C. or lower.
  • a ⁇ -Ga 2 O 3 crystal formed on a substrate having a (010) plane as a substrate surface or a substrate having a (001) plane as a substrate surface made of a ⁇ -Ga 2 O 3 crystal by the above-mentioned HVPE method is
  • the ⁇ -Ga 2 O 3 crystal grows only on the exposed surface (13) and does not grow on the mask 12, resulting in selective growth.
  • the side surfaces of the ⁇ -Ga 2 O 3 crystal formed by this growth reflect the facets of the crystal, have a low density of dangling bonds, and have a low density of crystal defects and interface states on the crystal surface.
  • a method for manufacturing the ⁇ -Ga 2 O 3 fin structure 301 by a conventional method using dry etching will be described with reference to FIG.
  • a substrate (semiconductor substrate) 11 made of ⁇ -Ga 2 O 3 crystal is prepared (FIG. 3(a)).
  • a ⁇ -Ga 2 O 3 crystal film (31a) is epitaxially grown on the substrate 11 (FIG. 3(b)).
  • a resist pattern 32 is formed on the ⁇ -Ga 2 O 3 crystal film (31a) (FIG. 3(c)), and the ⁇ -Ga 2 O 3 crystal film (31a) is etched by dry etching to form fins (lines).
  • a ⁇ -Ga 2 O 3 crystal 31 in which a trench (groove) is formed is formed (see FIG. 3(d)). Finally, the resist pattern 32 is peeled off, and the ⁇ -Ga 2 O 3 crystal fin structure 301 is manufactured as a semiconductor device (FIG. 3(e)).
  • the semiconductor device (fin structure 301) can also be considered to be the trench structure 101 if attention is paid to the trench portion, which is a concave pattern.
  • the following problem occurs in the conventional method of manufacturing the ⁇ -Ga 2 O 3 crystal fin structure 301 using dry etching.
  • the sidewall surfaces (side surfaces) of the trenches and fins that are formed are subject to machining damage. Therefore, after dry etching, it is necessary to remove damage by a wet process using an alkali or acid. Here, even if wet etching is performed, the damage may not be completely recovered.
  • the sidewall surface (side surface) formed by dry etching does not reflect the facets of the crystal, and therefore has a high density of dangling bonds. This leads to an increase in the crystal surface and junction interface state density, which deteriorates device characteristics.
  • (3) In processing by dry etching it is difficult to create narrow and deep trenches that are desirable for device applications, or completely vertical sidewall surfaces (side surfaces). Such a limited processing shape becomes a constraint on device design.
  • Embodiment 2 a trench metal oxide semiconductor Schottky Barrier Diode (MOSSBD) 201, which is one of the semiconductor devices suitable for use as a power device, will be described, including its manufacturing method.
  • MOSSBD trench metal oxide semiconductor Schottky Barrier Diode
  • a method for manufacturing the trench MOSSBD (201) will be described with reference to FIGS. 5 and 6.
  • a substrate 51 made of ⁇ -Ga 2 O 3 crystal, a SiO 2 mask 52, and a ⁇ -Ga 2 O 3 crystal pattern ( ⁇ -Ga 2 O 3 crystal) grown in the mask opening are shown.
  • a sample (FIG. 5(a)) having a semiconductor layer) 53 is prepared.
  • the substrate 51 made of ⁇ -Ga 2 O 3 crystal one doped with Si, Sn, etc. in an amount of 10 17 cm -3 or more and 10 19 cm -3 or less can be preferably used.
  • the first embodiment as seen in the above description using FIGS.
  • the ⁇ -Ga 2 O 3 crystal pattern 53 is expressed by focusing on a convex pattern, that is, a fin (linear protrusion).
  • the grooves formed between the ⁇ -Ga 2 O 3 crystal patterns 53 are focused and expressed as a concave pattern, that is, a trench.
  • an insulating film 54a is conformally formed. It is preferable that the insulating film 54a has few levels and defects and has excellent breakdown voltage, and is made of, for example, from the group consisting of HfO 2 , Al 2 O 3 , SiO 2 , Ta 2 O 5 , HfSiO 2 , Si 3 N 4 , and SiON. You can list one or more to choose from. A single layer film or a laminated film selected from these films may be used.
  • the film forming method is not particularly limited, and examples include CVD, sputtering, and ALD (Atomic Layer Deposition).
  • the thickness of the insulating film 54a is not particularly limited, but can be 10 nm or more and 100 nm or less.
  • the first insulating film 54 is processed by removing the upper surface portion of the film 54a.
  • this processing method include a CMP (Chemical Mechanical Polishing) method, an etchback method, and a combination thereof.
  • an insulating film 56a is deposited (FIG. 5(d)), and then a resist pattern 57 having an opening exposing a desired region where a trench is to be formed is formed (FIG. 5(e)).
  • examples of the insulating film 56a include SiO 2 , SiON, SOG (Spin on Glass), and polyimide.
  • Examples of the forming method include a CVD method, a sputtering method, and a coating method.
  • the insulating film 56a is etched (FIG. 6(a)), and then the resist pattern 57 is removed by oxygen gas ashing, ozone treatment, stripping solution, etc., and a second An insulating film 56 (for example, SiO 2 ) is formed (FIG. 6(b)).
  • the upper surface portion 55 of the ⁇ -Ga 2 O 3 crystal pattern 53 where the ⁇ -Ga 2 O 3 crystal is exposed (that is, the ⁇ -Ga 2 O 3 crystal exposed portion) 55 and the exposed surface of the first insulating film 54 are After thorough cleaning, a conductive film 58a that will become an anode is formed on the surface (top surface) on the ⁇ -Ga 2 O 3 crystal pattern 53 side, and a conductive film 59 that will become a cathode is formed on the back surface (FIG. 6(c). )).
  • examples of the conductive film 58a include Pt, Au, Ni, Ag, Ru, Rh, Pd, W, Mo, Ta, and Cu.
  • Examples of methods for forming the conductive film 58a include a vapor deposition method, a sputtering method, and an MOCVD method.
  • Examples of the conductive film 59 include at least one selected from the group consisting of Ti, Al, Au, Pt, and ITO, and an alloy containing at least one selected from these groups.
  • Examples of methods for forming the conductive film 59 include a vapor deposition method, a sputtering method, and an MOCVD method.
  • the conductive film 59 is preferably in ohmic contact with the substrate 51 made of ⁇ -Ga 2 O 3 crystal. Taking this into consideration, it is also preferable to control the doping of the substrate 51 made of ⁇ -Ga 2 O 3 crystal, and to form the conductive film 59 into a laminated film.
  • the conductive film 58a is processed by lithography and etching to produce a trench MOSSBD (201) having the desired anode electrode 58 and cathode electrode (conductive film) 59.
  • the anode electrode 58 may be formed by a lift-off method instead of the film formation, lithography, and etching methods.
  • the anode electrode 58 is formed by forming an upper surface portion ( ⁇ -Ga 2 O 3 crystal exposed portion) 55 of a ⁇ -Ga 2 O 3 crystal pattern ( ⁇ -Ga 2 O 3 crystal semiconductor layer) 53 in which ⁇ -Ga 2 O 3 crystal is exposed. Therefore, the upper surface portion ( ⁇ -Ga 2 O 3 crystal exposed portion) 55 can also be called a Schottky connection portion. As shown in FIG.
  • the three-dimensional structure of the semiconductor layer made of ⁇ -Ga 2 O 3 crystals is formed between the ⁇ -Ga 2 O 3 crystal patterns 53. Focusing on the groove, it has the shape of a trench (groove), and the insulation film 54 disposed on the side wall surface (side surface) of the trench (groove) and the bottom surface of the trench (groove) (here, the insulation film 54 is The film 54 may be disposed on at least a portion of the side wall surface (side surface) of the trench (groove).)
  • the anode electrode 58 is formed to cover the trench (groove) having the three-dimensional structure.
  • the anode electrode 58 only needs to cover at least a portion of the trench.
  • the anode electrode 58 may cover at least a portion of the three-dimensional structure (that is, the trench) , has a structure in which Schottky contact is made with the semiconductor layer made of ⁇ -Ga 2 O 3 crystal.
  • the semiconductor layer 53 made of ⁇ -Ga 2 O 3 crystal (that is, the ⁇ -Ga 2 O 3 crystal semiconductor layer) is in Schottky contact with the anode electrode 58, and the ⁇ -Ga Since the side wall surface (side surface) of the 2 O 3 crystal semiconductor layer 53 reflects the facets of the crystal and has a low density of dangling bonds, the semiconductor device has a low density of crystal defects and interface states on the crystal surface.
  • the manufactured trench MOSSBD (201) has a leakage resistance that is particularly suitable for power device applications. It becomes a high voltage diode, which is a semiconductor device with excellent current characteristics.
  • the fin structure 101 using the ⁇ -Ga 2 O 3 crystal of the first embodiment is applied to a (horizontal) FinFET (202).
  • Embodiment 3 will be described below with reference to FIG. 7.
  • the structure of the (horizontal) FinFET (202) is referred to as a "Fin MOSFET structure.”
  • the lateral FinFET (202) includes an insulating substrate 61 made of ⁇ -Ga 2 O 3 crystal, a fin 62 made of ⁇ -Ga 2 O 3 crystal semiconductor, Consisting of a mask 63 made of a thin film of SiO 2 or the like, an insulating film 64 of SiO 2 or the like, a gate insulating film 65, and a gate electrode 66, a source 67 is placed at one end of the fin 62 with the gate electrode 66 in between, and a source 67 is placed at the other end. It has a structure in which a drain 68 is connected.
  • the insulating film 64 can be omitted.
  • a fin structure having the fins 62 formed in the openings of the mask 63 formed on the substrate 61 is prepared by the method described in Embodiment 1, and then CVD or sputtering is performed.
  • An insulating film 64 is formed by, for example, a gate insulating film 65 is formed thereon, and one side wall surface (first side surface) of the fin 62, the top surface, and the other side wall surface (second side surface) opposite to the first side surface. That is, a gate electrode 66 is formed so as to cover at least part of the upper surface and both side wall surfaces (both side surfaces) of the fin three-dimensional structure, and a source 67 is formed at one end of the fin 62 with the gate electrode 66 in between.
  • a drain 68 can be formed and connected to the other end.
  • the gate insulating film 65 it is preferable to use a so-called High-k film such as HfO 2 , HfSiO 2 , Al 2 O 3 and Si 3 N 4 in addition to SiO 2 .
  • the gate electrode 66 is connected to at least one side wall surface (side surface) of the three -dimensional structure (specifically, the fin 62) of the semiconductor layer made of ⁇ -Ga 2 O 3 crystal.
  • a structure is provided that is arranged (formed) so as to cover the top and side surfaces of the three-dimensional structure (that is, the entire surface of the three-dimensional structure).
  • the side wall surface (side surface) of the fin 62 made of ⁇ -Ga 2 O 3 crystalline semiconductor that becomes the channel reflects the facet of the crystal and has a low density of dangling bonds, so it is free from crystal defects and This results in a semiconductor device with a low density of interface states on the crystal surface.
  • the FinFET (202) is a FET (Field Effect Transistor) with excellent current characteristics due to the combination of the fin 62 made of such a high-quality ⁇ -Ga 2 O 3 crystalline semiconductor and the FinFET structure that can bring out excellent electrical characteristics. become. In other words, the horizontal FinFET (202) becomes a power device.
  • the fin structure 101 made of ⁇ -Ga 2 O 3 crystal of the first embodiment is applied to a (vertical) FinFET (203).
  • Embodiment 4 will be described below with reference to FIG. 8.
  • the structure of the FinFET (203) is referred to as a "Fin type MOSFET structure” like the structure of the (horizontal) FinFET (202).
  • the vertical FinFET (203) includes a substrate 71 made of ⁇ -Ga 2 O 3 crystal, an epitaxial ⁇ -Ga 2 O 3 crystal forming layer 72, a fin 73 made of ⁇ -Ga 2 O 3 crystal, and when the fin 73 is formed.
  • a mask 74 made of SiO 2 or the like that serves as a template for the process an insulating film 75 that functions as a gate insulating film, a gate electrode 76, an insulating layer 77 that serves to electrically separate the gate electrode and source electrode, etc., the fin 73 and the source electrode.
  • 79 is an ohmic contact, and includes an n + layer 78 and a drain electrode 80 which have the function of lowering the contact resistance. As shown in FIG.
  • the gate electrode 76 is formed on at least one side wall surface (side surface) of the three -dimensional structure (specifically, the fin 73) of the semiconductor layer made of ⁇ -Ga 2 O 3 crystal. It will have a structure arranged (formed) so as to cover it.
  • the substrate 71 is preferably doped with Si, Sn, or the like in an amount of 10 18 cm -3 to 10 20 cm -3 in terms of electrical resistance.
  • the epitaxial ⁇ -Ga 2 O 3 crystal forming layer 72 is a ⁇ -Ga 2 O 3 crystal with a dopant amount of 10 15 cm -3 or more and 10 17 cm -3 or less, which is formed by HVPE method or the like.
  • the thickness is preferably 1 ⁇ m or more and 50 ⁇ m or less.
  • Fin 73 is formed on epitaxial ⁇ -Ga 2 O 3 crystal formation layer 72 using mask 74 in the same manner as in the first embodiment.
  • the doping amount of the fin 73 is preferably set to 10 15 cm -3 or more and 10 17 cm -3 or less.
  • the vicinity of the surface layer of the side wall surface (side surface) of the fin 73 functions as a channel layer.
  • the insulating film (gate insulating film) 75 it is preferable to use a so-called High-k film such as HfO 2 , HfSiO 2 , Al 2 O 3 and Si 3 N 4 in addition to SiO 2 .
  • the thickness is preferably 10 nm or more and 100 nm or less.
  • the gate electrode 76 is made of Pt, Cr, Au, Ni, Ag, Ru, Rh, Pd, W, Mo, Ta, PolySi (polysilicon), and Cu
  • the source electrode 79 and drain electrode 80 are made of Ti, Al, etc. , Au, Pt, and ITO (indium tin oxide), and an alloy containing at least one member selected from these groups can be preferably used.
  • the source electrode 79 is a laminated film in which Ti, Al, and Pt are laminated in order from the bottom layer
  • the drain electrode 80 is a laminated film in which Ti and Au are laminated in order from the bottom layer.
  • a two-layer membrane can be preferably used.
  • Examples of the insulating layer 77 include SiO 2 , SiON, SOG (Spin on Glass), and polyimide.
  • N + layer 78 can be formed by ion implantation.
  • Examples of the dopant include Si and Sn, and the amount of the dopant is in the range of 10 18 cm -3 to 10 20 cm -3 .
  • the thickness can be 50 nm or more and 500 nm or less. Note that this n + layer 78 may be omitted depending on the doping amount of the fin 73 from the viewpoint of easy manufacturing.
  • the vertical FinFET (203) has a fin structure including a fin 73 formed in the opening of a mask 74 formed on the epitaxial ⁇ -Ga 2 O 3 crystal formation layer 72 by the method described in Embodiment 1.
  • An insulating film (gate insulating film) 75 is formed by a CVD method, a sputtering method, etc., and a region including at least a part of the side wall surface (side surface) of the fin 73 is formed by an evaporation method, a sputtering method, a CVD method, or an MOCVD method.
  • the gate electrode 76 is formed by a method such as a method, an insulating layer 77 is formed by a sputtering method, a CVD method, or a coating method, and a source electrode 79 and a drain electrode 80 are formed thereon.
  • the side wall surface (side surface) of the fin 73 which is made of a ⁇ -Ga 2 O 3 crystal semiconductor and serves as a channel layer, reflects the facet of the crystal and has a low density of dangling bonds. This results in a semiconductor device with low crystal defects and low density of interface states on the crystal surface.
  • the FinFET (203) has a combination of the fin 73 made of such a high-quality ⁇ -Ga 2 O 3 crystalline semiconductor and the vertical FinFET structure that can bring out excellent electrical characteristics, resulting in an FET with excellent current characteristics. Furthermore, it is desirable that the channel layer in the vertical FinFET (203) has as large an area as possible, since current can be earned more efficiently.
  • the vertical FinFET (203) In the structure of the vertical FinFET (203), by forming a large number of fins 73 per unit area by microfabrication, it is possible to increase the surface area of the channel layer. According to the present invention, it is possible to form the fins 73 that have a high packing density, are fine, and have a high aspect ratio. Therefore, the vertical FinFET (203) according to the fourth embodiment has excellent electrical characteristics, which is particularly suitable for power device applications. In other words, the vertical FinFET (203) becomes a power device.
  • Example 1 In Example 1, a sample was prepared using a substrate made of ⁇ -Ga 2 O 3 crystal with (001) plane and (010) plane as substrate planes, and was evaluated. The results are described below along with the sample preparation method.
  • a substrate 11 made of ⁇ -Ga 2 O 3 crystal was prepared, and a thin film 12a of amorphous SiO 2 was formed on the substrate 11 (FIG. 2(b)).
  • a substrate 11 made of ⁇ -Ga 2 O 3 crystal a substrate having (001) and (010) planes, which is commercially available from Novel Crystal Technology, was used.
  • the thin film 12a made of amorphous SiO 2 was formed by plasma chemical vapor deposition using tetraethoxysilane (TEOS) as a precursor, and the film thickness was 100 nm.
  • TEOS tetraethoxysilane
  • a resist pattern 15 having a groove-shaped opening pattern was formed (FIG. 2(c)). Thereafter, wet etching is performed using a hydrofluoric acid buffer (FIG. 2(d)), and then the resist pattern 15 is peeled off to form a mask made of SiO 2 (12) having groove-shaped openings 13. 12 was formed (FIG. 2(e)).
  • the resist was removed by acetone and oxygen plasma ashing, and the exposed portion ( ⁇ -Ga 2 O 3 crystal substrate exposed portion) 13a of the substrate made of ⁇ -Ga 2 O 3 crystal was degreased. .
  • the opening 13 of the mask 12 was formed so as to be parallel to the [010] direction in the substrate 11 whose substrate surface is the (001) plane, and to be parallel to the [001] direction in the substrate 11 whose substrate surface is the (010) plane. .
  • the opening 13 has a width of 1.2 ⁇ m and a length of 100 ⁇ m.
  • ⁇ -Ga 2 O 3 crystal is selectively grown by halide vapor phase epitaxy to form a semiconductor layer 14 made of ⁇ -Ga 2 O 3 crystal in the mask opening 13. Formed.
  • the details are shown below.
  • the equipment used for halide vapor phase growth was independently manufactured.
  • O 2 (purity>99.99999%) (oxygen source gas) and GaCl precursor (gallium compound gas) were used as the gas for growing ⁇ -Ga 2 O 3 crystals, and quartz heated to 1040°C was used.
  • the GaCl precursor is produced by chemically reacting Ga metal (purity>99.99999%) and HCl gas (purity>99.999%) (gallium compound gas) at 820°C.
  • the one synthesized upstream was used.
  • HCl gas was directly supplied to the production reaction region as an etching gas at a partial pressure of 0.25 kPa.
  • HCl gas has the property of etching Ga 2 O 3 crystals. The purpose of introducing this gas is to avoid parasitic gas phase reactions and to more effectively prevent the formation of Ga 2 O 3 crystal nuclei on the mask 12.
  • purified N 2 gas (dew point ⁇ -110° C.) was used as the carrier gas.
  • the flow rate was 7870 sccm.
  • the film formation time (growth time) was 15 minutes, and film formation was performed under the same conditions on the substrate 11 having either the (001) plane or the (010) plane as the substrate surface.
  • film formation was also carried out under conditions in which HCl gas, which is an etching gas for preventing nucleation on the mask 12, was not supplied.
  • FIG. 9 is an example in which a case where HCl gas is introduced (FIG. 9(a)) and a case where HCl gas is not introduced (FIG. 9(b)) are observed by SEM from above and compared.
  • SU8230 manufactured by Hitachi High-Tech
  • FIG. 9(a) a linear pattern of ⁇ -Ga 2 O 3 crystals is formed at the location corresponding to the mask opening 13, and the region where the mask 12 is formed is in a further state.
  • deposits have been confirmed on the mask 12 at a distance of 100 ⁇ m or more from the mask opening 13.
  • a resist having an opening in the field part 100 ⁇ m or more away from the mask opening 13 is used.
  • a pattern is formed, and then unnecessary deposits of Ga 2 O 3 crystals are removed by wet etching or the like, or a dummy opening is formed in advance in a field part 100 ⁇ m or more away from the mask opening 13. It is preferable to form a ⁇ -Ga 2 O 3 crystal pattern.
  • it is also effective to increase the amount of HCl gas introduced or to reduce the amount of growth precursor supplied (for example, the amount of GaCl precursor supplied) to promote the desorption reaction.
  • the trench (corresponding to the longitudinal direction of the linear protrusion (fin)) needs to be parallel to the line of intersection between the (100) plane and the substrate surface (that is, the substrate surface of the substrate).
  • the directions correspond to the [010] direction and the [001] direction, respectively.
  • FIGS. 11(a) and (010) an example in which a ⁇ -Ga 2 O 3 crystal pattern is formed with the longitudinal direction of the mask opening 13 in the [010] direction on a substrate whose substrate surface is the (001) plane is shown in FIGS. 11(a) and (010).
  • FIG. 11(b) shows an example in which a ⁇ -Ga 2 O 3 crystal pattern is formed on a substrate whose longitudinal direction is the [001] direction. It can be seen that a good striped pattern with smooth sidewall surfaces (side surfaces) was formed.
  • the substrate with the (010) plane as the substrate surface had an uneven structure with a higher aspect ratio than the substrate with the (001) plane as the substrate surface. This reflects that the growth rate in the [010] direction is high, so that the vertical growth component is sufficiently larger than the lateral growth component. Note that the facet side wall surface (side surface) of the (100) plane is perpendicular to the substrate surface. Focusing on this characteristic, when selective growth technology is used, the (010) plane is more suitable for forming trenches and fins (linear protrusions) than the (001) plane.
  • the inclination angle of the ⁇ -Ga 2 O 3 crystal pattern (specifically, SAG (Selective area growth) island) and the ⁇ -Ga 2 O 3 crystal pattern to be formed are A schematic cross-sectional view of the height is shown in FIG.
  • trenches (grooves) and fins (wires) with the (001) plane facets as the side wall surfaces (side surfaces) can be used.
  • trenches (grooves) and fins (wires) with the (001) plane facets as the side wall surfaces (side surfaces) can be used.
  • trenches (grooves) and fins (wires) with the (001) plane facets as the side wall surfaces (side surfaces) can be used.
  • the (like protrusion) structure can be formed by selective growth technology.
  • Example 2 In Example 2, a sample was prepared and evaluated using a substrate made of ⁇ -Ga 2 O 3 crystal with the (-102) plane as the substrate surface. The results are described below along with the sample preparation method.
  • the (-102) plane of the substrate has a perpendicular relationship between the (-102) plane and the (100) plane fin (linear protrusion) side wall surface (side surface), so the fin (linear protrusion) is highly useful for device applications. The formation of linear protrusions can be expected. In Example 2, this was demonstrated.
  • a sample (semiconductor device 101 according to FIG. 1) was fabricated using the same steps as in Example 1 except that a substrate with the (-102) plane as the substrate surface was used.
  • the substrate made of ⁇ -Ga 2 O 3 crystal with the (-102) plane as the substrate surface was manufactured by Novel Crystal Technology Co., Ltd., and the sample size was 10 ⁇ 15 mm 2 and the thickness is 0.65 mm.
  • the dopant was also Sn as in Example 1, and the carrier concentration was 4.9 ⁇ 10 18 cm ⁇ 3 . It was confirmed by X-ray diffraction measurement that the substrate had a (-102) plane as the substrate surface.
  • FIG. 17(a) shows the results.
  • FIG. 17(b) is a schematic diagram of the cross-sectional shape obtained by tracing the SEM observation shape.
  • the side wall surfaces (side surfaces) of the fins (linear protrusions) are (100) facets perpendicular to the main surface of the substrate.
  • a semiconductor device using a ⁇ -Ga 2 O 3 crystal semiconductor which suppresses the generation of interface states, provides good device characteristics, and is suitable for microfabrication.
  • this semiconductor device has a trench (groove) or fin (linear protrusion) structure, and brings out the characteristics of a ⁇ -Ga 2 O 3 crystal semiconductor that has a high breakdown voltage and a wide band gap.
  • it is suitable as a high-performance power device.
  • Power devices are used in a variety of fields, including the power trains of EVs and hybrid vehicles, power supplies for servers, renewable energy equipment, industrial equipment, and railway vehicles, and are positioned as indispensable devices for realizing a smart society. Therefore, it is believed that the present invention has a large impact on society and on industry.
  • SiO 2 57 Resist pattern 58 Electrode (anode electrode) 58a Conductive film 59 Conductive film (cathode electrode) 61 Insulating substrate ( ⁇ -Ga 2 O 3 crystal) 62 Fin ( ⁇ -Ga 2 O 3 crystal) 63 Mask (e.g. SiO 2 ) 64 Insulating film (e.g. SiO 2 ) 65 Gate insulating film (e.g. SiO 2 ) 66 Gate electrode 67 Source 68 Drain 71 Substrate ( ⁇ -Ga 2 O 3 crystal) 72 Formation layer of epitaxial ⁇ -Ga 2 O 3 crystal 73 Fin ( ⁇ -Ga 2 O 3 crystal) 74 Mask (e.g.

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CN119433708A (zh) * 2024-10-15 2025-02-14 南京大学 一种抑制(001)面β-Ga2O3外延生长各向异性的方法

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