WO2023231566A1 - 半导体外延结构及其制备方法、半导体器件 - Google Patents

半导体外延结构及其制备方法、半导体器件 Download PDF

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WO2023231566A1
WO2023231566A1 PCT/CN2023/086299 CN2023086299W WO2023231566A1 WO 2023231566 A1 WO2023231566 A1 WO 2023231566A1 CN 2023086299 W CN2023086299 W CN 2023086299W WO 2023231566 A1 WO2023231566 A1 WO 2023231566A1
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layer
thin film
film layer
substrate
doping
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French (fr)
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房育涛
陈帅
叶念慈
张洁
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湖南三安半导体有限责任公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/157—Doping structures, e.g. doping superlattices, nipi superlattices
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C30B25/186—Epitaxial-layer growth characterised by the substrate being specially pre-treated by, e.g. chemical or physical means
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C30B29/406—Gallium nitride
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H01L21/02507—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present disclosure relates to the field of semiconductor epitaxial technology, and specifically to a semiconductor epitaxial structure, a method for preparing the semiconductor epitaxial structure, and a semiconductor device.
  • Aluminum nitride film is an important third-generation semiconductor material with excellent characteristics such as large band gap, high breakdown field strength, corrosion resistance, strong radiation resistance, and good thermal stability. Due to the lack of large-sized and high-quality commercial gallium nitride and aluminum nitride substrates, nitride semiconductor materials are generally grown on silicon, silicon carbide or sapphire substrates through heteroepitaxial methods. Because aluminum nitride has good wettability with heteroepitaxial substrates, it is usually used as a nucleation layer material for nitride heteroepitaxial substrates. High-quality AlN thin film preparation is also a key technology for the epitaxial growth of nitride semiconductor thin film materials.
  • the methods to obtain high-quality AlN heteroepitaxial thin film materials include the following: 1. Use higher growth temperature (>1200°C) or pulse deposition method to increase the mobility of Al atoms during the AlN growth process, reduce the generation and increase of interface dislocations Dislocation annihilation efficiency; 2. Reduce the interface mismatch dislocation density by processing the substrate interface state before the growth of the AlN nucleation layer and optimizing the growth conditions of the interface AlN layer; 3. Use the patterned substrate to achieve penetration through lateral epitaxy. Dislocations are bent and terminated or annihilated at the grain boundary to reduce the dislocation density of subsequent epitaxial layers; 4.
  • the above methods will either It is more or less limited by conditions such as the narrow epitaxial growth window, equipment heating temperature limitations, and the difficulty in removing the AlN film on the graphite parts in the reaction chamber after growth. It is difficult to obtain high-quality AlN film materials simply and efficiently.
  • the objectives of the present disclosure include, for example, providing a semiconductor epitaxial structure and a method for preparing the semiconductor epitaxial structure, which can simply and efficiently obtain a high-quality nucleation layer, reduce epitaxial layer threading dislocations, and obtain a high-crystal quality epitaxial film.
  • embodiments of the present disclosure provide a semiconductor epitaxial structure, including:
  • a substrate located on one side of the substrate; and a buffer layer located on the side of the nucleation layer away from the substrate.
  • the nucleation layer includes a plurality of semiconductor periodic stacks stacked sequentially in a direction away from the substrate, and the plurality of semiconductor periodic stacks have a superlattice structure.
  • embodiments of the present disclosure provide a semiconductor device, including:
  • a substrate a nucleation layer located on one side of the substrate; a buffer layer located on the side of the nucleation layer away from the substrate; and an electrode layer located on the side of the buffer layer away from the substrate.
  • the nucleation layer includes a plurality of semiconductor periodic stacks stacked sequentially in a direction away from the substrate, and the plurality of semiconductor periodic stacks have a superlattice structure.
  • embodiments of the present disclosure provide a method for preparing a semiconductor epitaxial structure, which is used to prepare the semiconductor epitaxial structure as described in the previous embodiment.
  • the preparation method includes:
  • a substrate is provided; a nucleation layer is grown on one side of the substrate; and a buffer layer is grown on a side of the nucleation layer away from the substrate.
  • the nucleation layer includes a plurality of semiconductor periodic stacks stacked sequentially in a direction away from the substrate, and the plurality of semiconductor periodic stacking layers have a superlattice structure.
  • Embodiments of the present disclosure form a nucleation layer on a substrate, and then form a buffer layer on the nucleation layer, where the nucleation layer includes multiple layers of semiconductor periodic stacks stacked in sequence, and multiple layers of the semiconductor periodic stacking layers It is a superlattice structure.
  • the crystal quality of the nucleation layer is improved by using a multi-layer superlattice structure.
  • the superlattice structure can effectively bend the threading dislocations.
  • Reducing the dislocation density in subsequent epitaxial films achieves the effect of improving the crystal quality of the epitaxial buffer layer. And compared with the component-modulated superlattice, the interface stress of the superlattice is relatively small, so the generation of misfit dislocations at the superlattice interface can be avoided.
  • a high crystal quality gallium nitride-based buffer layer can be obtained to improve the optical and electrical properties of the device.
  • this composite nucleation layer is simple to grow, has little dependence on equipment, and can be used for nitrogen. Epitaxial wafers for gallium-based electronic devices and light-emitting devices are being mass-produced.
  • the embodiments of the present disclosure can reduce threading dislocations in the epitaxial layer by utilizing the superlattice structure to obtain a high-crystalline quality epitaxial film, and can simply and efficiently obtain a high-quality nucleation layer and reduce the number of epitaxial layers. Through threading dislocations, high crystal quality epitaxial films are obtained.
  • Figure 1 is a schematic diagram of a semiconductor epitaxial structure provided by some embodiments of the present disclosure
  • Figure 2 is a schematic structural diagram of the nucleation layer in Figure 1;
  • Figure 3 is a schematic diagram of a semiconductor epitaxial structure provided by some embodiments of the present disclosure.
  • Figure 4 is a schematic diagram of a semiconductor epitaxial structure provided by some embodiments of the present disclosure.
  • FIG. 5 is a schematic flowchart of a method for preparing a semiconductor epitaxial structure provided by some embodiments of the present disclosure.
  • Icon 100-semiconductor epitaxial structure; 110-substrate; 130-nucleation layer; 131-first thin film layer; 133-second thin film layer; 150-buffer layer; 170-channel layer; 180-stress transfer layer; 190-Barrier layer.
  • the above methods are all more or less limited by the narrow epitaxial growth window, equipment heating temperature limitations, and the difficulty in removing the AlN film on the graphite parts in the reaction chamber after growth. It is difficult to obtain high-quality AlN film materials simply and efficiently.
  • embodiments of the present disclosure provide a semiconductor epitaxial structure, a semiconductor device and a method for preparing a semiconductor epitaxial structure, which uses different superlattice structures as nucleation layers to improve the crystal quality of the nucleation layer.
  • the superlattice structure can effectively bend the threading dislocations and reduce the dislocation density in the subsequent epitaxial film. The effect of improving the crystal quality of the epitaxial buffer layer.
  • a semiconductor epitaxial structure 100 is provided that can simply and efficiently obtain a high-quality nucleation layer 130 , reduce epitaxial layer threading dislocations, and obtain high-crystal quality epitaxy. film.
  • the semiconductor epitaxial structure 100 includes a substrate 110, a nucleation layer 130 and a buffer layer 150.
  • the nucleation layer 130 is located on one side of the substrate 110, and the buffer layer 150 is located on one side of the nucleation layer 130.
  • the nucleation layer 130 is located on one side of the nucleation layer 130.
  • 130 includes a plurality of semiconductor periodic stacks sequentially stacked in a direction away from the substrate 110, and the multilayer semiconductor periodic stacking has a superlattice structure.
  • each semiconductor periodic stack in the nucleation layer may be doped with impurity atoms, or part of the semiconductor periodic layers may be doped with impurity atoms.
  • there are different layers of semiconductor periodic stacks in the nucleation layer that are doped with different impurity atoms or there are different layers of semiconductor periodic stacks that are doped with the same impurity atoms but with different concentrations.
  • the semiconductor epitaxial structure 100 may be suitable for semiconductor devices such as gallium nitride-based electronic devices or light-emitting devices, where the substrate 110 may be silicon (Si), silicon carbide (SiC), sapphire (Saphire), or other materials, The substrate 110 is used for heteroepitaxial growth.
  • semiconductor devices such as gallium nitride-based electronic devices or light-emitting devices
  • the substrate 110 may be silicon (Si), silicon carbide (SiC), sapphire (Saphire), or other materials
  • the substrate 110 is used for heteroepitaxial growth.
  • the deposition method of the substrate 110 may include CVD (Chemical Vapor Deposition, chemical vapor deposition), VPE (Vapour Phase Epitaxy, vapor phase epitaxy), MOCVD (Metal-organic Chemical Vapor Deposition, metal organic compound chemical vapor deposition), LPCVD (Low Pressure) Chemical Vapor Deposition, low pressure chemical vapor deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition), PLD (Pulsed Laser Deposition, pulse laser deposition), atomic layer epitaxy, MBE (Molecular Beam Epitaxy, molecular beam Epitaxy), sputtering, evaporation, etc.
  • CVD Chemical Vapor Deposition, chemical vapor deposition
  • VPE Vapour Phase Epitaxy, vapor phase epitaxy
  • MOCVD Metal-organic Chemical Vapor Deposition, metal organic compound chemical vapor deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • PECVD Pulsed Laser De
  • the nucleation layer 130 is an AlN material, where the nucleation layer 130 includes a multi-layer semiconductor periodic stack in a direction away from the substrate 110 , that is, it refers to including multiple layers of AlN with different doping types. film.
  • the buffer layer 150 is a gallium nitride-based buffer material, such as GaN or AlGaN.
  • the materials of the substrate 110, the nucleation layer 130 and the buffer layer 150 are only listed here and are not limiting.
  • both the nucleation layer 130 and the buffer layer 150 can be formed using CVD (Chemical Vapor Deposition), VPE (Vapor Phase Epitaxy), or MOCVD (Metal-organic Chemical Vapor Deposition).
  • the epitaxial growth is achieved by other processes.
  • the nucleation layer 130 here can be prepared using a MOCVD process.
  • the growth process of the nucleation layer 130 and the buffer layer 150 is not specifically limited.
  • the nucleation layer 130 here is a doped superlattice structure with different doping types, and due to the large lattice mismatch between the epitaxial film and the substrate 110 during the heterogeneous growth process, As a result, there are a large number of threading dislocations in the nucleation layer 130.
  • the doped superlattice structure can effectively bend the threading dislocations and reduce the dislocation density in the subsequent epitaxial film to improve the epitaxial buffer layer 150. Effect of crystal quality.
  • the interface stress of the doped superlattice is relatively small, so the generation of misfit dislocations at the superlattice interface can be avoided.
  • doping impurity atoms in the superlattice can also promote dislocation movement and dislocation annihilation, thereby reducing the threading dislocation density.
  • the doping concentration in the doped superlattice structure can be achieved by controlling the flow of the doping source, making the growth of the doped superlattice structure very convenient. Moreover, the doping atoms only form a small amount of carriers in the nucleation layer 130 and do not affect the high resistance characteristics of the nucleation layer 130 .
  • the semiconductor epitaxial structure 100 can be used to form a semiconductor device.
  • the semiconductor device can include an electrode layer formed on the buffer layer 150.
  • the electrode layer can include sources spaced apart on the buffer layer 150. , gate and drain.
  • the semiconductor device may be a gallium nitride-based electronic device and/or a light-emitting device, etc.
  • a gallium nitride-based buffer layer 150 with high crystal quality can be obtained by using a doped superlattice nucleation layer 130 to improve the optical and electrical properties of the device.
  • the composite nucleation layer 130 is simple to grow and is suitable for It has little equipment dependence and can be used in the mass production of epitaxial wafers for gallium nitride-based electronic devices and light-emitting devices.
  • the interface stress of the doped superlattice is relatively small, so the generation of misfit dislocations at the superlattice interface can be avoided.
  • doping impurity atoms in the superlattice can also promote dislocation movement and dislocation annihilation, thereby reducing the threading dislocation density.
  • the doping concentration in the doped superlattice can be controlled by the flow rate of the doping source.
  • the growth of the doped superlattice structure is very convenient, and the bandgap width of AlN is as high as 6.2eV. Doping atoms only form a small amount of carriers in AlN. Currents do not affect the high resistance characteristics of AlN.
  • a high crystal quality gallium nitride-based buffer layer can be obtained by using a doped superlattice AlN nucleation layer to improve the optical and electrical properties of the device.
  • this composite AlN layer is simple to grow and has little dependence on equipment and can be used for Epitaxial wafers for gallium nitride-based electronic devices and light-emitting devices are in mass production.
  • doping impurity atoms in the superlattice can also promote dislocation movement and dislocation annihilation, thereby reducing the threading dislocation density.
  • the doping concentration in the doped superlattice can be achieved by controlling the flow of the doping source, making the growth of the doped superlattice structure very convenient.
  • the doping atoms only form a small amount of carriers in the nucleation layer and do not affect the high resistance characteristics of the nucleation layer.
  • each semiconductor periodic stack is a first thin film layer 131 and a second thin film layer 133 sequentially stacked in a direction away from the substrate 110, and the first thin film layer 131 is doped with a first doping atom,
  • the second thin film layer 133 is doped with second doping atoms, where the first doping atoms and the second doping atoms are different types of doping atoms.
  • a doping source containing first doping atoms may be introduced.
  • a doping source containing second doping atoms may be introduced.
  • the first The doping atom is at least one of In, Ga, Si, Mg, and Zn; the second doping atom is at least one of In, Ga, Si, Mg, and Zn.
  • the doped superlattice AlN layer mentioned in this embodiment means that during the growth of the AlN layer, electron doping sources such as Ga (In) or holes (electrons) such as Mg (Si) are periodically introduced. ) superlattice structure formed by doping source.
  • the periodic deposition rules of the layer 131 and the second thin film layer 133 are adapted to periodically introduce different doping sources, thereby forming a periodically doped superlattice structure with different doping types.
  • the superlattice structure formed in this way The lattice structure has periodic stress changes, and the periodic stress changes in the doped superlattice and the aggregation effect of doped atoms near the dislocations can bend the threading dislocations in the AlN layer, thereby reducing the The density of threading dislocations in the epitaxial film further improves the crystal quality of the epitaxial GaN buffer layer 150 .
  • the doping concentration of the first doping atoms in the first thin film layer 131 and the doping concentration of the second doping atoms in the second thin film layer 133 are both in the range of 1E16/cm 3 -1E21/cm 3 between.
  • the doping concentration in the first thin film layer 131 and the second thin film layer 133 is both 1E18/cm 3 .
  • the first doping concentration and the second doping concentration are kept consistent, so that the periodic changes of the superlattice structure are more stable, the stress changes become more linear and stable, and the aggregation effect is more obvious.
  • the thickness of the first thin film layer 131 and the second thin film layer 133 is between 1-20 nm.
  • the thickness of the first thin film layer 131 and the second thin film layer 133 is both 5 nm.
  • the thicknesses of the first thin film layer 131 and the second thin film layer 133 are kept consistent, and the first thin film layer 131 and the second thin film layer 133 are
  • the basic material of layer 133 is AlN, so the same growth equipment can be used for periodic epitaxial growth, which is very convenient and simplifies the process steps.
  • the number of layers of the first film layer 131 and the second film layer 133 is greater than or equal to 3.
  • each first film layer 131 and the adjacent second film layer 133 constitute a One growth cycle.
  • the growth cycle in the nucleation layer 130 needs to be greater than or equal to 3, so that a superlattice structure with a sufficient number of layers can be formed, which is more conducive to realizing periodic stress changes in the nucleation layer 130 and The clustering effect of dopant atoms near dislocations.
  • both the first thin film layer 131 and the second thin film layer 133 have 12 layers, which on the one hand ensures that they can better exhibit periodic stress changes and the aggregation effect of doped atoms, and on the other hand, On the one hand, the overall thickness can be reduced, which is conducive to the miniaturization of the entire semiconductor device.
  • the thickness of nucleation layer 130 is between 20-250 nm.
  • the thickness of the nucleation layer 130 here is 120 nm, which ensures that it can achieve periodic stress changes and aggregation effects of dopant atoms while also preventing the nucleation layer 130 from being too thick.
  • FIG. 5 is a flow chart of a method for preparing a semiconductor epitaxial structure provided by some embodiments of the present disclosure. Schematic diagram of the process, the preparation method includes the following steps:
  • Step 1 Provide a substrate 110;
  • Step 2 Grow the nucleation layer 130 on one side of the substrate 110 .
  • a substrate 110 is first provided and sent into a reaction chamber, and then the nucleation layer 130 is grown on the substrate 110 .
  • the nucleation layer 130 includes multiple semiconductor periodic stacks stacked sequentially in a direction away from the substrate 110 .
  • At least one semiconductor periodic stack is a doped structure, and the multiple semiconductor periodic stacks form different doping types.
  • Superlattice structure For example, each semiconductor periodic stack layer may be doped with impurity atoms, or part of the semiconductor periodic layers may be doped with impurity atoms.
  • the substrate 110 can be made of silicon (Si), silicon carbide (SiC), sapphire (Saphire) or other materials, where the substrate 110 is used for heteroepitaxial growth.
  • the deposition method of the substrate 110 may include CVD (Chemical Vapor Deposition, chemical vapor deposition), VPE (Vapour Phase Epitaxy, vapor phase epitaxy), MOCVD (Metal-organic Chemical Vapor Deposition, metal organic compound chemical vapor deposition), LPCVD (Low Pressure) Chemical Vapor Deposition, low pressure chemical vapor deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition), PLD (Pulsed Laser Deposition, pulse laser deposition), atomic layer epitaxy, MBE (Molecular Beam Epitaxy, molecular beam Epitaxy), sputtering, evaporation, etc.
  • CVD Chemical Vapor Deposition, chemical vapor deposition
  • VPE Vapour Phase Epitaxy, vapor phase epitaxy
  • MOCVD Metal-organic Chemical Vapor Deposition, metal organic compound chemical vapor deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • PECVD Pulsed Laser De
  • a first thin film layer 131 doped with first doping atoms is grown on the substrate 110, and then a first thin film layer 131 doped with second doping atoms is grown.
  • the second thin film layer 133 is then repeatedly grown several times, so that the first thin film layer 131 and the second thin film layer 133 are periodically staggered, and finally the nucleation layer 130 is obtained. .
  • both the first thin film layer 131 and the second thin film layer 133 can adopt CVD (Chemical Vapor Deposition, chemical vapor deposition), VPE (Vapour Phase Epitaxy, vapor phase epitaxy), MOCVD (Metal-organic Chemical Vapor Deposition) , metal organic compound chemical vapor deposition), LPCVD (Low Pressure Chemical Vapor Deposition, low pressure chemical vapor deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition), PLD (Pulsed Laser Deposition, pulse laser deposition) , atomic layer epitaxy, MBE (Molecular Beam Epitaxy, molecular beam epitaxy) and other processes to achieve epitaxial growth.
  • the nucleation layer 130 here is performed using the MOCVD (Metal-organic Chemical Vapor Deposition, metal organic compound chemical vapor deposition) process. preparation.
  • the first doping atom and the second doping atom here may come from different doping sources, that is, during the process of growing the first thin film layer 131 , the first doping atom is continuously introduced into the reaction chamber.
  • the atomic doping source continuously introduces the doping source containing the second doping atoms into the reaction chamber, thereby using the method of periodically introducing the doping source to form a layer without doping.
  • the first thin film layer 131 and the second thin film layer 133 are of heterogeneous type.
  • Step 3 Grow the buffer layer 150 on the side of the nucleation layer 130 away from the substrate 110 .
  • the nucleation is completed after the first thin film layer 131 and the second thin film layer 133 are periodically formed to reach a preset thickness.
  • the layer 130 is prepared, and then the buffer layer 150 is grown on the surface of the nucleation layer 130 .
  • the buffer layer 150 can also be prepared using a MOCVD (Metal-organic Chemical Vapor Deposition) process.
  • step 1 Put the substrate 110 (sapphire, SiC, Si) used for heteroepitaxial growth into a metal organic chemical vapor deposition device (MOCVD), and heat the substrate 110 in a high-temperature hydrogen environment to oxidize the surface of the substrate 110 The material is decomposed and the surface damage of the substrate 110 is repaired.
  • MOCVD metal organic chemical vapor deposition device
  • step 2 grow the doped superlattice structure on the surface of the selected substrate 110 for heteroepitaxial growth, that is, grow the nucleation layer 130 on the surface of the substrate 110, and the growth temperature range is 800°C-1200°C.
  • the thickness of the nucleation layer 130 ranges from 20 nm to 200 nm.
  • the specific growth method of doped superlattice structure is as follows:
  • a doping source containing first doping atoms is introduced.
  • the first doping atoms include one of In, Ga, Si, Mg, and Zn, and the first thin film layer 131 is grown.
  • the growth thickness of the first thin film layer 131 is It is 1-20nm, and the doping concentration is between 1E16/cm 3 -1E21/cm 3 .
  • a doping source containing a second doping atom is introduced.
  • the second doping atom contains one of In, Ga, Si, Mg, and Zn, and the second thin film layer 133 is grown.
  • the growth thickness of the second thin film layer 133 is 1-20nm, the doping concentration is between 1E16/cm 3 -1E21/cm 3 , and the first doping atom and the second doping atom are of different types.
  • the first thin film layer 131 and the second thin film layer 133 are repeatedly grown for n cycles, where n ⁇ 3, and finally a doped superlattice AlN layer with a total thickness of 20-250 nm is grown.
  • step 3 grow the GaN buffer layer 150 or the AlGaN/GaN buffer layer 150 on the above-mentioned doped superlattice AlN nucleation layer 130.
  • the embodiments of the present disclosure provide a semiconductor epitaxial structure 100 and a preparation method thereof.
  • the nucleation layer 130 is formed on the substrate 110, and then the buffer layer 150 is formed on the nucleation layer 130, wherein the nucleation layer 150 is formed on the nucleation layer 130.
  • the layer 130 includes multiple layers of semiconductor periodic stacks stacked in sequence, and at least one layer of the semiconductor periodic stacking is a doped structure, so that the nucleation layer 130 forms a doped superlattice structure with different doping types.
  • the present disclosure uses doped superlattice structures of different doping types to improve the crystal quality of the nucleation layer 130 .
  • the doping superlattice structure can effectively make the threading dislocations.
  • the bending of dislocations reduces the dislocation density in subsequent epitaxial films, thereby improving the crystal quality of the epitaxial buffer layer 150 .
  • the interface stress of the doped superlattice is relatively small, so the generation of misfit dislocations at the superlattice interface can be avoided.
  • doping impurity atoms in the superlattice can also promote dislocation movement and dislocation annihilation, thereby reducing the threading dislocation density.
  • the doping concentration in the doped superlattice can be achieved by controlling the flow of the doping source, making the growth of the doped superlattice structure very convenient.
  • the preparation of the doped superlattice is simple, the interface stress is small, and no new interfaces are introduced. Dislocation.
  • the doping atoms only form a small amount of carriers in the nucleation layer 130 and do not affect the high resistance characteristics of the nucleation layer 130.
  • the bandgap width of AlN is high, the ionization efficiency of the dopant in AlN is low, and the doped superlattice AlN layer still has high resistance.
  • the doped superlattice nucleation layer 130 a high crystal quality gallium nitride-based buffer layer 150 can be obtained to improve the optical and electrical properties of the device.
  • the composite nucleation layer 130 is simple to grow and has little dependence on equipment. , can be used in the mass production of epitaxial wafers for gallium nitride-based electronic devices and light-emitting devices.
  • FIGS. 1 and 2 a semiconductor epitaxial structure 100 is provided. Its basic structure and principle and the technical effects produced are the same as those of the above-mentioned embodiments. For the sake of brief description, parts of this embodiment are not included. Where mentioned, please refer to the corresponding content in the above embodiments. The difference between this embodiment and the above-mentioned embodiment lies in the structure of the nucleation layer 130 .
  • the semiconductor epitaxial structure 100 includes a substrate 110, a nucleation layer 130 and a buffer layer 150.
  • the nucleation layer 130 is located on one side of the substrate 110, and the buffer layer 150 is located on one side of the nucleation layer 130, wherein,
  • the nucleation layer 130 includes a plurality of periodically doped and repeatedly arranged semiconductor periodic stacks, so that the nucleation layer 130 forms a doped superlattice structure with different doping types.
  • the multi-layer semiconductor periodic stack includes a first thin film layer 131 and a second thin film layer 133 that are periodically staggered.
  • the first thin film layer 131 is doped into an undoped layer, and the second thin film layer 133 is doped.
  • Doped with a second doping atom wherein the second doping atom is at least one of In, Ga, Si, Mg, and Zn.
  • the doping source may not be passed through, and when the second thin film layer 133 is grown, the doping source containing the first doping atoms may be passed through, so that the first thin film layer 131 forms a non-ionic doping source.
  • the doping layer also forms a periodically doped superlattice structure by periodically passing in a doping source.
  • the second thin film layer 133 has a doped structure
  • the first thin film layer 131 has an undoped structure, so that the first thin film layer 131 and the second thin film layer 133 can also form a superlattice structure of different doping types.
  • Different doping types can refer to the difference between doping and non-doping.
  • the periodic deposition rules of the layer 131 and the second thin film layer 133 are adapted to periodically introduce the doping source, thereby forming a periodically doped superlattice structure with different doping types.
  • the superlattice formed in this way The structure has periodic stress changes, and the periodic stress changes in the doped superlattice and the aggregation effect of doped atoms near the dislocations can bend the threading dislocations in the AlN layer, thus reducing the size of the epitaxial film.
  • the density of threading dislocations in the GaN buffer layer 150 increases the crystal quality of the epitaxial GaN buffer layer 150 .
  • the thicknesses of the first thin film layer 131 and the second thin film layer 133 may be different.
  • the first thin film layer 131 is an undoped layer
  • the second thin film layer 133 is a doped layer
  • the first thin film layer 133 is a doped layer.
  • the thickness of the layer 131 may be greater than that of the second thin film layer 133.
  • the thickness of the first thin film layer 131 is 10 nm
  • the thickness of the second thin film layer 133 is 5 nm.
  • the thickness of layer 133 is not limited in any way.
  • This embodiment also provides a method for preparing the semiconductor epitaxial structure 100, which is different from the above method embodiment in step 2, that is, the step of growing the nucleation layer 130.
  • the method for preparing the semiconductor epitaxial structure 100 provided in this embodiment includes:
  • the nucleation layer 130 is grown on one side of the substrate 110. Specifically, an undoped layer is first grown on the substrate 110, that is, an undoped first thin film layer 131 is grown, and then a non-doped first thin film layer 131 is grown on the first thin film layer. A second thin film layer 133 doped with second doping atoms is grown on 131, and then the first thin film layer 131 and the second thin film layer 133 are periodically and repeatedly grown, and finally the nucleation layer 130 is formed.
  • the substrate 110 here first needs to be sent into the reaction chamber.
  • the doping source is introduced into the reaction chamber.
  • the doping source including the third doping atom causes the second thin film layer 133 to form a doping structure.
  • Step 3 is the same as the above embodiment and will not be described again.
  • the semiconductor epitaxial structure 100 and its preparation method provided by the embodiment of the present disclosure form a nucleation layer 130 on the substrate 110, and then form a buffer layer 150 on the nucleation layer 130, wherein the nucleation layer 130 is grown by periodic repetition It consists of a first thin film layer 131 and a second thin film layer 133.
  • the first thin film layer 131 is an undoped layer
  • the second thin film layer 133 is doped with second doping atoms.
  • the embodiment of the present disclosure adopts different doping types.
  • the hybrid superlattice structure improves the crystal quality of the nucleation layer 130 .
  • the doping superlattice structure can effectively make the threading dislocations.
  • the bending of dislocations reduces the dislocation density in subsequent epitaxial films, thereby improving the crystal quality of the epitaxial buffer layer 150 .
  • the interface stress of the doped superlattice is relatively small, so the generation of misfit dislocations at the superlattice interface can be avoided.
  • doping impurity atoms in the superlattice can also promote dislocation movement and dislocation annihilation, thereby reducing the threading dislocation density.
  • the doping concentration in the doped superlattice can be achieved by controlling the flow of the doping source, making the growth of the doped superlattice structure very convenient.
  • the doping atoms only form a small amount of carriers in the nucleation layer 130 and do not affect the high resistance characteristics of the nucleation layer 130 .
  • a high crystal quality gallium nitride-based buffer layer 150 can be obtained to improve the optical and electrical properties of the device.
  • the composite nucleation layer 130 is simple to grow and has little dependence on equipment. , can be used in the mass production of epitaxial wafers for gallium nitride-based electronic devices and light-emitting devices.
  • a semiconductor epitaxial structure 100 is provided. Its basic structure and principle and the technical effects produced are the same as those of the above-mentioned embodiments. For the sake of brief description, the parts not mentioned in this embodiment can be Refer to the corresponding content in the above embodiments.
  • the semiconductor epitaxial structure 100 includes a substrate 110, a nucleation layer 130, a buffer layer 150, a channel layer 170 and a barrier layer 190.
  • the nucleation layer 130 is located on one side of the substrate 110, and the buffer layer 150 Located on one side of the nucleation layer 130 , the nucleation layer 130 includes multiple periodically doped and repeatedly arranged semiconductor periodic stacks, so that the nucleation layer 130 forms a doped superlattice with different doping types. structure.
  • the channel layer 170 is located on the side of the buffer layer 150 away from the substrate 110
  • the barrier layer 190 is located on the side of the channel layer 170 away from the substrate 110 .
  • the nucleation layer 130 is formed on the surface of the substrate 110.
  • the formation process and structure may be referred to the above embodiments.
  • the buffer layer 150 is formed on the surface of the nucleation layer 130, and the channel layer 170 is formed on the surface of the substrate 110.
  • the barrier layer 190 is formed on the channel The surface of layer 170 thereby forms the semiconductor epitaxial structure 100, thereby facilitating the formation of a semiconductor device.
  • the substrate 110 is a SiC substrate 110 with a (0001) crystal orientation
  • the nucleation layer 130 is a periodically doped AlN superlattice structure
  • the buffer layer 150 is a GaN layer
  • the channel layer 170 is a high-temperature GaN layer
  • the barrier layer 190 is an AlGaN layer.
  • This embodiment also provides a method for preparing the semiconductor epitaxial structure 100. Compared with the above embodiment, the difference is that after step 3, the following steps are also performed:
  • the channel layer 170 is grown on the side of the buffer layer 150 away from the substrate 110.
  • the channel layer 170 can also be formed using a MOCVD (Metal-organic Chemical Vapor Deposition) process.
  • MOCVD Metal-organic Chemical Vapor Deposition
  • Step 4 Grow the barrier layer 190 on the side of the channel layer 170 away from the substrate 110 .
  • the barrier layer 190 can also be prepared using a MOCVD (Metal-organic Chemical Vapor Deposition) process.
  • MOCVD Metal-organic Chemical Vapor Deposition
  • Step 11 Select a silicon carbide substrate 110 with a crystal orientation of (0001), put it into a metal organic chemical vapor deposition equipment, heat the substrate 110 to 1100°C in a hydrogen atmosphere and desorb for 5 minutes to remove the oxidation on the surface of the substrate 110 objects and defective layers.
  • Step 21 Grow an AlN nucleation layer 130 with a doped superlattice structure on the surface of the substrate 110 after completing step 11.
  • the growth of the composite AlN nucleation layer 130 includes the following steps:
  • a 5 nm Si-doped AlN layer is grown to form the first thin film layer 131.
  • the growth conditions are: the substrate 110 temperature is 1100°C, the TMAl flow rate is 300 sccm, the TMIn flow rate is 5 sccm, the NH 3 flow rate is 3000 sccm, and the growth time is 1.5 min;
  • a 5 nm Mg-doped AlN layer is grown on the first thin film layer 131 to form the second thin film layer 133.
  • the growth conditions are: substrate 110 temperature 1100°C, reaction chamber pressure 75 mbar, TMAl flow rate 300 sccm, Cp2Mg flow rate 300 sccm, The NH 3 flow rate is 3000sccm, and the growth time is 1.5min;
  • Step 31 Grow the GaN buffer layer 150 on the superlattice AlN nucleation layer 130 formed in step 21.
  • the growth conditions are substrate 110 temperature 980°C, reaction chamber pressure 100mbar, TMGa flow 230sccm, NH 3 flow 1500sccm, growth time 20min, and thickness 1000nm;
  • Step 41 Grow the high-temperature gallium nitride channel layer 170 on the gallium nitride buffer layer 150 formed in step 31.
  • the growth conditions of the high-temperature GaN channel layer 170 are: the flow rate of TMGa is 200 sccm, the flow rate of NH 3 is 30000 sccm, and the surface temperature The temperature is 1090°C, the growth rate is 2um/h, the growth time is 9min, and the thickness is about 300nm.
  • Step 51 Continue to grow the barrier layer 190 on the gallium nitride channel layer 170 formed in step 41.
  • the generation of barrier layer 190 The long conditions are: surface temperature: 1080°C, NH 3 flow rate: 8000sccm. It should be noted that before growing the barrier layer 190, an AlN intercalation layer (not shown) needs to be grown.
  • the flow rate of the AlN intercalation layer into TMAl is 400 sccm, the growth time is 16 s, and the thickness is about 1 nm; the AlGaN potential
  • the growth conditions of the barrier layer 190 are: TMAl400sccm, the Al composition corresponding to TMGa180sccm is about 25%, the growth time is 60s, and the thickness is about 20nm; after the growth of the barrier layer 190 is completed, the GaN cap layer can continue to grow, and the GaN cap layer During growth, the flow rate into TMGa is 150sccm, the growth time is 20s, and the corresponding GaN cap layer thickness is 3nm.
  • the epitaxial wafer is prepared according to the above steps, which is a gallium nitride-based HEMT epitaxial wafer with a doped superlattice nucleation layer 130 on the SiC substrate 110.
  • a semiconductor epitaxial structure 100 is provided. Its basic structure and principle and the technical effects produced are the same as those of the above-mentioned embodiments. For the sake of brief description, parts not mentioned in this embodiment can be Refer to the corresponding content in the above embodiments.
  • the semiconductor epitaxial structure 100 includes a substrate 110, a nucleation layer 130, a stress transfer layer 180, a buffer layer 150, a channel layer 170, and a barrier layer 190.
  • the nucleation layer 130 is located on one side of the substrate 110.
  • the buffer layer 150 is located on one side of the nucleation layer 130, wherein the nucleation layer 130 includes a plurality of periodically doped and repeatedly arranged semiconductor periodic stacks, so that the nucleation layer 130 forms a doped layer with different doping types.
  • Hybrid superlattice structure The stress transfer layer 180 is located between the buffer layer 150 and the nucleation layer 130, and the opposite side surfaces of the stress transfer layer 180 are in contact with the nucleation layer 130 and the buffer layer 150 respectively.
  • the channel layer 170 is located on the side of the buffer layer 150 away from the substrate 110 , and the barrier layer 190 is located on the side of the channel layer 170 away from the substrate 110 .
  • the nucleation layer 130 is formed on the surface of the substrate 110 .
  • the formation process and structure may be referred to the above embodiments.
  • the stress transfer layer 180 is formed on the surface of the nucleation layer 130
  • the buffer layer 150 is formed on the surface of the substrate 110 .
  • the channel layer 170 is formed on the surface of the buffer layer 150
  • the barrier layer 190 is formed on the surface of the channel layer 170, thereby forming the semiconductor epitaxial structure 100, which further facilitates the formation of a semiconductor device.
  • the substrate 110 selects a silicon substrate 110 with a crystal orientation of (111), the nucleation layer 130 is a periodically doped AlN superlattice structure, the stress transfer layer 180 is an AlGaN layer, and the buffer layer 150 is GaN layer, the channel layer 170 is a high-temperature GaN layer, and the barrier layer 190 is an AlGaN layer.
  • This embodiment also provides a method for preparing the semiconductor epitaxial structure 100, which is used to prepare the aforementioned semiconductor epitaxial structure 100.
  • the preparation method includes the following steps:
  • the nucleation layer 130 is grown on one side of the substrate 110.
  • the growth process of the nucleation layer 130 is consistent with the process of the previous embodiment, and will not be described again.
  • S2 Form the stress transfer layer 180 on the side of the nucleation layer 130 away from the substrate 110.
  • the AlGaN stress transfer layer 180 can be grown on the superlattice AlN nucleation layer 130.
  • the stress transfer layer 180 can play a role in stress transfer. So that periodic stress changes in the nucleation layer 130 can be better transmitted.
  • S3 Form the buffer layer 150 on the side of the stress transfer layer 180 away from the substrate 110.
  • the buffer layer 150 can be directly grown on the stress transfer layer 180, and the growth method is the same as the previous embodiment, which is not detailed here.
  • Step 12 Select a silicon substrate 110 with the crystal orientation (111) and put it into the metal organic chemical vapor deposition equipment. Heat the substrate 110 to 1060°C in a hydrogen atmosphere for 5 minutes to desorb and remove the oxide layer on the surface of the silicon substrate 110. .
  • Step 22 Grow an AlN nucleation layer 130 with a doped superlattice structure on the surface of the substrate 110 after completing step 12.
  • the growth of the superlattice nucleation layer 130 includes the following steps:
  • the organic metal source TMAl is pre-passed.
  • the pre-pass conditions of TMAl are: substrate 110 temperature 1050°C, reaction chamber pressure 75 mbar, TMAl flow rate 100 sccm, pre-pass time 40 seconds;
  • the growth conditions are: the substrate 110 temperature is 1100°C, the TMAl flow rate is 300 sccm, the NH 3 flow rate is 3000 sccm, and the growth time is 3 minutes;
  • a 5 nm silicon-doped AlN layer is grown on the AlN layer on the first thin film layer 131 to form the second thin film layer 133.
  • the growth conditions are: substrate 110 temperature 1100°C, reaction chamber pressure 75 mbar, TMAl flow rate 300 sccm, 200 ppm SiH4 /H2 flow rate is 500sccm, NH 3 flow rate is 3000sccm, and growth time is 1.5min;
  • Step 32 Grow the AlGaN stress transfer layer 180 on the superlattice AlN nucleation layer 130 formed in step 22.
  • the stress transfer layer 180 includes a 300nm Al 0.75 Ga 0.25 N layer, a 1000nm Al 0.5 Ga 0.5 N layer and a 1500nm Al 0.2 Ga 0.8 N layer.
  • the growth temperature is 1030°C
  • the pressure of the reaction chamber is 55mbar
  • the NH 3 flow rate is 3000 sccm. .
  • Step 42 Grow the GaN buffer layer 150 on the stress transfer layer 180 formed in step 32.
  • the growth conditions are the temperature of the substrate 110 is 980°C, the pressure of the reaction chamber is 55mbar, the flow rate of TMGa is 230sccm, the flow rate of NH 3 is 1500sccm, and the growth time is 30 minutes. Thickness is 1500nm;
  • Step 52 Grow a high-temperature gallium nitride channel layer 170 on the gallium nitride layer formed in step 42.
  • the growth conditions of the high-temperature GaN channel layer 170 are: the TMGa flow rate is 200 sccm, the NH 3 flow rate is 30,000 sccm, the surface temperature is 1080°C, the growth rate is 2um/h, the growth time is 6 minutes, and the thickness is about 200nm.
  • Step 62 Continue to grow the barrier layer 190 on the GaN channel layer 170.
  • the growth conditions of the barrier layer 190 are: the surface temperature is: 1080°C, the NH3 flow rate is 8000 sccm; the growth rate of the AlN intercalation layer into TMAl is 400 sccm, the growth time is 16 s, and the thickness is about 1 nm; the AlGaN barrier layer 190
  • the growth conditions are: TMAl200sccm, TMGa200sccm corresponding to an Al composition of about 20%, a growth time of 80s, a thickness of about 25nm; and the growth of the GaN cap layer, the flow rate into TMGa is 150sccm, a growth time of 20s, corresponding to a GaN cap layer thickness of 3nm. .
  • the epitaxial wafer prepared according to the above steps is a gallium nitride-based HEMT epitaxial wafer with a doped superlattice nucleation layer 130 on the Si substrate 110 .
  • a stress transfer layer 180 is added, which is used to store sufficient compressive stress to balance the tensile stress generated by the cooling of the gallium nitride-based epitaxial film after growth on the silicon substrate 110, thereby obtaining an epitaxial wafer with low warpage.

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Abstract

本公开的实施例提供了一种半导体外延结构和半导体外延结构的制备方法，涉及半导体外延技术领域，该半导体外延结构包括衬底、成核层和缓冲层，本公开通过在衬底上形成成核层，然后再在成核层上形成缓冲层，其中，成核层包括多层周期性掺杂且重复排列的半导体周期叠层，从而使得成核层形成了具有不同掺杂类型的掺杂超晶格结构，本公开实施例采用不同掺杂类型的掺杂超晶格结构提高成核层的晶体质量，本公开实施例利用形成的掺杂超晶格可以减小外延层穿透位错而获得高晶体质量的外延薄膜，并且能够简单高效地获得高质量成核层，减少外延层穿透位错，从而获得高晶体质量的外延薄膜。

Description

半导体外延结构及其制备方法、半导体器件
相关申请的交叉引用
本公开要求于2022年05月30日提交中国国家知识产权局的申请号为202210601247.3、名称为“半导体外延结构和半导体外延结构的制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体外延技术领域，具体而言，涉及一种半导体外延结构、半导体外延结构的制备方法及半导体器件。
背景技术
氮化铝薄膜是一种重要的第三代半导体材料，具有禁带宽度大、击穿场强高、耐腐蚀、抗辐射能力强、热稳定性好等优良特性。氮化物半导体材料由于缺乏大尺寸高质量商用的氮化镓和氮化铝衬底，一般是通过异质外延的方法生长在硅、碳化硅或蓝宝石衬底上。由于氮化铝与异质外延衬底具有较好的浸润性，通常被用作氮化物异质外延的成核层材料。高质量的AlN薄膜制备也是氮化物半导体薄膜材料外延生长的关键技术。
氮化铝薄膜和碳化硅衬底(硅衬底)之间一般存在较大的晶格失配和热失配，因此异质外延生长的AlN薄膜中存在大量的穿透位错和微裂纹。氮化铝异质外延生长中的穿透位错密度降低通常需要界面或点缺陷的参与来促进穿透位错的湮灭，因此获得高质量AlN层需要优化生长条件或采用特定外延结构。
一般获得高质量AlN异质外延薄膜材料的方法有下面几种：1.采用较高生长温度(>1200℃)或脉冲沉积方法提高AlN生长过程中Al原子迁移率减小界面位错产生和提高位错湮灭效率；2.通过处理AlN成核层生长前衬底界面状态和优化界面AlN层生长条件降低界面失配位错密度；3.利用图形化衬底通过侧向外延的方法使穿透位错在晶界发生弯曲而终止或湮灭减小后续外延层的位错密度；4.增加AlN层的生长厚度从而增加位错湮灭几率减小AlN表面的穿透位错密度；上述方法都会或多或少受到外延生长窗口偏窄、设备加热温度限制以及生长后反应室石墨件上AlN薄膜难以去除等条件限制，难以简单高效地获得高质量AlN薄膜材料。
发明内容
本公开的目的包括，例如，提供了一种半导体外延结构和半导体外延结构的制备方法，其能够简单高效地获得高质量成核层，减少外延层穿透位错获得高晶体质量的外延薄膜。
本公开的实施例可以这样实现：
第一方面，本公开实施例提供一种半导体外延结构，包括：
衬底；位于所述衬底一侧的成核层；以及位于所述成核层远离所述衬底一侧的缓冲层。
其中，所述成核层包括多层沿远离所述衬底方向上依次堆叠的半导体周期叠层，且多层所述半导体周期叠层为超晶格结构。
第二方面，本公开实施例提供一种半导体器件，包括：
衬底；位于所述衬底一侧的成核层；位于所述成核层远离所述衬底一侧的缓冲层；位于所述缓冲层远离所述衬底一侧的电极层。
其中，所述成核层包括多层沿远离所述衬底方向上依次堆叠的半导体周期叠层，且多层所述半导体周期叠层为超晶格结构。
第三方面，本公开实施例提供一种半导体外延结构的制备方法，用于制备如前述实施方式所述的半导体外延结构，所述制备方法包括：
提供一衬底；在所述衬底的一侧生长成核层；在所述成核层远离所述衬底的一侧生长缓冲层。
其中，所述成核层包括沿远离所述衬底方向上多层依次堆叠的半导体周期叠层，且多层所述半导体周期叠层为超晶格结构。
本公开实施例的有益效果包括：
本公开实施例通过在衬底上形成成核层，然后再在成核层上形成缓冲层，其中，成核层包括多层依次堆叠的半导体周期叠层，且多层所述半导体周期叠层为超晶格结构，如此，通过采用多层超晶格结构提高成核层的晶体质量。在异质生长过程中由于外延薄膜和衬底之间存在较大的晶格失配，使得成核层中存在大量的穿透位错，利用超晶格结构可以有效使穿透位错发生弯曲减小后续外延膜中的位错密度实现提高外延缓冲层晶体质量的效果。并且相比于组分调制超晶格，超晶格的界面应力比较小，因此可以避免超晶格界面处失配位错的产生。利用超晶格的成核层可以获得高晶体质量的氮化镓基缓冲层从而改善器件的光学和电性特性，同时这种复合成核层生长简单、对设备依赖性小，可以用于氮化镓基电子器件和发光器件的外延片大量生产中。相较于现有技术，本公开实施例通过利用超晶格结构可以减小外延层穿透位错而获得高晶体质量的外延薄膜，并且能够简单高效地获得高质量成核层，减少外延层穿透位错获得高晶体质量的外延薄膜。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本公开的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为本公开一些实施例提供的半导体外延结构的示意图；
图2为图1中成核层的结构示意图；
图3为本公开一些实施例提供的半导体外延结构的示意图；
图4为本公开一些实施例提供的半导体外延结构的示意图；
图5为本公开一些实施例提供的半导体外延结构的制备方法的流程示意图。
图标：100-半导体外延结构；110-衬底；130-成核层；131-第一薄膜层；133-第二薄膜层；150-缓冲层；170-沟道层；180-应力传递层；190-势垒层。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本公开实施例的组件可以以各种不同的配置来布置和设计。
因此，以下对在附图中提供的本公开的实施例的详细描述并非旨在限制要求保护的本公开的范围，而是仅仅表示本公开的选定实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
在本公开的描述中，需要说明的是，若出现术语“上”、“下”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该发明产品使用时惯常摆放的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
此外，若出现术语“第一”、“第二”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
正如背景技术中所公开的，现有技术中为了获取高质量AlN异质外延薄膜材料，通常采用以下几种方式：
1、采用较高生长温度(>1200℃)或脉冲沉积方法提高AlN生长过程中Al原子迁移率减小界面位错产生和提高位错湮灭效率，这种方式需要用到高温环境，并且对设备的要求较高，难以实现量产。
2、通过处理AlN成核层生长前衬底界面状态和优化界面AlN层生长条件降低界面失配位错密度。
3、利用图形化衬底通过侧向外延的方法使穿透位错在晶界发生弯曲而终止或湮灭减小后续外延层的位错密度。
4、增加AlN层的生长厚度从而增加位错湮灭几率减小AlN表面的穿透位错密度。
然而，上述方法都会或多或少受到外延生长窗口偏窄、设备加热温度限制以及生长后反应室石墨件上AlN薄膜难以去除等条件限制，难以简单高效地获得高质量AlN薄膜材料。
为了解决上述问题，本公开实施例提供了一种半导体外延结构、半导体器件和半导体外延结构的制备方法，其采用不同超晶格结构作为成核层以提高成核层的晶体质量。在异质外成核层中由于外延薄膜和衬底之间存在较大的晶格失配，利用超晶格结构可以有效使穿透位错发生弯曲减小后续外延膜中的位错密度实现提高外延缓冲层晶体质量的效果。
需要说明的是，在不冲突的情况下，本公开的实施例中的特征可以相互结合。
在一些实施例中，参见图1和图2，提供了一种半导体外延结构100，其能够简单高效地获得高质量成核层130，减少外延层穿透位错，并获得高晶体质量的外延薄膜。
这里，半导体外延结构100，包括衬底110、成核层130和缓冲层150，成核层130位于衬底110的一侧，缓冲层150位于成核层130的一侧，其中，成核层130包括多层沿远离衬底110方向上依次堆叠的半导体周期叠层，且多层半导体周期叠层为超晶格结构。示例性地，成核层中每层半导体周期叠层可以是均掺杂有杂质原子，也可以是其中部分半导体周期层掺杂有杂质原子。示例性地，成核层中存在不同层半导体周期叠层掺杂的杂质原子不同，或者是，存在不同层半导体周期叠层中掺杂的杂质原子相同但浓度不同。
在一些实施例中，半导体外延结构100可以适用于氮化镓基电子器件或发光器件等半导体器件，其中衬底110可以是硅(Si)、碳化硅(SiC)、蓝宝石(Saphhire)等材料，其中衬底110用于异质外延生长。衬底110的沉积方法可以包括CVD(Chemical Vapor Deposition，化学气相沉积)、VPE(Vapour Phase Epitaxy，气相外延)、MOCVD(Metal-organic Chemical Vapor Deposition，金属有机化合物化学气相沉积)、LPCVD(Low Pressure Chemical Vapor Deposition，低压力化学气相沉积)、PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积)、PLD(Pulsed Laser Deposition，脉冲激光沉积)、原子层外延、MBE(Molecular Beam Epitaxy，分子束外延)、溅射、蒸发等。当然，此处对于衬底110的沉积方法并不作具体限定。
在一些实施例中，成核层130为AlN材料，此处成核层130包括有沿远离衬底110方向的多层半导体周期叠层，即指的是包括多层具有不同掺杂类型的AlN薄膜。同时，缓冲层150为氮化镓基缓冲材料，例如GaN或AlGaN。当然，此处对于衬底110、成核层130以及缓冲层150的材料仅仅是列举，并不起到限定作用。
在一些实施例中，成核层130和缓冲层150均可以采用CVD(Chemical Vapor Deposition，化学气相沉积)、VPE(Vapour Phase Epitaxy，气相外延)、MOCVD(Metal-organic Chemical Vapor Deposition，金属有机化合物化学气相沉积)、LPCVD(Low Pressure Chemical Vapor  Deposition，低压力化学气相沉积)、PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积)、PLD(Pulsed Laser Deposition，脉冲激光沉积)、原子层外延、MBE(Molecular Beam Epitaxy，分子束外延)等工艺实现外延生长，示例性地，此处成核层130可以采用MOCVD工艺制备，当然，对于此处成核层130和缓冲层150的生长工艺并不作具体限定。
需要说明的是，此处成核层130为具有不同掺杂类型的掺杂超晶格结构，而在异质生长过程中由于外延薄膜和衬底110之间存在较大的晶格失配，使得成核层130中存在大量的穿透位错，本实施例中利用掺杂超晶格结构可以有效使穿透位错发生弯曲减小后续外延膜中的位错密度实现提高外延缓冲层150晶体质量的效果。并且相比于组分调制超晶格，掺杂超晶格的界面应力比较小，因此可以避免超晶格界面处失配位错的产生。另外掺杂超晶格中的杂质原子也可以促进位错的运动和位错湮灭进而减小穿透位错密度。
还需要说明的是，掺杂超晶格结构中的掺杂浓度大小可以通过掺杂源的流量控制实现，使得掺杂超晶格结构生长非常方便。并且掺杂原子在成核层130中仅形成少量的载流子，不影响成核层130的高阻特性。需要补充的是，该半导体外延结构100可以用于形成半导体器件，该半导体器件可以包括在缓冲层150上形成的电极层，示例性地，电极层可以包括间隔设置在缓冲层150上的源极、栅极和漏极。该半导体器件可以为氮化镓基电子器件和/或发光器件等。本实施例通过利用具有掺杂超晶格成核层130可以获得高晶体质量的氮化镓基缓冲层150从而改善器件的光学和电性特性，同时这种复合成核层130生长简单、对设备依赖性小，可以用于氮化镓基电子器件和发光器件的外延片大量生产中。
相比于组分调制超晶格，掺杂超晶格的界面应力比较小，因此可以避免超晶格界面处失配位错的产生。另外掺杂超晶格中的杂质原子也可以促进位错的运动和位错湮灭进而减小穿透位错密度。掺杂超晶格中的掺杂浓度大小可以通过掺杂源的流量控制实现掺杂超晶格结构生长非常方便，并且AlN的禁带宽度高达6.2eV掺杂原子在AlN中仅形成少量的载流子不影响AlN高阻特性。利用具有掺杂超晶格AlN成核层可以获得高晶体质量的氮化镓基缓冲层从而改善器件的光学和电性特性，同时这种复合AlN层生长简单、对设备依赖性小可以用于氮化镓基电子器件和发光器件的外延片大量生产中。
另外掺杂超晶格中的杂质原子也可以促进位错的运动和位错湮灭进而减小穿透位错密度。掺杂超晶格中的掺杂浓度大小可以通过掺杂源的流量控制实现，使得掺杂超晶格结构生长非常方便。并且掺杂原子在成核层中仅形成少量的载流子，不影响成核层的高阻特性。
在一些实施例中，每层半导体周期叠层为沿远离衬底110方向上依次堆叠的第一薄膜层131和第二薄膜层133，第一薄膜层131中掺杂有第一掺杂原子，第二薄膜层133掺杂有第二掺杂原子，其中第一掺杂原子和第二掺杂原子为不同种类的掺杂原子。具体地，在 生长第一薄膜层131时，可以通入包含第一掺杂原子的掺杂源，在生长第二薄膜层133时，可以通入包含第二掺杂原子的掺杂源，具体地，第一掺杂原子为In，Ga，Si，Mg，Zn中的至少一种；第二掺杂原子为In，Ga，Si，Mg，Zn中的至少一种。也就是说，本实施例中提及的具有掺杂超晶格AlN层，是指在AlN层生长时周期性通入Ga(In)等电子掺杂源或者Mg(Si)等空穴(电子)掺杂源形成的超晶格结构。
值得注意的是，此处通过周期性地通入掺杂源以实现超晶格结构在工艺上并不难实现，与常规的超晶格结构所不同的是，本实施例中根据第一薄膜层131和第二薄膜层133的周期性沉积规律，适配地周期性通入不同的掺杂源，从而使得形成周期性掺杂且具有不同掺杂类型的超晶格结构，这样形成的超晶格结构具有周期性的应力变化，而利用掺杂超晶格中周期性的应力变化和掺杂原子在位错附近的聚集效应可以使AlN层中的穿透位错发生弯曲，从而减小外延膜中的穿透位错的密度，进而提高外延GaN缓冲层150的晶体质量。
在一些实施例中，第一掺杂原子在第一薄膜层131中的掺杂浓度和第二掺杂原子在第二薄膜层133中的掺杂浓度均在1E16/cm3-1E21/cm3之间。示例性地，此处第一薄膜层131和第二薄膜层133中的掺杂浓度均为1E18/cm3。本实施例中将第一掺杂浓度和第二掺杂浓度保持一致，使得超晶格结构的周期性变化更加稳定，并且应力变化更加趋于线性和稳定，且使得聚集效应更加明显。
在一些实施例中，第一薄膜层131和第二薄膜层133的厚度均在1-20nm之间。示例性地，第一薄膜层131和第二薄膜层133的厚度均为5nm，此处将第一薄膜层131和第二薄膜层133的厚度保持一致，并且第一薄膜层131和第二薄膜层133的基础材料均为AlN，故可以采用同一生长设备进行周期性外延生长，十分方便，并简化了工艺步骤。
在一些实施例中，第一薄膜层131和第二薄膜层133的层数均大于或等于3，具体地，此处每个第一薄膜层131和相邻的第二薄膜层133即构成了一个生长周期，本实施例中成核层130中的生长周期需要大于或等于3，从而能够构成具有足够层数的超晶格结构，更加有利于实现成核层130中周期性的应力变化和掺杂原子在位错附近的聚集效应。示例性地，在一些实施例中第一薄膜层131和第二薄膜层133均为12层，一方面能够保证其能够更好地显现出周期性的应力变化和掺杂原子的聚集效应，另一方面能够实现整体厚度的减薄，有利于整个半导体器件的微型化。
在一些实施例中，成核层130的厚度在20-250nm之间。示例性地，此处成核层130的厚度为120nm，在保证其能够实现周期性的应力变化和掺杂原子的聚集效应的同时，也能够避免成核层130过厚。
本实施例还提供了一种半导体外延结构100的制备方法，其用于制备前述的半导体外延结构100，请参见图5，图5为本公开一些实施例提供的半导体外延结构的制备方法的流 程示意图，该制备方法包括以下步骤：
步骤1：提供一衬底110；
步骤2：在衬底110的一侧生长成核层130。
具体地，首先提供一衬底110，并将衬底110送入一反应腔，然后在衬底110上生长成核层130。其中，成核层130包括沿远离衬底110方向的多层依次堆叠的半导体周期叠层，至少一层半导体周期叠层为掺杂结构，且多层半导体叠层形成不同掺杂类型的掺杂超晶格结构。示例性地，可以是每层半导体周期叠层均掺杂有杂质原子，也可以是其中部分半导体周期层掺杂有杂质原子。该衬底110可以是硅(Si)、碳化硅(SiC)、蓝宝石(Saphhire)等材料，其中衬底110用于异质外延生长。衬底110的沉积方法可以包括CVD(Chemical Vapor Deposition，化学气相沉积)、VPE(Vapour Phase Epitaxy，气相外延)、MOCVD(Metal-organic Chemical Vapor Deposition，金属有机化合物化学气相沉积)、LPCVD(Low Pressure Chemical Vapor Deposition，低压力化学气相沉积)、PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积)、PLD(Pulsed Laser Deposition，脉冲激光沉积)、原子层外延、MBE(Molecular Beam Epitaxy，分子束外延)、溅射、蒸发等。当然，此处对于衬底110的沉积方法并不作具体限定。
在衬底110上生长成核层130时，首先在衬底110上生长掺杂有第一掺杂原子第一薄膜层131，然后再在第一薄膜层131生长掺杂有第二掺杂原子第二薄膜层133，再然后重复生长第一薄膜层131和第二薄膜层133若干次，以使第一薄膜层131和第二薄膜层133周期性交错分别，并最终得到了成核层130。需要说明的是，此处第一薄膜层131和第二薄膜层133均可以采用CVD(Chemical Vapor Deposition，化学气相沉积)、VPE(Vapour Phase Epitaxy，气相外延)、MOCVD(Metal-organic Chemical Vapor Deposition，金属有机化合物化学气相沉积)、LPCVD(Low Pressure Chemical Vapor Deposition，低压力化学气相沉积)、PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积)、PLD(Pulsed Laser Deposition，脉冲激光沉积)、原子层外延、MBE(Molecular Beam Epitaxy，分子束外延)等工艺实现外延生长，示例性地，此处成核层130采用MOCVD(Metal-organic Chemical Vapor Deposition，金属有机化合物化学气相沉积)工艺进行制备。
值得注意的是，此处第一掺杂原子和第二掺杂原子可以来自不同的掺杂源，即在生长第一薄膜层131的过程中，持续向反应腔内通入包含第一掺杂原子的掺杂源，在生长第二薄膜层133的过程中，持续向反应腔内通入包含第二掺杂原子的掺杂源，从而利用周期性通入掺杂源的方法来形成不用掺杂类型的第一薄膜层131和第二薄膜层133。
步骤3：在成核层130远离衬底110的一侧生长缓冲层150。
具体地，在周期性地形成第一薄膜层131和第二薄膜层133达到预设厚度后完成成核 层130的制备，然后在成核层130的表面生长形成缓冲层150。缓冲层150也可以采用MOCVD(Metal-organic Chemical Vapor Deposition，金属有机化合物化学气相沉积)工艺进行制备。
下面对实际工艺过程以及环境参数进行详细描述：
在步骤1中：将用于异质外延的衬底110(蓝宝石，SiC，Si)放入金属有机化学气相沉积设备(MOCVD)中，在高温氢气环境加热衬底110，使得衬底110表面氧化物分解，并修复衬底110表面损伤。
在步骤2中：在所选的用于异质外延的衬底110表面生长掺杂超晶格结构，即在衬底110的表面生长成核层130，生长温度范围为800℃-1200℃，成核层130的厚度范围为20nm-200nm。掺杂超晶格结构具体生长方式如下：
首先通入包含第一掺杂原子的掺杂源，第一掺杂原子包含In，Ga，Si，Mg，Zn中的一种，并生长第一薄膜层131，第一薄膜层131的生长厚度为1-20nm，掺杂浓度在1E16/cm3-1E21/cm3之间。
然后通入包含第二掺杂原子的掺杂源，第二掺杂原子包含In，Ga，Si，Mg，Zn中的一种，并生长第二薄膜层133，第二薄膜层133的生长厚度为1-20nm，掺杂浓度在1E16/cm3-1E21/cm3之间，且第一掺杂原子与第二掺杂原子的种类不同。
再然后重复生长n个周期的第一薄膜层131和第二薄膜层133，其中n≥3，最终生长总厚度20-250nm的掺杂超晶格AlN层。
在步骤3中：在上述掺杂超晶格AlN成核层130上生长GaN缓冲层150或AlGaN/GaN缓冲层150。
综上所述，本公开实施例提供了一种半导体外延结构100及其制备方法，在衬底110上形成成核层130，然后再在成核层130上形成缓冲层150，其中，成核层130包括多层多层依次堆叠的半导体周期叠层，至少一层半导体周期叠层为掺杂结构，从而使得成核层130形成了具有不同掺杂类型的掺杂超晶格结构，本公开实施例采用不同掺杂类型的掺杂超晶格结构提高成核层130的晶体质量。在异质生长过程中由于外延薄膜和衬底110之间存在较大的晶格失配，使得成核层130中存在大量的穿透位错，利用掺杂超晶格结构可以有效使穿透位错发生弯曲减小后续外延膜中的位错密度实现提高外延缓冲层150晶体质量的效果。并且相比于组分调制超晶格，掺杂超晶格的界面应力比较小，因此可以避免超晶格界面处失配位错的产生。另外掺杂超晶格中的杂质原子也可以促进位错的运动和位错湮灭进而减小穿透位错密度。掺杂超晶格中的掺杂浓度大小可以通过掺杂源的流量控制实现，使得掺杂超晶格结构生长非常方便，掺杂超晶格制备简单界面应力较小且不会引入新的界面位错。并且掺杂原子在成核层130中仅形成少量的载流子，不影响成核层130的高阻特性， 即本实施例中AlN的禁带宽度高，掺杂剂在AlN中的电离效率低，掺杂超晶格AlN层仍具有高阻性。利用具有掺杂超晶格成核层130可以获得高晶体质量的氮化镓基缓冲层150从而改善器件的光学和电性特性，同时这种复合成核层130生长简单、对设备依赖性小，可以用于氮化镓基电子器件和发光器件的外延片大量生产中。
在另一些实施例中，请继续参见图1和图2，提供了一种半导体外延结构100，其基本结构和原理及产生的技术效果和上述实施例相同，为简要描述，本实施例部分未提及之处，可参考上述实施例中相应内容。本实施例与上述实施例不同的是在于成核层130的结构。
在一些实施例中，半导体外延结构100包括衬底110、成核层130和缓冲层150，成核层130位于衬底110的一侧，缓冲层150位于成核层130的一侧，其中，成核层130包括多层周期性掺杂且重复排列的半导体周期叠层，从而使得成核层130形成了具有不同掺杂类型的掺杂超晶格结构。
在一些实施例中，多层半导体周期叠层包括周期性交错分布的第一薄膜层131和第二薄膜层133，第一薄膜层131中掺杂为非掺杂层，第二薄膜层133掺杂有第二掺杂原子，其中，第二掺杂原子为In，Ga，Si，Mg，Zn中的至少一种。具体地，在生长第一薄膜层131时，可以不通入掺杂源，在生长第二薄膜层133时，可以通入包含第一掺杂原子的掺杂源，使得第一薄膜层131形成非掺杂层，其同样通过周期性地通入掺杂源形成了周期性掺杂的超晶格结构。其中，第二薄膜层133为掺杂结构，第一薄膜层131为非掺杂结构，从而使得第一薄膜层131和第二薄膜层133也可以构成不同掺杂类型的超晶格结构，此处不同掺杂类型可以指的是掺杂和非掺杂的区别。
值得注意的是，此处通过周期性地通入掺杂源以实现超晶格结构在工艺上并不难实现，与常规的超晶格结构所不同的是，本实施例中根据第一薄膜层131和第二薄膜层133的周期性沉积规律，适配地周期性通入掺杂源，从而使得形成周期性掺杂且具有不同掺杂类型的超晶格结构，这样形成的超晶格结构具有周期性的应力变化，而利用掺杂超晶格中周期性的应力变化和掺杂原子在位错附近的聚集效应可以使AlN层中的穿透位错发生弯曲，从而减小外延膜中的穿透位错的密度，进而提高外延GaN缓冲层150的晶体质量。
需要说明的是，本实施例中第一薄膜层131和第二薄膜层133的厚度可以不一致，其中第一薄膜层131为非掺杂层，第二薄膜层133为掺杂层，第一薄膜层131的厚度可以大于第二薄膜层133，例如，第一薄膜层131为10nm，第二薄膜层133为5nm，当然，此处仅仅是举例说明，并不对第一薄膜层131和第二薄膜层133的厚度做任何限定。
本实施例也提供了一种半导体外延结构100的制备方法，其与上述方法实施例的不同在于步骤2，即生长成核层130的步骤不同。本实施例提供的半导体外延结构100的制备方法包括：
步骤2中，在衬底110的一侧生长成核层130，具体地，首先在衬底110上生长非掺杂层，即生长非掺杂的第一薄膜层131，然后在第一薄膜层131上生长掺杂有第二掺杂原子的第二薄膜层133，然后周期性地重复生长第一薄膜层131和第二薄膜层133，并最终形成了成核层130。
需要说明的是，此处衬底110首先需要送入反应腔，在生长第一薄膜层131时，可以避免向反应腔内通入掺杂源，在生长第二薄膜层133时，则通入包含第而掺杂原子的掺杂源，使得第二薄膜层133形成掺杂结构。
步骤3与上述实施例相同，在此不再赘述。
本公开实施例提供的半导体外延结构100及其制备方法，在衬底110上形成成核层130，然后再在成核层130上形成缓冲层150，其中，成核层130由周期性重复生长的第一薄膜层131和第二薄膜层133构成，第一薄膜层131为非掺杂层，第二薄膜层133掺杂有第二掺杂原子，本公开实施例采用不同掺杂类型的掺杂超晶格结构提高成核层130的晶体质量。在异质生长过程中由于外延薄膜和衬底110之间存在较大的晶格失配，使得成核层130中存在大量的穿透位错，利用掺杂超晶格结构可以有效使穿透位错发生弯曲减小后续外延膜中的位错密度实现提高外延缓冲层150晶体质量的效果。并且相比于组分调制超晶格，掺杂超晶格的界面应力比较小，因此可以避免超晶格界面处失配位错的产生。另外掺杂超晶格中的杂质原子也可以促进位错的运动和位错湮灭进而减小穿透位错密度。掺杂超晶格中的掺杂浓度大小可以通过掺杂源的流量控制实现，使得掺杂超晶格结构生长非常方便。并且掺杂原子在成核层130中仅形成少量的载流子，不影响成核层130的高阻特性。利用具有掺杂超晶格成核层130可以获得高晶体质量的氮化镓基缓冲层150从而改善器件的光学和电性特性，同时这种复合成核层130生长简单、对设备依赖性小，可以用于氮化镓基电子器件和发光器件的外延片大量生产中。
在一些实施例中，参见图3，提供了一种半导体外延结构100，其基本结构和原理及产生的技术效果和上述实施例相同，为简要描述，本实施例部分未提及之处，可参考上述实施例中相应内容。
在本公开实施例中，半导体外延结构100包括衬底110、成核层130、缓冲层150、沟道层170和势垒层190，成核层130位于衬底110的一侧，缓冲层150位于成核层130的一侧，其中，成核层130包括多层周期性掺杂且重复排列的半导体周期叠层，从而使得成核层130形成了具有不同掺杂类型的掺杂超晶格结构。沟道层170位于缓冲层150远离衬底110一侧，势垒层190位于沟道层170远离衬底110的一侧。在本实施例中，成核层130形成在衬底110的表面，其形成过程与形成结构具体可以参考上述实施例，同时缓冲层150形成在成核层130的表面，沟道层170形成在缓冲层150的表面，势垒层190形成在沟道 层170的表面，从而形成了半导体外延结构100，进而有助于形成半导体器件。
在本公开实施例中，衬底110为晶向为(0001)的SiC衬底110，成核层130为周期性掺杂的AlN超晶格结构，缓冲层150为GaN层，沟道层170为高温GaN层，势垒层190为AlGaN层。
本实施例还提供了一种半导体外延结构100的制备方法，与上述实施例相比，所不同之处在于在步骤3后还执行以下步骤：
在步骤3后，即在缓冲层150远离衬底110的一侧生长沟道层170。
具体地，同样可以采用MOCVD(Metal-organic Chemical Vapor Deposition，金属有机化合物化学气相沉积)工艺制备形成沟道层170。
步骤4：在沟道层170远离衬底110的一侧生长势垒层190。
具体地，势垒层190也可以采用MOCVD(Metal-organic Chemical Vapor Deposition，金属有机化合物化学气相沉积)工艺进行制备。
下面对本实施例提供的半导体外延结构100的制备方法的实际工艺步骤进行说明：
步骤11：选择一片晶向为(0001)的碳化硅衬底110，放入金属有机化学气相沉积设备中，在氢气气氛中将衬底110加热到1100℃脱附5min去除衬底110表面的氧化物和缺陷层。
步骤21：在完成步骤11后的衬底110表面生长具有掺杂超晶格结构的AlN成核层130。具体地，该复合AlN成核层130生长包含以下步骤：
首先生长5nm的Si掺杂的AlN层，形成第一薄膜层131，生长条件为：衬底110温度1100℃，TMAl流量300sccm，TMIn流量5sccm，NH3流量为3000sccm，生长时间为1.5min；
然后在第一薄膜层131上生长5nm的Mg掺杂的AlN层，形成第二薄膜层133，生长条件为：衬底110温度1100℃，反应的室压力75mbar，TMAl流量300sccm，Cp2Mg流量300sccm，NH3流量为3000sccm，生长时间为1.5min；
重复12个周期的第一薄膜层131和第二薄膜层133的生长，从而生长总厚度120nm的掺杂超晶格AlN成核层130；
步骤31：在步骤21形成的超晶格AlN成核层130上生长GaN缓冲层150。生长条件为衬底110温度980℃，反应室的压力100mbar，TMGa流量230sccm，NH3流量为1500sccm，生长时间为20min，厚度为1000nm；
步骤41：在步骤31形成的氮化镓缓冲层150上生长高温氮化镓沟道层170，高温GaN沟道层170生长条件为：TMGa流量为200sccm，同时NH3的流量为30000sccm，表面温度为1090℃，生长速率为2um/h，生长时间9min厚度为300nm左右。
步骤51：在步骤41形成的氮化镓沟道层170上继续生长势垒层190。势垒层190的生 长条件为：表面温度为：1080℃，NH3流量为8000sccm。需要说明的是，此处在生长势垒层190之前需要生长AlN插层(图未示)，AlN插层的生长通入TMAl的流量为400sccm，生长时间为16s，厚度为1nm左右；AlGaN势垒层190生长条件为：TMAl400sccm，TMGa180sccm对应的Al组分为25％左右，生长时间为60s厚度为20nm左右；在生长完成势垒层190后，还可以继续生长GaN帽层，GaN帽层的生长时，通入TMGa的流量为150sccm，生长时间为20s，对应GaN帽层的厚度为3nm。
按照上述步骤制备外延片既为SiC衬底110上具有掺杂超晶格成核层130氮化镓基HEMT外延片。
需要说明的是，在实际制备过程中，利用MOCVD(Metal-organic Chemical Vapor Deposition，金属有机化合物化学气相沉积)工艺进行制备是一项十分成熟的工艺，这也进一步降低了超晶格结构的AlN层的制备难度。
在一些实施例中，参见图4，提供了一种半导体外延结构100，其基本结构和原理及产生的技术效果和上述实施例相同，为简要描述，本实施例部分未提及之处，可参考上述实施例中相应内容。
在一些实施例中，半导体外延结构100包括衬底110、成核层130、应力传递层180、缓冲层150、沟道层170和势垒层190，成核层130位于衬底110的一侧，缓冲层150位于成核层130的一侧，其中，成核层130包括多层周期性掺杂且重复排列的半导体周期叠层，从而使得成核层130形成了具有不同掺杂类型的掺杂超晶格结构。应力传递层180位于缓冲层150和成核层130之间，且应力传递层180相对的两侧表面分别与成核层130和缓冲层150相接触。沟道层170位于缓冲层150远离衬底110一侧，势垒层190位于沟道层170远离衬底110的一侧。在本实施例中，成核层130形成在衬底110的表面，其形成过程与形成结构具体可以参考上述实施例，同时应力传递层180形成在成核层130的表面，缓冲层150形成在应力传递层180的表面，沟道层170形成在缓冲层150的表面，势垒层190形成在沟道层170的表面，从而形成了半导体外延结构100，进而有助于形成半导体器件。
在一些实施例中，衬底110选择晶向为(111)的硅衬底110，成核层130为周期性掺杂的AlN超晶格结构，应力传递层180为AlGaN层，缓冲层150为GaN层，沟道层170为高温GaN层，势垒层190为AlGaN层。
本实施例还提供了一种半导体外延结构100的制备方法，用于制备前述的半导体外延结构100，该制备方法包括以下步骤：
S1：在衬底110的一侧生长成核层130。
具体地，此处成核层130的生长过程与前述实施例的过程一致，在此不再赘述。
S2：在成核层130远离衬底110的一侧形成应力传递层180。
具体地，在完成超晶格结构的制备并生长成核层130后，可以在超晶格AlN成核层130上生长AlGaN应力传递层180，该应力传递层180能够起到应力传递的作用，以使得成核层130中周期性的应力变化能够更好地传递。
S3：在应力传递层180远离衬底110的一侧形成缓冲层150。
具体地，缓冲层150可以直接生长在应力传递层180上，生长方式与前述实施例相同，在此不作具体。
S4：在缓冲层150远离衬底110的一侧形成沟道层170。
S5：在沟道层170远离衬底110的一侧形成势垒层190。
其中，沟道层170和势垒层190的生长方式具体可以参考第三实施例。
下面对本实施例提供的半导体外延结构100的制备方法的实际工艺步骤进行说明：
步骤12：选择一片晶向为(111)的硅衬底110放入金属有机化学气相沉积设备中，在氢气气氛中将衬底110加热到1060℃脱附5min去除硅衬底110表面的氧化层。
步骤22：在完成步骤12后的衬底110表面生长具有掺杂超晶格结构的AlN成核层130。该超晶格成核层130生长包含以下步骤：
首先预通有机金属源TMAl。TMAl的预通条件为：衬底110温度1050℃，反应室的压力75mbar，TMAl流量100sccm，预通时间40s；
然后继续生长10nm非掺杂AlN层，以形成第一薄膜层131，生长条件为：衬底110温度1100℃，TMAl流量300sccm，NH3流量为3000sccm，生长时间为3min；
在第一薄膜层131上的AlN层上生长5nm的硅掺杂AlN层，以形成第二薄膜层133，生长条件为：衬底110温度1100℃，反应的室压力75mbar，TMAl流量300sccm，200ppmSiH4/H2流量500sccm，NH3流量为3000sccm，生长时间为1.5min；
重复15个周期的第一薄膜层131和第二薄膜层133的生长，从而生长总厚度225nm的超晶格AlN成核层130；
步骤32：在步骤22形成的超晶格AlN成核层130上生长AlGaN应力传递层180。该应力传递层180包含300nm的Al0.75Ga0.25N层、1000nm的Al0.5Ga0.5N层和1500nm的Al0.2Ga0.8N层，生长温度为1030℃，反应室的压力55mbar，NH3流量为3000sccm。
步骤42：在步骤32形成的应力传递层180上生长GaN缓冲层150，生长条件为衬底110温度980℃，反应室的压力55mbar，TMGa流量230sccm，NH3流量为1500sccm，生长时间为30min，厚度为1500nm；
步骤52：在步骤42形成的氮化镓层上生长高温氮化镓沟道层170。高温GaN沟道层170生长条件为：TMGa流量为200sccm，同时NH3的流量为30000sccm，表面温度为1080℃，生长速率为2um/h，生长时间6min厚度为200nm左右。
步骤62：在GaN沟道层170上继续生长势垒层190。势垒层190的生长条件为：表面温度为：1080℃，NH3流量为8000sccm；其中AlN插层的生长通入TMAl的流量为400sccm，生长时间为16s，厚度为1nm左右；AlGaN势垒层190生长条件为：TMAl200sccm，TMGa200sccm对应的Al组分为20％左右生长时间为80s厚度为25nm左右；而GaN帽层的生长通入TMGa的流量为150sccm生长时间为20s对应GaN帽层的厚度为3nm。
按照上述步骤制备外延片即为Si衬底110上具有掺杂超晶格成核层130氮化镓基HEMT外延片。
本实施例通过增加了应力传递层180，其作用是存储足够的压应力，以平衡硅衬底110上氮化镓基外延薄膜生长结束降温产生的张应力，获得低翘曲的外延片。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种半导体外延结构，其特征在于，包括：
    衬底；
    位于所述衬底一侧的成核层；
    以及位于所述成核层远离所述衬底一侧的缓冲层；
    其中，所述成核层包括多层沿远离所述衬底方向上依次堆叠的半导体周期叠层，且多层所述半导体周期叠层为超晶格结构。
  2. 根据权利要求1所述的半导体外延结构，其特征在于，每层所述半导体周期叠层为沿远离所述衬底方向上依次堆叠的第一薄膜层和第二薄膜层，所述第一薄膜层与所述第二薄膜层的掺杂类型不同。
  3. 根据权利要求2所述的半导体外延结构，其特征在于，所述第一薄膜层掺杂有第一掺杂原子，所述第二薄膜层掺杂有第二掺杂原子，其中，所述第一掺杂原子和所述第二掺杂原子为不同种类的掺杂原子。
  4. 根据权利要求3所述的半导体外延结构，其特征在于，所述第一掺杂原子为In，Ga，Si，Mg和Zn中的至少一种；所述第二掺杂原子为In，Ga，Si，Mg和Zn中的至少一种。
  5. 根据权利要求3所述的半导体外延结构，其特征在于，所述第一掺杂原子在所述第一薄膜层中的掺杂浓度和所述第二掺杂原子在所述第二薄膜层中的掺杂浓度均在1E16/cm3-1E21/cm3之间。
  6. 根据权利要求2所述的半导体外延结构，其特征在于，所述第一薄膜层为非掺杂层，所述第二薄膜层掺杂有第二掺杂原子。
  7. 根据权利要求6所述的半导体外延结构，其特征在于，所述第二掺杂原子为In，Ga，Si，Mg和Zn中的至少一种。
  8. 根据权利要求6所述的半导体外延结构，其特征在于，所述第二掺杂原子在所述第二薄膜层中的掺杂浓度均在1E16/cm3-1E21/cm3之间。
  9. 根据权利要求1所述的半导体外延结构，其特征在于，所述半导体周期叠层的层数大于或等于3。
  10. 根据权利要求1所述的半导体外延结构，其特征在于，所述成核层为掺杂或非掺杂的AlN层。
  11. 根据权利要求1所述的半导体外延结构，其特征在于，所述半导体外延结构还包括：
    位于所述缓冲层和所述成核层之间的应力传递层；
    其中，所述应力传递层相对的两侧表面分别与所述成核层和所述缓冲层相接触。
  12. 根据权利要求1所述的半导体外延结构，其特征在于，所述半导体外延结构还包括：
    位于所述缓冲层远离所述衬底一侧的沟道层；
    以及，位于所述沟道层远离所述衬底一侧的势垒层。
  13. 一种半导体器件，其特征在于，包括：
    衬底；
    位于所述衬底一侧的成核层；
    位于所述成核层远离所述衬底一侧的缓冲层；
    位于所述缓冲层远离所述衬底一侧的电极层；
    其中，所述成核层包括多层沿远离所述衬底方向上依次堆叠的半导体周期叠层，且多层所述半导体周期叠层为超晶格结构。
  14. 根据权利要求13所述的半导体器件，其特征在于，
    每层所述半导体周期叠层为沿远离所述衬底方向上的依次堆叠的第一薄膜层和第二薄膜层，所述第一薄膜层与所述第二薄膜层的掺杂类型不同。
  15. 根据权利要求14所述的半导体器件，其特征在于，所述第一薄膜层掺杂有第一掺杂原子，所述第二薄膜层掺杂有第二掺杂原子，其中，所述第一掺杂原子和所述第二掺杂原子为不同种类的掺杂原子。
  16. 根据权利要求14所述的半导体器件，其特征在于，所述第一薄膜层为非掺杂层，所述第二薄膜层掺杂有第二掺杂原子。
  17. 一种半导体外延结构的制备方法，其特征在于，所述制备方法包括：
    提供一衬底；
    在所述衬底的一侧生长成核层；
    在所述成核层远离所述衬底的一侧生长缓冲层；
    其中，所述成核层包括沿远离所述衬底方向上多层依次堆叠的半导体周期叠层，且多层所述半导体周期叠层为超晶格结构。
  18. 根据权利要求17所述的半导体外延结构的制备方法，其特征在于，在衬底的一侧生长成核层的步骤，包括：
    在所述衬底上生长第一薄膜层；
    在所述第一薄膜层上生长第二薄膜层；
    重复生长所述第一薄膜层和所述第二薄膜层的步骤若干次，得到所述成核层；
    其中，所述第一薄膜层与所述第二薄膜层的掺杂类型不同。
  19. 根据权利要求18所述的半导体外延结构的制备方法，其特征在于，
    所述在所述衬底上生长第一薄膜层，包括：
    在所述第一薄膜层上生长掺杂有第一掺杂原子的所述第一薄膜层；
    所述在所述第一薄膜层生长第二薄膜层，包括：
    在所述第一薄膜层上生长掺杂有第二掺杂原子的所述第二薄膜层；
    其中，所述第一掺杂原子和所述第二掺杂原子为不同种类的掺杂原子。
  20. 根据权利要求18所述的半导体外延结构的制备方法，其特征在于，
    所述在所述衬底上生长第一薄膜层，包括：
    在所述第一薄膜层上生长非掺杂的所述第一薄膜层；
    所述在所述第一薄膜层生长第二薄膜层，包括：
    在所述第一薄膜层上生长掺杂有第二掺杂原子的所述第二薄膜层。
PCT/CN2023/086299 2022-05-30 2023-04-04 半导体外延结构及其制备方法、半导体器件 WO2023231566A1 (zh)

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