WO2023231166A1 - 熔丝电路及熔丝阵列信号传输方法 - Google Patents

熔丝电路及熔丝阵列信号传输方法 Download PDF

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Publication number
WO2023231166A1
WO2023231166A1 PCT/CN2022/108130 CN2022108130W WO2023231166A1 WO 2023231166 A1 WO2023231166 A1 WO 2023231166A1 CN 2022108130 W CN2022108130 W CN 2022108130W WO 2023231166 A1 WO2023231166 A1 WO 2023231166A1
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Prior art keywords
signal
fuse
preset
flop
output
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PCT/CN2022/108130
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English (en)
French (fr)
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季汝敏
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长鑫存储技术有限公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits

Definitions

  • the present disclosure relates to the field of integrated circuits, and in particular, to a fuse circuit and a fuse array signal transmission method.
  • Anti-fuse programmable devices based on Anti-fuse technology are widely used in various types of chips.
  • anti-fuse programmable devices in DRAM (Dynamic Random Access Memory) chips can store data with The defective memory cell address information can be used to achieve redundant replacement (including row replacement and column replacement); it is also possible to program various internal parameters of the chip (such as voltage, current, frequency... ) for precise adjustment.
  • the information stored in the antifuse programmable device will be sent through the built-in transmission circuit and latched where it needs to be used.
  • addressing a fuse unit at a specific address requires the use of multiple chip pins. For example, if the interior of the fuse unit array (cell array) is composed of a 16*16 sub-array, then only the sub-array ) requires a 4-bit row address signal (XADD) and a 4-bit column address signal (YADD), and each row address signal and column address signal needs to be input through the chip pin. If you want to implement the addressing function, you need a sufficient majority Destination chip pin. Since the chip requires a large number of chip pins, it cannot meet the demand for chip miniaturization.
  • the technical problem to be solved by this disclosure is to provide a fuse circuit and a fuse array signal transmission method.
  • the present disclosure provides a fuse circuit, which includes: a fuse unit array that operates the fuse unit array according to the received first enable signal; an address signal generation module and the fuse unit array.
  • the wire unit array is coupled, and N preset signals are input to the address signal generation module in a serial manner and a target signal is output in a parallel manner.
  • the preset signals at least include a fuse row address signal and a fuse column address signal. , to address the preset fuse unit in the fuse unit array.
  • the preset signal further includes a fuse subunit row address signal, a fuse subunit column address signal, and a fuse group address signal.
  • the preset signal further includes a fuse operation mode command signal.
  • the address signal generation module includes a serial-to-parallel conversion module.
  • the serial-to-parallel conversion module includes a shift register with N flip-flops connected in cascade. The first input end of the first-stage flip-flop receives a plurality of The preset signal input in the serial mode is described, and the output terminal of each stage of the flip-flop outputs the intermediate signal correspondingly.
  • the serial-to-parallel conversion module further includes an N+1 flip-flop, forming a cascaded shift register of N+1 flip-flops, and a start signal is provided before the N preset signals.
  • the start signal is input to the first input terminal of the first-stage flip-flop as a first signal, and the first enable signal is correspondingly output through the output terminal of the N+1-th stage flip-flop.
  • the serial-to-parallel conversion module further includes an N+1th flip-flop and an N+2th flip-flop, forming a cascaded shift register of N+2 flip-flops.
  • a start signal is provided before, and the start signal is input to the first input terminal of the first-stage flip-flop as the first signal, and the first enable is correspondingly output through the output terminal of the N+2-th stage flip-flop.
  • signals, N preset signals correspondingly output the intermediate signals through the first to Nth stage flip-flop output terminals.
  • the N+2th level flip-flop includes two cascaded first latches and a second latch, the output terminal of the first latch correspondingly outputs a second enable signal, and the The second latch output terminal correspondingly outputs the first enable signal.
  • the fuse circuit further includes a clock signal generation module that performs logical operations on the shift clock signal and the inversion signal of the second enable signal, and the clock signal The output signal of the generating module is used as the clock signal of the serial-to-parallel conversion module.
  • a reset signal is further included, and the second input terminal of the flip-flop at each stage receives a reset signal to reset the shift register.
  • the start time of the reset signal corresponds to the time of operation of the fuse unit array. After the operation of the fuse unit array is completed, the reset signal is effective and the shift register is reset.
  • the address signal generation module further includes a decoding module.
  • the decoding module includes a plurality of decoding circuits.
  • the decoding circuit decodes the intermediate signal to form the target signal.
  • the fuse circuit is based on The target signal addresses a preset fuse unit in the fuse unit array.
  • a plurality of the decoding circuits selectively receive and decode the intermediate signals according to the sequence of the preset signals, and output a target signal corresponding to the preset signals.
  • the decoding circuit includes a plurality of logic gate circuits, and the logic gate circuits perform logical operations on the intermediate signal and the inverted signal of the intermediate signal to obtain the target signal.
  • the logic gate circuit includes: a first NAND gate circuit, an enable terminal of the first NAND gate circuit receives an enable signal, and a first input terminal of the first NAND gate circuit Receive the first intermediate signal or the inversion signal of the first intermediate signal, and the second input terminal of the first NAND gate circuit receives the second intermediate signal or the inversion signal of the second intermediate signal, and the first NAND gate
  • the output terminal of the circuit outputs a first signal; a second NAND gate circuit, the enable terminal of the second NAND gate circuit receives the enable signal, and the first input terminal of the second NAND gate circuit receives the third Three intermediate signals or the inverted signal of the third intermediate signal, the second input terminal of the second NAND gate circuit receives the fourth intermediate signal or the inverted signal of the fourth intermediate signal, and the second NAND gate circuit
  • the output terminal outputs a second signal; a NOR gate circuit, the first input terminal of the NOR gate circuit receives the first signal, the second input terminal of the NOR gate circuit receives the second signal, and the NOR gate
  • the logic gate circuit further includes an inverter group composed of an even number of inverters connected in series.
  • the output end of the NOR gate circuit is connected to the input end of the inverter group.
  • the inverter group The output signal of the phase group is used as the target signal.
  • An embodiment of the present disclosure also provides a fuse array signal transmission method, which includes: inputting N preset signals in a serial manner and outputting a target signal in a parallel manner, where the preset signals at least include a fuse row address signal and The fuse column address signal is used to address the preset fuse unit in the fuse unit array.
  • the preset signal further includes a fuse operation mode command signal.
  • a start signal is also included.
  • the start signal is input as the first input signal and N preset signals in a serial manner, and a target signal corresponding to the preset signal is output in a parallel manner. and a first enable signal corresponding to the start signal, and the fuse unit array can operate the fuse unit array according to the first enable signal.
  • the method further includes: forming a sensing amplification enable signal corresponding to the startup signal.
  • the method further includes: forming a second enable signal corresponding to the start signal, and performing a logical operation on the shift clock signal and the inverted signal of the second enable signal to form a clock signal for serial-to-parallel conversion.
  • the method further includes: performing a reset operation after completing the operation on the fuse unit array.
  • the fuse circuit and fuse array signal transmission method input the preset signal in a serial manner and output the target signal in a parallel manner, which can realize the input through only one chip pin, greatly reducing the chip cost.
  • the number of pins meets the needs of chip miniaturization.
  • Figure 1 is a schematic diagram of a fuse circuit provided by a first embodiment of the present disclosure
  • Figure 2 is a preset signal table provided by the first embodiment of the present disclosure
  • Figure 3 is a timing diagram of the fuse circuit provided by the first embodiment of the present disclosure.
  • Figure 4 is a circuit diagram of a decoding circuit provided by the first embodiment of the present disclosure.
  • Figure 5 is a circuit schematic diagram of a logic gate circuit provided by the first embodiment of the present disclosure.
  • Figure 6 is a schematic diagram of a fuse circuit provided by a second embodiment of the present disclosure.
  • Figure 7 is a timing diagram of the fuse circuit provided by the second embodiment of the present disclosure.
  • Figure 8 is a schematic diagram of a fuse circuit provided by a second embodiment of the present disclosure.
  • Figure 9 is a timing diagram of the fuse circuit provided by the second embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of the clock signal generation circuit of the fuse circuit provided by the third embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of a fuse circuit provided by a first embodiment of the present disclosure. Please refer to FIG. 1 .
  • the fuse circuit includes a fuse unit array 10 and an address signal generation module 20 .
  • the fuse unit array 10 operates the fuse unit array according to the received first enable signal DRVEN.
  • the address signal generation module 20 is coupled to the fuse unit array 10.
  • the N preset signals are The address signal generation module 20 is input in a serial manner and outputs a target signal in a parallel manner.
  • the preset signal at least includes a fuse row address signal XADD and a fuse column address signal YADD to preset the fuse unit array in The fuse unit 10 provided is addressed.
  • the preset signal of the fuse circuit of the present disclosure is input in a serial manner and the target signal is output in a parallel manner. It can realize input through only one chip pin, greatly reducing the number of chip pins and meeting the requirements of chip miniaturization. need. For example, if the interior of the fuse cell array (cell array) is composed of a 16*16 sub-array, then the sub-array (sub array) requires a 4-bit row address signal (XADD) and a 4-bit column address signal (YADD). If using The fuse circuit of the present disclosure can input row address signals and column address signals in a serial manner and output target signals in a parallel manner, so that multiple row address signals and column address signals can be realized through only one chip pin. input, greatly reducing the number of chip pins and meeting the need for chip miniaturization.
  • the fuse unit array 10 operates the fuse unit array 10 according to the received first enable signal, and the operations include programming operations and read operations.
  • the fuse unit array 10 is composed of a plurality of fuse units arranged in an array form.
  • the fuse unit is composed of an antifuse, and a high voltage is applied between the first end and the second end of the antifuse. The high voltage can breakdown the dielectric layer of the antifuse, causing the The antifuse changes from an insulating state to a conductive state to store information, that is, to program the antifuse.
  • the preset signal includes, in addition to the fuse row address signal XADD and the fuse column address signal YADD, the fuse subunit row address signal XSEG and Fuse subunit column address signal YSEG.
  • the fuse subunit row address signal Different sub arrays of (WL).
  • the fuse unit array 10 can be divided into different groups (split) as needed. For example, fuse units with different sizes are grouped into one group, and the sizes of the fuse units in different groups are different. , the group address signal ZADD can be used to distinguish different groups.
  • Figure 2 is a preset signal table, in which the preset signals A0 ⁇ A3 represent the fuse row address signals XADD ⁇ 3:0>, and the preset signals A4 ⁇ A7 represent the fuse subunit row address signals XSEG ⁇ 3:0>, the preset signals A8 ⁇ A11 represent the fuse column address signal YADD ⁇ 3:0>, the preset signals A12 ⁇ A15 represent the fuse subunit column address signal YSEG ⁇ 3:0>, the preset signal A16 ⁇ A19 represent the fuse group address signal ZADD ⁇ 3:0>.
  • the controller can determine what operation to perform on the fuse unit array 10 according to the fuse operation mode command signal MODE, such as a programming or read operation. For example, when the fuse operation mode command signal MODE is at a high level, it indicates that the fuse unit array is programmed. When the fuse operation mode command signal MODE is at a low level, it indicates that the fuse unit array is programmed. Read operation. It can be understood that in other embodiments, when the fuse operation mode command signal MODE is high level, it indicates that the read operation is performed on the fuse unit array, and when the fuse operation mode command signal MODE is low level, it indicates that the fuse unit array is read. Normally, programming is performed on the fuse unit array.
  • the preset signal further includes the fuse operation mode command signal MODE.
  • the preset signal A20 represents the fuse operation mode command signal MODE.
  • the fuse operation mode command signal MODE is input to the address signal generation module 20 in a serial manner, and a target signal is output in a parallel manner to address and operate the preset fuse unit 10 in the fuse unit array.
  • the number of the preset signals is N.
  • the preset signals include A0 to A20, a total of 21, that is, N is 21.
  • the preset signal may also include other signals, and the number of the preset signals is determined according to the actual situation.
  • the address signal generation module 20 includes a serial-to-parallel conversion module 21.
  • the serial-to-parallel conversion module 21 receives a plurality of the serial-to-parallel conversion modules. Preset signal input in parallel mode and output parallel intermediate signal.
  • the serial-to-parallel conversion module 21 includes a shift register with N flip-flops connected in cascade. The first input end of the first-stage flip-flop receives a plurality of preset signals input in a serial manner. The output of each stage of the flip-flop is The terminal corresponds to outputting the intermediate signal.
  • the number of cascades of the flip-flops is the same as the number of the preset signals, which are both N.
  • the number of the preset signals is 21, and the number of the flip-flops is also 21, that is, the flip-flops D0 to D20 .
  • the first input terminal of the first-stage flip-flop D0 receives a plurality of preset signals A0 ⁇ A20 input in a serial manner, and the output terminals of the flip-flops D0 ⁇ D20 correspondingly output intermediate signals Q0 ⁇ Q20.
  • the intermediate signals Q0 to Q20 are parallel signals.
  • the preset signal only includes a fuse row address signal and a fuse column address signal.
  • the number of the preset signals is 8, so the cascade number of the flip-flops is There are also 8.
  • FIG 3 is a timing diagram of the fuse circuit provided by the first embodiment of the present disclosure. Please refer to Figures 1 and 3.
  • the preset signals A0 ⁇ A20 are sequentially input to the first signal in a serial manner.
  • the first input terminal of the first-stage flip-flop D0 wherein, at time T0, the preset signal A20 is input to the first input terminal of the first-stage flip-flop D0; at time T1, the preset signal A19 is input to the first-stage flip-flop
  • the preset signal A20 forms an intermediate signal Q0 through the output terminal of the first-stage flip-flop D0; at time T2, the preset signal A18 is input to the first input terminal of the first-stage flip-flop D0.
  • the signal A19 passes through the output terminal of the first-stage flip-flop D0 to form an intermediate signal Q0
  • the preset signal A20 passes through the output terminal of the second-stage flip-flop D1 to form an intermediate signal Q1.
  • the preset signals A1 to A20 are sequentially shifted to the right bit by bit, and intermediate signals Q0 to Q20 are correspondingly output from the output terminals of each stage of the flip-flop.
  • the intermediate signal Q0 output by the output terminal of the first-stage flip-flop D0 corresponds to the preset signal A0
  • the intermediate signal Q1 output by the output terminal of the second-stage flip-flop D1 corresponds to the preset signal A1, and so on.
  • the intermediate signal Q20 output by the output terminal of the twenty-first-stage flip-flop D20 corresponds to the preset signal A20. Wherein, it can be determined according to the intermediate signal Q20 output corresponding to the preset signal A20 whether to perform a programming or a read operation on the fuse cell array.
  • the shift clock signal CLK and the clock enable signal CLKEN are used as the clock signal of the serial-to-parallel conversion module 21 after an AND logic operation.
  • the fuse circuit further includes a reset signal RST, and the second input terminal of the flip-flop of each stage receives the reset signal RST to reset, thereby realizing the reset of the shift register. reset.
  • RST reset signal
  • the reset signal RST becomes high level
  • each flip-flop is reset.
  • the reset signal RST becomes low level.
  • the start time of the reset signal RST corresponds to the time of the fuse unit array operation, for example, programming or read operation.
  • the The reset signal RST resets the shift register.
  • the reset signal RST changes from low level to high level to reset the shift register. Therefore, in the fuse circuit of the present disclosure, the reset signal RST can be used to control the timing of programming or reading operations on the fuse unit array 10. For example, after completing the programming of an anti-fuse unit, the reset signal RST is inserted. Reset to end the current programming operation and allow programming of another antifuse unit. Similarly, after completing the read operation of one anti-fuse unit, the reset signal RST is inserted to reset to end the current read operation, and the read operation of another anti-fuse unit can be performed.
  • the address signal generation module 20 further includes a decoding module 22 for decoding the intermediate signal to form a target signal.
  • the decoding module 22 includes a plurality of decoding circuits 220, and each decoding circuit 220 decodes the intermediate signal to form the target signal.
  • the fuse circuit addresses the preset fuse unit in the fuse unit array 10 according to the target signal.
  • a plurality of the decoding circuits 220 selectively receive and decode the intermediate signals according to the sequence of the preset signals, and output a target signal corresponding to the preset signals. That is, the plurality of decoding circuits 220 sequentially acquire one or several of the intermediate signals according to the order of the preset signals A0 to A20, and output a target signal corresponding to the preset signal.
  • the first decoding circuit 220 receives the intermediate signals Q0 ⁇ Q3 corresponding to the preset signals A0 ⁇ A3, and decodes the four-bit fuse row address signal XADD ⁇ 3:0> into the corresponding 16 bit fuse row address signal > Decoded into the corresponding 16-bit fuse subunit row address signal The address signal YADD ⁇ 3:0> is decoded into the corresponding 16-bit fuse column address signal YADD ⁇ 15:0>.
  • the fourth decoding circuit 220 receives the intermediate signals Q12 ⁇ Q15 corresponding to the preset signals A12 ⁇ A15, and The four-bit fuse subunit column address signal YSEG ⁇ 3:0> is decoded into the corresponding 16-bit fuse subunit column address signal YSEG ⁇ 15:0>, and the fifth decoding circuit 220 receives the preset signals A16 ⁇ A19 The corresponding intermediate signals Q16 ⁇ Q19 decode the four-bit fuse group address signal ZADD ⁇ 3:0> into the corresponding 16-bit fuse group address signal ZADD ⁇ 15:0>.
  • the fuse circuit is configured according to the 16-bit fuse row address signal XADD ⁇ 15:0>, the fuse subunit row address signal XSEG ⁇ 15:0>, the fuse column address signal YADD ⁇ 15:0>, and the fuse subunit
  • the column address signal YSEG ⁇ 15:0> and the fuse group address signal ZADD ⁇ 15:0> address the preset fuse unit in the fuse unit array 10 .
  • the preset signal only includes the fuse row address signal XADD ⁇ 3:0> and the fuse column address signal YADD ⁇ 3:0>
  • the plurality of decoding circuits 220 Receive the intermediate signal corresponding to the preset signal, decode the four-bit fuse row address signal XADD ⁇ 3:0> into the corresponding 16-bit fuse row address signal XADD ⁇ 15:0>, and decode the four-bit fuse row address signal YADD ⁇ 3:0> is decoded into the corresponding 16-bit fuse row address signal YADD ⁇ 15:0>.
  • the fuse circuit is based on the 16-bit fuse row address signal XADD ⁇ 15:0> and the fuse column address signal YADD. ⁇ 15:0> Address the preset fuse unit in the fuse unit array 10 .
  • an embodiment of the present disclosure also provides the decoding circuit 220.
  • Figure 4 is a circuit diagram of the decoding circuit 220 provided by the first embodiment of the present disclosure.
  • the decoding circuit is used to decode the four-bit signal ADDR ⁇ 3:0> into the corresponding 16-bit signal ADDR ⁇ 15:0>. .
  • the four-bit signal ADDR ⁇ 3:0> is used as the input signal of the decoding circuit, which can represent the four-bit fuse row address signal XADD ⁇ 3:0>, the four-bit fuse subunit row address signal XSEG ⁇ 3:0>, Four-bit fuse column address signal YADD ⁇ 3:0>, four-bit fuse subunit column address signal YSEG ⁇ 3:0> and four-bit fuse group address signal ZADD ⁇ 3:0>, 16-bit signal ADDR ⁇ 15 :0> as the output signal of the decoding circuit, that is, the target signal, which can represent the 16-bit fuse row address signal XADD ⁇ 15:0>, the 16-bit fuse subunit row address signal XSEG ⁇ 15:0>, 16 The bit fuse column address signal YADD ⁇ 15:0>, the 16-bit fuse subunit column address signal YSEG ⁇ 15:0>, and the 16-bit fuse group address signal ZADD ⁇ 15:0>.
  • the decoding circuit 220 includes a plurality of logic gate circuits. Each of the logic gate circuits performs a logical operation on the intermediate signal and the inverted signal of the intermediate signal to obtain the target signal. That is, the intermediate signal and the inverted signal of the intermediate signal are used as the input signal of the logic gate circuit, and the output signal of the logic gate circuit is the target signal.
  • FIG. 5 is a schematic circuit diagram of a logic gate circuit. Please refer to FIG. 5 .
  • the logic gate circuit includes a first NAND gate circuit NAND_1, a second NAND gate circuit NAND_2 and a NOR gate circuit NOR.
  • the enable terminal of the first NAND gate circuit NAND_1 receives the enable signal EN, and the first input terminal of the first NAND gate circuit NAND_1 receives the first intermediate signal A ⁇ 0> or the inversion of the first intermediate signal. signal AN ⁇ 0>, the second input terminal of the first NAND gate circuit NAND_1 receives the second intermediate signal A ⁇ 1> or the inverted signal AN ⁇ 1> of the second intermediate signal, the first NAND gate
  • the output terminal of the circuit outputs the first signal out1.
  • the second NAND gate circuit NAND_2 is connected in parallel with the first NAND gate circuit NAND_1.
  • the enable terminal of the second NAND gate circuit NAND_2 receives the enable signal EN.
  • the second NAND gate circuit NAND_2 is connected in parallel with the first NAND gate circuit NAND_1.
  • the first input terminal of NAND_2 receives the third intermediate signal A ⁇ 2> or the inverted signal AN ⁇ 2> of the third intermediate signal
  • the second input terminal of the second NAND gate circuit NAND_2 receives the fourth intermediate signal A ⁇ 3> or the inverted signal AN ⁇ 3> of the fourth intermediate signal
  • the output terminal of the second NAND gate circuit NAND_2 outputs the second signal out2.
  • the first input terminal of the NOR gate circuit NOR receives the first signal out1, the second input terminal of the NOR gate circuit NOR receives the second signal out2, and the output terminal of the NOR gate circuit NOR outputs the Describe the target signal ADDR ⁇ N>.
  • the four-bit signal ADDR ⁇ 3:0> serves as the input signal of the decoding circuit, which provides the first intermediate signal A ⁇ 0>, the second intermediate signal A ⁇ 1>, and the third intermediate signal A ⁇ 2 > and the fourth intermediate signal A ⁇ 3>.
  • the enable terminal of the first NAND gate circuit NAND_1 receives the enable signal EN
  • the first input terminal of the first NAND gate circuit NAND_1 receives the first The inverted signal AN ⁇ 0> of the intermediate signal
  • the second input terminal of the first NAND gate circuit NAND_1 receives the inverted signal AN ⁇ 1> of the second intermediate signal
  • the enable terminal of the second NAND gate circuit NAND_2 receives the enable signal EN, and the first input terminal of the second NAND gate circuit NAND_2 receives the inverted signal AN ⁇ 2> of the third intermediate signal, so The second input terminal of the second NAND gate circuit NAND_2 receives the inverted signal AN ⁇ 3> of the fourth intermediate signal, and the output terminal of the second NAND gate circuit NAND_2 outputs the second signal out2.
  • the first input terminal of the NOR gate circuit NOR receives the first signal out1, the second input terminal of the NOR gate circuit NOR receives the second signal out2, and the output terminal of the NOR gate circuit NOR outputs the Describe the target signal ADDR ⁇ 0>.
  • the enable terminal of the first NAND gate circuit NAND_1 receives the enable signal EN
  • the first input terminal of the first NAND gate circuit NAND_1 receives the first Intermediate signal A ⁇ 0>
  • the second input terminal of the first NAND gate circuit NAND_1 receives the inverted signal AN ⁇ 1> of the second intermediate signal
  • the output terminal of the first NAND gate circuit outputs the first signal out1.
  • the enable terminal of the second NAND gate circuit NAND_2 receives the enable signal EN, and the first input terminal of the second NAND gate circuit NAND_2 receives the inverted signal AN ⁇ 2> of the third intermediate signal, so The second input terminal of the second NAND gate circuit NAND_2 receives the inverted signal AN ⁇ 3> of the fourth intermediate signal, and the output terminal of the second NAND gate circuit NAND_2 outputs the second signal out2.
  • the first input terminal of the NOR gate circuit NOR receives the first signal out1, the second input terminal of the NOR gate circuit NOR receives the second signal out2, and the output terminal of the NOR gate circuit NOR outputs the Describe the target signal ADDR ⁇ 1>.
  • the first intermediate signal, the second intermediate signal, the third intermediate signal, the fourth intermediate signal and the inverted signals of the four intermediate signals provided by the four-bit signal ADDR ⁇ 3:0> are combined as a logic
  • the input signal of the gate circuit achieves the purpose of decoding the four-bit signal ADDR ⁇ 3:0> into the corresponding 16-bit signal ADDR ⁇ 15:0>.
  • the logic gate circuit further includes an inverter group composed of an even number of inverters connected in series, and the output end of the NOR gate circuit is connected to the input end of the inverter group to control all the inverters.
  • the output signal of the NOR gate circuit is buffered to improve the stability of the target signal.
  • the logic gate circuit also includes a first inverter group P1 composed of an even number of inverters connected in series. The output end of the NOR gate circuit NOR is connected to the first inverter group P1.
  • the input terminal of the inverter group P1, the output signal of the NOR gate circuit NOR is used as the input signal of the first inverter group P1, and the output signal of the first inverter group P1 is used as the target signal ADDR ⁇ N>.
  • the first inverter group P1 includes two series-connected inverters, namely an inverter P11 and an inverter P12.
  • the output signal of the output terminal of the NOR gate circuit NOR is used as the The input signal of the inverter P11 is used as the input signal of the inverter P11, the output signal of the inverter P12 is used as the input signal of the inverter P12, and the output signal of the inverter P12 is used as the target signal ADDR ⁇ N>.
  • decoding circuits with other structures may also be used to decode the intermediate signals of the disclosure, and the disclosure is not limited thereto.
  • the fuse circuit provided by the first embodiment of the present disclosure uses a serial-to-parallel conversion module and a decoding circuit to convert a preset signal input in a serial manner into a parallel output target signal, so that the preset signal only passes through one chip pin. input, greatly reducing the number of chip pins and meeting the need for chip miniaturization.
  • the number of the preset signals is N
  • the serial-to-parallel conversion module includes N flip-flop cascaded shift registers.
  • the serial-to-parallel conversion module It also includes an N+1th flip-flop, forming an N+1 bit shift register of N+1 flip-flops cascade.
  • a start signal is set before the N preset signals, and the start signal serves as the first The signal is input to the first input terminal of the first-stage flip-flop, and the first enable signal is correspondingly output through the output terminal of the N+1-th stage flip-flop.
  • FIG. 6 is a schematic diagram of a fuse circuit provided by the second embodiment of the present disclosure.
  • the serial-to-parallel conversion module 21 also includes an N+th One flip-flop, that is, the twenty-second-level flip-flop D21, and N+1 flip-flops constitute an N+1-bit shift register.
  • a start signal start is provided before the N preset signals. The start signal start is input as the first signal to the first input end of the first-stage flip-flop D0 and passes through the twenty-second-stage flip-flop.
  • the output terminal of D21 corresponds to outputting the first enable signal DRVEN.
  • the first enable signal DRVEN can also be used as an input signal of the decoding module 22 , and the decoding module 22 determines the operation mode of the fuse unit array 10 according to the first enable signal DRVEN.
  • the operation mode includes programming or read operations.
  • Figure 7 is a timing diagram of the fuse circuit provided by the second embodiment of the present disclosure. Please refer to Figures 6 and 7.
  • the start signal start and the preset signals A0 ⁇ A20 are connected in a serial manner. Input to the first input terminal of the first-stage flip-flop D0 in turn, wherein, at Ts time, the start signal start is input to the first input terminal of the first-stage flip-flop D0; at T0 time, the preset signal A20 is input to the first The first input terminal of the first-stage flip-flop D0, the start signal start forms the intermediate signal Q0 through the output terminal of the first-stage flip-flop D0; at time T1, the preset signal A19 is input to the first input terminal of the first-stage flip-flop D0 , the preset signal A20 forms an intermediate signal Q0 through the output terminal of the first-stage flip-flop D0, and the start signal start forms an intermediate signal Q1 through the output terminal of the second-stage flip-flop D1; at time T2, the
  • the intermediate signal Q0 output by the output terminal of the first-stage flip-flop D0 corresponds to the preset signal A0
  • the intermediate signal Q1 output by the output terminal of the second-stage flip-flop D1 corresponds to the preset signal A1, and so on.
  • the intermediate signal Q20 output by the output terminal of the twenty-first-stage flip-flop D20 corresponds to the preset signal A20
  • the intermediate signal Q21 output by the output terminal of the twenty-second-stage flip-flop D21 corresponds to the start signal start.
  • the start signal start and the preset signal are input in a serial manner and output in a parallel manner, wherein the start signal start corresponds to the output of the first enable signal DRVEN, so that It can avoid using a separate chip pin input for the start signal start, further reducing the number of chip pins.
  • the shift clock signal CLK and the clock enable signal CLKEN are used as the clock signal of the serial-to-parallel conversion module 21 after an AND logic operation.
  • the number of the preset signals is N
  • the serial-to-parallel conversion module includes N+1 flip-flop cascaded shift registers.
  • the serial-to-parallel conversion module The conversion module 22 not only includes the N+1-th flip-flop, but also includes the N+2-th flip-flop, constituting an N+2-bit shift register in which N+2 flip-flops are cascaded.
  • a start signal is provided before the N preset signals. The start signal is input as the first signal to the first input terminal of the first-stage flip-flop and passes through the output terminal of the N+2-th stage flip-flop.
  • the first enable signal is output, and the N preset signals are correspondingly outputted to the intermediate signal through the first stage to the Nth stage flip-flop output terminals.
  • FIG. 8 is a schematic diagram of a fuse circuit provided by the third embodiment of the present disclosure.
  • the serial-to-parallel conversion module 22 not only includes the N+th 1 flip-flop, that is, the 22nd-level flip-flop D21, also includes the N+2 flip-flop D22, that is, the 23rd-level flip-flop D22, N+2 flip-flops are cascaded to form N+2 displacement bit register.
  • a start signal start is provided before the N preset signals. The start signal start is input as the first signal to the first input end of the first-level flip-flop D0 and passes through the twenty-third level flip-flop.
  • the output terminal of D22 correspondingly outputs the first enable signal DRVEN, and the N preset signals correspondingly output the intermediate signal through the output terminals of the first to Nth stage flip-flops.
  • the output terminal of the twenty-second-level flip-flop D21 does not output an intermediate signal, and the twenty-second-level flip-flop D21 and the twenty-third-level flip-flop D22 work together to make the The delayed output of the start signal start forms the first enable signal DRVEN, which improves the stability of signal transmission.
  • the twenty-third level flip-flop D22 includes two cascaded first latches (not shown in the drawings) and second latches (not shown in the drawings), so The first latch output terminal correspondingly outputs the second enable signal Q22_05.
  • the second enable signal Q22_05 serves as the sensing amplification enable signal SAEN, and the second latch output terminal correspondingly outputs the first enable signal DRVEN.
  • the sensing amplification enable signal SAEN is used to enable the sensing circuit (not shown in the drawing) in the fuse circuit, and the sensing circuit is used to detect the information stored in the fuse unit in the read operation mode. and judgment.
  • Figure 9 is a timing diagram of the fuse circuit provided by the third embodiment of the present disclosure.
  • the start signal start and the preset signals A0 ⁇ A20 are connected in a serial manner. Input to the first input terminal of the first-stage flip-flop D0 in turn, wherein, at Ts time, the start signal start is input to the first input terminal of the first-stage flip-flop D0; at T0 time, the preset signal A20 is input to the first The first input terminal of the first-stage flip-flop D0, the start signal start forms the intermediate signal Q0 through the output terminal of the first-stage flip-flop D0; at time T1, the preset signal A19 is input to the first input terminal of the first-stage flip-flop D0 , the preset signal A20 forms an intermediate signal Q0 through the output terminal of the first-stage flip-flop D0, and the start signal start forms an intermediate signal Q1 through the output terminal of the second-stage flip-flop D1; at time T2, the preset signal A18 is input to The first input terminal of the first-stage flip-flop D
  • the intermediate signal Q0 output by the output terminal of the first-stage flip-flop D0 corresponds to the preset signal A0
  • the intermediate signal Q1 output by the output terminal of the second-stage flip-flop D1 corresponds to the preset signal A1, and so on.
  • the intermediate signal Q20 output by the output terminal of the twenty-first-stage flip-flop D20 corresponds to the preset signal A20
  • the output signal of the twenty-second-stage flip-flop D21 corresponds to the start signal start, and serves as the twenty-third stage flip-flop D22 input signal
  • the twenty-third-level flip-flop D22 outputs the first enable signal DRVEN and the sensing amplification enable signal SAEN
  • the fuse unit array responds to the first enable signal DRVEN
  • the sensing amplification enable signal SAEN enables the sensing circuit in the fuse circuit.
  • the fuse circuit uses the N+2 flip-flop to implement delayed output of the start signal to ensure the stability of signal transmission.
  • the shift clock signal CLK and the clock enable signal CLKEN are subjected to an AND logic operation to form a clock signal CLKout.
  • the clock signal CLKout serves as the clock signal for the first-stage flip-flop D0 to the twenty-second-stage flip-flop D21
  • the shift clock signal CLK alone serves as the clock signal of the twenty-third-stage flip-flop D22, so that the output of the first enable signal is not affected by the clock enable signal CLKEN.
  • the second enable signal Q22_05 is inverted and used as the clock enable signal CLKEN.
  • the fuse circuit further includes a clock signal generation module that performs logical operations on the shift clock signal CLK and the clock enable signal CLKEN.
  • the clock signal generation module The clock signal CLKout output by the module is used as the clock signal of the serial-to-parallel conversion module 21 .
  • the clock signal generation module includes a third NAND gate circuit NAND_3 and a second inverter group P2.
  • the output terminal of the third NAND gate circuit NAND_3 is connected to the input terminal of the second inverter group P2.
  • the clock signal CLKout output by the output terminal of the second inverter group P2 is used as the clock signal CLKout of the serial-to-parallel conversion module 21. clock signal.
  • the second inverter group P2 is composed of an odd number of inverters connected in series.
  • the second inverter group P2 is composed of inverters P21, P22 and P23 connected in series.
  • the shift clock signal CLK is used as the input signal of the first input terminal of the third NAND gate circuit NAND_3, and the second enable signal Q22_05 is inverted by the inverter P31 to form the clock enable signal CLKEN, so
  • the clock enable signal CLKEN is used as the input signal of the second input terminal of the third NAND gate circuit NAND_3, and the third NAND gate circuit NAND_3 performs NAND logic on the shift clock signal CLK and the clock enable signal CLKEN. operation, and the output signal is used as the input signal of the second inverter group P2.
  • the second inverter group P2 inverts the input signal and outputs a clock signal CLKout.
  • the clock signal CLKout serves as the clock signal of the serial-to-parallel conversion module 21 .
  • the clock signal CLKout output by the clock signal generating circuit is low level, that is, the serial-to-parallel conversion module 21
  • the clock signal becomes low level the clock signal of the serial-to-parallel conversion module 21 is invalid;
  • the second enable signal Q22_05 is low level, the clock enable signal CLKEN is high level, then the clock signal is generated
  • the clock signal CLKout output by the circuit is high level, that is, the clock signal of the serial-to-parallel conversion module 21 becomes high level, and the clock signal of the serial-to-parallel conversion module 21 is valid.
  • the preset signal of the fuse circuit of the present disclosure is input in a serial manner and the target signal is output in a parallel manner. It can realize input through only one chip pin, greatly reducing the number of chip pins and meeting the requirements of chip miniaturization. need.
  • the present disclosure also provides a fuse array signal transmission method, which uses the above-mentioned fuse circuit.
  • the method includes: inputting N preset signals in a serial manner and outputting a target signal in a parallel manner, the preset signals at least include a fuse row address signal and a fuse column address signal to control the fuse unit array in the fuse unit array. Preset fuse units are addressed.
  • the fuse array signal transmission method of the present disclosure inputs the preset signal in a serial manner and outputs the target signal in a parallel manner. It can realize the input through only one chip pin, greatly reducing the number of chip pins and meeting the requirements of the chip. The need for miniaturization.
  • the preset signal further includes a fuse operation mode command signal. That is, the fuse operation mode command signal and the fuse row address signal and fuse column address signal are input from the same chip pin, which greatly reduces the number of chip pins and meets the need for chip miniaturization.
  • a start signal is also included.
  • the start signal is input as the first input signal and N preset signals in a serial manner, and a target signal corresponding to the preset signal is output in a parallel manner. and a first enable signal corresponding to the start signal, and the fuse unit array can operate the fuse unit array according to the first enable signal. If the start signal and the preset signal are input in a serial manner, they can use the same chip pin, which greatly reduces the number of chip pins and meets the need for chip miniaturization.
  • the method further includes forming a sensing amplification enable signal corresponding to the startup signal.
  • the sensing amplification enable signal SAEN is used to enable the sensing circuit (not shown in the drawing) in the fuse circuit, and the sensing circuit is used to detect the information stored in the fuse unit in the read operation mode. and judgment.
  • the method further includes forming a second enable signal corresponding to the start signal. And logical operations are performed on the shift clock signal and the inverted signal of the second enable signal to form a clock signal for serial-to-parallel conversion.
  • the N preset signals are input in a serial manner according to the clock signal, and a target signal is output in a parallel manner.
  • the method further includes: performing a reset operation after ending the programming or reading operation on the fuse cell array.
  • a reset signal is inserted to perform a reset operation.
  • the reset signal changes from low level to high level to perform the reset operation.
  • the period of the reset signal can be used to control the time of programming or reading operations on the fuse cell array.
  • a reset signal is inserted for reset to end the current programming operation.
  • another antifuse unit can be programmed.
  • a reset signal is inserted to reset to end the current read operation, and the read operation of another anti-fuse unit can be performed.

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Abstract

本公开实施例提供一种熔丝电路，其包括：熔丝单元阵列，根据接收的第一使能信号对所述熔丝单元阵列进行操作；地址信号产生模块，与所述熔丝单元阵列耦接，N个预设信号以串行方式输入至所述地址信号产生模块，并以并行方式输出目标信号，所述预设信号至少包括熔丝行地址信号和熔丝列地址信号，以对熔丝单元阵列中预设的熔丝单元进行寻址。本公开实施例提供的熔丝电路及熔丝阵列信号传输方法将预设信号以串行方式输入，并以并行方式输出目标信号，其能够仅通过一个芯片管脚就实现输入，大大减少了芯片管脚的数量，满足了芯片小型化的需求。

Description

熔丝电路及熔丝阵列信号传输方法
相关申请引用说明
本申请要求于2022年06月01日递交的中国专利申请号202210616372.1、申请名为“熔丝电路及熔丝阵列信号传输方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及集成电路领域，尤其涉及一种熔丝电路及熔丝阵列信号传输方法。
背景技术
基于Anti-fuse(反熔丝)技术的一次可编程器件被广泛应用于各类芯片中，例如DRAM(Dynamic Random Access Memory，动态随机存取存储器)芯片中利用反熔丝可编程器件可以存储具有缺陷的存储单元地址信息，进而实现冗余替换(包括行替换和列替换)；也可以通过对反熔丝可编程器件进行编程，进而实现对芯片内部各种参数(例如电压、电流、频率…)的精确修调。在芯片上电启动时，反熔丝可编程器件中存储的信息会通过内置的传输电路进行发送并锁存在需要用到的地方。
目前，对特定地址的熔丝单元寻址需要用到多个芯片管脚，例如若熔丝单元阵列(cell array)的内部由16*16的子阵列构成的话，那么仅仅是子阵列(sub array)就需要4bit的行地址信号(XADD)和4bit的列地址信号(YADD)，而每个行地址信号与列地址信号均需要通过芯片管脚输入，则若要实现寻址功能，需要足够多数目的芯片管脚。由于芯片需要设置数量庞大的芯片管脚，则无法满足芯片小型化的需求。
发明内容
本公开所要解决的技术问题是，提供一种熔丝电路及熔丝阵列信号传输方法。
为了解决上述问题，本公开提供了一种熔丝电路，其包括：熔丝单元阵列，根据接收的第一使能信号对所述熔丝单元阵列进行操作；地址信号产生模块，与所述熔丝单元阵列耦接，N个预设信号以串行方式输入至所述地址信号产生模块，并以并行方式输出目标信号，所述预设信号至少包括熔丝行地址信号和熔丝列地址信号，以对熔丝单元阵列中预设的熔丝单元进行寻址。
在一实施例中，所述预设信号还包括熔丝子单元行地址信号、熔丝子单元列地址信号、熔丝分组地址信号。
在一实施例中，所述预设信号还包括熔丝操作模式命令信号。
在一实施例中，所述地址信号产生模块包括串并转换模块，所述串并转换模块包括N 个触发器级联的移位寄存器，第一级触发器的第一输入端接收多个所述串行方式输入的预设信号，每一级触发器的输出端对应输出中间信号。
在一实施例中，所述串并转换模块还包括第N+1个触发器，构成N+1个触发器级联的移位寄存器，在N个所述预设信号之前设置有启动信号，所述启动信号作为第一个信号输入至所述第一级触发器的第一输入端，并经第N+1级触发器的输出端对应输出所述第一使能信号。
在一实施例中，所述串并转换模块还包括第N+1个及第N+2个触发器，构成N+2个触发器级联的移位寄存器，在N个所述预设信号之前设置有启动信号，所述启动信号作为第一个信号输入至所述第一级触发器的第一输入端，并经第N+2级触发器的输出端对应输出所述第一使能信号，N个所述预设信号经第一级至第N级触发器输出端对应输出所述中间信号。
在一实施例中，第N+2级触发器包括两个级联的第一锁存器及第二锁存器，所述第一锁存器输出端对应输出第二使能信号，所述第二锁存器输出端对应输出所述第一使能信号。
在一实施例中，所述熔丝电路还包括时钟信号产生模块，所述时钟信号产生模块对移位时钟信号及所述第二使能信号的取反信号进行逻辑运算，且所述时钟信号产生模块的输出信号作为所述串并转换模块的时钟信号。
在一实施例中，还包括复位信号，每一级所述触发器的第二输入端均接收复位信号，以对所述移位寄存器进行复位。
在一实施例中，所述复位信号的开始时间与所述熔丝单元阵列操作的时间对应，当结束对熔丝单元阵列的操作后，所述复位信号有效，复位所述移位寄存器。
在一实施例中，所述地址信号产生模块还包括解码模块，所述解码模块包括多个解码电路，所述解码电路对所述中间信号解码，形成所述目标信号，所述熔丝电路根据所述目标信号对所述熔丝单元阵列中预设的熔丝单元进行寻址。
在一实施例中，多个所述解码电路根据所述预设信号的排序对所述中间信号进行选择性接收及解码，并输出与所述预设信号对应的目标信号。
在一实施例中，所述解码电路包括多个逻辑门电路，所述逻辑门电路对所述中间信号及所述中间信号的取反信号进行逻辑运算，获得所述目标信号。
在一实施例中，所述逻辑门电路包括：第一与非门电路，所述第一与非门电路的使能端接收使能信号，所述第一与非门电路的第一输入端接收第一中间信号或者第一中间信号 的取反信号，所述第一与非门电路的第二输入端接收第二中间信号或者第二中间信号的取反信号，所述第一与非门电路的输出端输出第一信号；第二与非门电路，所述第二与非门电路的使能端接收所述使能信号，所述第二与非门电路的第一输入端接收第三中间信号或者第三中间信号的取反信号，所述第二与非门电路的第二输入端接收第四中间信号或者第四中间信号的取反信号，所述第二与非门电路的输出端输出第二信号；或非门电路，所述或非门电路的第一输入端接收所述第一信号，所述或非门电路的第二输入端接收第二信号，所述或非门电路的输出端输出所述目标信号。
在一实施例中，所述逻辑门电路还包括偶数个反相器串联而成的反相器组，所述或非门电路的输出端连接所述反相器组的输入端，所述反相器组的输出信号作为所述目标信号。
本公开实施例还提供一种熔丝阵列信号传输方法，其包括：N个预设信号以串行方式输入，并以并行方式输出目标信号，所述预设信号至少包括熔丝行地址信号和熔丝列地址信号，以对熔丝单元阵列中预设的熔丝单元进行寻址。
在一实施例中，所述预设信号还包括熔丝操作模式命令信号。
在一实施例中，还包括启动信号，所述启动信号作为第一个输入信号与N个所述预设信号以串行方式输入，并以并行方式输出与所述预设信号对应的目标信号及与所述启动信号对应的第一使能信号，熔丝单元阵列能够根据所述第一使能信号对所述熔丝单元阵列进行操作。
在一实施例中，所述方法还包括：形成与所述启动信号对应的感测放大使能信号。
在一实施例中，所述方法还包括：形成与所述启动信号对应的第二使能信号，并对移位时钟信号及所述第二使能信号的取反信号进行逻辑运算，形成用于串并转换的时钟信号。
在一实施例中，所述方法还包括：在结束对熔丝单元阵列的操作后，执行复位操作。
本公开实施例提供的熔丝电路及熔丝阵列信号传输方法将预设信号以串行方式输入，并以并行方式输出目标信号，其能够仅通过一个芯片管脚就实现输入，大大减少了芯片管脚的数量，满足了芯片小型化的需求。
附图说明
图1是本公开第一实施例提供的熔丝电路的示意图；
图2是本公开第一实施例提供的预设信号表格；
图3是本公开第一实施例提供的熔丝电路的时序图；
图4是本公开第一实施例提供的解码电路的电路图；
图5是本公开第一实施例提供的逻辑门电路的电路示意图；
图6是本公开第二实施例提供的熔丝电路的示意图；
图7是本公开第二实施例提供的熔丝电路的时序图；
图8是本公开第二实施例提供的熔丝电路的示意图；
图9是本公开第二实施例提供的熔丝电路的时序图；
图10是本公开第三实施例提供的熔丝电路的时钟信号产生电路示意图。
具体实施方式
下面结合附图对本公开提供的熔丝电路及熔丝阵列信号传输方法的具体实施方式做详细说明。
图1是本公开第一实施例提供的熔丝电路的示意图，请参阅图1，所述熔丝电路包括熔丝单元阵列10及地址信号产生模块20。所述熔丝单元阵列10根据接收的第一使能信号DRVEN对所述熔丝单元阵列进行操作，所述地址信号产生模块20与所述熔丝单元阵列10耦接，N个预设信号以串行方式输入至所述地址信号产生模块20，并以并行方式输出目标信号，所述预设信号至少包括熔丝行地址信号XADD和熔丝列地址信号YADD，以对熔丝单元阵列中预设的熔丝单元10进行寻址。
本公开熔丝电路的预设信号以串行方式输入，并以并行方式输出目标信号，其能够仅通过一个芯片管脚就实现输入，大大减少了芯片管脚的数量，满足了芯片小型化的需求。例如若熔丝单元阵列(cell array)的内部由16*16的子阵列构成的话，那么子阵列(sub array)需要4bit的行地址信号(XADD)和4bit的列地址信号(YADD)，若采用本公开熔丝电路，可将行地址信号与列地址信号以串行方式输入，并以并行方式输出目标信号，则可仅仅通过一个芯片管脚即可实现多个行地址信号与列地址信号的输入，大大减少了芯片管脚的数量，满足芯片小型化的需求。
在一些实施例中，所述熔丝单元阵列10根据接收的第一使能信号对所述熔丝单元阵列10进行操作，所述操作包括编程操作及读操作。所述熔丝单元阵列10由多个熔丝单元以阵列形式排布而成。在一些实施例中，所述熔丝单元由反熔丝构成，在所述反熔丝的第一端与第二端之间施加高压，高压能够击穿反熔丝的介质层，使所述反熔丝从绝缘状态变为导电状态，实现信息的存储，即对反熔丝进行编程。
在一些实施例中，为了进一步减小芯片管脚的数量，所述预设信号除包括熔丝行地址信号XADD和熔丝列地址信号YADD之外，还包括熔丝子单元行地址信号XSEG及熔丝子 单元列地址信号YSEG。其中，所述熔丝子单元行地址信号XSEG用于区分共享同一根位线(BL)的不同子阵列(sub array)，所述熔丝子单元列地址信号YSEG用于区分共享同一根字线(WL)的不同子阵列(sub array)。在一些实施例中，熔丝单元阵列10可以根据需要分成不同的分组(split)，例如，将具有不同尺寸的熔丝单元归为一组，不同的分组下的熔丝单元的尺寸有所区别，可以用分组地址信号ZADD区分不同的分组。
作为示例，请参阅图2，其为预设信号表格，其中，预设信号A0～A3表示熔丝行地址信号XADD<3:0>，预设信号A4～A7表示熔丝子单元行地址信号XSEG<3:0>，预设信号A8～A11表示熔丝列地址信号YADD<3:0>，预设信号A12～A15表示熔丝子单元列地址信号YSEG<3:0>，预设信号A16～A19表示熔丝分组地址信号ZADD<3:0>。
对于熔丝电路而言，还存在熔丝操作模式命令信号MODE，控制器根据所述熔丝操作模式命令信号MODE能够确定对所述熔丝单元阵列10执行何种操作，例如编程或者读操作。例如，所述熔丝操作模式命令信号MODE为高电平时，表征对所述熔丝单元阵列执行编程，所述熔丝操作模式命令信号MODE为低电平时，表征对所述熔丝单元阵列执行读操作。可以理解的是，在另一些实施例中，所述熔丝操作模式命令信号MODE为高电平时，表征对所述熔丝单元阵列执行读操作，所述熔丝操作模式命令信号MODE为低电平时，表征对所述熔丝单元阵列执行编程。
在一些实施例中，所述预设信号还包括所述熔丝操作模式命令信号MODE。请参阅图2，预设信号A20表示所述熔丝操作模式命令信号MODE。所述熔丝行地址信号XADD、所述熔丝列地址信号YADD、所述熔丝子单元行地址信号XSEG、所述熔丝子单元列地址信号YSEG、所述熔丝分组地址信号ZADD及所述熔丝操作模式命令信号MODE以串行方式输入至所述地址信号产生模块20，并以并行方式输出目标信号，以对熔丝单元阵列中预设的熔丝单元10进行寻址及操作。
所述预设信号的数量为N个，例如，在图2所示的表格中，所述预设信号包括A0～A20，共21个，即N为21。在本公开其他实施例中，所述预设信号还可包括其他信号，则所述预设信号的数量根据实际情况确定。
本实施例还提供一种实现所述地址信号产生模块的结构，请继续参阅图1，所述地址信号产生模块20包括串并转换模块21，所述串并转换模块21接收多个所述串行方式输入的预设信号，并输出并行的中间信号。所述串并转换模块21包括N个触发器级联的移位寄存器，第一级触发器的第一输入端接收多个所述串行方式输入的预设信号，每一级触发器的 输出端对应输出中间信号。
其中，在本实施例中，所述触发器的级联数量与所述预设信号的数量相同，均为N个。作为示例，请参阅图1及图2，所述预设信号的数量为21个，则所述触发器的数量也为21个，即触发器D0～D20。第一级触发器D0的第一输入端接收多个所述串行方式输入的预设信号A0～A20，所述触发器D0～D20的输出端对应输出中间信号Q0～Q20。所述中间信号Q0～Q20为并行信号。可以理解的是，在一些实施例中，所述预设信号仅包括熔丝行地址信号及熔丝列地址信号，所述预设信号的数量为8个，则所述触发器的级联数量的也为8个。
图3是本公开第一实施例提供的熔丝电路的时序图，请参阅图1及图3，在移位时钟信号CLK的控制下，预设信号A0～A20以串行方式依次输入至第一级触发器D0的第一输入端，其中，在T0时刻，预设信号A20输入至第一级触发器D0的第一输入端；在T1时刻，预设信号A19输入至第一级触发器D0的第一输入端，预设信号A20经所述第一级触发器D0输出端形成中间信号Q0；在T2时刻，预设信号A18输入至第一级触发器D0的第一输入端，预设信号A19经所述第一级触发器D0输出端形成中间信号Q0，预设信号A20经所述第二级触发器D1输出端形成中间信号Q1。以此类推，在移位时钟信号CLK作用下，预设信号A1～A20依次逐位右移，并自每一级触发器的输出端对应输出中间信号Q0～Q20。在T21时刻，第一级触发器D0的输出端输出的中间信号Q0与预设信号A0对应，第二级触发器D1的输出端输出的中间信号Q1与预设信号A1对应，以此类推，第二十一级触发器D20的输出端输出的中间信号Q20与预设信号A20对应。其中，可根据所述预设信号A20对应输出的中间信号Q20确定需要对熔丝单元阵列执行编程还是读操作。
在第一实施例中，所述移位时钟信号CLK及时钟使能信号CLKEN经过与逻辑运算后作为所述串并转换模块21的时钟信号。
在一些实施例中，所述熔丝电路还包括复位信号RST，每一级所述触发器的第二输入端均接收所述复位信号RST，以进行复位，进而实现对所述移位寄存器的复位。作为示例，请参阅图1及图3，当复位信号RST变为高电平时，每一所述触发器被复位，当复位结束，所述复位信号RST变为低电平。
在一些实施例中，所述复位信号RST的开始时间与所述熔丝单元阵列操作的时间对应，例如，编程或者读操作，当结束对熔丝单元阵列的编程或读操作后，插入所述复位信号RST复位所述移位寄存器。例如，当结束对熔丝单元阵列10的编程或读操作后，所述复位信号RST由低电平变为高电平，以复位所述移位寄存器。因此，在本公开熔丝电路中，可利用 所述复位信号RST控制对熔丝单元阵列10的编程或读操作的时间，例如，当完成一个反熔丝单元的编程之后，插入复位信号RST进行复位，以结束当前编程操作，可以进行另一个反熔丝单元的编程。同样地，当完成一个反熔丝单元的读操作后，插入复位信号RST进行复位，以结束当前读操作，可以进行另一个反熔丝单元的读操作。
在一些实施例中，所述地址信号产生模块20还包括解码模块22，用于对所述中间信号进行解码，形成目标信号。所述解码模块22包括多个解码电路220，每一所述解码电路220对所述中间信号解码，形成所述目标信号。所述熔丝电路根据所述目标信号对所述熔丝单元阵列10中预设的熔丝单元进行寻址。
在一些实施例中，多个所述解码电路220根据所述预设信号的排序对所述中间信号进行选择性接收及解码，并输出与所述预设信号对应的目标信号。即多个所述解码电路220根据所述预设信号A0至A20的排序，依次获取一个或几个所述中间信号，并输出与所述预设信号对应的目标信号。
例如，在本实施例中，第一个所述解码电路220接收预设信号A0～A3对应的中间信号Q0～Q3，将四位熔丝行地址信号XADD<3:0>解码为对应的16位熔丝行地址信号XADD<15:0>，第二所述解码电路220接收预设信号A4～A7对应的中间信号Q4～Q7，将四位熔丝子单元行地址信号XSEG<3:0>解码为对应的16位熔丝子单元行地址信号XSEG<15:0>，第三个所述解码电路220接收预设信号A8～A11对应的中间信号Q8～Q11，将四位熔丝列地址信号YADD<3:0>解码为对应的16位熔丝列地址信号YADD<15:0>，第四个所述解码电路220接收预设信号A12～A15对应的中间信号Q12～Q15，将四位熔丝子单元列地址信号YSEG<3:0>解码为对应的16位熔丝子单元列地址信号YSEG<15:0>，第五个所述解码电路220接收预设信号A16～A19对应的中间信号Q16～Q19，将四位熔丝分组地址信号ZADD<3:0>解码为对应的16位熔丝分组地址信号ZADD<15:0>。所述熔丝电路根据16位熔丝行地址信号XADD<15:0>、熔丝子单元行地址信号XSEG<15:0>、熔丝列地址信号YADD<15:0>、熔丝子单元列地址信号YSEG<15:0>及熔丝分组地址信号ZADD<15:0>对所述熔丝单元阵列10中预设的熔丝单元进行寻址。
可以理解的是，在一些实施例中，所述预设信号仅包括熔丝行地址信号XADD<3:0>及熔丝列地址信号YADD<3:0>，则多个所述解码电路220接收预设信号对应的中间信号，将四位熔丝行地址信号XADD<3:0>解码为对应的16位熔丝行地址信号XADD<15:0>，将四位熔丝列地址信号YADD<3:0>解码为对应的16位熔丝列地址信号YADD<15:0>，所述熔 丝电路根据16为位熔丝行地址信号XADD<15:0>、熔丝列地址信号YADD<15:0>对所述熔丝单元阵列10中预设的熔丝单元进行寻址。
作为示例，本公开实施例还提供一种所述解码电路220。请参阅图4，其为本公开第一实施例提供的解码电路220的电路图，所述解码电路用于将四位信号ADDR<3:0>解码为对应的16位信号ADDR<15:0>。其中四位信号ADDR<3:0>作为解码电路的输入信号，其可表示四位熔丝行地址信号XADD<3:0>、四位熔丝子单元行地址信号XSEG<3:0>、四位熔丝列地址信号YADD<3:0>、四位熔丝子单元列地址信号YSEG<3:0>及四位熔丝分组地址信号ZADD<3:0>，16位信号ADDR<15:0>作为解码电路的输出信号，即所述目标信号，其可表示16位熔丝行地址信号XADD<15:0>、16位熔丝子单元行地址信号XSEG<15:0>、16位熔丝列地址信号YADD<15:0>、16位熔丝子单元列地址信号YSEG<15:0>及16位熔丝分组地址信号ZADD<15:0>。
所述解码电路220包括多个逻辑门电路，每一所述逻辑门电路对所述中间信号及所述中间信号的取反信号进行逻辑运算，获得所述目标信号。即所述中间信号及所述中间信号的取反信号作为所述逻辑门电路的输入信号，所述逻辑门电路的输出信号为所述目标信号。
图5为一个逻辑门电路的电路示意图，请参阅图5，所述逻辑门电路包括第一与非门电路NAND_1、第二与非门电路NAND_2及或非门电路NOR。
所述第一与非门电路NAND_1的使能端接收使能信号EN，所述第一与非门电路NAND_1的第一输入端接收第一中间信号A<0>或者第一中间信号的取反信号AN<0>，所述第一与非门电路NAND_1的第二输入端接收第二中间信号A<1>或者第二中间信号的取反信号AN<1>，所述第一与非门电路的输出端输出第一信号out1。
所述第二与非门电路NAND_2与所述第一与非门电路NAND_1并联，所述第二与非门电路NAND_2的使能端接收所述使能信号EN，所述第二与非门电路NAND_2的第一输入端接收第三中间信号A<2>或者第三中间信号的取反信号AN<2>，所述第二与非门电路NAND_2的第二输入端接收第四中间信号A<3>或者第四中间信号的取反信号AN<3>，所述第二与非门电路NAND_2的输出端输出第二信号out2。
所述或非门电路NOR的第一输入端接收所述第一信号out1，所述或非门电路NOR的第二输入端接收第二信号out2，所述或非门电路NOR的输出端输出所述目标信号ADDR<N>。
可以理解的是，四位信号ADDR<3:0>作为解码电路的输入信号，其提供所述第一中间 信号A<0>、第二中间信号A<1>、第三中间信号A<2>及第四中间信号A<3>。
作为示例，请参阅图4，对于逻辑门电路C0，所述第一与非门电路NAND_1的使能端接收使能信号EN，所述第一与非门电路NAND_1的第一输入端接收第一中间信号的取反信号AN<0>，所述第一与非门电路NAND_1的第二输入端接收第二中间信号的取反信号AN<1>，所述第一与非门电路的输出端输出第一信号out1。所述第二与非门电路NAND_2的使能端接收所述使能信号EN，所述第二与非门电路NAND_2的第一输入端接收第三中间信号的取反信号AN<2>，所述第二与非门电路NAND_2的第二输入端接收第四中间信号的取反信号AN<3>，所述第二与非门电路NAND_2的输出端输出第二信号out2。所述或非门电路NOR的第一输入端接收所述第一信号out1，所述或非门电路NOR的第二输入端接收第二信号out2，所述或非门电路NOR的输出端输出所述目标信号ADDR<0>。
再例如，请参阅图4，对于逻辑门电路C1，所述第一与非门电路NAND_1的使能端接收使能信号EN，所述第一与非门电路NAND_1的第一输入端接收第一中间信号A<0>，所述第一与非门电路NAND_1的第二输入端接收第二中间信号的取反信号AN<1>，所述第一与非门电路的输出端输出第一信号out1。所述第二与非门电路NAND_2的使能端接收所述使能信号EN，所述第二与非门电路NAND_2的第一输入端接收第三中间信号的取反信号AN<2>，所述第二与非门电路NAND_2的第二输入端接收第四中间信号的取反信号AN<3>，所述第二与非门电路NAND_2的输出端输出第二信号out2。所述或非门电路NOR的第一输入端接收所述第一信号out1，所述或非门电路NOR的第二输入端接收第二信号out2，所述或非门电路NOR的输出端输出所述目标信号ADDR<1>。
以此类推，将四位信号ADDR<3:0>提供的所述第一中间信号、第二中间信号、第三中间信号、第四中间信号及四个中间信号的取反信号进行组合作为逻辑门电路的输入信号，实现将四位信号ADDR<3:0>解码为对应的16位信号ADDR<15:0>的目的。
在一些实施例中，所述逻辑门电路还包括偶数个反相器串联而成的反相器组，所述或非门电路的输出端连接所述反相器组的输入端，以对所述或非门电路的输出信号进行缓冲，提高目标信号的稳定性。具体地说，请参阅图5，所述逻辑门电路还包括偶数个反相器串联而成的第一反相器组P1，所述或非门电路NOR的输出端连接所述第一反相器组P1的输入端，所述或非门电路NOR的输出信号作为所述第一反相器组P1的输入信号，所述第一反相器组P1的输出信号作为所述目标信号ADDR<N>。在本实施例中，所述第一反相器组P1包括两个串联的反相器，分别为反相器P11及反相器P12，所述或非门电路NOR的输出端 的输出信号作为所述反相器P11的输入信号，所述反相器P11的输出信号作为所述反相器P12的输入信号，所述反相器P12的输出信号作为所述目标信号ADDR<N>。
上述仅为解码电路的一个示例，也可采用其他结构的解码电路实现对本公开中间信号的解码，本公开并不以此为限。
本公开第一实施例提供的熔丝电路利用串并转换模块及解码电路实现了将串行方式输入的预设信号转换为并行方式输出目标信号，使得预设信号仅通过一个芯片管脚即可输入，大大减少了芯片管脚的数量，满足芯片小型化的需求。
在第一实施例中，所述预设信号为N个，所述串并转换模块包括N个触发器级联的移位寄存器，而在本公开第二实施例中，所述串并转换模块还包括第N+1个触发器，构成N+1个触发器级联的N+1位移位寄存器，在N个所述预设信号之前设置有启动信号，所述启动信号作为第一个信号输入至所述第一级触发器的第一输入端，并经第N+1级触发器的输出端对应输出所述第一使能信号。
具体地说，请参阅图6，其为本公开第二实施例提供的熔丝电路的示意图，第二实施例与第一实施例的区别在于，所述串并转换模块21还包括第N+1个触发器，即第二十二级触发器D21，N+1个触发器构成N+1位移位寄存器。在N个所述预设信号之前设置有启动信号start，所述启动信号start作为第一个信号输入至所述第一级触发器D0的第一输入端，并经第二十二级触发器D21的输出端对应输出所述第一使能信号DRVEN。在本实施例中，所述第一使能信号DRVEN也可作为所述解码模块22的一个输入信号，所述解码模块22根据所述第一使能信号DRVEN确定熔丝单元阵列10的操作模式，所述操作模式包括编程或读操作。
图7是本公开第二实施例提供的熔丝电路的时序图，请参阅图6及图7，在移位时钟信号CLK的控制下，启动信号start及预设信号A0～A20以串行方式依次输入至第一级触发器D0的第一输入端，其中，在Ts时刻，启动信号start输入至第一级触发器D0的第一输入端；在T0时刻，预设信号A20输入至第一级触发器D0的第一输入端，启动信号start经所述第一级触发器D0输出端形成中间信号Q0；在T1时刻，预设信号A19输入至第一级触发器D0的第一输入端，预设信号A20经所述第一级触发器D0输出端形成中间信号Q0，启动信号start经所述第二级触发器D1输出端形成中间信号Q1；在T2时刻，预设信号A18输入至第一级触发器D0的第一输入端，预设信号A19经所述第一级触发器D0输出端形成中间信号Q0，预设信号A20经所述第二级触发器D1输出端形成中间信号Q1，启动信号start 经所述第三级触发器D2输出端形成中间信号Q2；以此类推，在移位时钟信号CLK作用下，启动信号start及预设信号A1～A20依次逐位右移，并自每一级触发器的输出端对应输出中间信号Q0～Q21。在T21时刻，第一级触发器D0的输出端输出的中间信号Q0与预设信号A0对应，第二级触发器D1的输出端输出的中间信号Q1与预设信号A1对应，以此类推，第二十一级触发器D20的输出端输出的中间信号Q20与预设信号A20对应，第二十二级触发器D21的输出端输出的中间信号Q21与启动信号start对应，所述中间信号Q21即为所述第一使能信号DRVEN。
在第二实施例中，所述启动信号start与所述预设信号以串行的方式输入，并以并行的方式输出，其中所述启动信号start对应输出所述第一使能信号DRVEN，从而可避免启动信号start采用单独的芯片引脚输入，进一步降低了芯片引脚的数量。在第二实施例中，所述移位时钟信号CLK及时钟使能信号CLKEN经过与逻辑运算后作为所述串并转换模块21的时钟信号。
在第二实施例中，所述预设信号为N个，所述串并转换模块包括N+1个触发器级联的移位寄存器，而在本公开第三实施例中，所述串并转换模块22不仅包括第N+1个触发器，还包括第N+2个触发器，构成N+2个触发器级联的N+2位移位寄存器。在N个所述预设信号之前设置有启动信号，所述启动信号作为第一个信号输入至所述第一级触发器的第一输入端，并经第N+2级触发器的输出端对应输出所述第一使能信号，N个所述预设信号经第一级至第N级触发器输出端对应输出所述中间信号。
具体地说，请参阅图8，其为本公开第三实施例提供的熔丝电路的示意图，第三实施例与第二实施例的区别在于，所述串并转换模块22不仅包括第N+1个触发器，即第二十二级触发器D21，还包括第N+2个触发器D22，即第二十三级触发器D22，N+2个触发器级联构成N+2位移位寄存器。在N个所述预设信号之前设置有启动信号start，所述启动信号start作为第一个信号输入至所述第一级触发器D0的第一输入端，并经第二十三级触发器D22的输出端对应输出所述第一使能信号DRVEN，N个所述预设信号经第一级至第N级触发器输出端对应输出所述中间信号。
在第三实施例中，第二十二级触发器D21的输出端并不输出中间信号，所述第二十二级触发器D21与所述第二十三级触发器D22共同作用使所述启动信号start延迟输出形成所述第一使能信号DRVEN，提高信号传输的稳定性。
在第三实施例中，第二十三级触发器D22包括两个级联的第一锁存器(附图中未绘示) 及第二锁存器(附图中未绘示)，所述第一锁存器输出端对应输出第二使能信号Q22_05。在一些实施例中，所述第二使能信号Q22_05作为感测放大使能信号SAEN，所述第二锁存器输出端对应输出所述第一使能信号DRVEN。所述感测放大使能信号SAEN用于使能熔丝电路中的感测电路(附图中未绘示)，所述感测电路用于在读操作模式下对熔丝单元存储的信息进行检测和判断。图9是本公开第三实施例提供的熔丝电路的时序图，请参阅图8及图9，在移位时钟信号CLK的控制下，启动信号start及预设信号A0～A20以串行方式依次输入至第一级触发器D0的第一输入端，其中，在Ts时刻，启动信号start输入至第一级触发器D0的第一输入端；在T0时刻，预设信号A20输入至第一级触发器D0的第一输入端，启动信号start经所述第一级触发器D0输出端形成中间信号Q0；在T1时刻，预设信号A19输入至第一级触发器D0的第一输入端，预设信号A20经所述第一级触发器D0输出端形成中间信号Q0，启动信号start经所述第二级触发器D1输出端形成中间信号Q1；在T2时刻，预设信号A18输入至第一级触发器D0的第一输入端，预设信号A19经所述第一级触发器D0输出端形成中间信号Q0，预设信号A20经所述第二级触发器D0输出端形成中间信号Q1，启动信号start经所述第三级触发器D2输出端形成中间信号Q2；以此类推，在移位时钟信号CLK作用下，启动信号start及预设信号A0～A20依次逐位右移，并自触发器D0～D20的输出端对应输出中间信号Q0～Q20，触发器D22的输出端输出第一使能信号DRVEN。在T21时刻，第一级触发器D0的输出端输出的中间信号Q0与预设信号A0对应，第二级触发器D1的输出端输出的中间信号Q1与预设信号A1对应，以此类推，第二十一级触发器D20的输出端输出的中间信号Q20与预设信号A20对应，第二十二级触发器D21的输出信号与启动信号start对应，且作为第二十三级触发器D22的输入信号，在T21时刻之后，第二十三级触发器D22输出所述第一使能信号DRVEN及感测放大使能信号SAEN，所述熔丝单元阵列根据所述第一使能信号DRVEN执行操作，例如编程或者读操作，当需要执行读操作时，所述感测放大使能信号SAEN使能熔丝电路中的感测电路。
在第三实施例中，所述熔丝电路利用第N+2个触发器实现对启动信号的延迟输出，保证信号传输的稳定性。
在第三实施例中，移位时钟信号CLK及时钟使能信号CLKEN经过与逻辑运算后形成时钟信号CLKout，时钟信号CLKout作为第一级触发器D0～第二十二级触发器D21的时钟信号，移位时钟信号CLK单独作为第二十三级触发器D22的时钟信号，以使得所述第一使能信号的输出不受所述时钟使能信号CLKEN的影响。其中，所述第二使能信号Q22_05取 反后作为所述时钟使能信号CLKEN。
在第三实施例中，所述熔丝电路还包括时钟信号产生模块，所述时钟信号产生模块对所述移位时钟信号CLK及所述时钟使能信号CLKEN进行逻辑运算，所述时钟信号产生模块输出的时钟信号CLKout作为所述串并转换模块21的时钟信号。
请参阅图10，其为本公开第三实施例提供的熔丝电路的时钟信号产生电路示意图，所述时钟信号产生模块包括第三与非门电路NAND_3及第二反相器组P2，所述第三与非门电路NAND_3的输出端与所述第二反相器组P2的输入端连接，所述第二反相器组P2输出端输出的时钟信号CLKout作为所述串并转换模块21的时钟信号。所述第二反相器组P2由奇数个反相器串联而成，例如在本实施例中，所述第二反相器组P2由反相器P21、P22及P23串联而成。
在本实施例中，移位时钟信号CLK作为所述第三与非门电路NAND_3第一输入端的输入信号，第二使能信号Q22_05经反相器P31取反后形成时钟使能信号CLKEN，所述时钟使能信号CLKEN作为所述第三与非门电路NAND_3第二输入端的输入信号，所述第三与非门电路NAND_3对所述移位时钟信号CLK及时钟使能信号CLKEN进行与非逻辑运算，并将输出信号作为所述第二反相器组P2的输入信号。所述第二反相器组P2对输入信号进行取反并输出时钟信号CLKout，时钟信号CLKout作为所述串并转换模块21的时钟信号。当所述第二使能信号Q22_05为高电平时，时钟使能信号CLKEN为低电平，则所述时钟信号产生电路输出的时钟信号CLKout为低电平，即所述串并转换模块21的时钟信号变为低电平，所述串并转换模块21的时钟信号无效；当所述第二使能信号Q22_05为低电平时，时钟使能信号CLKEN为高电平，则所述时钟信号产生电路输出的时钟信号CLKout为高电平，即所述串并转换模块21的时钟信号变为高电平，所述串并转换模块21的时钟信号有效。
可以理解的是，在本公开其他实施例中，也可采用其他逻辑电路实现所述时钟信号生成模块的功能，例如与逻辑电路。
本公开熔丝电路的预设信号以串行方式输入，并以并行方式输出目标信号，其能够仅通过一个芯片管脚就实现输入，大大减少了芯片管脚的数量，满足了芯片小型化的需求。
基于相同构思，本公开还提供一种熔丝阵列信号传输方法，所述熔丝阵列信号传输方法采用上述熔丝电路。所述方法包括：N个预设信号以串行方式输入，并以并行方式输出目标信号，所述预设信号至少包括熔丝行地址信号和熔丝列地址信号，以对熔丝单元阵列 中预设的熔丝单元进行寻址。本公开熔丝阵列信号传输方法将预设信号以串行方式输入，并以并行方式输出目标信号，其能够仅通过一个芯片管脚就实现输入，大大减少了芯片管脚的数量，满足了芯片小型化的需求。
在一些实施例中，所述预设信号还包括熔丝操作模式命令信号。即所述熔丝操作模式命令信号与所述熔丝行地址信号和熔丝列地址信号采用同一个芯片管脚输入，大大减少了芯片管脚的数量，满足了芯片小型化的需求。
在一些实施例中，还包括启动信号，所述启动信号作为第一个输入信号与N个所述预设信号以串行方式输入，并以并行方式输出与所述预设信号对应的目标信号及与所述启动信号对应的第一使能信号，熔丝单元阵列能够根据所述第一使能信号对所述熔丝单元阵列进行操作。所述启动信号与所述预设信号以串行方式输入，则两者可采用同一芯片管脚，大大减少了芯片管脚的数量，满足了芯片小型化的需求。
在一些实施例中，所述方法还包括，形成与所述启动信号对应的感测放大使能信号。所述感测放大使能信号SAEN用于使能熔丝电路中的感测电路(附图中未绘示)，所述感测电路用于在读操作模式下对熔丝单元存储的信息进行检测和判断。
在一些实施例中，所述方法还包括，形成与所述启动信号对应的第二使能信号。并对移位时钟信号及所述第二使能信号的取反信号进行逻辑运算，形成用于串并转换的时钟信号。所述N个预设信号根据所述时钟信号以串行方式输入，并以并行方式输出目标信号。
在一些实施例中，所述方法还包括：在结束对熔丝单元阵列的编程或读操作后，执行复位操作。在一些实施例中，当结束对熔丝单元阵列的编程或读操作后，插入复位信号执行复位操作。例如，当结束对熔丝单元阵列的编程或读操作后，复位信号由低电平变为高电平，以执行复位操作。在本公开方法中，可利用复位信号的周期控制对熔丝单元阵列的编程或读操作的时间，例如，当完成一个反熔丝单元的编程之后，插入复位信号进行复位，以结束当前编程操作，可以进行另一个反熔丝单元的编程。同样地，当完成一个反熔丝单元的读操作后，插入复位信号进行复位，以结束当前读操作，可以进行另一个反熔丝单元的读操作。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (21)

  1. 一种熔丝电路，包括：
    熔丝单元阵列，根据接收的第一使能信号对所述熔丝单元阵列进行操作；
    地址信号产生模块，与所述熔丝单元阵列耦接，N个预设信号以串行方式输入至所述地址信号产生模块，并以并行方式输出目标信号，所述预设信号至少包括熔丝行地址信号和熔丝列地址信号，以对熔丝单元阵列中预设的熔丝单元进行寻址。
  2. 根据权利要求1所述的熔丝电路，其中，所述预设信号还包括熔丝子单元行地址信号、熔丝子单元列地址信号、熔丝分组地址信号。
  3. 根据权利要求1所述的熔丝电路，其中，所述预设信号还包括熔丝操作模式命令信号。
  4. 根据权利要求1所述的熔丝电路，其中，所述地址信号产生模块包括串并转换模块，所述串并转换模块包括N个触发器级联的移位寄存器，第一级触发器的第一输入端接收多个所述串行方式输入的预设信号，每一级触发器的输出端对应输出中间信号。
  5. 根据权利要求4所述的熔丝电路，其中，所述串并转换模块还包括第N+1个触发器，构成N+1个触发器级联的移位寄存器，在N个所述预设信号之前设置有启动信号，所述启动信号作为第一个信号输入至所述第一级触发器的第一输入端，并经第N+1级触发器的输出端对应输出所述第一使能信号。
  6. 根据权利要求4所述的熔丝电路，其中，所述串并转换模块还包括第N+1个及第N+2个触发器，构成N+2个触发器级联的移位寄存器，在N个所述预设信号之前设置有启动信号，所述启动信号作为第一个信号输入至所述第一级触发器的第一输入端，并经第N+2级触发器的输出端对应输出所述第一使能信号，N个所述预设信号经第一级至第N级触发器输出端对应输出所述中间信号。
  7. 根据权利要求6所述的熔丝电路，其中，第N+2级触发器包括两个级联的第一锁存器及第二锁存器，所述第一锁存器输出端对应输出第二使能信号，所述第二锁存器输出端对应输出所述第一使能信号。
  8. 根据权利要求7所述的熔丝电路，其中，所述熔丝电路还包括时钟信号产生模块，所述时钟信号产生模块对移位时钟信号及所述第二使能信号的取反信号进行逻辑运算，且所述时钟信号产生模块的输出信号作为所述串并转换模块的时钟信号。
  9. 根据权利要求4所述的熔丝电路，其中，还包括复位信号，每一级所述触发器的第二输入端均接收复位信号，以对所述移位寄存器进行复位。
  10. 根据权利要求9所述的熔丝电路，其中，所述复位信号的开始时间与所述熔丝单元阵列操作的时间对应，当结束对熔丝单元阵列的操作后，所述复位信号有效，复位所述移位寄存器。
  11. 根据权利要求4所述的熔丝电路，其中，所述地址信号产生模块还包括解码模块，所述解码模块包括多个解码电路，所述解码电路对所述中间信号解码，形成所述目标信号，所述熔丝电路根据所述目标信号对所述熔丝单元阵列中预设的熔丝单元进行寻址。
  12. 根据权利要求11所述的熔丝电路，其中，多个所述解码电路根据所述预设信号的排序对所述中间信号进行选择性接收及解码，并输出与所述预设信号对应的目标信号。
  13. 根据权利要求11所述的熔丝电路，其中，所述解码电路包括多个逻辑门电路，所述逻辑门电路对所述中间信号及所述中间信号的取反信号进行逻辑运算，获得所述目标信号。
  14. 根据权利要求13所述的熔丝电路，其中，所述逻辑门电路包括：
    第一与非门电路，所述第一与非门电路的使能端接收使能信号，所述第一与非门电路的第一输入端接收第一中间信号或者第一中间信号的取反信号，所述第一与非门电路的第二输入端接收第二中间信号或者第二中间信号的取反信号，所述第一与非门电路的输出端输出第一信号；
    第二与非门电路，所述第二与非门电路的使能端接收所述使能信号，所述第二与非门电路的第一输入端接收第三中间信号或者第三中间信号的取反信号，所述第二与非门电路的第二输入端接收第四中间信号或者第四中间信号的取反信号，所述第二与非门电路的输出端输出第二信号；
    或非门电路，所述或非门电路的第一输入端接收所述第一信号，所述或非门电路的第二输入端接收第二信号，所述或非门电路的输出端输出所述目标信号。
  15. 根据权利要求14所述的熔丝电路，其中，所述逻辑门电路还包括偶数个反相器串联而成的反相器组，所述或非门电路的输出端连接所述反相器组的输入端，所述反相器组的输出信号作为所述目标信号。
  16. 一种熔丝阵列信号传输方法，包括：
    N个预设信号以串行方式输入，并以并行方式输出目标信号，所述预设信号至少包括熔丝行地址信号和熔丝列地址信号，以对熔丝单元阵列中预设的熔丝单元进行寻址。
  17. 根据权利要求16所述的熔丝阵列信号传输方法，其中，所述预设信号还包括熔丝操作模式命令信号。
  18. 根据权利要求16所述的熔丝阵列信号传输方法，其中，还包括启动信号，所述启动信号作为第一个输入信号与N个所述预设信号以串行方式输入，并以并行方式输出与所述预设信号对应的目标信号及与所述启动信号对应的第一使能信号，熔丝单元阵列能够根据所述第一使能信号对所述熔丝单元阵列进行操作。
  19. 根据权利要求18所述的熔丝阵列信号传输方法，其中，所述方法还包括：形成与所述启动信号对应的感测放大使能信号。
  20. 根据权利要求18所述的熔丝阵列信号传输方法，其中，所述方法还包括：形成与所述启动信号对应的第二使能信号，并对移位时钟信号及所述第二使能信号的取反信号进行逻辑运算，形成用于串并转换的时钟信号。
  21. 根据权利要求16所述的熔丝阵列信号传输方法，其中，所述方法还包括：在结束对熔丝单元阵列的操作后，执行复位操作。
PCT/CN2022/108130 2022-06-01 2022-07-27 熔丝电路及熔丝阵列信号传输方法 WO2023231166A1 (zh)

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US6373771B1 (en) * 2001-01-17 2002-04-16 International Business Machines Corporation Integrated fuse latch and shift register for efficient programming and fuse readout
US7339400B1 (en) * 2006-06-09 2008-03-04 Xilinx, Inc. Interface port for electrically programmed fuses in a programmable logic device
CN112530500A (zh) * 2019-09-19 2021-03-19 晶豪科技股份有限公司 电子熔丝烧入电路以及电子熔丝烧入方法

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* Cited by examiner, † Cited by third party
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US6373771B1 (en) * 2001-01-17 2002-04-16 International Business Machines Corporation Integrated fuse latch and shift register for efficient programming and fuse readout
US7339400B1 (en) * 2006-06-09 2008-03-04 Xilinx, Inc. Interface port for electrically programmed fuses in a programmable logic device
CN112530500A (zh) * 2019-09-19 2021-03-19 晶豪科技股份有限公司 电子熔丝烧入电路以及电子熔丝烧入方法

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