WO2023226741A1 - 一种显示驱动电路、显示驱动方法及显示设备 - Google Patents

一种显示驱动电路、显示驱动方法及显示设备 Download PDF

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Publication number
WO2023226741A1
WO2023226741A1 PCT/CN2023/092835 CN2023092835W WO2023226741A1 WO 2023226741 A1 WO2023226741 A1 WO 2023226741A1 CN 2023092835 W CN2023092835 W CN 2023092835W WO 2023226741 A1 WO2023226741 A1 WO 2023226741A1
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Prior art keywords
display
level
pulse signal
driving circuit
scan pulse
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PCT/CN2023/092835
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English (en)
French (fr)
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WO2023226741A9 (zh
Inventor
汪俊
戴珂
聂春扬
周留刚
陈韫璐
黄艳庭
权宇
尹晓峰
孙建伟
李清
胡胜华
Original Assignee
京东方科技集团股份有限公司
合肥京东方显示技术有限公司
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Publication of WO2023226741A1 publication Critical patent/WO2023226741A1/zh
Publication of WO2023226741A9 publication Critical patent/WO2023226741A9/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display driving circuit, a display driving method and a display device.
  • Embodiments of the present disclosure provide a display driving circuit, a display driving method and a display device, which can improve horizontal stripe defects caused by differences in charging rates between pixel rows.
  • a display driving circuit includes:
  • a gate modulation module the gate modulation module is electrically connected to the display pixels in the display panel, and is used to receive the scan pulse signal, and to adjust the first level of the first level and the second level of the scan pulse signal.
  • a flat amplitude, the first level is a high level relative to the second level;
  • the scan pulse signal is used to drive the display pixels of the display panel to display the picture.
  • the gate modulation module is also used to receive the first level reference voltage, and to adjust the first level reference voltage to output the adjusted reference voltage;
  • the adjustment reference voltage is used to adjust the amplitude of the first level of the scan pulse signal.
  • the adjustment reference voltage corresponds to the scan pulse signal one-to-one.
  • the gate modulation module is used to adjust the partial voltage of the scan path used by the scan drive signal to drive the display pixel, so as to adjust the first voltage of the scan pulse signal corresponding to the scan path. flat amplitude.
  • the gate modulation module includes: an adjustment unit, the adjustment unit is used to adjust the amplitude of the first level of the scan pulse signal, and the adjustment unit corresponds to the scan pulse signal one-to-one. .
  • the adjustment unit includes: at least one switch.
  • the adjustment unit includes: a plurality of switches connected in parallel; at least one fixed resistor and/or an adjustable resistor is included between any two switches connected in parallel.
  • the adjustment unit includes: a plurality of switches connected in parallel, and a fixed resistor and/or an adjustable resistor is connected in series on the path where each switch is located.
  • the switch includes: at least one transistor.
  • the display driving circuit also includes: a level conversion module;
  • the level conversion module includes a first level reference input pin, and the first level reference input pin is electrically connected to the output pin of the gate modulation module.
  • the display driving circuit also includes: a level conversion module;
  • the level conversion module includes a scan pulse output pin, and the scan pulse output pin is electrically connected to the input pin of the gate modulation module.
  • the display driving circuit also includes: an output discharge module;
  • the output discharge module is electrically connected between the level conversion module and the gate modulation module; or the gate modulation module is electrically connected between the level conversion module and the output discharge module.
  • the display driving circuit also includes: a modulation control module;
  • the modulation control module is used to provide a modulation control signal to the gate modulation module, and the modulation control signal is used to control the gate modulation module to adjust the amplitude of the first level of the scan pulse signal.
  • a display driving method which is applied to the display driving circuit as described in the above aspect, and the display driving method includes:
  • the gate modulation module is used to adjust the amplitude of the first level among the first level and the second level of the received scan pulse signal. value to reduce the current difference between different scanning paths;
  • the scanning path is a path through which the scanning driving signal drives the display pixel;
  • the first level is a high level relative to the second level.
  • the display control instruction includes: modulating a control signal; before receiving the display control instruction, the display driving method further includes:
  • the amplitude of the first level among the first level and the second level of the received scan pulse signal is adjusted by the gate modulation module.
  • the amplitude of the first level of the received scan pulse signal is adjusted based on the modulation control signal.
  • adjusting the amplitude of the first level among the first level and the second level of the received scan pulse signal through the gate modulation module includes:
  • the amplitude of the first level of the scan pulse signal is adjusted.
  • adjusting the amplitude of the first level among the first level and the second level of the received scan pulse signal through the gate modulation module includes:
  • Adjust the partial voltage of the scanning path to adjust the amplitude of the first level of the scanning pulse signal corresponding to the scanning path.
  • a display driving controller including:
  • a processor the processor is configured to implement the display driving method as described in the above-mentioned other aspect when executing the computer program.
  • a display device comprising:
  • the display device also includes:
  • a display panel has a display area and a non-display area
  • control circuit board the control circuit board is electrically connected to the display panel
  • the display driving circuit included in the display device is bound to the non-display area of the display panel; or, the display driving circuit included in the display device is disposed on the control circuit board.
  • Figure 1 is a schematic structural block diagram of a display driving circuit provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural block diagram of a raster scanning circuit of a display panel provided by an embodiment of the present disclosure
  • Figure 3 is a partial equivalent circuit diagram of a display pixel driven by a scan pulse signal according to an embodiment of the present disclosure
  • Figure 4 is a schematic diagram corresponding to the refresh frequency and charging time of a display panel provided by an embodiment of the present disclosure
  • Figure 5 is a schematic structural block diagram of another display driving circuit provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic structural block diagram of yet another display driving circuit provided by an embodiment of the present disclosure.
  • Figure 7 is a schematic structural block diagram of a gate modulation module provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic structural block diagram of another gate modulation module provided by an embodiment of the present disclosure.
  • Figure 9 is a schematic structural diagram of an adjustment unit provided by an embodiment of the present disclosure.
  • Figure 10 is a signal timing diagram of a display driving circuit provided by an embodiment of the present disclosure.
  • Figure 11 is a schematic structural diagram of another adjustment unit provided by an embodiment of the present disclosure.
  • Figure 12 is a schematic flow chart of a display driving method provided by an embodiment of the present disclosure.
  • Figure 13 is a schematic structural block diagram of a drive controller provided by an embodiment of the present disclosure.
  • Figure 14 is a schematic structural block diagram of a display device provided by an embodiment of the present disclosure.
  • the term "more than two” includes two or more than two.
  • the term "and/or” means that three relationships can exist. For example, A and/or B can mean: A alone exists, A and B exist simultaneously, and B alone exists.
  • the character "/" generally indicates that the related objects are in an "or” relationship.
  • embodiments of the present disclosure provide a display driving circuit, a display driving method and a display device, which can improve horizontal stripe defects caused by differences in charging rates between pixel rows.
  • FIG. 1 is a schematic structural block diagram of a display driving circuit provided by an embodiment of the present disclosure.
  • a display driving circuit provided by an embodiment of the present disclosure includes: a gate modulation module 100 .
  • the gate modulation module 100 is electrically connected to the display pixels 210 in the display panel 200, and is used to receive the scan pulse signal CLK, and to adjust the amplitude of the first level among the first level and the second level of the scan pulse signal CLK.
  • the first level may be a high level relative to the second level.
  • the scan pulse signal CLK is used to drive the display pixels 210 of the display panel 200 to implement raster scanning of the display pixels, so that the display pixels 210 can be lit and display a picture.
  • FIG. 2 is a schematic structural block diagram of a raster scanning circuit of a display panel provided by an embodiment of the present disclosure.
  • the gate scanning circuit of the display panel can adopt an array substrate row driver (Gate on Array, GOA) architecture.
  • the scan pulse signal CLK may include a first scan pulse signal CLK1, a second scan pulse signal CLK2, a third scan pulse signal CLK3, a fourth scan pulse signal CLK4, a fifth scan pulse signal CLK5, and a sixth scan pulse signal CLK6.
  • Each row of display pixels 210 in the display panel can correspond to one GOA.
  • Figure 2 schematically shows six GOAs, namely GOA1 to GOA6.
  • each GOA can include a pulse input pin clk, a high-level input pin VDD, a low-level input pin Flat input pin Vss, frame start signal pin IN and cascade pin R.
  • the pulse input pin clk is used to receive the scan pulse signal CLK
  • the high-level input pin VDD is used to receive a high-level signal.
  • the level signal VDD2, the first high-level signal VDD1 and the second high-level signal VDD2 can be the same in value, but are transmitted through two signal lines respectively.
  • the corresponding high-level input pin VDD is respectively used as VDD(1 ) and VDD(2) indicate that the low-level input pin Vss is used to receive the low-level signal Vss, the frame start signal pin IN is used to receive the frame start signal STV, and the cascade connection pin R is used to receive the cascade connection Feedback signal.
  • low-level signals and high-level signals are also relative. Since the display pixels 210 are scanned row by row, the starting time of scanning each row of the display pixels 210 is different. In addition, since the pulse needs to be reset after the scanning is completed, the GOA that has not been scanned needs to perform cascade feedback on the GOA that has been scanned, so as to reset the pulse of the scanned GOA. In addition, it should be noted that all rows of display pixels 210 included in the display panel 200 can provide scan pulse signals from CLK1 to CLK6.
  • FIG. 3 is a partial equivalent circuit diagram of a display pixel driven by a scan pulse signal according to an embodiment of the present disclosure.
  • the first scan pulse signal CLK1 may be electrically connected to the gate of the first thin film transistor T1 .
  • the first thin film transistor T1 may represent a driving device of the display pixel 210 .
  • the first electrode of the first thin film transistor T1 may be connected to the gate electrode of the first thin film transistor T1 .
  • the data signal line Data Line is electrically connected, and the second electrode of the first thin film transistor T1 can be electrically connected to the pixel electrode.
  • the second scan pulse signal CLK2 may be electrically connected to the gate of the second thin film transistor T2.
  • the second thin film transistor T2 may represent a driving device of the display pixel 210.
  • the first electrode of the second thin film transistor T2 may be electrically connected to the data signal line Data Line. connection, the second electrode of the second thin film transistor T2 may be electrically connected to the pixel electrode.
  • the equivalent impedance of the first scan pulse signal CLK1 and the corresponding scanning path of the pixel electrode is the first resistor R01
  • the equivalent impedance of the second scan pulse signal CLK2 and the corresponding scanning path of the pixel electrode is the second resistor R02.
  • the divided voltage of the first resistor R01 is V1
  • the divided voltage of the second resistor R02 is V2.
  • the data signal line Data Line can be used to provide data signals to the first thin film transistor T1 and the second thin film transistor T2 respectively, and the data signals charge the pixel electrode.
  • the data signal received by the first thin film transistor T1 and the charging current of the corresponding electrically connected pixel electrode are the first charging current i1
  • the data signal received by the second thin film transistor T2 and the charging current of the corresponding electrically connected pixel electrode are the second charging current i1.
  • the high level amplitudes of the first scan pulse signal CLK1 and the second scan pulse signal CLK2 are the same. Due to the voltage division of the first resistor R01 and the second resistor R02, the gate voltage reaching the first thin film transistor T1 can be scan The high-level amplitude of the pulse signal minus the divided voltage.
  • the internal circuit circuit forming process of display panels usually includes: metal deposition, exposure and etching. Waiting for multiple steps, slight unevenness in each step will cause differences in the equivalent impedance of each scanning path. If the resistance of the first resistor R01 and the resistance of the second resistor R02 are different due to process fluctuations, there will be a difference between the first charging current i1 and the second charging current i2. Furthermore, the charging time rates of the pixel electrodes of the display pixels 210 in different rows will be different, causing horizontal stripes in the display screen.
  • FIG. 4 is a schematic diagram corresponding to the refresh frequency and charging time of a display panel provided by an embodiment of the present disclosure. As shown in FIG. 4 , as the refresh frequency of the display panel of high-end products increases, the charging time for each row of display pixels 210 decreases.
  • the refresh frequency is from 60 Hertz (Hz) to 576Hz.
  • the scan pulse signal CLK drives the gate of the driving device of the display pixel 210
  • the data signal line Data Line charges the pixel electrode of the display pixel 210 within a period of 1H.
  • the time is reduced from 7.4 microseconds (us) to 0.72us, and the charging time has changed by an order of magnitude.
  • the short charging time makes the charging rate of each display pixel 210 extremely sensitive to the difference in equivalent impedance of the path.
  • the difference in equivalent impedance of the scanning path will cause a difference in the gate voltage of the thin film transistor, affecting the turn-on time of the thin film transistor or
  • the conduction performance leads to differences in the charging currents i1 and i2 of the data signal line Data Line, which ultimately leads to differences in charging rates, especially the formation of horizontal stripes in pure grayscale images.
  • the high-level amplitude of the scan pulse signal CLK is fixed and cannot be adjusted.
  • the high-level amplitudes of CLK1 to CLK6 are all unadjustable. In this case, process fluctuations lead to equivalent changes in the scanning paths of the display pixels.
  • the gate voltages of the thin film transistors corresponding to the display pixels are different, which ultimately leads to differences in the charging rates of the pixel electrodes, resulting in poor horizontal stripes on the display screen.
  • the display driving circuit provided by the embodiment of the present disclosure is provided with a gate modulation module 100.
  • the gate modulation module 100 can adjust the high-level amplitude of the scan pulse signal CLK.
  • the gate voltage of the thin film transistor of the display pixel 210 is adjusted by adjusting the high-level amplitude of the scan pulse signal CLK to ensure that the thin film transistor continues to be turned on within a required period of time to ensure that the pixel electrode
  • the charging time is not affected by the difference in equivalent impedance, can reduce the difference in charging rates between the display pixels 210 in different rows, and can improve the horizontal stripe defects of the display screen.
  • the amount of charge accumulated in the gates of the thin film transistors corresponding to the display pixels 210 in different rows is relatively even, so as to ensure that the thin films in different rows The transistors are turned on more evenly. In this way, the difference in charging time of pixel electrodes in different rows can be reduced, ensuring that the charging rates of pixel electrodes in different rows are relatively balanced, and no horizontal stripe defects caused by differences in charging rates of pixel electrodes in different rows will occur.
  • the display driving circuit provided by the embodiment of the present disclosure is provided with a gate modulation module 100.
  • the gate modulation module 100 adjusts the high-level amplitude of the received scan pulse signal CLK.
  • the gate voltage of the thin film transistor of the display pixel 210 is adjusted by adjusting the high-level amplitude of the scan pulse signal CLK to ensure that the thin film transistor continues to be turned on within the required period of time to ensure that the pixel
  • the charging time of the electrode is not affected by the difference in equivalent impedance, can reduce the difference in charging rate between the display pixels 210 in different rows, and can improve the horizontal stripe defect of the display screen.
  • the gate modulation module 100 can also be used to receive a first level (ie, high level) reference voltage, and can be used to adjust the first level reference voltage to output an adjusted reference voltage.
  • a first level (ie, high level) reference voltage ie, high level
  • adjusting the reference voltage may be used to adjust the amplitude of the first level of the scan pulse signal CLK.
  • the high-level amplitude of the scan pulse signal CLK is determined by the high-level reference voltage. For example, if the high-level reference voltage of a display panel is 12V, then the high-level amplitude of the scan pulse signal CLK that drives the row scanning of the display panel may be 12V.
  • the gate modulation module 100 can adjust the high-level amplitude of the scan pulse signal CLK by adjusting the high-level reference voltage.
  • the gate modulation module 100 adjusts the high-level reference voltage to obtain an adjusted reference voltage. Adjusting the reference voltage can control the high-level amplitude of the corresponding scan pulse signal CLK.
  • the adjustment reference voltage can correspond to the scan pulse signal one-to-one, which can realize one-to-one independent adjustment of the high-level reference voltage to the scan pulse signal.
  • the existing display driving circuit is generally provided with only one high-level reference voltage signal line.
  • the display driving circuit provided by the embodiment of the present disclosure can obtain multiple adjustment reference voltages through the adjustment of the gate modulation module 100, each of which is Adjusting the reference voltage can be used to control the high-level amplitude of a scan pulse signal CLK, which can reduce the difference in charging rates of display pixels in different rows, thereby improving the horizontal stripe defects of the display screen.
  • FIG. 5 is a schematic structural block diagram of another display driving circuit provided by an embodiment of the present disclosure.
  • the display driving circuit also includes: a level conversion module Level Shifter.
  • the level conversion module Level Shifter includes a first level (ie, high level) reference input pin.
  • the first level reference input pin It is electrically connected to the output pin of the gate modulation module 100 .
  • the high-level reference voltage VGH can be adjusted by the gate modulation module 100 to obtain N adjusted reference voltages, which are VGHO1 to VGHON respectively.
  • N can be a natural number greater than zero, and the corresponding scan pulse
  • the number of signals CLK is also N, which are CLK1 ⁇ CLKN respectively.
  • the scan pulse signal CLK is in the time control circuit (Timming Controller, T-Con)
  • T-Con time control circuit
  • the high-level amplitude during output is low, such as 3.3 volts (V), but the high-level amplitude of the scan pulse signal CLK required by the display panel is usually high, such as 12V, 24V or 37V.
  • the value size can be determined based on the size and pixel design of different display panels. Therefore, the level shift module Level Shifter can raise the high-level amplitude of the scan pulse signal CLK output by the T-Con, and the raised amplitude can be determined by the high-level reference voltage VGH.
  • the level shift module Level Shifter can also be used to receive the low-level reference voltage VGL, and the low-level reference voltage VGL can be used to determine the low-level amplitude of the scan pulse signal CLK.
  • the output pin of the gate modulation module 100 is used to output the adjustment reference voltage, and the first level reference input pin of the level shift module Level Shifter is used to receive the adjustment reference voltage.
  • the display driving circuit uses the gate control module 100 to adjust the high-level reference voltage VGH to obtain multiple adjustment reference voltages.
  • Each adjustment reference voltage is used to control the high-level amplitude of a scan pulse signal. value, it is possible to reduce the difference in charging rates of display pixels 210 in different rows, thereby improving the horizontal stripe defects of the display screen.
  • the display driving circuit may also include an output discharge module XAO and a logic module Logic Block.
  • the output discharge module XAO is used to pull all scan pulse signals CLK to the high-level reference voltage VGH when the entire display panel is in a shutdown state, so that the pixel capacitance in the display pixel 210 can be discharged.
  • the logic module Logic Block can be used to pull up the scan pulse signal to set the shutdown state.
  • the level conversion module Level Shifter can be electrically connected (that is, set between) the logic module Logic Block and the output discharge module XAO.
  • the scan pulse signal after adjusting the high-level amplitude can be output from the output discharge module XAO to obtain the scan drive signal, respectively represented as CLK1Out ⁇ CLKN Out, and the frame start drive signal STV Out.
  • the gate modulation module 100 can be used to adjust the voltage division of the scan path for driving the display pixel with the scan drive signal to adjust the first level (ie, high level) of the scan pulse signal CLK corresponding to the scan path. ) amplitude. That is to say, a voltage divider can be connected to the scan path, for example, a resistor can be connected to realize voltage division, or other devices can be connected to realize voltage division, which are not specifically limited in the embodiments of the present disclosure.
  • accessing the voltage divider can change the high-level amplitude of the scan pulse signal CLK corresponding to the scan channel, thereby changing the voltage applied to the gate of the thin film transistor in the scan channel, and also changing the voltage flowing through the gate of the thin film transistor.
  • the current that is, the current of the scanning path
  • the current of the scanning path can weaken or eliminate the charging rate difference caused by the equivalent impedance by adjusting the access voltage divider. Due to process differences, the equivalent impedance of the scanning path is different, which in turn leads to the current difference of the scanning path.
  • the access voltage divider By adjusting the access voltage divider, the current of the scanning path can be adjusted, thereby reducing the gate turn-on of the thin film transistor between display pixels 210 in different rows. time difference, Reducing the charging rate difference between display pixels 210 in different rows can improve the problem of horizontal stripes on the display screen.
  • the level shift module Level Shifter may include a scan pulse output pin, and the scan pulse output pin may be electrically connected to the input pin of the gate modulation module 100 . Furthermore, the gate modulation module 100 can be connected to the scan path and can be used to adjust the partial voltage of the scan path.
  • FIG. 6 is a schematic structural block diagram of yet another display driving circuit provided by an embodiment of the present disclosure.
  • the output discharge module XAO may be electrically connected (that is, disposed) between the level conversion module Level Shifter and the gate modulation module 100 .
  • the gate modulation module 100 may also be disposed between the level conversion module Level Shifter and the output discharge module XAO.
  • N scan pulse signals output from the output discharge module XAO are divided by N channels through the gate modulation module 100, and N high-level amplitude-adjusted scan drive signals can be obtained, respectively expressed as CLK1Out ⁇ CLKN Out.
  • the display driving circuit adjusts the voltage division of the scan path through the gate modulation module 100 to adjust the high-level amplitude of the scan pulse signal CLK corresponding to the scan path.
  • the adjustment of the access voltage divider can change the high-level amplitude of the scan drive signal corresponding to the scan channel, thereby changing the voltage applied to the gate of the thin film transistor in the scan channel, and also changing the current flowing through the gate of the thin film transistor. , that is, the current of the scanning path.
  • the access voltage divider By adjusting the access voltage divider, the charging rate difference caused by the equivalent impedance can be weakened or eliminated, and the problem of horizontal stripes on the display screen can be improved.
  • the gate modulation module 100 may include an adjustment unit, the adjustment unit may be used to adjust the amplitude of the first level (ie, high level) of the scan pulse signal CLK, and the adjustment unit and the scan pulse signal may One-to-one correspondence.
  • the adjustment unit may be used to adjust the amplitude of the first level (ie, high level) of the scan pulse signal CLK, and the adjustment unit and the scan pulse signal may One-to-one correspondence.
  • FIG. 7 is a schematic structural block diagram of a gate modulation module provided by an embodiment of the present disclosure.
  • the gate modulation module 100 includes N (an integer greater than 1) adjustment units, which are the first adjustment unit 110, the second adjustment unit 120, the third adjustment unit 130... the Nth adjustment unit 1N0,
  • the high-level reference voltage VGH is adjusted by each adjustment unit of the gate modulation module 100 to obtain the adjusted reference voltages VGHO1 ⁇ VGHON. Adjusting the reference voltages VGHO1 to VGHON can be used to adjust the high-level amplitudes of the scan pulse signals CLK1 to CLKN.
  • FIG. 8 is a schematic structural block diagram of another gate modulation module provided by an embodiment of the present disclosure.
  • the scan pulse signal CLK1 passes through the first adjustment unit 110 to obtain CLK1Out, ..., and the scan pulse signal CLKN passes through the Nth adjustment unit 1N0 to obtain CLKN Out.
  • the adjustment unit may include at least one switch.
  • the switch can be used to receive the modulation control signal and turn on or off based on the modulation control signal.
  • the turning on of the switch can open the path of the regulating unit to turn on the regulating function.
  • the closing of the switch can disconnect the path of the regulating unit to turn off the regulating function.
  • the adjustment unit may include a plurality of switches connected in parallel, and at least one fixed resistor and/or an adjustable resistor may be included (ie, provided) between any two switches connected in parallel.
  • Fixed resistors and adjustable resistors can divide voltage and regulate current.
  • FIG. 9 is a schematic structural diagram of an adjustment unit provided by an embodiment of the present disclosure.
  • each adjustment unit includes n switches and n resistors.
  • the resistors can be fixed resistors or adjustable resistors.
  • the resistances are represented by R0 ⁇ Rn respectively, n is any natural number greater than 1.
  • n switches can receive n modulation control signals, respectively represented as D0 ⁇ Dn.
  • Each adjustment unit corresponds to a group of modulation control signals.
  • Each group of modulation control signals includes D0 ⁇ Dn.
  • n switches can realize multiple adjustments of the adjustment unit. gear to increase the adjustment capability range of the adjustment unit.
  • Each adjustment unit correspondingly outputs an adjustment reference voltage VGHOQ, 1 ⁇ Q ⁇ N.
  • the modulation control signal can be expressed in binary form. For example, “1" can represent the switch-on modulation control signal, and “0" can represent the switch-off modulation control signal. Then the modulation control signal corresponding to each adjustment unit includes a code composed of a set of binary digits.
  • Table 1 is a schematic diagram of a binary modulation control signal.
  • FIG. 10 is a signal timing diagram of a display driving circuit provided by an embodiment of the present disclosure.
  • the values between VGHO1, VGHO2, VGHO3...VGHON are not exactly the same, and the corresponding high-level amplitudes between CLK1, CLK2, CLK3...CLKN are also not exactly the same.
  • the current of the scanning path can be adjusted, thereby reducing the difference in the gate turn-on time of the thin film transistor between the display pixels 210 in different rows, reducing the charging rate difference between the display pixels 210 in different rows, and improving the display screen. Horizontal stripe problem.
  • the adjustment unit may include a plurality of switches connected in parallel, each switch being located on the channel Fixed resistors and/or adjustable resistors can be connected in series on the road. The switch and the resistor are connected in series. The switch and the resistor in series can form an adjustment gear, which can be used to adjust the divided voltage of the access scan path.
  • FIG. 11 is a schematic structural diagram of another adjustment unit provided by an embodiment of the present disclosure.
  • each adjustment unit includes n switches and n resistors.
  • the resistors can be fixed resistors or adjustable resistors.
  • the resistances are represented by R0 ⁇ Rn respectively, n is any natural number greater than 1.
  • Resistors and switches are connected in series.
  • the series-connected resistors and switches are connected in parallel with other series-connected resistors and switches to form n adjustment gears.
  • n switches can receive n modulation control signals, respectively represented as D0 ⁇ Dn.
  • Each adjustment unit corresponds to a group of modulation control signals.
  • Each group of modulation control signals includes D0 ⁇ Dn.
  • n switches can realize multiple adjustments of the adjustment unit. gear to increase the adjustment capability range of the adjustment unit.
  • Each adjustment unit can correspondingly output a scan pulse signal CLKQ Out, 1 ⁇ Q ⁇ N.
  • Table 2 is a schematic diagram of another binary modulation control signal.
  • the display driving circuit may further include: a modulation control module.
  • the modulation control module may be used to provide a modulation control signal to the gate modulation module 100 .
  • the modulation control signal may be used to control the gate modulation module 100 to adjust the scan pulse signal.
  • the amplitude of the first level i.e., high level).
  • the modulation control signal can be programmed into the modulation control module and sent to the gate modulation module 100 according to the display control instructions during the display driving process.
  • the existing high-level reference voltage is 37V.
  • the high-level reference voltage can be set to 40V.
  • control the opening of the switch in the adjustment unit increase the resistance connected to the scanning loop, and act as a voltage divider to reduce the high-level amplitude of the scanning pulse signal. Control the corresponding number and position according to specific needs.
  • the opening of the switch It can also be based on the modulation control signal to control the opening of the switch in the adjustment unit, increase the resistance connected to the high-level reference voltage adjustment loop, and act as a voltage divider to achieve the effect of lowering the high-level reference voltage, thereby controlling the adjustment.
  • the high-level amplitude of the low scan pulse signal controls the opening of the corresponding number and corresponding position switches according to specific needs.
  • the high-level amplitude of the scan pulse signal can be achieved by pulling up the high-level reference signal in advance, then lowering the value of the high-level reference signal according to the specific situation, or directly lowering the high-level amplitude of the scan pulse signal.
  • value adjustable properties thereby adjusting the current of the scanning path, thereby reducing the difference in the gate conduction performance of the thin film transistor between display pixels in different rows, reducing the charging rate difference between the display pixels in different rows, and improving the horizontal aspect of the display screen. tattoo problem.
  • the switch may include at least one transistor (eg, the thin film transistor described in the above embodiments).
  • the thin film transistors can be used as switching devices, and the process is mature and stable.
  • the switches may also adopt other forms of switching devices, which are not specifically limited in the embodiments of the present disclosure.
  • FIG. 12 is a schematic flow chart of a display driving method provided by the embodiment of the present disclosure. As shown in Figure 12, the display driving method includes:
  • S301 Receive display control instructions.
  • the display control instructions may be issued by the control motherboard or by other control chips, which are not specifically limited in the embodiments of the present disclosure.
  • the amplitude of the first level among the first level and the second level of the received scan pulse signal is adjusted through the gate modulation module, To reduce the current difference between different scanning paths.
  • the scanning path is a path through which the scanning driving signal drives the display pixel; the first level is a high level relative to the second level.
  • the high-level amplitude of the pulse signal CLK in the existing display drive circuit is fixed and cannot be adjusted.
  • the high-level amplitudes of CLK1 to CLK6 are all unadjustable.
  • the gate voltages of the thin film transistors corresponding to the display pixels are different, which ultimately leads to differences in the charging rates of the pixel electrodes, resulting in poor horizontal stripes on the display screen.
  • the display driving circuit provided by the embodiment of the present disclosure is provided with a gate modulation module 100.
  • the gate modulation module 100 can adjust the high-level amplitude of the scan pulse signal CLK.
  • the high-level amplitude of the scan pulse signal CLK by adjusting the high-level amplitude of the scan pulse signal CLK, according to the difference in equivalent states, it is ensured that the accumulated charge amount of the gates of the thin film transistors corresponding to the display pixels in different rows is relatively even, so as to ensure that the The turn-on time of the thin film transistors in the same row is relatively average, which can reduce the difference in the charging time of the pixel electrodes in different rows, ensure that the charging rates of the pixel electrodes in different rows are more balanced, and will not cause the difference in charging rates of the pixel electrodes in different rows.
  • the horizontal lines are bad.
  • the display driving method provided by the embodiment of the present disclosure uses the gate modulation module 100 to adjust the high-level amplitude of the received scan pulse signal CLK.
  • the gate voltage of the thin film transistor of the display pixel is adjusted to ensure that the gate of the thin film transistor is continuously turned on within the required period of time to ensure that the charging time of the pixel electrode is not affected.
  • the influence of the difference in equivalent impedance can reduce the difference in charging rates between display pixels in different rows, and can improve the horizontal stripe defects of the display screen.
  • the display control instruction includes a modulation control signal.
  • the display driving method may further include:
  • a test fixture or an electrical signal acquisition device can be used to test the current of each scanning path corresponding to the scanning pulse signal to obtain the corresponding initial scanning current.
  • the scan paths that require compensation current and the corresponding compensation current values are determined.
  • the compensation current value can be a positive number or a negative number, which is mainly determined based on the difference in initial scanning current between different scanning paths.
  • a modulation control signal is generated according to the scanning path that requires compensation current and the corresponding compensation current value.
  • the modulation control signal includes the address of the scanning path that requires compensation current and the corresponding compensation current value.
  • control program for collecting the initial scan current and generating the modulation control signal can be executed during the startup phase of the display device, or it can be executed every time or at set intervals. The number of executions can be based on the operating computing power of the display device. set up. That is, the control program for collecting the initial scanning current and generating the modulation control signal can be run while the user is using the display device.
  • the process of collecting the initial scan current and generating the modulation control signal is only performed during the debugging stage before the display device or display panel leaves the factory, and the debugged modulation control signal is burned into the modulation control module for the user to use. Adjust the scan pulse signal while using the display device.
  • the above step S302 may include:
  • the amplitude of the first level (ie, high level) of the received scan pulse signal is adjusted based on the modulation control signal.
  • the gate modulation module can adjust the high-level amplitude of the scan pulse signal based on the modulation control signal.
  • the high-level voltage compensation of the scan pulse signal scan paths with current differences can be realized.
  • the high-level amplitude of the scanning pulse signal can be reduced or increased, which is mainly determined based on the compensation current value.
  • the display driving method provided by the embodiment of the present disclosure is that the high-level amplitude of the pulse signal CLK in the existing display driving circuit is fixed and cannot be adjusted.
  • the difference in the initial scan current determines the scan path that needs to be compensated current and the corresponding compensation current value.
  • a modulation control signal is generated.
  • the gate modulation module 100 adjusts based on the modulation control signal.
  • the amplitude of the high level of the scanning pulse signal CLK When process fluctuations lead to differences in the equivalent impedances of the scanning paths of the display pixels, testing the differences in the initial scanning currents of the scanning paths can reflect the differences in the equivalent impedances of different scanning paths.
  • the initial scanning current Difference determine the adjustment amplitude of the high-level amplitude of the scan pulse signal CLK, and adjust the high-level amplitude of the scan pulse signal CLK, which can reduce the difference in charging rates between display pixels in different rows and improve the quality of the display screen. Bad transverse lines.
  • adjusting the amplitude of the first level among the first level and the second level of the received scan pulse signal through the gate modulation module may include:
  • the first level (ie, high level) reference voltage is adjusted to output the adjusted reference voltage.
  • the gate modulation module 100 can adjust the high-level amplitude of the scan pulse signal CLK by adjusting the high-level reference voltage.
  • the gate modulation module 100 adjusts the high-level reference voltage to obtain an adjusted reference voltage. Adjusting the reference voltage can control the high-level amplitude of the corresponding scan pulse signal.
  • the adjusted reference voltage can correspond to the scan pulse signal one-to-one.
  • the existing display driving circuit is only provided with one high-level reference voltage signal line.
  • the display driving circuit provided by the embodiment of the present disclosure can obtain multiple adjustment reference voltages through the adjustment of the gate modulation module 100. Each adjustment The reference voltage is used to control the high-level amplitude of a scan pulse signal, which can reduce the difference in charging rates of display pixels in different rows, thereby improving the horizontal stripes of the display screen.
  • the gate modulation module is used to adjust the amplitude of the first level among the first level and the second level of the received scan pulse signal, including:
  • Adjust the partial voltage of the scan path to adjust the first level of the scan pulse signal corresponding to the scan path (i.e., high level) amplitude.
  • a voltage divider can be added to the scan path, for example, a resistor can be added to implement voltage division, or other devices can be added to implement voltage division, which are not specifically limited in the embodiments of the present disclosure.
  • Accessing the voltage divider can change the high-level amplitude of the scan drive signal corresponding to the scan path, thereby changing the voltage applied to the gate of the thin film transistor in the scan path, and also changing the current flowing through the gate of the thin film transistor, that is, The current in the scanning path can be weakened or eliminated by adjusting the access voltage divider to weaken or eliminate the charging rate difference caused by equivalent impedance.
  • the equivalent impedance of the scanning path is different, which in turn leads to the current difference of the scanning path.
  • the access voltage divider By adjusting the access voltage divider, the current of the scanning path can be adjusted, thereby reducing the thin film transistor between different rows of display pixels.
  • the difference in gate turn-on time can reduce the difference in charging rates between display pixels in different rows, and can improve the problem of horizontal stripes on the display screen.
  • FIG. 13 is a schematic structural block diagram of a display driving controller provided by an embodiment of the present disclosure. As shown in Figure 13, the display driver controller includes:
  • Memory 401 a computer program is stored in memory 401;
  • the processor 402 is configured to implement the display driving method described in the second aspect when executing a computer program.
  • the display driving controller can be provided on the control motherboard of the display device, and the display driving controller can be provided in the display device in the form of a chip, which is not specifically limited in the embodiments of the present disclosure.
  • FIG. 14 is a schematic structural block diagram of a display device provided by an embodiment of the present disclosure.
  • the display device includes: a display driving circuit 501 as described in the first aspect, and/or a display driving controller 502 as described in the third aspect.
  • the display driving circuit 501 may be a driving chip in the display device, and the display driving controller 502 may be provided on the control motherboard of the display device.
  • the display device provided by the embodiment of the present disclosure includes a display driving circuit 501 and a display driving controller 502.
  • the display driving controller 502 can control the operation of the display driving circuit 501.
  • the display device may further include:
  • the display panel may have a display area and a non-display area.
  • the display pixels located in the display area of the display panel that is, the display pixels described in the above embodiments, can be disposed in the display area of the display panel.
  • Control circuit board the control circuit board can be electrically connected with the display panel.
  • the display panel may be a liquid crystal display panel, an organic light-emitting display panel or an LED display panel, which are not specifically limited in the embodiments of the present disclosure.
  • the control circuit board can be understood as the control main board of the display device, and the display driving circuit included in the display device can be bound to the non-display area of the display panel.
  • the display driving circuit 501 can be bound to the non-display area of the display panel in the form of a driving chip.
  • the display panel can be a flexible display panel, and the non-display area bound to the display driving circuit 501 can be bent to the display panel. the back of the panel to shrink the bezels of the display device.
  • the display driving circuit 501 included in the display device can also be disposed on the control circuit board, and can be reasonably designed according to the space of the specific display device.
  • the display device may be a smart phone, a notebook computer, a tablet computer, a television or other display, etc., and the embodiments of the present disclosure are not specifically limited.
  • embodiments of the present disclosure may be provided as methods, systems, or computer program products. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment that combines software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk memory, CD-ROM, optical storage, etc.) having computer-readable program code embodied therein.
  • computer-readable storage media including, but not limited to, disk memory, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory that causes a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction means, the instructions
  • the device implements the functions specified in a process or processes of the flowchart and/or a block or blocks of the block diagram.
  • These computer program instructions may also be loaded onto a computer or other programmable data processing device, causing a series of operating steps to be performed on the computer or other programmable device to produce computer-implemented processing, thereby executing on the computer or other programmable device.
  • Instructions are provided for implementing a Process or processes and/or block diagram The steps of a function specified in a block or blocks.
  • Embodiments of the present disclosure also provide a computer program product.
  • the computer program product includes computer software instructions.
  • the processing device executes the process of the display driving method.
  • a computer program product includes one or more computer instructions. When computer program instructions are loaded and executed on a computer, processes or functions according to embodiments of the present disclosure are produced, in whole or in part.
  • the computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • Computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, e.g., computer instructions may be transmitted from a website, computer, server or data center via a wired link (e.g. Coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) means to transmit to another website, computer, server or data center.
  • a wired link e.g. Coaxial cable, optical fiber, digital subscriber line (DSL)
  • wireless such as infrared, wireless, microwave, etc.
  • Computer-readable storage media can be any available media that a computer can store, or a data storage device such as a server or data center integrated with one or more available media. Available media may be magnetic media (eg, floppy disk, hard disk, tape), optical media (eg, DVD), or semiconductor media (eg, solid state disk (SSD)), etc.
  • Available media may be magnetic media (eg, floppy disk, hard disk, tape), optical media (eg, DVD), or semiconductor media (eg, solid state disk (SSD)), etc.
  • the disclosed equipment, devices and methods can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or integrated. to another system, or some features can be ignored, or not implemented.
  • the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical, mechanical or other forms.
  • a unit described as a separate component may or may not be physically separate.
  • a component shown as a unit may or may not be a physical unit, that is, it may be located in one place, or it may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in various embodiments of the present disclosure can be integrated into one processing unit, Each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above integrated units can be implemented in the form of hardware or software functional units.
  • Integrated units may be stored in a computer-readable storage medium if they are implemented in the form of software functional units and sold or used as independent products.
  • the technical solution of the present disclosure is essentially or contributes to the existing technology, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present disclosure.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program code. .

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Abstract

一种显示驱动电路、显示驱动方法及显示设备，属于显示技术领域。其中，显示驱动电路包括：选通调制模块(100)，选通调制模块(100)用于调节接收到的扫描脉冲信号(CLK)的高电平的幅值，扫描脉冲信号(CLK)用于驱动显示面板(200)的显示像素(210)。如此，在工艺波动导致显示像素(210)的扫描通路的等效阻抗存在差异的情况下，可以通过调节扫描脉冲信号(CLK)的高电平的幅值，减小不同行的显示像素(210)之间的充电率差异，进而可以改善显示画面的横纹不良。

Description

一种显示驱动电路、显示驱动方法及显示设备
本公开要求于2022年5月23日提交的申请号为202210562881.0、发明名称为“一种显示驱动电路、显示驱动方法及相关设备”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示驱动电路、显示驱动方法及显示设备。
背景技术
随着显示技术的快速发展，显示产品逐渐向高分辨率和高刷新率演变，随之带来的显示技术难度也是呈数量级的递增。
由于工艺波动，不同扫描脉冲信号对应的通路阻抗略有差异。随着高端显示产品刷新率的增加，每行像素充电时间随之减小，每行像素之间的充电率容易存在差异，从而引起像素行之间的显示差异，形成横纹不良。
发明内容
本公开实施例提供一种显示驱动电路、显示驱动方法及显示设备，能够改善像素行之间的充电率差异引起的横纹不良。
一方面，提供了一种显示驱动电路，所述显示驱动电路包括：
选通调制模块，所述选通调制模块与显示面板中的显示像素电连接，并用于接收扫描脉冲信号，且用于调节所述扫描脉冲信号的第一电平和第二电平中第一电平的幅值，所述第一电平相对于所述第二电平为高电平；
其中，所述扫描脉冲信号用于驱动显示面板的显示像素显示画面。
可选的，所述选通调制模块还用于接收第一电平参考电压，并用于调节第一电平参考电压，以输出调节参考电压；
其中，所述调节参考电压用于调节所述扫描脉冲信号的第一电平的幅值。
可选的，所述调节参考电压与所述扫描脉冲信号一一对应。
可选的，所述选通调制模块用于调节对所述扫描驱动信号驱动所述显示像素的扫描通路的分压，以调节所述扫描通路对应的所述扫描脉冲信号的第一电 平的幅值。
可选的，所述选通调制模块包括：调节单元，所述调节单元用于调节所述扫描脉冲信号的第一电平的幅值，且所述调节单元与所述扫描脉冲信号一一对应。
可选的，所述调节单元包括：至少一个开关。
可选的，所述调节单元包括：多个并联的所述开关；任意并联的两个所述开关之间包括：至少一个固定电阻和/或可调电阻。
可选的，所述调节单元包括：多个并联的所述开关，每个所述开关所在通路上均串联有固定电阻和/或可调电阻。
可选的，所述开关包括：至少一个晶体管。
可选的，所述显示驱动电路还包括：电平转换模块；
所述电平转换模块包括第一电平参考输入引脚，所述第一电平参考输入引脚与所述选通调制模块的输出引脚电连接。
可选的，所述显示驱动电路还包括：电平转换模块；
所述电平转换模块包括扫描脉冲输出引脚，所述扫描脉冲输出引脚与所述选通调制模块的输入引脚电连接。
可选的，所述显示驱动电路还包括：输出放电模块；
所述输出放电模块电连接于所述电平转换模块与所述选通调制模块之间；或，所述选通调制模块电连接于所述电平转换模块与所述输出放电模块之间。
可选的，所述显示驱动电路还包括：调制控制模块；
所述调制控制模块用于向所述选通调制模块提供调制控制信号，所述调制控制信号用于控制所述选通调制模块调节所述扫描脉冲信号的第一电平的幅值。
另一方面，提供了一种显示驱动方法，应用于如上述一方面所述的显示驱动电路，所述显示驱动方法包括：
接收显示控制指令；
基于所述显示控制指令，驱动显示面板的显示像素显示画面；
其中，在基于所述显示控制指令，驱动显示面板的显示像素显示画面的过程中，通过选通调制模块调节接收到的扫描脉冲信号的第一电平和第二电平中第一电平的幅值，以减小不同的扫描通路之间的电流差异；
并且，所述扫描通路为所述扫描驱动信号驱动所述显示像素的通路；所述 第一电平相对于所述第二电平为高电平。
可选的，所述显示控制指令包括：调制控制信号；在所述接收显示控制指令之前，所述显示驱动方法还包括：
采集所述扫描通路的电流，得到初始扫描电流；
根据不同的所述扫描通路之间的所述初始扫描电流的差异，确定需要补偿电流的所述扫描通路以及对应的补偿电流数值；
根据需要补偿电流的所述扫描通路以及对应的补偿电流数值，生成调制控制信号；
所述在基于所述显示控制指令，驱动显示面板的显示像素显示画面的过程中，通过选通调制模块调节接收到的扫描脉冲信号的第一电平和第二电平中第一电平的幅值，包括：
在基于所述显示控制指令，驱动显示面板的所述显示像素显示画面的过程中，基于所述调制控制信号调节接收到的所述扫描脉冲信号的第一电平的幅值。
可选的，所述通过选通调制模块调节接收到的扫描脉冲信号的第一电平和第二电平中第一电平的幅值，包括：
调节第一电平参考电压，以输出调节参考电压；
基于所述调节参考电压，调节所述扫描脉冲信号的第一电平的幅值。
可选的，所述通过选通调制模块调节接收到的扫描脉冲信号的第一电平和第二电平中第一电平的幅值，包括：
调节对所述扫描通路的分压，以调节所述扫描通路对应的所述扫描脉冲信号的第一电平的幅值。
又一方面，提供了一种显示驱动控制器，所述显示驱动控制器包括：
存储器，所述存储器中存储有计算机程序；
处理器，所述处理器用于执行所述计算机程序时实现如上述另一方面所述的显示驱动方法。
再一方面，提供了一种显示装置，所述显示装置包括：
如上述一方面所述的显示驱动电路，和/或，如上述又一方面所述的显示驱动控制器。
可选的，所述显示装置还包括：
显示面板，具有显示区和非显示区；
位于所述显示面板的显示区的显示像素；
控制电路板，所述控制电路板与所述显示面板电连接；
其中，所述显示装置包括的显示驱动电路绑定于所述显示面板的非显示区；或，所述显示装置包括的显示驱动电路设置于所述控制电路板上。
附图说明
图1为本公开实施例提供的一种显示驱动电路的示意性结构框图；
图2为本公开实施例提供的一种显示面板的栅扫描电路的示意性结构框图；
图3为本公开实施例提供的一种扫描脉冲信号驱动显示像素的局部等效电路图；
图4为本公开实施例提供的一种显示面板的刷新频率与充电时间的对应示意图；
图5为本公开实施例提供的另一种显示驱动电路的示意性结构框图；
图6为本公开实施例提供的又一种显示驱动电路的示意性结构框图；
图7为本公开实施例提供的一种选通调制模块示意性结构框图；
图8为本公开实施例提供的另一种选通调制模块的示意性结构框图；
图9为本公开实施例提供的一种调节单元的示意性结构图；
图10为本公开实施例提供的一种显示驱动电路的信号时序示意图；
图11为本公开实施例提供的另一种调节单元的示意性结构图；
图12为本公开实施例提供的一种显示驱动方法的示意性流程图；
图13为本公开实施例提供的一种驱动控制器的示意性结构框图；
图14为本公开实施例提供的一种显示装置的示意性结构框图。
具体实施方式
为了更好的理解本说明书实施例提供的技术方案，下面通过附图以及具体实施例对本说明书实施例的技术方案做详细的说明，应当理解本说明书实施例以及实施例中的具体特征是对本说明书实施例技术方案的详细的说明，而不是对本说明书技术方案的限定，在不冲突的情况下，本说明书实施例以及实施例中的技术特征可以相互组合。
在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何 其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。术语“两个以上”包括两个或大于两个的情况。术语“和/或”，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
随着显示技术的快速发展，显示产品逐渐向高分辨率和高刷新率演变，随之带来的显示技术难度也是程数量级的递增。由于工艺波动，扫描脉冲信号对应的通路阻抗略有差异。随着高端产品刷新率的增加，每行像素充电时间随之减小，每行像素之间的充电率容易存在差异，从而引起像素行之间的显示差异，形成横纹不良。
有鉴于此,本公开实施例提供一种显示驱动电路、显示驱动方法及显示设备，能够改善像素行之间的充电率差异引起的横纹不良。
本公开实施例的第一方面，提供一种显示驱动电路，图1为本公开实施例提供的一种显示驱动电路的示意性结构框图。如图1所示，本公开实施例提供的显示驱动电路，包括：选通调制模块100。
选通调制模块100与显示面板200中的显示像素210电连接，并用于接收扫描脉冲信号CLK，且用于调节该扫描脉冲信号CLK的第一电平和第二电平中第一电平的幅值，该第一电平相对于第二电平可以为高电平。下述实施例均以高电平表示第一电平，低电平表示第二电平为例进行说明。
其中，该扫描脉冲信号CLK用于驱动显示面板200的显示像素210，以实现显示像素的栅扫描，显示像素210可以被点亮，并显示画面。
示例性的，图2为本公开实施例提供的一种显示面板的栅扫描电路的示意性结构框图。如图2所示，显示面板的栅扫描电路可以采用阵列基板行驱动(Gate on Array，GOA)架构。扫描脉冲信号CLK可以包括第一扫描脉冲信号CLK1、第二扫描脉冲信号CLK2、第三扫描脉冲信号CLK3、第四扫描脉冲信号CLK4、第五扫描脉冲信号CLK5和第六扫描脉冲信号CLK6。显示面板中的每行显示像素210可以对应一个GOA，图2示意性的示出6个GOA，分别是GOA1～GOA6。
其中，每个GOA可以包括脉冲输入引脚clk、高电平输入引脚VDD、低电 平输入引脚Vss、帧起始信号引脚IN和级连引脚R。脉冲输入引脚clk用于接收扫描脉冲信号CLK，高电平输入引脚VDD用于接收高电平信号，高电平信号可以有两个，分别是第一高电平信号VDD1和第二高电平信号VDD2，第一高电平信号VDD1和第二高电平信号VDD2在数值上可以相同，只是通过两条信号线分别进行传输，对应的高电平输入引脚VDD分别用VDD(1)和VDD(2)表示，低电平输入引脚Vss用于接收低电平信号Vss，帧起始信号引脚IN用于接收帧起始信号STV，级连引脚R用于接收级连反馈信号。其中，低电平信号和高电平信号也是相对而言的。由于显示像素210是逐行扫描的，因此扫描每行显示像素210的起始时间不同。又由于扫描完成后需要进行脉冲复位，因此需要未进行扫描的GOA对已经扫描完成的GOA进行级连反馈，以将扫描完成的GOA的脉冲复位。另外需要说明的是，显示面板200包括的所有行显示像素210均可以由CLK1～CLK6提供扫描脉冲信号。
示例性的，图3为本公开实施例提供的一种扫描脉冲信号驱动显示像素的局部等效电路图。如图3所示，第一扫描脉冲信号CLK1可以对应电连接第一薄膜晶体管T1的栅极，第一薄膜晶体管T1可以代表显示像素210的驱动器件，第一薄膜晶体管T1的第一极可以与数据信号线Data Line电连接，第一薄膜晶体管T1的第二极可以电连接像素电极。第二扫描脉冲信号CLK2可以对应电连接第二薄膜晶体管T2的栅极，第二薄膜晶体管T2可以代表显示像素210的驱动器件，第二薄膜晶体管T2的第一极可以与数据信号线Data Line电连接，第二薄膜晶体管T2的第二极可以电连接像素电极。
其中，第一扫描脉冲信号CLK1与对应的像素电极的扫描通路的等效阻抗为第一电阻R01，第二扫描脉冲信号CLK2与对应的像素电极的扫描通路的等效阻抗为第二电阻R02，第一电阻R01的分压为V1，第二电阻R02的分压为V2。数据信号线Data Line可以用于分别向第一薄膜晶体管T1和第二薄膜晶体管T2提供数据信号，数据信号对像素电极进行充电。第一薄膜晶体管T1接收到的数据信号与对应电连接的像素电极的充电电流为第一充电电流i1，第二薄膜晶体管T2接收到的数据信号与对应电连接的像素电极的充电电流为第二充电电流i2。第一扫描脉冲信号CLK1与第二扫描脉冲信号CLK2的高电平的幅值相同，由于第一电阻R01和第二电阻R02的分压情况，到达第一薄膜晶体管T1的栅极电压可以是扫描脉冲信号的高电平的幅值减去分压。
目前显示面板的内部电路线路成型工艺通常包括：金属沉积、曝光和刻蚀 等多个步骤，每个步骤微小的不均匀都会造成每个扫描通路的等效阻抗的差异。若由于工艺的波动，引起第一电阻R01的阻值和第二电阻R02的阻值产生差异，则第一充电电流i1和第二充电电流i2即会存在差异。进一步，不同行的显示像素210的像素电极的充电时间率即会存在差异，造成显示画面的横纹不良。
示例性的，结合图2和图3，CLK1～CLK6的通路内每个通路的等效阻抗R01～R06用于表示由于工艺波动导致的阻抗差异。图4为本公开实施例提供的一种显示面板的刷新频率与充电时间的对应示意图。如图4所示，随着高端产品的显示面板的刷新频率的增加，针对每行显示像素210充电时间随之减小。
例如，刷新频率从60赫兹(Hz)到576Hz，在扫描脉冲信号CLK对显示像素210的驱动器件的栅极进行驱动，数据信号线Data Line对显示像素210的像素电极在一个周期1H内的充电时间由7.4微秒(us)减小到0.72us，充电时间产生了数量级的变化。较短的充电时间使得每个显示像素210的充电率对通路的等效阻抗的差异极其敏感，扫描通路的等效阻抗差异会引起薄膜晶体管的栅极电压的差异，影响薄膜晶体管的开启时间或导通性能，进而导致数据信号线Data Line的充电电流i1和i2存在差异，最终导致充电率的差异，尤其在纯灰阶画面形成横纹不良。
针对现有显示驱动电路中，扫描脉冲信号CLK的高电平幅值固定不可调，例如，CLK1～CLK6的高电平幅值均不可调，则在工艺波动导致显示像素的扫描通路的等效阻抗存在差异的情况下，显示像素对应的薄膜晶体管的栅极电压不同，最终导致像素电极的充电率差异，造成显示画面横纹不良。本公开实施例提供的显示驱动电路，设置有选通调制模块100，选通调制模块100可以调节扫描脉冲信号CLK的高电平的幅值，在工艺波动导致显示像素210的扫描通路的等效阻抗存在差异的情况下，通过调节扫描脉冲信号CLK的高电平幅值，来调节显示像素210的薄膜晶体管的栅极电压，保证薄膜晶体管在需要的时间段内持续开启，以保证像素电极的充电时间不受等效阻抗差异的影响，能够减小不同行的显示像素210之间的充电率差异，可以改善显示画面的横纹不良。
可以理解为：通过调节扫描脉冲信号CLK的高电平幅值，来根据等效差异，保证不同行的显示像素210对应的薄膜晶体管的栅极累积的电荷量较为平均，以保证不同行的薄膜晶体管的开启时间较为平均。如此，即能够减少不同行的像素电极的充电时间的差异，保证不同行的像素电极的充电率较为均衡，不会产生由于不同行的像素电极的充电率差异造成的横纹不良。
本公开实施例提供的显示驱动电路，设置选通调制模块100，通过选通调制模块100调节接收到的扫描脉冲信号CLK的高电平的幅值，在工艺波动导致显示像素210的扫描通路的等效阻抗存在差异的情况下，通过调节扫描脉冲信号CLK的高电平幅值，来调节显示像素210的薄膜晶体管的栅极电压，保证薄膜晶体管在需要的时间段内持续开启，以保证像素电极的充电时间不受等效阻抗差异的影响，能够减小不同行的显示像素210之间的充电率差异，可以改善显示画面的横纹不良。
在一些实施方式中，选通调制模块100还可以用于接收第一电平(即，高电平)参考电压，并可以用于调节第一电平参考电压，以输出调节参考电压。
其中，调节参考电压可以用于调节扫描脉冲信号CLK的第一电平的幅值。
需要说明的是，扫描脉冲信号CLK的高电平的幅值是由高电平参考电压决定的。示例性的，一种显示面板的高电平参考电压为12V，则驱动显示面板的行扫描的扫描脉冲信号CLK的高电平的幅值可以为12V。选通调制模块100对于扫描脉冲信号CLK的高电平的幅值的调节，可以通过调节高电平参考电压来实现。选通调制模块100对高电平参考电压进行调节，得到调节参考电压，调节参考电压可以控制对应的扫描脉冲信号CLK的高电平的幅值。
可选的，调节参考电压可以与扫描脉冲信号一一对应，可以实现高电平参考电压对扫描脉冲信号的一对一单独调节。
通常，现有的显示驱动电路一般只设置有一个高电平参考电压信号线，本公开实施例提供的显示驱动电路，通过选通调制模块100的调节，可以得到多个调节参考电压，每个调节参考电压可以用于控制一个扫描脉冲信号CLK的高电平的幅值，可以实现减少不同行显示像素的充电率差异，从而改善显示画面的横纹不良。
在一些实施方式中，图5为本公开实施例提供的另一种显示驱动电路的示意性结构框图。如图5所示，显示驱动电路还包括：电平转换模块Level Shifter，电平转换模块Level Shifter包括第一电平(即，高电平)参考输入引脚，第一电平参考输入引脚与选通调制模块100的输出引脚电连接。
示例性的，如图5所示，高电平参考电压VGH通过选通调制模块100的调节可以得到N个调节参考电压，分别是VGHO1～VGHON，N可以是大于零的自然数，对应的扫描脉冲信号CLK的数量也是N个，分别为CLK1～CLKN。
通常，扫描脉冲信号CLK在时间控制电路(Timming Controller，T-Con) 输出时的高电平的幅值较低，例如3.3伏特(V)，但是显示面板需要的扫描脉冲信号CLK的高电平幅值通常较高，例如12V、24V或37V，该高电平幅值大小可以根据不同显示面板的尺寸和像素设计确定。故，电平转换模块Level Shifter可以对T-Con输出的扫描脉冲信号CLK的高电平幅值进行拉高，拉高后的幅值可以由高电平参考电压VGH来决定。电平转换模块Level Shifter还可以用于接收低电平参考电压VGL，低电平参考电压VGL可以用于确定扫描脉冲信号CLK的低电平的幅值。选通调制模块100的输出引脚用于输出调节参考电压，电平转换模块Level Shifter的第一电平参考输入引脚用于接收调节参考电压。
本公开实施例提供的显示驱动电路，利用选通控制模块100调节高电平参考电压VGH，可以得到多个调节参考电压，每个调节参考电压用于控制一个扫描脉冲信号的高电平的幅值，可以实现减少不同行显示像素210的充电率差异，从而改善显示画面的横纹不良。
示例性的，参考图5，显示驱动电路还可以包括输出放电模块XAO和逻辑模块Logic Block。输出放电模块XAO用于在显示面板整体处于关机状态时将所有扫描脉冲信号CLK拉至高电平参考电压VGH，可以对显示像素210中的像素电容进行放电操作。逻辑模块Logic Block可以用于进行设定关机状态的扫描脉冲信号拉高操作，通常电平转换模块Level Shifter可以电连接于(即，设置在)逻辑模块Logic Block与输出放电模块XAO之间。调节高电平的幅值后的扫描脉冲信号可以从输出放电模块XAO输出，得到扫描驱动信号，分别表示为CLK1Out～CLKN Out，以及得到帧起始驱动信号STV Out。
在一些实施方式中，选通调制模块100可以用于调节对扫描驱动信号驱动显示像素的扫描通路的分压，以调节扫描通路对应的扫描脉冲信号CLK的第一电平(即，高电平)的幅值。也即是，可以在扫描通路中接入分压，例如接入电阻实现分压，也可以接入其他器件实现分压，本公开实施例不作具体限定。
其中，接入分压可以改变扫描通路对应的扫描脉冲信号CLK的高电平的幅值，进而改变施加在扫描通路中薄膜晶体管栅极上的电压，同时也改变了流经薄膜晶体管栅极的电流，即扫描通路的电流，通过对接入分压的调节可以削弱或者消除等效阻抗带来的充电率差异。由于工艺差异导致扫描通路的等效阻抗差异，进而导致扫描通路的电流差异，通过调节接入分压可以调节扫描通路的电流，进而减小不同行的显示像素210之间的薄膜晶体管栅极开启时间的差异， 减少不同行的显示像素210之间的充电率差异，可以改善显示画面横纹的问题。
在一些实施方式中，电平转换模块Level Shifter可以包括扫描脉冲输出引脚，扫描脉冲输出引脚可以与选通调制模块100的输入引脚电连接。进而，选通调制模块100可以接入扫描通路中，能够用于调节扫描通路的分压。
具体的，示例性的，图6为本公开实施例提供的又一种显示驱动电路的示意性结构框图。如图6所示，输出放电模块XAO可以电连接于(即，设置于)电平转换模块Level Shifter与选通调制模块100之间。在一些实施方式中，还可以是选通调制模块100设置于电平转换模块Level Shifter与输出放电模块XAO之间。
如图6所示，从输出放电模块XAO输出的N个扫描脉冲信号经过选通调制模块100的N路分压，可以得到N个高电平的幅值调节后的扫描驱动信号，分别表示为CLK1Out～CLKN Out。
本公开实施例提供的显示驱动电路，通过选通调制模块100调节扫描通路的分压，以调节扫描通路对应的扫描脉冲信号CLK的高电平的幅值。接入分压的调节可以改变扫描通路对应的扫描驱动信号的高电平的幅值，进而改变施加在扫描通路中薄膜晶体管栅极上的电压，同时也改变了流经薄膜晶体管栅极的电流，即扫描通路的电流，通过对接入分压的调节可以削弱或者和消除等效阻抗带来的充电率差异，可以改善显示画面横纹的问题。
在一些实施方式中，选通调制模块100可以包括调节单元，调节单元可以用于调节扫描脉冲信号CLK的第一电平(即，高电平)的幅值，且调节单元与扫描脉冲信号可以一一对应。
示例性的，图7为本公开实施例提供的一种选通调制模块示意性结构框图。如图7所示，选通调制模块100包括N(为大于1的整数)个调节单元，分别为第一调节单元110、第二调节单元120、第三调节单元130…第N调节单元1N0，高电平参考电压VGH经过选通调制模块100的各个调节单元调节后得到调节参考电压VGHO1～VGHON。调节参考电压VGHO1～VGHON可以用于调节扫描脉冲信号CLK1～CLKN的高电平幅值。
图5和图6中对应N个扫描脉冲信号CLK，电平转换模块Level Shifter内设置有N个调节单元，通过×N进行表示。
示例性的，图8为本公开实施例提供的另一种选通调制模块的示意性结构框图。对应选通调制模块100对扫描通路的分压的调节，参考图8，可以使得 扫描脉冲信号CLK1经过第一调节单元110得到CLK1Out，…，扫描脉冲信号CLKN经过第N调节单元1N0得到CLKN Out。
在一些实施方式中，调节单元可以包括至少一个开关。开关可以用于接收调制控制信号，并基于调制控制信号开启或关闭，开关的开启可以导通调节单元的通路，以开启调节功能，开关的关闭可以断开调节单元的通路，以关闭调节功能。
在一些实施方式中，调节单元可以包括多个并联的开关，任意并联的两个开关之间可以包括(即，设置有)至少一个固定电阻和/或可调电阻。固定电阻和可调电阻可以起到分压以及调节电流的作用。
示例性的，图9为本公开实施例提供的一种调节单元的示意性结构图。如图9所示，每个调节单元包括n个开关和n个电阻，电阻可以是固定电阻，还可以是可调电阻。电阻分别表示为R0～Rn，n是大于1的任意自然数。n个开关可以接收n个调制控制信号，分别表示为D0～Dn，每个调节单元对应一组调制控制信号，每组调制控制信号包括D0～Dn，n个开关可以实现调节单元的多个调节挡位，增加调节单元的调节能力范围。每个调节单元对应输出一个调节参考电压VGHOQ，1≤Q≤N。调制控制信号可以采用二进制的形式表示，例如，“1”可以代表开关的开启调制控制信号，“0”可以代表开关的关闭调制控制信号。则每个调节单元对应的调制控制信号包括一组二进制数字组成的编码。
示例性的，表1为一种二进制调制控制信号的示意。
表1
示例性的，图10为本公开实施例提供的一种显示驱动电路的信号时序示意图。如图10所示，VGHO1、VGHO2、VGHO3…VGHON之间的数值不完全相同，则对应控制CLK1、CLK2、CLK3…CLKN之间的高电平幅值也不完全相同。如此，可以调节扫描通路的电流，进而实现减小不同行的显示像素210之间的薄膜晶体管栅极开启时间的差异，能够减少不同行的显示像素210之间的充电率差异，可以改善显示画面横纹的问题。
在一些实施方式中，调节单元可以包括多个并联的开关，每个开关所在通 路上均可以串联有固定电阻和/或可调电阻。开关与电阻串联，串联的开关和电阻可以形成一个调节挡位，可以用于调节接入扫描通路的分压。
示例性的，图11为本公开实施例提供的另一种调节单元的示意性结构图。如图11所示，每个调节单元包括n个开关和n个电阻，电阻可以是固定电阻，还可以是可调电阻。电阻分别表示为R0～Rn，n是大于1的任意自然数。电阻和开关串联，串联后的电阻和开关与其他串联的电阻和开关再并联，可以形成n个调节挡位。n个开关可以接收n个调制控制信号，分别表示为D0～Dn，每个调节单元对应一组调制控制信号，每组调制控制信号包括D0～Dn，n个开关可以实现调节单元的多个调节挡位，增加调节单元的调节能力范围。每个调节单元可以对应输出一个扫描脉冲信号CLKQ Out，1≤Q≤N。
示例性的，表2为另一种二进制调制控制信号的示意。
表2
在一些实施方式中，显示驱动电路还可以包括：调制控制模块，调制控制模块可以用于向选通调制模块100提供调制控制信号，调制控制信号可以用于控制选通调制模块100调节扫描脉冲信号的第一电平(即，高电平)的幅值。
可选的，调制控制信号可以通过编程的方式将程序烧录在调制控制模块内，在显示驱动的过程中根据显示控制指令发送至选通调制模块100。
示例性的，现有的高电平参考电压为37V，在本公开实施例提供的显示驱动电路中，可以设置高电平参考电压为40V，通过接入选通调制模块100，基于调制控制信号，控制调节单元内的开关的开启，增加接入扫描回路的电阻，起到分压作用，来实现调低扫描脉冲信号的高电平幅值的作用，根据具体需要控制对应数量和对应位置的开关的开启。还可以基于调制控制信号，控制调节单元内的开关的开启，增加接入高电平参考电压调节回路的电阻，起到分压作用，来实现调低高电平参考电压的作用，进而控制调低扫描脉冲信号的高电平的幅值，根据具体需要控制对应数量和对应位置的开关的开启。可以通过预先拉高高电平参考信号，在根据具体情况调低高电平参考信号的数值，或者直接调低扫描脉冲信号的高电平的幅值，来实现扫描脉冲信号的高电平幅值的可调 性，从而调节扫描通路的电流，进而实现减小不同行的显示像素之间的薄膜晶体管栅极导通性能的差异，能够减少不同行的显示像素之间的充电率差异，可以改善显示画面横纹的问题。
在一些实施方式中，开关可以包括至少一个晶体管(如，上述实施例记载的薄膜晶体管)。在半导体集成电路中，例如驱动芯片中可以采用薄膜晶体管作为开关器件，工艺成熟且稳定。当然，在一些其他实施方式中，开关也可以采用其他形式的开关器件，本公开实施例中不作具体限定。
本公开实施例的第二方面，提供一种显示驱动方法，应用于如第一方面记载的显示驱动电路，图12为本公开实施例提供的一种显示驱动方法的示意性流程图。如图12所示，该显示驱动方法包括：
S301：接收显示控制指令。
其中，显示控制指令可以是由控制主板发出的，也可以是由其他控制芯片发出的，本公开实施例不作具体限定。
S302：基于显示控制指令，驱动显示面板的显示像素显示画面。
其中，在基于显示控制指令，驱动显示面板的显示像素显示画面的过程中，通过选通调制模块调节接收到的扫描脉冲信号的第一电平和第二电平中第一电平的幅值，以减小不同的扫描通路之间的电流差异。
并且，扫描通路为扫描驱动信号驱动显示像素的通路；第一电平相对于第二电平为高电平。
针对现有显示驱动电路中的脉冲信号CLK的高电平幅值是固定不可调的，例如，CLK1～CLK6的高电平幅值均不可调，则在工艺波动导致显示像素的扫描通路的等效阻抗存在差异的情况下，显示像素对应的薄膜晶体管的栅极电压不同，最终导致像素电极的充电率差异，造成显示画面横纹不良。本公开实施例提供的显示驱动电路，设置有选通调制模块100，选通调制模块100可以调节扫描脉冲信号CLK的高电平的幅值，在工艺波动导致显示像素的扫描通路的等效阻抗存在差异的情况下，通过调节扫描脉冲信号CLK的高电平幅值，来调节显示像素的薄膜晶体管的栅极电压，保证薄膜晶体管的栅极在需要的时间段内持续开启，以保证像素电极的充电时间不受等效阻抗差异的影响，能够减小不同行的显示像素之间的充电率差异，可以改善显示画面的横纹不良。具体的可以理解为，通过调节扫描脉冲信号CLK的高电平幅值，来根据等效状差异，保证不同行的显示像素对应的薄膜晶体管的栅极累积电荷量较为平均，以保证不 同行的薄膜晶体管的开启时间较为平均，则能够减少不同行的像素电极的充电时间的差异，保证不同行的像素电极的充电率较为均衡，不会产生由于不同行的像素电极的充电率差异造成的横纹不良。
本公开实施例提供的显示驱动方法，通过选通调制模块100调节接收到的扫描脉冲信号CLK的高电平的幅值，在工艺波动导致显示像素的扫描通路的等效阻抗存在差异的情况下，通过调节扫描脉冲信号CLK的高电平幅值，来调节显示像素的薄膜晶体管的栅极电压，保证薄膜晶体管的栅极在需要的时间段内持续开启，以保证像素电极的充电时间不受等效阻抗差异的影响，能够减小不同行的显示像素之间的充电率差异，可以改善显示画面的横纹不良。
在一些实施方式中，显示控制指令包括调制控制信号，相应的，在上述步骤S301之前，显示驱动方法还可以包括：
首先，采集扫描通路的电流，得到初始扫描电流。
可选的，可以利用测试治具或者电信号采集装置测试扫描脉冲信号对应的各个扫描通路的电流，得到对应的初始扫描电流。
其次，根据不同的扫描通路之间的初始扫描电流的差异，确定需要补偿电流的扫描通路以及对应的补偿电流数值。
需要说明的是，补偿电流数值可以是正数，也可以是负数，主要根据不同扫描通路之间的初始扫描电流的差异确定。
最后，根据需要补偿电流的扫描通路以及对应的补偿电流数值，生成调制控制信号。
可选的，调制控制信号包括需要补偿电流的扫描通路的地址和对应的补偿电流数值。
需要说明的是，采集初始扫描电流以及生成调制控制信号的控制程序可以在显示装置启动阶段执行，也可以是每次或者间隔设定周期的执行改程序，执行次数可以根据显示装置的运行运算能力设置。即采集初始扫描电流以及生成调制控制信号的控制程序可以在用户使用显示装置的过程中运行。
在一些实施方式中，采集初始扫描电流以及生成调制控制信号的过程只在显示装置或显示面板出厂前的调试阶段进行，将调试完成的调制控制信号烧录在调制控制模块内，以供用户在使用显示装置的过程中进行扫描脉冲信号的调节。
在上述实施例基础上，上述步骤S302，可以包括：
在基于显示控制指令，驱动显示面板的显示像素显示画面的过程中，基于调制控制信号调节接收到的扫描脉冲信号的第一电平(即，高电平)的幅值。
选通调制模块接收到调制控制信号后，可以基于调制控制信号对扫描脉冲信号的高电平的幅值进行调节，通过扫描脉冲信号的高电平的电压补偿可以实现对具有电流差异的扫描通路进行补偿，扫描脉冲信号的高电平幅值可以是降低的，也可以是提高的，主要根据补偿电流值确定。
本公开实施例提供的显示驱动方法，针对现有显示驱动电路中的脉冲信号CLK的高电平幅值是固定不可调的，本公开实施例预先采集初始扫描电流，根据不同的扫描通路之间的初始扫描电流的差异，确定需要补偿电流的扫描通路以及对应的补偿电流数值，根据需要补偿电流的扫描通路以及对应的补偿电流数值，生成调制控制信号，选通调制模块100基于调制控制信号调节扫描脉冲信号CLK的高电平的幅值。在工艺波动导致显示像素的扫描通路的等效阻抗存在差异的情况下，通过测试扫描通路的初始扫描电流的差异，能够反映不同扫描通路的等效阻抗之间的差异，可以根据初始扫描电流的差异，确定扫描脉冲信号CLK的高电平幅值的调节幅度，调节扫描脉冲信号CLK的高电平的幅值，能够减小不同行的显示像素之间的充电率差异，可以改善显示画面的横纹不良。
在一些实施方式中，通过选通调制模块调节接收到的扫描脉冲信号的第一电平和第二电平中第一电平的幅值，可以包括：
调节第一电平(即，高电平)参考电压，以输出调节参考电压。
基于调节参考电压，调节扫描脉冲信号的高电平的幅值。选通调制模块100对于扫描脉冲信号CLK的高电平的幅值的调节，可以通过调节高电平参考电压来实现。选通调制模块100对高电平参考电压进行调节，得到调节参考电压，调节参考电压可以控制对应的扫描脉冲信号的高电平的幅值。具体的，调节参考电压可以与扫描脉冲信号一一对应。通常，现有的显示驱动电路只设置有一个高电平参考电压信号线，本公开实施例提供的显示驱动电路，通过选通调制模块100的调节，可以得到多个调节参考电压，每个调节参考电压用于控制一个扫描脉冲信号的高电平的幅值，可以实现减少不同行显示像素的充电率差异，从而改善显示画面的横纹不良。
在一些实施方式中，通过选通调制模块调节接收到的扫描脉冲信号的第一电平和第二电平中第一电平的幅值，包括：
调节对扫描通路的分压，以调节扫描通路对应的扫描脉冲信号的第一电平 (即，高电平)的幅值。
可选的，如上述实施例记载，可以在扫描通路中接入分压，例如接入电阻实现分压，也可以接入其他器件实现分压，本公开实施例不作具体限定。接入分压可以改变扫描通路对应的扫描驱动信号的高电平的幅值，进而改变施加在扫描通路中薄膜晶体管栅极上的电压，同时也改变了流经薄膜晶体管栅极的电流，即扫描通路的电流，通过对接入分压的调节可以削弱或者和消除等效阻抗带来的充电率差异。具体的，由于工艺差异导致扫描通路的等效阻抗差异，进而导致扫描通路的电流差异，通过调节接入分压可以调节扫描通路的电流，进而实现减小不同行的显示像素之间的薄膜晶体管栅极开启时间的差异，能够减少不同行的显示像素之间的充电率差异，可以改善显示画面横纹的问题。
本公开实施例的第三方面，提供一种显示驱动控制器，图13为本公开实施例提供的一种显示驱动控制器的示意性结构框图。如图13所示，显示驱动控制器包括：
存储器401，存储器401中存储有计算机程序；
处理器402，处理器402用于执行计算机程序时实现如第二方面记载的显示驱动方法。
需要说明的是，显示驱动控制器可以设置在显示装置的控制主板上，显示驱动控制器可以是以芯片的形式设置在显示装置中，本公开实施例均不作具体限定。
本公开实施例的第四方面，提供一种显示装置，图14为本公开实施例提供的一种显示装置的示意性结构框图。如图14所示，显示装置包括：如第一方面记载的显示驱动电路501，和/或，如第三方面记载的显示驱动控制器502。显示驱动电路501可以是显示装置内的驱动芯片，显示驱动控制器502可以设置在显示装置的控制主板上。
示例性的，本公开实施例提供的显示装置包括显示驱动电路501和显示驱动控制器502，显示驱动控制器502可以控制显示驱动电路501的运行。
在一些实施方式中，显示装置还可以包括：
显示面板，显示面板可以具有显示区和非显示区。
位于显示面板的显示区的显示像素，即上述实施例记载的显示像素可以设置于显示面板的显示区。
控制电路板，控制电路板可以与显示面板电连接。
可选的，显示面板可以是液晶显示面板、有机发光显示面板或LED显示面板，本公开实施例均不作具体限定。控制电路板可以理解为显示装置的控制主板，显示装置包括的显示驱动电路可以绑定于显示面板的非显示区。
示例性的，显示驱动电路501可以以驱动芯片的形式绑定在显示面板的非显示区，则显示面板可以是柔性显示面板，可以将绑定有显示驱动电路501的非显示区弯折至显示面板的背面，以缩小显示装置的边框。在一些实施方式中，显示装置包括的显示驱动电路501还可以设置于控制电路板上，可以根据具体的显示装置的空间进行合理设计。
需要说明的是，本公开实施例提供的显示装置可以是智能手机、笔记本电脑、平板电脑、电视或其他显示器等，本公开实施例均不作具体限定。
需要说明的是，在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详细描述的部分，可以参见其它实施例的相关描述。
本领域内的技术人员应明白，本公开的实施例可提供为方法、系统、或计算机程序产品。因此，本公开可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本公开可采用在一个或多个其中包含有计算机可读程序代码的计算机可读存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本公开是参照根据本公开实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式计算机或者其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个 流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
本公开实施例还提供了一种计算机程序产品，该计算机程序产品包括计算机软件指令，当计算机软件指令在处理设备上运行时，使得处理设备执行显示驱动方法的流程。
计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行计算机程序指令时，全部或部分地产生按照本公开实施例的流程或功能。计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一计算机可读存储介质传输，例如，计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(digital subscriber line，DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。计算机可读存储介质可以是计算机能够存储的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘(solid state disk，SSD))等。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本公开所提供的几个实施例中，应该理解到，所揭露的设备，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本公开各个实施例中的各功能单元可以集成在一个处理单元中， 也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本公开的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本公开各个实施例方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上，以上实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的精神和范围。
尽管已描述了本说明书的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本说明书范围的所有变更和修改。
显然，本领域的技术人员可以对本说明书进行各种改动和变型而不脱离本说明书的精神和范围。这样，倘若本说明书的这些修改和变型属于本说明书权利要求及其等同技术的范围之内，则本说明书也意图包含这些改动和变型在内。

Claims (20)

  1. 一种显示驱动电路，所述显示驱动电路包括：
    选通调制模块，所述选通调制模块与显示面板中的显示像素电连接，并用于接收扫描脉冲信号，且用于调节所述扫描脉冲信号的第一电平和第二电平中第一电平的幅值，所述第一电平相对于所述第二电平为高电平；
    其中，所述扫描脉冲信号用于驱动显示面板的显示像素显示画面。
  2. 根据权利要求1所述的显示驱动电路，其中，所述选通调制模块还用于接收第一电平参考电压，并用于调节第一电平参考电压，以输出调节参考电压；
    其中，所述调节参考电压用于调节所述扫描脉冲信号的第一电平的幅值。
  3. 根据权利要求2所述的显示驱动电路，其中，所述调节参考电压与所述扫描脉冲信号一一对应。
  4. 根据权利要求1所述的显示驱动电路，其中，所述选通调制模块用于调节对所述扫描驱动信号驱动所述显示像素的扫描通路的分压，以调节所述扫描通路对应的所述扫描脉冲信号的第一电平的幅值。
  5. 根据权利要求1-4中任一项所述的显示驱动电路，其中，所述选通调制模块包括：调节单元，所述调节单元用于调节所述扫描脉冲信号的第一电平的幅值，且所述调节单元与所述扫描脉冲信号一一对应。
  6. 根据权利要求5所述的显示驱动电路，其中，所述调节单元包括：至少一个开关。
  7. 根据权利要求6所述的显示驱动电路，其中，所述调节单元包括：多个并联的所述开关；任意并联的两个所述开关之间包括：至少一个固定电阻和/或可调电阻。
  8. 根据权利要求6所述的显示驱动电路，其中，所述调节单元包括：多个 并联的所述开关，每个所述开关所在通路上均串联有固定电阻和/或可调电阻。
  9. 根据权利要求6所述的显示驱动电路，其中，所述开关包括：至少一个晶体管。
  10. 根据权利要求2所述的显示驱动电路，其中，所述显示驱动电路还包括：电平转换模块；
    所述电平转换模块包括第一电平参考输入引脚，所述第一电平参考输入引脚与所述选通调制模块的输出引脚电连接。
  11. 根据权利要求4所述的显示驱动电路，其中，所述显示驱动电路还包括：电平转换模块；
    所述电平转换模块包括扫描脉冲输出引脚，所述扫描脉冲输出引脚与所述选通调制模块的输入引脚电连接。
  12. 根据权利要求10或11所述的显示驱动电路，其中，所述显示驱动电路还包括：输出放电模块；
    所述输出放电模块电连接于所述电平转换模块与所述选通调制模块之间；或，所述选通调制模块电连接于所述电平转换模块与所述输出放电模块之间。
  13. 根据权利要求1-12中任一项所述的显示驱动电路，其中，所述显示驱动电路还包括：调制控制模块；
    所述调制控制模块用于向所述选通调制模块提供调制控制信号，所述调制控制信号用于控制所述选通调制模块调节所述扫描脉冲信号的第一电平的幅值。
  14. 一种显示驱动方法，应用于如权利要求1-13中任一项所述的显示驱动电路，所述显示驱动方法包括：
    接收显示控制指令；
    基于所述显示控制指令，驱动显示面板的显示像素显示画面；
    其中，在基于所述显示控制指令，驱动显示面板的显示像素显示画面的过 程中，通过选通调制模块调节接收到的扫描脉冲信号的第一电平和第二电平中第一电平的幅值，以减小不同的扫描通路之间的电流差异；
    并且，所述扫描通路为所述扫描驱动信号驱动所述显示像素的通路；所述第一电平相对于所述第二电平为高电平。
  15. 根据权利要求14所述的显示驱动方法，其中，所述显示控制指令包括：调制控制信号；在所述接收显示控制指令之前，所述显示驱动方法还包括：
    采集所述扫描通路的电流，得到初始扫描电流；
    根据不同的所述扫描通路之间的所述初始扫描电流的差异，确定需要补偿电流的所述扫描通路以及对应的补偿电流数值；
    根据需要补偿电流的所述扫描通路以及对应的补偿电流数值，生成调制控制信号；
    所述在基于所述显示控制指令，驱动显示面板的显示像素显示画面的过程中，通过选通调制模块调节接收到的扫描脉冲信号的第一电平和第二电平中第一电平的幅值，包括：
    在基于所述显示控制指令，驱动显示面板的所述显示像素显示画面的过程中，基于所述调制控制信号调节接收到的所述扫描脉冲信号的第一电平的幅值。
  16. 根据权利要求14所述的显示驱动方法，其中，所述通过选通调制模块调节接收到的扫描脉冲信号的第一电平和第二电平中第一电平的幅值，包括：
    调节第一电平参考电压，以输出调节参考电压；
    基于所述调节参考电压，调节所述扫描脉冲信号的第一电平的幅值。
  17. 根据权利要求14所述的显示驱动方法，其中，所述通过选通调制模块调节接收到的扫描脉冲信号的第一电平和第二电平中第一电平的幅值，包括：
    调节对所述扫描通路的分压，以调节所述扫描通路对应的所述扫描脉冲信号的第一电平的幅值。
  18. 一种显示驱动控制器，所述显示驱动控制器包括：
    存储器，所述存储器中存储有计算机程序；
    处理器，所述处理器用于执行所述计算机程序时实现如权利要求14-17 中任一项所述的显示驱动方法。
  19. 一种显示装置，所述显示装置包括：
    如权利要求1-13中任一项所述的显示驱动电路，和/或，如权利要求18所述的显示驱动控制器。
  20. 根据权利要求19所述的显示装置，其中，所述显示装置还包括：
    显示面板，具有显示区和非显示区；
    位于所述显示面板的显示区的显示像素；
    控制电路板，所述控制电路板与所述显示面板电连接；
    其中，所述显示装置包括的显示驱动电路绑定于所述显示面板的非显示区；或，所述显示装置包括的显示驱动电路设置于所述控制电路板上。
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