WO2023226708A1 - 像素驱动电路及其驱动方法、阵列基板及显示装置 - Google Patents

像素驱动电路及其驱动方法、阵列基板及显示装置 Download PDF

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Publication number
WO2023226708A1
WO2023226708A1 PCT/CN2023/092110 CN2023092110W WO2023226708A1 WO 2023226708 A1 WO2023226708 A1 WO 2023226708A1 CN 2023092110 W CN2023092110 W CN 2023092110W WO 2023226708 A1 WO2023226708 A1 WO 2023226708A1
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Prior art keywords
signal
circuit
sub
terminal
level
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PCT/CN2023/092110
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English (en)
French (fr)
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WO2023226708A9 (zh
Inventor
汪锐
胡明
邱海军
陈军涛
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京东方科技集团股份有限公司
重庆京东方显示技术有限公司
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Publication of WO2023226708A1 publication Critical patent/WO2023226708A1/zh
Publication of WO2023226708A9 publication Critical patent/WO2023226708A9/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel driving circuit and a driving method thereof, an array substrate and a display device.
  • OLED Organic Light Emitting Diode
  • the OLED display device may include multiple sub-pixels, and each sub-pixel includes a pixel driving circuit and a light-emitting device arranged in one-to-one correspondence.
  • the pixel drive circuit can drive the corresponding light-emitting device to emit light under the control of the gate drive (Gate Driver On Array, GOA) drive signal of the array substrate.
  • GOA Gate Driver On Array
  • a pixel driving circuit including: a driving sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a data writing sub-circuit, a compensation sub-circuit and a first reset sub-circuit; wherein the driving sub-circuit
  • the circuit includes a control end, a first end and a second end; in an initialization stage in a display frame of the pixel driving circuit, the voltage difference between the control end of the driving subcircuit and the first end of the driving subcircuit is fixed; first The light-emitting control sub-circuit is coupled to the first voltage terminal and the first terminal of the driving sub-circuit, and is configured to drive the light-emitting element to emit light in response to a signal from the first light-emitting signal control terminal; the second light-emitting control sub-circuit is coupled to the driving sub-circuit.
  • the second end of the circuit and the first electrode of the light-emitting element are configured to drive the light-emitting element to emit light in response to a signal from the second light-emitting signal control end; the data writing sub-circuit is coupled to the data signal end and the first electrode of the driving sub-circuit.
  • the compensation sub-circuit is coupled to the second terminal of the driving sub-circuit and the control of the driving sub-circuit terminal, and is configured to perform threshold compensation on the driver sub-circuit in response to a signal from the compensation signal control terminal;
  • the first reset sub-circuit is coupled between the second voltage terminal and the control terminal of the driver sub-circuit, and is configured to respond to The signal at the first reset signal control end is used to write the signal at the second voltage end into the control end of the drive sub-circuit to reset the control end of the drive sub-circuit; the pulse width of the signal at the first reset signal control end is adjustable.
  • the first terminal of the first reset sub-circuit is coupled to the control terminal of the driving sub-circuit through the compensation sub-circuit, and the second terminal of the first reset sub-circuit is coupled to the second voltage terminal.
  • the pixel driving circuit further includes a third lighting control sub-circuit, the third lighting control sub-circuit is coupled to the second end of the driving sub-circuit and the first end of the first reset sub-circuit; the third lighting control sub-circuit The circuit is configured to synchronously initialize the control end of the driving sub-circuit and the first end of the driving sub-circuit in the initialization stage in response to the signal from the third light-emitting signal control end, and drive the light-emitting element to emit light in the light-emitting stage.
  • the first terminal of the first reset sub-circuit is coupled to the control terminal of the driving sub-circuit, and the second terminal of the first reset sub-circuit is coupled to the second voltage terminal.
  • the pixel driving circuit further includes a second reset sub-circuit, the second reset sub-circuit is coupled to the third voltage terminal and the second terminal of the driving sub-circuit; the second reset sub-circuit is configured to respond to the first The signal at the second reset signal control terminal writes the signal at the third voltage terminal into the second terminal of the driver sub-circuit to reset the second terminal of the driver sub-circuit.
  • the first lighting signal control terminal and the second lighting signal control terminal are connected to different signal lines, and the first lighting control sub-circuit is further configured to write the signal of the first voltage terminal into the driving sub-circuit during the initialization phase. First end.
  • the first light-emitting signal control terminal and the second light-emitting signal control terminal are connected to the same signal line
  • the pixel driving circuit further includes a third reset sub-circuit, the third reset sub-circuit is coupled to the fourth voltage terminal and the driving The first end of the sub-circuit, and is configured to respond to the signal of the second signal control end, write the signal of the fourth voltage end into the first end of the driving sub-circuit, and reset the first end of the driving sub-circuit; the fourth voltage The signal voltage at the first voltage terminal is higher than the signal voltage at the first voltage terminal.
  • a pixel driving circuit including: a driving sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a data writing sub-circuit, a compensation sub-circuit and a first reset sub-circuit; wherein, the driving sub-circuit The sub-circuit includes a control terminal, a first terminal and a second terminal; the first lighting control sub-circuit is coupled to the first voltage terminal and the first terminal of the driving sub-circuit, and is configured to respond to the signal of the first lighting signal control terminal, Driving the light-emitting element to emit light; the second light-emitting control subcircuit is coupled to the second terminal of the driving sub-circuit and the first electrode of the light-emitting element, and is configured to drive the light-emitting element to emit light in response to a signal from the second light-emitting signal control terminal; data writing The input subcircuit is coupled to the data signal terminal and the first terminal of the driver sub
  • the above-mentioned pixel driving circuit further includes a fourth reset sub-circuit, the fourth reset sub-circuit is coupled to the fifth voltage terminal and the first electrode of the light-emitting element, and is configured to respond to a signal from the third signal control terminal. , writing the signal at the fifth voltage terminal into the first electrode of the light-emitting element, and resetting the first electrode of the light-emitting element.
  • the above-mentioned pixel driving circuit further includes a storage subcircuit.
  • the storage subcircuit is coupled to the control terminal and the first voltage terminal of the driving subcircuit and is configured to store the compensation signal obtained based on the data signal.
  • an array substrate including: the pixel driving circuit as in any one of the above embodiments, wherein the pixel driving circuit includes a data writing subcircuit and a first reset subcircuit, and the data writing subcircuit includes a third Four transistors, the first reset sub-circuit includes a sixth transistor.
  • the array substrate includes: a substrate, a first active layer and a first gate layer; wherein the first active layer provided on one side of the substrate includes a fourth active layer of the fourth transistor, a third layer of the sixth transistor.
  • the first gate layer provided on the side of the first active layer away from the substrate includes a first gate signal line and a second gate signal line.
  • the orthographic projection of the first gate signal line on the substrate overlaps with the orthographic projection of the fourth active layer, and the orthographic projection of the second gate signal line on the substrate overlaps with the orthographic projection of the sixth active layer, where, Relative to the electrical signal transmitted by the first gate signal line, the pulse width of the electrical signal transmitted by the second gate signal line is adjustable.
  • the first gate signal line is insulated from the second gate signal line.
  • the pixel driving circuit further includes a driving subcircuit, a first lighting control subcircuit, a second lighting control subcircuit, and a third reset subcircuit
  • the driving subcircuit includes a first transistor
  • the first lighting control subcircuit includes The second transistor
  • the second lighting control sub-circuit includes a third transistor
  • the third reset sub-circuit includes a tenth transistor
  • the first active layer also includes a first active layer of the first transistor, a second active layer of the second transistor, a third active layer of the third transistor, and a tenth active layer of the tenth transistor. , the first active layer, the second active layer and the tenth active layer are all connected to the first connection point.
  • the first gate layer also includes a third gate signal line, an orthographic projection of the third gate signal line on the substrate, an orthographic projection of the third active layer on the substrate, and an orthographic projection of the second active layer on the substrate.
  • the orthographic projections on have overlap.
  • the fourth gate signal line, the orthographic projection of the fourth gate signal line on the substrate overlaps with the orthographic projection of the tenth active layer on the substrate.
  • the array substrate further includes a third gate layer, the third gate layer is disposed on a side of the first gate layer away from the substrate, the third gate layer further includes a third initialization signal line, and the third initialization signal line is The signal line is electrically connected to the active layer of the tenth transistor.
  • the array substrate further includes a second gate layer, the second gate layer is disposed between the first gate layer and the third gate layer, and the second gate layer further includes a first initialization signal line, The first initialization signal line is electrically connected to the sixth active layer.
  • the same layer patterns of every two adjacent pixel driving circuits are substantially mirror symmetrical.
  • the pixel driving circuit further includes a storage sub-circuit, and the second gate layer includes a second plate of the capacitance of the storage sub-circuit, wherein the two mirror-symmetric second plates are connected.
  • the pixel driving circuit includes a fourth reset sub-circuit
  • the first active layer further includes an active layer of a seventh transistor of the fourth reset sub-circuit.
  • the array substrate also includes a first source and drain metal layer.
  • the first source and drain metal layer is disposed on a side of the third gate layer away from the substrate.
  • the first source and drain metal layer includes a second initialization signal line, and an adjacent second initialization signal line. The signal lines are electrically connected, and the second initialization signal line is electrically connected to the active layer of the seventh transistor.
  • the first connection point is provided on the first source-drain metal layer.
  • the first source-drain metal layer also includes a fourth connection trace. One end of the fourth connection trace is via a hole to the first active layer and connected to the first source-drain metal layer.
  • the tenth active layer is electrically connected, the other end of the fourth connection line is electrically connected to the first connection point, and the first connection point passes through a hole to the first active layer and is connected to the second active layer and the first active layer.
  • Source layer electrical connections One end of the fourth connection trace is via a hole to the first active layer and connected to the first source-drain metal layer.
  • the tenth active layer is electrically connected
  • the other end of the fourth connection line is electrically connected to the first connection point
  • the first connection point passes through a hole to the first active layer and is connected to the second active layer and the first active layer.
  • Source layer electrical connections.
  • the first source-drain metal layer also includes a fifth connection wire.
  • One end of the fifth connection wire is through a hole to the third gate layer and is electrically connected to the third initialization signal line.
  • the fifth connection wire The other end of the first active layer is electrically connected to the tenth active layer through a hole.
  • the first source-drain metal layer also includes a sixth connection trace. Both ends of the sixth connection trace are via holes to the second gate layer and are electrically connected to the first initialization signal line.
  • the sixth connection trace is electrically connected to the first initialization signal line.
  • the middle part of the line is through-hole to the first active layer and is electrically connected to the first active layer.
  • the array substrate further includes a second source-drain metal layer, the second source-drain metal layer is disposed on a side of the first source-drain metal layer away from the substrate, and the second source-drain metal layer includes a first voltage signal line.
  • the first source-drain metal layer also includes third connection traces.
  • the third connection traces are mirror-symmetrical in pairs.
  • the first voltage signal line is through-hole to the first source-drain metal layer and the two third connection traces are mirror-symmetrical. one of the electrical connections.
  • the two mirror-symmetrical third connection lines are routed through the holes to the second gate layer and are electrically connected to the second plate corresponding to the same pixel driving circuit.
  • a display device including: the display panel according to any of the above embodiments.
  • a method for driving a pixel driving circuit which is used to drive the pixel driving circuit as in any of the above embodiments, wherein the working process of the pixel driving circuit in a display frame includes an initialization phase and a data writing phase.
  • the driving method includes: in the initialization stage, controlling the level of the signal at the first reset signal control terminal to the first level, controlling the level of the signal at the compensation signal control terminal to the second level, controlling the first signal control
  • the level of the signal at the terminal is the second level; the pulse width of the signal at the first reset signal control terminal is adjustable; during the data writing phase, the level of the signal at the first reset signal control terminal is controlled to be the second level, and the compensation signal is controlled
  • the level of the signal at the control end is the second level, and the level of the signal at the control end of the control terminal is the first level; during the lighting phase, the level of the signal at the control end of the control compensation signal is the first level, and the level of the signal at the control end is the first level.
  • the level of the signal at the reset signal control terminal is the second level, and the level of the signal controlling the first signal control terminal is the second level.
  • the driving method of the above-mentioned pixel driving circuit further includes: in the initialization stage, controlling the level of the signal at the first light-emitting signal control terminal to be a first level, and controlling the level of the signal at the second light-emitting signal control terminal to be a third level. Two levels; in the initialization stage, the level of the signal controlling the first light-emitting signal control terminal is the first level, and the level of the signal controlling the second light-emitting signal control terminal is the second level; in the light-emitting stage, the first light-emitting signal is controlled The level of the signal at the signal control terminal is the first level, and the level of the signal controlling the second light-emitting signal control terminal is the first level.
  • the above-mentioned pixel driving circuit further includes a third reset sub-circuit, the third reset sub-circuit is coupled to the fourth voltage terminal and the first terminal of the driving sub-circuit, and the control terminal of the third reset sub-circuit is configured In order to receive the signal from the second signal control terminal; the signal voltage of the fourth voltage terminal is higher than the signal voltage of the first voltage terminal; the above method also includes: in the initialization stage, controlling the voltage of the signals of the first luminous signal control terminal and the second luminous signal control terminal.
  • the signal controlling the second signal control terminal is the first level; in the data writing stage, the level of the signal controlling the first light-emitting signal control terminal and the second light-emitting signal control terminal is the second level, Control the signal at the second signal control terminal to the second level; when sending In the light stage, the level of the signal controlling the first light-emitting signal control terminal and the second light-emitting signal control terminal is the first level, and the signal controlling the second signal control terminal is the second level.
  • the first terminal of the above-mentioned first reset sub-circuit is coupled to the control terminal of the driving sub-circuit through the compensation sub-circuit, and the second terminal of the first reset sub-circuit is coupled to the second voltage terminal;
  • the pixel driving circuit It also includes a third lighting control sub-circuit, the third lighting control sub-circuit is coupled to the second end of the driving sub-circuit and the first end of the first reset sub-circuit, the third lighting control sub-circuit control end is configured to receive the third The signal of the light-emitting signal control terminal;
  • the above method also includes: in the initialization stage, controlling the level of the signal of the third light-emitting signal control terminal to be the second level; in the data writing stage, controlling the level of the signal of the third light-emitting signal control terminal to be The first level or the second level; in the light-emitting stage, the level of the signal controlling the third light-emitting signal control terminal is the first level.
  • the first end of the first reset sub-circuit is coupled to the control end of the driving sub-circuit, and the second end of the first reset sub-circuit is coupled to the second voltage end;
  • the pixel driving circuit further includes a second Reset sub-circuit, the second reset sub-circuit is coupled to the third voltage terminal and the second terminal of the driving sub-circuit, the control terminal of the second reset sub-circuit is configured to receive the signal of the second reset signal control terminal;
  • the above method also includes: In the initialization phase, the level of the signal controlling the second reset signal control terminal is the first level; in the data writing phase, the level of the signal controlling the second reset signal control terminal is the second level; in the light-emitting phase, the level of the signal controlling the second reset signal control terminal is the second level.
  • the level of the signal at the second reset signal control terminal is the second level.
  • Figure 1 is a structural diagram of a pixel driving circuit in the related art
  • Figure 2 is a signal timing diagram of a pixel driving circuit in the related art
  • Figure 3 is one of the structural diagrams of a display panel according to some embodiments.
  • Figure 4 is a block diagram of a pixel driving circuit according to some embodiments.
  • Figure 5 is a block diagram of another pixel driving circuit according to some embodiments.
  • Figure 6 is a circuit diagram of a pixel driving circuit according to some embodiments.
  • Figure 7 is a signal timing diagram of a pixel driving circuit according to some embodiments.
  • Figure 8 is a circuit diagram of another pixel driving circuit according to some embodiments.
  • Figure 9 is a signal timing diagram of another pixel driving circuit according to some embodiments.
  • Figure 10 is a circuit diagram of yet another pixel driving circuit according to some embodiments.
  • Figure 11 is a signal timing diagram of yet another pixel driving circuit according to some embodiments.
  • Figure 12 is a circuit diagram of yet another pixel driving circuit according to some embodiments.
  • Figure 13 is a circuit diagram of yet another pixel driving circuit according to some embodiments.
  • Figure 14A is a signal timing diagram of yet another pixel driving circuit according to some embodiments.
  • Figure 14B is a signal timing diagram of yet another pixel driving circuit according to some embodiments.
  • Figure 15 is a circuit diagram of yet another pixel driving circuit according to some embodiments.
  • Figure 16 is a signal timing diagram of yet another pixel driving circuit according to some embodiments.
  • Figure 17 is a circuit diagram of yet another pixel driving circuit according to some embodiments.
  • Figure 18 is a circuit diagram of yet another pixel driving circuit according to some embodiments.
  • Figure 19 is a circuit diagram of yet another pixel driving circuit according to some embodiments.
  • Figure 20 is a signal timing diagram of yet another pixel driving circuit according to some embodiments.
  • Figure 21 is a cross-sectional view of an array substrate according to some embodiments.
  • Figure 22 is a structural diagram of a first active layer according to some embodiments.
  • Figure 23 is a structural diagram of a first gate layer according to some embodiments.
  • Figure 24 is a structural diagram of a first gate layer and a first gate layer according to some embodiments.
  • Figure 25 is a structural diagram of a second gate layer according to some embodiments.
  • Figure 26 is a structural diagram of a second active layer according to some embodiments.
  • Figure 27 is a structural diagram of a third gate layer according to some embodiments.
  • Figure 28 is a structural diagram of a first source and drain metal layer according to some embodiments.
  • Figure 29 is a structural diagram of a second source and drain metal layer according to some embodiments.
  • Figure 30 is a structural diagram of some layers of an array substrate according to some embodiments.
  • Figure 31 is a structural diagram of an array substrate according to some embodiments.
  • Figure 32 is a structural diagram of another first active layer according to some embodiments.
  • Figure 33 is a structural diagram of another first active layer and a first source-drain metal layer according to some embodiments.
  • Figure 34 is a structural diagram of another first gate layer according to some embodiments.
  • Figure 35 is a structural diagram of another first active layer and a first gate layer according to some embodiments.
  • Figure 36 is a structural diagram of another second gate layer according to some embodiments.
  • Figure 37 is a structural diagram of another third gate layer according to some embodiments.
  • Figure 38 is a structural diagram of another first source and drain metal layer according to some embodiments.
  • Figure 39 is a structural diagram of another array substrate according to some embodiments.
  • Figure 40 is a flow chart of a driving method of a pixel driving circuit according to some embodiments.
  • FIG. 41 is a flowchart of another driving method of a pixel driving circuit according to some embodiments.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and includes the following combinations of A, B and C: A only, B only, C only, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “in response to” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrase “if it is determined" or “if [stated condition or event] is detected” is optionally interpreted to mean “when it is determined" or “in response to the determination" or “on detection of [stated condition or event]” or “in response to detection of [stated condition or event]”.
  • parallel includes absolutely parallel and approximately parallel, and the acceptable deviation range of approximately parallel may be, for example, a deviation within 5°;
  • perpendicular includes absolutely vertical and approximately vertical, and the acceptable deviation range of approximately vertical may also be, for example, Deviation within 5°.
  • equal includes absolute equality and approximate equality, wherein the difference between the two that may be equal within the acceptable deviation range of approximately equal is less than or equal to 5% of either one, for example.
  • the transistors used in the circuits provided by the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • thin film transistors are used as examples for description.
  • FIG. 1 is a circuit diagram of a pixel driving circuit in a related art. As shown in Figure 1, the pixel driving circuit includes 7 transistors and 1 capacitor. The 7 transistors are transistors T1 to T7 respectively, and the 1 capacitor is capacitor Cst.
  • the working process of a pixel driving circuit in a display frame may include: an initialization phase t1, a data writing phase t2, and a lighting phase t3.
  • the working process of the pixel driving circuit shown in Figure 1 will be introduced below with reference to Figure 2.
  • the gate drive signals Gate[n-1] of the transistors T6 and T7 are low level
  • the gate drive signals Gate_N[n] of the transistor T5 are high level
  • the gates of the transistors T2 and T3 The drive signal EM[n] is at a high level
  • the gate drive signal Gate[n] of the transistor T4 is at a high level.
  • the gate that is, the first node N1, so that the voltage of the gate of the transistor T1 is vinit1, thereby realizing the gate initialization of the transistor T1.
  • the voltage vinit2 output by the voltage terminal Vinit2 can be provided to the first electrode of the light-emitting element through the turned-on transistor T7 to reset the first electrode of the light-emitting element.
  • the gate drive signals Gate[n-1] of the transistors T6 and T7 are high level
  • the gate drive signals Gate_N[n] of the transistor T5 are high level
  • the gate drive signals Gate_N[n] of the transistor T5 are high level.
  • the gate drive signal EM[n] is high level
  • the gate drive signal Gate[n] of the transistor T4 is low level.
  • the gate drive signals Gate[n-1] of the transistors T6 and T7 are high level, the gate drive signals Gate_N[n] of the transistor T5 are low level, and the gates of the transistors T2 and T3
  • the drive signal EM[n] is low level, and the gate drive signal Gate[n] of the transistor T4 is high level.
  • the transistors T1 to T3 are turned on, and the transistors T4 to T7 are turned off, so that the voltage vdd output by the voltage terminal VDD can be provided to the first electrode of the light-emitting element through the transistors T1 to T3 to achieve driving.
  • the light-emitting element emits light.
  • the gate drive signal of transistor T4 is Gate[n]
  • the gate drive signal of transistor T6 is Gate[n-1]
  • the gate drive signal Gate[n-1] of T6 is the gate of transistor T4.
  • some embodiments of the present disclosure provide a pixel driving circuit and a display device
  • the pixel driving circuit can ensure that the voltage difference between the control end of the driving subcircuit and the first end of the driving subcircuit is fixed, that is, it can ensure that the voltage difference between the gate and the source of the driving transistor is fixed. , so the first transistor has a fixed VGS bias signal (on-bias) during the initialization phase. Since the fixed voltage difference on the first transistor is an actively generated bias voltage, compared with the passively generated bias voltage on the first transistor in the solution shown in FIG. 1 , the afterimage problem caused by the hysteresis effect of the first transistor can be improved.
  • the time of the initialization phase can be Independent control to achieve time balance between initialization and data writing phases and achieve good lighting effects.
  • the display device 30 can be a tablet computer, a display, a mobile phone, a billboard, a digital photo frame or a personal digital assistant (Personal Digital Assistant, PDA) or any other device with A device that displays functionality.
  • PDA Personal Digital Assistant
  • the display device 30 may be an organic light-emitting diode (Organic Light-Emitting Diode, OLED) display device, quantum dot electroluminescent diode (Quantum Dot Light Emitting Diodes, QLED) display device or active matrix organic light emitting diode (Active-Matrix Organic Light Emitting Diode, AMOLED) display device.
  • OLED Organic Light-Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes
  • AMOLED active matrix organic light emitting diode
  • the embodiment of the present application does not place any special restrictions on the specific type of the display device 30 .
  • the following embodiments take an OLED display device as an example for detailed description.
  • the display device 30 includes a display area A, and a peripheral area B provided on at least one side of the display area A.
  • the display area A is an area where an image is displayed, and the display area A is configured to provide sub-pixels P.
  • the peripheral area B is an area where no image is displayed, and the peripheral area B is configured to provide a display driving circuit, for example, a gate driving circuit and a source driving circuit.
  • the plurality of sub-pixels P are arranged in multiple rows and multiple columns. Each row includes a plurality of sub-pixels P arranged along the first direction X, and each column includes a plurality of sub-pixels P arranged along the second direction Y. Each row of sub-pixels P may include multiple sub-pixels P, and each column of sub-pixels P may include multiple sub-pixels P.
  • first direction X and the second direction Y cross each other.
  • the angle between the first direction X and the second direction Y can be selected and set according to actual needs.
  • the angle between the first direction X and the second direction Y may be 85°, 89°, 90°, etc.
  • the above-mentioned display device 30 may further include a plurality of gate lines GL and a plurality of data lines DL located in the display area A.
  • the plurality of gate lines GL extend along the first direction X
  • the plurality of data lines DL extend along the second direction Y.
  • the sub-pixels P arranged in a row along the first direction may be coupled to the same gate line GL, and the sub-pixels P in the same column may be coupled to the same data line DL.
  • Each sub-pixel P may include a pixel driving circuit 31 and a light-emitting element coupled to the pixel driving circuit 31 .
  • one gate line GL can be coupled to multiple pixel driving circuits 31 in the same row of sub-pixels P
  • one data line DL can be coupled to multiple pixel driving circuits 31 in the same column of sub-pixels P.
  • each sub-pixel P its pixel driving circuit 31 can receive the GOA driving signal (for example, the signal of the first luminescence signal control terminal, the signal of the second luminescence signal control terminal, the signal of the third luminescence signal control terminal, the signal of the first luminescence signal control terminal) through the gate line GL.
  • the GOA driving signal for example, the signal of the first luminescence signal control terminal, the signal of the second luminescence signal control terminal, the signal of the third luminescence signal control terminal, the signal of the first luminescence signal control terminal
  • the voltage signal at the data voltage terminal enables the pixel driving circuit 31 to drive the corresponding light-emitting element to emit light according to the voltage signal at the data voltage terminal under the control of the GOA driving signal.
  • the pixel driving circuit 31 includes: a driving sub-circuit 311, a first light-emitting control sub-circuit 312, a second light-emitting control sub-circuit 313, a data write input sub-circuit 314, compensation sub-circuit 315, and first reset sub-circuit 316.
  • the pixel driving circuit 31 is configured to generate a driving current to control the light emitting element to emit light.
  • the driving subcircuit 311 includes a control terminal, a first terminal and a second terminal.
  • the driving sub-circuit 311 is used to provide driving light emitting The driving current for the component to emit light. Wherein, during the initialization phase t1 in a display frame of the pixel driving circuit 31, the voltage difference between the control terminal of the driving sub-circuit 311 and the first terminal of the driving sub-circuit is fixed.
  • the first light-emitting control sub-circuit 312 is coupled to the first voltage terminal VDD and the first terminal of the driving sub-circuit 311, and is configured to drive the light-emitting element to emit light in response to a signal from the first light-emitting signal control terminal EM1.
  • the second light-emitting control sub-circuit 313 is coupled to the second terminal of the driving sub-circuit 311 and the first electrode of the light-emitting element, and is configured to drive the light-emitting element to emit light in response to a signal from the second light-emitting signal control terminal EM2.
  • the data writing sub-circuit 314 is coupled to the data signal terminal Vdata and the first terminal of the driving sub-circuit 311, and is configured to write the signal of the data signal terminal Vdata in response to the signal Gate[n] of the first signal control terminal S1. into the first terminal of the driver sub-circuit 311.
  • the compensation sub-circuit 315 is coupled to the second terminal of the driving sub-circuit 311 and the control terminal of the driving sub-circuit 311, and is configured to perform threshold compensation on the driving sub-circuit 311 in response to the signal of the compensation signal control terminal G1.
  • the first reset sub-circuit 316 is coupled between the second voltage terminal Vinit1 and the control terminal of the driving sub-circuit 311, and is configured to write the signal of the second voltage terminal Vinit1 in response to the signal of the first reset signal control terminal R1. Enter the control terminal of the driving sub-circuit 311 to reset the control terminal of the driving sub-circuit 311.
  • the first reset sub-circuit 316 can be coupled between the second voltage terminal Vinit1 and the control terminal of the driving sub-circuit 311 through two circuit structures. These two circuit structures are introduced below.
  • the first circuit structure as shown in Figure 4, the first end of the first reset sub-circuit 316 is coupled to the control end of the driving sub-circuit 311 through the compensation sub-circuit 315, and the second end of the first reset sub-circuit 316 is coupled to to the second voltage terminal Vinit1.
  • the second circuit structure is as shown in Figure 5.
  • the first terminal of the first reset sub-circuit 316 is coupled to the control terminal of the driving sub-circuit 311, and the second terminal of the first reset sub-circuit 316 is coupled to the second voltage terminal. Vinit1.
  • the first light-emitting signal control terminal EM1 and the second light-emitting signal control terminal EM2 may be connected to the same GOA driving signal line, or may be connected to different GOA driving signal lines.
  • the first light-emitting control sub-circuit 312 is configured to change the first voltage terminal VDD during the initialization phase t1.
  • the signal vdd is written into the first end of the driving sub-circuit 311, and drives the light-emitting element to emit light in the light-emitting stage t3.
  • the first light-emitting signal control terminal EM1 and the second light-emitting signal control terminal EM2 are connected to different GOA driving signal lines, and the first light-emitting signal control terminal EM2
  • the signal at the terminal EM1 is EM1[n]
  • the signal at the second light-emitting signal control terminal EM2 is EM2[n].
  • the signal vdd of the first voltage terminal VDD is written into the first terminal of the driving sub-circuit 311 during the initialization phase t1, thereby ensuring that the first terminal of the driving sub-circuit 311 is a fixed voltage.
  • the voltage at the first terminal of the driving subcircuit 311 is vdd, and the control terminal voltage and the second terminal voltage of the driving subcircuit 311 are close to the voltage vinit1, therefore during the initialization phase t1, the gate source of the driving subcircuit 311
  • the voltage VGS is vinit1-vdd, so the driving sub-circuit 311 is in the fixed bias on-bias state, and then enters the data writing stage t2, It can ensure that the brightness of this frame is not affected by the status of the previous frame and improve the short-term afterimage problem.
  • the pixel driving circuit 31 further includes a third reset sub-circuit 321, and the third reset sub-circuit 321 is coupled to the GOA driving signal line. Connected to the fourth voltage terminal Vinit3 and the first terminal of the driving sub-circuit 311.
  • the third reset sub-circuit 321 is configured to write the signal vinit3 of the fourth voltage terminal Vinit3 into the first terminal of the driving sub-circuit 311 in response to the signal of the second signal control terminal S2 during the initialization phase t1, to the driving sub-circuit 311. The first end is reset.
  • the first light-emitting signal control terminal EM1 and the second light-emitting signal control terminal EM2 are connected to the same GOA driving signal line, and the signal of the first light-emitting signal control terminal EM1 is EM[n], the signal of the second light-emitting signal control terminal EM2 is also EM[n].
  • the signal vinit3 of the fourth voltage terminal Vinit3 is written into the first terminal of the driving sub-circuit 311 during the initialization phase t1, thereby ensuring that the first terminal of the driving sub-circuit 311 is a fixed voltage.
  • the voltage at the first terminal of the driver sub-circuit 311 is vinit3, and the control terminal voltage and the second terminal voltage of the driver sub-circuit 311 are close to the voltage vinit1, therefore during the initialization stage, the gate-source voltage of the driver sub-circuit 311 VGS is vinit1-vinit3, so the driving subcircuit 311 is in the fixed bias on-bias state, and then enters the data writing stage t2, which can ensure that the brightness of this frame is not affected by the state of the previous frame and improve the short-term afterimage problem. .
  • the pixel driving circuit 31 may further include a storage sub-circuit 317 coupled to the control terminal of the driving sub-circuit 311 and the first voltage terminal VDD, and is configured to store the compensation signal obtained based on the data signal vdata.
  • the pixel driving circuit 31 may further include a fourth reset sub-circuit 318 coupled to the fifth voltage terminal Vinit4 and the first electrode of the light-emitting element. , and is configured to write the signal vinit4 of the fifth voltage terminal Vinit4 into the first electrode of the light-emitting element in response to the signal of the third signal control terminal S3, and reset the first electrode of the light-emitting element.
  • the initialization phase t1 can be implemented by using the pixel driving circuit 31 with a variety of different circuit structures to ensure that the voltage difference between the control end of the driving sub-circuit 311 and the first end of the driving sub-circuit is fixed.
  • the driving sub-circuit 311 in the pixel driving circuit 31 includes a first transistor T1.
  • the gate of the first transistor T1 is the control terminal of the driving sub-circuit.
  • the first pole of the first transistor T1 is the third terminal of the driving sub-circuit 311.
  • One end, the second pole of the first transistor T1 drives the second end of the sub-circuit 311 .
  • the gate of the first transistor T1 is coupled to the first node N1, the source of the first transistor T1 is coupled to the second node N2, and the drain of the first transistor T1 is coupled to the third node N3.
  • the first transistor T1 may be a driving thin film transistor (DTFT).
  • DTFT driving thin film transistor
  • the first transistor T1 may be a driving thin film transistor (DTFT) capable of providing a driving light-emitting element.
  • the device emits light by driving current to any type of transistor.
  • the first lighting control sub-circuit 312 includes a second transistor T2 , a first pole of the second transistor T2 is coupled to the first voltage terminal VDD, and a second pole of the second transistor T2 is coupled to the first voltage terminal VDD.
  • the gate electrode of the second transistor T2 is coupled to the first light-emitting signal control terminal EM1.
  • the second transistor T2 may be turned on or off in response to the signal EM1[n] of the first light emitting signal control terminal EM1.
  • the initialization phase t1 when the second transistor T2 is turned on, the connection between the first voltage terminal VDD and the first electrode of the first transistor T1 is turned on, and the signal vdd of the first voltage terminal VDD can be written to the third
  • the voltage of the first pole of a transistor T1, that is, the second node N2, is vdd.
  • the second light emitting control sub-circuit 313 includes a third transistor T3.
  • the first electrode of the third transistor T3 is coupled to the second electrode of the first transistor T1.
  • the third transistor T3 The second electrode of the third transistor T3 is coupled to the first electrode of the light-emitting element, and the gate electrode of the third transistor T3 is coupled to the second light-emitting signal control terminal EM2.
  • the gate drive signal of the second transistor T2 in the first light emission control sub-circuit 312 is EM1[n]
  • the gate of the third transistor T3 in the second light emission control sub-circuit 313 is EM1[n].
  • the driving signal is EM2[n]. That is, the gate drive signal of the second transistor T2 in the first light emission control sub-circuit 312 is different from the gate drive signal of the third transistor T3 in the second light emission control sub-circuit 313 .
  • the second transistor T2 in the first light emitting control sub-circuit 312 is turned on, so that the signal vdd of the first voltage terminal VDD can be written into the first pole of the first transistor T1, thereby ensuring that the first transistor The first pole of T1 is at a fixed voltage.
  • the first electrode voltage of the first transistor T1 is vdd, and the gate voltage and the second electrode voltage of the first transistor T1 are close to the voltage vinit1, therefore during the initialization stage t1, the gate-source voltage of the first transistor T1 VGS is vinit1-vdd, so the first transistor T1 is in the fixed bias on-bias state, and then enters the data writing stage t2, which can ensure that the brightness of this frame is not affected by the state of the previous frame and improve the short-term afterimage problem. .
  • the data writing sub-circuit 314 includes a fourth transistor T4 , a first pole of the fourth transistor T4 is coupled to the data signal terminal Vdata, and a second pole of the fourth transistor T4 is coupled to the data signal terminal Vdata. to the first terminal of the first transistor T1 and the second terminal of the second transistor T2, and the gate of the fourth transistor T4 is coupled to the first signal control terminal S1.
  • the compensation subcircuit 315 includes a fifth transistor T5 , a first pole of the fifth transistor T5 is coupled to the gate of the first transistor T1 , and a second pole of the fifth transistor T5 is coupled to the gate of the first transistor T1 . Connected to the second electrode of the first transistor T1, the gate of the fifth transistor T5 is coupled to the compensation signal control terminal G1.
  • the first reset sub-circuit 316 includes a sixth transistor T6 , the first electrode of the sixth transistor T6 is coupled to the second electrode of the fifth transistor T5 , and the first electrode of the sixth transistor T6 is coupled to the second electrode of the fifth transistor T5 .
  • the diode is coupled to the second voltage terminal Vinit1, and the gate of the sixth transistor T6 is coupled to the first reset signal control terminal R1.
  • the memory sub-circuit 317 includes a capacitor Cst, one end of the capacitor Cst is coupled to the first voltage terminal VDD, and the other end of the capacitor Cst is coupled to the gate of the first transistor T1.
  • the capacitor Cst is configured to store the compensation signal obtained based on the data signal vdata.
  • the fourth reset sub-circuit 318 includes a seventh transistor T7 , a first pole of the seventh transistor T7 is coupled to the fifth voltage terminal Vinit4 , and a second pole of the seventh transistor T7 is coupled to the fifth voltage terminal Vinit4 .
  • the gate of the seventh transistor T7 is coupled to the third signal control terminal S3.
  • the seventh transistor T7 is turned on, the signal vinit4 of the fifth voltage terminal Vinit4 can be written into the first electrode of the light-emitting element to reset the first electrode of the light-emitting element.
  • the first electrode of the transistor in the embodiment of the present disclosure may be one of the source electrode and the drain electrode, and the second electrode of the transistor may be the other one of the source electrode and the drain electrode. Since the source and drain of the transistor may be symmetrical in structure, the source and drain of the transistor may be structurally indistinguishable. That is to say, the first electrode and the third electrode of the transistor in the embodiment of the present disclosure
  • the two poles can be structurally indistinguishable.
  • the transistor is a P-type transistor
  • the first pole of the transistor is the source
  • the second pole is the drain
  • the first pole of the transistor is the drain
  • the second pole is the source. This disclosure is not limited to whether the first to tenth transistors T1 to T10 are N-type or P-type.
  • a driving cycle of the pixel driving circuit 31 in the embodiment of the present disclosure includes three stages: an initialization stage t1, a data writing stage t2, and a light-emitting stage t3.
  • an initialization stage t1 a data writing stage t2
  • a light-emitting stage t3 a driving cycle of the pixel driving circuit 31 in the embodiment of the present disclosure.
  • the level of the signal EM1[n] of the first light-emitting signal control terminal EM1 is the first level (for example, low level), and then the second transistor T2 is turned on.
  • the level of the signal EM2[n] of the second light emitting signal control terminal EM2 is the second level (for example, high level), then the third transistor T3 is turned off.
  • the sixth transistor T6 is turned on.
  • the fourth transistor T4 is turned off.
  • the level of the signal Gate_N[n] at the compensation signal control terminal G1 is the second level, that is, the fifth transistor T5 is turned on.
  • the level of the signal Gate[n-1] at the third signal control terminal S3 is the first level, that is, the seventh transistor T7 is turned on.
  • the signal vdd of the first voltage terminal VDD can be written into the first pole of the first transistor T1 through the second transistor T2, that is, the voltage value of the second node N2 is vdd.
  • the signal vinit1 at the second voltage terminal Vinit1 is written into the gate of the first transistor T1 through the sixth transistor T6 and the fifth transistor T5. That is, the voltage value of the first node N1 is vinit1.
  • the source and gate of the first transistor T1 A fixed voltage difference vinit1-vdd is generated between the poles, so the first transistor T1 is in the fixed biased on-bias state, and then enters the data writing stage t2 to ensure that the brightness of this frame is not affected by the state of the previous frame. impact and improve short-term afterimage problems.
  • the voltage vinit4 output by the fifth voltage terminal Vinit4 can be provided to the first electrode of the light-emitting element through the turned-on transistor T7 to reset the first electrode of the light-emitting element.
  • the level of the signal EM1[n] of the first light-emitting signal control terminal EM1 is the second level, and the second transistor T2 is turned off.
  • the level of the signal EM2[n] of the second light-emitting signal control terminal EM2 is the second level, then the Three transistors T3 are turned off.
  • the sixth transistor T6 is turned off.
  • the level of the signal Gate[n] at the first signal control terminal S1 is the first level, and the level of the signal vdata at the data signal terminal Vdata is the second level, so the fourth transistor T4 is turned on.
  • the level of the signal Gate_N[n] at the compensation signal control terminal G1 is the second level, that is, the fifth transistor T5 is turned on.
  • the level of the signal Gate[n-1] at the third signal control terminal S3 is the second level, that is, the seventh transistor T7 is turned off.
  • the voltage vdata at the data signal terminal Vdata can be written into the first pole of the first transistor T1 through the fourth transistor T4.
  • the conduction of the fifth transistor T5 allows the first transistor T1 to form a diode connection, so that the first electrode voltage vdata of the first transistor T1 charges the gate of the first transistor T1 until the gate voltage of the first transistor T1 is vdata.
  • the voltage vdata+Vth of the gate of the first transistor T1 is stored by the capacitor Cst.
  • the level of the signal EM1[n] of the first light-emitting signal control terminal EM1 is the first level, and the second transistor T2 is turned on. If the level of the signal EM2[n] at the second light-emitting signal control terminal EM2 is the first level, the third transistor T3 is turned on. When the level of the signal Reset[n] at the first reset signal control terminal R1 is the second level, the sixth transistor T6 is turned off. The level of the signal Gate[n] at the first signal control terminal S1 is the second level, and the fourth transistor T4 is turned off.
  • the level of the signal Gate_N[n] at the compensation signal control terminal G1 is the first level, that is, the fifth transistor T5 is turned off.
  • the level of the signal Gate[n-1] at the third signal control terminal S3 is the second level, that is, the seventh transistor T7 is turned off.
  • the first transistor T1, the second transistor T2 and the third transistor T3 are turned on, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off, so that the first transistor T1, the second transistor T2 and the third transistor T3 are turned on.
  • the voltage vdd output by the voltage terminal VDD can be provided to the first electrode of the light-emitting element through the second transistor T2, the first transistor T1 and the third transistor T3 to drive the light-emitting element to emit light.
  • the voltage of the first electrode of the first transistor T1 is vdata.
  • the voltage of the gate of the first transistor T1 is vdata+Vth, which can make the first transistor T1 saturated. state.
  • K is related to the process and design related structural constants. Therefore, the driving current generated by the first transistor T1 is not affected by the threshold voltage Vth of the first transistor T1 , so the problem of brightness unevenness (mura) in the display panel caused by uneven Vth can be improved.
  • the sixth transistor T6 in the pixel driving circuit 31 shown in FIG. 6 may also be N-type.
  • the sixth transistor T6 is an N-type transistor, what is different from the signal timing diagram shown in Figure 7 is that in the initialization stage t1, the level of the signal Reset[n] of the first reset signal control terminal R1 is high level, The sixth transistor T6 is turned on. In the data writing phase t2 and the light emitting phase t3, the level of the signal Reset[n] of the first reset signal control terminal R1 is low level, and the sixth transistor T6 is turned off.
  • the gate driving signal of the sixth transistor T6 in the pixel driving circuit 31 shown in FIG. 6 is Reset[n]
  • the gate driving signal of the fourth transistor T4 is Gate[n]
  • the pulse width of the sixth transistor T6 can be modulated, so the initialization phase
  • the time can be controlled independently, so that the time balance between the initialization and data writing stages can be achieved to achieve a good lighting effect.
  • the third transistor T3 and the fourth transistor T4 are turned off, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned on. Since the voltage vdd of the first voltage terminal VDD can be written to the second node N2 through the second transistor T2, at this time, the first node N1, the second node N2 and the third node N3 are short-circuited, and the voltage division of the second transistor T2 makes The voltage value of the N2 node is slightly lower than vdd, and the voltage of the nodes N1 and N3 will be slightly higher than vinit1, so a little power consumption will be generated, but this does not affect the fixed voltage generated between the gate and source of the first transistor T1 Poor, it will not affect the on-bias bias effect.
  • some embodiments of the present disclosure also provide a pixel driving circuit 31 shown in FIG. 8 .
  • the pixel driving circuit 31 may also include a third lighting control sub-circuit 319 .
  • the third lighting control sub-circuit 319 is coupled to the second terminal of the driving sub-circuit 311 and A first terminal of the first reset sub-circuit 316 .
  • the third lighting control sub-circuit 319 is configured to, in response to the signal EM3[n] of the third lighting signal control terminal EM3, connect the control terminal of the driving sub-circuit 311 and the first terminal of the driving sub-circuit 311 during the initialization phase t1. Initialize synchronously, and drive the light-emitting element to emit light in the light-emitting phase t3.
  • the third lighting control sub-circuit 319 includes an eighth transistor T8 .
  • the first pole of the eighth transistor T8 is coupled to the second pole of the first transistor T1 .
  • the second pole of the eighth transistor T8 is coupled to The first electrode of the sixth transistor T6, the first electrode of the third transistor T3 and the second electrode of the fifth transistor T5.
  • the gate of the eighth transistor T8 is coupled to the third lighting signal control terminal EM3.
  • the working flow of the pixel driving circuit 31 shown in Fig. 8 in a display frame is similar to the working flow of the pixel driving circuit 31 shown in Fig. 6 in a display frame.
  • the following is a description of the pixel driving circuit shown in Fig. 8 in conjunction with Fig. 9 The difference between the working flow of the circuit 31 in a display frame and the working flow of the pixel driving circuit 31 in a display frame shown in FIG. 6 will be described.
  • the level of the signal EM3[n] of the third light emitting signal control terminal EM3 is the second level, and the eighth transistor T8 is turned off. Therefore, during the initialization phase t1, the first node N1 and the second node N2 can be initialized synchronously, thereby ensuring that the gate and source of the first transistor T1 generate a stable voltage difference, achieving a better on-bias bias effect, thereby Better improve the afterimage problem.
  • the level of the signal EM3[n] of the third light emitting signal control terminal EM3 can be the first level or the second level.
  • the eighth transistor T8 is turned on.
  • the eighth transistor T8 is turned off.
  • FIG. 9 illustrates an example by taking the level of the signal EM3[n] of the third light-emitting signal control terminal EM3 as the first level during the data writing stage t2.
  • the pixel driving circuit 31 shown in FIG. 8 adds an eighth transistor T8 based on the pixel driving circuit 31 shown in FIG. 6 . Therefore, except for the gate drive signal of the eighth transistor T8 (for example, the signal EM3[n] of the third light-emitting signal control terminal EM3), the control methods and working processes of the gate drive signals of other transistors at each stage are the same as those in FIG. The working flow of the pixel driving circuit 31 shown in Figure 6 is the same in one display frame.
  • Some embodiments of the present disclosure also provide a pixel driving circuit 31.
  • the pixel driving circuit 31 has a similar structure to the pixel driving circuit 31 shown in FIG. 6 .
  • the difference between the pixel driving circuit 31 shown in FIG. 10 and the pixel driving circuit 31 shown in FIG. 6 lies in the first reset.
  • Subcircuit 316 is connected differently.
  • the difference between the structure of the pixel driving circuit 31 shown in FIG. 10 and the structure of the pixel driving circuit 31 shown in FIG. 6 will be described.
  • the first reset sub-circuit 316 includes a sixth transistor T6 , a first electrode of the sixth transistor T6 is coupled to the gate of the first transistor T1 and the first electrode of the fifth transistor T5 . pole, the second pole of the sixth transistor T6 is coupled to the second voltage terminal Vinit1, and the gate of the sixth transistor T6 is coupled to the first reset signal control terminal R1.
  • the sixth transistor T6 may be turned on or off in response to the signal Reset[n] of the first reset signal control terminal R1.
  • the voltage vinit1 of the second voltage terminal Vinit1 cannot be written into the gate of the first transistor T1, and the gate of the first transistor T1 cannot be reset.
  • the sixth transistor T6 is turned on, the voltage vinit1 of the second voltage terminal Vinit1 can be written into the gate of the first transistor T1, and the gate of the first transistor T1 can be reset.
  • the level of the signal EM1[n] of the first light-emitting signal control terminal EM1 is low level, and the second transistor T2 is turned on.
  • the third transistor T3 is turned off.
  • the level of the signal Reset[n] at the first reset signal control terminal R1 is low level, and the sixth transistor T6 is turned on.
  • the level of the signal Gate[n] at the first signal control terminal S1 is high level, and the fourth transistor T4 is turned off.
  • the level of the signal Gate_N[n] at the compensation signal control terminal G1 is low level, that is, the fifth transistor T5 is turned off.
  • the level of the signal Gate[n-1] of the third signal control terminal S3 is low level, that is, the seventh transistor T7 is turned on.
  • the signal vdd of the first voltage terminal VDD can be written into the first pole of the first transistor T1 through the second transistor T2, that is, the voltage value of the second node N2 is vdd.
  • the signal vinit1 of the second voltage terminal Vinit1 is written into the gate of the first transistor T1 through the sixth transistor T6, that is, the voltage value of the first node N1 is vinit1.
  • a fixed voltage is generated between the source and the gate of the first transistor T1.
  • the voltage difference vinit1-vdd so the first transistor T1 is in the fixed bias on-bias state, and then enters the data writing stage, it can ensure that the brightness of this frame is not affected by the state of the previous frame.
  • the signal vinit4 of the fifth voltage terminal Vinit4 can be provided to the first electrode of the light-emitting element through the turned-on transistor T7 to reset the first electrode of the light-emitting element.
  • the level of the signal EM1[n] of the first light emitting signal control terminal EM is high level, and the second transistor T2 is turned off.
  • the third transistor T3 is turned off.
  • the level of the signal Reset[n] at the first reset signal control terminal R1 is high level, and the sixth transistor T6 is turned off.
  • the level of the signal Gate[n] at the first signal control terminal S1 is low level, and the fourth transistor T4 is turned on.
  • the level Gate_N[n] of the signal at the compensation signal control terminal G1 is high level, that is, the fifth transistor T5 is turned on.
  • the level of the signal Gate[n-1] of the third signal control terminal S3 is high level, that is, the seventh transistor T7 is turned off.
  • the voltage vdata at the data signal terminal Vdata can be written into the first pole of the first transistor T1 through the fourth transistor T4.
  • the conduction of the fifth transistor T5 allows the first transistor T1 to form a diode connection, so that the first electrode voltage vdata of the first transistor T1 charges the gate of the first transistor T1 until the gate voltage of the first transistor T1 is vdata.
  • the voltage vdata+Vth of the gate of the first transistor T1 is stored by the capacitor Cst.
  • the level of the signal EM1[n] of the first light-emitting signal control terminal EM1 is low level, and the second transistor T2 is turned on.
  • the level of the signal EM2[n] of the second light-emitting signal control terminal EM2 is low level, and the third transistor T3 is turned on.
  • the level of the signal Reset[n] at the first reset signal control terminal R1 is high level, and the sixth transistor T6 is turned off.
  • the level of the signal Gate[n] at the first signal control terminal S1 is high level, and the fourth transistor T4 is turned off.
  • the level of the signal Gate_N[n] at the compensation signal control terminal G1 is low level, that is, the fifth transistor T5 is turned off.
  • the level of the signal Gate[n-1] of the third signal control terminal S3 is high level, that is, the seventh transistor T7 is turned off.
  • the first transistor T1, the second transistor T2, and the third transistor T3 are turned on, and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off, so that the The voltage vdd output by a voltage terminal VDD can be provided to the first electrode of the light-emitting element through the first transistor T1 to the third transistor T3 to drive the light-emitting element to emit light.
  • the voltage of the first electrode of the first transistor T1 is vdata.
  • some embodiments of the present disclosure also provide a pixel driving circuit shown in Figure 12 31.
  • the pixel driving circuit 31 may also include a second reset sub-circuit 320 .
  • the second reset sub-circuit 320 is coupled to the second end and the third end of the driving sub-circuit 311 . Voltage terminal Vinit2. Should The second reset sub-circuit 320 is configured to reset the second terminal of the driving sub-circuit 311 in response to the signal Reset[n] of the second reset signal control terminal R2.
  • the second reset sub-circuit 320 includes a ninth transistor T9 , a first pole of the ninth transistor T9 is coupled to the third voltage terminal Vinit2 , and a second pole of the ninth transistor T9 is coupled to the first transistor T1
  • the second electrode of the ninth transistor T9 is coupled to the second reset signal control terminal R2.
  • the working flow of the pixel driving circuit 31 shown in Fig. 12 in a display frame is similar to the working flow of the pixel driving circuit 31 shown in Fig. 10 in a display frame.
  • the following is a description of the pixel driving circuit shown in Fig. 12 in conjunction with Fig. 11
  • the difference between the working flow of the circuit 31 in a display frame and the working flow of the pixel driving circuit 31 in a display frame shown in FIG. 10 will be described.
  • the level of the signal Reset[n] of the second reset signal control terminal R2 is low level, and the ninth transistor T9 is turned on.
  • the first node N1, the second node N2 and the third node N3 can be initialized synchronously, ensuring that the first transistor T1 generates a stable voltage difference, achieving better on-bias bias effect and better Improve the afterimage problem.
  • the pixel driving circuit 31 shown in FIG. 12 adds a ninth transistor T9 based on the pixel driving circuit 31 shown in FIG. 10 , the gate driving signal of the ninth transistor T9 is Reset[n]. Therefore, the working flow of the pixel driving circuit 31 shown in FIG. 12 is the same as the working flow of the pixel driving circuit 31 shown in FIG. 10 in one display frame, that is, the signal timing of the driving method of the pixel driving circuit 31 shown in FIG. 12 The diagram is shown in Figure 11.
  • the pixel driving circuit 31 may also include a third reset sub-circuit 321 .
  • the third reset sub-circuit 321 is coupled to the second terminal and the fourth voltage terminal of the first light emitting control sub-circuit 312 . Vinit3.
  • the third reset sub-circuit 321 is configured to write the signal vinit3 of the fourth voltage terminal Vinit3 into the driver in the initialization stage t1 in response to the signal Gate[n-1] or Reset[n] of the second signal control terminal S2.
  • the first terminal of the circuit 311 resets the first terminal of the driving sub-circuit 311.
  • the third reset sub-circuit 321 includes a tenth transistor T10 , and the first pole of the tenth transistor T10 is coupled to the fourth voltage terminal Vinit3 .
  • the second electrode of the tenth transistor T10 is coupled to the second electrode of the second transistor T2, the first electrode of the first transistor T1, and the second electrode of the fourth transistor T4.
  • the gate of the tenth transistor T10 is coupled to the second signal control terminal S2.
  • the first luminescence signal control terminal EM1 of the second transistor T2 and the second luminescence signal of the third transistor T3 in the pixel driving circuit shown in FIG. 13 The control terminal EM2 can be connected to the same signal line.
  • the signal of the first light-emitting signal control terminal EM1 of the second transistor T2 is EM[n]
  • the signal of the second light-emitting signal control terminal EM2 of the third transistor T3 is also EM[n].
  • the transistor T9 and the tenth transistor T10 are P-type
  • the fifth transistor T5 is an N-type
  • the gate driving signal of the tenth transistor T10 is Reset[n].
  • the pixel driving circuit 31 shown in FIG. 13 is described with reference to FIG. 14A. The working process is introduced.
  • the level of the signal EM[n] of the first light-emitting signal control terminal EM1 and the second light-emitting signal control terminal EM2 is high level, then the second transistor T2 and the third transistor T3 Deadline.
  • the fifth transistor T5 is turned on.
  • the level of the signal Reset[n] at the first reset control terminal R1 and the second signal control terminal S2 is low level, then the sixth transistor T6 and the tenth transistor T10 are turned on.
  • the level of the signal Gate[n-1] of the third signal control terminal S3 is low level, and the seventh transistor T7 is turned on.
  • the fourth transistor T4 is turned off.
  • the signal vinit3 of the fourth voltage terminal Vinit3 can be written into the first pole of the first transistor T1, that is, the voltage value of the second node N2 is vinit3.
  • the signal vinit1 at the second voltage terminal Vinit1 is written into the gate of the first transistor T1 through the sixth transistor T6 and the fifth transistor T5. That is, the voltage value of the first node N1 is vinit1.
  • the source and gate of the first transistor T1 A fixed voltage difference vinit1-vinit3 is generated between the poles, so the first transistor T1 is in the on-bias state with a fixed bias.
  • the voltage vinit4 output by the fifth voltage terminal Vinit4 can be provided to the first electrode of the light-emitting element through the turned-on transistor T7 to reset the first electrode of the light-emitting element.
  • the voltage vinit3 of the fourth voltage terminal Vinit3 is higher than the voltage vdd of the first voltage terminal VDD. Therefore, during the initialization phase t1, the voltage vinit3 of the fourth voltage terminal Vinit3 can be written into the first pole of the first transistor T1, and the first transistor T1 is in the on-bias state with a fixed bias, so that the brightness of this frame is not affected by the previous one. Effect of frame status.
  • the voltage vinit3 of the fourth voltage terminal Vinit3 may be 5V.
  • the level of the signal EM[n] of the first light-emitting signal control terminal EM1 and the second light-emitting signal control terminal EM2 is high level, then the second transistor T2 and the third Transistor T3 is turned off.
  • the level of the signal Gate_N[n] at the compensation signal control terminal G1 is high level, the fifth transistor T5 is turned on.
  • the level of the signal Reset[n] at the first reset control terminal R1 and the second signal control terminal S2 is high level
  • the sixth transistor T6 and the tenth transistor T10 are turned off.
  • the level of the signal Gate[n-1] of the third signal control terminal S3 is high level, and the seventh transistor T7 is turned off.
  • the level of the signal Gate[n] at the first signal control terminal S1 is low level, and the fourth transistor T4 is turned on. Therefore, in the data writing stage t2, the voltage vdata of the data signal terminal Vdata can be written into the first pole of the first transistor T1 through the fourth transistor T4.
  • the level of the signal EM[n] of the first light-emitting signal control terminal EM1 and the second light-emitting signal control terminal EM2 is low level, then the second transistor T2 and the third transistor T3 conduction.
  • the fifth transistor T5 is turned off.
  • the sixth transistor T6 and the tenth transistor T10 are turned off.
  • the level of the signal Gate[n-1] of the third signal control terminal S3 is high level, and the seventh transistor T7 is turned off.
  • the level of the signal Gate[n] at the first signal control terminal S1 is high level, and the fourth transistor T4 is turned off. Therefore, in the light-emitting phase t3, the first transistor T1, the second transistor T2 and the third transistor T3 are turned on, so that the voltage vdd output by the first voltage terminal VDD can be provided to the first electrode of the light-emitting element through the transistor T1 to transistor T3, Realize driving the light-emitting element to emit light.
  • the gate drive signal of the tenth transistor T10 may also be Gate[n-1].
  • the signal timing diagram of the pixel driving circuit 31 shown in FIG. 14B is compared with that of FIG. 14A. The difference in the signal timing diagram of the pixel driving circuit 31 will be described below.
  • the initialization phase t1 includes a first initialization phase t1_1 and a second initialization phase t1_2.
  • the level of the first reset control terminal R1 signal Reset[n] is low level, and the sixth transistor T6 is turned on.
  • the level of the signal Gate[n-1] of the second signal control terminal S2 is high level, and the tenth transistor T10 is turned off. Therefore, in the first initialization stage t1_1, the fifth transistor T5 and the sixth transistor T6 are turned on, and the voltage vinit1 of the second voltage terminal Vinit1 is written into the gate of the first transistor T1, that is, the gate of the first node N1 through the fifth transistor T5.
  • the voltage is vinit1, which initializes the gate of the first transistor T1.
  • the level of the signal Gate_N[n] of the compensation signal control terminal G1 is low level, and the fifth transistor T5 is turned off.
  • the level of the first reset control terminal R1 signal Reset[n] is high level, and the sixth transistor T6 is turned off.
  • the level of the signal Gate[n-1] at the second signal control terminal S2 is low level, then the tenth transistor T10 and the seventh transistor T7 are turned on. Therefore, in the second initialization stage t1_2, the voltage vinit3 of the fourth voltage terminal Vinit3 is written into the first pole of the first transistor T1, that is, the voltage of the second node N2 is vinit3, thereby realizing the initialization of the first pole of the first transistor T1. .
  • the voltage vinit4 at the fifth voltage terminal Vinit4 is written into the first pole of the light-emitting element through the seventh transistor T7 to initialize the first pole of the light-emitting element.
  • Some embodiments of the present disclosure also provide a pixel driving circuit 31 shown in FIG. 15 .
  • the gate driving signal of the tenth transistor of the pixel driving circuit 31 is Reset[n].
  • the pixel driving circuit 31 may also include a third lighting control sub-circuit 319 .
  • the third lighting control sub-circuit 319 shown in FIG. 15 is the same as the pixel shown in FIG. 8
  • the connection method and function of the third light emitting control sub-circuit 319 in the structure of the driving circuit 31 are the same and will not be described again here.
  • the signal timing diagram of the pixel driving circuit 31 shown in FIG. 15 is shown in FIG. 16
  • the signal timing diagram of the pixel driving circuit 31 shown in FIG. 8 is shown in FIG. 9 .
  • the difference between the signal timing diagram shown in Figure 16 and the signal timing diagram shown in Figure 9 is that in the signal timing diagram shown in Figure 16, the signals of the first lighting signal control terminal EM1 and the second lighting signal control terminal EM2 are the same. is EM[n].
  • the signal of the first light-emitting signal control terminal EM1 and the signal of the second light-emitting signal control terminal EM2 are different.
  • the signal of the first light-emitting signal control terminal EM1 is EM1[n]
  • the signal of the second light-emitting signal control terminal EM2 is EM1[n].
  • the signal of control terminal EM2 is EM2[n].
  • the signal of the first luminescence signal control terminal EM1 and the signal of the second luminescence signal control terminal EM2 of the pixel driving circuit 31 are both EM[n].
  • the level of the signal EM[n] of the first light-emitting control terminal EM1 and the second light-emitting signal control terminal EM2 is high level, then the second transistor T2 and the third transistor T3 are turned off.
  • the level of the signal EM[n] of the first light-emitting control terminal EM1 and the second light-emitting signal control terminal EM2 is low level, and the second transistor T2 and the third transistor T3 are turned on.
  • the working flow of the pixel driving circuit 31 shown in Fig. 15 in a display frame is similar to the working flow of the pixel driving circuit 31 shown in Fig. 13 in a display frame.
  • the following is a description of the pixel driving circuit shown in Fig. 15 in conjunction with Fig. 16
  • the difference between the working flow of the circuit 31 in a display frame and the working flow of the pixel driving circuit 31 in a display frame shown in FIG. 13 will be described.
  • the level of the signal EM3[n] of the third light emitting signal control terminal EM3 is high level, and the eighth transistor T8 is turned off. Therefore, during the initialization phase t1, the first node N1 and the second node N2 can be initialized synchronously, thereby ensuring that the gate and source of the first transistor T1 generate a stable voltage difference, achieving a better on-bias bias effect, thereby Better improve the afterimage problem.
  • the level of the signal EM3[n] of the third light emitting signal control terminal EM3 can be low level or high level.
  • the eighth transistor T8 is turned on.
  • the eighth transistor T8 is turned off.
  • FIG. 16 illustrates an example by taking the level of the signal EM3[n] of the third light-emitting signal control terminal EM3 as low level during the data writing stage t2.
  • the pixel driving circuit 31 shown in FIG. 15 is based on the pixel driving circuit 31 shown in FIG. 13 and adds an eighth transistor T8. Therefore, in addition to the gate drive signal of the eighth transistor T8 (such as the signal EM3[n] of the third light-emitting signal control terminal EM3), the gate drive signals of other transistors are controlled in various stages and The working flow is the same as the working flow of the pixel driving circuit 31 shown in FIG. 13 in one display frame.
  • the gate drive signal of the eighth transistor T8 such as the signal EM3[n] of the third light-emitting signal control terminal EM3
  • Some embodiments of the present disclosure also provide a pixel driving circuit 31.
  • the pixel driving circuit 31 has a similar structure to the pixel driving circuit 31 shown in FIG. 13 .
  • the difference between the pixel driving circuit 31 shown in FIG. 17 and the pixel driving circuit 31 shown in FIG. 13 lies in the first reset.
  • Subcircuit 316 is connected differently.
  • the signal of the second signal control terminal S2 may be Gate[n-1] or Reset[n].
  • the structure of the pixel driving circuit 31 shown in FIG. 17 is similar to that of the pixel driving circuit 31 shown in FIG. 10 .
  • the difference between the pixel driving circuit 31 shown in Figure 17 and the pixel driving circuit 31 shown in Figure 10 is that in the pixel driving circuit 31 shown in Figure 17, the first luminescence signal control terminal EM1 and the second luminescence signal control terminal EM2 are connected to the same One signal line EM[n], and the pixel driving circuit 31 shown in FIG. 17 also includes a third reset sub-circuit 321.
  • the third reset sub-circuit 321 is coupled to the fourth voltage terminal Vinit3 and the first terminal of the driving sub-circuit 311, and is configured to write the signal vinit3 of the fourth voltage terminal Vinit3 in response to the signal of the second signal control terminal S2. Input the first terminal of the driving sub-circuit 311 to reset the first terminal of the driving sub-circuit 311.
  • the signal timing diagram of the pixel driving circuit shown in Figure 17 is similar to the signal timing diagram shown in Figure 11. The difference is that the first light-emitting signal EM1[n] and the second light-emitting signal EM2[n] are the same signal line EM[ n]. Next, the difference between the signal timing chart of the pixel driving circuit 31 shown in FIG. 17 and the signal timing chart shown in FIG. 11 will be described.
  • the signal of the first light-emitting signal control terminal EM1 and the signal of the second light-emitting signal control terminal EM2 are both EM[n].
  • the first light-emitting signal control terminal EM2 When the level of the signal EM[n] of the control terminal EM1 and the second light-emitting signal control terminal EM2 is high level, the second transistor T2 and the third transistor T3 are turned off.
  • the level of the signal EM[n] of the first light-emitting control terminal EM1 and the second light-emitting signal control terminal EM2 is low level, and the second transistor T2 and the third transistor T3 are turned on. That is to say, the signal timing of the signal EM[n] of the first light-emitting signal control terminal EM1 and the second light-emitting signal control terminal EM2 in the pixel driving circuit 31 shown in FIG. 17 is the same as the signal timing of EM2[n] in FIG. 11 Pictures are the same.
  • the gate driving signal of the tenth transistor T10 is Gate[n] or Reset[n]. Therefore, except for the signals of the first light-emitting signal control terminal EM1 and the second light-emitting signal control terminal EM2, the signal timing diagrams of the gate drive signals of other transistors at each stage are the same as the signal timing diagram shown in FIG. 11.
  • some embodiments of the present disclosure also provide a pixel driving circuit shown in Figure 18 31.
  • the pixel driving circuit 31 may also include a second reset sub-circuit 320 .
  • the second reset sub-circuit 320 is coupled to the second end and the third end of the driving sub-circuit 311 . Voltage terminal Vinit2.
  • the second reset sub-circuit 320 is configured to reset the second terminal of the driving sub-circuit 311 in response to the signal Reset[n] of the second reset signal control terminal R2.
  • the second reset sub-circuit 320 includes a ninth transistor T9 , a first pole of the ninth transistor T9 is coupled to the third voltage terminal Vinit2 , and a second pole of the ninth transistor T9 is coupled to the first transistor T1
  • the second electrode of the ninth transistor T9 is coupled to the second reset signal control terminal R2.
  • the pixel driving circuit 31 shown in FIG. 18 is based on the pixel driving circuit 31 shown in FIG. 17 and adds a ninth transistor T9.
  • the gate driving signal of the ninth transistor T9 is Reset[n]. Therefore, the signal timing chart of the pixel driving circuit 31 shown in FIG. 18 is consistent with the signal timing chart of the pixel driving circuit 31 shown in FIG. 17 .
  • Some embodiments of the present disclosure also provide a pixel driving circuit 31, as shown in Figure 19.
  • the pixel driving circuit 31 has a similar structure to the pixel driving circuit shown in Figure 1.
  • the pixel driving circuit 31 shown in Figure 19 is similar to that shown in Figure 19.
  • the difference between the pixel driving circuit shown in 1 is that the gate driving signal of the sixth transistor T6 is different.
  • the first reset sub-circuit 316 includes a sixth transistor T6 , and the gate driving signal of the sixth transistor T6 is changed from Gate[n-1] in FIG. 1 to Reset[n].
  • the pulse width of the gate driving signal of the sixth transistor T6 can be modulated, thereby achieving a balance between the initialization phase and the data writing phase in a display frame of the pixel driving circuit, and achieving better display effects.
  • the working process of the pixel driving circuit 31 shown in FIG. 19 will be introduced below with reference to FIG. 20 .
  • the difference between the signal timing diagram shown in Figure 20 and the signal timing diagram shown in Figure 2 is that the first reset signal Reset[n] is added.
  • the difference between the signal timing diagram of the pixel driving circuit 31 shown in FIG. 20 and the signal timing diagram of the pixel driving circuit shown in FIG. 2 will be described below.
  • the level of the signal Reset[n] of the first reset signal control terminal R1 is low level, and the sixth transistor T6 is turned on.
  • the signal vinit1 of the second voltage terminal Vinit1 is written into the gate of the first transistor T1 through the sixth transistor T6 and the fifth transistor T5, that is, the voltage value of the first node N1 is vinit1, and the first node N1 is initialized.
  • the signal vdata of the data signal terminal Vdata is low level.
  • the level of the signal Reset[n] of the first reset signal control terminal R1 is high level, and the sixth transistor T6 is turned off.
  • the signal vdata at the data signal terminal Vdata is high level, the voltage vdata at the data signal terminal Vdata can be written into the first pole of the first transistor T1 through the fourth transistor T4.
  • the level of the signal Reset[n] of the first reset signal control terminal R1 is high level, and the sixth transistor T6 is turned off.
  • the gate driving signal of the sixth transistor T6 in the pixel driving circuit 31 shown in FIG. 19 is the first reset signal Reset[n]
  • the gate driving signal of the fourth transistor T4 is Gate[n]
  • the gate drive signal of the sixth transistor T6 is no longer the upper-level signal of the fourth transistor T4, so the pulse width of the sixth transistor T6 can be modulated, so the time of the initialization phase can be independently controlled, thereby enabling initialization and data writing.
  • the time balance of the stages achieves a good luminous effect.
  • the array substrate 10 includes: a substrate 11 and a driving circuit layer 12 disposed on the substrate 11.
  • the substrate 11 may include a base 111 and a buffer layer (Buffer) 112.
  • the substrate 111 may be a silicon substrate or a flexible material such as polyimide (PI) or saturated polyester (PET).
  • a buffer layer 112 is provided on the substrate 111, and a driving circuit layer 12 is provided on the side of the buffer layer 112 away from the substrate 111.
  • the driving circuit layer 12 includes a functional layer and an insulating layer located between adjacent functional layers.
  • the functional layer may include: a first active layer 1211, a first gate layer 1212, a second gate layer 1213, and a second active layer. 1214.
  • An insulating layer may be provided between each functional layer, wherein the first active layer 1211, the first The gate layer 1212, the second gate layer 1213, the second active layer 1214, the third gate layer 1215 and the first source-drain metal layer 1216 are used to form a plurality of pixel driving circuits 31 in the display device.
  • a first active layer 1211 a first gate layer 1212, a second gate layer 1213, a second active layer 1214, a third gate layer 1215, a first Source-drain metal layer 1216 and second source-drain metal layer 1217.
  • a first gate insulating layer 1221 is disposed between the first active layer 1211 and the first gate layer 1212
  • a second gate insulating layer is disposed between the first gate layer 1212 and the second gate layer 1213. 1222.
  • a third gate insulating layer 1223 is provided between the second gate layer 1213 and the second active layer 1214
  • a fourth gate insulating layer is provided between the second active layer 1214 and the third gate layer 1215. 1224.
  • An interlayer dielectric layer 1225 is provided between the third gate layer 1215 and the first source-drain metal layer 1216, and a first planarization layer is provided between the first source-drain metal layer 1216 and the second source-drain metal layer 1217. 1226.
  • the second source-drain metal layer 1217 is also provided with a second planarization layer 1227 on the side away from the substrate 11.
  • the array substrate includes a plurality of pixel areas arranged in an array, and each pixel area is provided with two adjacent pixel driving circuits.
  • the first active layer provided on one side of the substrate includes a plurality of first pixel active patterns, and each first pixel active pattern includes an active layer of multiple transistors in a pixel driving circuit, as shown in Figure 22 As shown, it is a first pixel active pattern A in the first active layer 1211.
  • the first pixel active pattern A may include a first active layer S1 of a first transistor, a first active layer S1 of a second transistor, and a first active layer S1 of a second transistor.
  • Source layer S7 is a first active layer S1 of a first transistor, a first active layer S1 of a second transistor, and a first active layer S1 of a
  • the part of the first active layer 1211 located in the pixel area Q is the first pixel active pattern A of two adjacent pixel driving circuits, and the two first pixel active patterns A are mirror symmetrical.
  • the first gate layer 1212 disposed on the side of the first active layer away from the substrate includes: a plurality of gate signal lines and a first plate Cst1 of the capacitor.
  • the signal lines may be, for example, the first gate signal line R1, the second gate signal line R2, and the third gate signal line R3.
  • the first gate signal line R1, the second gate signal line R2 and the third gate signal line R3 are arranged in a cycle along the second direction Y.
  • the second gate signal line R2 passes through the sixth active layer and the seventh active layer.
  • the first gate signal line R1 passes through the fourth active layer
  • the first plate Cst1 passes through the first active layer
  • the third gate signal line R3 passes through the second active layer and the third active layer. layers.
  • the first gate layer includes a plurality of first gate signal lines and a plurality of second gate signal lines; wherein the orthographic projection of the fourth active layer on the substrate is consistent with the plurality of first gate signal lines.
  • the orthographic projection of the current-level first gate signal line on the substrate overlaps, and the orthographic projection of the sixth active layer on the substrate overlaps with the current-level second gate signal line among the plurality of second gate signal lines on the substrate.
  • the first gate signal line of the current stage or the second gate signal line of the current stage refers to one of multiple cascaded first gate signal lines or second gate signal lines, with the active layer of the corresponding transistor on the substrate.
  • the orthographic projections on have overlap.
  • the sixth active layer S6 of the first pixel active pattern of the next level is different from the first pixel active pattern of the current level.
  • the seventh active layer S7 of the pixel active pattern is located in the same area O extending along the first direction X, and the size of the area O in the second direction Y is smaller than that of the first pixel active pattern in the second direction Y. size of.
  • a second gate signal line R2 passes through the sixth active layer S6 of the current level's first pixel active pattern and the seventh active layer S7 of the previous level's first pixel active pattern; the other adjacent one
  • the second gate signal line R2 passes through the seventh active layer S7 of the first pixel active pattern of the current stage and the sixth active layer S6 of the first pixel active pattern of the next stage.
  • each gate signal line of the first gate layer 1212 passes through the active layer of the corresponding transistor, which means that each gate signal line of the first gate layer 1212 is lined with the active layer of the corresponding transistor.
  • the orthographic projection on the substrate overlaps.
  • the orthographic projection of the first gate signal line R1 on the substrate overlaps the orthographic projection of the fourth active layer S4 of the fourth transistor, or the second gate signal line R2 overlaps.
  • the orthographic projection on the substrate overlaps the orthographic projection of the sixth active layer S6 of the sixth transistor.
  • the second gate layer 1213 is provided with a second plate Cst2 of the capacitor and a first write control data line GN1, wherein the second plate Cst2 passes through the first plate, That is to say, the first plate Cst1 and the second plate are arranged oppositely to form a capacitor.
  • the second active layer 1214 is provided with a fifth active layer S5.
  • One end of the fifth active layer S5 is electrically connected to the first plate Cst1, and the other end of the fifth active layer S5 is electrically connected to the first plate Cst1.
  • One end is electrically connected to the sixth active pattern S6, and the fifth active layer S5 passes through the first write control data line GN1.
  • the third gate layer 1215 is provided with a second write control data line GN2, and the second write control data line GN2 passes through the fifth active layer S5.
  • the active layer of the first active layer uses low temperature polysilicon (Low Temperature Poly-Silicon, LTPS), and the fifth active layer S5 of the second active layer 1215 uses low temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide, LTPO). ). Therefore, two active layers are provided to facilitate active layer pattern processing of different materials.
  • low temperature polysilicon Low Temperature Poly-Silicon, LTPS
  • LTPO Low Temperature Polycrystalline Oxide
  • Figure 30 is a partial layer structure diagram of two pixel driving circuits.
  • the partial layer structure diagram of the pixel driving circuit on the left is relative to that on the right.
  • Part of the layer structure diagram of the side pixel driving circuit lacks the second plate Cst2.
  • the first source-drain metal layer 1216 shown in FIG. 28 is provided with a first initialization signal line V1, a second initialization signal line V2, a first connection line L1, a second connection line L2 and a third connection line L3.
  • the first initialization signal line V1 is electrically connected to the other end of the sixth active layer pattern S6, and the first initialization signal line V1 is configured to transmit the vinit1 signal to the sixth active layer S6.
  • the second initialization signal line V2 is electrically connected to one end of the seventh active layer S7, and the second initialization signal line V2 is configured to transmit data to the seventh active layer S7. Lose the vinit2 signal.
  • the other end of the sixth active layer S6 is the second voltage terminal of the pixel driving circuit
  • one end of the seventh active layer S7 is the fifth voltage terminal of the pixel driving circuit. That is to say, the first initialization signal line V1 transmits the vinit1 signal to the pixel driving circuit through the other end (second voltage end) of the sixth active layer S6, and the second initialization signal line V2 passes through the seventh active layer S7. The other end (fifth voltage end) transmits the vinit2 signal to the pixel driving circuit.
  • One end of the first connection line L1 is electrically connected to one end of the first active layer S1 and the other end of the fifth active layer S5.
  • the other end of the first connection line L1 is electrically connected to one end of the sixth active layer S6.
  • Connection, specifically, one end of the first connection line L1 is electrically connected to one end of the first active layer S1 through a hole in the first active layer 1211, and one end of the first connection line L1 is also connected to the second active layer through a hole.
  • the layer 1214 is electrically connected to the other end of the fifth active layer S5; the other end of the first connection line L1 is electrically connected to the first active layer 1211 and one end of the sixth active layer S6 through a hole, thereby achieving an electrical connection between the first active layer 1211 and the sixth active layer S6.
  • the first active layer S1 and the sixth active layer S6 of the active layer 1211 are electrically connected to the fifth active layer S5 located in the second active layer.
  • the third connection line L3 is electrically connected to the second plate Cst2 and one end of the second active layer S2.
  • the third connection line L3 is configured to provide the voltage vdd to the second plate Cst2 and the second active layer S2.
  • the first source-drain metal layer 1216 is also provided with two connection terminals: a first connection terminal D1 and a second connection terminal D2.
  • the first connection terminal D1 is via a hole to the first active layer 1211 and is connected to the fourth active layer 1211 .
  • One end of layer S4 is electrically connected; the second connection end D2 is through a hole to the first active layer 1211 and is electrically connected to the connection position of the third active layer S3 and the seventh active layer S7.
  • the second source-drain metal layer 1217 is provided with a first voltage signal line Vd and a data signal line Data.
  • the first voltage signal line Vd is via a hole to the first source-drain metal layer 1216, and is connected to the third
  • the connection line L3 is electrically connected, and the data signal line Data passes through the first source-drain metal layer 1216 and is electrically connected to the first connection terminal D1.
  • one end of the second active layer S2 is the first voltage end of the pixel driving circuit
  • one end of the fourth transistor active layer pattern S7 is the data signal end of the pixel driving circuit. That is to say, the first voltage signal line V transmits the voltage vdd to the pixel driving circuit through one end (first voltage end) of the second active layer S2, and the data signal line Data passes through one end (first voltage end) of the fourth transistor active layer pattern S7. Data signal terminal) transmits voltage vdata to the pixel driving circuit.
  • multiple pixel drive circuits are arranged in an array.
  • the area where each pixel drive circuit is located includes an area along the vertical gate signal line.
  • the first gate signal line and the second gate signal line are arranged in an extending direction (first direction), the first gate signal line transmits the data signal, and the second gate signal line transmits the first reset signal.
  • the first gate signal line located in the area where the pixel driving circuit of this level is located is electrically connected to the second gate signal line located in the area of the previous level pixel driving circuit.
  • the data signal received by the pixel drive circuit at the previous level is also the first reset signal received by the pixel drive circuit at this level.
  • the gate drive signal of the fourth transistor of the pixel drive circuit at the previous level is also the pixel at this level.
  • the pulse width of the first reset signal is adjustable, that is, relative
  • the electrical signals transmitted by the first gate signal line and the electrical signals transmitted by the second gate signal line have adjustable pulse widths.
  • this embodiment provides another array substrate.
  • the other array substrate includes the pixel driving circuit provided in any of the above embodiments.
  • the pixel driving circuit includes a data writing subcircuit and a first reset subcircuit.
  • the data writing subcircuit includes a fourth transistor, and the first reset sub-circuit includes a sixth transistor.
  • another type of array substrate includes: a substrate and a driving circuit layer.
  • the position of the driving circuit layer and the structure of each film layer are consistent with the above-mentioned uniform array substrate, which will not be described in detail here.
  • another type of array substrate The first gate signal line R1 and the second gate signal line R2 of the array substrate are insulated.
  • the first gate signal line R1 and the second gate signal line R2 are insulated, so that the first gate signal line R1 and the second gate signal line R2 can transmit two different electrical signals. That is to say, when the first gate signal line R1 transmits When the pulse width of the voltage vdata is fixed, the pulse width of the first reset signal transmitted by the second gate signal line R2 is adjustable. In this way, the time of the pixel driving circuit in the initialization phase can be independently controlled, thereby enabling initialization and data The time balance of the writing stage achieves a good luminous effect.
  • the pixel driving circuit further includes a third reset sub-circuit
  • the third reset sub-circuit includes a tenth transistor
  • the first pixel active pattern further includes a tenth active pattern of the tenth transistor.
  • Layer S10 the first active layer S1, the second active layer S2 and the tenth active layer S10 are all connected to the first connection point G.
  • the first connection point G is provided on the first active layer, and the first active layer S1 and the second active layer S2 are connected to the first connection point G.
  • the first gate layer 1212 also includes a plurality of third gate signal lines and a plurality of fourth gate signal lines.
  • the second gate signal lines R2 does not pass through the seventh active layer S7, but only passes through the sixth active layer S6.
  • the fourth gate signal line R4 passes through the seventh active layer S7 and the tenth active layer S10. Specifically, the orthographic projection of the fourth gate signal line R4 on the substrate overlaps with the orthographic projection of the tenth active layer S10 on the substrate.
  • the tenth active layer S10 and the passing fourth gate signal line R4 form a tenth transistor, and the first active layer S1, the second active layer S2 and the tenth active layer S10 are all connected to the first Junction.
  • the tenth transistor transmits an electrical signal to the first connection point, which can initialize the first pole of the first transistor and prevent the voltage at the first pole of the first transistor from being affected by the voltage vdata of the previous frame. , so that the brightness of this frame is not affected by the status of the previous frame, and improves the short-term afterimage problem.
  • the third gate layer 1215 of another array substrate is disposed on the side of the first gate layer away from the substrate, and the third gate layer also includes a third initialization signal line V3 , the third initialization signal line V3 is electrically connected to the tenth active layer.
  • the third initialization signal line V3 transmits the vinit3 signal to the tenth active layer.
  • the vinit3 signal keeps the voltage at the first connection point consistent, so that the next frame image is not affected by the previous frame image. Impact.
  • the second gate layer 1214 of another array substrate is disposed between the first gate layer and the third gate layer.
  • the second gate layer 1214 also includes a plurality of first initialization signal lines V1, and a plurality of first initialization signal lines V1.
  • One of the signal lines is electrically connected to the sixth transistor active layer.
  • the patterns of the same layer in the plurality of film layers included in the array substrate are substantially mirror symmetrical.
  • the pixel driving circuit also includes a storage sub-circuit, and the second gate layer includes a second plate Cst2 of the capacitance of the storage sub-circuit; the two second plates Cst2 are connected in the same pixel area.
  • two pixel driving circuits are arranged opposite each other, that is, the two adjacent pixel driving circuits are symmetrical about an intermediate line H.
  • This structure can reduce the number of traces arranged along the second direction Y and reduce the process difficulty and improve efficiency.
  • the mirror-symmetrical connection of the two second plates Cst2 can reduce the number of via holes for electrical connection between the first voltage signal line and the second plate Cst2, thus reducing the difficulty of the production process and improving the production efficiency.
  • the first source and drain metal layer 1216 of another array substrate is disposed on the side of the third gate layer away from the substrate.
  • the first source and drain metal layer 1216 is disposed on the side of the third gate layer away from the substrate.
  • the drain metal layer 1216 includes a plurality of second initialization signal lines V2, and adjacent second initialization signal lines V2 are electrically connected. Specifically, a connecting trace is provided between two adjacent second initialization signal lines V2. L7, making the voltages of all second initialization signal lines V2 the same. Among them, one of the plurality of second initialization signal lines V2 is electrically connected to the seventh active layer S7.
  • the first source-drain metal layer 1216 also includes a fourth connection line L4, and one end of the fourth connection line L4 passes through a first via hole penetrating to the first active layer 1211. It is electrically connected to the tenth active layer S10 , and the other end of the fourth connection line L4 is electrically connected to the first connection point G through a second via hole penetrating to the first active layer 1211 .
  • the sixth active layer is electrically connected to a first initialization signal line.
  • the first source-drain metal layer 1216 also includes a fifth connection line L5.
  • One end of the fifth connection line L5 is electrically connected to the third initialization signal line through a third via hole penetrating to the third gate layer.
  • the other end of the fifth connection line L5 is electrically connected to the tenth active layer S10 through a fourth via hole penetrating to the first active layer 1211 .
  • the first source-drain metal layer 1216 also includes a sixth connection line L6, and both ends of the sixth connection line L6 pass through two of the second gate layer.
  • the fifth via hole is electrically connected to the first initialization signal line, and the middle part of the sixth connection line L6 is electrically connected to the first active layer through the sixth via hole penetrating to the first active layer.
  • the array substrate also includes a second source and drain metal layer 1217.
  • the second source and drain metal layer 1217 is disposed on the side of the first source and drain metal layer 1216 away from the substrate.
  • the metal layer 1217 includes the first voltage signal line Vd.
  • the first source-drain metal layer 1216 also includes a plurality of third connection traces L3.
  • One end of each third connection trace L3 is electrically connected to the second plate through a seventh via hole penetrating to the second gate layer.
  • the third connection trace L3 is electrically connected to the second active layer through the eighth via hole that penetrates to the first active layer, and the first voltage signal line passes through the ninth via hole that penetrates to the second source-drain metal layer.
  • the via hole is electrically connected to the third connection line L3.
  • Embodiments of the present disclosure provide a display device, including a plurality of sub-pixels arranged in an array, wherein each sub-pixel includes It includes a light-emitting element and a pixel driving circuit 31 as in any of the above embodiments.
  • an embodiment of the present disclosure provides a display device, including an array substrate as provided in any of the above embodiments, a light-emitting device layer provided on the array substrate, and an encapsulation layer provided on a side of the light-emitting device layer away from the array substrate.
  • the third signal control terminal S3 of the pixel driving circuit of the plurality of sub-pixels located in the i-th row and the first signal control terminal S1 of the pixel driving circuit of the plurality of sub-pixels located in the i-1th row are connected to the same terminal.
  • Some embodiments of the present disclosure provide a driving method for a pixel driving circuit, which is used in the pixel driving circuit 31 shown in FIG. 6, FIG. 8, FIG. 10, and FIG. 12.
  • the work flow of the pixel driving circuit 31 in a display frame includes a compensation control stage, a data writing stage and a light emitting stage.
  • the driving method includes the following steps 2101 to 2103.
  • Step 2101. Control the signal level of the first reset signal control terminal to be the first level, control the signal level of the compensation signal control terminal to be the second level, and control the signal level of the first signal control terminal to be the second level.
  • the level of the signal controlling the first light-emitting signal control terminal is the first level
  • the level of the signal controlling the second light-emitting signal control terminal is the second level.
  • the pulse width of the signal at the first reset signal control end is adjustable.
  • the signal at the first reset signal control terminal is Reset[n].
  • the first level is a low level
  • the second level is a high level
  • Step 2102. Control the signal level of the first reset signal control terminal to be the second level, control the signal level of the compensation signal control terminal to be the second level, and control the signal level of the first signal control terminal to be the first level.
  • the level of the signal controlling the first light-emitting signal control terminal is the second level, and the level of the signal controlling the second light-emitting signal control terminal is the second level.
  • Step 2103. Control the signal level of the compensation signal control terminal to be the first level, control the signal level of the first reset signal control terminal to be the second level, and control the signal level of the first signal control terminal to be the second level.
  • the level of the signal controlling the first light-emitting signal control terminal is the first level
  • the level of the signal controlling the second light-emitting signal control terminal is the first level.
  • Some embodiments of the present disclosure provide another driving method of a pixel driving circuit for the pixel driving circuit 31 shown in FIG. 13, FIG. 15, FIG. 17, and FIG. 18.
  • the work flow of the pixel driving circuit 31 in a display frame includes a compensation control stage, a data writing stage and a light emitting stage.
  • the driving method includes the following steps 2201 to 2203.
  • Step 2201 Control the signal level of the first reset signal control terminal to be the first level, control the signal level of the compensation signal control terminal to be the second level, and control the signal level of the first signal control terminal to be the second level. ;
  • the pulse width of the signal at the first reset signal control terminal is adjustable; the level of the signal controlling the first luminous signal control terminal and the second luminous signal control terminal is the second level, and the signal controlling the second signal control terminal is the first level .
  • Step 2202 Control the signal level of the first reset signal control terminal to be the second level, control the signal level of the compensation signal control terminal to be the second level, and control the signal level of the first signal control terminal to be the first level. , controlling the signal level of the first light-emitting signal control terminal and the second light-emitting signal control terminal to be the second level, controlling the signal of the second signal control terminal is the second level.
  • Step 2203. Control the signal level of the compensation signal control terminal to be the first level, control the signal level of the first reset signal control terminal to be the second level, and control the signal level of the first signal control terminal to be the second level. , controlling the signal level of the first light-emitting signal control terminal and the second light-emitting signal control terminal to be the first level, and controlling the signal of the second signal control terminal to be the second level.
  • the above driving method further includes: during the initialization phase, controlling the level of the signal of the third light-emitting signal control terminal to the second level; in the data writing stage, the level of the signal controlling the third light-emitting signal control terminal is the first level or the second level; in the light-emitting stage, the level of the signal controlling the third light-emitting signal control terminal is the first level flat.
  • the above method further includes: during the initialization phase, controlling the level of the signal at the second reset signal control end to be the first level. level; in the data writing stage, the level of the signal controlling the second reset signal control terminal is the second level; in the light-emitting stage, the level of the signal controlling the second reset signal control terminal is the second level.
  • the above method further includes: in the initialization phase, controlling the level of the signal at the third signal control terminal to the first level; in the data writing phase , the level of the signal at the third signal control terminal is controlled to be the second level; during the light-emitting phase, the level of the signal at the third signal control terminal is controlled to be the second level.

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Abstract

一种像素驱动电路(31)，包括：驱动子电路(311)、第一发光控制子电路(312)、第二发光控制子电路(313)、数据写入子电路(314)、补偿子电路(315)和第一复位子电路(316)。其中，驱动子电路(311)包括控制端、第一端和第二端；在像素驱动电路(31)的一个显示帧中的初始化阶段(t1)，驱动子电路(311)的控制端和驱动子电路(311)的第一端之间的电压差值固定。

Description

像素驱动电路及其驱动方法、阵列基板及显示装置
本申请要求于2022年5月24日提交的、申请号为202210569842.3的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素驱动电路及其驱动方法、阵列基板及显示装置。
背景技术
目前，有机发光二极管(Organic Light Emitting Diode，OLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度等优点，已广泛应用于手机、平板电脑、数码相机等显示产品。OLED显示装置可以包括多个子像素，每个子像素均包括一一对应设置的像素驱动电路和发光器件。其中，像素驱动电路可以在阵列基板栅极驱动(Gate Driver On Array，GOA)驱动信号的控制下，驱动与其对应的发光器件发光。
发明内容
一方面，提供一种像素驱动电路，包括：驱动子电路、第一发光控制子电路、第二发光控制子电路、数据写入子电路、补偿子电路和第一复位子电路；其中，驱动子电路包括控制端、第一端和第二端；在像素驱动电路的一个显示帧中的初始化阶段，驱动子电路的控制端和驱动子电路的第一端之间的电压差值固定；第一发光控制子电路耦接至第一电压端和驱动子电路的第一端，且被配置为响应于第一发光信号控制端的信号，驱动发光元件发光；第二发光控制子电路耦接至驱动子电路的第二端和发光元件的第一电极，且被配置为响应于第二发光信号控制端的信号，驱动发光元件发光；数据写入子电路耦接至数据信号端和驱动子电路的第一端，且被配置为响应于第一信号控制端的信号，将数据信号端的数据信号写入驱动子电路的第一端；补偿子电路耦接至驱动子电路的第二端和驱动子电路的控制端，且被配置为响应于补偿信号控制端的信号，对驱动子电路进行阈值补偿；第一复位子电路耦接在第二电压端和驱动子电路的控制端之间，且被配置为响应于第一复位信号控制端的信号，将第二电压端的信号写入驱动子电路的控制端，对驱动子电路的控制端进行复位；第一复位信号控制端的信号的脉宽可调。
在一些实施例中，第一复位子电路的第一端通过补偿子电路耦接至驱动子电路的控制端，第一复位子电路的第二端耦接至第二电压端。
在一些实施例中，像素驱动电路还包括第三发光控制子电路，第三发光控制子电路耦接至驱动子电路的第二端和第一复位子电路的第一端；第三发光控制子电路，被配置为响应于第三发光信号控制端的信号，在初始化阶段将驱动子电路的控制端和驱动子电路的第一端进行同步初始化，并在发光阶段驱动发光元件发光。
在一些实施例中，第一复位子电路的第一端耦接至驱动子电路的控制端，第一复位子电路的第二端耦接至第二电压端。
在一些实施例中，像素驱动电路还包括第二复位子电路，第二复位子电路耦接至第三电压端和驱动子电路的第二端；第二复位子电路，被配置为响应于第二复位信号控制端的信号，将第三电压端的信号写入驱动子电路的第二端，对驱动子电路的第二端进行复位。
在一些实施例中，第一发光信号控制端和第二发光信号控制端连接不同的信号线，第一发光控制子电路还被配置为在初始化阶段将第一电压端的信号写入驱动子电路的第一端。
在一些实施例中，第一发光信号控制端和第二发光信号控制端连接同一条信号线，像素驱动电路还包括第三复位子电路，第三复位子电路耦接至第四电压端和驱动子电路的第一端，且被配置为响应于第二信号控制端的信号，将第四电压端的信号写入驱动子电路的第一端，对驱动子电路的第一端进行复位；第四电压端的信号电压高于第一电压端的信号电压。
另一方面，提供一种像素驱动电路，包括：驱动子电路、第一发光控制子电路、第二发光控制子电路、数据写入子电路、补偿子电路和第一复位子电路；其中，驱动子电路包括控制端、第一端和第二端；第一发光控制子电路耦接至第一电压端和驱动子电路的第一端，且被配置为响应于第一发光信号控制端的信号，驱动发光元件发光；第二发光控制子电路耦接至驱动子电路的第二端和发光元件的第一电极，且被配置为响应于第二发光信号控制端的信号，驱动发光元件发光；数据写入子电路耦接至数据信号端和驱动子电路的第一端，且被配置为响应于第一信号控制端的信号，将数据信号端的数据信号写入驱动子电路的第一端；补偿子电路耦接至驱动子电路的第二端和驱动子电路的控制端，且被配置为响应于补偿信号控制端的信号，对驱动子电路进行阈值补偿；第一复位子电路耦接至补偿子电路和第二电压端，且被配置为响应于第一复位信号控制端的信号，将第二电压端的信号写入驱动子电路的控制端，对驱动子电路的控制端进行复位；第一复位信号控制端的信号的脉宽可调。
在一些实施例中，上述像素驱动电路还包括第四复位子电路，第四复位子电路耦接至第五电压端和发光元件的第一电极，且被配置为响应于第三信号控制端的信号，将第五电压端的信号写入发光元件的第一电极，对发光元件的第一电极进行复位。
在一些实施例中，上述像素驱动电路还包括存储子电路，存储子电路耦接至驱动子电路的控制端和第一电压端，且被配置为存储基于数据信号得到的补偿信号。
又一方面，提供一种阵列基板，包括：如上述实施例中任一项的像素驱动电路，其中，像素驱动电路包括数据写入子电路和第一复位子电路，数据写入子电路包括第四晶体管，第一复位子电路包括第六晶体管。
阵列基板包括：衬底、第一有源层和第一栅极层；其中，设置于衬底一侧的第一有源层包括第四晶体管的第四有源图层、第六晶体管的第六有源图层。设置于第一有源层远离衬底一侧的第一栅极层包括第一栅信号线和第二栅信号线。
第一栅信号线在衬底的正投影与第四有源图层的正投影有重叠，第二栅信号线在衬底的正投影与第六有源图层的正投影有重叠，其中，相对第一栅信号线传输的电信号，第二栅信号线传输的电信号的脉宽可调。
在一些实施例中，第一栅信号线与第二栅信号线绝缘。
在一些实施例中，像素驱动电路还包括驱动子电路、第一发光控制子电路、第二发光控制子电路和第三复位子电路，驱动子电路包括第一晶体管，第一发光控制子电路包括第二晶体管，第二发光控制子电路包括第三晶体管，第三复位子电路包括第十晶体管。
第一有源层还包括第一晶体管的第一有源图层、第二晶体管的第二有源图层、第三晶体管的第三有源图层和第十晶体管的第十有源图层，第一有源图层、第二有源图层以及第十有源图层均连接于第一连接点。
第一栅极层还包括第三栅信号线，第三栅信号线在衬底上的正投影，与第三有源图层在衬底上的正投影、第二有源图层在衬底上的正投影有重叠。第四栅信号线，第四栅信号线在衬底上的正投影与第十有源图层在衬底上的正投影有重叠。
在一些实施例中，阵列基板还包括第三栅极层，第三栅极层设置于第一栅极层远离衬底一侧，第三栅极层还包括第三初始化信号线，第三初始化信号线与第十晶体管的有源图层电连接。
在一些实施例中，阵列基板还包括第二栅极层，第二栅极层设置于第一栅极层和第三栅极层之间，第二栅极层还包括第一初始化信号线，第一初始化信号线与第六有源图层电连接。
在一些实施例中，阵列基板中，沿第一初始化信号线延伸方向布置的像素驱动电路中，每两两相邻的两个像素驱动电路的同层图案实质上镜像对称。像素驱动电路还包括存储子电路，第二栅极层包括存储子电路的电容的第二极板，其中，镜像对称的两个第二极板相连接。
在一些实施例中，像素驱动电路包括第四复位子电路，第一有源层还包括第四复位子电路的第七晶体管的有源图层。阵列基板还包括第一源漏金属层，第一源漏金属层设置于第三栅极层远离衬底一侧，第一源漏金属层包括第二初始化信号线，且相邻的第二初始化信号线之间电连接，第二初始化信号线与第七晶体管有源图层电连接。
在一些实施例中，第一连接点设置于第一源漏金属层，第一源漏金属层还包括第四连接走线，第四连接走线的一端过孔至第一有源层后与第十有源图层电连接，第四连接走线的另一端与第一连接点电连接，第一连接点过孔至第一有源层后与第二有源图层、第一有 源图层电连接。
在一些实施例中，第一源漏金属层还包括第五连接走线，第五连接走线的一端过孔至第三栅极层后与第三初始化信号线电连接，第五连接走线的另一端过孔至第一有源层后与第十有源图层电连接。
在一些实施例中，第一源漏金属层还包括第六连接走线，第六连接走线的两端过孔至第二栅极层后与第一初始化信号线电连接，第六连接走线的中部过孔至第一有源层后与第一有源图层电连接。
在一些实施例中，阵列基板还包括第二源漏金属层，第二源漏金属层设置于第一源漏金属层远离衬底一侧，第二源漏金属层包括第一电压信号线。第一源漏金属层还包括第三连接走线，第三连接走线两两镜像对称，第一电压信号线过孔至第一源漏金属层后与镜像对称的两条第三连接走线中的一条电连接。镜像对称的两条第三连接走线过孔至第二栅极层，与对应于同一个像素驱动电路的第二极板电连接。
再一方面，提供一种显示装置，包括：如上述任一实施例的显示面板。
还有一方面，提供一种像素驱动电路的驱动方法，用于驱动如上述任一实施例的像素驱动电路，其中，像素驱动电路在一个显示帧中的工作过程包括初始化阶段、数据写入阶段和发光阶段，该驱动方法包括：在初始化阶段，控制第一复位信号控制端的信号的电平为第一电平，控制补偿信号控制端的信号的电平为第二电平，控制第一信号控制端的信号的电平为第二电平；第一复位信号控制端的信号的脉宽可调；在数据写入阶段，控制第一复位信号控制端的信号的电平为第二电平，控制补偿信号控制端的信号的电平为第二电平，控制第一信号控制端的信号的电平为第一电平；在发光阶段，控制补偿信号控制端的信号的电平为第一电平，控制第一复位信号控制端的信号的电平为第二电平，控制第一信号控制端的信号的电平为第二电平。
在一些实施例中，上述像素驱动电路的驱动方法还包括：在初始化阶段，控制第一发光信号控制端的信号的电平为第一电平，控制第二发光信号控制端的信号的电平为第二电平；在初始化阶段，控制第一发光信号控制端的信号的电平为第一电平，控制第二发光信号控制端的信号的电平为第二电平；在发光阶段，控制第一发光信号控制端的信号的电平为第一电平，控制第二发光信号控制端的信号的电平为第一电平。
在一些实施例中，上述像素驱动电路还包括第三复位子电路，第三复位子电路耦接至第四电压端和驱动子电路的第一端，且第三复位子电路的控制端被配置为接收第二信号控制端的信号；第四电压端的信号电压高于第一电压端的信号电压；上述方法还包括：在初始化阶段，控制第一发光信号控制端和第二发光信号控制端的信号的电平为第二电平，控制第二信号控制端的信号为第一电平；在数据写入阶段，控制第一发光信号控制端和第二发光信号控制端的信号的电平为第二电平，控制第二信号控制端的信号为第二电平；在发 光阶段，控制第一发光信号控制端和第二发光信号控制端的信号的电平为第一电平，控制第二信号控制端的信号为第二电平。
在一些实施例中，上述第一复位子电路的第一端通过补偿子电路耦接至驱动子电路的控制端，第一复位子电路的第二端耦接至第二电压端；像素驱动电路还包括第三发光控制子电路，第三发光控制子电路耦接至驱动子电路的第二端和第一复位子电路的第一端，第三发光控制子电路控制端被配置为接收第三发光信号控制端的信号；上述方法还包括：在初始化阶段，控制第三发光信号控制端的信号的电平为第二电平；在数据写入阶段，控制第三发光信号控制端的信号的电平为第一电平或第二电平；在发光阶段，控制第三发光信号控制端的信号的电平为第一电平。
在一些实施例中，上述第一复位子电路的第一端耦接至驱动子电路的控制端，第一复位子电路的第二端耦接至第二电压端；像素驱动电路还包括第二复位子电路，第二复位子电路耦接至第三电压端和驱动子电路的第二端，第二复位子电路的控制端被配置为接收第二复位信号控制端的信号；上述方法还包括：在初始化阶段，控制第二复位信号控制端的信号的电平为第一电平；在数据写入阶段，控制第二复位信号控制端的信号的电平为第二电平；在发光阶段，控制第二复位信号控制端的信号的电平为第二电平。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为相关技术中的像素驱动电路的结构图；
图2为相关技术中的像素驱动电路的信号时序图；
图3为根据一些实施例的显示面板的结构图之一；
图4为根据一些实施例的一种像素驱动电路的框图；
图5为根据一些实施例的另一种像素驱动电路的框图；
图6为根据一些实施例的一种像素驱动电路的电路图；
图7为根据一些实施例的一种像素驱动电路的信号时序图；
图8为根据一些实施例的另一种像素驱动电路的电路图；
图9为根据一些实施例的另一种像素驱动电路的信号时序图；
图10为根据一些实施例的又一种像素驱动电路的电路图；
图11为根据一些实施例的又一种像素驱动电路的信号时序图；
图12为根据一些实施例的又一种像素驱动电路的电路图；
图13为根据一些实施例的又一种像素驱动电路的电路图；
图14A为根据一些实施例的又一种像素驱动电路的信号时序图；
图14B为根据一些实施例的又一种像素驱动电路的信号时序图；
图15为根据一些实施例的又一种像素驱动电路的电路图；
图16为根据一些实施例的又一种像素驱动电路的信号时序图；
图17为根据一些实施例的又一种像素驱动电路的电路图；
图18为根据一些实施例的又一种像素驱动电路的电路图；
图19为根据一些实施例的又一种像素驱动电路的电路图；
图20为根据一些实施例的又一种像素驱动电路的信号时序图；
图21为根据一些实施例的一种阵列基板的截面图；
图22为根据一些实施例的一种第一有源层的结构图；
图23为根据一些实施例的一种第一栅极层的结构图；
图24为根据一些实施例的一种第一栅极层和第一栅极层的结构图；
图25为根据一些实施例的一种第二栅极层的结构图；
图26为根据一些实施例的一种第二有源层的结构图；
图27为根据一些实施例的一种第三栅极层的结构图；
图28为根据一些实施例的一种第一源漏金属层的结构图；
图29为根据一些实施例的一种第二源漏金属层的结构图；
图30为根据一些实施例的一种阵列基板部分图层的结构图；
图31为根据一些实施例的一种阵列基板的结构图；
图32为根据一些实施例的另一种第一有源层的结构图；
图33为根据一些实施例的另一种第一有源层和第一源漏金属层的结构图；
图34为根据一些实施例的另一种第一栅极层的结构图；
图35为根据一些实施例的另一种第一有源层和第一栅极层的结构图；
图36为根据一些实施例的另一种第二栅极层的结构图；
图37为根据一些实施例的另一种第三栅极层的结构图；
图38为根据一些实施例的另一种第一源漏金属层的结构图；
图39为根据一些实施例的另一种阵列基板的结构图；
图40为根据一些实施例的一种像素驱动电路的驱动方法的流程图；
图41为根据一些实施例的另一种像素驱动电路的驱动方法的流程图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的 实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
本公开的实施例提供的电路中所采用的晶体管可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。
在整个说明书中，所提到的“一个实施例”意味着所描述的与该实施例相关的特定特征、结构或特性被包括在至少一个实施例中。因此，在整个说明书中，在各个地方出现的短语“在一个实施例中”不一定都指同一个实施例。此外，这些特定特征、结构或特性可以以任意合适的方式组合在一个或多个实施例中。
图1为一种相关技术中的像素驱动电路的电路图。如图1所示，该像素驱动电路包括7个晶体管和1个电容器，7个晶体管分别为晶体管T1至晶体管T7，1个电容为电容Cst。
在一些实施例中，一个像素驱动电路在一个显示帧中的工作过程可以包括：初始化阶段t1、数据写入阶段t2和发光阶段t3。下面结合图2对图1所示的像素驱动电路的工作过程进行介绍。
在初始化阶段t1，晶体管T6和晶体管T7的栅极驱动信号Gate[n-1]为低电平，晶体管T5的栅极驱动信号Gate_N[n]为高电平，晶体管T2和晶体管T3的栅极驱动信号EM[n]为高电平，晶体管T4的栅极驱动信号Gate[n]为高电平。如此一来，在初始化阶段t1，晶体管T5、晶体管T6和晶体管T7导通，晶体管T1至晶体管T4截止，从而电压端Vinit1输出的电压vinit1可以通过导通的晶体管T5和晶体管T6提供给晶体管T1的栅极，即第一节点N1，从而使晶体管T1的栅极的电压为vinit1，实现对晶体管T1的栅极初始化。同时，电压端Vinit2输出的电压vinit2可以通过导通的晶体管T7提供给发光元件的第一电极，以对发光元件的第一电极进行复位。
在数据写入阶段t2，晶体管T6和晶体管T7的栅极驱动信号Gate[n-1]为高电平，晶体管T5的栅极驱动信号Gate_N[n]为高电平，晶体管T2和晶体管T3的栅极驱动信号EM[n]为高电平，晶体管T4的栅极驱动信号Gate[n]为低电平。如此一来，在数据写入阶段t2， 晶体管T4、晶体管T5导通，晶体管T1至晶体管T3、晶体管T6和晶体管T7截止，从而数据信号端Vdata输出的电压vdata可以通过晶体管T4写入第一晶体管T1的第一极，即第二节点N2，从而使晶体管T1的第一极的电压为vdata，实现对晶体管T1的第一极初始化。
在发光阶段t3，晶体管T6和晶体管T7的栅极驱动信号Gate[n-1]为高电平，晶体管T5的栅极驱动信号Gate_N[n]为低电平，晶体管T2和晶体管T3的栅极驱动信号EM[n]为低电平，晶体管T4的栅极驱动信号Gate[n]为高电平。如此一来，在发光阶段t3，晶体管T1至晶体管T3导通，晶体管T4至晶体管T7截止，从而电压端VDD输出的电压vdd可以通过晶体管T1至晶体管T3提供给发光元件的第一电极，实现驱动发光元件发光。
结合图1和图2可知，在初始化阶段t1，晶体管T1的栅极电压和漏极电压为vinit1，晶体管T1的源极电压会被下拉放电至vinit1-Vth截止，从而使得晶体管T1的栅极与漏极之间产生固定电压差，晶体管T1处于固定偏置的截止状态(off-bias)。采用该方案时，无论前一帧的数据信号为黑态还是白态信号，晶体管T1都由固定偏置的截止状态开始进入数据写入阶段t2，从而可以改善由于迟滞效应可能产生的短期残像问题。但是，该方案中晶体管T1上的固定电压差是被动产生的偏压，因此偏压效果不佳，导致改善残像的效果不佳。
另外，由于晶体管T4的栅极驱动信号为Gate[n]，晶体管T6的栅极驱动信号为Gate[n-1]，即T6的栅极驱动信号Gate[n-1]为晶体管T4的栅极驱动信号Gate[n]的上一级信号。因此T6的栅极驱动信号的脉宽无法调制，即不能独立控制初始化阶段的时间，故不能保证初始化阶段和数据写入阶段时间平衡，无法达到良好的发光效果。
为解决上述问题，本公开一些实施例提供一种像素驱动电路和显示装置，
该像素驱动电路在初始化阶段，能够确保驱动子电路的控制端和驱动子电路的第一端之间的电压差值固定，即能够确保驱动晶体管的栅极和源极之间的电压差值固定，因此在初始化阶段第一晶体管为固定VGS偏压信号(on-bias)。由于第一晶体管上的固定电压差是主动产生的偏压，与图1所示的方案中第一晶体管上被动产生的偏压相比，能够改善由于第一晶体管的迟滞效应引起的残像问题。而且通过将第六晶体管配置为响应于第一复位信号实现第一晶体管栅极的复位，由于该第一复位信号和第四晶体管的栅极驱动信号连接不同的信号线，因此初始化阶段的时间能够独立控制，从而实现初始化和数据写入阶段的时间平衡，达到良好的发光效果。
针对上述技术问题，本公开的一些实施例提供一种显示装置30，该显示装置30可以为平板电脑，显示器，手机，广告牌，数码相框或个人数字助理(Personal Digital Assistant，PDA)等任何具有显示功能的装置。
示例性地，显示装置30可以为有机电致发光二极管(Organic Light-Emitting Diode， OLED)显示装置、量子点电致发光二极管(Quantum Dot Light Emitting Diodes，QLED)显示装置或有源矩阵有机发光二极管(Active-Matrix Organic Light Emitting Diode，AMOLED)显示装置。本申请实施例对显示装置30的具体类型不做特殊限制。以下实施例以OLED显示装置为例进行详细说明。
如图3所示，显示装置30包括显示区A，以及设置在显示区A至少一侧的周边区B。显示区A为显示图像的区域，显示区A被配置为设置子像素P。周边区B为不显示图像的区域，周边区B被配置为设置显示驱动电路，例如，栅极驱动电路和源极驱动电路。
该多个子像素P排列为多行和多列，每行包括沿第一方向X排列的多个子像素P，每列包括沿第二方向Y排列的多个子像素P。其中，每行子像素P可以包括多个子像素P，每列子像素P可以包括多个子像素P。
此处，第一方向X和第二方向Y相互交叉。第一方向X和第二方向Y之间的夹角可以根据实际需要选择设置。示例性地，第一方向X和第二方向Y之间的夹角可以为85°、89°或90°等。
在一些实施例中，如图3所示，上述显示装置30还可以包括位于显示区A的多条栅线GL以及多条数据线DL。其中，该多条栅线GL沿第一方向X延伸，该多条数据线DL沿第二方向Y延伸。
示例性地，可以将沿第一方向X排列成一行的子像素P称为同一行子像素P，将沿第二方向Y排列成一列的子像素P称为同一列子像素P。同一行子像素P可以与同一条栅线GL耦接，同一列子像素P可以与同一条数据线DL耦接。
每个子像素P均可以包括像素驱动电路31及与像素驱动电路31耦接的发光元件。其中，一条栅线GL可以与同一行子像素P中的多个像素驱动电路31耦接，一条数据线DL可以与同一列子像素P中的多个像素驱动电路31耦接。
对于每一个子像素P，其像素驱动电路31可以通过栅线GL接收GOA驱动信号(例如，第一发光信号控制端的信号、第二发光信号控制端的信号、第三发光信号控制端的信号、第一信号控制端的信号、第二信号控制端的信号、第三信号控制端的信号、补偿信号控制端的信号、第一复位信号控制端的信号、第二复位信号控制端的信号)，并通过数据线DL接收数据电压端的电压信号，以使得该像素驱动电路31在GOA驱动信号的控制下，驱动对应的发光元件根据数据电压端的电压信号进行发光。
本公开的一些实施例提供一种像素驱动电路31，如图4所示，该像素驱动电路31包括：驱动子电路311、第一发光控制子电路312、第二发光控制子电路313、数据写入子电路314、补偿子电路315、第一复位子电路316。该像素驱动电路31被配置为生成驱动电流以控制发光元件发光。
驱动子电路311包括控制端、第一端和第二端。该驱动子电路311用于提供驱动发光 元件发光的驱动电流。其中，在像素驱动电路31的一个显示帧中的初始化阶段t1，驱动子电路311的控制端和驱动子电路的第一端之间的电压差值固定。
第一发光控制子电路312耦接至第一电压端VDD和驱动子电路311的第一端，且被配置为响应于第一发光信号控制端EM1的信号，驱动发光元件发光。
第二发光控制子电路313耦接至驱动子电路311的第二端和发光元件的第一电极，且被配置为响应于第二发光信号控制端EM2的信号，驱动发光元件发光。
数据写入子电路314耦接至数据信号端Vdata和驱动子电路311的第一端，且被配置为响应于第一信号控制端S1的信号Gate[n]，将数据信号端Vdata的信号写入驱动子电路311的第一端。
补偿子电路315耦接至驱动子电路311的第二端和驱动子电路311的控制端，且被配置为响应于补偿信号控制端G1的信号，对驱动子电路311进行阈值补偿。
第一复位子电路316耦接在第二电压端Vinit1和驱动子电路311的控制端之间，且被配置为响应于第一复位信号控制端R1的信号，将第二电压端Vinit1的信号写入驱动子电路311的控制端，对驱动子电路311的控制端进行复位。
在一些实施例中，第一复位子电路316可以通过两种电路结构耦接在第二电压端Vinit1和驱动子电路311的控制端之间，下面分别对这两种电路结构进行介绍。
第一种电路结构，如图4所示，第一复位子电路316的第一端通过补偿子电路315耦接至驱动子电路311的控制端，第一复位子电路316的第二端耦接至第二电压端Vinit1。
第二种电路结构，如图5所示，第一复位子电路316的第一端耦接至驱动子电路311的控制端，第一复位子电路316的第二端耦接至第二电压端Vinit1。
在一些实施例中，第一发光信号控制端EM1和第二发光信号控制端EM2可以连接同一条GOA驱动信号线，也可以连接不同的GOA驱动信号线。
示例性的，当第一发光信号控制端EM1和第二发光信号控制端EM2连接不同的GOA驱动信号线时，第一发光控制子电路312被配置为在初始化阶段t1，将第一电压端VDD的信号vdd写入驱动子电路311的第一端，并在发光阶段t3驱动发光元件发光。
例如，如图6、图8、图10、图12所示的像素驱动电路中，第一发光信号控制端EM1和第二发光信号控制端EM2连接不同的GOA驱动信号线，第一发光信号控制端EM1的信号为EM1[n]，第二发光信号控制端EM2的信号为EM2[n]。
可以理解的，本公开实施例通过在初始化阶段t1，将第一电压端VDD的信号vdd写入驱动子电路311的第一端，从而确保驱动子电路311的第一端为固定电压。由于在初始化阶段t1，驱动子电路311的第一端的电压为vdd，驱动子电路311的控制端电压和第二端电压接近于电压vinit1，因此在初始化阶段t1，驱动子电路311的栅源电压VGS为vinit1-vdd，故驱动子电路311处于固定偏置的开启状态on-bias，然后再进入数据写入阶段t2时， 可以确保本帧亮度不受上一帧状态的影响，改善短期残像问题。
示例性的，当第一发光信号控制端EM1和第二发光信号控制端EM2连接同一条GOA驱动信号线时，像素驱动电路31还包括第三复位子电路321，该第三复位子电路321耦接至第四电压端Vinit3和驱动子电路311的第一端。第三复位子电路321被配置为在初始化阶段t1，响应于第二信号控制端S2的信号，将第四电压端Vinit3的信号vinit3写入驱动子电路311的第一端，对驱动子电路311的第一端进行复位。
例如，如图13、图15、图17、图18所示，第一发光信号控制端EM1和第二发光信号控制端EM2连接同一条GOA驱动信号线，第一发光信号控制端EM1的信号为EM[n]，第二发光信号控制端EM2的信号也为EM[n]。
可以理解的，本公开实施例通过在初始化阶段t1，将第四电压端Vinit3的信号vinit3写入驱动子电路311的第一端，从而确保驱动子电路311的第一端为固定电压。由于在初始化阶段t1，驱动子电路311的第一端的电压为vinit3，驱动子电路311的控制端电压和第二端电压接近于电压vinit1，因此驱动子电路311在初始化阶段时，栅源电压VGS为vinit1-vinit3，故驱动子电路311处于固定偏置的开启状态on-bias，然后再进入数据写入阶段t2时，可以确保本帧亮度不受上一帧状态的影响，改善短期残像问题。
在一些实施例中，如图4和图5所示，像素驱动电路31还可以包括存储子电路317，该存储子电路317耦接至驱动子电路311的控制端和第一电压端VDD，且被配置为存储基于数据信号vdata得到的补偿信号。
在一些实施例中，如图4和图5所示，像素驱动电路31还可以包括第四复位子电路318，第四复位子电路318耦接至第五电压端Vinit4和发光元件的第一电极，且被配置为响应于第三信号控制端S3的信号，将第五电压端Vinit4的信号vinit4写入发光元件的第一电极，对发光元件的第一电极进行复位。
本公开的一些实施例中，可以通过多种不同电路结构的像素驱动电路31实现在初始化阶段t1，确保驱动子电路311的控制端和驱动子电路的第一端之间的电压差值固定这一方案。下面以像素驱动电路31为图6、图8、图10、图12、图13、图15、图17、图18所示的像素驱动电路为例，对每个像素驱动电路31的工作过程进行介绍。
如图6所示，像素驱动电路31中的驱动子电路311包括第一晶体管T1，第一晶体管T1的栅极为驱动子电路的控制端，第一晶体管T1的第一极为驱动子电路311的第一端，第一晶体管T1的第二极为驱动子电路311的第二端。第一晶体管T1的栅极耦接至第一节点N1，第一晶体管T1的源极耦接至第二节点N2，第一晶体管T1的漏极耦接至第三节点N3。
示例性的，第一晶体管T1可以为驱动薄膜晶体管(Driving Thin Film Transistor，DTFT)，本公开对于第一晶体管T1的类型不作限定，该第一晶体管T1可以为能够提供驱动发光元 件发光的驱动电流的任一类型的晶体管。
在一些实施例中，如图6所示，第一发光控制子电路312包括第二晶体管T2，该第二晶体管T2的第一极耦接至第一电压端VDD，第二晶体管T2的第二极耦接至第一晶体管T1的第一极，第二晶体管T2的栅极耦接至第一发光信号控制端EM1。
示例性地，第二晶体管T2响应于第一发光信号控制端EM1的信号EM1[n]，可以导通或截止。在初始化阶段t1，当第二晶体管T2导通时，第一电压端VDD与第一晶体管T1的第一极之间的连接导通，即可将第一电压端VDD的信号vdd写入以第一晶体管T1的第一极，即第二节点N2的电压为vdd。
在一些实施例中，如图6所示，第二发光控制子电路313包括第三晶体管T3，该第三晶体管T3的第一极耦接至第一晶体管T1的第二极，第三晶体管T3的第二极耦接至发光元件的第一电极，第三晶体管T3的栅极耦接至第二发光信号控制端EM2。
可以理解的，在本公开实施例中第一发光控制子电路312中的第二晶体管T2的栅极驱动信号为EM1[n]，第二发光控制子电路313中的第三晶体管T3的栅极驱动信号为EM2[n]。即，第一发光控制子电路312中的第二晶体管T2的栅极驱动信号与第二发光控制子电路313中的第三晶体管T3的栅极驱动信号不同。而且通过在初始化阶段t1，将第一发光控制子电路312中的第二晶体管T2导通，使得第一电压端VDD的信号vdd可以写入第一晶体管T1的第一极，从而确保第一晶体管T1的第一极为固定电压。由于在初始化阶段t1，第一晶体管T1的第一极电压为vdd，第一晶体管T1的栅极电压和第二极电压接近于电压vinit1，因此第一晶体管T1在初始化阶段t1时，栅源电压VGS为vinit1-vdd，故第一晶体管T1处于固定偏置的开启状态on-bias，然后再进入数据写入阶段t2时，可以确保本帧亮度不受上一帧状态的影响，改善短期残像问题。
在一些实施例中，如图6所示，数据写入子电路314包括第四晶体管T4，第四晶体管T4的第一极耦接至数据信号端Vdata，第四晶体管T4的第二极耦接至第一晶体管T1的第一极和第二晶体管T2的第二极，第四晶体管T4的栅极耦接至第一信号控制端S1。
在一些实施例中，如图6所示，补偿子电路315包括第五晶体管T5，第五晶体管T5的第一极耦接至第一晶体管T1的栅极，第五晶体管T5的第二极耦接至第一晶体管T1的第二极，第五晶体管T5的栅极耦接至补偿信号控制端G1。
在一些实施例中，如图6所示，第一复位子电路316包括第六晶体管T6，第六晶体管T6的第一极耦接至第五晶体管T5的第二极，第六晶体管T6的第二极耦接至第二电压端Vinit1，第六晶体管T6的栅极耦接至第一复位信号控制端R1。
在一些实施例中，如图6所示，存储子电路317包括电容Cst，电容Cst的一端耦接至第一电压端VDD，电容Cst的另一端耦接至第一晶体管T1的栅极。电容Cst被配置为存储基于数据信号vdata得到的补偿信号。
在一些实施例中，如图6所示，第四复位子电路318包括第七晶体管T7，第七晶体管T7的第一极耦接至第五电压端Vinit4，第七晶体管T7的第二极耦接至发光元件的第一电极，第七晶体管T7的栅极耦接至第三信号控制端S3。当第七晶体管T7导通时，可将第五电压端Vinit4的信号vinit4写入发光元件的第一电极，以实现对发光元件的第一电极进行复位。
本公开实施例中的晶体管的第一极可以为源极和漏极中的一者，晶体管的第二极可以为源极和漏极中的另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性的，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。本公开对于上述第一晶体管T1至第十晶体管T10的类型是N型还是P型并不限定。
本公开实施例中的像素驱动电路31的一个驱动周期包括初始化阶段t1、数据写入阶段t2和发光阶段t3三个阶段。下面以第一晶体管T1至第四晶体管T4、第六晶体管T6和第七晶体管T7为P型，第五晶体管T5为N型为例，结合图7对图6所示的像素驱动电路31的工作过程进行介绍。
如图7所示，在初始化阶段t1，第一发光信号控制端EM1的信号EM1[n]的电平为第一电平(例如，低电平)，则第二晶体管T2导通。第二发光信号控制端EM2的信号EM2[n]的电平为第二电平(例如，高电平)，则第三晶体管T3截至。第一复位信号控制端R1的信号Reset[n]的电平为第一电平，则第六晶体管T6导通。第一信号控制端S1的信号Gate[n]的电平为第二电平，则第四晶体管T4截至。补偿信号控制端G1的信号Gate_N[n]的电平为第二电平，即第五晶体管T5导通。第三信号控制端S3的信号Gate[n-1]的电平为第一电平，即第七晶体管T7导通。
由此一来，在初始化阶段t1，第一电压端VDD的信号vdd可经第二晶体管T2写入第一晶体管T1的第一极，即第二节点N2的电压值为vdd。第二电压端Vinit1的信号vinit1经第六晶体管T6和第五晶体管T5写入第一晶体管T1的栅极，即第一节点N1的电压值为vinit1，此时第一晶体管T1的源极和栅极之间产生固定的电压差vinit1-vdd，故第一晶体管T1处于固定偏置的开启状态on-bias，然后再进入数据写入阶段t2时，可以确保本帧亮度不受上一帧状态的影响，改善短期残像问题。同时，第五电压端Vinit4输出的电压vinit4可以通过导通的晶体管T7提供给发光元件的第一电极，以对发光元件的第一电极进行复位。
在数据写入阶段t2，第一发光信号控制端EM1的信号EM1[n]的电平为第二电平，则第二晶体管T2截至。第二发光信号控制端EM2的信号EM2[n]的电平为第二电平，则第 三晶体管T3截止。第一复位信号控制端R1的信号Reset[n]的电平为第二电平，则第六晶体管T6截至。第一信号控制端S1的信号Gate[n]的电平为第一电平，数据信号端Vdata的信号vdata的电平为第二电平，则第四晶体管T4导通。补偿信号控制端G1的信号Gate_N[n]的电平为第二电平，即第五晶体管T5导通。第三信号控制端S3的信号Gate[n-1]的电平为第二电平，即第七晶体管T7截止。
由此一来，在数据写入阶段t2，数据信号端Vdata的电压vdata可以通过第四晶体管T4写入第一晶体管T1的第一极。第五晶体管T5的导通使得第一晶体管T1可以形成二极管连接方式，从而第一晶体管T1的第一极电压vdata对第一晶体管T1的栅极进行充电直到第一晶体管T1的栅极电压为vdata+Vth为止，第一晶体管T1的栅极的电压vdata+Vth通过电容Cst进行存储。
在发光阶段t3，第一发光信号控制端EM1的信号EM1[n]的电平为第一电平，则第二晶体管T2导通。第二发光信号控制端EM2的信号EM2[n]的电平为第一电平，则第三晶体管T3导通。第一复位信号控制端R1的信号Reset[n]的电平为第二电平，则第六晶体管T6截至。第一信号控制端S1的信号Gate[n]的电平为第二电平，则第四晶体管T4截止。补偿信号控制端G1的信号Gate_N[n]的电平为第一电平，即第五晶体管T5截止。第三信号控制端S3的信号Gate[n-1]的电平为第二电平，即第七晶体管T7截止。
由此一来，在发光阶段t3，第一晶体管T1、第二晶体管T2和第三晶体管T3导通，第四晶体管T4、第五晶体管T5第六晶体管T6和第七晶体管T7截止，使得第一电压端VDD输出的电压vdd可以通过第二晶体管T2、第一晶体管T1和第三晶体管T3提供给发光元件的第一电极，实现驱动发光元件发光。同时，在发光阶段t3，第一晶体管T1的第一极的电压为vdata，基于电容Cst的保持作用，第一晶体管T1的栅极的电压为vdata+Vth，这样可以使第一晶体管T1处于饱和状态。从而使第一晶体管T1产生驱动电流Ids＝K*(Vgs-Vth)2＝K*((vdata+Vth-vdd)-Vth)2＝K*(vdata-vdd)2，K为与工艺和设计有关的结构常数。因此，第一晶体管T1的产生的驱动电流不受第一晶体管T1的阈值电压Vth的影响，因此能够改善因Vth不均匀导致显示面板出现的亮度不均匀(mura)的问题。
在一些实施例中，图6所示的像素驱动电路31中的第六晶体管T6也可以是N型。当第六晶体管T6为N型晶体管时，与图7所示的信号时序图不同的是，在初始化阶段t1，第一复位信号控制端R1的信号Reset[n]的电平为高电平，第六晶体管T6导通。在数据写入阶段t2和发光阶段t3，第一复位信号控制端R1的信号Reset[n]的电平为低电平，第六晶体管T6截止。
可以理解的是，由于图6所示的像素驱动电路31中第六晶体管T6的栅极驱动信号为Reset[n]，第四晶体管T4的栅极驱动信号为Gate[n]，即第六晶体管T6的栅极驱动信号不再是第四晶体管T4的上一级信号，因此第六晶体管T6的脉宽可以调制，故初始化阶段的 时间能够独立控制，从而能够实现初始化和数据写入阶段的时间平衡，达到良好的发光效果。
在一些实施例中，在初始化阶段t1，第三晶体管T3和第四晶体管T4截止，第一晶体管T1、第二晶体管T2、第五晶体管T5、第六晶体管T6和第七晶体管T7导通。由于第一电压端VDD的电压vdd经过第二晶体管T2可以写入第二节点N2，此时第一节点N1、第二节点N2和第三节点N3之间短路，第二晶体管T2的分压使得N2节点的电压值略低于vdd，节点N1和N3的电压会略高于vinit1，因此会产生一点功耗，但这并不影响第一晶体管T1的栅极和源极之间产生固定的电压差，也不会影响on-bias偏压效果。
为了确保在初始化阶段t1，对第一节点N1和第二节点N2进行同步初始化，进一步改善短期残像问题，本公开的一些实施例还提供图8所示的一种像素驱动电路31。
如图8所示，像素驱动电路31除包括图6所示的电路外，还可以包括第三发光控制子电路319，第三发光控制子电路319耦接至驱动子电路311的第二端和第一复位子电路316的第一端。该第三发光控制子电路319，被配置为响应于第三发光信号控制端EM3的信号EM3[n]，在初始化阶段t1将驱动子电路311的控制端和驱动子电路311的第一端进行同步初始化，并在发光阶段t3驱动发光元件发光。
如图8所示，第三发光控制子电路319包括第八晶体管T8，第八晶体管T8的第一极耦接至第一晶体管T1的第二极，第八晶体管T8的第二极耦接至第六晶体管T6的第一极、第三晶体管T3的第一极和第五晶体管T5的第二极。第八晶体管T8的栅极耦接至第三发光信号控制端EM3。
图8所示的像素驱动电路31在一个显示帧中的工作流程与图6所示的像素驱动电路31在一个显示帧中的工作流程类似，下面结合图9，对图8所示的像素驱动电路31在一个显示帧中的工作流程与图6所示的像素驱动电路31在一个显示帧中的工作流程的区别进行说明。
结合图8，如图9所示，在初始化阶段t1，第三发光信号控制端EM3的信号EM3[n]的电平为第二电平，则第八晶体管T8截止。从而使得在初始化阶段t1，第一节点N1和第二节点N2能够同步初始化，从而确保第一晶体管T1的栅极和源极产生稳定的电压差，达到更好的on-bias偏压效果，从而更好的改善残像问题。
结合图8，如图9所示，在数据写入阶段t2，第三发光信号控制端EM3的信号EM3[n]的电平可以为第一电平，也可以为第二电平。当第三发光信号控制端EM3的信号EM3[n]的电平为第一电平时，第八晶体管T8导通。当第三发光信号控制端EM3的信号EM3[n]的电平为第二电平时，第八晶体管T8截止。图9以在数据写入阶段t2，第三发光信号控制端EM3的信号EM3[n]的电平为第一电平为例进行示例性示意。
结合图8，如图9所示，在发光阶段t3，第三发光信号控制端EM3的信号EM3[n]的 电平为第一电平，则第八晶体管T8导通。因此，在发光阶段t3，第一晶体管T1、第二晶体管T2、第三晶体管T3和第八晶体管T8导通，第四晶体管T4至第七晶体管T7截止，使得像素驱动电路的第一电压端VDD与电压端VSS之间形成电流通路，从而驱动发光元件发光。
可以理解地，由于图8所示的像素驱动电路31是在图6所示的像素驱动电路31的基础上增加了第八晶体管T8。因此，除第八晶体管T8的栅极驱动信号(如，第三发光信号控制端EM3的信号EM3[n])外，其他晶体管的栅极驱动信号在各个阶段的控制方式及工作流程均与图6所示的像素驱动电路31在一个显示帧中的工作流程相同。
本公开的一些实施例还提供一种像素驱动电路31。如图10所示，该像素驱动电路31与图6所示的像素驱动电路31的结构类似，图10所示的像素驱动电路31与图6所示的像素驱动电路31的区别在于第一复位子电路316的连接方式不同。下面对图10所示的像素驱动电路31的结构与图6所示的像素驱动电路31的结构的区别进行说明。
在一些实施例中，如图10所示，第一复位子电路316包括第六晶体管T6，第六晶体管T6的第一极耦接至第一晶体管T1的栅极和第五晶体管T5的第一极，第六晶体管T6的第二极耦接至第二电压端Vinit1，第六晶体管T6的栅极耦接至第一复位信号控制端R1。
示例性的，第六晶体管T6响应于第一复位信号控制端R1的信号Reset[n]，可以导通或截止。当第六晶体管T6截止，第二电压端Vinit1的电压vinit1无法写入第一晶体管T1的栅极，无法对第一晶体管T1的栅极进行复位。当第六晶体管T6导通，第二电压端Vinit1的电压vinit1可以写入第一晶体管T1的栅极，可以对第一晶体管T1的栅极进行复位。
下面以第一晶体管T1至第四晶体管T4、第六晶体管T6和第七晶体管T7为P型，第五晶体管T5为N型为例，结合图11对图10所示的像素驱动电路31的工作过程进行介绍。
如图11所示，在初始化阶段t1，第一发光信号控制端EM1的信号EM1[n]的电平为低电平，则第二晶体管T2导通。第二发光信号控制端EM2的信号EM2[n]的电平为高电平，则第三晶体管T3截至。第一复位信号控制端R1的信号Reset[n]的电平为低电平，则第六晶体管T6导通。第一信号控制端S1的信号Gate[n]的电平为高电平，则第四晶体管T4截至。补偿信号控制端G1的信号Gate_N[n]的电平为低电平，即第五晶体管T5截止。第三信号控制端S3的信号Gate[n-1]的电平为低电平，即第七晶体管T7导通。
由此一来，在初始化阶段t1，第一电压端VDD的信号vdd可经第二晶体管T2写入第一晶体管T1的第一极，即第二节点N2的电压值为vdd。第二电压端Vinit1的信号vinit1经第六晶体管T6写入第一晶体管T1的栅极，即第一节点N1的电压值为vinit1，此时第一晶体管T1的源极和栅极之间产生固定的电压差vinit1-vdd，故第一晶体管T1处于固定偏置的开启状态on-bias，然后再进入数据写入阶段时，可以确保本帧亮度不受上一帧状态 的影响，改善短期残像问题。同时，第五电压端Vinit4的信号vinit4可以通过导通的晶体管T7提供给发光元件的第一电极，以对发光元件的第一电极进行复位。
如图11所示，在数据写入阶段t2，第一发光信号控制端EM的信号EM1[n]的电平为高电平，则第二晶体管T2截至。第二发光信号控制端EM2的信号EM2[n]的电平为高电平，则第三晶体管T3截止。第一复位信号控制端R1的信号Reset[n]的电平为高电平，则第六晶体管T6截至。第一信号控制端S1的信号Gate[n]的电平为低电平，则第四晶体管T4导通。补偿信号控制端G1的信号的电平Gate_N[n]为高电平，即第五晶体管T5导通。第三信号控制端S3的信号Gate[n-1]的电平为高电平，即第七晶体管T7截止。
由此一来，在数据写入阶段t2，数据信号端Vdata的电压vdata可以通过第四晶体管T4写入第一晶体管T1的第一极。第五晶体管T5的导通使得第一晶体管T1可以形成二极管连接方式，从而第一晶体管T1的第一极电压vdata对第一晶体管T1的栅极进行充电直到第一晶体管T1的栅极电压为vdata+Vth为止，第一晶体管T1的栅极的电压vdata+Vth通过电容Cst进行存储。
如图11所示，在发光阶段t3，第一发光信号控制端EM1的信号EM1[n]的电平为低电平，则第二晶体管T2导通。第二发光信号控制端EM2的信号EM2[n]的电平为低电平，则第三晶体管T3导通。第一复位信号控制端R1的信号Reset[n]的电平为高电平，则第六晶体管T6截至。第一信号控制端S1的信号Gate[n]的电平为高电平，则第四晶体管T4截止。补偿信号控制端G1的信号Gate_N[n]的电平为低电平，即第五晶体管T5截止。第三信号控制端S3的信号Gate[n-1]的电平为高电平，即第七晶体管T7截止。
由此一来，在发光阶段t3，第一晶体管T1、第二晶体管T2和第三晶体管T3导通，第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7截止，使得第一电压端VDD输出的电压vdd可以通过第一晶体管T1至第三晶体管T3提供给发光元件的第一电极，实现驱动发光元件发光。同时，在发光阶段t3，第一晶体管T1的第一极的电压为vdata，基于电容Cst的保持作用，第一晶体管T1的栅极的电压为vdata+Vth，这样可以使第一晶体管T1处于饱和状态，从而使第一晶体管T1产生驱动电流Ids＝K*(Vgs-Vth)2＝K*((vdata+Vth-vdd)-Vth)2＝K*(vdata-vdd)2，K为与工艺和设计有关的结构常数。因此，第一晶体管T1的产生的驱动电流不受第一晶体管T1的阈值电压Vth的影响，因此能够改善因Vth不均匀导致显示面板出现的亮度不均匀(mura)的问题。
为了确保在初始化阶段t1，对第一节点N1、第二节点N2和第三节点N3进行同步初始化，进一步改善短期残像问题，本公开的一些实施例还提供图12所示的一种像素驱动电路31。
如图12所示，像素驱动电路31除包括图10所示的电路外，还可以包括第二复位子电路320，第二复位子电路320耦接至驱动子电路311的第二端和第三电压端Vinit2。该 第二复位子电路320，被配置为响应于第二复位信号控制端R2的信号Reset[n]，对驱动子电路311的第二端进行复位。
如图12所示，第二复位子电路320包括第九晶体管T9，第九晶体管T9的第一极耦接至第三电压端Vinit2，第九晶体管T9的第二极耦接至第一晶体管T1的第二极，第九晶体管T9的栅极耦接至第二复位信号控制端R2。
图12所示的像素驱动电路31在一个显示帧中的工作流程与图10所示的像素驱动电路31在一个显示帧中的工作流程类似，下面结合图11，对图12所示的像素驱动电路31在一个显示帧中的工作流程与图10所示的像素驱动电路31在一个显示帧中的工作流程的区别进行说明。
结合图12，如图11所示，在初始化阶段t1，第二复位信号控制端R2的信号Reset[n]的电平为低电平，则第九晶体管T9导通。从而使得在初始化阶段t1，第一节点N1、第二节点N2和第三节点N3能够同步初始化，确保第一晶体管T1产生稳定的电压差，达到更好的on-bias偏压效果，更好的改善残像问题。
结合图12，如图11所示，在数据写入阶段t2和发光阶段t3，第二复位信号控制端R2的信号Reset[n]的电平为高电平，第九晶体管T9截止。
可以理解地，由于图12所示的像素驱动电路31是在图10所示的像素驱动电路31的基础上增加了第九晶体管T9，第九晶体管T9的栅极驱动信号为Reset[n]。因此，图12所示的像素驱动电路31的工作流程与图10所示的像素驱动电路31在一个显示帧中的工作流程相同，即图12所示的像素驱动电路31的驱动方法的信号时序图如图11所示。
本公开的一些实施例还提供一种像素驱动电路31。如图13所示。该像素驱动电路31除包括图6所示的电路外，还可以包括第三复位子电路321，第三复位子电路321耦接至第一发光控制子电路312的第二端和第四电压端Vinit3。该第三复位子电路321，被配置为响应于第二信号控制端S2的信号Gate[n-1]或Reset[n]，在初始化阶段t1将第四电压端Vinit3的信号vinit3写入驱动子电路311的第一端，对驱动子电路311的第一端进行复位。
如图13所示，第三复位子电路321包括第十晶体管T10，第十晶体管T10的第一极耦接至第四电压端Vinit3。第十晶体管T10的第二极耦接至第二晶体管T2的第二极、第一晶体管T1的第一极和第四晶体管T4的第二极。第十晶体管T10的栅极耦接至第二信号控制端S2。
可以理解的是，与图6所示的像素驱动电路31不同的是，图13所示的像素驱动电路中第二晶体管T2的第一发光信号控制端EM1和第三晶体管T3的第二发光信号控制端EM2可以连接同一条信号线。例如，第二晶体管T2的第一发光信号控制端EM1的信号为EM[n]，第三晶体管T3的第二发光信号控制端EM2的信号也为EM[n]。
下面以第一晶体管T1至第四晶体管T4、第六晶体管T6和第七晶体管T7、第九晶体 管T9、第十晶体管T10为P型，第五晶体管T5为N型，第十晶体管T10的栅极驱动信号为Reset[n]为例，结合图14A对图13所示的像素驱动电路31的工作过程进行介绍。
如图14A所示，在初始化阶段t1，第一发光信号控制端EM1和第二发光信号控制端EM2的信号EM[n]的电平为高电平，则第二晶体管T2和第三晶体管T3截止。补偿信号控制端G1的信号Gate_N[n]的电平为高电平，则第五晶体管T5导通。第一复位控制端R1和第二信号控制端S2的信号Reset[n]的电平为低电平，则第六晶体管T6和第十晶体管T10导通。第三信号控制端S3的信号Gate[n-1]的电平为低电平，则第七晶体管T7导通。数据写入控制端Vdata的信号vdata的电平为低电平，则第四晶体管T4截止。
由此一来，在初始化阶段t1，第四电压端Vinit3的信号vinit3可写入第一晶体管T1的第一极，即第二节点N2的电压值为vinit3。第二电压端Vinit1的信号vinit1经第六晶体管T6和第五晶体管T5写入第一晶体管T1的栅极，即第一节点N1的电压值为vinit1，此时第一晶体管T1的源极和栅极之间产生固定的电压差vinit1-vinit3，故第一晶体管T1处于固定偏置的开启状态on-bias。同时，第五电压端Vinit4输出的电压vinit4可以通过导通的晶体管T7提供给发光元件的第一电极，以对发光元件的第一电极进行复位。
在一些实施例中，第四电压端Vinit3的电压vinit3高于第一电压端VDD的电压vdd。因此，在初始化阶段t1，第四电压端Vinit3的电压vinit3可以写入第一晶体管T1的第一极，第一晶体管T1处于固定偏置的开启状态on-bias，使本帧亮度不受上一帧状态的影响。示例性的，第四电压端Vinit3的电压vinit3可以为5V。如图14A所示，在数据写入阶段t2，第一发光信号控制端EM1和第二发光信号控制端EM2的信号EM[n]的电平为高电平，则第二晶体管T2和第三晶体管T3截止。补偿信号控制端G1的信号Gate_N[n]的电平为高电平，则第五晶体管T5导通。第一复位控制端R1和第二信号控制端S2的信号Reset[n]的电平为高电平，则第六晶体管T6和第十晶体管T10截止。第三信号控制端S3的信号Gate[n-1]的电平为高电平，则第七晶体管T7截止。第一信号控制端S1的信号Gate[n]的电平为低电平，则第四晶体管T4导通。因此，在数据写入阶段t2，数据信号端Vdata的电压vdata可以通过第四晶体管T4写入第一晶体管T1的第一极。
如图14A所示，在发光阶段t3，第一发光信号控制端EM1和第二发光信号控制端EM2的信号EM[n]的电平为低电平，则第二晶体管T2和第三晶体管T3导通。补偿信号控制端G1的信号Gate_N[n]的电平为低电平，则第五晶体管T5截止。第一复位控制端R1和第二信号控制端S2的信号Reset[n]的电平为高电平，则第六晶体管T6和第十晶体管T10截止。第三信号控制端S3的信号Gate[n-1]的电平为高电平，则第七晶体管T7截止。第一信号控制端S1的信号Gate[n]的电平为高电平，则第四晶体管T4截止。因此，在发光阶段t3，第一晶体管T1、第二晶体管T2和第三晶体管T3导通，使得第一电压端VDD输出的电压vdd可以通过晶体管T1至晶体管T3提供给发光元件的第一电极，实现驱动发光元件发光。
在一些实施例中，第十晶体管T10的栅极驱动信号也可以为Gate[n-1]，图14B所示的信号时序图与图14A所示的信号时序图的区别在于第三复位子电路321的控制端信号不同。下面结合图13所示的像素驱动电路31(图13中第十晶体管T10的栅极驱动信号为Gate[n-1])，对图14B所示的像素驱动电路31的信号时序图与图14A所示的像素驱动电路31的信号时序图的区别进行说明。
如图14B所示，初始化阶段t1包括第一初始化阶段t1_1和第二初始化阶段t1_2。在第一初始化阶段t1_1，第一复位控制端R1信号Reset[n]的电平为低电平，则第六晶体管T6导通。第二信号控制端S2的信号Gate[n-1]的电平为高电平，则第十晶体管T10截止。因此，在第一初始化阶段t1_1，第五晶体管T5和第六晶体管T6导通，第二电压端Vinit1的电压vinit1通过第五晶体管T5写入第一晶体管T1的栅极，即第一节点N1的电压为vinit1，实现对第一晶体管T1栅极的初始化。
在第二初始化阶段t1_2，补偿信号控制端G1的信号Gate_N[n]的电平为低电平，则第五晶体管T5截止。第一复位控制端R1信号Reset[n]的电平为高电平，则第六晶体管T6截止。第二信号控制端S2的信号Gate[n-1]的电平为低电平，则第十晶体管T10和第七晶体管T7导通。因此，在第二初始化阶段t1_2，第四电压端Vinit3的电压vinit3写入第一晶体管T1的第一极，即第二节点N2的电压为vinit3，实现对第一晶体管T1的第一极的初始化。第五电压端Vinit4的电压vinit4通过第七晶体管T7写入发光元件的第一极，实现对发光元件的第一极的初始化。
在数据写入阶段t2和发光阶段t3，由于图14B所示的信号时序图与图14A所示的信号时序图相同，故像素驱动电路31的工作流程也是相同的，在此不再赘述。
可以理解的是，在第二初始化阶段t1_2，初始化第二节点N2时，由于第五晶体管T5截止，因此第一节点N1的电压不受第三节点N3的影响，第一晶体管T1的源极和栅极之间产生固定的电压差vinit1-vinit3，故第一晶体管T1处于固定偏置的开启状态on-bias，然后再进入数据写入阶段t2时，可以确保本帧亮度不受上一帧状态的影响，改善短期残像问题。
需要说明的是，当第十晶体管T10的栅极驱动信号为Gate[n-1]时，如图14B所示，Reset[n]，Gate[n-1]，Gate[n]可以是同一组GOA驱动信号。
为了确保在初始化阶段t1，对第一节点N1和第二节点N2进行同步初始化，进一步改善短期残像问题。本公开的一些实施例还提供图15所示的一种像素驱动电路31。该像素驱动电路31的第十晶体管的栅极驱动信号为Reset[n]。
如图15所示，像素驱动电路31除包括图13所示的电路外，还可以包括第三发光控制子电路319，图15所示的第三发光控制子电路319与图8所示的像素驱动电路31结构中的第三发光控制子电路319的连接方式与功能相同，在此不再赘述。
可以理解的是，图15所示的像素驱动电路31的信号时序图为图16，图8所示的像素驱动电路31的信号时序图为图9。图16所示的信号时序图与图9所示的信号时序图的区别在于，图16所示的信号时序图中第一发光信号控制端EM1和第二发光信号控制端EM2的信号相同，均为EM[n]。而图9所示的信号时序图中第一发光信号控制端EM1的信号和第二发光信号控制端EM2的信号不同，第一发光信号控制端EM1的信号为EM1[n]，第二发光信号控制端EM2的信号为EM2[n]。下面对图16所示的像素驱动电路31的信号时序图与图9所示的像素驱动电路31的信号时序图的区别进行说明。
结合图15，如图16所示，像素驱动电路31的第一发光信号控制端EM1的信号和第二发光信号控制端EM2的信号均为EM[n]，在初始化阶段t1和数据写入阶段t2，第一发光控制端EM1和第二发光信号控制端EM2的信号EM[n]的电平为高电平，则第二晶体管T2和第三晶体管T3截止。在发光阶段t3，第一发光控制端EM1和第二发光信号控制端EM2的信号EM[n]的电平为低电平，则第二晶体管T2和第三晶体管T3导通。
图15所示的像素驱动电路31在一个显示帧中的工作流程与图13所示的像素驱动电路31在一个显示帧中的工作流程类似，下面结合图16，对图15所示的像素驱动电路31在一个显示帧中的工作流程与图13所示的像素驱动电路31在一个显示帧中的工作流程的区别进行说明。
结合图15，如图16所示，在初始化阶段t1，第三发光信号控制端EM3的信号EM3[n]的电平为高电平，则第八晶体管T8截止。从而使得在初始化阶段t1，第一节点N1和第二节点N2能够同步初始化，从而确保第一晶体管T1的栅极和源极产生稳定的电压差，达到更好的on-bias偏压效果，从而更好的改善残像问题。
结合图15，如图16所示，在数据写入阶段t2，第三发光信号控制端EM3的信号EM3[n]的电平可以为低电平，也可以为高电平。当第三发光信号控制端EM3的信号EM3[n]的电平为低电平时，第八晶体管T8导通。当第三发光信号控制端EM3的信号EM3[n]的电平为高电平时，第八晶体管T8截止。图16以在数据写入阶段t2，第三发光信号控制端EM3的信号EM3[n]的电平为低电平为例进行示例性示意。
结合图15，如图16所示，在发光阶段t3，第三发光信号控制端EM3的信号EM3[n]的电平为低电平，则第八晶体管T8导通。因此，在发光阶段t3，第一晶体管T1、第二晶体管T2、第三晶体管T3和第八晶体管T8导通，第四晶体管T4至第七晶体管T7截止，使得像素驱动电路的第一电压端VDD与电压端VSS之间形成电流通路，从而驱动发光元件发光。
可以理解地，由于图15所示的像素驱动电路31是在图13所示的像素驱动电路31的基础上增加了第八晶体管T8。因此，除第八晶体管T8的栅极驱动信号(如，第三发光信号控制端EM3的信号EM3[n])外，其他晶体管的栅极驱动信号在各个阶段的控制方式及 工作流程均与图13所示的像素驱动电路31在一个显示帧中的工作流程相同。
本公开的一些实施例还提供一种像素驱动电路31。如图17所示，该像素驱动电路31与图13所示的像素驱动电路31的结构类似，图17所示的像素驱动电路31与图13所示的像素驱动电路31的区别在于第一复位子电路316的连接方式不同。
在一些实施例中，第二信号控制端S2的信号可以为Gate[n-1]或Reset[n]。
可以理解的是，图17所示的像素驱动电路31与图10所示的像素驱动电路31的结构类似。图17所示的像素驱动电路31与图10所示的像素驱动电路31的区别在于，图17所示的像素驱动电路31中第一发光信号控制端EM1和第二发光信号控制端EM2连接同一条信号线EM[n]，且图17所示的像素驱动电路31还包括第三复位子电路321。该第三复位子电路321耦接至第四电压端Vinit3和驱动子电路311的第一端，且被配置为响应于第二信号控制端S2的信号，将第四电压端Vinit3的信号vinit3写入驱动子电路311的第一端，对驱动子电路311的第一端进行复位。
图17所示的像素驱动电路的信号时序图与图11所示的信号时序图类似，区别在于：第一发光信号EM1[n]与第二发光信号EM2[n]为同一条信号线EM[n]。下面对图17所示的像素驱动电路31的信号时序图与图11所示的信号时序图的区别进行说明。
图17所示的像素驱动电路31中第一发光信号控制端EM1的信号和第二发光信号控制端EM2的信号均为EM[n]，在初始化阶段t1和数据写入阶段t2，第一发光控制端EM1和第二发光信号控制端EM2的信号EM[n]的电平为高电平，则第二晶体管T2和第三晶体管T3截止。在发光阶段t3，第一发光控制端EM1和第二发光信号控制端EM2的信号EM[n]的电平为低电平，则第二晶体管T2和第三晶体管T3导通。也就是说，图17所示的像素驱动电路31中第一发光信号控制端EM1和第二发光信号控制端EM2的信号EM[n]的信号时序与图11中的EM2[n]的信号时序图相同。
可以理解地，由于图17所示的像素驱动电路31是在图10所示的像素驱动电路31的基础上增加了第十晶体管T10，第十晶体管T10的栅极驱动信号为Gate[n]或Reset[n]。因此，除第一发光信号控制端EM1和第二发光信号控制端EM2的信号外，其他晶体管的栅极驱动信号在各个阶段的信号时序图均与图11所示的信号时序图相同。
为了确保在初始化阶段t1，对第一节点N1、第二节点N2和第三节点N3进行同步初始化，进一步改善短期残像问题，本公开的一些实施例还提供图18所示的一种像素驱动电路31。
如图18所示，像素驱动电路31除包括图17所示的电路外，还可以包括第二复位子电路320，第二复位子电路320耦接至驱动子电路311的第二端和第三电压端Vinit2。该第二复位子电路320，被配置为响应于第二复位信号控制端R2的信号Reset[n]，对驱动子电路311的第二端进行复位。
如图18所示，第二复位子电路320包括第九晶体管T9，第九晶体管T9的第一极耦接至第三电压端Vinit2，第九晶体管T9的第二极耦接至第一晶体管T1的第二极，第九晶体管T9的栅极耦接至第二复位信号控制端R2。
图18所示的像素驱动电路31是在图17所示的像素驱动电路31的基础上增加了第九晶体管T9，第九晶体管T9的栅极驱动信号为Reset[n]。因此，图18所示的像素驱动电路31的信号时序图与图17所示的像素驱动电路31的信号时序图一致。
本公开的一些实施例还提供一种像素驱动电路31，如图19所示，该像素驱动电路31与图1所示的像素驱动电路的结构类似，图19所示的像素驱动电路31与图1所示的像素驱动电路的区别在于第六晶体管T6的栅极驱动信号不同。如图19所示，第一复位子电路316包括第六晶体管T6，第六晶体管T6的栅极驱动信号由图1中的Gate[n-1]改变为Reset[n]。由此一来，第六晶体管T6的栅极驱动信号的脉宽可以调制，进而实现像素驱动电路的一个显示帧中的初始化阶段和数据写入阶段平衡，达到更好的显示效果。
下面结合图20对图19所示的像素驱动电路31的工作过程进行介绍。图20所示的信号时序图与图2所示的信号时序图的区别在于：增加了第一复位信号Reset[n]。下面对图20所示的像素驱动电路31的信号时序图与图2所示的像素驱动电路的信号时序图的区别进行说明。
如图20所示，在初始化阶段t1，第一复位信号控制端R1的信号Reset[n]的电平为低电平，则第六晶体管T6导通。第二电压端Vinit1的信号vinit1经第六晶体管T6和第五晶体管T5写入第一晶体管T1的栅极，即第一节点N1的电压值为vinit1，初始化第一节点N1。数据信号端Vdata的信号vdata为低电平。
如图20所示，在数据写入阶段t2，第一复位信号控制端R1的信号Reset[n]的电平为高电平，则第六晶体管T6截止。数据信号端Vdata的信号vdata为高电平，则数据信号端Vdata的电压vdata可以通过第四晶体管T4写入第一晶体管T1的第一极。
如图20所示，在发光阶段t3，第一复位信号控制端R1的信号Reset[n]的电平为高电平，则第六晶体管T6截止。
可以理解地，由于图19所示的像素驱动电路31中第六晶体管T6的栅极驱动信号为第一复位信号Reset[n]，第四晶体管T4的栅极驱动信号为Gate[n]，即第六晶体管T6的栅极驱动信号不再是第四晶体管T4的上一级信号，因此第六晶体管T6的脉宽可以调制，故初始化阶段的时间能够独立控制，从而能够实现初始化和数据写入阶段的时间平衡，达到良好的发光效果。
本公开的一些实施例提供一种阵列基板10，如图21所示，阵列基板10包括：衬底11和设置于衬底11上的驱动电路层12。其中，衬底11可以包括基底111和缓冲层(Buffer)112。其中，基底111可以为硅衬底或者可以为聚酰亚胺(PI)、饱和聚酯(PET)等柔性材 料，在基底111上设置缓冲层112，在缓冲层112远离基底111一侧设置驱动电路层12。
驱动电路层12包括功能层和位于相邻功能层之间的绝缘层，功能层可以包括：第一有源层1211、第一栅极层1212、第二栅极层1213、第二有源层1214、第三栅极层1215、第一源漏金属层1216和第二源漏金属层1217，在每个功能层之间可以设置有一个绝缘层，其中，第一有源层1211、第一栅极层1212、第二栅极层1213、第二有源层1214、第三栅极层1215和第一源漏金属层1216用于形成显示装置中的多个像素驱动电路31。
示例性地，在衬底1一侧依次设置有第一有源层1211、第一栅极层1212、第二栅极层1213、第二有源层1214、第三栅极层1215、第一源漏金属层1216和第二源漏金属层1217。其中，第一有源层1211和第一栅极层1212之间设置有第一栅极绝缘层1221，第一栅极层1212和第二栅极层1213之间设置有第二栅极绝缘层1222，第二栅极层1213和第二有源层1214之间设置有第三栅极绝缘层1223，第二有源层1214和第三栅极层1215之间设置有第四栅极绝缘层1224，第三栅极层1215和第一源漏金属层1216之间设置有层间介质层1225，第一源漏金属层1216和第二源漏金属层1217之间设置有第一平坦化层1226，第二源漏金属层1217远离衬底11一侧还设置有第二平坦化层1227。
在一些实施例中，阵列基板包括阵列布置的多个像素区域，每个像素区域设置有相邻两个像素驱动电路。其中，设置于衬底一侧的第一有源层包括多个第一像素有源图案，每个第一像素有源图案包括一个像素驱动电路中多个晶体管的有源图层，如图22所示，为第一有源层1211中的一个第一像素有源图案A，具体地，第一像素有源图案A可以包括第一晶体管的第一有源图层S1、第二晶体管的第二有源图层S2、第三晶体管的第三有源图层S3、第四晶体管的第四有源图层S4、第六晶体管的第六有源图层S6、第七晶体管的第七有源图层S7。
示例性地，第一有源层1211位于像素区域Q的部分为两个相邻的像素驱动电路的第一像素有源图案A，两个第一像素有源图案A镜像对称。
在一些实施例中，如图23所示，设置于第一有源层远离衬底一侧的第一栅极层1212包括：多条栅信号线和电容的第一极板Cst1，多条栅信号线例如可以为第一栅信号线R1、第二栅信号线R2和第三栅信号线R3。其中，第一栅信号线R1、第二栅信号线R2和第三栅信号线R3沿第二方向Y依次循环排列，具体地，第二栅信号线R2经过第六有源图层和第七有源图层，第一栅信号线R1经过第四有源图层，第一极板Cst1经过第一有源图层，第三栅信号线R3经过第二有源图层和第三有源图层。
示例性地，第一栅极层包括多条第一栅信号线和多条第二栅信号线；其中，第四有源图层在衬底上的正投影与多条第一栅信号线中的当前级第一栅信号线在衬底的正投影有重叠，第六有源图层在衬底上的正投影与多条第二栅信号线中的当前级第二栅信号线在衬底上的正投影与有重叠。
当前级第一栅信号线或者当前级第二栅信号线是指，多条级联的第一栅信号线或第二栅信号线中的一条，与对应的晶体管的有源图层在衬底上的正投影有重叠。
可以理解的是，如图24所示，在第二方向Y上排列的相邻两个有源图案中，下一级第一像素有源图案的第六有源图层S6与当前级第一像素有源图案的第七有源图层S7，位于沿第一方向X延伸的同一区域O内，该区域O在第二方向Y上的尺寸小于第一像素有源图案在第二方向Y上的尺寸。因此，一条第二栅信号线R2经过当前级第一像素有源图案的第六有源图层S6和上一级第一像素有源图案的第七有源图层S7；相邻的另一条第二栅信号线R2经过当前级第一像素有源图案的第七有源图层S7和下一级第一像素有源图案的第六有源图层S6。
需要说明的是，本公开中的“经过”是指前者在衬底上的正投影与后者在衬底上的正投影有重叠。例如图24示出的第一栅极层1212的各栅信号线经过对应晶体管的有源图层，是指第一栅极层1212的各栅信号线与对应的晶体管的有源图层在衬底上的正投影有重叠，例如可以为第一栅信号线R1在衬底上的正投影与第四晶体管的第四有源图层S4的正投影有重叠，或第二栅信号线R2在衬底上的正投影与第六晶体管的第六有源图层S6的正投影有重叠。
在一些实施例中，如图25所示，第二栅极层1213设置有电容的第二极板Cst2和第一写入控制数据线GN1，其中，第二极板Cst2经过第一极板，也就是说，第一极板Cst1和第二极板相对设置形成电容。
如图26和图31所示，第二有源层1214设置有第五有源图层S5，第五有源图层S5一端与第一极板Cst1电连接，第五有源图层S5另一端与第六有源图案S6电连接，且第五有源图层S5经过第一写入控制数据线GN1。
如图27和图31所示，第三栅极层1215设置有第二写入控制数据线GN2，第二写入控制数据线GN2经过第五有源图层S5。
第一有源层的有源图层采用低温多晶硅(Low Temperature Poly-Silicon，LTPS)，第二有源层1215的第五有源图层S5采用低温多晶氧化物(Low Temperature Polycrystalline Oxide，LTPO)。因此设置两个有源层，便于不同材质的有源层图案加工。
如图28和图30所示，其中，图30为两个像素驱动电路的部分图层结构图，在图30中，为便于视图和理解，左侧像素驱动电路的部分图层结构图相对右侧像素驱动电路的部分图层结构图缺少第二极板Cst2。图28示出的第一源漏金属层1216中设置有第一初始化信号线V1、第二初始化信号线V2、第一连接走线L1、第二连接走线L2和第三连接走线L3。其中，结合图30所示，第一初始化信号线V1与第六有源层图案S6的另一端电连接，第一初始化信号线V1被配置为向第六有源图层S6传输vinit1信号。第二初始化信号线V2与第七有源图层S7的一端电连接，第二初始化信号线V2被配置为向第七有源图层S7传 输vinit2信号。
可以知道的是，第六有源图层S6的另一端即为像素驱动电路的第二电压端，第七有源图层S7的一端为像素驱动电路的第五电压端。也就是说，第一初始化信号线V1经过第六有源图层S6的另一端(第二电压端)向像素驱动电路传输vinit1信号，第二初始化信号线V2经过第七有源图层S7的另一端(第五电压端)向像素驱动电路传输vinit2信号。
第一连接走线L1一端与第一有源图层S1的一端和第五有源图层S5的另一端电连接，第一连接走线L1另一端与第六有源图层S6的一端电连接，具体地，第一连接走线L1一端过孔至第一有源层1211与第一有源图层S1的一端电连接，且第一连接走线L1一端还过孔至第二有源层1214与第五有源图层S5的另一端电连接；第一连接走线L1另一端过孔至第一有源层1211与第六有源图层S6的一端电连接，实现位于第一有源层1211的第一有源图层S1、第六有源图层S6，与位于第二有源层的第五有源图层S5电连接。
第二连接走线L2一端与第一极板Cst1电连接，另一端与第五有源图层S5的一端电连接。第三连接走线L3与第二极板Cst2和第二有源图层S2的一端电连接，第三连接走线L3被配置为，将电压vdd提供给第二极板和第二有源图层S2。
第一源漏金属层1216还设置有两个连接端：第一连接端D1和第二连接端D2，其中，第一连接端D1过孔至第一有源层1211，与第四有源图层S4的一端电连接；第二连接端D2过孔至第一有源层1211，与第三有源图层S3和第七有源图层S7的连接位置处电连接。
如图29和图31所示，第二源漏金属层1217设置有第一电压信号线Vd和数据信号线Data，第一电压信号线Vd过孔至第一源漏金属层1216，与第三连接走线L3电连接，数据信号线Data过孔至第一源漏金属层1216，与第一连接端D1电连接。
可以知道是，第二有源图层S2的一端即为像素驱动电路的第一电压端，第四晶体管有源层图案S7的一端为像素驱动电路的数据信号端。也就是说，第一电压信号线V经过第二有源图层S2的一端(第一电压端)向像素驱动电路传输电压vdd，数据信号线Data经过第四晶体管有源层图案S7的一端(数据信号端)向像素驱动电路传输电压vdata。
在一些实施例中，多个像素驱动电路呈阵列布置，在沿栅信号线延伸方向(第二方向)排列的多个像素驱动电路中，每个像素驱动电路所在区域包括沿沿垂直栅信号线延伸的方向(第一方向)布置的第一栅信号线和第二栅信号线，第一栅信号线传输数据信号，第二栅信号线传输第一复位信号。其中，在沿栅信号线延伸方向排列的一列像素驱动电路中，位于本级像素驱动电路所在区域的第一栅信号线，与位于上一级像素驱动电路所在区域的第二栅信号线电连接，即在上一级像素驱动电路接收的数据信号，也是本级像素驱动电路接收的第一复位信号，具体地，上一级像素驱动电路的第四晶体管的栅极驱动信号，也是本级像素驱动电路的第一晶体管的栅极驱动信号。
在一些实施例中，为实现在一列像素驱动电路中，第一复位信号的脉宽可调，即相对 第一栅信号线传输的电信号，第二栅信号线传输的电信号的脉宽可调。
基于此，本实施例提供另一种阵列基板，另一种阵列基板包括上述任一项实施例中提供的像素驱动电路，像素驱动电路包括数据写入子电路和第一复位子电路，数据写入子电路包括第四晶体管，第一复位子电路包括第六晶体管。
其中，另一种阵列基板包括：衬底和驱动电路层，驱动电路层的位置和各膜层的结构与上述一致阵列基板一致，在此不做赘述，其中，如图31所示，另一种阵列基板的第一栅信号线R1与第二栅信号线R2绝缘。
第一栅信号线R1与第二栅信号线R2绝缘，可以使第一栅信号线R1和第二栅信号线R2传输两种不同的电信号，也就是说，在第一栅信号线R1传输的电压vdata的脉宽固定的情况下，第二栅信号线R2传输的第一复位信号的脉宽可调，如此，实现像素驱动电路在初始化阶段的时间能够独立控制，从而能够实现初始化和数据写入阶段的时间平衡，达到良好的发光效果。
在一些实施例中，如图32所示，像素驱动电路还包括第三复位子电路，第三复位子电路包括第十晶体管，第一像素有源图案还包括第十晶体管的第十有源图层S10。其中，第一有源图层S1、第二有源图层S2以及第十有源图层S10均连接于第一连接点G。
在一些实施例中，如图32所示，第一连接点G设置于第一有源层，第一有源图层S1和第二有源图层S2连接于第一连接点G。
在一些实施例中，如图34和图35所示，第一栅极层1212还包括多条第三栅信号线和多条第四栅信号线，在该实施例中，第二栅信号线R2不经过第七有源图层S7，仅经过第六有源图层S6。第四栅信号线R4经过第七有源图层S7和第十有源图层S10。具体地，第四栅信号线R4在衬底的正投影与第十有源图层S10在衬底的正投影有重叠。
第十有源图层S10与经过的第四栅信号线R4形成第十晶体管，且第一有源图层S1、第二有源图层S2以及第十有源图层S10均连接于第一连接点。在像素驱动电路初始化时，第十晶体管向第一连接点传输电信号，可以实现对第一晶体管的第一极的初始化，避免第一晶体管的第一极处电压受上一帧电压vdata的影响，使本帧亮度不受上一帧状态的影响，改善短期残像问题。
在一些实施例中，如图37所示，另一种阵列基板的第三栅极层1215设置于第一栅极层远离衬底一侧，第三栅极层还包括第三初始化信号线V3，第三初始化信号线V3与第十有源图层电连接。
示例性地，第三初始化信号线V3传输vinit3信号至第十有源图层，在初始化阶段，vinit3信号使第一连接点处的电压保持一致，如此实现下一帧图像不受上一帧图像的影响。
在一些实施例中，如图36所示，另一种阵列基板的第二栅极层1214设置于第一栅极层和第三栅极层之间。第二栅极层1214还包括多条第一初始化信号线V1，多条第一初始 化信号线中的一条与第六晶体管有源图层电连接。
在一些实施例中，在阵列基板中，在像素区域内，阵列基板包括的多个膜层中的同层图案实质上镜像对称。其中，像素驱动电路还包括存储子电路，第二栅极层包括存储子电路的电容的第二极板Cst2；位于同一像素区域内两个第二极板Cst2相连接。
示例性地，在像素区域内，两个像素驱动电路相对设置，即相邻的两个像素驱动电路关于一条中间线H对称，该结构可以减少沿第二方向Y布置的走线数量，降低工艺难度，提高效率。
其中，镜像对称的两个第二极板Cst2相连接可以减少第一电压信号线与第二极板Cst2电连接的过孔数量，如此降低生产工艺难度，提高生产效率。
在一些实施例中，如图33和图38所示，另一种阵列基板的第一源漏金属层1216设置于第三栅极层远离衬底一侧，在该阵列基板中，第一源漏金属层1216包括多条第二初始化信号线V2，且相邻的第二初始化信号线V2之间电连接，具体地，相邻的两条第二初始化信号线V2之间设置有连接走线L7，使所有第二初始化信号线V2的电压相同。其中，多条第二初始化信号线V2中的一条与第七有源图层S7电连接。
在一些实施例中，如图33所示，第一源漏金属层1216还包括第四连接走线L4，第四连接走线L4的一端通过贯穿至第一有源层1211的第一过孔与第十有源图层S10电连接，第四连接走线L4的另一端通过贯穿至第一有源层1211的第二过孔与第一连接点G电连接。
在一些实施例中，第六有源图层与一条第一初始化信号线电连接。如图33所示，第一源漏金属层1216还包括第五连接走线L5，第五连接走线L5的一端通过贯穿至第三栅极层的第三过孔与第三初始化信号线电连接，第五连接走线L5的另一端通过贯穿至至第一有源层1211的第四过孔与第十有源图层S10电连接。
在一些实施例中，如图33所示，第一源漏金属层1216还包括第六连接走线L6，第六连接走线L6的两端分别通过贯穿至至第二栅极层的两个第五过孔与第一初始化信号线电连接，第六连接走线L6的中部通过贯穿至第一有源层的第六过孔与第一有源图层电连接。
在一些实施例中，如图39所示，阵列基板还包括第二源漏金属层1217，第二源漏金属层1217设置于第一源漏金属层1216远离衬底一侧，第二源漏金属层1217包括第一电压信号线Vd。
第一源漏金属层1216还包括多个第三连接走线L3，每个第三连接走线L3的一端通过贯穿至第二栅极层的第七过孔与第二极板电连接，每个第三连接走线L3的通过贯穿至第一有源图层的第八过孔与第二有源图层电连连接，第一电压信号线通过贯穿至第二源漏金属层的第九过孔与第三连接走线L3电连接。
本公开实施例提供一种显示装置，包括阵列排布的多个子像素，其中，每个子像素包 括发光元件和如上述任一实施例的像素驱动电路31。
或者，本公开实施例提供一种显示装置，包括如上述任一项实施例提供的阵列基板，设置于阵列基板上的发光器件层以及设置于发光器件层远离阵列基板一侧的封装层。
在一些实施例中，位于第i行的多个子像素的像素驱动电路的第三信号控制端S3与位于第i-1行的多个子像素的像素驱动电路的第一信号控制端S1连接至同一条信号线，其中，i为大于1的正整数，且i小于等于多个子像素的总行数。
本公开的一些实施例提供一种像素驱动电路的驱动方法，用于如图6、图8、图10、图12所示的像素驱动电路31。该像素驱动电路31在一个显示帧中的工作流程包括补偿控制阶段、数据写入阶段和发光阶段。如图40所示，该驱动方法包括以下步骤2101～步骤2103。
步骤2101、控制第一复位信号控制端的信号的电平为第一电平，控制补偿信号控制端的信号的电平为第二电平，控制第一信号控制端的信号的电平为第二电平，控制第一发光信号控制端的信号的电平为第一电平，控制第二发光信号控制端的信号的电平为第二电平。
在一些实施例中，第一复位信号控制端的信号的脉宽可调。例如，第一复位信号控制端的信号为Reset[n]。
在一些实施例中，上述第一电平为低电平，第二电平为高电平。
步骤2102、控制第一复位信号控制端的信号的电平为第二电平，控制补偿信号控制端的信号的电平为第二电平，控制第一信号控制端的信号的电平为第一电平，控制第一发光信号控制端的信号的电平为第二电平，控制第二发光信号控制端的信号的电平为第二电平。
步骤2103、控制补偿信号控制端的信号的电平为第一电平，控制第一复位信号控制端的信号的电平为第二电平，控制第一信号控制端的信号的电平为第二电平，控制第一发光信号控制端的信号的电平为第一电平，控制第二发光信号控制端的信号的电平为第一电平。
本公开的一些实施例提供另一种像素驱动电路的驱动方法，用于如图13、图15、图17、图18所示的像素驱动电路31。该像素驱动电路31在一个显示帧中的工作流程包括补偿控制阶段、数据写入阶段和发光阶段。如图41所示，该驱动方法包括以下步骤2201～步骤2203。
步骤2201、控制第一复位信号控制端的信号的电平为第一电平，控制补偿信号控制端的信号的电平为第二电平，控制第一信号控制端的信号的电平为第二电平；第一复位信号控制端的信号的脉宽可调；控制第一发光信号控制端和第二发光信号控制端的信号的电平为第二电平，控制第二信号控制端的信号为第一电平。
步骤2202、控制第一复位信号控制端的信号的电平为第二电平，控制补偿信号控制端的信号的电平为第二电平，控制第一信号控制端的信号的电平为第一电平，控制第一发光信号控制端和第二发光信号控制端的信号的电平为第二电平，控制第二信号控制端的信号 为第二电平。
步骤2203、控制补偿信号控制端的信号的电平为第一电平，控制第一复位信号控制端的信号的电平为第二电平，控制第一信号控制端的信号的电平为第二电平，控制第一发光信号控制端和第二发光信号控制端的信号的电平为第一电平，控制第二信号控制端的信号为第二电平。
在一些实施例中，当像素驱动电路31为图8或图15所示的像素驱动电路31时，上述驱动方法还包括：在初始化阶段，控制第三发光信号控制端的信号的电平为第二电平；在数据写入阶段，控制第三发光信号控制端的信号的电平为第一电平或第二电平；在发光阶段，控制第三发光信号控制端的信号的电平为第一电平。
在一些实施例中，当像素驱动电路31为图12或图18所示的像素驱动电路31时，上述方法还包括：在初始化阶段，控制第二复位信号控制端的信号的电平为第一电平；在数据写入阶段，控制第二复位信号控制端的信号的电平为第二电平；在发光阶段，控制第二复位信号控制端的信号的电平为第二电平。
在一些实施例中，当像素驱动电路31包括第四复位子电路318时，上述方法还包括：在初始化阶段，控制第三信号控制端的信号的电平为第一电平；在数据写入阶段，控制第三信号控制端的信号的电平为第二电平；在发光阶段，控制第三信号控制端的信号的电平为第二电平。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (26)

  1. 一种像素驱动电路，包括：驱动子电路、第一发光控制子电路、第二发光控制子电路、数据写入子电路、补偿子电路和第一复位子电路；其中，
    所述驱动子电路包括控制端、第一端和第二端；在所述像素驱动电路的一个显示帧中的初始化阶段，所述驱动子电路的控制端和所述驱动子电路的第一端之间的电压差值固定；
    所述第一发光控制子电路耦接至第一电压端和所述驱动子电路的第一端，且被配置为响应于第一发光信号控制端的信号，驱动发光元件发光；
    所述第二发光控制子电路耦接至所述驱动子电路的第二端和所述发光元件的第一电极，且被配置为响应于第二发光信号控制端的信号，驱动所述发光元件发光；
    所述数据写入子电路耦接至数据信号端和所述驱动子电路的第一端，且被配置为响应于第一信号控制端的信号，将所述数据信号端的数据信号写入所述驱动子电路的第一端；
    所述补偿子电路耦接至所述驱动子电路的第二端和所述驱动子电路的控制端，且被配置为响应于补偿信号控制端的信号，对所述驱动子电路进行阈值补偿；
    所述第一复位子电路耦接在第二电压端和所述驱动子电路的控制端之间，且被配置为响应于第一复位信号控制端的信号，将所述第二电压端的信号写入所述驱动子电路的控制端，对所述驱动子电路的控制端进行复位；所述第一复位信号控制端的信号的脉宽可调。
  2. 根据权利要求1所述的像素驱动电路，其中，所述第一复位子电路的第一端通过所述补偿子电路耦接至所述驱动子电路的控制端，所述第一复位子电路的第二端耦接至所述第二电压端。
  3. 根据权利要求2所述的像素驱动电路，其中，所述像素驱动电路还包括第三发光控制子电路，所述第三发光控制子电路耦接至所述驱动子电路的第二端和所述第一复位子电路的第一端；
    所述第三发光控制子电路，被配置为响应于第三发光信号控制端的信号，在所述初始化阶段将所述驱动子电路的控制端和所述驱动子电路的第一端进行同步初始化，并在所述发光阶段驱动所述发光元件发光。
  4. 根据权利要求1所述的像素驱动电路，其中，所述第一复位子电路的第一端耦接至所述驱动子电路的控制端，所述第一复位子电路的第二端耦接至所述第二电压端。
  5. 根据权利要求4所述的像素驱动电路，其中，所述像素驱动电路还包括第二复位子电路，所述第二复位子电路耦接至第三电压端和所述驱动子电路的第二端；
    所述第二复位子电路，被配置为响应于第二复位信号控制端的信号，将所述第三电压端的信号写入所述驱动子电路的第二端，对所述驱动子电路的第二端进行复位。
  6. 根据权利要求2-5中任一项所述的像素驱动电路，其中，所述第一发光信号控制端和所述第二发光信号控制端连接不同的信号线，所述第一发光控制子电路还被配置为在所述初始化阶段将所述第一电压端的信号写入所述驱动子电路的第一端。
  7. 根据权利要求2-5中任一项所述的像素驱动电路，其中，所述第一发光信号控制端和所述第二发光信号控制端连接同一条信号线，所述像素驱动电路还包括第三复位子电路，所述第三复位子电路耦接至第四电压端和所述驱动子电路的第一端，且被配置为响应于第二信号控制端的信号，将所述第四电压端的信号写入所述驱动子电路的第一端，对所述驱动子电路的第一端进行复位；所述第四电压端的信号电压高于所述第一电压端的信号电压。
  8. 一种像素驱动电路，包括：驱动子电路、第一发光控制子电路、第二发光控制子电路、数据写入子电路、补偿子电路和第一复位子电路；其中，
    所述驱动子电路包括控制端、第一端和第二端；
    所述第一发光控制子电路耦接至第一电压端和所述驱动子电路的第一端，且被配置为响应于第一发光信号控制端的信号，驱动发光元件发光；
    所述第二发光控制子电路耦接至所述驱动子电路的第二端和所述发光元件的第一电极，且被配置为响应于第二发光信号控制端的信号，驱动所述发光元件发光；
    所述数据写入子电路耦接至数据信号端和所述驱动子电路的第一端，且被配置为响应于第一信号控制端的信号，将所述数据信号端的数据信号写入所述驱动子电路的第一端；
    所述补偿子电路耦接至所述驱动子电路的第二端和所述驱动子电路的控制端，且被配置为响应于补偿信号控制端的信号，对所述驱动子电路进行阈值补偿；
    所述第一复位子电路耦接至所述补偿子电路和第二电压端，且被配置为响应于第一复位信号控制端的信号，将所述第二电压端的信号写入所述驱动子电路的控制端，对所述驱动子电路的控制端进行复位；所述第一复位信号控制端的信号的脉宽可调。
  9. 根据权利要求1或8所述的像素驱动电路，其中，所述像素驱动电路还包括第四复位子电路，所述第四复位子电路耦接至第五电压端和所述发光元件的第一电极，且被配置为响应于第三信号控制端的信号，将所述第五电压端的信号写入所述发光元件的第一电极，对所述发光元件的第一电极进行复位。
  10. 根据权利要求9所述的像素驱动电路，其中，所述像素驱动电路还包括存储子电路，所述存储子电路耦接至所述驱动子电路的控制端和所述第一电压端，且被配置为存储基于所述数据信号得到的补偿信号。
  11. 一种阵列基板，包括：多个如权利要求1-10中任一项所述的像素驱动电路，其中，每个像素驱动电路包括数据写入子电路和第一复位子电路，所述数据写入子电路包括第四晶体管，所述第一复位子电路包括第六晶体管；
    所述阵列基板包括：
    衬底；
    设置于所述衬底一侧的第一有源层，所述第一有源层包括多个第一像素有源图案，每个第一像素有源图案包括所述第四晶体管的第四有源图层、所述第六晶体管的第六有源图 层；
    设置于所述第一有源层远离所述衬底一侧的第一栅极层，所述第一栅极层包括多条第一栅信号线和多条第二栅信号线；
    第四有源图层在所述衬底上的正投影与所述多条第一栅信号线中的当前级第一栅信号线在所述衬底的正投影有重叠，所述第六有源图层在所述衬底上的正投影与所述多条第二栅信号线中的当前级第二栅信号线在所述衬底上的正投影与有重叠，其中，相对所述第一栅信号线传输的电信号，所述第二栅信号线传输的电信号的脉宽可调。
  12. 根据权利要求11所述的阵列基板，其中，包括：所述像素驱动电路还包括驱动子电路、第一发光控制子电路、第二发光控制子电路和第三复位子电路，所述驱动子电路包括第一晶体管，所述第一发光控制子电路包括第二晶体管，所述第二发光控制子电路包括第三晶体管，所述第三复位子电路包括第十晶体管；
    所述第一像素有源图案还包括所述第一晶体管的第一有源图层、所述第二晶体管的第二有源图层、所述第三晶体管的第三有源图层和所述第十晶体管的第十有源图层，所述第一有源图层、所述第二有源图层以及所述第十有源图层均连接于第一连接点；
    所述第一栅极层还包括多条第三栅信号线和多条第四栅信号线，所述第三有源图层在衬底上的正投影和所述第二有源图层在衬底上的正投影，与所述多条第三栅信号线中的当前级第三栅信号线在所述衬底上的正投影有重叠；所述第十有源图层在所述衬底上的正投影与所述多条第四栅信号线中的当前级第四栅信号线在所述衬底上的正投影与有重叠。
  13. 根据权利要求12所述的阵列基板，其中，所述阵列基板还包括第三栅极层，所述第三栅极层设置于所述第一栅极层远离所述衬底一侧，所述第三栅极层还包括多条第三初始化信号线，所述多条第三初始化信号线中的一条与所述第十有源图层电连接。
  14. 根据权利要求13所述的阵列基板，其中，所述阵列基板还包括第二栅极层，所述第二栅极层设置于所述第一栅极层和所述第三栅极层之间，所述第二栅极层还包括多条第一初始化信号线，所述多条第一初始化信号线中的一条与所述第六有源图层电连接。
  15. 根据权利要求14所述的阵列基板，其中，所述阵列基板包括阵列布置的多个像素区域，每个像素区域设置有相邻两个像素驱动电路；在所述像素区域内，所述阵列基板包括的多个膜层中的同层图案实质上镜像对称；
    所述像素驱动电路还包括存储子电路，所述第二栅极层包括所述存储子电路的电容的第二极板；
    其中，位于同一像素区域内的两个所述第二极板相连接。
  16. 根据权利要求13-15任一项所述的阵列基板，其中，所述像素驱动电路包括第四复位子电路，所述第一有源层还包括所述第四复位子电路的第七有源图层；
    所述阵列基板还包括第一源漏金属层，所述第一源漏金属层设置于所述第三栅极层远 离所述衬底一侧，所述第一源漏金属层包括多条第二初始化信号线，且相邻的第二初始化信号线之间电连接，所述多条第二初始化信号线中的一条与所述第七有源图层电连接。
  17. 根据权利要求16所述的阵列基板，其中，所述第一连接点设置于所述第一有源层，所述第一有源图层和所述第二有源图层连接于所述第一连接点；
    所述第一源漏金属层还包括第四连接走线，所述第四连接走线的一端通过贯穿至所述第一有源层的第一过孔与所述第十有源图层电连接，所述第四连接走线的另一端通过贯穿至所述第一有源层的第二过孔与所述第一连接点电连接。
  18. 根据权利要求16所述的阵列基板，其中，所述第六有源图层与一条第一初始化信号线电连接；
    所述第一源漏金属层还包括第五连接走线，所述第五连接走线的一端通过贯穿至第三栅极层的第三过孔与所述第三初始化信号线电连接，所述第五连接走线的另一端通过贯穿至至所述第一有源层的第四过孔与所述第十有源图层电连接。
  19. 根据权利要求18所述的阵列基板，其中，所述第一源漏金属层还包括第六连接走线，所述第六连接走线的两端分别通过贯穿至至所述第二栅极层的两个第五过孔与所述第一初始化信号线电连接，所述第六连接走线的中部通过贯穿至所述第一有源层的第六过孔与所述第一有源图层电连接。
  20. 根据权利要求18所述的阵列基板，其中，所述阵列基板还包括第二源漏金属层，所述第二源漏金属层设置于所述第一源漏金属层远离所述衬底一侧，所述第二源漏金属层包括第一电压信号线；
    所述第一源漏金属层还包括多个第三连接走线，每个第三连接走线的一端通过贯穿至所述第二栅极层的第七过孔与所述第二极板电连接，所述每个第三连接走线的通过贯穿至第一有源图层的第八过孔与所述第二有源图层电连连接，所述第一电压信号线通过贯穿至所述第二源漏金属层的第九过孔与所述第三连接走线电连接。
  21. 一种显示装置，包括多个子像素，每个子像素包括如权利要求1-10中任一项所述的像素驱动电路和所述发光元件；
    或者，所述显示装置包括如权利要求11-20中任一项所述的阵列基板、设置于所述阵列基板上的发光器件层以及设置于所述发光器件层远离所述阵列基板一侧的封装层。
  22. 一种像素驱动电路的驱动方法，用于驱动如权利要求1-10中任一所述的像素驱动电路，其中，所述像素驱动电路在一个显示帧中的工作过程包括初始化阶段、数据写入阶段和发光阶段，
    所述驱动方法包括：
    在所述初始化阶段，控制所述第一复位信号控制端的信号的电平为第一电平，控制所述补偿信号控制端的信号的电平为第二电平，控制所述第一信号控制端的信号的电平为第 二电平；所述第一复位信号控制端的信号的脉宽可调；
    在所述数据写入阶段，控制所述第一复位信号控制端的信号的电平为第二电平，控制所述补偿信号控制端的信号的电平为第二电平，控制所述第一信号控制端的信号的电平为第一电平；
    在所述发光阶段，控制所述第一复位信号控制端的信号的电平为第二电平，控制所述补偿信号控制端的信号的电平为第一电平，控制所述第一信号控制端的信号的电平为第二电平。
  23. 根据权利要求22所述的方法，其中，所述方法还包括：
    在所述初始化阶段，控制所述第一发光信号控制端的信号的电平为第一电平，控制所述第二发光信号控制端的信号的电平为第二电平；
    在所述数据写入阶段，控制所述第一发光信号控制端的信号的电平为第二电平，控制所述第二发光信号控制端的信号的电平为第二电平；
    在所述发光阶段，控制所述第一发光信号控制端的信号的电平为第一电平，控制所述第二发光信号控制端的信号的电平为第一电平。
  24. 根据权利要求22所述的方法，其中，所述像素驱动电路还包括第三复位子电路，所述第三复位子电路耦接至第四电压端和所述驱动子电路的第一端，且所述第三复位子电路的控制端被配置为接收第二信号控制端的信号；所述第四电压端的信号电压高于所述第一电压端的信号电压；所述方法还包括：
    在所述初始化阶段，控制所述第一发光信号控制端和所述第二发光信号控制端的信号的电平为第二电平，控制所述第二信号控制端的信号为第一电平；
    在所述数据写入阶段，控制所述第一发光信号控制端和所述第二发光信号控制端的信号的电平为第二电平，控制所述第二信号控制端的信号为第二电平；
    在所述发光阶段，控制所述第一发光信号控制端和所述第二发光信号控制端的信号的电平为第一电平，控制所述第二信号控制端的信号为第二电平。
  25. 根据权利要求22-24中任一项所述的方法，其中，所述第一复位子电路的第一端通过所述补偿子电路耦接至所述驱动子电路的控制端，所述第一复位子电路的第二端耦接至所述第二电压端；所述像素驱动电路还包括第三发光控制子电路，所述第三发光控制子电路耦接至所述驱动子电路的第二端和所述第一复位子电路的第一端，所述第三发光控制子电路控制端被配置为接收第三发光信号控制端的信号；所述方法还包括：
    在所述初始化阶段，控制所述第三发光信号控制端的信号的电平为第二电平；
    在所述数据写入阶段，控制所述第三发光信号控制端的信号的电平为第一电平或第二电平；
    在所述发光阶段，控制所述第三发光信号控制端的信号的电平为第一电平。
  26. 根据权利要求22-24中任一项所述的方法，其中，所述第一复位子电路的第一端耦接至所述驱动子电路的控制端，所述第一复位子电路的第二端耦接至所述第二电压端；所述像素驱动电路还包括第二复位子电路，所述第二复位子电路耦接至第三电压端和所述驱动子电路的第二端，所述第二复位子电路的控制端被配置为接收第二复位信号控制端的信号；所述方法还包括：
    在所述初始化阶段，控制所述第二复位信号控制端的信号的电平为第一电平；
    在所述数据写入阶段，控制所述第二复位信号控制端的信号的电平为第二电平；
    在所述发光阶段，控制所述第二复位信号控制端的信号的电平为第二电平。
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