WO2023226303A1 - 发光芯片外延结构及其制作方法、发光芯片以及显示面板 - Google Patents

发光芯片外延结构及其制作方法、发光芯片以及显示面板 Download PDF

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Publication number
WO2023226303A1
WO2023226303A1 PCT/CN2022/128694 CN2022128694W WO2023226303A1 WO 2023226303 A1 WO2023226303 A1 WO 2023226303A1 CN 2022128694 W CN2022128694 W CN 2022128694W WO 2023226303 A1 WO2023226303 A1 WO 2023226303A1
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layer
gradient
doping concentration
light
ohmic contact
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PCT/CN2022/128694
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English (en)
French (fr)
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孙威威
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重庆康佳光电技术研究院有限公司
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Publication of WO2023226303A1 publication Critical patent/WO2023226303A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table

Definitions

  • the present application relates to the field of display technology, and in particular to a light-emitting chip epitaxial structure, a method for manufacturing a light-emitting chip epitaxial structure, a light-emitting chip having the light-emitting chip epitaxial structure, and a display panel having the light-emitting chip.
  • Mini LED sub-millimeter light emitting diode
  • Micro LED micro light emitting diode
  • Mini LED chips and Micro The LED chip has a small size and a thin epitaxial layer, so it requires a lower operating voltage. Low operating voltage can also reduce power consumption during operation.
  • reducing the operating voltage of LED chips mainly involves increasing the doping concentration of each doped layer or reducing the thickness of the undoped layer.
  • excessive doping will lead to doping saturation, which will not increase the concentration of electrons or holes in the doped layer, but will instead deteriorate the crystal quality or morphology of the source material;
  • Thinning the thickness of the non-doped layer can reduce the voltage, but this will affect the photoelectric performance and aging characteristics of the LED chip. Therefore, how to reduce the series resistance of the LED chip to reduce the operating voltage without affecting the optical performance and quality of the LED chip is an urgent problem to be solved.
  • the purpose of this application is to provide a light-emitting chip epitaxial structure, a method for manufacturing a light-emitting chip epitaxial structure, a light-emitting chip with the light-emitting chip epitaxial structure, and a light-emitting chip with the light-emitting chip epitaxial structure.
  • the display panel is designed to reduce the series resistance of the light-emitting chip without affecting the optical performance and quality of the light-emitting chip to reduce its operating voltage.
  • a light-emitting chip epitaxial structure includes a first semiconductor component, a light-emitting layer and a second semiconductor component that are stacked in sequence.
  • the first semiconductor component includes a buffer layer, a first graded layer, a corrosion stop layer, a second graded layer, an ohmic contact layer, a third graded layer, a current spreading layer, a first limiting layer and a first layer that are stacked in sequence. waveguide layer.
  • the first gradient layer makes the doping concentration of the buffer layer and the doping concentration of the corrosion stop layer continuous
  • the second gradient layer makes the doping concentration of the corrosion stop layer and the ohmic contact layer continuous.
  • the doping concentration is continuous
  • the third gradient layer makes the doping concentration of the ohmic contact layer and the doping concentration of the current spreading layer continuous.
  • the above-mentioned epitaxial structure of the light-emitting chip includes a first semiconductor component, a light-emitting layer and a second semiconductor component that are stacked in sequence.
  • the first semiconductor component includes a buffer layer, a first graded layer, a corrosion stop layer, a second graded layer, an ohmic contact layer, a third graded layer, a current spreading layer, a first limiting layer and a first layer that are stacked in sequence. waveguide layer.
  • the first gradient layer makes the doping concentration of the buffer layer and the doping concentration of the corrosion stop layer continuous
  • the second gradient layer makes the doping concentration of the corrosion stop layer and the ohmic contact layer continuous.
  • the doping concentration is continuous, and the third gradient layer makes the doping concentration of the ohmic contact layer and the doping concentration of the current spreading layer continuous. Therefore, the first gradient layer, the second gradient layer and the third gradient layer make the doping between the doped layers of the first semiconductor component more continuous, reducing the interference between the doped layers.
  • the series resistor further reduces the operating voltage of the epitaxial structure of the light-emitting chip and also reduces the power consumption of the epitaxial structure of the light-emitting chip.
  • the gradient mode of the doping concentration of the first gradient layer includes any one or more combinations of linear changes, nonlinear changes and step changes
  • the gradient of the doping concentration of the second gradient layer is The method includes any one or more combinations of linear change, nonlinear change or step change.
  • the gradient method of the doping concentration of the third gradient layer includes any one of linear change, nonlinear change or step change. one or more combinations.
  • the doping concentration of the first gradient layer gradually increases in a direction from the buffer layer to the corrosion stop layer, and the doping concentration of the second gradient layer points from the corrosion stop layer to the corrosion stop layer.
  • the direction of the ohmic contact layer gradually increases, and the doping concentration of the third gradient layer gradually decreases in the direction from the ohmic contact layer to the current spreading layer.
  • the first gradient layer is a silicon arsenide and silicon layer
  • the second gradient layer is a silicon phosphide layer and silicon
  • the third gradient layer is a silicon arsenide and silicon layer.
  • the buffer layer is a gallium arsenide layer, the thickness of the buffer layer is 100nm to 300nm, the corrosion cutoff layer is a Ga x1 In 1-x1 P layer, the thickness of the corrosion cutoff layer is 50nm to 300nm.
  • the ohmic contact layer is a gallium arsenide layer, the thickness of the ohmic contact layer is 10nm to 150nm, the current expansion layer is an Al x2 Ga 1-x2 InP layer, the thickness of the current expansion layer is 1000nm to 150nm.
  • the first confinement layer is an Al x3 In 1-x3 P layer
  • the thickness of the first confinement layer is 250 nm to 450 nm
  • the first waveguide layer is an Al x4 Ga 1-x4 InP layer
  • the The thickness of a waveguide layer is 70nm to 150nm, where x1, x2, x3 and x4 are all greater than 0 and less than 1.
  • the light-emitting layer is a quantum well layer
  • the second semiconductor component includes a second waveguide layer, a second confinement layer, a transition layer, and a second waveguide layer, a second confinement layer, and a transition layer which are stacked in sequence on a side of the light-emitting layer facing away from the first waveguide layer. layer and window layer.
  • the present application provides a light-emitting chip.
  • the light-emitting chip includes a first chip electrode, a second chip electrode and the above-mentioned light-emitting chip epitaxial structure.
  • the first chip electrode and the third of the light-emitting chip epitaxial structure A semiconductor component is electrically connected, and the second chip electrode is electrically connected to the second semiconductor component of the epitaxial structure of the light-emitting chip.
  • the above-mentioned light-emitting chip includes a first chip electrode, a second chip electrode, and a light-emitting chip epitaxial structure.
  • the light-emitting chip epitaxial structure includes a first semiconductor component, a light-emitting layer, and a second semiconductor component that are stacked in sequence.
  • the first semiconductor component includes a buffer layer, a first graded layer, a corrosion stop layer, a second graded layer, an ohmic contact layer, a third graded layer, a current spreading layer, a first limiting layer and a first layer that are stacked in sequence. waveguide layer.
  • the first gradient layer makes the doping concentration of the buffer layer and the doping concentration of the corrosion stop layer continuous
  • the second gradient layer makes the doping concentration of the corrosion stop layer and the ohmic contact layer continuous.
  • the doping concentration is continuous
  • the third gradient layer makes the doping concentration of the ohmic contact layer and the doping concentration of the current spreading layer continuous. Therefore, the first gradient layer, the second gradient layer and the third gradient layer make the doping between the doped layers of the first semiconductor component more continuous, reducing the interference between the doped layers.
  • the series resistor further reduces the operating voltage of the epitaxial structure of the light-emitting chip and also reduces the power consumption of the epitaxial structure of the light-emitting chip.
  • the present application also provides a display panel.
  • the display panel includes a driving substrate and a plurality of the above-mentioned light-emitting chips.
  • the plurality of light-emitting chips are disposed on the driving substrate and interact with the driving substrate.
  • the substrates are electrically connected, and the driving substrate is used to transmit electrical signals to a plurality of the light-emitting chips to control the plurality of the light-emitting chips to emit light.
  • the above-mentioned display panel includes a driving substrate and a plurality of light-emitting chips.
  • the light-emitting chip includes a first chip electrode, a second chip electrode, and a light-emitting chip epitaxial structure.
  • the light-emitting chip epitaxial structure includes a first semiconductor component, a light-emitting layer, and a light-emitting layer. second semiconductor component.
  • the first semiconductor component includes a buffer layer, a first graded layer, a corrosion stop layer, a second graded layer, an ohmic contact layer, a third graded layer, a current spreading layer, a first limiting layer and a first layer that are stacked in sequence. waveguide layer.
  • the first gradient layer makes the doping concentration of the buffer layer and the doping concentration of the corrosion stop layer continuous
  • the second gradient layer makes the doping concentration of the corrosion stop layer and the ohmic contact layer continuous.
  • the doping concentration is continuous
  • the third gradient layer makes the doping concentration of the ohmic contact layer and the doping concentration of the current spreading layer continuous. Therefore, the first gradient layer, the second gradient layer and the third gradient layer make the doping between the doped layers of the first semiconductor component more continuous, reducing the interference between the doped layers.
  • the series resistor further reduces the operating voltage of the epitaxial structure of the light-emitting chip and also reduces the power consumption of the epitaxial structure of the light-emitting chip.
  • this application also provides a method for manufacturing the epitaxial structure of a light-emitting chip, which is used to manufacture the above-mentioned epitaxial structure of a light-emitting chip.
  • the manufacturing method includes:
  • a first semiconductor component is generated on the substrate, wherein the first semiconductor component includes a buffer layer, a first gradient layer, an etching stop layer, a second gradient layer, and an ohmic contact that are sequentially stacked on the substrate. layer, a third gradient layer, a current expansion layer, a first confinement layer and a first waveguide layer;
  • a second semiconductor component is formed on a surface of the light-emitting layer facing away from the first semiconductor component.
  • generating the first semiconductor component on the substrate includes:
  • the Group III source corresponding to the growth of the buffer layer is interrupted, and the Group V source corresponding to the growth of the buffer layer is maintained.
  • the doping source gradually changes from the doping concentration corresponding to the growth of the buffer layer to the doping concentration corresponding to the growth of the corrosion stop layer. impurity concentration to generate the first gradient layer on the surface of the buffer layer facing away from the substrate;
  • the Group III source corresponding to the growth of the corrosion cutoff layer is interrupted, and the Group V source corresponding to the growth of the corrosion cutoff layer is maintained.
  • the doping source gradually changes from the doping concentration corresponding to the growth of the corrosion cutoff layer to the growth of the ohmic contact. a doping concentration of the layer to generate the second graded layer on the surface of the corrosion stop layer facing away from the first graded layer;
  • the Group III source corresponding to the ohmic contact layer, the Group V source corresponding to the ohmic contact layer and the doping source are passed through to generate the ohmic layer on the surface of the second gradient layer facing away from the corrosion stop layer. contact layer;
  • the Group III source corresponding to the growth of the ohmic contact layer is interrupted, and the Group V source corresponding to the growth of the Ohmic contact layer is maintained.
  • the doping source gradually changes from the doping concentration corresponding to the growth of the Ohmic contact layer to the current expansion of the growth. a doping concentration of the layer to generate the third graded layer on the surface of the ohmic contact layer facing away from the second graded layer;
  • the current spreading layer is generated on the surface of the third gradient layer facing away from the ohmic contact layer;
  • the first confinement layer is generated on the surface of the current expansion layer facing away from the third gradient layer;
  • the first waveguide layer is formed on a surface of the first confinement layer facing away from the current spreading layer.
  • the above-mentioned manufacturing method includes: providing a substrate; generating a first semiconductor component on the substrate, wherein the first semiconductor component includes a buffer layer, a first gradient layer, and a buffer layer that are sequentially stacked on the substrate. Erosion stop layer, second gradient layer, ohmic contact layer, third gradient layer, current spreading layer, first confinement layer and first waveguide layer; forming luminescence on the surface of the first semiconductor component facing away from the substrate layer; generating a second semiconductor component on a surface of the light-emitting layer facing away from the first semiconductor component. Therefore, the first gradient layer, the second gradient layer and the third gradient layer make the doping between the doped layers of the first semiconductor component more continuous, reducing the interference between the doped layers.
  • the series resistor further reduces the operating voltage of the epitaxial structure of the light-emitting chip and also reduces the power consumption of the epitaxial structure of the light-emitting chip.
  • the first gradient layer makes the doping concentration of the buffer layer and the doping concentration of the corrosion stop layer continuous
  • the second gradient layer makes the doping concentration of the corrosion stop layer and the ohmic contact layer continuous.
  • the doping concentration is continuous
  • the third gradient layer makes the doping concentration of the ohmic contact layer and the doping concentration of the current spreading layer continuous. Therefore, the first gradient layer, the second gradient layer and the third gradient layer make the doping between the doped layers of the first semiconductor component more continuous, reducing the interference between the doped layers.
  • the series resistor further reduces the operating voltage of the epitaxial structure of the light-emitting chip and also reduces the power consumption of the epitaxial structure of the light-emitting chip.
  • Figure 1 is a schematic diagram of the layer structure of a light-emitting chip epitaxial structure disclosed in an embodiment of the present application
  • Figure 2 is a coordinate system diagram of the doping concentration-growth time curve disclosed in the embodiment of the present application.
  • Figure 3 is a schematic diagram of the layer structure of a light-emitting chip disclosed in the embodiment of the present application.
  • Figure 4 is a schematic diagram of the layer structure of a display panel disclosed in an embodiment of the present application.
  • Figure 5 is a schematic diagram of the layer structure of a display device disclosed in an embodiment of the present application.
  • Figure 6 is a schematic flow chart of a method for manufacturing a light-emitting chip epitaxial structure disclosed in an embodiment of the present application
  • FIG. 7 is a schematic flowchart of step S420 in a method for manufacturing an epitaxial structure of a light-emitting chip disclosed in an embodiment of the present application.
  • 100-Light-emitting chip epitaxial structure 10-substrate; 30-first semiconductor component; 31-buffer layer; 33-first gradient layer; 35-corrosion cutoff layer; 37-second gradient layer; 39-ohmic contact layer; 41-Third gradient layer; 43-Current expansion layer; 45-First confinement layer; 47-First waveguide layer; 50-Light-emitting layer; 70-Second semiconductor component; 71-Second waveguide layer; 73-Second Confinement layer; 75-transition layer; 77-window layer; 150-light-emitting chip; 101-first chip electrode; 103-second chip electrode; 200-driving substrate; 500-display panel; 700-glass cover plate; 1000- Display device; N1-first doping concentration; N2-second doping concentration; N3-third doping concentration; N4-fourth doping concentration; S410-S440-steps of the method for manufacturing a light-emitting chip epitaxial structure; S421- S429
  • Mini LED sub-millimeter light emitting diode
  • Micro LED micro light emitting diode
  • other LED chips have been widely used in the field of display screens due to their small size, high integration, thin thickness, and better brightness, resolution, and contrast.
  • Mini LED chips and Micro The LED chip has a small size and a thin epitaxial layer, so it requires a lower operating voltage. Low operating voltage can also reduce power consumption during operation.
  • the industry mainly reduces the operating voltage of LED chips by increasing the doping concentration of each doped layer or reducing the thickness of the undoped layer.
  • this application hopes to provide a solution that can solve the above technical problems, which can reduce the series resistance of the light-emitting chip to reduce its operating voltage without affecting the optical performance and quality of the light-emitting chip.
  • the details of which will be in This is explained in subsequent examples.
  • FIG. 1 is a schematic diagram of the layer structure of a light-emitting chip epitaxial structure disclosed in an embodiment of the present application.
  • the light-emitting chip epitaxial structure 100 provided by the embodiment of the present application may at least include a substrate 10, a first semiconductor component 30, a light-emitting layer 50 and a second semiconductor component 70 that are stacked in sequence. That is, the light-emitting layer 50 is located on the Between the first semiconductor component 30 and the second semiconductor component 70 , the substrate 10 is located on the side of the first semiconductor component 30 facing away from the light-emitting layer 50 .
  • the second semiconductor components 70 are respectively used to provide corresponding carriers to the light-emitting layer 50 , and the light-emitting layer 50 is used to receive carriers and emit light.
  • the first semiconductor component 30 includes a buffer layer 31 , a first gradient layer 33 , an corrosion stop layer 35 , and a second buffer layer 31 , which are stacked along the direction from the substrate 10 to the light-emitting layer 50 .
  • the first gradient layer 33 is used to make the doping concentration of the buffer layer 31 and the corrosion stop layer 35 continuous
  • the second gradient layer 37 is used to make the doping concentration of the corrosion stop layer 35 continuous.
  • the doping concentration of the ohmic contact layer 39 is continuous with that of the ohmic contact layer 39
  • the third gradient layer 41 is used to make the doping concentration of the ohmic contact layer 39 continuous with that of the current spreading layer 43 .
  • the doping concentration difference between the buffer layer 31 and the corrosion stop layer 35, the doping concentration difference between the corrosion stop layer 35 and the ohmic contact layer 39, and the ohmic contact affects the movement of carriers, making the series resistance of the light-emitting chip epitaxial structure 100 larger.
  • FIG. 2 is a coordinate system diagram of a doping concentration-growth time curve disclosed in an embodiment of the present application.
  • the doping concentration of the buffer layer 31 is defined as the first doping concentration N1
  • the doping concentration of the corrosion stop layer 35 is defined as the second doping concentration N2
  • the doping concentration of the ohmic contact layer 39 is defined as It is defined as the third doping concentration N3, and the doping concentration of the current spreading layer 43 is defined as the fourth doping concentration N4.
  • the second doping concentration N2 is greater than the first doping concentration N1
  • the third doping concentration N3 is greater than the second doping concentration N2
  • the fourth doping concentration N4 is less than the third doping concentration N1.
  • the doping concentration of the first gradient layer 33 gradually increases from the buffer layer 31 to the corrosion stop layer 35
  • the doping concentration of the second gradient layer 37 increases from the corrosion stop layer 31 to the corrosion stop layer 35
  • the layer 35 gradually increases in the direction toward the ohmic contact layer 39
  • the doping concentration of the third gradient layer 41 gradually decreases in the direction from the ohmic contact layer 39 toward the current spreading layer 43 .
  • the ohmic contact layer 39 needs to form ohmic contact with the first chip electrode. Therefore, the doping concentration of the ohmic contact layer 39 is the highest, that is, the third doping concentration N3 is the largest.
  • the first doping concentration N1, the second doping concentration N2, the third doping concentration N3 and the fourth doping concentration N4 are all in the range of 1E18cm-3 to 1E19cm- Within the range of 3, for example, 1.13E18cm-3, 1.33E18cm-3, 1.5E18cm-3, 1.86E18cm-3, 1E19cm-3, or other values.
  • the doping concentration of the first gradient layer 33 changes linearly from the first doping concentration N1 to the second doping concentration N2, and the doping concentration of the second gradient layer 37
  • the doping concentration of the third gradient layer 41 changes linearly from the second doping concentration N2 to the third doping concentration N3, and the doping concentration of the third gradient layer 41 changes from the third doping concentration N3 to the fourth doping concentration N4.
  • linear change refers to the linear relationship between the thickness of the gradient layer and the doping concentration difference on its opposite sides.
  • the doping concentration of the first gradient layer 33 changes nonlinearly or stepwise from the first doping concentration N1 to the second doping concentration N2.
  • the second gradient layer 37 The doping concentration changes linearly or stepwise from the second doping concentration N2 to the third doping concentration N3, and the doping concentration of the third gradient layer 41 changes from the third doping concentration N3 to The fourth doping concentration N4 changes linearly or stepwise.
  • the gradient manner of the doping concentration of the first gradient layer 33 includes one or more combinations of linear changes, non-linear changes and step changes, and the doping concentration of the second gradient layer 37
  • the gradient mode includes one or more combinations of linear change, nonlinear change or step change.
  • the gradient mode of the doping concentration of the third gradient layer 41 includes linear change, nonlinear change or step change. One or more combinations. This application does not impose specific restrictions on this.
  • the light-emitting chip epitaxial structure 100 includes a substrate 10, a first semiconductor component 30, a light-emitting layer 50 and a second semiconductor component 70 that are stacked in sequence.
  • the buffer layer 31, the first gradient layer 33, the corrosion stop layer 35, the second gradient layer 37, the ohmic contact layer 39, the third gradient layer 41, the current expansion layer 43, and the first restriction layer are stacked on the substrate 10. layer 45 and the first waveguide layer 47.
  • the first gradient layer 33 makes the doping concentration of the buffer layer 31 and the doping concentration of the corrosion stop layer 35 continuous
  • the second gradient layer 37 makes the doping concentration of the corrosion stop layer 35 and the doping concentration of the corrosion stop layer 35 continuous.
  • the doping concentration of the ohmic contact layer 39 is continuous, and the third gradient layer 41 makes the doping concentration of the ohmic contact layer 39 and the doping concentration of the current spreading layer 43 continuous. Therefore, the first gradient layer 33 , the second gradient layer 37 and the third gradient layer 41 make the doping between the doped layers of the first semiconductor component 30 more continuous, reducing the doping of each layer.
  • the series resistance between the layers further reduces the operating voltage of the light-emitting chip epitaxial structure 100 and also reduces the power consumption of the light-emitting chip epitaxial structure 100 .
  • the first semiconductor component 30 may be an N (Negative) type semiconductor
  • the second semiconductor component 70 may be a P (Positive) type semiconductor.
  • the buffer layer 31 is used to avoid lattice mismatch between the substrate 10 and the first semiconductor component 30 , which is beneficial to the generation of the first semiconductor component 30 .
  • the buffer layer 31 can also be used to eliminate the impact of surface defects of the substrate 10 on the first semiconductor component 30, provide a smooth interface for subsequent formation of doped layers, and improve the quality of the light-emitting chip epitaxial structure 100. the quality of.
  • the corrosion stop layer 35 is used as a protective layer in the etching process of manufacturing the light-emitting chip epitaxial structure 100 to prevent the substrate 10 and the buffer layer 31 from being corroded by the etching liquid.
  • the ohmic contact layer 39 is used to form ohmic contact with the first chip electrode (not shown), which is beneficial to the input or output of current.
  • the current spreading layer 43 is used to distribute the current passing through the current spreading layer 43 as uniformly as possible, thereby greatly improving the luminous efficiency of the light-emitting layer 50 .
  • the first confinement layer 45 is used to provide electrons to the light-emitting layer 50 while preventing carriers (electrons and holes) in the light-emitting layer 50 from moving outward, allowing more carriers (electrons and holes) to move outward. Holes) recombine in the light-emitting layer 50 to generate photons to ensure the amount of light emitted.
  • the first waveguide layer 47 is used to prevent impurities from diffusing into the light-emitting layer 50 .
  • the doping source used to make the first semiconductor component 30 may be silane (SiH4).
  • the substrate 10 may be a gallium arsenide (GaAs) substrate.
  • the substrate 10 may also be a sapphire substrate, a silicon substrate, a gallium nitride (GaN) substrate, a gallium phosphide (GaP) substrate, an aluminum gallium arsenide (AlGaAs) substrate, or Aluminum gallium indium phosphide (AlGaInP) substrate, etc.
  • the first gradient layer 33 may be silicon arsenide (SiAs) and a silicon layer
  • the second gradient layer 37 may be silicon phosphide (SiP) and a silicon layer
  • the third gradient layer 37 may be silicon phosphide (SiP) and a silicon layer.
  • Layer 41 may be a silicon arsenide or silicon layer.
  • the buffer layer 31 may be a Si-doped GaAs layer, and its thickness may be from 100 nm to 300 nm, for example, 100 nm, 150 nm, 170 nm, 200 nm, 240 nm, 300 nm, or other values. This application describes There is no specific limit to this.
  • the corrosion stop layer 35 may be a Si-doped Ga x1 In 1-x1 P layer, where x1 is greater than 0 and less than 1, for example, 0.05, 0.1, 0.45, 0.8, 0.99, or For other numerical values, this application does not impose specific restrictions on this.
  • the thickness of the corrosion stop layer 35 may be 50 nm to 300 nm, for example, 50 nm, 70 nm, 100 nm, 180 nm, 210 nm, 260 nm, 300 nm, or other values, which is not specifically limited in this application.
  • the ohmic contact layer 39 may be a Si-doped GaAs layer, and its thickness may be 10 nm to 150 nm, for example, 10 nm, 30 nm, 50 nm, 90 nm, 120 nm, 150 nm, or other numerical values. There are no specific restrictions on this application.
  • the current spreading layer 43 may be a Si -doped Al , 0.99, or other values, this application does not impose specific restrictions on this.
  • the thickness of the current spreading layer 43 may be 1000nm to 3000nm, for example, 1000nm, 1250nm, 1870nm, 2400nm, 3000nm, or other values, which is not specifically limited in this application.
  • the first confinement layer 45 may be a Si-doped Alx3In1 -x3P layer, where x3 is greater than 0 and less than 1, for example, 0.09, 0.10, 0.20, 0.25, 0.47, 0.71, 0.96, or other values, this application does not impose specific restrictions on this.
  • the thickness of the first confinement layer 45 may be 250nm to 450nm, for example, 250nm, 280nm, 300nm, 315nm, 380nm, 450nm, or other values, which is not specifically limited in this application.
  • the first waveguide layer 47 may be an Al x4 Ga 1-x4 InP layer, where x4 is greater than 0 and less than 1, for example, 0.03, 0.08, 0.14, 0.20, 0.39, 0.50, 0.67, 0.80, 0.95, or other values, this application does not impose specific restrictions on this.
  • the thickness of the first waveguide layer 47 may be 70 nm to 150 nm, for example, 70 nm, 81 nm, 105 nm, 110 nm, 135 nm, 150 nm, or other values, which is not specifically limited in this application.
  • the light-emitting layer 50 may be a quantum well layer, and the light-emitting layer 50 is used to radiatively recombine electrons and holes and emit light.
  • the light-emitting layer 50 may be an Al z1 Ga 1-z1 InP layer, where z1 is greater than 0 and less than 1, for example, 0.05, 0.10, 0.20, 0.23, 0.41, 0.50, 0.66, 0.98, or other numerical values, this application does not impose specific restrictions on this.
  • the thickness of the light-emitting layer 50 may be 100 nm to 300 nm, for example, 100 nm, 130 nm, 170 nm, 200 nm, 240 nm, 280 nm, 300 nm, or other values, which is not specifically limited in this application.
  • the second semiconductor component 70 includes a second waveguide layer 71 , a second confinement layer 73 , and a transition layer 75 that are stacked along the direction from the first semiconductor component 30 to the light-emitting layer 50 .
  • the window layer 77 that is, the second semiconductor component 70 includes a second waveguide layer 71, a second confinement layer 73, a transition layer 75 and a second waveguide layer 71 stacked on the surface of the light-emitting layer 50 facing away from the first waveguide layer 47. Window layer 77.
  • the second waveguide layer 71 is located on the side of the light-emitting layer 50 facing away from the first waveguide layer 47 and is attached to the light-emitting layer 50
  • the second limiting layer 73 is located on the side of the light-emitting layer 50 facing away from the first waveguide layer 47 .
  • the window layer 77 is located on the surface of the transition layer 75 facing away from the second confinement layer 73 .
  • the second waveguide layer 71 is used to prevent impurities from diffusing into the light-emitting layer 50 .
  • the second confinement layer 73 is used to provide holes for the light-emitting layer 50 while preventing carriers (electrons and holes) in the light-emitting layer 50 from moving outward, allowing more carriers (electrons) to and holes) recombine in the light-emitting layer 50 to generate photons to ensure the amount of light emitted.
  • the transition layer 75 is used to provide a growth surface for the window layer 77 and is beneficial to the crystal growth of the window layer 77 .
  • the window layer 77 is used to distribute the current passing through the window layer 77 as uniformly as possible, which greatly improves the luminous efficiency of the light-emitting layer 50. It is also used to form an ohmic contact with the second chip electrode, which is beneficial to the current flow. input or output.
  • the doping source of the second semiconductor component 70 may be a magnesium (Mg) source.
  • the second waveguide layer 71 may be an Al x5 Ga 1-x5 InP layer, where x5 is greater than 0 and less than 1, for example, 0.03, 0.10, 0.14, 0.20, 0.30, 0.39, 0.50, 0.67, 0.80, 0.95, or other values, this application does not impose specific restrictions on this.
  • the thickness of the second waveguide layer 71 may be 70 nm to 150 nm, for example, 70 nm, 81 nm, 90 nm, 100 nm, 105 nm, 120 nm, 135 nm, 150 nm, or other values, which is not specifically limited in this application.
  • the second confinement layer 73 may be a Mg-doped Alx6In1 -x6P layer, where x6 is greater than 0 and less than 1, for example, 0.05, 0.10, 0.21, 0.40, 0.50, 0.57, 0.68, 0.80, 0.90, 0.96, or other values, this application does not impose specific restrictions on this.
  • the thickness of the second confinement layer 73 may be 250nm to 450nm, for example, 250nm, 270nm, 300nm, 325nm, 375nm, 400nm, 450nm, or other values, which is not specifically limited in this application.
  • the transition layer 75 may be a Mg-doped (Al x7 Ga 1-x7 ) y In 1-y P layer, where x7 is greater than 0 and less than 1, for example, 0.03, 0.10, 0.15 , 0.21, 0.40, 0.47, 0.60, 0.73, 0.84, 0.95, or other values, this application does not impose specific restrictions on this; y is greater than 0 and less than 1, for example, 0.03, 0.10, 0.19, 0.30, 0.37, 0.50, 0.63, 0.80, 0.89, 0.90, 0.95, or other values, this application does not impose specific restrictions on this.
  • the thickness of the transition layer 75 may be 10 nm to 150 nm, for example, 10 nm, 25 nm, 50 nm, 57 nm, 100 nm, 106 nm, 120 nm, 145 nm, 150 nm, or other values, which is not specifically limited in this application.
  • the window layer 77 may be a Mg-doped gallium phosphide (GaP) layer, and its thickness may be from 3000 nm to 8000 nm, for example, 3000 nm, 4500 nm, 5500 nm, 6800 nm, 7400 nm, 8000 nm, or others. Numerical value, this application does not impose specific restrictions on this.
  • the light-emitting chip epitaxial structure 100 includes a substrate 10, a first semiconductor component 30, a light-emitting layer 50 and a second semiconductor component 70 that are stacked in sequence.
  • the buffer layer 31, the first gradient layer 33, the corrosion stop layer 35, the second gradient layer 37, the ohmic contact layer 39, the third gradient layer 41, the current expansion layer 43, and the first restriction layer are stacked on the substrate 10. layer 45 and the first waveguide layer 47.
  • the first gradient layer 33 makes the doping concentration of the buffer layer 31 and the doping concentration of the corrosion stop layer 35 continuous
  • the second gradient layer 37 makes the doping concentration of the corrosion stop layer 35 and the doping concentration of the corrosion stop layer 35 continuous.
  • the doping concentration of the ohmic contact layer 39 is continuous, and the third gradient layer 41 makes the doping concentration of the ohmic contact layer 39 and the doping concentration of the current spreading layer 43 continuous.
  • the buffer layer 31 is used to avoid lattice mismatch between the substrate 10 and the first semiconductor component 30, and can also eliminate the impact of surface defects of the substrate 10 on the first semiconductor component 30. Subsequent formation of each doped layer provides a smooth interface and improves the quality of the light-emitting chip epitaxial structure 100 .
  • the corrosion stop layer 35 serves as a protective layer during the etching process of manufacturing the light-emitting chip epitaxial structure 100 to prevent the substrate 10 and the buffer layer 31 from being corroded by the etching liquid.
  • the ohmic contact layer 39 forms ohmic contact with the first chip electrode, which is beneficial to the input or output of current.
  • the current spreading layer 43 distributes the current passing through the current spreading layer 43 as evenly as possible, which greatly improves the luminous efficiency of the luminescent layer 50 .
  • the first confinement layer 45 is used to provide electrons to the light-emitting layer 50 while preventing carriers (electrons and holes) in the light-emitting layer 50 from moving outward, allowing more carriers (electrons and holes) to move outward. Holes) recombine in the light-emitting layer 50 to generate photons to ensure the amount of light emitted.
  • the first waveguide layer 47 prevents impurities from diffusing into the light-emitting layer 50 .
  • the first gradient layer 33 , the second gradient layer 37 and the third gradient layer 41 make the doping between the doped layers of the first semiconductor component 30 more continuous, reducing the doping of each layer.
  • the series resistance between the layers further reduces the operating voltage of the light-emitting chip epitaxial structure 100 and also reduces the power consumption of the light-emitting chip epitaxial structure 100 .
  • FIG. 3 is a schematic diagram of the layer structure of a light-emitting chip disclosed in an embodiment of the present application.
  • the light-emitting chip 150 includes a first chip electrode 101, a second chip electrode 103 and the above-mentioned light-emitting chip epitaxial structure 100.
  • the first chip electrode 101 is electrically connected to the first semiconductor component 30, and the second chip electrode 103 is electrically connected to the second semiconductor component 70 .
  • the first chip electrode 101 is electrically connected to the ohmic contact layer 39
  • the second chip electrode 103 is electrically connected to the window layer 77 .
  • the light emitting chip 150 may be a Mini LED chip or a Micro LED chip.
  • the light-emitting chip 150 may be an aluminum gallium indium phosphide (AlGaInP) based light-emitting chip.
  • AlGaInP aluminum gallium indium phosphide
  • the light-emitting chip 150 provided by the embodiment of the present application includes a first chip electrode 101, a second chip electrode 103, and a light-emitting chip epitaxial structure 100.
  • the light-emitting chip epitaxial structure 100 includes a substrate 10 and a third chip that are stacked in sequence.
  • the first semiconductor component 30 includes a buffer layer 31, a first gradient layer 33, a corrosion stop layer 35 and a The second gradient layer 37 , the ohmic contact layer 39 , the third gradient layer 41 , the current spreading layer 43 and the first limiting layer 45 .
  • the first gradient layer 33 is used to make the doping concentration of the buffer layer 31 and the corrosion stop layer 35 continuous
  • the second gradient layer 37 is used to make the doping concentration of the corrosion stop layer 35 continuous.
  • the doping concentration of the ohmic contact layer 39 is continuous with that of the ohmic contact layer 39
  • the third gradient layer 41 is used to make the doping concentration of the ohmic contact layer 39 continuous with that of the current spreading layer 43 . Therefore, the first gradient layer 33 , the second gradient layer 37 and the third gradient layer 41 make the doping between the doped layers of the first semiconductor component 30 more continuous, reducing the doping of each layer.
  • the series resistance between the layers further reduces the operating voltage of the light-emitting chip epitaxial structure 100 and also reduces the power consumption of the light-emitting chip epitaxial structure 100 .
  • FIG. 4 is a schematic diagram of the layer structure of a display panel disclosed in an embodiment of the present application.
  • the display panel 500 provided in the embodiment of the present application includes a driving substrate 200 and a plurality of the above-mentioned light-emitting chips 150.
  • the plurality of light-emitting chips 150 are arranged on the same side of the driving substrate 200 and are electrically connected to the driving substrate 200.
  • the driving substrate 200 is used to transmit electrical signals to the plurality of light-emitting chips 150 to control the plurality of light-emitting chips 150 to emit light. Since the light-emitting chip epitaxial structure 100 and the light-emitting chip 150 have been described in detail in the embodiments shown in FIGS. 1 to 3 , they will not be described again here.
  • the display panel may be used to include a device such as a Personal Digital Assistant (Personal Digital Assistant). Assistant, PDA) and/or music player functions, such as mobile phones, tablets, wearable electronic devices with wireless communication functions (such as smart watches), etc.
  • PDA Personal Digital Assistant
  • music player functions such as mobile phones, tablets, wearable electronic devices with wireless communication functions (such as smart watches), etc.
  • the above-mentioned electronic device may also be other electronic devices, such as a laptop computer (Laptop) with a touch-sensitive surface (such as a touch panel).
  • the electronic device may have a communication function, that is, it can communicate through 2G (second generation mobile phone communication technical specifications), 3G (third generation mobile phone communication technical specifications), 4G (fourth generation mobile phone communication technical specifications) , 5G (fifth generation mobile phone communication technology specifications) or W-LAN (wireless local area network) or communication methods that may appear in the future to establish communication with the network.
  • 2G second generation mobile phone communication technical specifications
  • 3G third generation mobile phone communication technical specifications
  • 4G fourth generation mobile phone communication technical specifications
  • 5G fifth generation mobile phone communication technology specifications
  • W-LAN wireless local area network
  • the display panel 500 provided by the embodiment of the present application includes a driving substrate 200 and a light-emitting chip 150.
  • the light-emitting chip 150 includes a first chip electrode 101, a second chip electrode 103 and a light-emitting chip epitaxial structure 100.
  • the chip epitaxial structure 100 includes a substrate 10 , a first semiconductor component 30 , a light-emitting layer 50 and a second semiconductor component 70 that are stacked in sequence.
  • the first semiconductor component 30 includes a buffer layer that is stacked in sequence on the substrate 10 31.
  • the first gradient layer 33 , the corrosion stop layer 35 , the second gradient layer 37 , the ohmic contact layer 39 , the third gradient layer 41 , the current spreading layer 43 and the first confinement layer 45 are examples of the first semiconductor component 30 .
  • the first gradient layer 33 is used to make the doping concentration of the buffer layer 31 and the corrosion stop layer 35 continuous
  • the second gradient layer 37 is used to make the doping concentration of the corrosion stop layer 35 continuous.
  • the doping concentration of the ohmic contact layer 39 is continuous with that of the ohmic contact layer 39
  • the third gradient layer 41 is used to make the doping concentration of the ohmic contact layer 39 continuous with that of the current spreading layer 43 . Therefore, the first gradient layer 33 , the second gradient layer 37 and the third gradient layer 41 make the doping between the doped layers of the first semiconductor component 30 more continuous, reducing the doping of each layer.
  • the series resistance between the layers further reduces the operating voltage of the light-emitting chip epitaxial structure 100 and also reduces the power consumption of the light-emitting chip epitaxial structure 100 .
  • FIG. 5 is a schematic diagram of the layer structure of a display device disclosed in an embodiment of the present application.
  • the display device 1000 provided by the embodiment of the present application includes a glass cover 700 and the above-mentioned display panel 500.
  • the glass cover 700 is covered on the light exit side of the display panel 500.
  • the glass cover 700 is used to protect the display panel 500.
  • the display panel 500 prevents the display panel 500 from being affected by impurities such as external air, water vapor, dust, etc., thereby reducing the service life of the display panel 500 or causing damage.
  • the display device includes but is not limited to: Mini LED panel, Mirco LED panel, mobile phone, tablet computer, navigator, display and any other electronic device or component with a display function, which is not specifically limited in this application.
  • the specific type of the display device is not particularly limited. Those skilled in the art can design it accordingly according to the specific usage requirements of the display device, which will not be described again here.
  • the display device also includes other necessary components and components such as a power board, a high voltage board, a key control board, etc. Those skilled in the art can supplement accordingly according to the specific type and actual functions of the display device. I won’t go into details here.
  • the display device 1000 provided by the embodiment of the present application includes a glass cover 700 and a display panel 500.
  • the display panel 500 includes a driving substrate 200 and a light-emitting chip 150.
  • the light-emitting chip 150 includes a first chip electrode 101
  • the second chip electrode 103 and the light-emitting chip epitaxial structure 100 include a substrate 10, a first semiconductor component 30, a light-emitting layer 50 and a second semiconductor component 70 that are stacked in sequence.
  • the first semiconductor component 30 includes a buffer layer 31, a first gradient layer 33, an corrosion stop layer 35, a second gradient layer 37, an ohmic contact layer 39, a third gradient layer 41, and a current expansion layer 43 that are sequentially stacked on the substrate 10.
  • the first confinement layer 45 and the first waveguide layer 47 The first gradient layer 33 is used to make the doping concentration of the buffer layer 31 and the corrosion stop layer 35 continuous, and the second gradient layer 37 is used to make the doping concentration of the corrosion stop layer 35 continuous.
  • the doping concentration of the ohmic contact layer 39 is continuous with that of the ohmic contact layer 39
  • the third gradient layer 41 is used to make the doping concentration of the ohmic contact layer 39 continuous with that of the current spreading layer 43 . Therefore, the first gradient layer 33 , the second gradient layer 37 and the third gradient layer 41 make the doping between the doped layers of the first semiconductor component 30 more continuous, reducing the doping of each layer.
  • the series resistance between the layers further reduces the operating voltage of the light-emitting chip epitaxial structure 100 and also reduces the power consumption of the light-emitting chip epitaxial structure 100 .
  • embodiments of the present application provide a method for manufacturing a light-emitting chip epitaxial structure, which is used to manufacture the above-mentioned light-emitting chip epitaxial structure 100 .
  • FIG. 6 is a schematic flowchart of a method for manufacturing an epitaxial structure of a light-emitting chip disclosed in an embodiment of the present application.
  • the manufacturing method is used to manufacture the light-emitting chip epitaxial structure 100 shown in FIGS. 1 and 2.
  • the manufacturing method of this embodiment is Descriptions related to the light-emitting chip epitaxial structure 100 can be directly referred to the above embodiments and will not be described again here.
  • the method for manufacturing the epitaxial structure of the light-emitting chip provided by the embodiment of the present application may at least include the following steps.
  • a substrate 10 is provided, and the substrate 10 can be cleaned with organic solvents and acid solutions.
  • the substrate 10 can also be subjected to high temperature treatment to clean the surface of the substrate 10 .
  • the substrate 10 may be a GaAs substrate, and the substrate 10 provides a growth surface for subsequent epitaxial structures.
  • the first semiconductor component includes a buffer layer, a first gradient layer, an corrosion stop layer, and a second gradient layer that are sequentially stacked on the substrate.
  • the light-emitting layer 50 may be an Alz1Ga1-z1InP layer, where z1 is greater than 0 and less than 1, and the thickness of the light-emitting layer 50 may be 100 nm to 300 nm.
  • the second semiconductor component 70 includes a second waveguide layer 71 , a second confinement layer 73 , a transition layer 75 and a window layer 77 that are sequentially stacked on the light-emitting layer 50 .
  • the second waveguide layer 71 may be an Al x5 Ga 1-x5 InP layer, where x5 is greater than 0 and less than 1, and the thickness of the second waveguide layer 71 may be 70 nm to 150 nm.
  • the second confinement layer 73 may be a Mg - doped Al 75 may be a Mg-doped (Al x7 Ga 1-x7 ) y In 1-y P layer, where x7 is greater than 0 and less than 1, and the thickness of the transition layer 75 may be 10 nm to 150 nm.
  • the window layer 77 may be a Mg-doped gallium phosphide (GaP) layer, and its thickness may be 3000 nm to 8000 nm.
  • step S420 is a schematic flowchart of step S420 in a method for manufacturing a light-emitting chip epitaxial structure disclosed in an embodiment of the present application. Please refer to FIG. 1 .
  • step S420 may include at least the following steps.
  • the substrate 10 is placed in a reaction chamber, the temperature in the reaction chamber is set to 690 to 730°C and the pressure is 50 mbar, and arsane, trimethylgallium and the third reaction chamber are simultaneously introduced into the reaction chamber.
  • a silane doped with concentration N1 wherein the trimethylgallium is a Group III source, the arsane is a Group V source, the trimethylgallium is introduced into the reaction chamber with hydrogen as a carrier, and the silane is doped Miscellaneous sources. That is, arsane, trimethylgallium and silane with the first doping concentration N1 are simultaneously introduced into the reaction chamber to generate the buffer layer 31 on the substrate 10 .
  • the temperature in the reaction chamber may be: 690°C, 700°C, 715°C, 720°C, 730°C, or other values.
  • the buffer layer 31 may be a Si-doped GaAs layer, and its thickness may be 100 nm to 300 nm.
  • the buffer layer 31 matches the crystal lattice of the substrate 10 to avoid the The buffer layer 31 is misaligned with the substrate 10 , which is beneficial to the subsequent generation of epitaxial structures.
  • the flow of trimethylgallium is turned off and the flow of silane and arsane is maintained. That is, the passage of silane and arsane is maintained, and the concentration of silane is gradually changed from the first doping concentration N1 to the second doping concentration N2, so that the buffer layer 31 faces away from the substrate 10 A first gradient layer 33 is generated on the surface.
  • the concentration of silane introduced increases, part of the silane reacts with arsane to form silicon arsenide, and part of the silane is cracked to form silicon, so the first gradient layer 33 is made of arsenic. silicon and silicon layers. Since the amount of silane introduced is gradually increased, the concentration of silicon in the first gradient layer 33 is gradually increased.
  • the second doping concentration N2 is greater than the first doping concentration N1, and the process of the first doping concentration N1 gradually changing to the second doping concentration N2 is a linear change.
  • the first gradient layer 33 may be a silicon arsenide (SiAs) and silicon layer, that is, silane reacts with arsane to form silicon arsenide, and part of the silane is cracked to form silicon.
  • phosphane, trimethylgallium, trimethylindium and silane with the second doping concentration N2 are simultaneously introduced into the reaction chamber, so that the first gradient layer 33 faces away from the buffer layer.
  • the corrosion stop layer 35 is formed on the surface.
  • the phosphane is a Group V source
  • the trimethylgallium and the trimethylindium are a Group III source
  • the silane is a doping source.
  • the corrosion stop layer 35 may be a Si-doped Ga x1 In 1-x1 P layer, where x1 is greater than 0 and less than 1.
  • the thickness of the corrosion stop layer 35 may be 50 nm to 300 nm.
  • the doping concentration of the ohmic contact layer is such that the second graded layer is formed on the surface of the corrosion stop layer facing away from the first graded layer.
  • the access to trimethylgallium and trimethylindium is closed, and the access to silane and phosphorane is maintained. That is, the access of silane and phosphorane is maintained, and the silane concentration is gradually changed from the second doping concentration N2 to the third doping concentration N3, so that the corrosion stop layer 35 faces away from the first gradient layer 33 Said second gradient layer 37 is produced on the surface.
  • the concentration of silane introduced increases, part of the silane reacts with phosphorus to form silicon phosphide, and part of the silane is cracked to form silicon, so the first gradient layer is phosphide. Silicon and silicon layers. Since the amount of silane introduced is gradually increased, the concentration of silicon in the second gradient layer 37 is gradually increased.
  • the third doping concentration N3 is greater than the second doping concentration N2, and the process of the second doping concentration N2 gradually changing to the third doping concentration N3 is a linear change.
  • the second gradient layer 37 may be a silicon phosphide (SiP) and silicon layer, that is, silane reacts with phosphorane to generate silicon phosphide, and part of the silane is cracked to generate silicon.
  • arsenane, trimethylgallium and silane with the third doping concentration N3 are simultaneously introduced into the reaction chamber to generate a gas on the surface of the second gradient layer 37 facing away from the corrosion stop layer 35 .
  • the ohmic contact layer 39 .
  • the arsane is a Group V source
  • the trimethylgallium is a Group III source
  • the silane is a doping source.
  • the ohmic contact layer 39 may be a Si-doped GaAs layer, and may have a thickness of 10 nm to 150 nm.
  • the access to trimethylgallium is turned off and the access to silane and arsane is maintained. That is, the access of silane and arsane is maintained, and the concentration of silane is gradually changed from the third doping concentration N3 to the fourth doping concentration N4, so that the ohmic contact layer 39 faces away from the second gradient.
  • Said third gradient layer 41 is formed on the surface of layer 37 .
  • the third gradient layer 41 when the third gradient layer 41 is grown, part of the silane reacts with arsane to form silicon arsenide, and part of the silane is cracked to form silicon, so the third gradient layer 41 is a silicon arsenide and silicon layer. Since the amount of silane introduced is gradually reduced, the concentration of silicon in the third gradient layer 41 is gradually reduced.
  • the fourth doping concentration N4 is smaller than the third doping concentration N3, and the process of the third doping concentration N3 gradually changing to the second doping concentration N2 is a linear change.
  • the third gradient layer 41 may be a silicon arsenide (SiAs) and silicon layer, that is, silane reacts with arsane to form silicon arsenide, and part of the silane is cracked to form silicon.
  • phosphane, trimethylaluminum, trimethylgallium, trimethylindium and silane with the fourth doping concentration N4 are simultaneously introduced into the reaction chamber, so that the third gradient layer 41 faces The current spreading layer 43 is formed on the surface of the ohmic contact layer 39 .
  • the phosphane is a Group V source
  • the trimethylaluminum, trimethylgallium and trimethylindium are Group III sources
  • silane is a doping source.
  • the current spreading layer 43 may be a Si-doped Al x2 Ga 1-x2 InP layer, where x2 is greater than 0 and less than 1.
  • the thickness of the current spreading layer 43 may be 1000 nm to 3000 nm.
  • phosphane, trimethylaluminum, trimethylindium and silane are simultaneously introduced into the reaction chamber to generate the said current spreading layer 43 on the surface facing away from the third gradient layer 41 .
  • the phosphane is a Group V source
  • the trimethylaluminum and the trimethylindium are a Group III source
  • the silane is a doping source.
  • the first confinement layer 45 may be a Si-doped Al x3 In 1-x3 P layer, where x3 is greater than 0 and less than 1.
  • the thickness of the first confinement layer 45 may be 250 nm to 450 nm.
  • First waveguide layer 47 phosphane, trimethylaluminum, trimethylgallium and trimethylindium are simultaneously introduced into the reaction chamber to generate the first confinement layer 45 on the surface facing away from the current spreading layer 43 .
  • First waveguide layer 47 may be an Al x4 Ga 1-x4 InP layer, where x4 is greater than 0 and less than 1.
  • the thickness of the first waveguide layer 47 may be 70 nm to 150 nm.
  • the ratio of the molar amount of the group V source to the molar amount of the group III source is 150 to 250, that is, V/III is 150-250.
  • Group V sources include trimethylaluminum, trimethylgallium and trimethylindium
  • Group III sources include arsane and phosphine.
  • the flow rate of the Group III source passed in may range from 30 sccm to 100 sccm, for example, 30 sccm, 41 sccm, 67 sccm, 80 sccm, 100 sccm, or other values.
  • sccm is the standard liter per minute flow value.
  • the manufacturing method of the light-emitting chip epitaxial structure 100 can be chemical vapor deposition (Chemical Vapor Deposition, CVD) or physical vapor deposition (Physical Vapor Deposition, PVD).
  • CVD refers to a method in which chemical gases or vapor react on the surface of a substrate to synthesize coatings or nanomaterials.
  • PVD refers to the use of physical methods under vacuum conditions to vaporize the surface of a material source (solid or liquid) into gaseous atoms or molecules, or partially A technology that ionizes into ions and deposits thin films on the surface of a substrate through a low-pressure gas (or plasma) process.
  • the method for manufacturing the epitaxial structure of a light-emitting chip at least includes: providing a substrate 10; forming a first semiconductor component 30 on the substrate 10, wherein the first semiconductor component 30 It includes the buffer layer 31, the first gradient layer 33, the corrosion stop layer 35, the second gradient layer 37, the ohmic contact layer 39, the third gradient layer 41, the current expansion layer 43, and the third gradient layer 31, which are sequentially stacked on the substrate 10.
  • a confinement layer 45 and a first waveguide layer 47; a luminescent layer 50 is formed on the surface of the first semiconductor component 30 facing away from the substrate 10; a luminescent layer 50 is formed on a surface facing away from the first semiconductor component 30
  • a second semiconductor component 70 is formed on the surface.
  • the first gradient layer 33 is used to make the doping concentration of the buffer layer 31 and the corrosion stop layer 35 continuous
  • the second gradient layer 37 is used to make the doping concentration of the corrosion stop layer 35 continuous.
  • the doping concentration of the ohmic contact layer 39 is continuous with that of the ohmic contact layer 39
  • the third gradient layer 41 is used to make the doping concentration of the ohmic contact layer 39 continuous with that of the current spreading layer 43 . Therefore, the first gradient layer 33 , the second gradient layer 37 and the third gradient layer 41 make the doping between the doped layers of the first semiconductor component 30 more continuous, reducing the doping of each layer.
  • the series resistance between the layers further reduces the operating voltage of the light-emitting chip epitaxial structure 100 and also reduces the power consumption of the light-emitting chip epitaxial structure 100 .

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Abstract

本申请涉及一种发光芯片外延结构（100），包括依次层叠设置的第一半导体组件（30）、发光层（50）和第二半导体组件（70），第一半导体组件（30）包括依次层叠设置的缓冲层（31）、第一渐变层（33）、腐蚀截止层（35）、第二渐变层（37）、欧姆接触层（39）、第三渐变层（41）、电流扩展层（43）、第一限制层（45）和第一波导层（47），第一渐变层（33）使缓冲层（31）的掺杂浓度和腐蚀截止层（35）的掺杂浓度连续，第二渐变层（37）使腐蚀截止层（35）的掺杂浓度和欧姆接触层（39）的掺杂浓度连续，第三渐变层（41）使欧姆接触层（39）的掺杂浓度和电流扩展层（43）的掺杂浓度连续。

Description

发光芯片外延结构及其制作方法、发光芯片以及显示面板 技术领域
本申请涉及显示技术领域，特别涉及一种发光芯片外延结构、一种发光芯片外延结构的制作方法、一种具有该发光芯片外延结构的发光芯片以及一种具有该发光芯片的显示面板。
 背景技术
由于次毫米发光二极管(Mini Light Emitting Diode，Mini LED)芯片、微型发光二极管(Micro Light Emitting Diode，Micro LED)芯片等LED芯片的尺寸小、集成度高、厚度薄以及更优的亮度、分辨率和对比度等优点，在显示屏领域得到了广泛的应用。因为Mini LED芯片和Micro LED芯片的尺寸小以及外延层薄，故其需要更低的工作电压，低工作电压也可降低工作时的功耗。
 技术问题
目前，降低LED芯片的工作电压主要是采用提高各掺杂层的掺杂浓度或把非掺杂层的厚度减薄的方式。但是，由于掺杂层的源材料溶解度有限，过多的掺杂会导致掺杂饱和，这并不能提高掺杂层中电子或空穴的浓度，反而会恶化源材料的晶体质量或形貌；非掺杂层的厚度减薄可以起到降低电压的效果，但是这会影响到LED芯片的光电性能及老化特性。因此，如何在不影响LED芯片的光学性能及质量的同时降低LED芯片的串联电阻以降低工作电压是亟待解决的问题。
 技术解决方案
鉴于上述现有技术的不足，本申请的目的在于提供一种发光芯片外延结构、一种发光芯片外延结构的制作方法、一种具有该发光芯片外延结构的发光芯片以及一种具有该发光芯片的显示面板，其旨在不影响发光芯片的光学性能及质量的同时降低发光芯片的串联电阻以降低其工作电压。
一种发光芯片外延结构，包括依次层叠设置的第一半导体组件、发光层以及第二半导体组件。其中，所述第一半导体组件包括依次层叠设置的缓冲层、第一渐变层、腐蚀截止层、第二渐变层、欧姆接触层、第三渐变层、电流扩展层、第一限制层以及第一波导层。所述第一渐变层使所述缓冲层的掺杂浓度和所述腐蚀截止层的掺杂浓度连续，所述第二渐变层使所述腐蚀截止层的掺杂浓度和所述欧姆接触层的掺杂浓度连续，所述第三渐变层使所述欧姆接触层的掺杂浓度和所述电流扩展层的掺杂浓度连续。
上述的发光芯片外延结构包括依次层叠设置的第一半导体组件、发光层以及第二半导体组件。其中，所述第一半导体组件包括依次层叠设置的缓冲层、第一渐变层、腐蚀截止层、第二渐变层、欧姆接触层、第三渐变层、电流扩展层、第一限制层以及第一波导层。所述第一渐变层使所述缓冲层的掺杂浓度和所述腐蚀截止层的掺杂浓度连续，所述第二渐变层使所述腐蚀截止层的掺杂浓度和所述欧姆接触层的掺杂浓度连续，所述第三渐变层使所述欧姆接触层的掺杂浓度和所述电流扩展层的掺杂浓度连续。因此，所述第一渐变层、所述第二渐变层和所述第三渐变层使得所述第一半导体组件的各掺杂层之间掺杂更连续，降低了各掺杂层之间的串联电阻，进而降低了所述发光芯片外延结构的工作电压，同时也降低了所述发光芯片外延结构的功耗。
可选地，所述第一渐变层的掺杂浓度的渐变方式包括线性变化、非线性变化和阶梯式变化中的任意一种或多种组合，所述第二渐变层的掺杂浓度的渐变方式包括线性变化、非线性变化或阶梯式变化中的任意一种或多种组合，所述第三渐变层的掺杂浓度的渐变方式包括线性变化、非线性变化或阶梯式变化中的任意一种或多种组合。
可选地，所述第一渐变层的掺杂浓度由所述缓冲层指向所述腐蚀截止层的方向逐渐增大，所述第二渐变层的掺杂浓度由所述腐蚀截止层指向所述欧姆接触层的方向逐渐增大，所述第三渐变层的掺杂浓度由所述欧姆接触层指向所述电流扩展层的方向逐渐减小。
可选地，所述第一渐变层为砷化硅和硅层，所述第二渐变层为磷化硅层和硅，所述第三渐变层为砷化硅和硅层。
可选地，所述缓冲层为砷化镓层，所述缓冲层的厚度为100nm至300nm，所述腐蚀截止层为Ga x1In 1-x1P层，所述腐蚀截止层的厚度为50nm至300nm，所述欧姆接触层为砷化镓层，所述欧姆接触层的厚度为10nm至150nm，所述电流扩展层为Al x2Ga 1-x2InP层，所述电流扩展层的厚度为1000nm至3000nm，所述第一限制层为Al x3In 1-x3P层，所述第一限制层的厚度为250nm至450nm，所述第一波导层为Al x4Ga 1-x4InP层，所述第一波导层的厚度为70nm至150nm，其中，x1、x2、x3和x4均大于0且小于1。
可选地，所述发光层为量子阱层，所述第二半导体组件包括依次层叠设置于所述发光层背对所述第一波导层一侧的第二波导层、第二限制层、过渡层以及窗口层。
基于同样的构思，本申请提供一种发光芯片，所述发光芯片包括第一芯片电极、第二芯片电极以及上述的发光芯片外延结构，所述第一芯片电极与所述发光芯片外延结构的第一半导体组件电连接，所述第二芯片电极与所述发光芯片外延结构的第二半导体组件电连接。
上述的发光芯片包括第一芯片电极、第二芯片电极以及发光芯片外延结构，所述发光芯片外延结构包括依次层叠设置的第一半导体组件、发光层以及第二半导体组件。其中，所述第一半导体组件包括依次层叠设置的缓冲层、第一渐变层、腐蚀截止层、第二渐变层、欧姆接触层、第三渐变层、电流扩展层、第一限制层以及第一波导层。所述第一渐变层使所述缓冲层的掺杂浓度和所述腐蚀截止层的掺杂浓度连续，所述第二渐变层使所述腐蚀截止层的掺杂浓度和所述欧姆接触层的掺杂浓度连续，所述第三渐变层使所述欧姆接触层的掺杂浓度和所述电流扩展层的掺杂浓度连续。因此，所述第一渐变层、所述第二渐变层和所述第三渐变层使得所述第一半导体组件的各掺杂层之间掺杂更连续，降低了各掺杂层之间的串联电阻，进而降低了所述发光芯片外延结构的工作电压，同时也降低了所述发光芯片外延结构的功耗。
基于同样的构思，本申请还提供一种显示面板，所述显示面板包括驱动基板以及多个上所述的发光芯片，多个所述发光芯片设置在所述驱动基板上，并与所述驱动基板电连接，所述驱动基板用于向多个所述发光芯片传输电信号以控制多个所述发光芯片发光。
上述显示面板包括驱动基板和多个发光芯片，所述发光芯片包括第一芯片电极、第二芯片电极以及发光芯片外延结构，所述发光芯片外延结构包括依次层叠设置第一半导体组件、发光层以及第二半导体组件。其中，所述第一半导体组件包括依次层叠设置的缓冲层、第一渐变层、腐蚀截止层、第二渐变层、欧姆接触层、第三渐变层、电流扩展层、第一限制层以及第一波导层。所述第一渐变层使所述缓冲层的掺杂浓度和所述腐蚀截止层的掺杂浓度连续，所述第二渐变层使所述腐蚀截止层的掺杂浓度和所述欧姆接触层的掺杂浓度连续，所述第三渐变层使所述欧姆接触层的掺杂浓度和所述电流扩展层的掺杂浓度连续。因此，所述第一渐变层、所述第二渐变层和所述第三渐变层使得所述第一半导体组件的各掺杂层之间掺杂更连续，降低了各掺杂层之间的串联电阻，进而降低了所述发光芯片外延结构的工作电压，同时也降低了所述发光芯片外延结构的功耗。
基于同样的构思，本申请还提供一种发光芯片外延结构的制作方法，用于制作上所述的发光芯片外延结构，所述制作方法包括：
提供一衬底；
在所述衬底上生成第一半导体组件，其中，所述第一半导体组件包括依次层叠设置于所述衬底上的缓冲层、第一渐变层、腐蚀截止层、第二渐变层、欧姆接触层、第三渐变层、电流扩展层、第一限制层以及第一波导层；
在所述第一半导体组件背对所述衬底的表面上形成发光层；
在所述发光层背对所述第一半导体组件的表面上生成第二半导体组件。
可选地，所述在所述衬底上生成第一半导体组件，包括：
通入所述缓冲层对应的Ⅲ族源、所述缓冲层对应的Ⅴ族源以及掺杂源，以在所述衬底上生成所述缓冲层；
中断生长所述缓冲层对应的Ⅲ族源，保持生长所述缓冲层对应的Ⅴ族源通入，掺杂源由生长所述缓冲层对应的掺杂浓度渐变至生长所述腐蚀截止层的掺杂浓度，以在所述缓冲层背对所述衬底的表面上生成所述第一渐变层；
通入所述腐蚀截止层对应的Ⅲ族源、所述腐蚀截止层对应的Ⅴ族源以及掺杂源，以在所述第一渐变层背对所述缓冲层的表面上生成所述腐蚀截止层；
中断生长所述腐蚀截止层对应的Ⅲ族源，保持生长所述腐蚀截止层对应的Ⅴ族源通入，掺杂源由生长所述腐蚀截止层对应的掺杂浓度渐变至生长所述欧姆接触层的掺杂浓度，以在所述腐蚀截止层背对所述第一渐变层的表面上生成所述第二渐变层；
通入所述欧姆接触层对应的Ⅲ族源、所述欧姆接触层对应的Ⅴ族源以及掺杂源，以在所述第二渐变层背对所述腐蚀截止层的表面上生成所述欧姆接触层；
中断生长所述欧姆接触层对应的Ⅲ族源，保持生长所述欧姆接触层对应的Ⅴ族源通入，掺杂源由生长所述欧姆接触层对应的掺杂浓度渐变至生长所述电流扩展层的掺杂浓度，以在所述欧姆接触层背对所述第二渐变层的表面上生成所述第三渐变层；
在所述第三渐变层背对所述欧姆接触层的表面上生成所述电流扩展层；
在所述电流扩展层背对所述第三渐变层的表面上生成所述第一限制层；
在所述第一限制层背对所述电流扩展层表面上生成所述第一波导层。
上述的制作方法包括：提供一衬底；在所述衬底上生成第一半导体组件，其中，所述第一半导体组件包括依次层叠设置于所述衬底上的缓冲层、第一渐变层、腐蚀截止层、第二渐变层、欧姆接触层、第三渐变层、电流扩展层、第一限制层以及第一波导层；在所述第一半导体组件背对所述衬底的表面上形成发光层；在所述发光层背对所述第一半导体组件的表面上生成第二半导体组件。因此，所述第一渐变层、所述第二渐变层和所述第三渐变层使得所述第一半导体组件的各掺杂层之间掺杂更连续，降低了各掺杂层之间的串联电阻，进而降低了所述发光芯片外延结构的工作电压，同时也降低了所述发光芯片外延结构的功耗。
 有益效果
所述第一渐变层使所述缓冲层的掺杂浓度和所述腐蚀截止层的掺杂浓度连续，所述第二渐变层使所述腐蚀截止层的掺杂浓度和所述欧姆接触层的掺杂浓度连续，所述第三渐变层使所述欧姆接触层的掺杂浓度和所述电流扩展层的掺杂浓度连续。因此，所述第一渐变层、所述第二渐变层和所述第三渐变层使得所述第一半导体组件的各掺杂层之间掺杂更连续，降低了各掺杂层之间的串联电阻，进而降低了所述发光芯片外延结构的工作电压，同时也降低了所述发光芯片外延结构的功耗。
 附图说明
图1为本申请实施例公开的一种发光芯片外延结构的层结构示意图；
图2为本申请实施例公开的掺杂浓度-生长时间曲线的坐标系图；
图3为本申请实施例公开的一种发光芯片的层结构示意图；
图4为本申请实施例公开的一种显示面板的层结构示意图；
图5为本申请实施例公开的一种显示装置的层结构示意图；
图6为本申请实施例公开的一种发光芯片外延结构制作方法的流程示意图；
图7本申请实施例公开的一种发光芯片外延结构的制作方法中步骤S420的流程示意图。
附图标记说明：
100-发光芯片外延结构；10-衬底；30-第一半导体组件；31-缓冲层；33-第一渐变层；35-腐蚀截止层；37-第二渐变层；39-欧姆接触层；41-第三渐变层；43-电流扩展层；45-第一限制层；47-第一波导层；50-发光层；70-第二半导体组件；71-第二波导层；73-第二限制层；75-过渡层；77-窗口层；150-发光芯片；101-第一芯片电极；103-第二芯片电极；200-驱动基板；500-显示面板；700-玻璃盖板；1000-显示装置；N1-第一掺杂浓度；N2-第二掺杂浓度；N3-第三掺杂浓度；N4-第四掺杂浓度；S410-S440-发光芯片外延结构制作方法的步骤；S421-S429-步骤S420的步骤。
 本发明的实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳实施方式。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施方式。相反地，提供这些实施方式的目的是使对本申请的公开内容理解的更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体地实施方式的目的，不是旨在于限制本申请。
由于次毫米发光二极管(Mini Light Emitting Diode，Mini LED)芯片、微型发光二极管(Micro Light Emitting Diode，Micro LED)芯片等LED芯片的尺寸小、集成度高、厚度薄以及更优的亮度、分辨率和对比度等优点，在显示屏领域得到了广泛的应用。因为Mini LED芯片和Micro LED芯片的尺寸小以及外延层薄，故其需要更低的工作电压，低工作电压也可降低工作时的功耗。目前，业界降低LED芯片的工作电压主要是采用提高各掺杂层的掺杂浓度或把非掺杂层的厚度减薄的方式。但是，由于掺杂层的源材料溶解度有限，过多的掺杂会导致掺杂饱和，这并不能提高掺杂层中电子或空穴的浓度，反而会恶化源材料的晶体质量或形貌；非掺杂层的厚度减薄可以起到降低电压的效果，但是这会影响到LED芯片的光电性能及老化特性。因此，如何在不影响LED芯片的光学性能及质量的同时降低LED芯片的串联电阻以降低工作电压是技术人员亟待解决的问题。
基于此，本申请希望提供一种能够解决上述技术问题的方案，其可以在不影响发光芯片的光学性能及质量的同时还可以降低发光芯片的串联电阻以降低其工作电压，其详细内容将在后续实施例中得以阐述。
本申请方案的详细阐述发光芯片外延结构、发光芯片外延结构的制作方法、发光芯片以及显示面板具体如下所述。
请参阅图1，图1为本申请实施例公开的一种发光芯片外延结构的层结构示意图。本申请实施例提供的发光芯片外延结构100至少可以包括依次层叠设置的衬底10、第一半导体组件30、发光层50以及第二半导体组件70，也即为，所述发光层50位于所述第一半导体组件30和所述第二半导体组件70之间，所述衬底10位于所述第一半导体组件30背对所述发光层50的一侧，所述第一半导体组件30和所述第二半导体组件70分别用于向所述发光层50提供相应的载流子，所述发光层50用于接收载流子并发光。
在本申请实施方式中，所述第一半导体组件30包括沿着由所述衬底10指向所述发光层50方向层叠设置的缓冲层31、第一渐变层33、腐蚀截止层35、第二渐变层37、欧姆接触层39、第三渐变层41、电流扩展层43、第一限制层45以及第一波导层47。所述第一渐变层33用于使所述缓冲层31的掺杂浓度和所述腐蚀截止层35的掺杂浓度连续，所述第二渐变层37用于使所述腐蚀截止层35的掺杂浓度和所述欧姆接触层39的掺杂浓度连续，所述第三渐变层41用于使所述欧姆接触层39的掺杂浓度和所述电流扩展层43的掺杂浓度连续。
可以理解的是，所述缓冲层31和所述腐蚀截止层35之间的掺杂浓度差、所述腐蚀截止层35和所述欧姆接触层39之间的掺杂浓度差以及所述欧姆接触层39与所述电流扩展层43之间的掺杂浓度差影响了载流子的移动，使得所述发光芯片外延结构100的串联电阻较大。
在示例性实施方式中，请参阅图2，图2为本申请实施例公开的掺杂浓度-生长时间曲线的坐标系图。将所述缓冲层31的掺杂浓度定义为第一掺杂浓度N1，将所述腐蚀截止层35的掺杂浓度定义为第二掺杂浓度N2，将所述欧姆接触层39的掺杂浓度定义为第三掺杂浓度N3，将所述电流扩展层43的掺杂浓度定义为第四掺杂浓度N4。其中，所述第二掺杂浓度N2大于所述第一掺杂浓度N1，所述第三掺杂浓度N3大于所述第二掺杂浓度N2，所述第四掺杂浓度N4小于所述第一掺杂浓度N1，且N3≥N1+N2+N4。
也即为，所述第一渐变层33的掺杂浓度由所述缓冲层31指向所述腐蚀截止层35的方向逐渐增大，所述第二渐变层37的掺杂浓度由所述腐蚀截止层35指向所述欧姆接触层39的方向逐渐增大，所述第三渐变层41的掺杂浓度由所述欧姆接触层39指向所述电流扩展层43的方向逐渐减小。
可以理解的是，所述欧姆接触层39需要和第一芯片电极形成欧姆接触，因此，所述欧姆接触层39的掺杂浓度最高，即所述第三掺杂浓度N3最大。
在示例性实施方式中，所述第一掺杂浓度N1、所述第二掺杂浓度N2、所述第三掺杂浓度N3以及所述第四掺杂浓度N4均在1E18cm-3至1E19cm-3范围内，例如，1.13E18cm-3、1.33E18cm-3、1.5E18cm-3、1.86E18cm-3、1E19cm-3、或其他数值。
在示例性实施方式中，所述第一渐变层33的掺杂浓度由所述第一掺杂浓度N1向所述第二掺杂浓度N2线性变化，所述第二渐变层37的掺杂浓度由所述第二掺杂浓度N2向所述第三掺杂浓度N3线性变化，所述第三渐变层41的掺杂浓度由所述第三掺杂浓度N3向所述第四掺杂浓度N4线性变化。其中，线性变化指的是该渐变层的厚度与其相对两侧掺杂的浓度差为线性关系。
在其他实施例中，所述第一渐变层33的掺杂浓度由所述第一掺杂浓度N1向所述第二掺杂浓度N2非线性变化或阶梯式变化，所述第二渐变层37的掺杂浓度由所述第二掺杂浓度N2向所述第三掺杂浓度N3线性变化或阶梯式变化，所述第三渐变层41的掺杂浓度由所述第三掺杂浓度N3向所述第四掺杂浓度N4线性变化或阶梯式变化。
可以理解的是，所述第一渐变层33的掺杂浓度的渐变方式包括线性变化、非线性变化和阶梯式变化中的一种或多种组合，所述第二渐变层37的掺杂浓度的渐变方式包括线性变化、非线性变化或阶梯式变化中的一种或多种组合，所述第三渐变层41的掺杂浓度的渐变方式包括线性变化、非线性变化或阶梯式变化中的一种或多种组合。本申请对此不作具体限制。
综上所述，本申请实施例提供的发光芯片外延结构100包括依次层叠设置的衬底10、第一半导体组件30、发光层50以及第二半导体组件70，所述第一半导体组件30包括依次层叠设置于所述衬底10上的缓冲层31、第一渐变层33、腐蚀截止层35、第二渐变层37、欧姆接触层39、第三渐变层41、电流扩展层43、第一限制层45以及第一波导层47。所述第一渐变层33使所述缓冲层31的掺杂浓度和所述腐蚀截止层35的掺杂浓度连续，所述第二渐变层37使所述腐蚀截止层35的掺杂浓度和所述欧姆接触层39的掺杂浓度连续，所述第三渐变层41使所述欧姆接触层39的掺杂浓度和所述电流扩展层43的掺杂浓度连续。因此，所述第一渐变层33、所述第二渐变层37和所述第三渐变层41使得所述第一半导体组件30的各掺杂层之间掺杂更连续，降低了各掺杂层之间的串联电阻，进而降低了所述发光芯片外延结构100的工作电压，同时也降低了所述发光芯片外延结构100的功耗。
在本申请实施方式中，所述第一半导体组件30可为N（Negative）型半导体，所述第二半导体组件70可为P（Positive）型半导体。
可以理解的是，所述缓冲层31用于避免所述衬底10与所述第一半导体组件30出现晶格失配，有利于第一半导体组件30的生成。所述缓冲层31还可用于消除所述衬底10的表面缺陷对所述第一半导体组件30的影响，为后续形成各掺杂层提供了平整的界面，提高了所述发光芯片外延结构100的质量。所述腐蚀截止层35用于在制作所述发光芯片外延结构100的蚀刻工艺中作为保护层，以避免所述衬底10以及所述缓冲层31被蚀刻液腐蚀。所述欧姆接触层39用于与第一芯片电极（图未示）形成欧姆接触，有利于电流的输入或输出。所述电流扩展层43用于使经过所述电流扩展层43的电流尽可能均匀地分布，极大地提高了所述发光层50的发光效率。所述第一限制层45用于为所述发光层50提供电子，同时防止所述发光层50内的载流子（电子和空穴）向外运动，让更多的载流子（电子和空穴）在所述发光层50内复合产生光子，以保证发光量。所述第一波导层47用于阻止杂质扩散进所述发光层50内。
在示例性实施方式中，制成所述第一半导体组件30的掺杂源可为硅烷（SiH4）。
在示例性实施方式中，所述衬底10可为砷化镓（GaAs）衬底。在其他实施例中，所述衬底10还可为蓝宝石衬底、硅衬底、氮化镓（GaN）衬底、磷化镓（GaP）衬底、砷化铝镓（AlGaAs）衬底或磷化铝镓铟（AlGaInP）衬底等。
在示例性实施方式中，所述第一渐变层33可为砷化硅（SiAs）和硅层，所述第二渐变层37可为磷化硅（SiP）和硅层，所述第三渐变层41可为砷化硅和硅层。
在示例性实施方式中，所述缓冲层31可为掺杂Si的GaAs层，其厚度可为100nm至300nm，例如，100nm、150nm、170nm、200nm、240nm、300nm、或其他数值，本申请对此不作具体限制。
在示例性实施方式中，所述腐蚀截止层35可为掺杂Si的Ga x1In 1-x1P层，其中，x1大于0且小于1，例如，0.05、0.1、0.45、0.8、0.99、或其他数值，本申请对此不作具体限制。所述腐蚀截止层35的厚度可为50nm至300nm，例如，50nm、70nm、100nm、180nm、210nm、260nm、300nm、或其他数值，本申请对此不作具体限定。
在示例性实施方式中，所述欧姆接触层39可为掺杂Si的GaAs层，其厚度可为10nm至150nm，例如，10nm、30nm、50nm、90nm、120nm、150nm、或其他数量值，本申请对此不作具体限制。
在示例性实施方式中，所述电流扩展层43可为掺杂Si的Al x2Ga 1-x2InP层，其中，x2大于0且小于1，例如，0.04、0.10、0.15、0.40、0.60、0.81、0.99、或其他数值，本申请对此不作具体限制。所述电流扩展层43的厚度可为1000nm至3000nm，例如，1000nm、1250nm、1870nm、2400nm、3000nm、或其他数值，本申请对此不作具体限制。
在示例性实施方式中，所述第一限制层45可为掺杂Si的Al x3In 1-x3P层，其中，x3大于0且小于1，例如，0.09、0.10、0.20、0.25、0.47、0.71、0.96、或其他数值，本申请对此不作具体限制。所述第一限制层45的厚度可为250nm至450nm，例如，250nm、280nm、300nm、315nm、380nm、450nm、或其他数值，本申请对此不作具体限制。
在示例性实施方式中，所述第一波导层47可为Al x4Ga 1-x4InP层，其中，x4大于0且小于1，例如，0.03、0.08、0.14、0.20、0.39、0.50、0.67、0.80、0.95、或其他数值，本申请对此不作具体限制。所述第一波导层47的厚度可为70nm至150nm，例如，70nm、81nm、105nm、110nm、135nm、150nm、或其他数值，本申请对此不作具体限制。
在本申请实施方式中，所述发光层50可为量子阱层，所述发光层50用于对电子和空穴进行辐射复合，并发光。
在示例性实施方式中，所述发光层50可为Al z1Ga 1-z1InP层，其中，z1大于0且小于1，例如，0.05、0.10、0.20、0.23、0.41、0.50、0.66、0.98、或其他数值，本申请对此不作具体限制。所述发光层50的厚度可为100nm至300nm，例如，100nm、130nm、170nm、200nm、240nm、280nm、300nm、或其他数值、本申请对此不作具体限制。
在本申请实施例中，所述第二半导体组件70包括沿着由所述第一半导体组件30指向所述发光层50方向层叠设置的第二波导层71、第二限制层73、过渡层75以及窗口层77，即所述第二半导体组件70包括层叠设置于所述发光层50背对所述第一波导层47表面上的第二波导层71、第二限制层73、过渡层75以及窗口层77。也即为，所述第二波导层71位于所述发光层50背对所述第一波导层47的一侧，并与所述发光层50相贴合，所述第二限制层73位于所述第二波导层71和所述过渡层75之间，所述窗口层77位于所述过渡层75背对所述第二限制层73的表面上。
在本申请实施例中，所述第二波导层71用于阻止杂质扩散进所述发光层50内。所述第二限制层73用于为所述发光层50提供空穴，同时防止所述发光层50内的载流子（电子和空穴）向外运动，让更多的载流子（电子和空穴）在所述发光层50内复合产生光子，以保证发光量。所述过渡层75用于为所述窗口层77提供生长表面，且有利于所述窗口层77的长晶。所述窗口层77用于使经过所述窗口层77的电流尽可能均匀地分布，极大地提高了所述发光层50的发光效率，同时也用于第二芯片电极形成欧姆接触，有利于电流的输入或输出。
在示例性实施方式中，所述第二半导体组件70的掺杂源可为镁（Mg）源。
在示例性实施方式中，所述第二波导层71可为Al x5Ga 1-x5InP层，其中，x5大于0且小于1，例如，0.03、0.10、0.14、0.20、0.30、0.39、0.50、0.67、0.80、0.95、或其他数值，本申请对此不作具体限制。所述第二波导层71的厚度可为70nm至150nm，例如，70nm、81nm、90nm、100nm、105nm、120nm、135nm、150nm、或其他数值，本申请对此不作具体限制。
在示例性实施方式中，所述第二限制层73可为掺杂Mg的Al x6In 1-x6P层，其中，x6大于0且小于1，例如，0.05、0.10、0.21、0.40、0.50、0.57、0.68、0.80、0.90、0.96、或其他数值，本申请对此不作具体限制。所述第二限制层73的厚度可为250nm至450nm，例如，250nm、270nm、300nm、325nm、375nm、400nm、450nm、或其他数值，本申请对此不作具体限制。
在示例性实施方式中，所述过渡层75可为掺杂Mg的(Al x7Ga 1-x7) yIn 1-yP层，其中，x7大于0且小于1，例如，0.03、0.10、0.15、0.21、0.40、0.47、0.60、0.73、0.84、0.95、或其他数值，本申请对此不作具体限制；y大于0且小于1，例如，0.03、0.10、0.19、0.30、0.37、0.50、0.63、0.80、0.89、0.90、0.95、或其他数值，本申请对此不作具体限制。所述过渡层75的厚度可为10nm至150nm，例如，10nm、25nm、50nm、57nm、100nm、106nm、120nm、145nm、150nm、或其他数值，本申请对此不作具体限制。
在示例性实施方式中，所述窗口层77可为掺杂Mg的磷化镓（GaP）层，其厚度可为3000nm至8000nm，例如，3000nm、4500nm、5500nm、6800nm、7400nm、8000nm、或其他数值，本申请对此不作具体限制。
综上所述，本申请实施例提供的发光芯片外延结构100包括依次层叠设置的衬底10、第一半导体组件30、发光层50以及第二半导体组件70，所述第一半导体组件30包括依次层叠设置于所述衬底10上的缓冲层31、第一渐变层33、腐蚀截止层35、第二渐变层37、欧姆接触层39、第三渐变层41、电流扩展层43、第一限制层45以及第一波导层47。所述第一渐变层33使所述缓冲层31的掺杂浓度和所述腐蚀截止层35的掺杂浓度连续，所述第二渐变层37使所述腐蚀截止层35的掺杂浓度和所述欧姆接触层39的掺杂浓度连续，所述第三渐变层41使所述欧姆接触层39的掺杂浓度和所述电流扩展层43的掺杂浓度连续。所述缓冲层31用于避免所述衬底10与所述第一半导体组件30出现晶格失配，还可消除所述衬底10的表面缺陷对所述第一半导体组件30的影响，为后续形成各掺杂层提供了平整的界面，提高了所述发光芯片外延结构100的质量。所述腐蚀截止层35在制作所述发光芯片外延结构100的蚀刻工艺中作为保护层，以避免所述衬底10以及所述缓冲层31被蚀刻液腐蚀。所述欧姆接触层39与第一芯片电极形成欧姆接触，有利于电流的输入或输出。所述电流扩展层43使经过所述电流扩展层43的电流尽可能均匀地分布，极大地提高了所述发光层50的发光效率。所述第一限制层45用于为所述发光层50提供电子，同时防止所述发光层50内的载流子（电子和空穴）向外运动，让更多的载流子（电子和空穴）在所述发光层50内复合产生光子，以保证发光量。所述第一波导层47阻止杂质扩散进所述发光层50内。因此，所述第一渐变层33、所述第二渐变层37和所述第三渐变层41使得所述第一半导体组件30的各掺杂层之间掺杂更连续，降低了各掺杂层之间的串联电阻，进而降低了所述发光芯片外延结构100的工作电压，同时也降低了所述发光芯片外延结构100的功耗。
基于同样的构思，本申请实施例提供一种发光芯片。请参阅图3，图3为本申请实施例公开的一种发光芯片的层结构示意图。所述发光芯片150包括第一芯片电极101、第二芯片电极103以及上述的发光芯片外延结构100，所述第一芯片电极101与所述第一半导体组件30电连接，所述第二芯片电极103与所述第二半导体组件70电连接。
在本申请实施方式中，所述第一芯片电极101与所述欧姆接触层39电连接，所述第二芯片电极103与所述窗口层77电连接。
在示例性实施方式中，所述发光芯片150可为Mini LED芯片或Micro LED芯片。
在示例性实施方式中，所述发光芯片150可为磷化铝镓铟（AlGaInP）系发光芯片。
综上所述，本申请实施例提供的发光芯片150包括第一芯片电极101、第二芯片电极103以及发光芯片外延结构100，所述发光芯片外延结构100包括依次层叠设置的衬底10、第一半导体组件30、发光层50以及第二半导体组件70，所述第一半导体组件30包括依次层叠设置于所述衬底10上的缓冲层31、第一渐变层33、腐蚀截止层35、第二渐变层37、欧姆接触层39、第三渐变层41、电流扩展层43以及第一限制层45。所述第一渐变层33用于使所述缓冲层31的掺杂浓度和所述腐蚀截止层35的掺杂浓度连续，所述第二渐变层37用于使所述腐蚀截止层35的掺杂浓度和所述欧姆接触层39的掺杂浓度连续，所述第三渐变层41用于使所述欧姆接触层39的掺杂浓度和所述电流扩展层43的掺杂浓度连续。因此，所述第一渐变层33、所述第二渐变层37和所述第三渐变层41使得所述第一半导体组件30的各掺杂层之间掺杂更连续，降低了各掺杂层之间的串联电阻，进而降低了所述发光芯片外延结构100的工作电压，同时也降低了所述发光芯片外延结构100的功耗。
基于同样的构思，本申请实施例提供一种显示面板。请参阅图4，图4为本申请实施例公开的一种显示面板的层结构示意图。本申请实施例提供的显示面板500包括驱动基板200以及多个上述的发光芯片150，多个所述发光芯片150设置在所述驱动基板200的同一侧，并与所述驱动基板200电连接，所述驱动基板200用于向多个所述发光芯片150传输电信号以控制多个所述发光芯片150发光。由于图1至图3所示的实施例已对所述发光芯片外延结构100和所述发光芯片150进行了较为详细的阐述，在此不再赘述。
可以理解地，所述显示面板可用于包含诸如个人数字助理（Personal Digital Assistant，PDA）和/或音乐播放器功能的电子设备，诸如手机、平板电脑、具备无线通讯功能的可穿戴电子设备（如智能手表）等。上述电子设备也可以是其它电子装置，诸如具有触敏表面（例如触控面板）的膝上型计算机（Laptop）等。在一些实施例中，所述电子设备可以具有通信功能，即可以通过2G（第二代手机通信技术规格）、3G（第三代手机通信技术规格）、4G（第四代手机通信技术规格）、5G（第五代手机通信技术规格）或W-LAN（无线局域网）或今后可能出现的通信方式与网络建立通信。为简明起见，对此本申请实施例不做进一步限定。
综上所述，本申请实施例提供的显示面板500包括驱动基板200和发光芯片150，所述发光芯片150包括第一芯片电极101、第二芯片电极103以及发光芯片外延结构100，所述发光芯片外延结构100包括依次层叠设置的衬底10、第一半导体组件30、发光层50以及第二半导体组件70，所述第一半导体组件30包括依次层叠设置于所述衬底10上的缓冲层31、第一渐变层33、腐蚀截止层35、第二渐变层37、欧姆接触层39、第三渐变层41、电流扩展层43以及第一限制层45。所述第一渐变层33用于使所述缓冲层31的掺杂浓度和所述腐蚀截止层35的掺杂浓度连续，所述第二渐变层37用于使所述腐蚀截止层35的掺杂浓度和所述欧姆接触层39的掺杂浓度连续，所述第三渐变层41用于使所述欧姆接触层39的掺杂浓度和所述电流扩展层43的掺杂浓度连续。因此，所述第一渐变层33、所述第二渐变层37和所述第三渐变层41使得所述第一半导体组件30的各掺杂层之间掺杂更连续，降低了各掺杂层之间的串联电阻，进而降低了所述发光芯片外延结构100的工作电压，同时也降低了所述发光芯片外延结构100的功耗。
基于同样的构思，本申请实施例还提供一种显示装置。请参阅图5，图5为本申请实施例公开的一种显示装置的层结构示意图。本申请实施例提供的显示装置1000包括玻璃盖板700以及上述的显示面板500，所述玻璃盖板700罩设在所述显示面板500的出光侧，所述玻璃盖板700用于保护所述显示面板500，避免所述显示面板500受到外界空气、水汽或灰尘等杂质的影响进而造成所述显示面板500的使用寿命减少或损坏。
由于图1至图4所示的实施例已对所述显示面板500、所述发光芯片150以及所述发光芯片外延结构100进行了较为详细的阐述，在此不再赘述。
其中，所述显示装置包括但不局限于：Mini LED面板、Mirco LED面板、手机、平板电脑、导航仪、显示器等任何具有显示功能的电子设备或者部件，本申请对此不作具体限制。根据本申请的实施例，该显示装置的具体种类不受特别的限制，本领域技术人员可根据应用该显示装置的具体使用要求进行相应地设计，在此不再赘述。
在其中一个实施例中，所述显示装置还包括电源板、高压板、按键控制板等其他必要的部件和组成，本领域技术人员可根据该显示装置的具体类型和实际功能进行相应地补充，在此不再赘述。
综上所述，本申请实施例提供的显示装置1000包括玻璃盖板700和显示面板500，所述显示面板500包括驱动基板200和发光芯片150，所述发光芯片150包括第一芯片电极101、第二芯片电极103以及发光芯片外延结构100，所述发光芯片外延结构100包括依次层叠设置的衬底10、第一半导体组件30、发光层50以及第二半导体组件70，所述第一半导体组件30包括依次层叠设置于所述衬底10上的缓冲层31、第一渐变层33、腐蚀截止层35、第二渐变层37、欧姆接触层39、第三渐变层41、电流扩展层43、第一限制层45以及第一波导层47。所述第一渐变层33用于使所述缓冲层31的掺杂浓度和所述腐蚀截止层35的掺杂浓度连续，所述第二渐变层37用于使所述腐蚀截止层35的掺杂浓度和所述欧姆接触层39的掺杂浓度连续，所述第三渐变层41用于使所述欧姆接触层39的掺杂浓度和所述电流扩展层43的掺杂浓度连续。因此，所述第一渐变层33、所述第二渐变层37和所述第三渐变层41使得所述第一半导体组件30的各掺杂层之间掺杂更连续，降低了各掺杂层之间的串联电阻，进而降低了所述发光芯片外延结构100的工作电压，同时也降低了所述发光芯片外延结构100的功耗。
基于同样的构思，本申请实施例提供一种发光芯片外延结构的制作方法，用于制作上述的发光芯片外延结构100。请参阅图6，图6为本申请实施例公开的一种发光芯片外延结构的制作方法的流程示意图。在本申请实施例中，所述制作方法用于制作上述图1和图2所示的发光芯片外延结构100，由于上述实施例中已对发光芯片外延结构100详细阐述，本实施例制作方法所涉及发光芯片外延结构100的描述可以直接参考上述实施例，在此不再赘述。如图6所示，本申请实施例提供的发光芯片外延结构的制作方法至少可以包括以下步骤。
S410、提供一衬底。
具体为，提供一衬底10，可用有机溶剂和酸液清洗所述衬底10，还可以对所述衬底10进行高温处理，以清洁所述衬底10的表面。
在示例性实施方式中，所述衬底10可为GaAs衬底，所述衬底10给后续的外延结构提供了生长的表面。
S420、在所述衬底上生成第一半导体组件，其中，所述第一半导体组件包括依次层叠设置于所述衬底上的缓冲层、第一渐变层、腐蚀截止层、第二渐变层、欧姆接触层、第三渐变层、电流扩展层、第一限制层以及第一波导层。
S430、在所述第一半导体组件背对所述衬底的表面上形成发光层。
在示例性实施方式中，所述发光层50可为Alz1Ga1-z1InP层，其中，z1大于0且小于1，所述发光层50的厚度可为100nm至300nm。
S440、在所述发光层背对所述第一半导体组件的表面上生成第二半导体组件。
具体为，所述第二半导体组件70包括依次层叠与所述发光层50上的第二波导层71、第二限制层73、过渡层75以及窗口层77。
在示例性实施方式中，所述第二波导层71可为Al x5Ga 1-x5InP层，其中，x5大于0且小于1，所述第二波导层71的厚度可为70nm至150nm。所述第二限制层73可为掺杂Mg的Al x6In 1-x6P层，其中，x3大于0且小于1，所述第二限制层73的厚度可为250nm至450nm，所述过渡层75可为掺杂Mg的(Al x7Ga 1-x7) yIn 1-yP层，其中，x7大于0且小于1，所述过渡层75的厚度可为10nm至150nm。所述窗口层77可为掺杂Mg的磷化镓（GaP）层，其厚度可为3000nm至8000nm。
请参阅图7，图7为本申请实施例公开的一种发光芯片外延结构的制作方法中步骤S420的流程示意图。请结合图1所示，在本申请实施例中，所述步骤S420至少可以包括以下步骤。
S421、通入所述缓冲层对应的Ⅲ族源、所述缓冲层对应的Ⅴ族源以及掺杂源，以在所述衬底上生成所述缓冲层。
具体为，将所述衬底10放置于反应腔内，设定反应腔内的温度为690至730℃、压力为50mbar，向反应腔中同时通入砷烷、三甲基镓以及所述第一掺杂浓度N1的硅烷，其中，所述三甲基镓为Ⅲ族源，所述砷烷为Ⅴ族源，三甲基镓以氢气为载体通入到反应腔中，所述硅烷为掺杂源。也即为，向反应腔中同时通入砷烷、三甲基镓以及第一掺杂浓度N1的硅烷，以在所述衬底10上生成所述缓冲层31。在本申请实施例中，所述反应腔内的温度可为：690℃、700℃、715℃、720℃、730℃、或其他数值。
在示例性实施方式中，所述缓冲层31可为掺杂Si的GaAs层，其厚度可为100nm至300nm，所述缓冲层31与所述衬底10的晶格相匹配，避免了所述缓冲层31与所述衬底10错位，有利于后续外延结构的生成。
S422、中断生长所述缓冲层对应的Ⅲ族源，保持生长所述缓冲层对应的Ⅴ族源通入，掺杂源由生长所述缓冲层对应的掺杂浓度渐变至生长所述腐蚀截止层的掺杂浓度，以在所述缓冲层背对所述衬底的表面上生成所述第一渐变层。
具体为，在所述缓冲层31生长完成后，关闭三甲基镓的通入，保持硅烷和砷烷的通入。也即为，保持硅烷和砷烷的通入，且硅烷的浓度由所述第一掺杂浓度N1渐变为第二掺杂浓度N2，以在所述缓冲层31背对所述衬底10的表面上生成第一渐变层33。
可以理解的是，在生长所述第一渐变层33时，通入的硅烷浓度增加，部分硅烷与砷烷反应生成砷化硅，部分硅烷裂解生成硅，故所述第一渐变层33为砷化硅和硅层。由于硅烷的通入量是逐渐增加的，在所述第一渐变层33中，硅的浓度是逐渐增加的。
在示例性实施例中，所述第二掺杂浓度N2大于所述第一掺杂浓度N1，所述第一掺杂浓度N1渐变为第二掺杂浓度N2的过程为线性变化。所述第一渐变层33可为砷化硅（SiAs）和硅层，即硅烷与砷烷反应生成砷化硅，部分硅烷裂解生成硅。
S423、通入所述腐蚀截止层对应的Ⅲ族源、所述腐蚀截止层对应的Ⅴ族源以及掺杂源，以在所述第一渐变层背对所述缓冲层的表面上生成所述腐蚀截止层。
具体为，向反应腔中同时通入磷烷、三甲基镓、三甲基铟以及所述第二掺杂浓度N2的硅烷，以在所述第一渐变层33背对所述缓冲层的表面上生成所述腐蚀截止层35。其中，所述磷烷为Ⅴ族源，所述三甲基镓与所述三甲基铟为Ⅲ族源，所述硅烷为掺杂源。
在示例性实施方式中，所述腐蚀截止层35可为掺杂Si的Ga x1In 1-x1P层，其中，x1大于0且小于1。所述腐蚀截止层35的厚度可为50nm至300nm。
S424、中断生长所述腐蚀截止层对应的Ⅲ族源，保持生长所述腐蚀截止层对应的Ⅴ族源通入，掺杂源由生长所述腐蚀截止层对应的掺杂浓度渐变至生长所述欧姆接触层的掺杂浓度，以在所述腐蚀截止层背对所述第一渐变层的表面上生成所述第二渐变层。
具体为，在所述腐蚀截止层35生长完成后，关闭三甲基镓和三甲基铟的通入，保持硅烷和磷烷的通入。也即为，保持硅烷和磷烷的通入，且硅烷浓度由第二掺杂浓度N2渐变到第三掺杂浓度N3，以在所述腐蚀截止层35背对所述第一渐变层33的表面上生成所述第二渐变层37。
可以理解的是，在生长所述第二渐变层37时，通入的硅烷浓度增加，部分硅烷与磷烷反应生成磷化硅，部分硅烷裂解生成硅，故所述第一渐变层为磷化硅和硅层。由于硅烷的通入量是逐渐增加的，在所述第二渐变层37中，硅的浓度是逐渐增加的。
在示例性实施方式中，所述第三掺杂浓度N3大于所述第二掺杂浓度N2，所述第二掺杂浓度N2渐变为第三掺杂浓度N3的过程为线性变化。所述第二渐变层37可为磷化硅（SiP）和硅层，即硅烷与磷烷反应生成磷化硅，部分硅烷裂解生成硅。
S425、通入所述欧姆接触层对应的Ⅲ族源、所述欧姆接触层对应的Ⅴ族源以及掺杂源，以在所述第二渐变层背对所述腐蚀截止层的表面上生成所述欧姆接触层。
具体为，向反应腔中同时通入砷烷、三甲基镓以及所述第三掺杂浓度N3的硅烷，以在所述第二渐变层37背对所述腐蚀截止层35的表面上生成所述欧姆接触层39。其中，所述砷烷为Ⅴ族源，所述三甲基镓为Ⅲ族源，所述硅烷为掺杂源。
在示例性实施方式中，所述欧姆接触层39可为掺杂Si的GaAs层，其厚度可为10nm至150nm。
S426、中断生长所述欧姆接触层对应的Ⅲ族源，保持生长所述欧姆接触层对应的Ⅴ族源通入，掺杂源由生长所述欧姆接触层对应的掺杂浓度渐变至生长所述电流扩展层的掺杂浓度，以在所述欧姆接触层背对所述第二渐变层的表面上生成所述第三渐变层。
具体为，在所述欧姆接触层39生长完成后，关闭三甲基镓的通入，保持硅烷和砷烷的通入。也即为，保持硅烷和砷烷的通入，且硅烷的浓度由所述第三掺杂浓度N3渐变到第四掺杂浓度N4，以在所述欧姆接触层39背对所述第二渐变层37的表面上生成所述第三渐变层41。
可以理解的是，在生长所述第三渐变层41时，部分硅烷与砷烷反应生成砷化硅，部分硅烷裂解生成硅，故所述第三渐变层41为砷化硅和硅层。由于硅烷的通入量是逐渐减少的，在所述第三渐变层41中，硅的浓度是逐渐减少的。
在示例性实施方式中，所述第四掺杂浓度N4小于所述第三掺杂浓度N3，所述第三掺杂浓度N3渐变为第二掺杂浓度N2的过程为线性变化。所述第三渐变层41可为砷化硅（SiAs）和硅层，即硅烷与砷烷反应生成砷化硅，部分硅烷裂解生成硅。
S427、在所述第三渐变层背对所述欧姆接触层的表面上生成所述电流扩展层。
具体为，向反应腔中同时通入磷烷、三甲基铝、三甲基镓、三甲基铟以及所述第四掺杂浓度N4的硅烷，以在所述第三渐变层41背对所述欧姆接触层39的表面上生成所述电流扩展层43。其中，所述磷烷为Ⅴ族源，所述三甲基铝、所述三甲基镓和三甲基铟为Ⅲ族源，硅烷为掺杂源。
在示例性实施方式中，所述电流扩展层43可为掺杂Si的Al x2Ga 1-x2InP层，其中，x2大于0且小于1。所述电流扩展层43的厚度可为1000nm至3000nm。
S428、在所述电流扩展层背对所述第三渐变层的表面上生成所述第一限制层。
具体为，向反应腔中通入同时通入磷烷、三甲基铝、三甲基铟以及硅烷，以在所述电流扩展层43背对所述第三渐变层41的表面上生成所述第一限制层45。其中，所述磷烷为Ⅴ族源，所述三甲基铝和所述三甲基铟为Ⅲ族源，所述硅烷为掺杂源。
在示例性实施方式中，所述第一限制层45可为掺杂Si的Al x3In 1-x3P层，其中，x3大于0且小于1。所述第一限制层45的厚度可为250nm至450nm。
S429、在所述第一限制层背对所述电流扩展层表面上生成所述第一波导层。
具体为，向反应腔中同时通入磷烷、三甲基铝、三甲基镓以及三甲基铟，以在所述第一限制层45背对所述电流扩展层43表面上生成所述第一波导层47。其中，所述第一波导层47可为Al x4Ga 1-x4InP层，其中，x4大于0且小于1。所述第一波导层47的厚度可为70nm至150nm。
在本申请实施方式中，在步骤S421至步骤S429中，通入的Ⅴ族源的摩尔量与Ⅲ族源摩尔量的比值为150至250，即Ⅴ/Ⅲ为150-250。其中，Ⅴ族源包括三甲基铝、三甲基镓和三甲基铟，Ⅲ族源包括砷烷和磷烷。在步骤S421至步骤S429中，通入的Ⅲ族源的流量范围可为30sccm至100sccm，例如，30sccm、41sccm、67sccm、80sccm、100sccm、或其他数值。其中，sccm为标准公升每分钟流量值。
在本申请实施方式中，所述发光芯片外延结构100的制作方法可为化学气相沉积（Chemical Vapor Deposition，CVD）或物理气相沉积（Physical Vapor Deposition，PVD）。其中，CVD是指化学气体或蒸汽在基质表面反应合成涂层或纳米材料的方法，PVD是指在真空条件下采用物理方法将材料源(固体或液体)表面气化成气态原子或分子，或部分电离成离子，并通过低压气体(或等离子体)过程，在基体表面沉积薄膜的技术。
综上所述，本申请实施例提供的发光芯片外延结构的制作方法至少包括：提供一衬底10；在所述衬底10上形成第一半导体组件30，其中，所述第一半导体组件30包括依次层叠设置于所述衬底10上的缓冲层31、第一渐变层33、腐蚀截止层35、第二渐变层37、欧姆接触层39、第三渐变层41、电流扩展层43、第一限制层45以及第一波导层47；在所述第一半导体组件30背对所述衬底10的表面上形成发光层50；在所述发光层50背对所述第一半导体组件30的表面上形成第二半导体组件70。所述第一渐变层33用于使所述缓冲层31的掺杂浓度和所述腐蚀截止层35的掺杂浓度连续，所述第二渐变层37用于使所述腐蚀截止层35的掺杂浓度和所述欧姆接触层39的掺杂浓度连续，所述第三渐变层41用于使所述欧姆接触层39的掺杂浓度和所述电流扩展层43的掺杂浓度连续。因此，所述第一渐变层33、所述第二渐变层37和所述第三渐变层41使得所述第一半导体组件30的各掺杂层之间掺杂更连续，降低了各掺杂层之间的串联电阻，进而降低了所述发光芯片外延结构100的工作电压，同时也降低了所述发光芯片外延结构100的功耗。
应当理解的是，本申请的应用不限于上述的举例，对本领域普通技术人员来说，可以根据上述说明加以改进或变换，所有这些改进和变换都应属于本申请所附权利要求的保护范围。

Claims (20)

  1. 一种发光芯片外延结构，其中，包括依次层叠设置的第一半导体组件、发光层以及第二半导体组件，其中，所述第一半导体组件包括依次层叠设置的缓冲层、第一渐变层、腐蚀截止层、第二渐变层、欧姆接触层、第三渐变层、电流扩展层、第一限制层以及第一波导层，所述第一渐变层使所述缓冲层的掺杂浓度和所述腐蚀截止层的掺杂浓度连续，所述第二渐变层使所述腐蚀截止层的掺杂浓度和所述欧姆接触层的掺杂浓度连续，所述第三渐变层使所述欧姆接触层的掺杂浓度和所述电流扩展层的掺杂浓度连续。
  2. 如权利要求1所述的发光芯片外延结构，其中，所述第一渐变层的掺杂浓度的渐变方式包括线性变化、非线性变化和阶梯式变化中的任意一种或多种组合，所述第二渐变层的掺杂浓度的渐变方式包括线性变化、非线性变化或阶梯式变化中的任意一种或多种组合，所述第三渐变层的掺杂浓度的渐变方式包括线性变化、非线性变化或阶梯式变化中的任意一种或多种组合。
  3. 如权利要求1所述的发光芯片外延结构，其中，所述第一渐变层的掺杂浓度由所述缓冲层指向所述腐蚀截止层的方向逐渐增大，所述第二渐变层的掺杂浓度由所述腐蚀截止层指向所述欧姆接触层的方向逐渐增大，所述第三渐变层的掺杂浓度由所述欧姆接触层指向所述电流扩展层的方向逐渐减小。
  4. 如权利要求1所述的发光芯片外延结构，其中，所述第一渐变层为砷化硅和硅层，所述第二渐变层为磷化硅和硅层，所述第三渐变层为砷化硅和硅层。
  5. 如权利要求1所述的发光芯片外延结构，其中，所述缓冲层为砷化镓层，所述缓冲层的厚度为100nm至300nm，所述腐蚀截止层为Ga x1In 1-x1P层，所述腐蚀截止层的厚度为50nm至300nm，所述欧姆接触层为砷化镓层，所述欧姆接触层的厚度为10nm至150nm，所述电流扩展层为Al x2Ga 1-x2InP层，所述电流扩展层的厚度为1000nm至3000nm，所述第一限制层为Al x3In 1-x3P层，所述第一限制层的厚度为250nm至450nm，所述第一波导层为Al x4Ga 1-x4InP层，所述第一波导层的厚度为70nm至150nm，其中，x1、x2、x3和x4均大于0且小于1。
  6. 一种发光芯片，其中，包括第一芯片电极、第二芯片电极以及发光芯片外延结构，所述发光芯片外延结构包括依次层叠设置的第一半导体组件、发光层以及第二半导体组件，所述第一芯片电极与所述第一半导体组件电连接，所述第二芯片电极与所述第二半导体组件电连接，所述第一半导体组件包括依次层叠设置的缓冲层、第一渐变层、腐蚀截止层、第二渐变层、欧姆接触层、第三渐变层、电流扩展层、第一限制层以及第一波导层，所述第一渐变层使所述缓冲层的掺杂浓度和所述腐蚀截止层的掺杂浓度连续，所述第二渐变层使所述腐蚀截止层的掺杂浓度和所述欧姆接触层的掺杂浓度连续，所述第三渐变层使所述欧姆接触层的掺杂浓度和所述电流扩展层的掺杂浓度连续。
  7. 如权利要求6所述的发光芯片，其中，所述第一渐变层的掺杂浓度的渐变方式包括线性变化、非线性变化和阶梯式变化中的任意一种或多种组合，所述第二渐变层的掺杂浓度的渐变方式包括线性变化、非线性变化或阶梯式变化中的任意一种或多种组合，所述第三渐变层的掺杂浓度的渐变方式包括线性变化、非线性变化或阶梯式变化中的任意一种或多种组合。
  8. 如权利要求6所述的发光芯片，其中，所述第一渐变层的掺杂浓度由所述缓冲层指向所述腐蚀截止层的方向逐渐增大，所述第二渐变层的掺杂浓度由所述腐蚀截止层指向所述欧姆接触层的方向逐渐增大，所述第三渐变层的掺杂浓度由所述欧姆接触层指向所述电流扩展层的方向逐渐减小。
  9. 如权利要求6所述的发光芯片，其中，所述第一渐变层为砷化硅和硅层，所述第二渐变层为磷化硅和硅层，所述第三渐变层为砷化硅和硅层。
  10. 如权利要求6所述的发光芯片，其中，所述缓冲层为砷化镓层，所述缓冲层的厚度为100nm至300nm，所述腐蚀截止层为Ga x1In 1-x1P层，所述腐蚀截止层的厚度为50nm至300nm，所述欧姆接触层为砷化镓层，所述欧姆接触层的厚度为10nm至150nm，所述电流扩展层为Al x2Ga 1-x2InP层，所述电流扩展层的厚度为1000nm至3000nm，所述第一限制层为Al x3In 1-x3P层，所述第一限制层的厚度为250nm至450nm，所述第一波导层为Al x4Ga 1-x4InP层，所述第一波导层的厚度为70nm至150nm，其中，x1、x2、x3和x4均大于0且小于1。
  11. 一种显示面板，其中，包括驱动基板以及多个发光芯片，多个所述发光芯片设置在所述驱动基板上，并与所述驱动基板电连接，所述驱动基板用于向多个所述发光芯片传输电信号以控制多个所述发光芯片发光，所述发光芯片包括第一芯片电极、第二芯片电极以及发光芯片外延结构，所述发光芯片外延结构包括依次层叠设置的第一半导体组件、发光层以及第二半导体组件，所述第一芯片电极与所述第一半导体组件电连接，所述第二芯片电极与所述第二半导体组件电连接，所述第一半导体组件包括依次层叠设置的缓冲层、第一渐变层、腐蚀截止层、第二渐变层、欧姆接触层、第三渐变层、电流扩展层、第一限制层以及第一波导层，所述第一渐变层使所述缓冲层的掺杂浓度和所述腐蚀截止层的掺杂浓度连续，所述第二渐变层使所述腐蚀截止层的掺杂浓度和所述欧姆接触层的掺杂浓度连续，所述第三渐变层使所述欧姆接触层的掺杂浓度和所述电流扩展层的掺杂浓度连续。
  12. 如权利要求11所述的显示面板，其中，所述第一渐变层的掺杂浓度的渐变方式包括线性变化、非线性变化和阶梯式变化中的任意一种或多种组合，所述第二渐变层的掺杂浓度的渐变方式包括线性变化、非线性变化或阶梯式变化中的任意一种或多种组合，所述第三渐变层的掺杂浓度的渐变方式包括线性变化、非线性变化或阶梯式变化中的任意一种或多种组合。
  13. 如权利要求11所述的显示面板，其中，所述第一渐变层的掺杂浓度由所述缓冲层指向所述腐蚀截止层的方向逐渐增大，所述第二渐变层的掺杂浓度由所述腐蚀截止层指向所述欧姆接触层的方向逐渐增大，所述第三渐变层的掺杂浓度由所述欧姆接触层指向所述电流扩展层的方向逐渐减小。
  14. 如权利要求11所述的显示面板，其中，所述第一渐变层为砷化硅和硅层，所述第二渐变层为磷化硅和硅层，所述第三渐变层为砷化硅和硅层。
  15. 如权利要求11所述的显示面板，其中，所述缓冲层为砷化镓层，所述缓冲层的厚度为100nm至300nm，所述腐蚀截止层为Ga x1In 1-x1P层，所述腐蚀截止层的厚度为50nm至300nm，所述欧姆接触层为砷化镓层，所述欧姆接触层的厚度为10nm至150nm，所述电流扩展层为Al x2Ga 1-x2InP层，所述电流扩展层的厚度为1000nm至3000nm，所述第一限制层为Al x3In 1-x3P层，所述第一限制层的厚度为250nm至450nm，所述第一波导层为Al x4Ga 1-x4InP层，所述第一波导层的厚度为70nm至150nm，其中，x1、x2、x3和x4均大于0且小于1。
  16. 一种发光芯片外延结构的制作方法，用于制作发光芯片外延结构，其中，所述发光芯片外延结构的制作方法包括：
    提供一衬底；
    在所述衬底上生成第一半导体组件，其中，所述第一半导体组件包括依次层叠设置于所述衬底上的缓冲层、第一渐变层、腐蚀截止层、第二渐变层、欧姆接触层、第三渐变层、电流扩展层、第一限制层以及第一波导层，所述第一渐变层使所述缓冲层的掺杂浓度和所述腐蚀截止层的掺杂浓度连续，所述第二渐变层使所述腐蚀截止层的掺杂浓度和所述欧姆接触层的掺杂浓度连续，所述第三渐变层使所述欧姆接触层的掺杂浓度和所述电流扩展层的掺杂浓度连续；
    在所述第一半导体组件背对所述衬底的表面上形成发光层；
    在所述发光层背对所述第一半导体组件的表面上生成第二半导体组件。
  17. 如权利要求16所述的发光芯片外延结构的制作方法，其中，所述在所述衬底上生成第一半导体组件，包括：
    通入所述缓冲层对应的Ⅲ族源、所述缓冲层对应的Ⅴ族源以及掺杂源，以在所述衬底上生成所述缓冲层；
    中断生长所述缓冲层对应的Ⅲ族源，保持生长所述缓冲层对应的Ⅴ族源通入，掺杂源由生长所述缓冲层对应的掺杂浓度渐变至生长所述腐蚀截止层的掺杂浓度，以在所述缓冲层背对所述衬底的表面上生成所述第一渐变层；
    通入所述腐蚀截止层对应的Ⅲ族源、所述腐蚀截止层对应的Ⅴ族源以及掺杂源，以在所述第一渐变层背对所述缓冲层的表面上生成所述腐蚀截止层；
    中断生长所述腐蚀截止层对应的Ⅲ族源，保持生长所述腐蚀截止层对应的Ⅴ族源通入，掺杂源由生长所述腐蚀截止层对应的掺杂浓度渐变至生长所述欧姆接触层的掺杂浓度，以在所述腐蚀截止层背对所述第一渐变层的表面上生成所述第二渐变层；
    通入所述欧姆接触层对应的Ⅲ族源、所述欧姆接触层对应的Ⅴ族源以及掺杂源，以在所述第二渐变层背对所述腐蚀截止层的表面上生成所述欧姆接触层；
    中断生长所述欧姆接触层对应的Ⅲ族源，保持生长所述欧姆接触层对应的Ⅴ族源通入，掺杂源由生长所述欧姆接触层对应的掺杂浓度渐变至生长所述电流扩展层的掺杂浓度，以在所述欧姆接触层背对所述第二渐变层的表面上生成所述第三渐变层；
    在所述第三渐变层背对所述欧姆接触层的表面上生成所述电流扩展层；
    在所述电流扩展层背对所述第三渐变层的表面上生成所述第一限制层；
    在所述第一限制层背对所述电流扩展层表面上生成所述第一波导层。
  18. 如权利要求16所述的发光芯片外延结构的制作方法，其中，所述第一渐变层的掺杂浓度的渐变方式包括线性变化、非线性变化和阶梯式变化中的任意一种或多种组合，所述第二渐变层的掺杂浓度的渐变方式包括线性变化、非线性变化或阶梯式变化中的任意一种或多种组合，所述第三渐变层的掺杂浓度的渐变方式包括线性变化、非线性变化或阶梯式变化中的任意一种或多种组合。
  19. 如权利要求16所述的发光芯片外延结构的制作方法，其中，所述第一渐变层的掺杂浓度由所述缓冲层指向所述腐蚀截止层的方向逐渐增大，所述第二渐变层的掺杂浓度由所述腐蚀截止层指向所述欧姆接触层的方向逐渐增大，所述第三渐变层的掺杂浓度由所述欧姆接触层指向所述电流扩展层的方向逐渐减小。
  20. 如权利要求16所述的发光芯片外延结构的制作方法，其中，所述第一渐变层为砷化硅和硅层，所述第二渐变层为磷化硅和硅层，所述第三渐变层为砷化硅和硅层。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104157758A (zh) * 2014-08-21 2014-11-19 湘能华磊光电股份有限公司 发光二极管的外延片及其制作方法
CN104167473A (zh) * 2014-08-11 2014-11-26 厦门乾照光电股份有限公司 一种高晶体质量红外发光二极管的外延生长方法
CN106129201A (zh) * 2016-07-29 2016-11-16 华灿光电（浙江）有限公司 一种发光二极管的外延片及其制备方法
CN107546303A (zh) * 2017-08-25 2018-01-05 扬州乾照光电有限公司 一种AlGaInP基发光二极管及其制造方法
CN114447165A (zh) * 2022-01-27 2022-05-06 厦门士兰明镓化合物半导体有限公司 Led外延结构及其制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104167473A (zh) * 2014-08-11 2014-11-26 厦门乾照光电股份有限公司 一种高晶体质量红外发光二极管的外延生长方法
CN104157758A (zh) * 2014-08-21 2014-11-19 湘能华磊光电股份有限公司 发光二极管的外延片及其制作方法
CN106129201A (zh) * 2016-07-29 2016-11-16 华灿光电（浙江）有限公司 一种发光二极管的外延片及其制备方法
CN107546303A (zh) * 2017-08-25 2018-01-05 扬州乾照光电有限公司 一种AlGaInP基发光二极管及其制造方法
CN114447165A (zh) * 2022-01-27 2022-05-06 厦门士兰明镓化合物半导体有限公司 Led外延结构及其制备方法

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