WO2023221714A1 - 一种δ掺杂层制备方法及电子器件 - Google Patents

一种δ掺杂层制备方法及电子器件 Download PDF

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WO2023221714A1
WO2023221714A1 PCT/CN2023/088909 CN2023088909W WO2023221714A1 WO 2023221714 A1 WO2023221714 A1 WO 2023221714A1 CN 2023088909 W CN2023088909 W CN 2023088909W WO 2023221714 A1 WO2023221714 A1 WO 2023221714A1
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layer
doped layer
annealing
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delta doped
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但亚平
常善南
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上海交通大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H01L21/2256—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides through the applied layer
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
    • H01L31/0288—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PIN type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to the field of semiconductor integration, and specifically to a method for preparing a delta doped layer and an electronic device.
  • Delta doping is not only widely used in quantum devices and metal oxide semiconductor field effect transistors (MOSFETs), but also has extremely important application value in the field of deep ultraviolet light detectors.
  • MOSFETs metal oxide semiconductor field effect transistors
  • sun-blind UV detection technology has great application prospects in the fields of power grid security detection, medical imaging, life sciences, environmental and biochemical detection.
  • UVC band unblind zone
  • UVC band unblind zone
  • UVC band unblind zone
  • UV photodetectors based on GaN, SiC and other materials have mature manufacturing technologies and have been commercialized, the difficulty in obtaining high-quality single crystal films makes the development potential of wide-bandgap semiconductor devices poor while reducing costs. And improving the performance of devices are still difficult challenges for this type of detectors.
  • silicon-based photodetectors still have advantages in terms of high performance, reliability, low cost, and compatibility with CMOS processes.
  • traditional silicon-based photodiodes can absorb deep ultraviolet photons, the devices are not sensitive to the deep ultraviolet spectrum. This is because commercial photodiodes have a vertical structure, and the surface is highly doped to form the electrode of the diode, while preventing the surface state from being exposed in the depletion region to form a large leakage current.
  • the thickness of doped surfaces formed by ion implantation or thermal diffusion typically ranges from tens of nanometers to submicrometers. In contrast, the penetration depth of photons drops significantly from the micron level in the visible spectrum to below 10nm in the deep ultraviolet spectrum.
  • silicon-based UV detectors In order to meet the needs of practical applications, silicon-based UV detectors must have the following characteristics: high sensitivity, good linearity, high stability, and fast operation speed. Judging from the existing literature on silicon-based UV detectors, different device architectures have their own advantages and disadvantages: Schottky diodes have good radiation hardness, but relatively weak responsiveness, low breakdown voltage, and large dark current. For silicon-based p-n junction photodiodes, their spectral response range is wide and can extend to the infrared region. In order to make the device performance meet the requirements of ultraviolet detection, a filter is usually placed in front of the detector to select the spectral range corresponding to the target application, which undoubtedly increases the cost of the detection system.
  • the depletion region in the detector must be as wide as possible and as close to the surface as possible.
  • Another method is to generate an additional electric field near the detector surface in the same direction as the electric field in the depletion region, such as charge-coupled devices (CCD) devices. Therefore, light-generated charges near the device surface can be directed to the depletion region and eventually collected, thereby increasing the surface charge. charge collection efficiency (CCE) and device sensitivity.
  • CCD charge-coupled devices
  • the present invention uses defect-free self-assembled single-molecule doping or atomic layer deposition doping methods, combined with millisecond-level flash annealing or transient laser annealing technology, to fix P-containing impurities on the surface of a very shallow silicon layer.
  • Build delta doped layer A PN junction photodiode was prepared by preparing an n-type delta doped layer on a p-type Si substrate.
  • the atomic-level metal delta doped layer formed by the flash annealing process allows photons in the deep ultraviolet spectral range to be absorbed in the depletion region of the diode, making silicon-based devices highly sensitive in the deep ultraviolet spectral range.
  • the object of the present invention is to provide a delta doped layer preparation method and electronic device to solve the above problems.
  • the delta doped layer preparation method includes the following steps:
  • a monomolecular layer containing dopants or an atomic layer with a nanometer thickness is formed on the surface of the sample through a single-molecule self-assembly process or an atomic layer deposition process;
  • a nanometer-thick dielectric protective layer such as SiO 2 is formed on the monomolecular layer or the nanometer-thick atomic layer sample through atomic layer deposition;
  • the dielectric protective layer sample is subjected to laser or flash annealing to activate the dopant, thereby preparing a delta doped layer.
  • the annealing operating temperature range is 1000-1300°C
  • the substrate preheating temperature is 400-450°C.
  • the annealing working time is 3-20ms
  • the preheating temperature is 400-450°C.
  • it also includes: placing the sample into a mixed solution containing phosphorus trichloride, triethylamine, and benzene to undergo Si-H functionalization reaction, and maintaining the reaction at 70°C for 24 hours.
  • the specific steps of the atomic layer deposition process include: ALD growing an oxide or elemental film of doped elements such as P 2 O 5 or B 2 O 3 on the Si surface, and passing a suitable precursor on the surface of the functionalized silicon wafer The body, a self-terminating reaction occurs, producing chemical adsorbates, and then a vacuum pump is used to evacuate the remaining by-products of the reaction in the cavity until the surface returns to its original state. Repeat this cycle and control the number of cycles to grow several nanometer atomic layers. Thickness, film growth temperature is controlled at 100°C-300°C.
  • the flash annealing includes using a xenon lamp to perform flash annealing.
  • the substrate preheating temperature is set to 400-450°C, maintained for 30s, and then flash annealed for 20ms.
  • the annealing energy density is The temperature is 100J/cm 2 to 200J/cm 2 .
  • the annealing working time is 20-25ns, and the energy density is 0.65J/cm 2 to 0.75J/cm 2 .
  • an electronic device including a delta doped layer, and the delta doped layer is made by the above preparation method.
  • the electronic device includes a solar cell, a quantum device, a silicon-based deep ultraviolet detector or an ultraviolet imaging chip.
  • the advantages of this invention are: 1. It only needs to self-assemble a single layer of monomolecular film or atomic layer deposition layer, and the growth method is simple; 2. The raw materials and reagents used in the experiment are relatively simple and easy to prepare or purchase; 3. Adopt advanced Thermal annealing process, millisecond flash annealing, shortens the thermal diffusion time, does not require long-term heating, reduces the thermal budget, and reduces energy consumption from an environmental perspective; 4. Compatible with CMOS process, the experimental process strictly follows the CMOS process steps conduct.
  • Figure 1 Flowchart of the steps of self-assembly single molecule delta doping combined with flash annealing
  • Figure 2 (a) XPS narrow scan spectrum of P 2s of blank sample and (b) phosphorus functionalized sample (c) XPS narrow scan spectrum of Cl 2s (inset: chemical structure of Si-OP structure diagram);
  • Figure 3(a) The relationship between the sheet resistance of P-doped samples under different preheating temperatures and times.
  • the flash energy is 149.3J/cm 2 .
  • the inset is the AFM surface morphology of the sample under the corresponding parameters (b ) SIMS distribution diagram of samples S1, S2 and post-annealing treatment;
  • Figure 6 Flowchart of the steps of self-assembled single-molecule delta doping combined with pulsed laser annealing.
  • FIG. 1 The step flow chart of an embodiment of a delta doped layer preparation method provided by the present invention is shown in Figure 1.
  • Intrinsic SOI crystalline direction ⁇ 100>, thickness 525 ⁇ 25 ⁇ m, resistivity >10k ⁇ cm
  • a 15 ⁇ m thick silicon wafer is cut into 1 cm ⁇ 1 cm pieces with a diamond knife, and then the same 2 mm ⁇ 2 mm area is created on the chip through photolithography and etching techniques.
  • Pre-ion implantation of P with a concentration of approximately 10 19 cm -3 into the four corners of a 2 mm ⁇ 2 mm square to obtain good ohmic contact was performed, and the dopants were activated by rapid annealing at 1050°C for 30 s.
  • the silicon wafer is then cleaned using a standard RCA process to remove surface organic contamination and metal ions.
  • CMOS organic solvents
  • ALD technology was used to deposit a 50nm layer of SiO 2 on the surface of the sample after grafting PCl 3 molecules, and then the sample was placed in a flash annealing chamber with N 2 flowing.
  • a halogen lamp device is used for flash annealing, and the energy density is selected at 149.3J/cm 2 .
  • the sample is preheated to an intermediate temperature before reaching the peak temperature.
  • the preheating temperature is set between 400-500°C, and the flash pulse width is fixed at 3ms or 20ms.
  • HF aqueous solution to remove the oxide layer on the surface.
  • a layer of 25nm single crystal silicon was grown using MBE technology. Then, metal electrodes Al were deposited on the four corners of the sample to form ohmic contacts.
  • Figure 3a shows the change relationship of the sheet resistance of the sample under different preheating temperatures and times and an energy density of 149.3J/ cm2 .
  • preheating temperature and pulse width increase, the sheet resistance decreases from ⁇ 17.3k ⁇ /sq to 1.6k ⁇ /sq.
  • a decrease in sheet resistance means more dopants diffuse into the silicon lattice and become electrically activated.
  • S1 and S2 we label the samples annealed at 400°C+FLA 20ms and 450°C+FLA 20ms as S1 and S2, which will not be described again later.
  • the results show that the surface of non-molten silicon samples treated with preheating temperatures of 450°C or lower always maintains atomic planes. At the preheating temperature of 500 °C, melting occurred on the sample surface, as shown in the inset of Figure 3a.
  • the doping concentrations per unit area of S1 and S2 are 1.12 ⁇ 10 13 cm -2 and 1.27 ⁇ 10 13 cm -2 respectively.
  • the electron concentrations measured by the Hall effect of these two samples are 1.28 ⁇ 10 13 cm -2 and 1.8 ⁇ 10 13 cm -2 respectively, which are higher than the P doping concentrations calculated from SIMS in the two cases.
  • Conventional SIMS has limited spatial resolution, so it cannot resolve delta doping formed by molecular beam epitaxy.
  • RTA rapid thermal annealing
  • the concentration of the interface is 1.28 ⁇ 10 13 cm -2 . Since SIMS has a spatial resolution of 1 nm, it can be assumed that phosphorus atoms in the delta-doped layer accumulate within 1 nm near the interface. Based on this assumption, the concentration of ⁇ doping at the interface is estimated to be 1.28 ⁇ 10 21 cm -3 or higher, which far exceeds the solubility of P in silicon ( ⁇ 7 ⁇ 10 20 cm -3 at 1300°C).
  • the two-dimensional electron gas formed in the delta-doped layer inside the semiconductor exhibits quantum interference effects in carrier transport. Therefore, we place the sample in an adjustable magnetic field perpendicular to the sample surface to conduct low-temperature download currents.
  • the transport of ions was characterized.
  • the resistivity of the samples (S1 and S2) decreases monotonically as the temperature drops to 2K, as shown in Figure 4a. This indicates that the ⁇ -doped layer is in a degenerate state.
  • the resistance at 2K is 1.33k ⁇ /sq and 0.93k ⁇ /sq respectively.
  • the doping concentration and electron mobility of S1 and S2 samples are 4.06 ⁇ , respectively. 10 12 cm -2 and 1158cm 2 /Vs, 6.6 ⁇ 10 12 cm -2 and 1017cm 2 /Vs, as shown in Table 1.
  • Figure 4b shows the variation curves of the resistivity R xx and Hall resistance R xy of sample S2 with the magnetic field.
  • the resistance decreases monotonically. This phenomenon can be explained by the weak localization theory. Electrons in semiconductors do not simply follow ballistic transport, but undergo a series of random scattering at low temperatures. When the electrons in the film diffuse, the interference of electron waves passing through the time reversal path strengthens each other. The external magnetic field will break the weak localization of the electrons. As a result, the electrons are more likely to be transported in the classic way of elastic scattering, resulting in resistance (magnetoresistance). reduce.
  • ⁇ WL is the weak localization contribution of magnetic conductance
  • ⁇ is the double gamma function
  • the characteristic magnetic field B 0 Relevant to the transport relaxation mechanisms of impurity potential scattering and inelastic scattering respectively.
  • phase coherence of electrons is usually characterized by the phase coherence length l ⁇ and the phase relaxation time ⁇ ⁇ , which are measures of the length of time that electrons maintain phase information in the space and time domains, and are therefore also important parameters of solid qubits in quantum computers.
  • phase relaxation time ⁇ ⁇ depends on the phase coherence length
  • k is Boltzmann's constant
  • T is the absolute temperature
  • q is the charge unit.
  • This metal delta-doped layer can enhance the deep ultraviolet spectral response of silicon-based photodetectors.
  • Conventional silicon photodetectors have very low responsivity in the deep UV range because most UV light is absorbed in an extremely narrow layer just below the silicon surface, and UV light is generally not absorbed in highly doped space charge regions. , Photons cannot be separated effectively in this region and therefore contribute little to the photocurrent.
  • Our metallic delta-doped layer reduces the top highly doped n-type Si to the atomic scale, significantly improving deep UV photoresponsivity. Except for silicon dioxide removal and molecular beam epitaxy, the remaining steps of the device fabrication method are shown in Figure 1.
  • Figure 5a shows the IV curve of a Si diode with a delta doped layer under dark field and illumination.
  • Dark current exhibits rectifying characteristics similar to pn junction diodes.
  • the leakage current is much larger than expected, which may be caused by the non-uniform doping of the delta doped layer over a large area.
  • the surface state of the region where delta doping is not formed makes the pn junction diode Create a shunt resistance.
  • the device Under illumination, the device exhibits a large photocurrent (red line in Figure 5a).
  • the spectral response of the device is shown in Figure 5b (red curve). When the wavelength is reduced to 230nm, the photoresponse increases to ⁇ 1A/W.
  • Our device has high photoresponse at short wavelengths simply because the penetration depth of photons in the deep UV spectral range is reduced to less than 10 nm.
  • the delta-doped layer allows most of the UV light to be absorbed in the depletion region of the photodiode, with the result that photogenerated electron-hole pairs can be separated by the electric field as a photocurrent.
  • typical photodiodes have a thick, highly doped surface layer (tens of nanometers or more) through ion implantation or thermal diffusion, and most photons of deep UV light are highly doped in electrically neutral The region is absorbed and the electron-hole pairs generated by the light cannot be effectively separated.
  • this embodiment in addition to using millisecond-level flash annealing to prepare atomic-level delta doping, this embodiment can also use excimer laser annealing. Since laser annealing is a transient annealing, the heating time is short, up to nanoseconds. or femtosecond level, it can also effectively suppress further diffusion of impurities during the annealing process, greatly reducing the thermal budget and achieving ultra-shallow doping. The specific experimental steps are shown in Figure 6.

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Abstract

一种δ掺杂层制备方法及电子器件，涉及半导体集成领域，包括以下步骤：提供含有掺杂剂的分子或原子沉积前驱体分子；通过单分子自组装工艺或原子层沉积工艺在样品表面形成含有掺杂剂的单分子层或纳米级厚度的原子层；再通过原子层沉积在所述单分子层或纳米级厚度的原子层样品上形成纳米级厚度的SiO2等介质保护层；对所述介质保护层样品进行激光或闪光退火以激活所述掺杂剂，进而制备δ掺杂层。本发明通过自组装单分子或原子沉积掺杂工艺结合先进瞬态退火技术的方法制备δ掺杂，实验方法简单易操作，能够有效降低成本，并且与CMOS工艺兼容，工作环境不需要超真空，常温常压下就可以实现，减少能源消耗，有望实现大批量生产。

Description

一种δ掺杂层制备方法及电子器件 技术领域
本发明涉及半导体集成领域，具体而言，涉及一种δ掺杂层制备方法及电子器件。
背景技术
δ掺杂不仅在量子器件、金属氧化物半导体场效应晶体管(MOSFET)等方面有着广泛的应用，在深紫外光探测器领域也具有极其重要的应用价值。对于不受日光影响的日盲紫外探测，其工作在200nm到280nm的紫外光谱范围内，具有很高的灵敏度，由于在商业和军事领域的广泛应用引起了很多人的关注。除了在远距离通信外，日盲紫外检测技术在电网安全检测，医学成像，生命科学，环境和生化探测等领域具有很大的应用前景。
然而，对日盲辐射的表征需要在不受可见光或长波长紫外光干扰的情况下对UVC波段(日盲区)进行选择性响应。虽然基于GaN，SiC等材料的紫外光电探测器以具有成熟的制造技术，并已经商业化，但由于很难获得高质量的单晶薄膜，使得宽带隙半导体器件的发展潜力较差，同时降低成本和提高器件的性能仍然是这类探测器挑战的难点。
因此，硅基光电探测器在高性能、可靠性、低成本和兼容CMOS工艺方面仍具有优势。传统的硅基光电二极管虽然可以吸收深紫外光子，但器件对深紫外光谱不敏感。这是因为商用光电二极管是垂直结构，表面被高度掺杂，形成二极管的电极，同时避免表面态暴露在耗尽区从而形成较大的漏电流。通过离子注入或热扩散形成的掺杂表面厚度通常在几十纳米到亚微米之间。相比之下，光子的穿透深度从可见光谱的微米级大幅下降到深紫外光谱的10nm以下。结果，深紫外光谱中的光子全部被电中性的高掺杂表面层吸收，吸收所产生的电子-空穴对不能有效地分离形成光电流，导致器件在深紫外波段光响应极弱。
为了满足实际应用需求，硅基紫外探测器必须具有以下特点：灵敏度高、线性度好、稳定性高、运行速度快。从现有的硅基紫外探测器文献来看，不同的器件架构各有优缺点：肖特基二极管具有良好的辐射硬度，但响应性相对较弱，且击穿电压低，暗电流大。对于硅基p-n结光电二极管，其光谱响应范围广，并可延伸至红外区域。为了使器件性能符合紫外检测的要求，通常在探测器前放置滤波片，以便选择对应于目标应用的光谱范围，无疑增加了检测系统的成本。
为了接近理论上可达到的灵敏度，探测器中的耗尽区必须尽可能宽并靠近表面。耗尽区一般有两种实现方式：最直接的方式是在浅层表面形成δ层。另一种方法是在探测器表面附近产生一个与耗尽区电场方向相同的附加电场，例如charge-coupled devices(CCD)器件。因此，器件表面附近的光产生电荷可以定向到耗尽区并最终收集，从而提高了表面电 荷收集效率(CCE)和器件灵敏度。
一些研究也表明，利用硼δ掺杂技术制备的超浅结p-n结二极管在DUV/VUV/EUV范围内比其他任何商用Si基紫外探测器具有更高的响应性。
同时，传统的分子束外延技术在硅中生长δ掺杂层已经深入研究几十年，掺杂物P、B、Sb，As已经成功融入硅晶格当中，在硅表面形成了极浅的δ掺杂区域，由于抑制了与供体相关的缺陷对的形成，可以获得近100％的活化率。近年来，这种方法得到了广泛的研究。虽然MBE掺杂方法很容易超过硅的固溶度，达到超高的掺杂浓度，但由于超真空的工作环境要求，实现大批量生产是十分困难的，这种方法很难与CMOS工艺集成兼容。
基于以上研究，本发明采用无缺陷态自组装单分子掺杂或原子层沉积掺杂的方法，结合毫秒级闪光退火或瞬态激光退火技术，将含P杂质固定在很浅的硅层表面，构建δ掺杂层。通过在p型Si衬底上制备n型δ掺杂层，制备了PN结型光电二极管。由于闪光退火过程形成的原子级的金属δ掺杂层允许深紫外光谱范围的光子在二极管的耗尽区被吸收，从而使得硅基器件在深紫外光谱范围变得高度敏感。
发明内容
本发明的目的在于提供一种δ掺杂层制备方法及电子器件，以解决以上问题，该δ掺杂层制备方法包括以下步骤：
提供含有掺杂剂的分子或原子层沉积前驱体；
通过单分子自组装工艺或原子层沉积工艺在样品表面形成含有掺杂剂的单分子层或纳米级厚度的原子层；
再通过原子层沉积在所述单分子层或纳米级厚度的原子层样品上形成纳米级厚度的SiO2等介质保护层；
对所述介质保护层样品进行激光或闪光退火以激活所述掺杂剂，进而制备δ掺杂层。
可选地，当采用所述闪光退火时，当采用所述闪光退火时，退火工作温度范围为1000-1300℃，衬底预热温度在400-450℃。
可选地，当采用所述闪光退火时，退火工作时间为3-20ms，预热温度在400-450℃。
可选地，还包括：再将样品放入装有三氯化磷，三乙胺，苯的混合溶液中发生Si-H官能化反应，反应在70℃下维持24h。
可选地，所述原子层沉积工艺具体步骤包括：在Si表面ALD生长P2O5或B2O3等掺杂元素氧化物或单质薄膜，在官能化的硅片表面通入适合的前驱体，发生自终止反应，产生化学吸附物，然后利用真空泵排空腔体中反应残留的副产物，直至表面恢复到原来的状态，重复此循环，控制循环次数，使生长几个纳米的原子层厚度，薄膜生长温度控制在100℃-300℃。
可选地，所述闪光退火包括采用氙灯执行闪光退火。
可选地，当采用所述氙灯闪光退火时，衬底预热温度设置为400-450℃，保持30s，再经过闪光退火20ms，退火能量密 度为100J/cm2至200J/cm2。
可选地，当采用所述激光退火时，退火工作时间为20-25ns，能量密度为0.65J/cm2至0.75J/cm2。
另一方面，还提出一种电子器件，包含δ掺杂层，所述δ掺杂层是由上述制备方法所制成。
可选地，所述电子器件包括太阳能电池、量子器件、硅基深紫外探测器或紫外成像芯片。
本发明的优点是：1.只需自组装一层单分子膜或原子层沉积层，生长方法方式简单；2.实验所采用的原材料，试剂相对比较简单，易制备或购买；3.采用先进的热退火工艺，毫秒级闪光退火，缩短热扩散时间，不需要长时间加热，减少热预算，从环保的角度来看，减少能源消耗；4.与CMOS工艺兼容，实验流程严格按照CMOS工艺步骤进行。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本发明的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1通过自组装单分子δ掺杂结合闪光退火步骤流程图；
图2(a)空白样品和(b)磷官能化样品的P 2s的XPS窄扫描谱图(c)Cl 2s的XPS窄扫描谱图(插图：Si-O-P的化学结 构示意图)；
图3(a)P掺杂样品在不同预热温度和时间的条件下与方块电阻间的变化关系，闪光能量为149.3J/cm2，插图为对应参数下样品的AFM表面形貌图(b)样品S1，S2以及后退火处理后的SIMS分布图；
图4(a)S1和S2的方块电阻随温度的变化(2～300K)关系图(b)在T＝2K时，样品S2的方块电阻Rxx和霍尔电阻Rxy随磁场的变化曲线(c)S1和S2归一化后方块电阻与磁场的关系；
图5(a)δ掺杂光电二极管在暗场和光照(λ＝400nm)下的I-V曲线。(附图：器件结构)。(b)δ掺杂Si基p-i-n光电二极管和商用光电二极管在230～500nm范围内的光谱响应。器件反偏电压设置为-1V；
图6通过自组装单分子δ掺杂结合脉冲激光退火步骤流程图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本发明实施例的组件可以以各种不同的配置来布置和设计。
因此，以下对在附图中提供的本发明的实施例的详细描述并非旨在限制要求保护的本发明的范围，而是仅仅表示本发明的选定实施例。基于本发明中的实施例，本领域普通技术人员 在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明提供的一种δ掺杂层制备方法的一实施例步骤流程图如图1所示，采用本征SOI(晶向<100>，厚度525±25μm，电阻率＞10kΩ·cm)，顶硅15μm厚的硅片，用金刚石刀切成1cm×1cm的小片，然后通过光刻及刻蚀技术在片上制作相同的2mm×2mm的区域。在2mm×2mm正方形的四个角预先离子注入浓度约为1019cm-3的P，以获得良好的欧姆接触，经1050℃下快速退火30s激活掺杂剂。
然后采用标准的RCA流程对硅片进行清洗以去除表面有机物沾污以及金属离子。
将样品取出，氮气吹干后浸泡在2.5％HF的水溶液中2min，去除表面自然氧化层，从而形成Si-OH键端的表面，然后迅速将样品放入装有三氯化磷，三乙胺，苯的有机混合溶液中，70℃下加热24h，待反应结束后，分别用有机溶剂(CMOS)丙酮、乙醇、去离子水依次反复超声各3min，进一步去除反应接枝后表面吸附的有机残留物。将样品取出，表征分析备用。
本实施例经过实验，模拟，其结果合理，具体实验结果与分析如图2所示。
为了验证反应后P是否成功地接枝在硅片表面，并且不会引入外来污染，我们比较了空白样品与接枝反应后的样品，对表面进行XPS分析，如图2所示。从图中可以看出，空白样品只有一个Si的等离子损失峰(图2a)， 相比之下，对于官能化的样品，在Si等离子损失峰旁有一个凸起的小峰，约为191.4eV，归属于P 2s特征峰(图2b)，表明P已经成功地接枝到硅片表面。同时在XPS图谱中，Cl 2s的结合能为270eV，但是XPS并没有检测到Cl 2s的特征峰，如图2c所示。因此，在反应过程中最可能发生的反应如下面所示公式(1)。在反应过程中，如图2c插图所示，每个磷原子通过氧原子与三个硅结合，而Cl元素以HCl的形式被除去。
PCl3+3Si-OH→P(O-Si)3+3HCl     (1)
利用ALD技术在接枝PCl3分子后的样品表面沉积一层50nm的SiO2，然后将样品放置在N2流动的闪光退火腔体内。采用卤素灯装置进行闪光退火，能量密度选取在149.3J/cm2。为了减小热应力，在达到峰值温度前将样品先预热到某个中间温度，预热温度设置在400-500℃之间，闪光脉冲宽度固定在3ms或20ms。待退火结束后，用HF水溶液将表面的氧化层去掉。为了消除P杂质剖面中Si：H的影响，使用MBE技术生长一层25nm的单晶硅。紧接着在样品四角沉积金属电极Al，形成欧姆接触。
图3a显示了不同预热温度和时间，149.3J/cm2的能量密度下样品的方块电阻的变化关系。随着预热温度和脉冲宽度的增加，方块电阻从～17.3kΩ/sq下降到1.6kΩ/sq。方块电阻的降低意味着更多的掺杂剂扩散到硅晶格中并被电激活。为了简化样品信息，我们把400℃+FLA 20ms和450℃+FLA 20ms退火的样品标记为S1和S2，后面不再赘述。结果显示，450℃或更低的预热温度处理的非熔融硅样品，表面始终保持原子平面。在500℃的预热温度下，样品表面发生熔融，如图3a插图所示。
为了探究闪光退火处理后P的掺杂分布，使用二次离子质谱(SIMS)进行表征。从图3b中可以直接观察到，样品S1和S2在外延界面处的峰值浓 度均为～1.3×1019cm-3，磷浓度以8nm/dec的速率向两侧迅速衰减。前表面突然增加(图3b左侧)是由于来自表面与磷质量相同的Si-H二聚体的错误信号造成的。通过对掺杂浓度沿x坐标积分时(不考虑近表面突变)，我们发现S1和S2的单位面积掺杂浓度分别为1.12×1013cm-2和1.27×1013cm-2。而这两个样品的霍尔效应所测量的电子浓度分别为1.28×1013cm-2和1.8×1013cm-2，高于两种情况下从SIMS计算得到的P掺杂浓度。而常规SIMS的空间分辨率有限，因此无法分辨分子束外延形成的δ掺杂。为了确保掺杂剂能够被SIMS分辨，采用了额外的快速热退火(RTA)工艺，在1050℃下处理样品30s。经过RTA处理后，我们观察到S2样本的SIMS剖面中有一个额外的宽凸起延伸到体内(绿色曲线)。通过分析，RTA退火后P浓度从1.27×1013cm-2增加到2.55×1013cm-2。界面的δ掺杂浓度为1.28×1013cm-2。由于SIMS具有1nm的空间分辨率，可以假设δ-掺杂层中的磷原子在界面附近1nm内积累。根据这种假设，界面处δ掺杂的浓度估计为1.28×1021cm-3或更高，远超过P在硅中的溶解度(1300℃时～7×1020cm-3)。显然，形成了过饱和的δ-掺杂层。我们之前发现S2样品的总电子浓度为1.8×1013cm-2，除了δ掺杂层中的P被SIMS测得为1.27×1013cm-2(图3b中的蓝色曲线)，根据磷的电离相关理论，应该有～1.2×1013cm-2全部激活。这意味着电子浓度为0.6×1013cm-2来自于δ掺杂层。
对于半导体内部的δ掺杂层中形成的二维电子气在载流子传输中表现出量子干涉效应，因此，我们把样品放置在一个可调变磁场中并垂直于样品表面，对低温下载流子的输运进行了表征。当磁场为0时，样品(S1和S2)的电阻率随温度降至2K单调减小，如图4a所示。这表明δ掺杂层处于简并状态。对于样品S1和S2，2K时电阻分别为1.33kΩ/sq和0.93kΩ/sq。在此温度下，S1和S2样品的掺杂浓度和电子迁移率分别为4.06× 1012cm-2和1158cm2/Vs，6.6×1012cm-2和1017cm2/Vs，如表1所示。
图4b为样品S2的电阻率Rxx和霍尔电阻Rxy随磁场的变化曲线。当外加磁场强度在两个方向上增加时，电阻单调减小。这一现象可以用弱局域化理论来解释，半导体中的电子并不是简单地遵循弹道传输，而是在低温下经历一系列的随机散射。由于薄膜中的电子扩散时，经过时间反演路径的电子波干涉相互增强，外加磁场会打破电子的弱局域化，结果电子更可能以弹性散射的经典方式传输，导致电阻(磁阻)的降低。研究表明，P掺杂硅的自旋和自旋轨道散射都很弱，这意味着与这些散射相关的弛豫时间较长，与电子-电子和电子-声子相互作用相比可以忽略不计。电阻率减小或电导率增大随外加磁场B的函数关系由简化的Hikami模型(Eq.(2))给出。
其中ΔσWL是磁导的弱局域化贡献，σWL，0是B＝0处的电导，ψ是双伽马函数，特征磁场B0，分别与杂质势散射和非弹性散射的输运弛豫机制有关。
表一在2K下霍尔效应与磁阻测量相关参数

由于非弹性散射导致电子相位相干性的丧失，导致电子的弱局域化。所以重点讨论与非弹性散射相关的特征磁场。电子的相位相干通常用相位相干长度lφ和相位弛豫时间τφ表征，它们是电子在空间和时间域中保持相位信息的长度的度量，因此也是量子计算机中固体量子位的重要参数。根据Goh等人的研究，相位相干长度l与特征磁场的关系为相弛豫时间τφ依赖于相相干长度其中扩散系数与迁移率μ的关系为k为玻尔兹曼常数，T为绝对温度，q为电荷单位。将Eq.(2)与图4c的实验数据拟合得到的参数列在表一。
通过闪光退火，在硅衬底中单层掺杂确实形成了金属态的δ掺杂。这种金属δ掺杂层可以增强硅基光电探测器的深紫外光谱响应。传统的硅光电探测器在深紫外范围的响应性很低，因为大多数紫外光被吸收在硅表面正下方极窄的薄层中，在高度掺杂的空间电荷区域内通常吸收不到紫外光， 在这个区域光子不能被有效地分离，因此对光电流的贡献很小。我们的金属δ掺杂层将顶部高度掺杂的n型Si降低到原子尺度，从而显著提高了深紫外光响应性。器件制作方法除了二氧化硅去除和分子束外延外，其余步骤如图1所示，在p型Si衬底(0.009-0.0015Ω·cm)上制作，在S2样品相同的条件下(450℃+FLA 20ms)进行闪光退火处理。为了保证Al电极与金属δ掺杂层的适当接触，在图1的第一步，在Si晶片的接触区域(2mm×2mm Si晶片的四角处)预先注入浓度为1019cm-3的磷离子。最终的器件结构如图5a的插图所示。
图5a为δ掺杂层的Si二极管在暗场和光照下的I-V曲线。暗电流表现出类似于pn结二极管的整流特性。在负向偏置时，漏电流比预期的要大得多，这可能是因为δ掺杂层在大范围内掺杂不均匀造成的，δ掺杂未形成的区域的表面态使pn结二极管产生分流电阻。在光照下，器件表现出较大的光电流(图5a中红线)。器件的光谱响应如图5b(红色曲线)所示，当波长减小到230nm时，光响应增加到～1A/W。我们的装置在短波长具有高的光响应仅仅是因为光子在深紫外光谱范围的穿透深度减小到小于10nm。δ掺杂层允许大部分的紫外光在光电二极管的耗尽区被吸收，其结果是光电产生的电子-空穴对可以被作为光电流的电场分开。相比之下，典型的光电二极管通过离子注入或热扩散有一个很厚的高度掺杂的表面层(数十纳米或更厚)，大多数深紫外光的光子在电中性的高度掺杂区域被吸收，光产生的电子-空穴对不能有效地分离。事实上，当我们校准一个商业p-i-n光电二极管的光谱响应时，当波长从500nm缩短到230nm时，光响应从0.4A/W下降到0.05A/W，下降了一个数量级(图5b中的黑色曲线)。我们的光电二极管的硅衬底是高度掺杂的(1018cm-3)，这导致在金属δ掺杂层正下方有一个短的耗尽区(～28nm)。有趣的是，这个短耗尽区显著降低了较长波长的光响应，产生了实际应用中非常需要的日盲光响应探测。传统的日盲紫 外光探测器只能采用宽禁带半导体实现，而我们通过在高度掺杂的p型硅衬底上形成金属n型δ掺杂来实现。
如图6，本实施例除了使用毫秒级闪光退火制备原子级δ掺杂，同时也可以采用准分子激光退火来实现，激光退火由于其是一种瞬态退火，加热时间短，可达纳秒或飞秒级别，同样在退火过程中能够有效抑制杂质进一步扩散，极大地减少热预算，实现超浅掺杂。具体实验步骤如图6所示。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种δ掺杂层制备方法，其特征在于，包括以下步骤：
    提供含有掺杂剂的分子或原子层沉积前驱体；
    通过单分子自组装工艺或原子层沉积工艺在样品表面形成含有掺杂剂的单分子层或纳米级厚度的原子层；
    再通过原子层沉积在所述单分子层或纳米级厚度的原子层样品上形成纳米级厚度的SiO2介质保护层；
    对所述介质保护层样品进行激光或闪光退火以激活所述掺杂剂，进而制备δ掺杂层。
  2. 根据权利要求1所述的δ掺杂层制备方法，其特征在于，当采用所述闪光退火时，当采用所述闪光退火时，退火工作温度范围为1000-1300℃，衬底预热温度在400-450℃。
  3. 根据权利要求2所述的δ掺杂层制备方法，其特征在于，当采用所述闪光退火时，退火工作时间为3-20ms，预热温度在400-450℃。
  4. 根据权利要求1所述的δ掺杂层制备方法，其特征在于，还包括：再将样品放入装有三氯化磷，三乙胺，苯的混合溶液中发生Si-H官能化反应，反应在70℃下维持24h。
  5. 根据权利要求1所述的δ掺杂层制备方法，其特征在于，所述原子层沉积工艺具体步骤包括：在Si表面ALD生长P2O5或B2O3等掺杂元素氧化物或单质薄膜，在官能化的硅片表面通入适合的前驱体，发生自终止反应，产生化学吸附物，然后利用真 空泵排空腔体中反应残留的副产物，直至表面恢复到原来的状态，重复此循环，控制循环次数，使生长几个纳米的原子层厚度，薄膜生长温度控制在100-300℃。
  6. 根据权利要求1所述的δ掺杂层制备方法，其特征在于，所述闪光退火包括采用氙灯执行闪光退火。
  7. 根据权利要求6所述的δ掺杂层制备方法，其特征在于，当采用所述氙灯闪光退火时，衬底预热温度设置为400-450℃，保持30s，再经过闪光退火20ms，退火能量密度为100J/cm2至200J/cm2。
  8. 根据权利要求1所述的δ掺杂层制备方法，其特征在于，当采用所述激光退火时，退火工作时间为20-25ns，能量密度为0.65J/cm2至0.75J/cm2。
  9. 一种电子器件，其特征在于，包含δ掺杂层，所述δ掺杂层是由如权利要求1-8任意一项制备方法所制成。
  10. 根据权利要求9所述的电子器件，其特征在于，所述电子器件包括太阳能电池、量子器件、硅基深紫外探测器或紫外成像芯片。
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