WO2023221096A1 - 布线基板及电子装置 - Google Patents

布线基板及电子装置 Download PDF

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Publication number
WO2023221096A1
WO2023221096A1 PCT/CN2022/094141 CN2022094141W WO2023221096A1 WO 2023221096 A1 WO2023221096 A1 WO 2023221096A1 CN 2022094141 W CN2022094141 W CN 2022094141W WO 2023221096 A1 WO2023221096 A1 WO 2023221096A1
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WIPO (PCT)
Prior art keywords
pad
substrate
orthographic projection
area
pad area
Prior art date
Application number
PCT/CN2022/094141
Other languages
English (en)
French (fr)
Inventor
韩停伟
许邹明
王杰
吴信涛
徐佳伟
罗宁雨
Original Assignee
京东方科技集团股份有限公司
合肥京东方瑞晟科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥京东方瑞晟科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/094141 priority Critical patent/WO2023221096A1/zh
Priority to CN202280001308.0A priority patent/CN117441127A/zh
Publication of WO2023221096A1 publication Critical patent/WO2023221096A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a wiring substrate and an electronic device.
  • micro-light-emitting diodes is approximately less than 500 ⁇ m. Due to its smaller size, ultra-high brightness, long life and other advantages, the use trend in the display field has increased significantly.
  • a wiring substrate including:
  • a first pad group located on the substrate, the first pad group including output pads
  • a constant voltage signal line located on the same side of the substrate as the first pad group
  • the second pad group includes a plurality of sub-pad groups arranged in parallel, and each of the sub-pad groups includes a plurality of pad areas arranged in series.
  • the above-mentioned wiring substrate provided by the embodiment of the present disclosure further includes a connection line through which the constant voltage signal line is coupled to the plurality of sub-pad groups arranged in parallel.
  • the second pad group is multiple and arranged in an array on the substrate, and the second pad group in the same second pad group is arranged in an array. All the pad areas are arranged in an array on the substrate;
  • connection line is located between at least two of the pad areas in the second pad group.
  • the line width of the connection line is greater than the line width of the constant voltage signal line.
  • the connecting line includes a first wiring portion extending in the same direction as the constant voltage signal line, and an extending direction similar to that of the constant voltage signal line.
  • a second wiring portion is arranged at an intersection, and the second wiring portion connects the constant voltage signal line and the first wiring portion.
  • the orthographic projection of the first pad group on the substrate and the orthographic projection of the connecting line on the substrate are different from each other. overlap.
  • the second pad group includes two sub-pad groups arranged in parallel, wherein one of the sub-pad groups includes two sub-pad groups arranged in series.
  • the first pad area and the second pad area, and the other sub-pad group includes a third pad area and a fourth pad area arranged in series.
  • the first pad area and the second pad area are arranged in the same row and are arranged in the same row as the third pad area, and the The fourth pad area is arranged in the same row as the first pad area and in the same column as the third pad area.
  • the first pad area is arranged in the same row as the second pad area and is arranged in the same column as the third pad area
  • the The fourth pad area is arranged in the same row as the second pad area and in the same row as the third pad area.
  • the first pad area and the third pad area are arranged in the same column and are arranged in the same row as the fourth pad area, and the The second pad area is arranged in the same row as the third pad area and in the same row as the fourth pad area.
  • an embodiment of the present disclosure provides an electronic device, including the above-mentioned wiring substrate provided by the embodiment of the present disclosure, a micro driver chip coupled to the first pad group, and a micro driver chip coupled to the second pad group. Coupled electronic components.
  • the above-mentioned electronic device provided by the embodiment of the present disclosure further includes a plurality of first transparent protection structures, and the orthographic projection of each first transparent protection structure on the substrate covers each of the first transparent protection structures respectively. Orthographic projection of the electronic component onto the substrate.
  • the orthographic projection of the connecting line on the substrate and the orthographic projection of the first transparent protective structure on the substrate are different from each other. overlap.
  • the above-mentioned electronic device provided by the embodiment of the present disclosure further includes a second transparent protection structure, and the orthographic projection of the second transparent protection structure on the substrate covers the micro drive chip. Orthographic projection on the substrate.
  • the connecting line has a recess in the intersection area of the first wiring part and the second wiring part, and the first wiring part is in the The orthographic projection on the substrate and the orthographic projection of the second wiring portion on the substrate do not overlap with the orthographic projection of the second transparent protective structure on the substrate.
  • Figure 3 is another structural schematic diagram of the area where a first pad group and a coupled second pad group are located in the wiring substrate provided by an embodiment of the present disclosure
  • Figure 4 is another structural schematic diagram of the area where a first pad group and a coupled second pad group are located in the wiring substrate provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of an area where a first pad group and a coupled second pad group are located in the electronic device according to an embodiment of the present disclosure
  • FIG. 6 is another structural schematic diagram of an area where a first pad group and a coupled second pad group are located in the electronic device according to an embodiment of the present disclosure
  • FIG. 7 is another structural schematic diagram of an area where a first pad group and a coupled second pad group are located in the electronic device according to an embodiment of the present disclosure
  • Figure 9 is a schematic structural diagram of a micro driver chip provided by an embodiment of the present disclosure.
  • Micro-LED display technology combines many advantages of liquid crystal display technology and organic light-emitting display technology. Especially when micro-LED display technology is applied to backlights, it can achieve more precise dynamic backlight effects, effectively improving screen brightness and contrast. , it can also solve the glare phenomenon caused by traditional dynamic backlight between bright and dark areas of the screen, optimize the visual experience, and is more suitable for ultra-large screen products.
  • multiple electronic components and a micro driver chip form a functional area, and thousands of functional areas are arranged in an array. Without calculating path loss, in order to ensure that each electronic component operates normally under rated power, multiple electronic components in each functional area are connected in series, and a micro driver chip provides driving signals to multiple electronic components.
  • the output power is at least I 2 * Rtotal , where I is the rated current of the electronic component, and Rtotal is the sum of the resistances of multiple electronic components in a functional area.
  • An embodiment of the present disclosure provides a wiring substrate, as shown in Figures 1 and 2, including:
  • the first pad group 102 is located on the substrate 101, and the first pad group 102 includes the output pad Out;
  • the constant voltage signal line 103 is located on the same side of the substrate 101 as the first pad group 103;
  • the second pad group 104 includes a plurality of sub-pad groups 104' arranged in parallel, and each sub-pad group 104' includes a plurality of pad areas arranged in series (for example, E 1 and E 2 , E 3 and E 4 ), optionally, each pad area (for example, E 1 to E 4 ) includes at least a first pad 41 and a second pad 42, on the series circuit of each sub-pad group 104',
  • the first pad 41 of the first pad area (for example, E 1 or E 3 ) is coupled to the constant voltage signal line 103
  • the second pad 42 of the nth pad area (for example, E 1 or E 3 ) is coupled to the constant voltage signal line 103 .
  • the first pad 41 of the (n+1)th pad area (for example, E 2 or E 4 ) is coupled, and the second pad 42 of the last pad area (for example, E 2 or E 4 ) is coupled to the first pad 41 .
  • the output pad Out of the pad group 102 is coupled.
  • each pad area (for example, E 1 to E 4 ) is connected in series into a plurality of sub-pad groups 104 in a second pad group 104 (corresponding to one lamp area). ', and connect each sub-pad group 104' in parallel, so that the electronic components coupled to each pad area (for example, E 1 to E 4 ) are connected in series and parallel, without calculating the path loss.
  • the output power of the micro driver chip coupled to the first pad group 102 is at least
  • I is the rated current of the electronic component
  • m is the total number of sub-pad groups 104' contained in a second pad group 104
  • t is an integer greater than or equal to 1 and less than or equal to m
  • R m is a sub-pad
  • the sum of the resistances of each electronic component connected in series within group 104' is the reciprocal of the sum of the resistances of the electronic components connected in parallel in the second pad group 104 .
  • the output power of the micro driver chip in this disclosure is (N*R*I 2 )/m 2
  • the output power I 2 *R of the micro driver chip in the related art is always N*R*I 2 . From the comparison, it can be seen that the output power of the micro driver chip of the present disclosure is less than the output power of the micro driver chip in the related art. Therefore, the micro driver chip with smaller power and lower cost in the present disclosure can be used to replace the larger power and lower cost of the micro driver chip in the related art. Higher micro driver chip, thereby saving costs and improving product competitiveness.
  • the above-mentioned wiring substrate provided by the embodiment of the present disclosure may also include a connection line 105, through which the constant voltage signal line 103 is connected to a plurality of sub-solders arranged in parallel.
  • the pad group 104' is coupled.
  • the constant voltage signal line 103 is connected to the first pad 41 of each first pad area (such as E 1 and E 3 ) in each sub-pad group 104' through the connecting line 105.
  • the connection is such that the constant voltage signal provided by the constant voltage signal line 103 is transmitted to the first pad 41 of each first pad area (for example, E 1 and E 3 ) in each sub-pad group 104 ′ through the connection line 105 .
  • FIGS. 1 and 2 there are multiple second pad groups 104 (only 2*2 are shown in the figure) and in The substrate 101 is arranged in an array, and all the pad areas (for example, E 1 to E 4 ) in the same second pad group 104 are arranged in an array on the substrate 101; at least a part of the connection line 105 is located on the second pad group 104. between at least two pad areas (eg, E 1 to E 4 ) in the pad group 104 to rationally utilize the space between the pad areas (eg, E 1 to E 4 ) for wiring.
  • soldering can be fully utilized in order to reduce the loss of the constant voltage signal provided by the constant voltage signal line 103 on the transmission path.
  • the space between the panels eg E 1 to E 4 ) is designed to route the connection line 105 so that the line width of the connection line 105 is as large as possible, and accordingly the resistance of the connection line 105 is as small as possible.
  • the line width d 1 of the connection line 105 is greater than the line width d 2 of the constant voltage signal line.
  • the line width d 1 of the connecting line 105 is greater than 1000 ⁇ m and less than or equal to 3553 ⁇ m
  • the line width d 2 of the constant voltage signal line is greater than or equal to 1000 ⁇ m and less than or equal to 1433 ⁇ m.
  • the line width d 1 of the connecting line 105 can be 1991.82 ⁇ m, 2000 ⁇ m, etc.
  • the line width d2 of the constant voltage signal line is 1000 ⁇ m, etc.
  • connection line 105 may include a first wiring portion 51 extending in the same direction as the constant voltage signal line 103 , and The second wiring portion 52 is arranged to cross the constant voltage signal line 103 in its extending direction. The second wiring portion 52 connects the constant voltage signal line 103 and the first wiring portion 51 .
  • the first wiring portion 51 can be arranged at the column gap of each pad area (for example, E 1 to E 4 ) in the same second pad group 104, and the line width d 11 of the first wiring portion 51 is greater than Equal to 2000 ⁇ m and less than or equal to 3553 ⁇ m, for example, the line width d 11 of the first wiring portion 51 is 2000 ⁇ m, 2500 ⁇ m, 3000 ⁇ m, 3500 ⁇ m, etc.
  • the second wiring part 52 may be arranged at the row gap of the adjacent second pad group 104 , and the line width d 12 of the second wiring part 52 is greater than 1000 ⁇ m and less than or equal to 3200 ⁇ m, for example, the line width of the second wiring part 52 d 12 is 1500 ⁇ m, 2000 ⁇ m, 2500 ⁇ m, 3000 ⁇ m, etc.
  • the line width d 2 of the constant voltage signal line 103 is 1000 ⁇ m
  • the line width d 11 of the first wiring part 51 is 2000 ⁇ m
  • the line width d 12 of the second wiring part 52 is 1991.82 ⁇ m
  • the thickness of the line 103, the first wiring part 51, and the second wiring part 52 are all 1.8 ⁇ m
  • the sheet resistance (sheet resistance) is 0.011 ⁇ / ⁇ .
  • the total resistance of is 0.1851m ⁇ .
  • the line width compensation function of the constant voltage signal line 103 can be achieved through the first wiring part 51 and the second wiring part 52.
  • the orthographic projection of the first pad group 102 on the substrate 101 is the same as the connection line 105 on the substrate 101
  • the orthographic projections do not overlap with each other, so that the connecting wire 105 avoids the first pad group 102 and prevents the connecting wire 105 from being short-circuited with the first pad group 102 .
  • the second pad group 104 may include two sub-pad groups 104' arranged in parallel, one of which is The pad group 104' includes a first pad area E 1 and a second pad area E 2 arranged in series, and the other sub-pad group 104' includes a third pad area E 3 and a fourth pad area E arranged in series. 4 .
  • the first pad area E 1 and the second pad area E 2 are arranged in the same column and are arranged in the same row as the third pad area E 3
  • the fourth pad area E 4 is arranged in the same column as the first pad area E 3.
  • the pad area E 1 is arranged in the same row as the third pad area E 3 ; in Figure 3, the first pad area E 1 is arranged in the same row as the second pad area E 2 and is arranged in the same row as the third pad area E 3. 3 are arranged in the same column, the fourth pad area E 4 is arranged in the same column as the second pad area E 2 , and is arranged in the same row as the third pad area E 3; in Figure 4, the first pad area E 1 and the third pad area E 3 are arranged in the same row.
  • the pad area E 3 is arranged in the same column and is arranged in the same column as the fourth pad area E 4 .
  • the second pad area E 2 is arranged in the same row as the third pad area E 3 and is arranged in the same column as the fourth pad area E 4 .
  • the second pad group 104 includes two sub-pad groups 104' and each sub-pad group 104' includes two pad areas.
  • the second pad group 104 includes two sub-pad groups 104'.
  • the pad group 104 may also include more than two sub-pad groups 104', and each sub-pad group 104' may include more than two pad areas, which is not limited here.
  • the first pad group 102 may include, in addition to the output pad Out, the address pad Di, The power supply pad Pwr and the ground pad Gnd, where the address pad Di belonging to the same first pad group 102 is spaced apart from the power supply pad Pwr in the row direction X, and is spaced apart from the output pad Out in the column direction Y
  • the ground pad Gnd and the power supply pad Pwr are spaced apart from each other in the column direction Y, and are spaced apart from the output pad Out in the row direction X.
  • the output pad Out is located at the upper left corner of the first pad group 102
  • the address pad Di is located at the lower left corner of the first pad group 102
  • the ground pad Gnd is located at the upper right corner of the first pad group 102
  • Electrical pad Pwr is located at the lower right corner of the first pad group 102 .
  • each first pad group 102 may be coupled to one micro driver chip 002
  • each second pad group 104 may be coupled to a plurality of electronic components 003 .
  • the address pad Di can receive an address signal for strobing the micro driver chip 002 of the corresponding address.
  • the power supply pad Pwr can provide operating voltage and communication data to the micro driver chip 002, and the communication data can be used to control the working status of the corresponding electronic components.
  • the output pad Out can respectively output a relay signal and a drive signal in different time periods.
  • the relay signal is an address signal provided to the address pad Di in the first pad group 102 of the next level.
  • the drive signal It is a driving current used to drive electronic components coupled to the first pad group 102 where the output pad Out is located.
  • the ground pad Gnd receives the common voltage signal.
  • each first pad group 102 in the above wiring substrate provided by the embodiment of the present disclosure, as shown in FIGS. 1 and 2 , in the column direction Y, each first pad group 102 can be arranged in cascade, optionally, in the same column.
  • the address pad Di of the first pad group 102 of the first level is connected to the address signal line 107, and the output pad Out of the kth (k is a positive integer) first pad group 102 is connected to the (k+1)th level
  • the address pad Di of the first pad group 102 is connected through the cascade line 106 , and the output pad Out of the last stage of the first pad group 102 is connected to the feedback signal line 108 .
  • a power signal line 109 having a plurality of sub-sections 109' may also be included.
  • One sub-section 109' is connected to one column.
  • the power supply pads of a first pad group 102 are connected.
  • two adjacent sub-segments 109' in the column direction Y can be connected to each other through a connecting lead 110 to realize that the same power supply signal line 109 is in the same column level.
  • the power supply pads Pwr of the connected plurality of first pad groups 102 provide power.
  • the connection lead 110 and the sub-segment 109' are an integral structure.
  • the above-mentioned wiring substrate provided by the embodiment of the present disclosure may also include a common voltage signal line 111 for all first pad groups 102 arranged in cascade in one column.
  • the ground pad Gnd can be connected to the same common voltage signal line 111.
  • the line 109, the connecting lead 110 and the common voltage signal line 111 may be arranged on the same layer.
  • “same layer” refers to a layer structure formed by using the same film formation process to form a film layer for making a specific pattern, and then using the same mask to form a patterning process. That is, one patterning process corresponds to one mask (also called photomask).
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous. These specific patterns may be at the same height or Have the same thickness, may be at different heights or have different thicknesses.
  • the above-mentioned wiring substrate provided by the embodiments of the present disclosure also includes an insulating layer having a plurality of hollow structures on the side of all circuit layers farthest from the substrate, and each hollow structure exposes the ends of part of the circuits. to form respective pad regions (eg, E 1 to E 4 in FIG. 1 ) and the first pad group 102 respectively.
  • the insulating layer can be made of a material with high reflectivity, such as white ink.
  • an embodiment of the present disclosure provides an electronic device, as shown in FIG. 5 , including the above-mentioned wiring substrate 001 provided by the embodiment of the present disclosure, a micro driver chip 002 coupled to the first pad group 102, and Electronic component 003 coupled to second pad set 104 .
  • the electronic device including the above-mentioned wiring substrate 001 provided by the embodiment of the present disclosure, a micro driver chip 002 coupled to the first pad group 102, and Electronic component 003 coupled to second pad set 104 .
  • the orthographic projection area of the micro driver chip 002 on the substrate 101 is not greater than 300000 ⁇ m 2 ;
  • the electronic component 003 is a light-emitting element, and the light-emitting area of the light-emitting element does not exceed 300000 ⁇ m 2 . Specifically, it may not exceed 40000 ⁇ m 2 .
  • the light-emitting element There are two pins, and each pad area (for example, E1 to E4) includes a first pad 41 and a second pad 42, which are respectively connected to the two pins of the light-emitting element. It can be understood that when the electronic component 003 is another component, it may have other numbers of pins. Correspondingly, each pad area (eg, E1 to E4) has the same number of pads as the pins of the component.
  • a plurality of first transparent protection structures 112 may also be included, and each first transparent protection structure 112 is located on the substrate 101
  • the orthographic projection on the substrate 101 respectively covers the orthographic projection of each electronic component 003 on the substrate 101 to protect each electronic component 003 through the first transparent protection structure 112, and in the case where the electronic component 003 is a light-emitting component, the first transparent protection structure 112 can also play a role in improving light efficiency.
  • the first transparent protective structure 112 can be produced by glue dispensing or stencil printing.
  • the first transparent protection structure 112 can form a dome shape on the electronic component 003 (such as a light-emitting component).
  • This shape of the first transparent protection structure 112 can Known as a droplet lens (Lens), the orthogonal projection radius r of the first transparent protective structure 112 on the substrate 101 may be 1450 ⁇ m.
  • the deviation can be within ⁇ 150 ⁇ m, that is to say, the maximum radius r max of the orthographic projection of the first transparent protective structure 112 on the substrate 101 is 1600 ⁇ m, and the minimum radius r max is 1600 ⁇ m.
  • the radius r min is 1400 ⁇ m.
  • the space between the pad areas E in the second pad group 104 is large enough to effectively ensure connection.
  • the line width of the line 105 meets the voltage drop requirement. Therefore, the orthographic projection of the connecting line 105 on the substrate 101 may not overlap with the orthographic projection of the first transparent protection structure 112 on the substrate 110 to avoid the connecting line 105 being
  • the first transparent protective structure 112 is adhered, and during production and transportation, the first transparent protective structure 112 is scratched and accidentally drives the connecting wire 105, causing the connecting wire 105 to fall off.
  • the distance between the orthographic projection of the connection line 105 on the substrate 101 and the maximum orthographic projection of the first transparent protection structure 112 on the substrate 101 is greater than or equal to 50 ⁇ m.
  • the orthographic projection of the connection line 105 on the substrate 101 and the second transparent protection structure 113 on the substrate 101 overlap at least partially to prevent the connecting wire 105 from being adhered to by the second transparent protective structure 113.
  • the second transparent protective structure 113 is scratched and accidentally drives the connecting wire 105, causing the connecting wire 105 to fall off. risks of.
  • the distance between the orthographic projection of the connection line 105 on the substrate 101 and the minimum orthographic projection of the second transparent protection structure 113 is less than or equal to 50 ⁇ m, and the distance between the orthographic projection of the connecting line 105 and the solid crystal mark of the micro driver chip 002 is less than or equal to 50 ⁇ m.
  • the distance of v is greater than or equal to 40 ⁇ m.
  • connection line 105 has a recess C in the intersection area of the first wiring portion 51 and the second wiring portion 52 , the orthographic projection of the first wiring portion 51 on the substrate 101 , and the second wiring portion 52 on the substrate 101
  • the orthographic projection on the substrate 101 does not overlap with the orthographic projection of the second transparent protection structure 113 on the substrate 101 , so that the connection line 105 can avoid the second transparent structure 113 at the recess C.
  • the micro driver chip 002 may include a demodulation circuit 201, a physical layer interface circuit 202, a data processing control circuit 203, a pulse width modulation circuit 204, a drive signal generation circuit 205, a relay signal generation circuit circuit 206 and power supply circuit 207.
  • the demodulation circuit 201 is electrically connected to the power supply pad Pwr and the physical layer interface circuit 202, and is configured to demodulate the power line carrier communication signal input from the power supply pad Pwr to obtain communication data, and convert the communication Data is transferred to the physical layer interface circuit.
  • the communication data may be data that reflects the duration of light emission, thereby representing the required light-emitting brightness.
  • SPI Serial Peripheral Interface
  • the embodiment of the present disclosure adopts the Power Line Carrier Communication (PLC) protocol to superimpose the communication data on the power signal, which can effectively reduce The number of signal lines.
  • PLC Power Line Carrier Communication
  • the physical layer interface circuit 202 is also electrically connected to the data processing control circuit 203, and is configured to process the communication data to obtain data frames (such as frame rate data), and transmit the data frames to the data processing control circuit. 203.
  • the data frame obtained by the physical layer interface circuit 202 contains information that needs to be transmitted to the micro driver chip 002, such as information related to the light-emitting time (such as the specific length of the light-emitting time).
  • the physical layer interface circuit 202 is a common port physical layer (Physical, PHY).
  • Physical, PHY Physical, PHY
  • the data processing control circuit 203 is also electrically connected to the address pad Di, the pulse width modulation circuit 204 and the relay signal generation circuit 206.
  • the data processing control circuit 203 is configured to generate a pulse width control signal based on the data frame and transmit the pulse width control signal to the pulse width modulation circuit 204, and generate a relay control signal based on the address signal and transmit the relay control signal to the follow the signal generation circuit 206.
  • the light-emitting time required by the light-emitting element connected to the micro driver chip 002 can be learned based on the data frame, so a corresponding pulse width control signal is generated based on the light-emitting time.
  • the relay control signal is a signal generated after the data processing control circuit 203 processes the first input signal.
  • the address signal such as parsing, latching, decoding, etc.
  • the address signal corresponding to the micro driver chip 002 can be learned, and a relay control signal corresponding to the subsequent address will be generated, and the subsequent address corresponds to other Micro driver chip 002.
  • the data processing control circuit 203 can be implemented as a microcontroller, a central processing unit (Central Processing Unit, CPU), a digital signal processor, etc.
  • the pulse width modulation circuit 204 is also electrically connected to the drive signal generation circuit 205 and is configured to generate a pulse width modulation signal in response to the pulse width control signal and transmit the pulse width modulation signal to the drive signal generation circuit 205 .
  • the pulse width modulation signal generated by the pulse width modulation circuit 204 determines the lighting duration of the light-emitting element.
  • the effective pulse width duration is equal to the lighting duration of the light-emitting element.
  • the drive signal generation circuit 205 is also electrically connected to the output pad Out, is configured to generate a drive signal in response to the pulse width modulation signal, and outputs the drive signal from the output pad Out.
  • outputting the drive signal from the output pad Out can mean that the drive signal (for example, the drive current) flows from the output pad Out to the light-emitting element, or it can also mean that the drive signal (for example, the drive current) flows from the light-emitting element to the output pad Out.
  • the direction of the current is not restricted.
  • the driving signal generation circuit 205 may include a current source A and a transistor MOS, and the control electrode of the transistor MOS receives the pulse width modulation signal transmitted by the pulse width modulation circuit 204, thereby It is turned on or off under the control of pulse width modulation signal.
  • the first pole of the transistor MOS is connected to the output pad Out
  • the second pole of the transistor MOS is connected to the first pole of the current source A
  • the second pole of the current source A is connected to the ground pad Gnd to receive the common voltage.
  • current source A may be a constant current source.
  • the transistor MOS When the pulse width modulation signal is at a valid level, the transistor MOS is turned on, and the current source A provides the driving current through the output pad Out. When the pulse width modulation signal is at an inactive level, the transistor MOS is turned off, and the output pad Out does not provide drive current at this time.
  • the duration of the effective level of the pulse width modulation signal is equal to the conduction duration of the transistor MOS, and the conduction duration of the transistor MOS is equal to the duration of the drive current provided by the output pad Out.
  • the driving current flows from the output pad Out into the micro driver chip 002, flows through the transistor MOS and the current source A in sequence, and then flows into the ground terminal (for example, the ground pad Gnd).
  • the driving signal generation circuit 205 may also adopt other circuit structure forms, and the embodiment of the present disclosure does not limit this.
  • the drive signal generation circuit 205 and the relay signal generation circuit 206 are both electrically connected to the output pad Out, the drive signal generation circuit 205 and the relay signal generation circuit 206 are respectively in The drive signal and the relay signal are output in different time periods. The drive signal and the relay signal are transmitted in a time-shared manner through the output pad Out, so they will not affect each other.
  • the power supply circuit 207 is electrically connected to the demodulation circuit 201 and the data processing control circuit 203 respectively, and is configured to receive power and power the data processing control circuit 203 .
  • the DC power component i.e., electric energy
  • the power supply circuit 207 is provided to data processing control circuit 203.
  • the embodiments of the present disclosure are not limited thereto, and the power supply circuit 207 can also be electrically connected to other circuits in the micro driver chip 002 to provide electric energy.
  • the power supply circuit 207 can be implemented by a switching circuit, a voltage conversion circuit, a voltage stabilizing circuit, etc., and the embodiments of the present disclosure are not limited to this.
  • the micro driver chip 002 provided by the present disclosure can also include more circuits and components, and is not limited to the above-mentioned demodulation circuit 201, physical layer interface circuit 202, data processing control circuit 203, pulse width modulation circuit 204,
  • the driving signal generation circuit 205, the relay signal generation circuit 206 and the power supply circuit 207 can be determined according to the functions that need to be implemented, and the embodiments of the present disclosure are not limited to this.

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Abstract

本公开提供的布线基板及电子装置，包括衬底；第一焊盘组，位于衬底之上，第一焊盘组包括输出焊盘；恒压信号线，与第一焊盘组位于衬底的同一侧；第二焊盘组，第二焊盘组包括并联设置的多个子焊盘组，每个子焊盘组包括串联设置的多个焊盘区。

Description

布线基板及电子装置 技术领域
本公开涉及显示技术领域，尤其涉及一种布线基板及电子装置。
背景技术
微型发光二极管，其尺寸大约小于500μm，由于其具有更小的尺寸和超高的亮度、寿命长等优势，因此在显示领域使用趋势明显增大。
发明内容
本公开提供的布线基板及电子装置的具体方案如下：
一方面，本公开实施例提供了一种布线基板，包括：
衬底；
第一焊盘组，位于所述衬底之上，所述第一焊盘组包括输出焊盘；
恒压信号线，与所述第一焊盘组位于所述衬底的同一侧；
第二焊盘组，所述第二焊盘组包括并联设置的多个子焊盘组，每个所述子焊盘组包括串联设置的多个焊盘区。
在一些实施例中，在本公开实施例提供的上述布线基板中，还包括连接线，所述恒压信号线通过所述连接线与并联设置的所述多个子焊盘组耦接。
在一些实施例中，在本公开实施例提供的上述布线基板中，所述第二焊盘组为多个且在所述衬底上呈阵列排布，同一所述第二焊盘组中的全部所述焊盘区在所述衬底上呈阵列排布；
所述连接线的至少一部分位于所述第二焊盘组中至少两个所述焊盘区之间。
在一些实施例中，在本公开实施例提供的上述布线基板中，所述连接线的线宽大于所述恒压信号线的线宽。
在一些实施例中，在本公开实施例提供的上述布线基板中，所述连接线包括延伸方向与所述恒压信号线相同的第一走线部，以及延伸方向与所述恒压信号线交叉设置的第二走线部，所述第二走线部连接所述恒压信号线与所述第一走线部。
在一些实施例中，在本公开实施例提供的上述布线基板中，所述第一焊盘组在所述衬底上的正投影与所述连接线在所述衬底上的正投影互不交叠。
在一些实施例中，在本公开实施例提供的上述布线基板中，所述第二焊盘组包括并联设置的两个所述子焊盘组，其中一个所述子焊盘组包括串联设置的第一焊盘区和第二焊盘区，另一个所述子焊盘组包括串联设置的第三焊盘区和第四焊盘区。
在一些实施例中，在本公开实施例提供的上述布线基板中，所述第一焊盘区与所述第二焊盘区同列设置、并与所述第三焊盘区同行设置，所述第四焊盘区与所述第一焊盘区同行设置、并与所述第三焊盘区同列设置。
在一些实施例中，在本公开实施例提供的上述布线基板中，所述第一焊盘区与所述第二焊盘区同行设置、并与所述第三焊盘区同列设置，所述第四焊盘区与所述第二焊盘区同列设置、并与所述第三焊盘区同行设置。
在一些实施例中，在本公开实施例提供的上述布线基板中，所述第一焊盘区与所述第三焊盘区同列设置、并与所述第四焊盘区同行设置，所述第二焊盘区与所述第三焊盘区同行设置、并与所述第四焊盘区同列设置。
另一方面，本公开实施例提供了一种电子装置，包括本公开实施例提供的上述布线基板，与所述第一焊盘组耦接的微型驱动芯片，以及与所述第二焊盘组耦接的电子元件。
在一些实施例中，在本公开实施例提供的上述电子装置中，还包括多个第一透明保护结构，各所述第一透明保护结构在所述衬底上的正投影分别覆盖各所述电子元件在所述衬底上的正投影。
在一些实施例中，在本公开实施例提供的上述电子装置中，所述连接线在所述衬底上的正投影与所述第一透明保护结构在所述衬底上的正投影互不 交叠。
在一些实施例中，在本公开实施例提供的上述电子装置这种，还包括第二透明保护结构，所述第二透明保护结构在所述衬底上的正投影覆盖所述微型驱动芯片在所述衬底上的正投影。
在一些实施例中，在本公开实施例提供的上述电子装置中，所述连接线在所述衬底上的正投影与所述第二透明保护结构在所述衬底上的正投影至多部分交叠。
在一些实施例中，在本公开实施例提供的上述电子装置中，所述连接线在第一走线部与第二走线部的交汇区域具有凹部，所述第一走线部在所述衬底上的正投影、以及所述第二走线部在所述衬底上的正投影均与所述第二透明保护结构在所述衬底上的正投影互不交叠。
附图说明
图1为本公开实施例提供的布线基板的结构示意图；
图2为本公开实施例提供的布线基板中一个第一焊盘组及其耦接的一个第二焊盘组所在区的一种结构示意图；
图3为本公开实施例提供的布线基板中一个第一焊盘组及其耦接的一个第二焊盘组所在区的又一种结构示意图；
图4为本公开实施例提供的布线基板中一个第一焊盘组及其耦接的一个第二焊盘组所在区的又一种结构示意图；
图5为本公开实施例提供的电子装置中一个第一焊盘组及其耦接的一个第二焊盘组所在区的一种结构示意图；
图6为本公开实施例提供的电子装置中一个第一焊盘组及其耦接的一个第二焊盘组所在区的又一种结构示意图；
图7为本公开实施例提供的电子装置中一个第一焊盘组及其耦接的一个第二焊盘组所在区的又一种结构示意图；
图8为本公开实施例提供的电子装置中一个第一焊盘组及其耦接的一个 第二焊盘组所在区的又一种结构示意图；
图9为本公开实施例提供的微型驱动芯片的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。为了保持本公开实施例的以下说明清楚且简明，本公开省略了已知功能和已知部件的详细说明。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
微型发光二极管显示技术兼具液晶显示技术和有机发光显示技术的诸多优点，尤其是微型发光二极管显示技术应用于背光源时，能够实现更精密的动态背光效果，在有效提高屏幕亮度和对比度的同时，还能解决传统动态背光在屏幕亮暗区域之间造成的眩光现象，优化视觉体验，更适用超大屏产品。
在大尺寸电子装置中，多个电子元件和一个微型驱动芯片构成一个功能区，成千上万个功能区阵列排布。在不计算路径损耗的前提下，为保证各电子元件在额定功率下正常工作，每个功能区中的多个电子元件以串联的方式连接，则向多个电子元件提供驱动信号的微型驱动芯片的输出功率至少为I 2*R 总，其中，I为电子元件的额定电流，R 总为一个功能区内多个电子元件的 电阻总和。
本公开实施例提供了一种布线基板，如图1和图2所示，包括：
衬底101；
第一焊盘组102，位于衬底101之上，第一焊盘组102包括输出焊盘Out；
恒压信号线103，与第一焊盘组103位于衬底101的同一侧；
第二焊盘组104，第二焊盘组104包括并联设置的多个子焊盘组104'，每个子焊盘组104'包括串联设置的多个焊盘区(例如E 1和E 2、E 3和E 4)，可选地，每个焊盘区(例如E 1至E 4)至少包括第一焊盘41和第二焊盘42，在每个子焊盘组104'的串联电路上，第1个焊盘区(例如E 1或E 3)的第一焊盘41与恒压信号线103耦接，第n个焊盘区(例如E 1或E 3)的第二焊盘42与第(n+1)个焊盘区(例如E 2或E 4)的第一焊盘41耦接，最后一个焊盘区(例如E 2或E 4)的第二焊盘42与第一焊盘组102的输出焊盘Out耦接。
在本公开实施例提供的上述布线基板中，通过在一个第二焊盘组104(对应一个灯区)内，将各焊盘区(例如E 1至E 4)串联为多个子焊盘组104'，并将各子焊盘组104'进行并联，使得与各焊盘区(例如E 1至E 4)耦接的各电子元件之间是串联、并联结合的连接方式，在不计算路径损耗的前提下，为保证各电子元件在额定功率下正常工作，与第一焊盘组102耦接的微型驱动芯片的输出功率至少为
Figure PCTCN2022094141-appb-000001
其中，I为电子元件的额定电流，m为一个第二焊盘组104内所含子焊盘组104'的总数，t为大于等于1且小于等于m的整数，R m为一个子焊盘组104'内串联连接的各电子元件的电阻总和，
Figure PCTCN2022094141-appb-000002
为一个第二焊盘组104内并联连接的电子元件的电阻总和的倒数。在一个第二焊盘组104耦接的电子元件数量N不变，每个电子元件的电阻为R的情况下，
Figure PCTCN2022094141-appb-000003
为m 2/(N*R)，相关技术中R 总为N*R，因此本公开中微型驱动芯片的输出功率
Figure PCTCN2022094141-appb-000004
为(N*R*I 2)/m 2，相关技术中微型驱动芯片的输出功率I 2*R 总为 N*R*I 2。对比可见，本公开的微型驱动芯片的输出功率小于相关技术中微型驱动芯片的输出功率，由此本公开中可采用功率较小、成本较低的微型驱动芯片替代相关技术中功率较大、成本较高的微型驱动芯片，从而节约成本，提高产品竞争力。
在一些实施例中，在本公开实施例提供的上述布线基板中，如图1和图2所示，还可以包括连接线105，恒压信号线103通过连接线105与并联设置的多个子焊盘组104'耦接，可选地，恒压信号线103通过连接线105与各子焊盘组104'中各第1个焊盘区(例如E 1和E 3)的第一焊盘41连接，使得恒压信号线103提供的恒压信号通过连接线105传递至各子焊盘组104'中各第1个焊盘区(例如E 1和E 3)的第一焊盘41。
在一些实施例中，在本公开实施例提供的上述布线基板中，如图1和图2所示，第二焊盘组104为多个(图中仅示出了2*2个)且在衬底101上呈阵列排布，同一第二焊盘组104中的全部焊盘区(例如E 1至E 4)在衬底101上呈阵列排布；连接线105的至少一部分位于第二焊盘组104中至少两个焊盘区(例如E 1至E 4)之间，以合理利用焊盘区(例如E 1至E 4)之间的空间进行布线。
在一些实施例中，在本公开实施例提供的上述布线基板中，如图1和图2所示，为降低恒压信号线103提供的恒压信号在传输路径上的损耗，可充分利用焊盘区(例如E 1至E 4)之间的空间对连接线105进行布线设计，使得连接线105的线宽尽可能地大，相应地连接线105的电阻就会尽可能地小。可选地，连接线105的线宽d 1大于恒压信号线的线宽d 2。例如，连接线105的线宽d 1大于1000μm且小于等于3553μm，恒压信号线的线宽d 2大于等于1000μm且小于等于1433μm，具体地，连接线105的线宽d 1可以为1991.82μm、2000μm等，恒压信号线的线宽d 2为1000μm等。
在一些实施例中，在本公开实施例提供的上述布线基板中，如图1和图2所示，连接线105可以包括延伸方向与恒压信号线103相同的第一走线部51，以及延伸方向与恒压信号线103交叉设置的第二走线部52，第二走线部52连接恒压信号线103与第一走线部51。可选地，第一走线部51可以布设在同一第二 焊盘组104中各焊盘区(例如E 1至E 4)的列间隙处，第一走线部51的线宽d 11大于等于2000μm且小于等于3553μm，例如第一走线部51的线宽d 11为2000μm、2500μm、3000μm、3500μm等。第二走线部52可以布设在相邻第二焊盘组104的行间隙处，第二走线部52的线宽d 12大于1000μm且小于等于3200μm，例如第二走线部52的线宽d 12为1500μm、2000μm、2500μm、3000μm等。
在恒压信号线103的线宽d 2为1000μm，第一走线部51的线宽d 11为2000μm，第二走线部52的线宽d 12为1991.82μm的情况下，以恒压信号线103、第一走线部51、第二走线部52的厚度均为1.8μm、方块电阻(sheet resistance)均为0.011Ω/□为例，使用软件计算出来相关技术中恒压信号线103的总电阻为0.1851mΩ，本公开中通过第一走线部 51和第二走线部 52可实现对恒压信号线103的线宽补偿作用，计算出来恒压信号线103、第一走线部51、第二走线部52的总电阻为0.17331mΩ。可见，本公开中恒压信号传输路径上的电阻降低率为(1-0.17331/0.1851)*100＝6.4％。因此，本公开可降低恒压信号的压降，提升线路中的电学特性，增强产品均一性。
在一些实施例中，在本公开实施例提供的上述布线基板中，如图1和图2所示，第一焊盘组102在衬底101上的正投影与连接线105在衬底101上的正投影互不交叠，以使得连接线105避开第一焊盘组102，避免连接线105与第一焊盘组102短接。
在一些实施例中，在本公开实施例提供的上述布线基板中，如图2至图4所示，第二焊盘组104可以包括并联设置的两个子焊盘组104'，其中一个子焊盘组104'包括串联设置的第一焊盘区E 1和第二焊盘区E 2，另一个子焊盘组104'包括串联设置的第三焊盘区E 3和第四焊盘区E 4。可选地，在图2中，第一焊盘区E 1与第二焊盘区E 2同列设置、并与第三焊盘区E 3同行设置，第四焊盘区E 4与第一焊盘区E 1同行设置、并与第三焊盘区E 3同列设置；在图3中，第一焊盘区E 1与第二焊盘区E 2同行设置、并与第三焊盘区E 3同列设置，第四焊盘区E 4与第二焊盘区E 2同列设置、并与第三焊盘区E 3同行设置；在图4中，第一焊盘区E 1与第三焊盘区E 3同列设置、并与第四焊盘区E 4同行设置，第二焊盘区E 2 与第三焊盘区E 3同行设置、并与第四焊盘区E 4同列设置。
需要说明的是，本公开仅以第二焊盘组104包括两个子焊盘组104'，每个子焊盘组104'包括两个焊盘区为例进行说明，在具体实施时，第二焊盘组104还可以包括两个以上的子焊盘组104'，每个子焊盘组104'可以包括两个以上的焊盘区，在此不做限定。
在一些实施例中，在本公开实施例提供的上述布线基板中，如图1和图2所示，第一焊盘组102除了包括输出焊盘Out之外，还可以包括地址焊盘Di、供电焊盘Pwr和接地焊盘Gnd，其中，属于同一第一焊盘组102的地址焊盘Di与供电焊盘Pwr在行方向X上间隔设置、并与输出焊盘Out在列方向Y上间隔设置，接地焊盘Gnd与供电焊盘Pwr在列方向Y上间隔设置、并与输出焊盘Out在行方向X上间隔设置。示例性地，输出焊盘Out位于第一焊盘组102的左上角，地址焊盘Di位于第一焊盘组102的左下角，接地焊盘Gnd位于第一焊盘组102的右上角，供电焊盘Pwr位于第一焊盘组102的右下角。
可选地，每个第一焊盘组102可以与一个微型驱动芯片002耦接，每个第二焊盘组104与多个电子元件003耦接。在一些实施例中，地址焊盘Di可接收地址信号，以用于选通相应地址的微型驱动芯片002。供电焊盘Pwr可为微型驱动芯片002提供工作电压和通信数据，该通信数据可用于控制相应电子元件的工作状态。输出焊盘Out可在不同的时段内分别输出中继信号和驱动信号，可选地，中继信号为提供给下一级第一焊盘组102中的地址焊盘Di的地址信号，驱动信号为驱动电流，用于驱动与该输出焊盘Out所在第一焊盘组102耦接的电子元件。接地焊盘Gnd接收公共电压信号。
在一些实施例中，在本公开实施例提供的上述布线基板中，如图1和图2所示，在列方向Y上，各第一焊盘组102可以级联设置，可选地，同列中第1级第一焊盘组102的地址焊盘Di与地址信号线107连接，第k(k为正整数)级第一焊盘组102的输出焊盘Out和第(k+1)级第一焊盘组102的地址焊盘Di通过级联线106连接，最后一级第一焊盘组102的输出焊盘Out与反馈信号线108连接。
在一些实施例中，在本公开实施例提供的上述布线基板中，如图1和图2所示，还可以包括具有多个子段109'的电源信号线109，一个子段109'与一列中一个第一焊盘组102的供电焊盘连接，可选地，在列方向Y上相邻的两个子段109'可以通过一个连接引线110相互连接，以实现同一条电源信号线109为同列级联的多个第一焊盘组102的供电焊盘Pwr供电。可选地，连接引线110与子段109'为一体结构。
在一些实施例中，在本公开实施例提供的上述布线基板中，如图1和图2所示，还可以包括公共电压信号线111，一列中级联设置的全部第一焊盘组102的接地焊盘Gnd可以与同一条公共电压信号线111连接。
在一些实施例中，在本公开实施例提供的上述布线基板中，为减少工艺步骤，节约制作成本，恒压信号线103、级联线106、地址信号线107、反馈信号线108、电源信号线109、连接引线110和公共电压信号线111可以同层设置。在本公开中，“同层”指的是采用同一成膜工艺形成用于制作特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。即一次构图工艺对应一道掩模板(mask，也称光罩)。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而所形成层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形可能处于相同的高度或者具有相同的厚度、也可能处于不同的高度或者具有不同的厚度。
在一些实施例中，在本公开实施例提供的上述布线基板中，还包括在所有线路层最远离衬底的一侧设置具有多个镂空结构的绝缘层，各镂空结构暴露出部分线路的端部以分别形成各个焊盘区(例如图1中的E 1至E 4)和第一焊盘组102。可选地，绝缘层可以采用具有高反射率的材料制作，例如白色油墨等。
基于同一发明构思，本公开实施例提供了一种电子装置，如图5所示，包括本公开实施例提供的上述布线基板001，与第一焊盘组102耦接的微型驱动芯片002，以及与第二焊盘组104耦接的电子元件003。本公开实施例提供的该电子装置的具体实施可以参见本公开实施例提供的上述布线基板的具体实施， 重复之处不再赘述。可选地，微型驱动芯片002在衬底101上的正投影面积不大于300000μm 2；电子元件003为发光元件，发光元件的发光面积不超过300000μm 2，具体的，可以不超过40000μm 2，发光元件具有两个引脚，每个焊盘区(例如E1至E4)包括第一焊盘41和第二焊盘42，分别与发光元件的两个引脚对应连接。可以理解的是，电子元件003为其他元件时，其可以具有其他数目的引脚，相应的，每个焊盘区(例如E1至E4)具有与元件的引脚具有相同数目的焊盘。
在一些实施例中，在本公开实施例提供的上述电子装置中，如图5至图7所示，还可以包括多个第一透明保护结构112，各第一透明保护结构112在衬底101上的正投影分别覆盖各电子元件003在衬底101上的正投影，以通过第一透明保护结构112保护各电子元件003，并且在电子元件003为发光元件的情况下，第一透明保护结构112还可起到提升光效的作用。
在一些实施例中，可通过点胶或钢网印刷的方式制作第一透明保护结构112。可选地，为实现较好的保护效果并有效提高光效，第一透明保护结构112可在电子元件003(例如发光元件)之上形成穹顶形状，这种形状的第一透明保护结构112可被称为液滴透镜(Lens)，第一透明保护结构112在衬底101上的正投影半径r可为1450μm。但考虑到实际制作第一透明保护结构112时会有偏差，例如偏差可在±150μm以内，也就是说，第一透明保护结构112在衬底101上的正投影最大半径r max为1600μm、最小半径r min为1400μm。
在一些实施例中，在本公开实施例提供的上述电子装置中，如图5至图7所示，第二焊盘组104内各焊盘区E之间的空间足够大，可有效保证连接线105的线宽满足压降需求，因此，连接线105在衬底101上的正投影可以与第一透明保护结构112在衬底110上的正投影互不交叠，以避免连接线105被第一透明保护结构112粘附，在生产运输等过程中第一透明保护结构112受到剐蹭而意外带动连接线105，导致连接线105脱落的现象。可选地，连接线105在衬底101上的正投影与第一透明保护结构112在衬底101上的最大正投影(例如正投影半径为1600μm)之间的距离大于等于50μm。
在一些实施例中，在本公开实施例提供的上述电子装置中，如图5至图7所示，还可以包括第二透明保护结构113，第二透明保护结构113在衬底101上的正投影覆盖微型驱动芯片002在衬底101上的正投影，以通过第二透明保护结构113保护微型驱动芯片002。为了便于制作，第二透明保护结构113与第一透明保护结构112的制作要求可以相同，且二者在同一次工艺流程中形成。
在一些实施例中，在本公开实施例提供的上述电子装置中，如图5至图8所示，连接线105在衬底101上的正投影与第二透明保护结构113在衬底101上的正投影至多部分交叠，以降低避免连接线105被第二透明保护结构113粘附，在生产运输等过程中第二透明保护结构113受到剐蹭而意外带动连接线105，导致连接线105脱落的风险。可选地，连接线105在衬底101上的正投影与第二透明保护结构113的最小正投影(例如正投影半径为1400μm)的距离小于等于50μm，且与微型驱动芯片002的固晶标识v的距离大于等于40μm。
在一些实施例中，在本公开实施例提供的上述电子装置中，若相邻第二焊盘组104之间的空间足够大，可有效保证连接线105的线宽满足压降需求，可以设置连接线105在第一走线部51与第二走线部52的交汇区域具有凹部C，第一走线部51在衬底101上的正投影、以及第二走线部52在衬底101上的正投影均与第二透明保护结构113在衬底101上的正投影互不交叠，这样连接线105就可以在凹部C处避开第二透明结构113。
在一些示例中，如图9所示，微型驱动芯片002可以包括解调电路201、物理层接口电路202、数据处理控制电路203、脉宽调制电路204、驱动信号生成电路205、中继信号生成电路206和电源供给电路207。
在一些实施例中，解调电路201与供电焊盘Pwr和物理层接口电路202电连接，被配置为对供电焊盘Pwr输入的电力线载波通信信号进行解调以得到通信数据，并将该通信数据传输至物理层接口电路。在电子元件003为发光元件的情况下，通信数据可为反映发光时长的数据，进而代表了所需要的发光亮度。相比于通常的串行外设接口(Serial Peripheral Interface，SPI)协议，本公开实施例通过采用电力线载波通信(Power Line Carrier  Communication，PLC)协议，将通信数据叠加在电源信号上，可有效减少信号线的数量。
在一些实施例中，物理层接口电路202还与数据处理控制电路203电连接，被配置为对通信数据进行处理以得到数据帧(例如帧频数据)，并将数据帧传输至数据处理控制电路203。物理层接口电路202得到的数据帧包含了需要传输给该微型驱动芯片002的信息，例如与发光时间相关的信息(例如发光时间的具体时长)。可选地，物理层接口电路202为通常的端口物理层(Physical，PHY)，详细说明可参考常规设计，此处不再详述。
在一些实施例中，数据处理控制电路203还与地址焊盘Di、脉宽调制电路204和中继信号生成电路206电连接。数据处理控制电路203被配置为基于数据帧产生脉宽控制信号并将该脉宽控制信号传输至脉宽调制电路204，以及基于地址信号产生中继控制信号并将该中继控制信号传输至中继信号生成电路206。例如，根据数据帧可以获知与该微型驱动芯片002相连的发光元件所需要的发光时长，因此基于该发光时长产生对应的脉宽控制信号。例如，中继控制信号为数据处理控制电路203对第一输入信号处理之后产生的信号。通过对地址信号进行处理(例如解析、锁存、译码等)，可以获知对应于该微型驱动芯片002的地址信号，并且会产生对应于后续地址的中继控制信号，该后续地址对应于其他微型驱动芯片002。可选地，数据处理控制电路203可以实现为单片机、中央处理器(Central Processing Unit，CPU)、数字信号处理器等。
在一些实施例中，脉宽调制电路204还与驱动信号生成电路205电连接，被配置为响应于脉宽控制信号产生脉冲宽度调制信号，并将脉冲宽度调制信号传输至驱动信号生成电路205。例如，脉宽调制电路204产生的脉冲宽度调制信号决定了发光元件的发光时长，例如有效脉宽时长等于发光元件的发光时长。
在一些实施例中，驱动信号生成电路205还与输出焊盘Out电连接，被配置为响应于脉冲宽度调制信号产生驱动信号，并将该驱动信号从输出焊盘 Out输出。这里，将驱动信号从输出焊盘Out输出，可以表示驱动信号(例如驱动电流)从输出焊盘Out流向发光元件，也可以表示驱动信号(例如驱动电流)从发光元件流入输出焊盘Out，具体的电流方向不受限制。
示例性地，在一些示例中，当驱动信号为驱动电流时，驱动信号生成电路205可以包括电流源A和晶体管MOS，晶体管MOS的控制极接收脉宽调制电路204传输的脉冲宽度调制信号，从而在脉冲宽度调制信号的控制下导通或截止。晶体管MOS的第一极与输出焊盘Out连接，晶体管MOS的第二极与电流源A的第一极连接，电流源A的第二极与接地焊盘Gnd连接以接收公共电压。可选的地，电流源A可以为恒流源。当脉冲宽度调制信号为有效电平时，晶体管MOS导通，电流源A通过输出焊盘Out提供驱动电流。当脉冲宽度调制信号为无效电平时，晶体管MOS截止，此时输出焊盘Out不提供驱动电流。脉冲宽度调制信号的有效电平的时长等于晶体管MOS的导通时长，晶体管MOS的导通时长等于输出焊盘Out提供驱动电流的时长。由此，可以进一步控制发光元件的发光时长，进而控制视觉上的发光亮度。在一些实施例中，当晶体管MOS导通时，驱动电流从输出焊盘Out流入微型驱动芯片002，并依次流经晶体管MOS和电流源A，然后流入接地端(例如接地焊盘Gnd)。需要说明的是，本公开的实施例中，驱动信号生成电路205还可以采用其他电路结构形式，本公开的实施例对此不作限制。
在一些实施例中，中继信号生成电路206还与输出焊盘Out电连接，被配置为基于中继控制信号生成中继信号，并将中继信号从输出焊盘Out输出。例如，中继控制信号对应于后续地址，基于中继控制信号产生的中继信号包含了后续地址，该后续地址对应于其他微型驱动芯片002。中继信号从输出焊盘Out输出后，被提供给下一级联的微型驱动芯片002的地址焊盘Di，从而使下一级联的微型驱动芯片002获取对应的地址信号。中继信号生成电路206可以通过锁存器、译码器、编码器等实现，本公开的实施例对此不作限制。
要说明的是，本公开的实施例中，虽然驱动信号生成电路205和中继信号生成电路206均与输出焊盘Out电连接，但是，驱动信号生成电路205和 中继信号生成电路206分别在不同的时段输出驱动信号和中继信号，驱动信号和中继信号通过输出焊盘Out分时传输，因此不会彼此影响。
在一些实施例中，电源供给电路207分别与解调电路201和数据处理控制电路203电连接，被配置为接收电能并给数据处理控制电路203供电。在一些实施例中，解调电路201对供电焊盘Pwr输入的电力线载波通信信号进行解调后，电力线载波通信信号中的直流电源成分(即电能)传输至电源供给电路207，再由电源供给电路207提供给数据处理控制电路203。当然，本公开的实施例不限于此，电源供给电路207还可以与微型驱动芯片002中的其他电路电连接以提供电能。电源供给电路207可以通过开关电路、电压转换电路、稳压电路等实现，本公开的实施例对此不作限制。
需要说明的是，本公开提供的微型驱动芯片002还可以包括更多的电路和部件，不限于上述的解调电路201、物理层接口电路202、数据处理控制电路203、脉宽调制电路204、驱动信号生成电路205、中继信号生成电路206和电源供给电路207，这可以根据需要实现的功能而定，本公开的实施例对此不作限制。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (16)

  1. 一种布线基板，其中，包括：
    衬底；
    第一焊盘组，位于所述衬底之上，所述第一焊盘组包括输出焊盘；
    恒压信号线，与所述第一焊盘组位于所述衬底的同一侧；
    第二焊盘组，所述第二焊盘组包括并联设置的多个子焊盘组，每个所述子焊盘组包括串联设置的多个焊盘区。
  2. 如权利要求1所述的布线基板，其中，还包括连接线，所述恒压信号线通过所述连接线与并联设置的所述多个子焊盘组耦接。
  3. 如权利要求2所述的布线基板，其中，所述第二焊盘组为多个且在所述衬底上呈阵列排布，同一所述第二焊盘组中的全部所述焊盘区在所述衬底上呈阵列排布；
    所述连接线的至少一部分位于所述第二焊盘组中至少两个所述焊盘区之间。
  4. 如权利要求3所述的布线基板，其中，所述连接线的线宽大于所述恒压信号线的线宽。
  5. 如权利要求2～4任一项所述的布线基板，其中，所述连接线包括延伸方向与所述恒压信号线相同的第一走线部，以及延伸方向与所述恒压信号线交叉设置的第二走线部，所述第二走线部连接所述恒压信号线与所述第一走线部。
  6. 如权利要求2～5任一项所述的布线基板，其中，所述第一焊盘组在所述衬底上的正投影与所述连接线在所述衬底上的正投影互不交叠。
  7. 如权利要求1～6任一项所述的布线基板，其中，所述第二焊盘组包括并联设置的两个所述子焊盘组，其中一个所述子焊盘组包括串联设置的第一焊盘区和第二焊盘区，另一个所述子焊盘组包括串联设置的第三焊盘区和第四焊盘区。
  8. 如权利要求7所述的布线基板，其中，所述第一焊盘区与所述第二焊盘区同列设置、并与所述第三焊盘区同行设置，所述第四焊盘区与所述第一焊盘区同行设置、并与所述第三焊盘区同列设置。
  9. 如权利要求7所述的布线基板，其中，所述第一焊盘区与所述第二焊盘区同行设置、并与所述第三焊盘区同列设置，所述第四焊盘区与所述第二焊盘区同列设置、并与所述第三焊盘区同行设置。
  10. 如权利要求7所述的布线基板，其中，所述第一焊盘区与所述第三焊盘区同列设置、并与所述第四焊盘区同行设置，所述第二焊盘区与所述第三焊盘区同行设置、并与所述第四焊盘区同列设置。
  11. 一种电子装置，其中，包括如权利要求1～10任一项所述的布线基板，与所述第一焊盘组耦接的驱动芯片，以及与所述第二焊盘组耦接的电子元件。
  12. 如权利要求11所述的电子装置，其中，还包括多个第一透明保护结构，各所述第一透明保护结构在所述衬底上的正投影分别覆盖各所述电子元件在所述衬底上的正投影。
  13. 如权利要求12所述的电子装置，其中，所述连接线在所述衬底上的正投影与所述第一透明保护结构在所述衬底上的正投影互不交叠。
  14. 如权利要求11～13任一项所述的电子装置，其中，还包括第二透明保护结构，所述第二透明保护结构在所述衬底上的正投影覆盖所述微型驱动芯片在所述衬底上的正投影。
  15. 如权利要求14所述的电子装置，其中，所述连接线在所述衬底上的正投影与所述第二透明保护结构在所述衬底上的正投影至多部分交叠。
  16. 如权利要求15所述的电子装置，其中，所述连接线在第一走线部与第二走线部的交汇区域具有凹部，所述第一走线部在所述衬底上的正投影、以及所述第二走线部在所述衬底上的正投影均与所述第二透明保护结构在所述衬底上的正投影互不交叠。
PCT/CN2022/094141 2022-05-20 2022-05-20 布线基板及电子装置 WO2023221096A1 (zh)

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US20180084614A1 (en) * 2016-09-22 2018-03-22 X-Celeprint Limited Multi-led components
CN113964112A (zh) * 2021-10-25 2022-01-21 京东方科技集团股份有限公司 发光基板及显示装置
CN114171661A (zh) * 2020-09-10 2022-03-11 京东方科技集团股份有限公司 一种发光基板、显示装置及制作方法
CN114280841A (zh) * 2020-09-27 2022-04-05 合肥鑫晟光电科技有限公司 一种发光基板及显示装置
CN114442353A (zh) * 2020-10-30 2022-05-06 京东方科技集团股份有限公司 驱动背板及其制备方法和显示面板

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US20180084614A1 (en) * 2016-09-22 2018-03-22 X-Celeprint Limited Multi-led components
CN114171661A (zh) * 2020-09-10 2022-03-11 京东方科技集团股份有限公司 一种发光基板、显示装置及制作方法
CN114280841A (zh) * 2020-09-27 2022-04-05 合肥鑫晟光电科技有限公司 一种发光基板及显示装置
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