WO2023218943A1

WO2023218943A1 - Semiconductor device

Info

Publication number: WO2023218943A1
Application number: PCT/JP2023/016282
Authority: WO
Inventors: 沢水神田
Original assignee: ローム株式会社
Priority date: 2022-05-09
Filing date: 2023-04-25
Publication date: 2023-11-16

Abstract

A semiconductor device according to the present invention comprises a first semiconductor element, a second semiconductor element, first to third power terminals, first and second signal terminals, and a sealing resin. The first power terminal and the first signal terminal are electrically connected to the first semiconductor element. The second power terminal and the second signal terminal are electrically connected to the second semiconductor element. The third power terminal is electrically connected to the first semiconductor element and the second semiconductor element. The sealing resin has a first lateral surface and a second lateral surface, which face opposite directions in a second direction. The first power terminal and the second power terminal protrude from the first lateral surface. The third power terminal protrudes from the second lateral surface. The first power terminal and the second power terminal are separated from each other in a third direction.

Description

semiconductor equipment

The present disclosure relates to a semiconductor device.

Patent Document 1 discloses an example of a semiconductor device equipped with two power semiconductor elements (for example, IGBT). The semiconductor device is used in a power conversion device such as an inverter. The semiconductor device is surface mounted on a wiring board.

The semiconductor device disclosed in Patent Document 1 includes a plurality of power supply terminals and a plurality of control terminals. A plurality of power supply terminals and a plurality of control terminals protrude outside from a housing that covers the two power semiconductor elements. In each of these terminals, a portion protruding outward from the housing is bent into a gull wing shape to enable surface mounting. Here, when attempting to miniaturize the semiconductor device, the mutual spacing between the plurality of power supply terminals is further reduced. On the other hand, the semiconductor device has parasitic inductance. Therefore, among multiple power supply terminals, there is a concern that power loss at the terminal where DC current flows will increase due to mutual induction between the terminal where AC current flows and the adjacent terminal where DC current flows. .

Japanese Patent Application Publication No. 2012-244176

An object of the present disclosure is to provide a semiconductor device that is improved over conventional ones. In particular, in view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that can reduce parasitic inductance in the device while reducing the size of the device.

A semiconductor device provided by a first aspect of the present disclosure includes a first semiconductor element, a second semiconductor element, a first power terminal and a first signal terminal electrically connected to the first semiconductor element, and a first semiconductor element and a first signal terminal that are electrically connected to the first semiconductor element. a second power terminal and a second signal terminal that are electrically connected to the element; a third power terminal that is electrically conductive to the first semiconductor element and the second semiconductor element; and a seal that covers the first semiconductor element and the second semiconductor element. and a resin. The sealing resin has a bottom surface facing in a first direction, and first and second side surfaces facing oppositely to each other in a second direction perpendicular to the first direction. Each of the first power terminal, the second power terminal, and the third power terminal has a first mounting surface facing the same side as the bottom surface in the first direction. Each of the first signal terminal and the second signal terminal has a second mounting surface facing the same side as the bottom surface in the first direction. The positions of the first mounting surface and the second mounting surface in the first direction are closer to the bottom surface than to the first semiconductor element and the second semiconductor element. The first power terminal and the second power terminal protrude from the first side surface. The third power terminal protrudes from the second side surface. Each of the first signal terminal and the second signal terminal protrudes from either the first side surface or the second side surface. The first power terminal and the second power terminal are separated from each other in a third direction orthogonal to the first direction and the second direction.

According to the above configuration, it is possible to reduce the parasitic inductance in the semiconductor device while reducing the size of the semiconductor device.

Other features and advantages of the present disclosure will become more apparent from the detailed description given below with reference to the accompanying drawings.

FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a bottom view of the semiconductor device shown in FIG. 1. FIG. 3 is a bottom view corresponding to FIG. 2, through which the sealing resin is seen. FIG. 4 is a front view of the semiconductor device shown in FIG. 1. FIG. 5 is a rear view of the semiconductor device shown in FIG. 1. FIG. 6 is a right side view of the semiconductor device shown in FIG. 1. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. FIG. 10 is a partially enlarged view of FIG. 7. FIG. 11 is a plan view of a semiconductor device according to a second embodiment of the present disclosure. FIG. 12 is a bottom view of the semiconductor device shown in FIG. 11. FIG. 13 is a bottom view corresponding to FIG. 12, through which the sealing resin is seen. FIG. 14 is a front view of the semiconductor device shown in FIG. 11. FIG. 15 is a rear view of the semiconductor device shown in FIG. 11. FIG. 16 is a plan view of a semiconductor device according to a third embodiment of the present disclosure. FIG. 17 is a bottom view of the semiconductor device shown in FIG. 16. FIG. 18 is a bottom view corresponding to FIG. 17, in which the sealing resin is seen through. FIG. 19 is a front view of the semiconductor device shown in FIG. 16. FIG. 20 is a rear view of the semiconductor device shown in FIG. 16. FIG. 21 is a plan view of a semiconductor device according to a fourth embodiment of the present disclosure. 22 is a bottom view of the semiconductor device shown in FIG. 21. 23 is a front view of the semiconductor device shown in FIG. 21. FIG. 24 is a rear view of the semiconductor device shown in FIG. 21. FIG. 25 is a right side view of the semiconductor device shown in FIG. 21. FIG. 26 is a cross-sectional view taken along line XXVI-XXVI in FIG. 22. FIG. 27 is a plan view of a semiconductor device according to a fifth embodiment of the present disclosure. FIG. 28 is a bottom view of the semiconductor device shown in FIG. 27. FIG. 29 is a plan view of a semiconductor device according to a sixth embodiment of the present disclosure. FIG. 30 is a bottom view of the semiconductor device shown in FIG. 29.

A mode for carrying out the present disclosure will be described based on the accompanying drawings.

First embodiment:
A semiconductor device A10 according to a first embodiment of the present disclosure will be described based on FIGS. 1 to 10. The semiconductor device A10 is used in electronic equipment including a power conversion circuit such as an inverter. The semiconductor device A10 includes a support member 10, two semiconductor elements 20, a plurality of power terminals 30, a plurality of first signal terminals 31, a plurality of second signal terminals 32, two conductive members 40, and two gate wires 41, 2. The detection wire 42 and the sealing resin 50 are provided. Here, in FIG. 3, for convenience of understanding, the sealing resin 50 is shown. In FIG. 3, the outline of the transparent sealing resin 50 is shown by an imaginary line (two-dot chain line).

In the description of the semiconductor device A10, for convenience, the normal direction of the bottom surface 52 of the sealing resin 50, which will be described later, will be referred to as a "first direction z." One direction perpendicular to the first direction z is called a "second direction x." A direction perpendicular to both the first direction z and the second direction x is referred to as a "third direction y."

The semiconductor device A10 converts the DC power supply voltage applied to the first power terminal 30A and the second power terminal 30B (see FIGS. 1 and 2) among the plurality of power terminals 30 into AC power using the two semiconductor elements 20. Convert. The converted AC power is input from a third power terminal 30C (see FIGS. 1 and 2) among the plurality of power terminals 30 to a power supply target such as a motor. The semiconductor device A10 is surface mounted on a wiring board.

The sealing resin 50 covers the two semiconductor elements 20, as shown in FIGS. 2, 7, and 8. Furthermore, the sealing resin 50 covers the support member 10 excluding the heat dissipation layer 16, the two conductive members 40, the two gate wires 41, and the two detection wires 42. The sealing resin 50 has electrical insulation properties. The sealing resin 50 is made of a material containing, for example, a black epoxy resin. As shown in FIGS. 1 and 2, the sealing resin 50 has a top surface 51, a bottom surface 52, a first side surface 53, a second side surface 54, and two third side surfaces 55. The outer edge 501 shown in FIG. 1 corresponds to the outline of the sealing resin 50 when viewed in the first direction z.

As shown in FIGS. 4 to 9, the top surface 51 and the bottom surface 52 face oppositely to each other in the first direction z.

As shown in FIGS. 1, 2, and 6, the first side surface 53 and the second side surface 54 face opposite to each other in the second direction x. The first side surface 53 and the second side surface 54 are connected to the top surface 51 and the bottom surface 52. Each of the first side surface 53 and the second side surface 54 includes a region connected to the bottom surface 52 and facing in the second direction x, and a region connected to the top surface 51 and inclined with respect to the top surface 51.

As shown in FIGS. 1, 2, 4, and 5, the two third side surfaces 55 face oppositely to each other in the third direction y. The two third side surfaces 55 are connected to the top surface 51 and the bottom surface 52. Each of the two third side surfaces 55 includes a region connected to the bottom surface 52 and facing in the third direction y, and a region connected to the top surface 51 and inclined with respect to the top surface 51.

The support member 10 has two semiconductor elements 20 mounted thereon, as shown in FIGS. 3 and 9. As shown in FIGS. 1 and 3, the support member 10 includes an insulating layer 11, a first conductive layer 12, a second conductive layer 13, a third conductive layer 14, a plurality of pad layers 15, and a heat dissipation layer 16.

As shown in FIGS. 1 and 3, the insulating layer 11 is located between the first conductive layer 12 and the second conductive layer 13 and the heat dissipation layer 16 in the first direction z. The material for the insulating layer 11 is preferably one with relatively high thermal conductivity. Therefore, the insulating layer 11 is made of a material containing aluminum nitride (AlN) in its composition, for example. As shown in FIGS. 7 to 9, the ends of the insulating layer 11 in the direction perpendicular to the first direction z are sandwiched between the sealing resin 50 in the first direction z.

As shown in FIGS. 1 and 3, the first conductive layer 12, the second conductive layer 13, the third conductive layer 14, and the plurality of pad layers 15 are connected to the heat dissipation layer 16 with respect to the insulating layer 11 in the first direction z. located on the opposite side. The first conductive layer 12 and the second conductive layer 13 are located between the two semiconductor elements 20 and the insulating layer 11 in the first direction z. Each of the first conductive layer 12 , the second conductive layer 13 , the third conductive layer 14 , and the plurality of pad layers 15 is electrically connected to at least one of the two semiconductor elements 20 . The compositions of the first conductive layer 12, the second conductive layer 13, the third conductive layer 14, and the plurality of pad layers 15 include copper (Cu). The first conductive layer 12 is located on one side in the third direction y. The second conductive layer 13 is located next to the first conductive layer 12 in the third direction y. The third conductive layer 14 is sandwiched between the first conductive layer 12 and the second conductive layer 13 in the third direction y. The plurality of pad layers 15 are located on the opposite side of the third conductive layer 14 with respect to the first conductive layer 12 and the second conductive layer 13 in the second direction x. The plurality of pad layers 15 are arranged along the third direction y.

As shown in FIG. 9, the heat dissipation layer 16 is located on the opposite side of the first conductive layer 12 and the second conductive layer 13 with respect to the insulating layer 11 in the first direction z. The heat dissipation layer 16 is exposed from the top surface 51 of the sealing resin 50. The composition of the heat dissipation layer 16 includes copper. As shown in FIG. 1, the heat dissipation layer 16 completely overlaps each of the two semiconductor elements 20. As shown in FIG.

As shown in FIG. 9, the two semiconductor elements 20 are located between the bottom surface 52 of the sealing resin 50 and the support member 10 in the first direction z. As shown in FIGS. 3 and 9, the two semiconductor elements 20 are individually conductively bonded to the first conductive layer 12 and the second conductive layer 13 of the support member 10 via a bonding layer 29. Bonding layer 29 is, for example, solder. In addition, the bonding layer 29 may be a sintered metal containing silver (Ag) or the like. In the semiconductor device A10, the two semiconductor elements 20 are n-channel type MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) with a vertical structure. The two semiconductor elements 20 include compound semiconductor substrates. The main material of the compound semiconductor substrate is silicon carbide (SiC). In addition, silicon (Si) may be used as the main material of the compound semiconductor substrate. In addition, the two semiconductor elements 20 may be other switching elements such as IGBTs (Insulated Gate Bipolar Transistors). Furthermore, the number of semiconductor elements 20 in the semiconductor device A10 is just an example, and the number can be set freely.

As shown in FIG. 10, each of the two semiconductor elements 20 has a first electrode 21, a second electrode 22, and a gate electrode 23. The first electrode 21 is provided facing either the first conductive layer 12 or the second conductive layer 13 of the support member 10 . A current corresponding to the power before being converted by the semiconductor element 20 flows through the first electrode 21 . That is, the first electrode 21 corresponds to a drain electrode.

As shown in FIG. 10, the second electrode 22 is provided on the opposite side to the first electrode 21 in the first direction z. A current corresponding to the power converted by the semiconductor element 20 flows through the second electrode 22 . That is, the second electrode 22 corresponds to a source electrode.

As shown in FIG. 10, the gate electrode 23 is provided on the opposite side to the first electrode 21 in the first direction z, and is located away from the second electrode 22. A gate voltage for driving the semiconductor element 20 is applied to the gate electrode 23 . As shown in FIG. 3, the area of the gate electrode 23 is smaller than the area of the second electrode 22 when viewed in the first direction z.

As shown in FIGS. 3 and 9, the two semiconductor elements 20 include a first semiconductor element 20A and a second semiconductor element 20B. The first electrode 21 of the first semiconductor element 20A is conductively bonded to the first conductive layer 12 of the support member 10 via the bonding layer 29. Thereby, the first semiconductor element 20A is electrically connected to the first conductive layer 12. The first electrode 21 of the second semiconductor element 20B is conductively bonded to the second conductive layer 13 via the bonding layer 29. Thereby, the second semiconductor element 20B is electrically connected to the second conductive layer 13.

As shown in FIGS. 7 and 8, the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 are connected to the bottom surface 52 of the sealing resin 50 and the support member 10 in the first direction z. located between. As shown in FIG. 2, the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 are exposed from the bottom surface 52.

As shown in FIG. 1, when viewed in the first direction z, each of the plurality of power terminals 30, each of the plurality of first signal terminals 31, and each of the plurality of second signal terminals 32 are sealed with a sealing resin. It intersects with the outer edge 501 of 50. When viewed in the first direction z, each of the plurality of power terminals 30 , each of the plurality of first signal terminals 31 , and each of the plurality of second signal terminals 32 protrudes from the support member 10 . The compositions of the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 include copper. In the semiconductor device A10, the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 are metal leads.

As shown in FIGS. 1 to 3, the plurality of power terminals 30 include a first power terminal 30A, a second power terminal 30B, and a third power terminal 30C. As shown in FIGS. 2, 7, and 8, the first power terminal 30A and the second power terminal 30B protrude from the first side surface 53 of the sealing resin 50. As shown in FIG. 2, the third power terminal 30C protrudes from the second side surface 54 of the sealing resin 50. The first power terminal 30A, the second power terminal 30B, and the third power terminal 30C are located on opposite sides of the two semiconductor elements 20 in the second direction x. The first power terminal 30A and the second power terminal 30B are separated from each other in the third direction y. In the semiconductor device A10, the second power terminal 30B is located next to the first power terminal 30A in the third direction y.

As shown in FIGS. 3 and 7, the first power terminal 30A is conductively bonded to the first conductive layer 12 of the support member 10. Thereby, the first power terminal 30A is electrically connected to the first semiconductor element 20A. As shown in FIGS. 3 and 8, the second power terminal 30B is conductively bonded to the third conductive layer 14 of the support member 10. As shown in FIGS. As shown in FIG. 3, the third power terminal 30C is conductively bonded to the second conductive layer 13 of the support member 10. Thereby, the third power terminal 30C is electrically connected to the second semiconductor element 20B.

As shown in FIGS. 1 to 3, the plurality of first signal terminals 31 are located on the opposite side from the plurality of second signal terminals 32 with respect to the third power terminal 30C in the third direction y. As shown in FIGS. 2 and 7, the plurality of first signal terminals 31 protrude from the second side surface 54 of the sealing resin 50. The plurality of first signal terminals 31 include a first gate terminal 31A, a first detection terminal 31B, and a second detection terminal 31C. Each of the plurality of first signal terminals 31 is electrically connected to the first semiconductor element 20A. Among the plurality of first signal terminals 31, the first gate terminal 31A is located closest to the third power terminal 30C. The first detection terminal 31B is located between the first gate terminal 31A and the second detection terminal 31C in the third direction y.

As shown in FIG. 3, the first gate terminal 31A and the first detection terminal 31B are individually conductively bonded to any two of the plurality of pad layers 15 of the support member 10. The second detection terminal 31C is conductively bonded to the first conductive layer 12 of the support member 10. A gate voltage for driving the first semiconductor element 20A is applied to the first gate terminal 31A. A voltage equal to the potential applied to the second electrode 22 of the first semiconductor element 20A is applied to the first detection terminal 31B. A voltage equal to the potential applied to the first electrode 21 of the first semiconductor element 20A is applied to the second detection terminal 31C.

As shown in FIGS. 2 and 8, the plurality of second signal terminals 32 protrude from the second side surface 54 of the sealing resin 50. As shown in FIGS. 1 to 3, the plurality of second signal terminals 32 include a second gate terminal 32A, a third detection terminal 32B, and a fourth detection terminal 32C. Each of the plurality of second signal terminals 32 is electrically connected to the second semiconductor element 20B. Among the plurality of second signal terminals 32, the second gate terminal 32A is located closest to the third power terminal 30C. The third detection terminal 32B is located between the second gate terminal 32A and the fourth detection terminal 32C in the third direction y.

As shown in FIG. 3, the second gate terminal 32A and the third detection terminal 32B are individually conductively bonded to any two of the plurality of pad layers 15 of the support member 10. The fourth detection terminal 32C is electrically conductively bonded to the first conductive layer 12 of the support member 10. A gate voltage for driving the second semiconductor element 20B is applied to the second gate terminal 32A. A voltage equal to the potential applied to the second electrode 22 of the second semiconductor element 20B is applied to the third detection terminal 32B. A voltage equal to the potential applied to the first electrode 21 of the second semiconductor element 20B is applied to the fourth detection terminal 32C.

As shown in FIGS. 2, 7, and 8, each of the plurality of power terminals 30 has a first mounting surface 33. The position of the first mounting surface 33 in the first direction z is closer to the bottom surface 52 of the sealing resin 50 than to the first semiconductor element 20A and the second semiconductor element 20B. The first mounting surface 33 is exposed from the bottom surface 52. The first mounting surface 33 extends in the second direction x. The first mounting surface 33 includes a region protruding from either the first side surface 53 or the second side surface 54 of the sealing resin 50.

As shown in FIGS. 2, 7, and 8, each of the plurality of first signal terminals 31 and the plurality of second signal terminals 32 has a second mounting surface 34. The position of the second mounting surface 34 in the first direction z is closer to the bottom surface 52 of the sealing resin 50 than to the first semiconductor element 20A and the second semiconductor element 20B. The second mounting surface 34 is exposed from the bottom surface 52. The second mounting surface 34 extends in the second direction x. The second mounting surface 34 includes a region protruding from the second side surface 54 of the sealing resin 50.

As shown in FIG. 3, FIG. 7, and FIG. It has a section 36 and an intermediate section 37.

As shown in FIG. 3, FIG. 7, and FIG. Conductively bonded. The joint portion 35 is sandwiched between the sealing resin 50 and the support member 10. The mounting portion 36 is separated from the joining portion 35 in the first direction z. The mounting portion 36 is exposed from the bottom surface 52 of the sealing resin 50. The intermediate portion 37 connects the joint portion 35 and the mounting portion 36.

As shown in FIGS. 3, 7, and 8, the mounting portion 36 is located on the opposite side of the joint portion 35 with respect to the intermediate portion 37 in the second direction x. Each mounting portion 36 of the plurality of power terminals 30 includes a first mounting surface 33 . Each mounting portion 36 of the plurality of first signal terminals 31 and the plurality of second signal terminals 32 includes a second mounting surface 34. The intermediate portion 37 is inclined with respect to the mounting portion 36 such that the further away from the mounting portion 36 in the first direction z, the closer to the joint portion 35 in the second direction x.

As shown in FIG. 3, the two conductive members 40 are individually conductively bonded to the two semiconductor elements 20 and the second conductive layer 13 and the third conductive layer 14 of the support member 10. The two conductive members 40 include a first member 40A and a second member 40B. Each of the first member 40A and the second member 40B consists of a plurality of wires. The composition of the plurality of wires includes aluminum (Al). In addition, the composition of the plurality of wires may include copper. Furthermore, each of the first member 40A and the second member 40B may be a metal clip instead of the plurality of wires.

As shown in FIG. 3, the first member 40A is conductively bonded to the second electrode 22 of the first semiconductor element 20A and the second conductive layer 13 of the support member 10. Thereby, the first semiconductor element 20A is electrically connected to the second semiconductor element 20B and the third power terminal 30C among the plurality of power terminals 30. As shown in FIG. 3, the second member 40B is conductively bonded to the second electrode 22 of the second semiconductor element 20B and the third conductive layer 14 of the support member 10. Thereby, the second power terminal 30B among the plurality of power terminals 30 is electrically connected to the second semiconductor element 20B.

Further, as described above, the first power terminal 30A among the plurality of power terminals 30 is electrically connected to the first semiconductor element 20A. The third power terminal 30C is electrically connected to the second semiconductor element 20B. Therefore, the third power terminal 30C is electrically connected to the first semiconductor element 20A and the second semiconductor element 20B. From the above, it can be said that in the semiconductor device A10, the two semiconductor elements 20 and the plurality of power terminals 30 constitute a half-bridge circuit. In this case, the first power terminal 30A corresponds to the positive electrode (P terminal). Therefore, in the first power terminal 30A, a direct current flows from the outside toward the first semiconductor element 20A. Further, the second power terminal 30B corresponds to a negative electrode (N terminal). Therefore, in the second power terminal 30B, a direct current flows outward from the second semiconductor element 20B.

As shown in FIG. 3, one of the two gate wires 41 has the gate electrode 23 of the first semiconductor element 20A and the first gate terminal 31A of the plurality of pad layers 15 of the support member 10 conductive. It is conductively bonded to the bonded pad layer 15. Thereby, the first gate terminal 31A is electrically connected to the gate electrode 23 of the first semiconductor element 20A. The other gate wire 41 of the two gate wires 41 is connected to the gate electrode 23 of the second semiconductor element 20B and the pad layer 15 to which the second gate terminal 32A among the plurality of pad layers 15 of the support member 10 is conductively bonded. conductively bonded to the Thereby, the second gate terminal 32A is electrically connected to the gate electrode 23 of the second semiconductor element 20B. The composition of the two gate wires 41 includes gold (Au).

As shown in FIG. 3, one of the two detection wires 42 is connected to the second electrode 22 of the first semiconductor element 20A and the first detection terminal 31B among the plurality of pad layers 15 of the support member 10. It is conductively bonded to the pad layer 15 which is conductively bonded. Thereby, the first detection terminal 31B is electrically connected to the second electrode 22 of the first semiconductor element 20A. The other detection wire 42 of the two detection wires 42 is a pad layer 15 to which the second electrode 22 of the second semiconductor element 20B and the third detection terminal 32B among the plurality of pad layers 15 of the support member 10 are electrically bonded. and are electrically conductively bonded to each other. Thereby, the third detection terminal 32B is electrically connected to the second electrode 22 of the second semiconductor element 20B. The composition of the two sensing wires 42 includes aluminum.

Next, the effects of the semiconductor device A10 will be explained.

The semiconductor device A10 includes a first power terminal 30A and a first signal terminal 31 electrically connected to the first semiconductor element 20A, a second power terminal 30B and a second signal terminal 32 electrically connected to the second semiconductor element 20B, and a first semiconductor The third power terminal 30C is electrically connected to the element 20A and the second semiconductor element 20B. Further, the semiconductor device A10 includes a sealing resin 50 that covers the first semiconductor element 20A and the second semiconductor element 20B. The position of the first mounting surface 33 of each of the first power terminal 30A, the second power terminal 30B, and the second power terminal 30B in the first direction z, and the first signal terminal 31 and the second signal terminal 32 in the first direction z The position of each second mounting surface 34 is closer from the bottom surface 52 of the sealing resin 50 than from the first semiconductor element 20A and the second semiconductor element 20B. By adopting this configuration, surface mounting of the semiconductor device A10 on the wiring board becomes possible.

The first power terminal 30A and the second power terminal 30B protrude from the first side surface 53. The third power terminal 30C protrudes from the second side surface 54. The first power terminal 30A and the second power terminal 30B are separated from each other in the third direction y. By adopting this configuration, it is possible to improve the effect of mutual induction acting on the first power terminal 30A and the second power terminal 30B while suppressing the influence of the alternating current flowing through the third power terminal 30C. Therefore, according to this configuration, it is possible to reduce the parasitic inductance in the semiconductor device A10 while reducing the size of the semiconductor device A10.

The first signal terminal 31 of each of the first power terminal 30A, the second power terminal 30B, and the third power terminal 30C is exposed from the bottom surface 52 of the sealing resin 50. The first mounting surface 33 extends in the second direction x and includes a region protruding from either the first side surface 53 or the second side surface 54 of the sealing resin 50. With this configuration, even if the semiconductor device A10 is made smaller, the first mounting surface 33 for solder can be further enlarged when the semiconductor device A10 is mounted on a wiring board. This makes it possible to increase the bonding strength of the semiconductor device A10 to the wiring board.

The semiconductor device A10 further includes a support member 10 on which a first semiconductor element 20A and a second semiconductor element 20B are mounted. The support member 10 is exposed from the top surface 51 of the sealing resin 50. The first semiconductor element 20A, the second semiconductor element 20B, the first power terminal 30A, the second power terminal 30B, the third power terminal 30C, the first signal terminal 31, and the second signal terminal 32 are sealed in the first direction z. It is located between the bottom surface 52 of the resin 50 and the support member 10. With this configuration, in the semiconductor device A10, heat can be dissipated from the side opposite to the side where the wiring board on which the semiconductor device A10 is mounted is located in the first direction z.

In the above case, the support member 10 has the heat dissipation layer 16 exposed from the top surface 51. By adopting this configuration, the heat dissipation efficiency of the semiconductor device A10 can be further improved.

Each of the first power terminal 30A, the second power terminal 30B, and the third power terminal 30C has a joint portion 35, a mounting portion 36, and an intermediate portion 37. The joint portion 35 is joined to the support member 10. The mounting portion 36 is separated from the joint portion 35 in the first direction z and is exposed from the bottom surface 52 of the sealing resin 50. The intermediate portion 37 connects the joint portion 35 and the mounting portion 36. The joint portion 35 is sandwiched between the sealing resin 50 and the support member 10. By adopting this configuration, it is possible to prevent the plurality of power terminals 30 from falling off the bottom surface 52.

Second embodiment:
A semiconductor device A20 according to a second embodiment of the present disclosure will be described based on FIGS. 11 to 15. In these figures, elements that are the same as or similar to those of the semiconductor device A10 described above are denoted by the same reference numerals, and redundant explanation will be omitted. Here, in FIG. 13, for convenience of understanding, the sealing resin 50 is shown. In FIG. 13, the outline of the transparent sealing resin 50 is shown with imaginary lines.

In the semiconductor device A20, the configuration of the plurality of second signal terminals 32 is different from the configuration of the semiconductor device A10.

As shown in FIGS. 11 to 13, the second gate terminal 32A among the plurality of second signal terminals 32 protrudes from the first side surface 53 of the sealing resin 50. As shown in FIG. 14, the second gate terminal 32A is located next to the second power terminal 30B among the plurality of power terminals 30 in the third direction y. Among the plurality of second signal terminals 32, the third detection terminal 32B and the fourth detection terminal 32C are located on the opposite side of the second gate terminal 32A with respect to the two semiconductor elements 20 in the second direction x. As shown in FIG. 15, of the third detection terminal 32B and the fourth detection terminal 32C, the fourth detection terminal 32C is located closest to the third power terminal 30C among the plurality of power terminals 30.

As described above, the gate voltage for driving the second semiconductor element 20B of the two semiconductor elements 20 is applied to the second gate terminal 32A. Therefore, in the second gate terminal 32A, a current flows from the outside toward the gate electrode 23 of the second semiconductor element 20B. Therefore, the direction of the current flowing through the second gate terminal 32A is opposite to the direction of the current flowing through the second power terminal 30B.

As shown in FIGS. 11 and 14, the dimension in the third direction y of the second power terminal 30B is larger than the dimension in the third direction y of each of the plurality of second signal terminals 32 including the second gate terminal 32A. .

Next, the effects of the semiconductor device A20 will be explained.

The semiconductor device A20 includes a first power terminal 30A and a first signal terminal 31 electrically connected to the first semiconductor element 20A, a second power terminal 30B and a second signal terminal 32 electrically connected to the second semiconductor element 20B, and a first semiconductor The third power terminal 30C is electrically connected to the element 20A and the second semiconductor element 20B. Further, the semiconductor device A20 includes a sealing resin 50 that covers the first semiconductor element 20A and the second semiconductor element 20B. The position of the first mounting surface 33 of each of the first power terminal 30A, the second power terminal 30B, and the second power terminal 30B in the first direction z, and the first signal terminal 31 and the second signal terminal 32 in the first direction z The position of each second mounting surface 34 is closer from the bottom surface 52 of the sealing resin 50 than from the first semiconductor element 20A and the second semiconductor element 20B. The first power terminal 30A and the second power terminal 30B protrude from the first side surface 53. The third power terminal 30C protrudes from the second side surface 54. The first power terminal 30A and the second power terminal 30B are separated from each other in the third direction y. Therefore, according to this configuration, even in the semiconductor device A20, it is possible to reduce the parasitic inductance in the semiconductor device A20 while reducing the size of the semiconductor device A20. Furthermore, the semiconductor device A20 has the same configuration as the semiconductor device A10, and thus has the same effects as the semiconductor device A10.

In the semiconductor device A20, the second gate terminal 32A as the second signal terminal 32 protrudes from the first side surface 53 of the sealing resin 50. The current flowing through the second signal terminal 32 is opposite to that flowing through the second power terminal 30B. The second signal terminal 32 is located next to the second power terminal 30B in the third direction y. By adopting this configuration, mutual induction acts between the second signal terminal 32 and the second power terminal 30B. Therefore, it is possible to reduce the parasitic inductance at the second signal terminal 32. When the second signal terminal 32 is the second gate terminal 32A, it is possible to reduce switching loss associated with driving the second semiconductor element 20B.

Third embodiment:
A semiconductor device A30 according to a third embodiment of the present disclosure will be described based on FIGS. 16 to 20. In these figures, elements that are the same as or similar to those of the semiconductor device A10 described above are denoted by the same reference numerals, and redundant explanation will be omitted. Here, in FIG. 18, for convenience of understanding, the sealing resin 50 is shown. In FIG. 18, the outline of the transparent sealing resin 50 is shown with imaginary lines.

In the semiconductor device A30, the configuration of the plurality of first signal terminals 31 is different from the configuration of the semiconductor device A20 described above.

As shown in FIGS. 16 to 18, the first gate terminal 31A among the plurality of first signal terminals 31 protrudes from the first side surface 53 of the sealing resin 50. As shown in FIG. 19, the first gate terminal 31A is located next to the second power terminal 30B among the plurality of power terminals 30 in the third direction y. In the semiconductor device A30, the first power terminal 30A among the plurality of power terminals 30 is located on the opposite side of the second power terminal 30B with respect to the first gate terminal 31A in the third direction y. Among the plurality of first signal terminals 31, the first detection terminal 31B and the second detection terminal 31C are located on the opposite side of the first gate terminal 31A with respect to the two semiconductor elements 20 in the second direction x. As shown in FIG. 20, of the first detection terminal 31B and the second detection terminal 31C, the first detection terminal 31B is located closest to the third power terminal 30C among the plurality of power terminals 30.

As described above, the gate voltage for driving the first semiconductor element 20A of the two semiconductor elements 20 is applied to the first gate terminal 31A. Therefore, in the first gate terminal 31A, a current flows from the outside toward the gate electrode 23 of the first semiconductor element 20A. Therefore, the direction of the current flowing through the first gate terminal 31A is opposite to the direction of the current flowing through the second power terminal 30B.

As shown in FIGS. 16 and 19, the dimension in the third direction y of the second power terminal 30B is larger than the dimension in the third direction y of each of the plurality of first signal terminals 31 including the first gate terminal 31A. .

As shown in FIG. 19, the second gate terminal 32A among the plurality of second signal terminals 32 is located on the opposite side of the first power terminal 30A with respect to the second power terminal 30B in the third direction y, and It is located next to the second power terminal 30B in the third direction y.

Next, the effects of the semiconductor device A30 will be explained.

The semiconductor device A30 includes a first power terminal 30A and a first signal terminal 31 that are electrically connected to the first semiconductor element 20A, a second power terminal 30B and a second signal terminal 32 that are electrically electrically connected to the second semiconductor element 20B, and a first semiconductor The third power terminal 30C is electrically connected to the element 20A and the second semiconductor element 20B. Further, the semiconductor device A30 includes a sealing resin 50 that covers the first semiconductor element 20A and the second semiconductor element 20B. The position of the first mounting surface 33 of each of the first power terminal 30A, the second power terminal 30B, and the second power terminal 30B in the first direction z, and the first signal terminal 31 and the second signal terminal 32 in the first direction z The position of each second mounting surface 34 is closer from the bottom surface 52 of the sealing resin 50 than from the first semiconductor element 20A and the second semiconductor element 20B. The first power terminal 30A and the second power terminal 30B protrude from the first side surface 53. The third power terminal 30C protrudes from the second side surface 54. The first power terminal 30A and the second power terminal 30B are separated from each other in the third direction y. Therefore, according to this configuration, even in the semiconductor device A30, it is possible to reduce the parasitic inductance in the semiconductor device A30 while reducing the size of the semiconductor device A30. Furthermore, the semiconductor device A30 has the same configuration as the semiconductor device A10, and thus has the same effects as the semiconductor device A10.

In the semiconductor device A30, the first gate terminal 31A as the first signal terminal 31 protrudes from the first side surface 53 of the sealing resin 50. The current flowing through the first signal terminal 31 is opposite to that flowing through the second power terminal 30B. The first signal terminal 31 is located next to the second power terminal 30B in the third direction y. By adopting this configuration, mutual induction acts between the first signal terminal 31 and the second power terminal 30B. Therefore, it is possible to reduce the parasitic inductance at the first signal terminal 31. When the first signal terminal 31 is the first gate terminal 31A, it is possible to reduce switching loss associated with driving the first semiconductor element 20A.

Furthermore, in the semiconductor device A30, the second gate terminal 32A as the second signal terminal 32 protrudes from the first side surface 53 of the sealing resin 50. The current flowing through the second signal terminal 32 is opposite to that flowing through the second power terminal 30B. The second signal terminal 32 is located on the opposite side of the first signal terminal 31 with respect to the second power terminal 30B in the third direction y, and is located next to the second power terminal 30B in the third direction y. With this configuration, the second signal terminal 32 achieves the same effects as in the case of the semiconductor device A20.

Fourth embodiment:
A semiconductor device A40 according to a fourth embodiment of the present disclosure will be described based on FIGS. 21 to 26. In these figures, elements that are the same as or similar to those of the semiconductor device A10 described above are denoted by the same reference numerals, and redundant explanation will be omitted.

In the semiconductor device A40, the configurations of the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 are different from the configuration of the semiconductor device A10.

As shown in FIGS. 21 and 22, each of the plurality of power terminals 30 is exposed only from either the first side surface 53 of the sealing resin 50 or the second side surface 54 of the sealing resin 50. As shown in FIGS. 23 to 26, in each of the plurality of power terminals 30, the portion of the mounting portion 36 exposed from the sealing resin 50 is shaped like a gull wing when viewed from the bottom surface 50 of the sealing resin 50. It is bent towards. As shown in FIG. 22, the first mounting surface 33 of each of the plurality of power terminals 30 is spaced outward from the bottom surface 52 when viewed in the first direction z.

As shown in FIGS. 21 and 22, each of the plurality of first signal terminals 31 and the plurality of second signal terminals 32 is exposed only from the second side surface 54 of the sealing resin 50. As shown in FIGS. 24 to 26, in each of the plurality of first signal terminals 31 and the plurality of second signal terminals 32, the portion of the mounting portion 36 exposed from the sealing resin 50 is visible in the third direction y. It is bent toward the bottom surface 52 of the sealing resin 50 in a gull-wing shape. As shown in FIG. 22, when viewed in the first direction z, the second mounting surface 34 of each of the plurality of first signal terminals 31 and the plurality of second signal terminals 32 is spaced outward from the bottom surface 52. .

Next, the effects of the semiconductor device A40 will be explained.

The semiconductor device A40 includes a first power terminal 30A and a first signal terminal 31 that are electrically connected to the first semiconductor element 20A, a second power terminal 30B and a second signal terminal 32 that are electrically electrically connected to the second semiconductor element 20B, and a first semiconductor The third power terminal 30C is electrically connected to the element 20A and the second semiconductor element 20B. Further, the semiconductor device A40 includes a sealing resin 50 that covers the first semiconductor element 20A and the second semiconductor element 20B. The position of the first mounting surface 33 of each of the first power terminal 30A, the second power terminal 30B, and the second power terminal 30B in the first direction z, and the first signal terminal 31 and the second signal terminal 32 in the first direction z The position of each second mounting surface 34 is closer from the bottom surface 52 of the sealing resin 50 than from the first semiconductor element 20A and the second semiconductor element 20B. The first power terminal 30A and the second power terminal 30B protrude from the first side surface 53. The third power terminal 30C protrudes from the second side surface 54. The first power terminal 30A and the second power terminal 30B are separated from each other in the third direction y. Therefore, according to this configuration, even in the semiconductor device A40, it is possible to reduce the parasitic inductance in the semiconductor device A40 while reducing the size of the semiconductor device A40. Furthermore, the semiconductor device A40 has the same configuration as the semiconductor device A10, and thus has the same effects as the semiconductor device A10.

Fifth embodiment:
A semiconductor device A50 according to a fifth embodiment of the present disclosure will be described based on FIGS. 27 and 28. In these figures, elements that are the same as or similar to those of the semiconductor device A10 described above are denoted by the same reference numerals, and redundant explanation will be omitted.

In the semiconductor device A50, the configurations of the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 are different from the configuration of the semiconductor device A20.

As shown in FIGS. 27 and 28, each of the plurality of power terminals 30 is exposed only from either the first side surface 53 of the sealing resin 50 or the second side surface 54 of the sealing resin 50. As in the case of the semiconductor device A40, in each of the plurality of power terminals 30, the portion of the mounting portion 36 exposed from the sealing resin 50 is attached to the bottom surface 52 of the sealing resin 50 in a gull wing shape when viewed in the third direction y. It is bent towards. As shown in FIG. 28, the first mounting surface 33 of each of the plurality of power terminals 30 is spaced outward from the bottom surface 52 when viewed in the first direction z.

As shown in FIGS. 27 and 28, each of the plurality of first signal terminals 31 and the plurality of second signal terminals 32 is connected to a first side surface 53 of the sealing resin 50 and a second side surface 54 of the sealing resin 50. exposed only from either. As in the case of the semiconductor device A40, in each of the plurality of first signal terminals 31 and the plurality of second signal terminals 32, the portion of the mounting portion 36 exposed from the sealing resin 50 is It is bent toward the bottom surface 52 of the sealing resin 50 in a gullwing shape. As shown in FIG. 28, when viewed in the first direction z, the second mounting surface 34 of each of the plurality of first signal terminals 31 and the plurality of second signal terminals 32 is spaced outward from the bottom surface 52. .

Next, the effects of the semiconductor device A50 will be explained.

The semiconductor device A50 includes a first power terminal 30A and a first signal terminal 31 electrically connected to the first semiconductor element 20A, a second power terminal 30B and a second signal terminal 32 electrically connected to the second semiconductor element 20B, and a first semiconductor The third power terminal 30C is electrically connected to the element 20A and the second semiconductor element 20B. Further, the semiconductor device A50 includes a sealing resin 50 that covers the first semiconductor element 20A and the second semiconductor element 20B. The position of the first mounting surface 33 of each of the first power terminal 30A, the second power terminal 30B, and the second power terminal 30B in the first direction z, and the first signal terminal 31 and the second signal terminal 32 in the first direction z The position of each second mounting surface 34 is closer from the bottom surface 52 of the sealing resin 50 than from the first semiconductor element 20A and the second semiconductor element 20B. The first power terminal 30A and the second power terminal 30B protrude from the first side surface 53. The third power terminal 30C protrudes from the second side surface 54. The first power terminal 30A and the second power terminal 30B are separated from each other in the third direction y. Therefore, according to this configuration, even in the semiconductor device A50, it is possible to reduce the parasitic inductance in the semiconductor device A50 while reducing the size of the semiconductor device A50. Furthermore, the semiconductor device A50 has the same configuration as the semiconductor device A20, and thus has the same effects as the semiconductor device A20.

Sixth embodiment:
A semiconductor device A60 according to a sixth embodiment of the present disclosure will be described based on FIGS. 29 and 30. In these figures, elements that are the same as or similar to those of the semiconductor device A10 described above are denoted by the same reference numerals, and redundant explanation will be omitted.

In the semiconductor device A60, the configurations of the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 are different from the configuration of the semiconductor device A30.

As shown in FIGS. 29 and 30, each of the plurality of power terminals 30 is exposed only from either the first side surface 53 of the sealing resin 50 or the second side surface 54 of the sealing resin 50. As in the case of the semiconductor device A40, in each of the plurality of power terminals 30, the portion of the mounting portion 36 exposed from the sealing resin 50 is attached to the bottom surface 52 of the sealing resin 50 in a gull wing shape when viewed in the third direction y. It is bent towards. As shown in FIG. 30, the first mounting surface 33 of each of the plurality of power terminals 30 is spaced outward from the bottom surface 52 when viewed in the first direction z.

As shown in FIGS. 29 and 30, each of the plurality of first signal terminals 31 and the plurality of second signal terminals 32 is connected to a first side surface 53 of the sealing resin 50 and a second side surface 54 of the sealing resin 50. exposed only from either. As in the case of the semiconductor device A40, in each of the plurality of first signal terminals 31 and the plurality of second signal terminals 32, the portion of the mounting portion 36 exposed from the sealing resin 50 is It is bent toward the bottom surface 52 of the sealing resin 50 in a gullwing shape. As shown in FIG. 30, when viewed in the first direction z, the second mounting surface 34 of each of the plurality of first signal terminals 31 and the plurality of second signal terminals 32 is spaced outward from the bottom surface 52. .

Next, the effects of the semiconductor device A60 will be explained.

The semiconductor device A60 includes a first power terminal 30A and a first signal terminal 31 electrically connected to the first semiconductor element 20A, a second power terminal 30B and a second signal terminal 32 electrically connected to the second semiconductor element 20B, and a first semiconductor The third power terminal 30C is electrically connected to the element 20A and the second semiconductor element 20B. Further, the semiconductor device A60 includes a sealing resin 50 that covers the first semiconductor element 20A and the second semiconductor element 20B. The position of the first mounting surface 33 of each of the first power terminal 30A, the second power terminal 30B, and the second power terminal 30B in the first direction z, and the first signal terminal 31 and the second signal terminal 32 in the first direction z The position of each second mounting surface 34 is closer from the bottom surface 52 of the sealing resin 50 than from the first semiconductor element 20A and the second semiconductor element 20B. The first power terminal 30A and the second power terminal 30B protrude from the first side surface 53. The third power terminal 30C protrudes from the second side surface 54. The first power terminal 30A and the second power terminal 30B are separated from each other in the third direction y. Therefore, according to this configuration, even in the semiconductor device A60, it is possible to reduce the parasitic inductance in the semiconductor device A60 while reducing the size of the semiconductor device A60. Furthermore, the semiconductor device A60 has the same configuration as the semiconductor device A30, and thus has the same effects as the semiconductor device A30.

The present disclosure is not limited to the embodiments described above. The specific configuration of each part of the present disclosure can be modified in various ways.

The present disclosure includes embodiments described in the appendix below.

Additional note 1.
a first semiconductor element;
a second semiconductor element;
a first power terminal and a first signal terminal electrically connected to the first semiconductor element;
a second power terminal and a second signal terminal electrically connected to the second semiconductor element;
a third power terminal electrically connected to the first semiconductor element and the second semiconductor element;
a sealing resin that covers the first semiconductor element and the second semiconductor element,
The sealing resin has a bottom surface facing in a first direction, and a first side surface and a second side surface facing oppositely to each other in a second direction perpendicular to the first direction,
Each of the first power terminal, the second power terminal, and the third power terminal has a first mounting surface facing the same side as the bottom surface in the first direction,
Each of the first signal terminal and the second signal terminal has a second mounting surface facing the same side as the bottom surface in the first direction,
The positions of each of the first mounting surface and the second mounting surface in the first direction are closer from the bottom surface than from the first semiconductor element and the second semiconductor element,
The first power terminal and the second power terminal protrude from the first side surface,
The third power terminal protrudes from the second side surface,
Each of the first signal terminal and the second signal terminal protrudes from either the first side surface or the second side surface,
The semiconductor device, wherein the first power terminal and the second power terminal are separated from each other in a third direction orthogonal to the first direction and the second direction.
Appendix 2.
The first mounting surface is exposed from the bottom surface,
The semiconductor device according to supplementary note 1, wherein the first mounting surface extends in the second direction and includes a region protruding from either the first side surface or the second side surface.
Appendix 3.
The second mounting surface is exposed from the bottom surface,
The semiconductor device according to appendix 2, wherein the second mounting surface extends in the second direction and includes a region protruding from either the first side surface or the second side surface.
Appendix 4.
The semiconductor device according to appendix 2 or 3, wherein the second power terminal is located next to the first power terminal in the third direction.
Appendix 5.
The second signal terminal protrudes from the first side surface,
The direction of the current flowing through the second signal terminal is opposite to the direction of the current flowing through the second power terminal,
The semiconductor device according to appendix 4, wherein the second signal terminal is located next to the second power terminal in the third direction.
Appendix 6.
The semiconductor device according to appendix 5, wherein a dimension of the second power terminal in the third direction is larger than a dimension of the second signal terminal in the third direction.
Appendix 7.
The first signal terminal protrudes from the first side surface,
The direction of the current flowing through the first signal terminal is opposite to the direction of the current flowing through the second power terminal,
The semiconductor device according to appendix 2 or 3, wherein the first signal terminal is located next to the second power terminal in the third direction.
Appendix 8.
The semiconductor device according to appendix 7, wherein a dimension of the second power terminal in the third direction is larger than a dimension of the first signal terminal in the third direction.
Appendix 9.
The second signal terminal protrudes from the first side surface,
The direction of the current flowing through the second signal terminal is opposite to the direction of the current flowing through the second power terminal,
The second signal terminal is located on the opposite side of the first signal terminal with respect to the second power terminal in the third direction, and is located next to the second power terminal in the third direction. The semiconductor device according to appendix 8.
Appendix 10.
further comprising a support member on which the first semiconductor element and the second semiconductor element are mounted,
The semiconductor device according to any one of appendices 1 to 9, wherein the first semiconductor element and the second semiconductor element are located between the bottom surface and the support member in the first direction.
Appendix 11.
The first power terminal, the second power terminal, the third power terminal, the first signal terminal, and the second signal terminal are located between the bottom surface and the support member in the first direction, 11. The semiconductor device according to 10.
Appendix 12.
The sealing resin has a top surface facing opposite to the bottom surface in the first direction,
The semiconductor device according to appendix 11, wherein the support member is exposed from the top surface.
Appendix 13.
The semiconductor device according to appendix 12, wherein the first power terminal, the second power terminal, and the third power terminal are joined to the support member.
Appendix 14.
The semiconductor device according to attachment 13, wherein the first signal terminal and the second signal terminal are joined to the support member.
Appendix 15.
The support member includes an insulating layer, and a first conductive layer and a second conductive layer located between the first semiconductor element, the second semiconductor element, and the insulating layer in the first direction,
the first semiconductor element is conductively bonded to the first conductive layer,
15. The semiconductor device according to

appendix

13 or 14, wherein the second semiconductor element is conductively bonded to the second conductive layer.
Appendix 16.
the first power terminal is conductively bonded to the first conductive layer;
16. The semiconductor device according to appendix 15, wherein the third power terminal is conductively bonded to the second conductive layer.
Appendix 17.
The support member has a heat dissipation layer located on the opposite side of the first conductive layer and the second conductive layer with respect to the insulating layer,
17. The semiconductor device according to

appendix

15 or 16, wherein the heat dissipation layer is exposed from the top surface.

A10, A20, A30, A40, A50, A60: Semiconductor device 10: Support member 11: Insulating layer 12: First conductive layer 13: Second conductive layer 14: Third conductive layer 15: Pad layer 16: Heat dissipation layer 20: Semiconductor element 20A: First semiconductor element 20B: Second semiconductor element 21: First electrode 22: Second electrode 23: Gate electrode 29: Bonding layer 30: Power terminal 30A: First power terminal 30B: Second power terminal 30C: Third power terminal 31: First signal terminal 31A: First gate terminal 31B: First detection terminal 31C: Second detection terminal 32: Second signal terminal 32A: Second gate terminal 32B: Third detection terminal 32C: Fourth Detection terminal 33: First mounting surface 34: Second mounting surface 35: Joint portion 36: Mounting portion 37: Intermediate portion 40: Conductive member 40A: First member 40B: Second member 41: Gate wire 42: Detection wire 50: Sealing resin 501: Outer edge 51: Top surface 511: Peripheral edge 52: Bottom surface 53: First side surface 54: Second side surface 55: Third side surface z: First direction x: Second direction y: Third direction

Claims

a first semiconductor element;
a second semiconductor element;
a first power terminal and a first signal terminal electrically connected to the first semiconductor element;
a second power terminal and a second signal terminal electrically connected to the second semiconductor element;
a third power terminal electrically connected to the first semiconductor element and the second semiconductor element;
a sealing resin that covers the first semiconductor element and the second semiconductor element,
The sealing resin has a bottom surface facing in a first direction, and a first side surface and a second side surface facing oppositely to each other in a second direction perpendicular to the first direction,
Each of the first power terminal, the second power terminal, and the third power terminal has a first mounting surface facing the same side as the bottom surface in the first direction,
Each of the first signal terminal and the second signal terminal has a second mounting surface facing the same side as the bottom surface in the first direction,
The positions of each of the first mounting surface and the second mounting surface in the first direction are closer from the bottom surface than from the first semiconductor element and the second semiconductor element,
The first power terminal and the second power terminal protrude from the first side surface,
The third power terminal protrudes from the second side surface,
Each of the first signal terminal and the second signal terminal protrudes from either the first side surface or the second side surface,
The semiconductor device, wherein the first power terminal and the second power terminal are separated from each other in a third direction orthogonal to the first direction and the second direction.
The first mounting surface is exposed from the bottom surface,
2. The semiconductor device according to claim 1, wherein the first mounting surface includes a region extending in the second direction and protruding from either the first side surface or the second side surface.
The second mounting surface is exposed from the bottom surface,
3. The semiconductor device according to claim 2, wherein the second mounting surface includes a region extending in the second direction and protruding from either the first side surface or the second side surface.
4. The semiconductor device according to claim 2, wherein the second power terminal is located next to the first power terminal in the third direction.
The second signal terminal protrudes from the first side surface,
The direction of the current flowing through the second signal terminal is opposite to the direction of the current flowing through the second power terminal,
5. The semiconductor device according to claim 4, wherein the second signal terminal is located next to the second power terminal in the third direction.
The semiconductor device according to claim 5, wherein a dimension of the second power terminal in the third direction is larger than a dimension of the second signal terminal in the third direction.
The first signal terminal protrudes from the first side surface,
The direction of the current flowing through the first signal terminal is opposite to the direction of the current flowing through the second power terminal,
4. The semiconductor device according to claim 2, wherein the first signal terminal is located next to the second power terminal in the third direction.
The semiconductor device according to claim 7, wherein a dimension of the second power terminal in the third direction is larger than a dimension of the first signal terminal in the third direction.
The second signal terminal protrudes from the first side surface,
The direction of the current flowing through the second signal terminal is opposite to the direction of the current flowing through the second power terminal,
The second signal terminal is located on the opposite side of the first signal terminal with respect to the second power terminal in the third direction, and is located next to the second power terminal in the third direction. The semiconductor device according to claim 8.
further comprising a support member on which the first semiconductor element and the second semiconductor element are mounted,
10. The semiconductor device according to claim 1, wherein the first semiconductor element and the second semiconductor element are located between the bottom surface and the support member in the first direction.
The first power terminal, the second power terminal, the third power terminal, the first signal terminal, and the second signal terminal are located between the bottom surface and the support member in the first direction. The semiconductor device according to item 10.
The sealing resin has a top surface facing opposite to the bottom surface in the first direction,
The semiconductor device according to claim 11, wherein the support member is exposed from the top surface.
The semiconductor device according to claim 12, wherein the first power terminal, the second power terminal, and the third power terminal are joined to the support member.
The semiconductor device according to claim 13, wherein the first signal terminal and the second signal terminal are joined to the support member.
The support member includes an insulating layer, and a first conductive layer and a second conductive layer located between the first semiconductor element, the second semiconductor element, and the insulating layer in the first direction,
the first semiconductor element is conductively bonded to the first conductive layer,
15. The semiconductor device according to claim 13, wherein the second semiconductor element is conductively bonded to the second conductive layer.
the first power terminal is conductively bonded to the first conductive layer;
16. The semiconductor device according to claim 15, wherein the third power terminal is conductively bonded to the second conductive layer.
The support member has a heat dissipation layer located on the opposite side of the first conductive layer and the second conductive layer with respect to the insulating layer,
17. The semiconductor device according to claim 15, wherein the heat dissipation layer is exposed from the top surface.