WO2019235146A1 - Semiconductor module - Google Patents

Semiconductor module Download PDF

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Publication number
WO2019235146A1
WO2019235146A1 PCT/JP2019/019109 JP2019019109W WO2019235146A1 WO 2019235146 A1 WO2019235146 A1 WO 2019235146A1 JP 2019019109 W JP2019019109 W JP 2019019109W WO 2019235146 A1 WO2019235146 A1 WO 2019235146A1
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WO
WIPO (PCT)
Prior art keywords
terminal
pair
semiconductor module
semiconductor device
module according
Prior art date
Application number
PCT/JP2019/019109
Other languages
French (fr)
Japanese (ja)
Inventor
沢水 神田
松尾　昌明
Original Assignee
ローム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by ローム株式会社 filed Critical ローム株式会社
Priority to DE212019000029.0U priority Critical patent/DE212019000029U1/en
Publication of WO2019235146A1 publication Critical patent/WO2019235146A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/4917—Crossed wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • the present disclosure relates to a semiconductor module in which a semiconductor device including a plurality of semiconductor elements is bonded to a heat sink.
  • Patent Document 1 discloses a semiconductor device including a substrate, a metal foil disposed on the upper surface of the substrate, a plurality of IGBT chips joined in a conductive state to the metal foil, and a heat sink disposed on the lower surface of the substrate.
  • the semiconductor device is used for the purpose of power conversion for converting DC power into AC power.
  • a compound (silicone grease) is interposed between the heat radiating plate and the lower surface of the substrate to suppress a gap formed between the substrate and the heat radiating plate.
  • heat is generated from the plurality of IGBT chips.
  • Heat generated from the plurality of IGBT chips is conducted to the heat radiating plate through the metal foil, the substrate, and the silicone grease.
  • the heat conducted to the heat sink is dissipated into the atmosphere.
  • Silicone grease is a material having a relatively high thermal conductivity, but its thermal conductivity is less than 10 W / (m ⁇ K).
  • semiconductor devices intended for power conversion have been used in electric vehicles and the like. Such semiconductor devices are required to have higher output. In order to satisfy this requirement, it is an issue to further improve the heat dissipation of the semiconductor device.
  • a semiconductor module provided by the present disclosure includes: a base material having a first main surface and a first back surface facing opposite sides in the thickness direction; a conductive member disposed on the first main surface; and the conductive member.
  • a semiconductor device comprising: a plurality of semiconductor elements joined in a conductive state; and a sealing resin that covers the plurality of semiconductor elements so that the first back surface is exposed; a heat sink; the heat sink; A joining sheet interposed between the back surface and the joining sheet, the joining sheet has electrical insulation and flexibility, and the thermal conductivity of the joining sheet is the thermal conductivity of the sealing resin. Is bigger than.
  • FIG. 3 is a plan view of the semiconductor device shown in FIG. 2 and transmits a sealing resin.
  • FIG. 3 is a bottom view of the semiconductor device shown in FIG. 2.
  • FIG. 3 is a right side view of the semiconductor device shown in FIG. 2.
  • FIG. 3 is a left side view of the semiconductor device shown in FIG. 2.
  • FIG. 3 is a front view of the semiconductor device shown in FIG. 2.
  • FIG. 4 is a sectional view taken along line VIII-VIII in FIG. 3.
  • FIG. 4 is a cross-sectional view taken along line IX-IX in FIG. 3.
  • FIG. 4 is a cross-sectional view taken along line XX in FIG. 3. It is the elements on larger scale of FIG. FIG. 4 is a partially enlarged view of FIG. 3.
  • FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 12.
  • FIG. 15 is a sectional view taken along line XV-XV in FIG. 14. It is the elements on larger scale of FIG. It is the elements on larger scale of FIG. It is sectional drawing of the semiconductor device contained in the component of the semiconductor module concerning 2nd Embodiment of this indication. It is sectional drawing of the semiconductor device shown in FIG. It is the elements on larger scale of FIG.
  • FIG. 24 is a plan view of the semiconductor device included in the semiconductor device included in the components of the semiconductor module illustrated in FIG. 23.
  • FIG. 25 is a plan view of the semiconductor device shown in FIG. 24 and transmits the sealing resin.
  • FIG. 26 is a plan view corresponding to FIG. 25 and transmits the second terminal.
  • FIG. 25 is a bottom view of the semiconductor device shown in FIG. 24.
  • FIG. 25 is a right side view of the semiconductor device shown in FIG. 24.
  • FIG. 25 is a left side view of the semiconductor device shown in FIG. 24.
  • FIG. 25 is a front view of the semiconductor device shown in FIG. 24.
  • FIG. 26 is a sectional view taken along line XXXI-XXXI in FIG.
  • FIG. 26 is a sectional view taken along line XXXII-XXXII in FIG. 25. It is the elements on larger scale of FIG. It is the elements on larger scale of FIG.
  • FIG. 24 is a plan view of the semiconductor module shown in FIG. 23.
  • FIG. 36 is a sectional view taken along line XXXVI-XXXVI in FIG. 35. It is the elements on larger scale of FIG.
  • the semiconductor module A10 includes a semiconductor device B10, a heat sink 70, and a bonding sheet 80 as its components.
  • the sealing resin 60 is transmitted for convenience of understanding.
  • the VIII-VIII line, the IX-IX line, and the XX line are indicated by alternate long and short dash lines.
  • a semiconductor device B10 shown in FIG. 1 is a power conversion device (power module) on which a plurality of semiconductor elements such as MOSFETs are mounted.
  • the semiconductor device B10 is used for a drive source such as a motor or an inverter device of various electric products.
  • the semiconductor device B10 includes a base material 10, a conductive member 20, an auxiliary conductive member 21, a pair of input terminals 31, a pair of output terminals 32, a plurality of gate terminals 33, a plurality of detection terminals 34, a plurality of semiconductor elements 40, and a seal.
  • a stop resin 60 is provided.
  • the thickness direction of the base material 10 is referred to as “thickness direction z”.
  • a direction orthogonal to the thickness direction z is referred to as a “first direction x”.
  • a direction orthogonal to both the thickness direction z and the first direction x is referred to as a “second direction y”.
  • the semiconductor device B10 is rectangular when viewed along the thickness direction z, that is, when viewed in plan.
  • the first direction x corresponds to the short direction of the semiconductor device B10.
  • the second direction y corresponds to the longitudinal direction of the semiconductor device B10.
  • the side where the pair of input terminals 31 is located in the first direction x is referred to as “one side in the first direction x”.
  • the side where the pair of output terminals 32 is located in the first direction x is referred to as “the other side in the first direction x”.
  • the base member 10 is provided with a conductive member 20.
  • the base material 10 serves as a support member for the conductive member 20 and the plurality of semiconductor elements 40.
  • the base material 10 has electrical insulation.
  • the base material 10 is made of a material containing ceramics having relatively high thermal conductivity. An example of the ceramic is aluminum nitride (AlN).
  • the substrate 10 has a first main surface 11A and a first back surface 12A.
  • the first main surface 11A and the first back surface 12A face opposite to each other in the thickness direction z.
  • 11 A of 1st main surfaces face the side in which the electrically-conductive member 20 is arrange
  • the first main surface 11 ⁇ / b> A is covered with the sealing resin 60 together with the conductive member 20 and the plurality of semiconductor elements 40.
  • the first back surface 12 ⁇ / b> A is exposed from the sealing resin 60.
  • a surface treatment region 19 including a rough surface is formed on the first back surface 12A.
  • the surface treatment region 19 can be formed by sandblasting or the like.
  • the surface treatment region 19 is formed over the entire first back surface 12A.
  • the conductive member 20 is disposed on the first main surface 11A of the substrate 10 as shown in FIGS.
  • the conductive member 20 is a metal plate.
  • the said metal plate consists of copper (Cu) or a copper alloy.
  • the conductive member 20 is bonded to the first main surface 11A by a bonding material (not shown) such as silver (Ag) paste.
  • silver plating may be applied to the surface of the conductive member 20.
  • the conductive member 20 may be a metal foil such as a copper foil instead of the metal plate.
  • the conductive member 20 includes a pair of first conductive portions 20A and a pair of second conductive portions 20B.
  • the configuration of the conductive member 20 is not limited to this embodiment, and can be freely set based on the number of the plurality of semiconductor elements 40 set according to the performance required for the semiconductor device B10.
  • the pair of first conductive portions 20A is located on one side in the first direction x on the first main surface 11A. As viewed along the thickness direction z, the pair of first conductive portions 20A has a rectangular shape. The pair of first conductive portions 20A are separated from each other in the second direction y.
  • the pair of second conductive portions 20B are located on the other side in the first direction x on the first main surface 11A.
  • the pair of first conductive portions 20A and the pair of second conductive portions 20B are separated from each other in the first direction x.
  • the pair of second conductive portions 20B has a rectangular shape.
  • the pair of second conductive portions 20B are separated from each other in the second direction y.
  • the auxiliary conductive member 21 is disposed on the first main surface 11A of the base material 10 as shown in FIGS.
  • the auxiliary conductive member 21 is located on one side of the first main surface 11A in the first direction x and between the pair of first conductive portions 20A in the second direction y. Viewed along the thickness direction z, the auxiliary conductive member 21 has a rectangular shape.
  • the auxiliary conductive member 21 is a metal plate made of the same material as that of the conductive member 20.
  • the auxiliary conductive member 21 is bonded to the first main surface 11A by a bonding material (not shown) such as silver (Ag) paste.
  • silver plating may be applied to the surface of the auxiliary conductive member 21.
  • the auxiliary conductive member 21 may be a metal foil such as a copper foil instead of the metal plate.
  • the semiconductor device B ⁇ b> 10 further includes a connecting member 29.
  • the connecting member 29 has conductivity.
  • the connecting member 29 extends along the second direction y and is connected to the surfaces of the pair of first conductive portions 20 ⁇ / b> A while straddling the auxiliary conductive member 21.
  • the pair of first conductive portions 20 ⁇ / b> A are electrically connected to each other via the connecting member 29.
  • the connecting member 29 is composed of a plurality of wires.
  • the plurality of wires are made of, for example, aluminum (Al).
  • the connecting member 29 may be a metal piece that extends in the second direction y when viewed along the thickness direction z, instead of a plurality of wires.
  • the pair of input terminals 31 are located on one side in the first direction x in the semiconductor device B10, as shown in FIGS.
  • the pair of input terminals 31 are separated from each other in the second direction y.
  • the pair of input terminals 31 is supplied with external DC power.
  • the pair of input terminals 31 is composed of the same lead frame together with the pair of output terminals 32, the plurality of gate terminals 33, and the plurality of detection terminals 34.
  • the lead frame is made of copper or a copper alloy.
  • the pair of input terminals 31 includes a first terminal 31A and a second terminal 31B. Each of the first terminal 31A and the second terminal 31B has a pad portion 311 and a terminal portion 312.
  • the pad portion 311 is separated from the base material 10 as viewed along the thickness direction z, and is covered with the sealing resin 60. As a result, the pair of input terminals 31 are supported by the sealing resin 60.
  • a first connection wire 51 is connected to the surface of the pad portion 311.
  • the first connection wire 51 is made of aluminum, for example. Note that the surface of the pad portion 311 may be subjected to, for example, silver plating.
  • the first terminal 31A is the positive electrode (P terminal) of the pair of input terminals 31. As shown in FIGS. 3 and 8, the first connection wire 51 connected to the surface of the pad portion 311 of the first terminal 31A is connected to the surface of one first conductive portion 20A. Thereby, the first terminal 31A is electrically connected to the pair of first conductive portions 20A.
  • the second terminal 31B is the negative electrode (N terminal) of the pair of input terminals 31.
  • the first connection wire 51 connected to the surface of the pad portion 311 of the second terminal 31 ⁇ / b> B is connected to the surface of the auxiliary conductive member 21.
  • the second terminal 31 ⁇ / b> B is electrically connected to the auxiliary conductive member 21.
  • the terminal portion 312 is connected to the pad portion 311 and is exposed from the sealing resin 60.
  • the terminal portion 312 is used when the semiconductor device B10 is mounted on a wiring board.
  • the terminal portion 312 has a base portion 312A and an upright portion 312B.
  • the base 312A is connected to the pad 311 and extends in the first direction x from a first side surface 631 (details will be described later) of the sealing resin 60 located on one side in the first direction x. As shown in FIG.
  • the standing portion 312 ⁇ / b> B extends from the tip of the base portion 312 ⁇ / b> A in the first direction x toward the side where the first main surface 11 ⁇ / b> A of the base material 10 in the thickness direction z faces.
  • the terminal portion 312 has an L shape when viewed in the second direction y.
  • the pair of output terminals 32 are located on the other side in the first direction x in the semiconductor device B10, as shown in FIGS.
  • the pair of output terminals 32 are separated from each other in the second direction y. From the pair of output terminals 32, AC power (voltage) converted by the plurality of semiconductor elements 40 is output.
  • Each of the pair of output terminals 32 includes a pad portion 321 and a terminal portion 322. Note that the number of output terminals 32 is not limited to this embodiment, and can be freely set according to the performance required for the semiconductor device B10.
  • the pad portion 321 is separated from the base material 10 as viewed along the thickness direction z, and is covered with the sealing resin 60. Accordingly, the pair of output terminals 32 are supported by the sealing resin 60.
  • a second connection wire 52 is connected to the surface of the pad portion 321.
  • the second connection wire 52 is made of aluminum, for example. Note that the surface of the pad portion 321 may be subjected to, for example, silver plating.
  • the plurality of second connection wires 52 connected to the surfaces of the pair of pad portions 321 are connected to the surfaces of the pair of second conductive portions 20B. Thereby, the pair of output terminals 32 is electrically connected to the pair of second conductive portions 20B.
  • the terminal portion 322 is connected to the pad portion 321 and exposed from the sealing resin 60.
  • the terminal portion 322 is used when the semiconductor device B10 is mounted on a wiring board.
  • the terminal portion 322 has a base portion 322A and an upright portion 322B.
  • the base portion 322A is connected to the pad portion 321 and extends in the first direction x from a first side surface 631 (details will be described later) of the sealing resin 60 located on the other side in the first direction x. As shown in FIG.
  • the upright portion 322 ⁇ / b> B extends from the tip of the base portion 322 ⁇ / b> A in the first direction x toward the side where the first main surface 11 ⁇ / b> A of the base material 10 in the thickness direction z faces.
  • the terminal portion 322 is L-shaped when viewed in the second direction y. Note that the shape of the terminal portion 322 is the same as the shape of the terminal portion 312 of the pair of input terminals 31.
  • the plurality of semiconductor elements 40 are joined to the pair of first conductive portions 20 ⁇ / b> A and the pair of second conductive portions 20 ⁇ / b> B constituting the conductive member 20. .
  • the plurality of semiconductor elements 40 have a rectangular shape (square shape in the semiconductor device B10) when viewed along the thickness direction z.
  • the plurality of semiconductor elements 40 include a pair of first elements 40A and a pair of second elements 40B.
  • the pair of first elements 40A constitute an upper arm circuit of the semiconductor device B10.
  • the pair of second elements 40B constitutes the lower arm circuit of the semiconductor device B10. Note that the number of the plurality of semiconductor elements 40 is not limited to this configuration, and can be freely set according to the performance required for the semiconductor device B10.
  • the pair of first elements 40A and the pair of second elements 40B are MOSFETs (Metal-Oxide-Semiconductor-Field-Effect-Transistors) configured using a semiconductor material mainly composed of silicon carbide (SiC).
  • MOSFETs Metal-Oxide-Semiconductor-Field-Effect-Transistors
  • the pair of first elements 40A and the pair of second elements 40B are not limited to MOSFETs, but are field effect transistors including MISFETs (Metal-Insulator-Semiconductor-Field-Effect-Transistors) or IGBTs (Insulated-Gate-Bipolar-Transistors).
  • MISFETs Metal-Insulator-Semiconductor-Field-Effect-Transistors
  • IGBTs Insulated-Gate-Bipolar-Transistors.
  • a bipolar transistor may be used.
  • the plurality of semiconductor elements 40 include a pair
  • each of the pair of first elements 40A and the pair of second elements 40B includes a first surface 401, a second surface 402, a first electrode 41, a second electrode 42, and a gate electrode 43. And an insulating film 44.
  • the first surface 401 and the second surface 402 face away from each other in the thickness direction z.
  • the 1st surface 401 faces the side where 11 A of 1st main surfaces of the base material 10 face.
  • the first electrode 41 is provided on the first surface 401.
  • a source current flows through the first electrode 41.
  • the first electrode 41 is divided into four regions.
  • a plurality of first wires 501 are individually connected to the four divided regions.
  • the plurality of first wires 501 are made of aluminum, for example.
  • the plurality of first wires 501 connected to the first electrodes 41 of the pair of first elements 40A are connected to the surfaces of the pair of second conductive portions 20B. Thereby, the first electrodes 41 of the pair of first elements 40A are electrically connected to the pair of second conductive portions 20B.
  • a plurality of second wires 502 are individually connected to the four divided regions.
  • the plurality of second wires 502 are made of aluminum, for example.
  • the plurality of second wires 502 connected to the first electrodes 41 of the pair of second elements 40 ⁇ / b> B are connected to the surface of the auxiliary conductive member 21.
  • the first electrodes 41 of the pair of second elements 40 ⁇ / b> B are electrically connected to the auxiliary conductive member 21. Therefore, the second terminal 31B is electrically connected to the pair of second elements 40B via the auxiliary conductive member 21.
  • the second electrode 42 is provided over the entire second surface 402. A drain current flows through the second electrode 42.
  • each of the second electrodes 42 of the pair of first elements 40 ⁇ / b> A is bonded to the surface thereof in a state of being electrically connected to one of the pair of first conductive portions 20 ⁇ / b> A by the conductive bonding layer 49 having conductivity.
  • the conductive bonding layer 49 is, for example, lead-free solder mainly composed of tin (Sn).
  • each of the second electrodes 42 of the pair of second elements 40 ⁇ / b> B is connected to any of the pair of second conductive portions 20 ⁇ / b> B by the conductive bonding layer 49. It is joined to the surface in a state of electrical conduction.
  • the gate electrode 43 is provided on the first surface 401.
  • a gate voltage for driving each of the pair of first elements 40A and the pair of second elements 40B is applied to the gate electrode 43.
  • the size of the gate electrode 43 is smaller than the size of the first electrode 41.
  • the insulating film 44 is provided on the first surface 401.
  • the insulating film 44 surrounds the first electrode 41 when viewed along the thickness direction z.
  • the insulating film 44 is formed by laminating, for example, a silicon dioxide (SiO 2) layer, a silicon nitride (Si 3 N 4) layer, and a polybenzoxazole (PBO) layer in this order from the first surface 401.
  • Insulating film 44 may be a polyimide layer instead of the polybenzoxazole layer.
  • the plurality of gate terminals 33 are located on both sides of the first direction x in the semiconductor device B10 as shown in FIGS.
  • the plurality of gate terminals 33 are arranged corresponding to the number of the pair of first elements 40A and the pair of second elements 40B.
  • a gate voltage for driving one of the pair of first elements 40A and the pair of second elements 40B corresponding thereto is applied to each of the plurality of gate terminals 33.
  • Each of the plurality of gate terminals 33 includes a pad portion 331 and a terminal portion 332.
  • the pad portion 331 is separated from the base material 10 as viewed along the thickness direction z, and is covered with the sealing resin 60. Accordingly, the plurality of gate terminals 33 are supported by the sealing resin 60.
  • One of a plurality of gate wires 503 is connected to the surface of the pad portion 331.
  • the plurality of gate wires 503 are made of aluminum, for example. Note that the surface of the pad portion 331 may be subjected to, for example, silver plating.
  • each of the plurality of gate wires 503 connected to the surfaces of the plurality of pad portions 331 is a gate of one of the corresponding pair of first elements 40A and the pair of second elements 40B. It is connected to the electrode 43. Thereby, each of the plurality of gate terminals 33 is electrically connected to either the gate electrode 43 of the pair of first elements 40A or the gate electrode 43 of the pair of second elements 40B.
  • the terminal portion 332 is connected to the pad portion 331 and exposed from the sealing resin 60.
  • the terminal portion 332 is used when the semiconductor device B10 is mounted on a wiring board.
  • the terminal portion 332 has a base portion 332A and an upright portion 332B.
  • the base portion 332 ⁇ / b> A is connected to the pad portion 331 and extends in a first direction x from one of a pair of first side surfaces 631 (details will be described later) of the sealing resin 60.
  • the dimension of the base portion 332A in the first direction x is smaller than the dimensions of the base portion 312A of the pair of input terminals 31 and the base portions 322A of the pair of output terminals 32 in the first direction x. As shown in FIGS.
  • the standing portion 332 ⁇ / b> B extends from the tip of the base portion 332 ⁇ / b> A in the first direction x toward the side where the first main surface 11 ⁇ / b> A of the base material 10 in the thickness direction z faces. Accordingly, as shown in FIGS. 7 to 9, the terminal portion 332 is L-shaped when viewed along the second direction y.
  • the pair of gate terminals 33 corresponding to the pair of first elements 40A are located on the other side in the first direction x in the semiconductor device B10.
  • the pair of gate terminals 33 are located between the pair of output terminals 32 in the second direction y.
  • the pair of gate terminals 33 corresponding to the pair of second elements 40B are located on one side in the first direction x in the semiconductor device B10.
  • the pair of gate terminals 33 are located between the pair of input terminals 31 in the second direction y.
  • the plurality of detection terminals 34 are located on both sides of the first direction x in the semiconductor device B10 as shown in FIGS.
  • the plurality of detection terminals 34 are arranged corresponding to the number of the pair of first elements 40A and the pair of second elements 40B.
  • Each of the plurality of detection terminals 34 is located next to the gate terminal 33 that is electrically connected to the gate electrode 43 of one of the pair of first elements 40A and the pair of second elements 40B to which it corresponds.
  • a voltage corresponding to the source current flowing through the first electrode 41 of one of the pair of first elements 40A and the pair of second elements 40B is applied to each of the plurality of detection terminals 34. Based on the voltage applied to each of the plurality of detection terminals 34, the source current flowing through the first electrode 41 is detected in the external circuit of the semiconductor device B10.
  • Each of the plurality of detection terminals 34 includes a pad portion 341 and a terminal portion 342.
  • the pad portion 341 is separated from the base material 10 as viewed along the thickness direction z, and is covered with the sealing resin 60. Thereby, the plurality of detection terminals 34 are supported by the sealing resin 60.
  • One of a plurality of detection wires 504 is connected to the surface of the pad portion 341.
  • the plurality of detection wires 504 are made of aluminum, for example.
  • the surface of the pad portion 341 may be subjected to silver plating, for example.
  • each of the plurality of detection wires 504 connected to the surfaces of the plurality of pad portions 341 has the first of the corresponding pair of first elements 40A and the pair of second elements 40B.
  • One electrode 41 is connected. Thereby, each of the plurality of detection terminals 34 is electrically connected to one of the first electrode 41 of the pair of first elements 40A and the first electrode 41 of the pair of second elements 40B.
  • the terminal portion 342 is connected to the pad portion 341 and exposed from the sealing resin 60.
  • the terminal portion 342 is used when the semiconductor device B10 is mounted on a wiring board.
  • the terminal part 342 has a base part 342A and an upright part 342B.
  • the base portion 342A is connected to the pad portion 341, and extends in any of the first direction x from any one of a pair of first side surfaces 631 (details will be described later) of the sealing resin 60.
  • the dimension in the first direction x of the base portion 342A is smaller than the dimensions in the first direction x of the base portions 312A of the pair of input terminals 31 and the base portions 322A of the pair of output terminals 32. As shown in FIGS.
  • the standing portion 342 ⁇ / b> B extends from the tip of the base portion 342 ⁇ / b> A in the first direction x toward the side where the first main surface 11 ⁇ / b> A of the base material 10 in the thickness direction z faces.
  • the terminal portion 342 has an L shape when viewed in the second direction y. Note that the shape of the terminal portion 342 is the same as the shape of the terminal portion 332 of the plurality of gate terminals 33.
  • the sealing resin 60 includes the base material 10 (except the first back surface 12A), the conductive member 20, the auxiliary conductive member 21, the connecting member 29, and a plurality of semiconductor elements 40 ( A pair of first elements 40A and a pair of second elements 40B) are covered.
  • the sealing resin 60 further covers the plurality of first wires 501, the plurality of second wires 502, the plurality of gate wires 503, the plurality of detection wires 504, the plurality of first connection wires 51, and the plurality of second connection wires 52. ing.
  • the sealing resin 60 is made of a material containing, for example, an epoxy resin.
  • the sealing resin 60 has a top surface 61, a bottom surface 62, a pair of first side surfaces 631, a pair of second side surfaces 632, and a pair of through holes 64.
  • the top surface 61 faces the side to which the first main surface 11A of the substrate 10 in the thickness direction z faces.
  • the bottom surface 62 faces the side on which the first back surface 12A of the substrate 10 in the thickness direction z faces.
  • the first back surface 12 ⁇ / b> A is exposed from the bottom surface 62.
  • the bottom surface 62 has a frame shape surrounding the first back surface 12A.
  • the pair of first side surfaces 631 are connected to both the top surface 61 and the bottom surface 62 and face the first direction x. From one side in the first direction x of the first side surface 631, the terminal portions 312 of the pair of input terminals 31, the terminal portions 332 of the pair of gate terminals 33 disposed corresponding to the pair of second elements 40B, and The terminal portions 342 of the pair of detection terminals 34 are exposed. From the other side of the first side surface 631 in the first direction x, the terminal portions 322 of the pair of output terminals 32, the terminal portions 332 of the pair of gate terminals 33 disposed corresponding to the pair of first elements 40A, and The terminal portions 342 of the pair of detection terminals 34 are exposed.
  • the pair of second side surfaces 632 are connected to both the top surface 61 and the bottom surface 62 and face the second direction y.
  • the pair of through holes 64 penetrates the sealing resin 60 from the top surface 61 to the bottom surface 62 in the thickness direction z.
  • the hole edges of the pair of through holes 64 are circular.
  • the pair of through holes 64 are located on both sides of the base material 10 in the second direction y.
  • the heat sink 70 dissipates heat generated from the plurality of semiconductor elements 40 into the atmosphere during the operation of the semiconductor device B10. As shown in FIG. 1, in the example shown by the semiconductor module A10, the heat sink 70 has a rectangular parallelepiped shape, but the shape of the heat sink 70 is not limited to this.
  • the heat sink 70 is made of a metal having a relatively high thermal conductivity. Examples of the metal include copper, iron (Fe), and aluminum.
  • the heat sink 70 has an upper surface 71 and a pair of fastening members 72.
  • the upper surface 71 faces the side where the semiconductor device B10 in the thickness direction z is located.
  • Each of the pair of fastening members 72 includes a bolt 721 and a nut 722.
  • the pair of bolts 721 extend from the upper surface 71 in the thickness direction z.
  • the arrangement interval (interval in the second direction y) and the diameter of the pair of bolts 721 correspond to the pair of through holes 64 provided in the sealing resin 60 of the semiconductor device B10.
  • each of the pair of bolts 721 is configured to be inserted into one of the pair of through holes 64.
  • the tip of each of the pair of bolts 721 is threaded.
  • the nut 722 is engaged with the bolt 721.
  • the nut 722 is in contact with the top surface 61 of the sealing resin 60 of the semiconductor device B10.
  • the bonding sheet 80 is interposed between the upper surface 71 of the heat sink 70 and the first back surface 12A of the base material 10 of the semiconductor device B10.
  • the joining sheet 80 is an elastic sheet having electrical insulation and flexibility.
  • the thermal conductivity of the bonding sheet 80 is 10 W / (m ⁇ K) or more and 25 W / (m ⁇ K) or less. Therefore, the thermal conductivity of the bonding sheet 80 is the thermal conductivity of the sealing resin 60 of the semiconductor device B10 (the thermal conductivity of the sealing resin 60 made of a material containing an epoxy resin is 0.2 to 0.5 W / ( m ⁇ K)).
  • the thickness of the joining sheet 80 is 0.2 mm or more and 0.6 mm or less.
  • the bonding sheet 80 contains a filler containing boron nitride (BN).
  • both the first back surface 12 ⁇ / b> A of the base material 10 and the bottom surface 62 of the sealing resin 60 are pressure-bonded to the bonding sheet 80.
  • the joining sheet 80 is pressed by the upper surface 71 of the heat sink 70, the first back surface 12A, and the bottom surface 62. Crimping can be performed.
  • the surface treatment region 19 formed on the first back surface 12 ⁇ / b> A is in uniform contact with the bonding sheet 80. For this reason, the surface treatment region 19 is in a state of being engaged with the bonding sheet 80.
  • the semiconductor module A10 includes the semiconductor device B10 including the sealing resin 60 and the base material 10 having the first back surface 12A exposed from the sealing resin 60, the heat sink 70, and the bonding sheet 80.
  • the joining sheet 80 is interposed between the heat sink 70 and the first back surface 12A.
  • the thermal conductivity of the bonding sheet 80 is larger than the thermal conductivity of the sealing resin 60, the heat reaching the first back surface 12 ⁇ / b> A can be efficiently transferred to the heat sink 70.
  • the joining sheet 80 has flexibility, as shown in FIG. 16, even if there is unevenness on the upper surface 71 of the heat sink 70, the joining sheet 80 follows the unevenness and joins the heat sink 70. It can suppress that a space
  • the base material 10 and the heat sink 70 repeat thermal expansion and thermal contraction.
  • the compound when a compound is used instead of the bonding sheet 80, the compound gradually flows out due to the thermal expansion and contraction, and a gap is formed between the heat sink 70 and the semiconductor device B10 (pump (Out phenomenon) may occur.
  • the gap is formed, the heat dissipation of the semiconductor device B10 is lowered. Therefore, according to the bonding sheet 80 having flexibility, since the bonding sheet 80 follows the thermal expansion and contraction of the base material 10 and the heat sink 70, a gap is formed between the heat sink 70 and the semiconductor device B10. Can be prevented.
  • the first back surface 12A of the base material 10 is pressure-bonded to the bonding sheet 80.
  • a surface treatment region 19 including a rough surface is formed in a portion in contact with the bonding sheet 80.
  • the thermal conductivity of the bonding sheet 80 is preferably 10 W / (m ⁇ K) or more and 25 W / (m ⁇ K), which is larger than the thermal conductivity of the compound. Thereby, the heat dissipation of semiconductor device B10 can be improved more.
  • a filler containing boron nitride is contained in the bonding sheet 80 in order to obtain the thermal conductivity of the bonding sheet 80.
  • the semiconductor device B10 includes warpage C (the first back surface 12A of the base material 10, the boundary between the bottom surface 62 of the sealing resin 60 and the second side surface 632 (or the first side surface 631)). (Dimension in the thickness direction z) may occur.
  • the warp C is about 0.1 mm at the maximum. Therefore, in order to suppress the formation of the gap between the heat sink 70 and the semiconductor device B10, the bonding sheet 80 is used to fill the gap between the heat sink 70 and the semiconductor device B10 formed by the warp C.
  • the thickness is preferably 0.2 mm or more and 0.6 mm or less.
  • the bottom surface 62 of the sealing resin 60 is pressure-bonded to the bonding sheet 80.
  • the bottom surface 62 has a frame shape surrounding the first back surface 12 ⁇ / b> A of the base material 10.
  • the semiconductor module A20 includes a semiconductor device B20, a heat sink 70, and a bonding sheet 80. Among these, the configuration of the semiconductor device B20 is different from the semiconductor module A10 described above. Note that the cross-sectional position of the semiconductor device B20 illustrated in FIG. 18 is the same as the cross-sectional position of the semiconductor device B10 illustrated in FIG. The cross-sectional position of the semiconductor device B20 shown in FIG. 19 is the same as the cross-sectional position of the semiconductor device B10 shown in FIG. The cross-sectional position of the semiconductor module A20 shown in FIG. 21 is the same as the cross-sectional position of the semiconductor module A10 shown in FIG.
  • the semiconductor device B20 constituting the semiconductor module A20 will be described.
  • the configuration of the substrate 10 is different from the semiconductor device B10 of the semiconductor module A10 described above.
  • the external shape and circuit configuration of the semiconductor device B20 are the same as the external shape and circuit configuration of the semiconductor device B10 shown in FIGS.
  • the substrate 10 has a first substrate 10A and a second substrate 10B.
  • the first base material 10A includes a first main surface 11A and a second back surface 12B. Among these, the second back surface 12B faces the side opposite to the first main surface 11A.
  • the first base material 10A has electrical insulation.
  • the first base material 10A is made of a material containing ceramics having excellent thermal conductivity. Examples of the ceramic include aluminum nitride (AlN).
  • the second base material 10B includes a first back surface 12A and a second main surface 11B. Among these, the 2nd main surface 11B faces the opposite side to 12 A of 1st back surfaces.
  • the second base material 10B has conductivity.
  • Second substrate 10B is made of copper, for example.
  • the second main surface 11B is joined to the second back surface 12B.
  • the base material 10 is a composite member made of different materials.
  • a surface treatment region 19 including a rough surface is formed on the first back surface 12A of the second base material 10B.
  • the surface treatment region 19 is formed over the entire first back surface 12A.
  • the bonding sheet 80 is interposed between the upper surface 71 of the heat sink 70 and the first back surface 12A of the second base material 10B of the semiconductor device B20.
  • both the first back surface 12A of the second base material 10B and the bottom surface 62 of the sealing resin 60 are pressure-bonded to the bonding sheet 80.
  • the surface treatment region 19 formed on the first back surface 12 ⁇ / b> A of the second base material 10 ⁇ / b> B is uniformly in contact with the bonding sheet 80. For this reason, the surface treatment region 19 is in a state of being engaged with the bonding sheet 80.
  • the semiconductor module A20 includes the semiconductor device B20 including the sealing resin 60 and the base material 10 having the first back surface 12A exposed from the sealing resin 60, the heat sink 70, and the bonding sheet 80.
  • the joining sheet 80 has electrical insulation and flexibility, and is interposed between the heat sink 70 and the first back surface 12A.
  • the thermal conductivity of the bonding sheet 80 is larger than the thermal conductivity of the sealing resin 60. Therefore, even with the semiconductor module A20, the heat dissipation of the semiconductor device B20 can be further improved.
  • the base material 10 of the semiconductor device B20 has a first base material 10A and a second base material 10B.
  • the first main surface 11A of the second base material 10B is joined to the second back surface 12B of the first base material 10A.
  • a metal such as copper as the material of the second base material 10B
  • the thermal conductivity of the whole base material 10 can be made larger than the thermal conductivity of the base material 10 of the semiconductor device B10. Therefore, the heat dissipation of the semiconductor device B20 can be made larger than that of the semiconductor device B10.
  • FIG. 23 the semiconductor module A30 includes a semiconductor device B30, a heat sink 70, and a bonding sheet 80. Among these, the configurations of the semiconductor device B30 and the heat sink 70 are different from the semiconductor module A10 described above.
  • the sealing resin 60 is transmitted for the sake of convenience. In FIG.
  • FIG. 26 passes through the sealing resin 60 and the second terminal 31 ⁇ / b> B for convenience of understanding.
  • the semiconductor device B30 has a pair of insulating substrates 22, a pair of gate layers 23, a pair of detection layers 24, a plurality of dummy terminals 35, an insulating member 39, a pair of third connection wires 53, and a pair of semiconductor devices B10.
  • a fourth connection wire 54 is further provided.
  • the semiconductor device B30 does not include the auxiliary conductive member 21, the connecting member 29, the plurality of first connection wires 51, and the plurality of second connection wires 52.
  • the side where the first terminal 31A and the second terminal 31B are located in the first direction x is referred to as “one side in the first direction x”.
  • the side where the output terminal 32 is located in the first direction x is referred to as “the other side in the first direction x”.
  • the semiconductor device B30 includes a pair of base materials 10 as shown in FIGS.
  • the pair of base materials 10 are separated from each other in the first direction x. Viewed along the thickness direction z, the pair of base materials 10 has a rectangular shape with the second direction y as a long side.
  • the material of the pair of base materials 10 is the same as the material of the base material 10 of the semiconductor device B10.
  • a surface treatment region 19 including a rough surface is formed on the first back surface 12A.
  • the surface treatment region 19 is formed over the entire first back surface 12A.
  • the semiconductor device B30 includes a conductive member 20, as shown in FIGS. 25, 26, 31, and 32.
  • the conductive member 20 includes a first conductive portion 20A and a second conductive portion 20B. Viewed along the thickness direction z, the first conductive portion 20A and the second conductive portion 20B have a rectangular shape with the second direction y as a long side. 20 A of 1st electroconductive parts are joined to 11 A of 1st main surfaces of the base material 10 located in the one side of the 1st direction x. In the first conductive portion 20A, the plurality of first elements 40A are joined to the surface thereof in a state of being electrically connected to the first conductive portion 20A.
  • the second conductive portion 20B is joined to the first main surface 11A of the base material 10 located on the other side in the first direction x.
  • the plurality of second elements 40B are joined to the surface thereof in a state of being electrically connected to the second conductive portion 20B.
  • the material of the conductive member 20 is the same as the material of the conductive member 20 of the semiconductor device B10.
  • the pair of insulating substrates 22 is bonded to the surface of the first conductive portion 20A and the other is bonded to the surface of the second conductive portion 20B. ing.
  • the pair of insulating substrates 22 has a strip shape extending in the second direction y.
  • the insulating substrate 22 bonded to the surface of the first conductive portion 20A is located on the other side in the first direction x with respect to the plurality of first elements 40A.
  • the insulating substrate 22 bonded to the surface of the second conductive portion 20B is located on one side in the first direction x with respect to the plurality of second elements 40B.
  • the pair of insulating substrates 22 is made of a material containing, for example, a glass epoxy resin.
  • the pair of gate layers 23 is disposed on the insulating substrate 22 bonded to the surface of the first conductive portion 20A, and the other is the second conductive layer. It arrange
  • the pair of gate layers 23 has a strip shape extending in the second direction y.
  • the pair of gate layers 23 has conductivity.
  • the pair of gate layers 23 is made of, for example, copper.
  • the pair of detection layers 24 is disposed on the insulating substrate 22 bonded to the surface of the first conductive portion 20A, and the other is the second conductive layer. It arrange
  • the pair of detection layers 24 has a strip shape extending in the second direction y.
  • the pair of detection layers 24 have conductivity.
  • the pair of detection layers 24 is made of copper, for example.
  • the semiconductor device B30 includes a first terminal 31A and a second terminal 31B, as shown in FIGS.
  • the first terminal 31A and the second terminal 31B are located on one side in the first direction x.
  • the first terminal 31A and the second terminal 31B are separated from each other in the thickness direction z.
  • the first terminal 31A and the second terminal 31B are metal plates.
  • the said metal plate consists of copper or a copper alloy, for example.
  • the first terminal 31A includes a pad portion 311 and a terminal portion 312.
  • the boundary between the pad portion 311 and the terminal portion 312 is a surface along the second direction y and the thickness direction z, and the sealing resin 60 located on one side in the first direction x. This is a surface including the first side surface 631.
  • the pad portion 311 is entirely covered with the sealing resin 60.
  • the other side of the pad portion 311 in the first direction x has a comb shape. This comb-like portion is joined to the surface thereof in a state of being electrically connected to the first conductive portion 20A. The joining is performed by solder joining or ultrasonic joining.
  • the first terminal 31A is electrically connected to the first conductive portion 20A.
  • the terminal portion 312 extends from the first side surface 631 in the first direction x.
  • the terminal portion 312 has a rectangular shape.
  • both sides of the terminal portion 312 in the second direction y are covered with the sealing resin 60.
  • Other portions of the terminal portion 312 are exposed from the first side surface 631.
  • the first terminal 31 ⁇ / b> A is supported by the sealing resin 60.
  • the base material 10 positioned on one side in the first direction x is supported by the first terminal 31A via the first conductive portion 20A.
  • the second terminal 31B has a pad portion 311 and a terminal portion 312.
  • the pad portion 311 has a connecting portion 311A and a plurality of extending portions 311B.
  • the connecting portion 311A has a strip shape extending in the second direction y.
  • the connecting portion 311A is connected to the terminal portion 312.
  • the plurality of extending portions 311B extend from the connecting portion 311A toward the other side in the first direction x.
  • the plurality of extending portions 311B are separated from each other in the second direction y.
  • the terminal portion 312 has a strip shape extending from the first side surface 631 in the first direction x. As viewed along the thickness direction z, the terminal portion 312 has a rectangular shape. In the example shown by the semiconductor device B ⁇ b> 30, both sides of the terminal portion 312 in the second direction y are covered with the sealing resin 60. Other portions of the terminal portion 312 are exposed from the first side surface 631. As shown in FIGS.
  • the terminal portion 312 overlaps the terminal portion 312 of the first terminal 31 ⁇ / b> A as viewed along the thickness direction z.
  • the shape of the terminal portion 312 is the same as the shape of the first terminal 31A, and when viewed along the thickness direction z, the entire terminal portion 312 is the first terminal 31A. It overlaps with the terminal portion 312.
  • the insulating member 39 is interposed between the first terminal 31A and the second terminal 31B in the thickness direction z.
  • the insulating member 39 is a flat plate.
  • the insulating member 39 is, for example, insulating paper.
  • the entire first terminal 31 ⁇ / b> A overlaps the insulating member 39.
  • the second terminal 31 ⁇ / b> B a part of the pad portion 311 and the entire terminal portion 312 overlap the insulating member 39 when viewed along the thickness direction z.
  • These portions that overlap the insulating member 39 when viewed along the thickness direction z are in contact with the insulating member 39.
  • the first terminal 31A and the second terminal 31B are insulated from each other by the insulating member 39.
  • a part of the insulating member 39 is covered with the sealing resin 60.
  • the semiconductor device B30 includes an output terminal 32 as shown in FIGS. 24 to 27 and FIG.
  • the output terminal 32 is located on the other side in the first direction x.
  • the output terminal 32 is a metal plate.
  • the said metal plate consists of copper or a copper alloy, for example.
  • the output terminal 32 has a pad portion 321 and a terminal portion 322.
  • the boundary between the pad portion 321 and the terminal portion 322 is a surface along the second direction y and the thickness direction z and the first side surface 631 of the sealing resin 60 located on the other side in the first direction x. It is a surface to include.
  • the pad portion 321 is entirely covered with the sealing resin 60.
  • One side of the pad portion 321 in the first direction x has a comb shape.
  • the comb-like portion is joined to the surface thereof in a state of conducting to the second conductive portion 20B.
  • the joining is performed by solder joining or ultrasonic joining.
  • the output terminal 32 is electrically connected to the second conductive portion 20B.
  • the terminal portion 322 extends from the first side surface 631 in the first direction x. Viewed along the thickness direction z, the terminal portion 322 has a rectangular shape.
  • both sides of the terminal portion 322 in the second direction y are covered with the sealing resin 60. Other portions of the terminal portion 322 are exposed from the first side surface 631.
  • the output terminal 32 is supported by the sealing resin 60.
  • the base material 10 positioned on the other side in the first direction x is supported by the output terminal 32 via the second conductive portion 20B.
  • the semiconductor device B30 includes a pair of gate terminals 33 and a pair of detection terminals 34, as shown in FIGS.
  • the pair of gate terminals 33 and the pair of detection terminals 34 are configured from the same lead frame together with the plurality of dummy terminals 35.
  • the lead frame is made of copper or a copper alloy.
  • the pair of gate terminals 33 is located next to the pair of base materials 10 in the second direction y.
  • One gate terminal 33 is located next to the substrate 10 located on one side in the first direction x.
  • the other gate terminal 33 is located next to the base material 10 located on the other side in the first direction x.
  • Each of the pair of gate terminals 33 includes a pad portion 331 and a terminal portion 332.
  • the pad portion 331 is covered with the sealing resin 60. Thereby, the pair of gate terminals 33 are supported by the sealing resin 60.
  • the surface of the pad portion 331 may be subjected to, for example, silver plating.
  • the terminal portion 332 is connected to the pad portion 331 and exposed from the second side surface 632 of the sealing resin 60 (see FIG. 30). When viewed along the first direction x, the terminal portion 332 has an L shape.
  • the pair of detection terminals 34 are located next to the pair of gate terminals 33 in the first direction x.
  • Each of the pair of detection terminals 34 includes a pad portion 341 and a terminal portion 342.
  • the pad portion 341 is covered with the sealing resin 60. Thereby, the pair of detection terminals 34 are supported by the sealing resin 60.
  • the surface of the pad portion 341 may be subjected to silver plating, for example.
  • the terminal portion 342 is connected to the pad portion 341 and exposed from the second side surface 632 of the sealing resin 60 (see FIG. 30). When viewed along the first direction x, the terminal portion 342 has an L shape.
  • the plurality of dummy terminals 35 are positioned on the opposite side of the pair of gate terminals 33 with respect to the pair of detection terminals 34 in the first direction x, as shown in FIGS. 25, 26 and 34.
  • the number of dummy terminals 35 is six. Of these, the three dummy terminals 35 are located on one side in the first direction x. The remaining three dummy terminals 35 are located on the other side in the first direction x.
  • the number of the dummy terminals 35 is not limited to this.
  • the semiconductor device B30 may be configured not to include a plurality of dummy terminals 35. Each of the plurality of dummy terminals 35 has a pad portion 351 and a terminal portion 352.
  • the pad portion 351 is covered with the sealing resin 60. Accordingly, the plurality of dummy terminals 35 are supported by the sealing resin 60. Note that the surface of the pad portion 351 may be subjected to silver plating, for example.
  • the terminal portion 352 is connected to the pad portion 351 and exposed from the second side surface 632 of the sealing resin 60 (see FIG. 30). As shown in FIGS. 28 and 29, the terminal portion 352 is L-shaped when viewed along the first direction x. Note that the shapes of the terminal portions 332 of the pair of gate terminals 33 and the terminal portions 342 of the pair of detection terminals 34 are the same as the shapes of the terminal portions 352.
  • the plurality of semiconductor elements 40 are joined in a state of conducting to the conductive member 20 so as to be staggered with respect to the second direction y when viewed along the thickness direction z. ing.
  • the plurality of first wires 501 connected to the first electrode 41 are connected to the surface of the second conductive portion 20B. Thereby, the plurality of first elements 40A are electrically connected to the second conductive portion 20B.
  • the multiple first wires 501 extend in the first direction x.
  • the gate wire 503 connected to the gate electrode 43 is connected to the gate layer 23 disposed on the insulating substrate 22 bonded to the first conductive portion 20A.
  • the detection wire 504 connected to any region of the first electrode 41 is connected to the detection layer 24 disposed on the insulating substrate 22 bonded to the first conductive portion 20A.
  • the plurality of second wires 502 connected to the first electrode 41 are connected to the extending portion 311B of the pad portion 311 of the second terminal 31B. Thereby, the plurality of second elements 40B are electrically connected to the second terminal 31B.
  • the plurality of second wires 502 extend in the first direction x.
  • the gate wire 503 connected to the gate electrode 43 is connected to the gate layer 23 disposed on the insulating substrate 22 bonded to the second conductive portion 20B.
  • the detection wire 504 connected to any region of the first electrode 41 is connected to the detection layer 24 disposed on the insulating substrate 22 bonded to the second conductive portion 20B.
  • the pair of third connection wires 53 are connected to the pair of gate layers 23 and the pair of gate terminals 33 as shown in FIGS.
  • the pair of third connection wires 53 are connected to the surfaces of the pair of pad portions 331.
  • the pair of third connection wires 53 is made of, for example, aluminum.
  • the gate terminal 33 located on one side in the first direction x is electrically connected to the gate electrodes 43 of the plurality of first elements 40A.
  • the gate terminal 33 located on the other side in the first direction x is electrically connected to the gate electrodes 43 of the plurality of second elements 40B.
  • the pair of third connection wires 53 are covered with the sealing resin 60.
  • the pair of fourth connection wires 54 are connected to the pair of detection layers 24 and the pair of detection terminals 34 as shown in FIGS. 25 and 34.
  • the pair of fourth connection wires 54 are connected to the surfaces of the pair of pad portions 341.
  • the pair of fourth connection wires 54 is made of, for example, aluminum.
  • the detection terminal 34 located on one side in the first direction x is electrically connected to the first electrodes 41 of the plurality of first elements 40A.
  • the detection terminal 34 located on the other side in the first direction x is electrically connected to the first electrodes 41 of the plurality of second elements 40B.
  • the pair of fourth connection wires 54 are covered with the sealing resin 60.
  • the sealing resin 60 includes a top surface 61, a bottom surface 62, a pair of first side surfaces 631, a pair of second side surfaces 632, a plurality of third side surfaces 633, and a plurality of fourth side surfaces 634. And a plurality of through holes 64. Note that, among these, the configurations of the top surface 61, the bottom surface 62, and the pair of second side surfaces 632 are the same as those in the semiconductor device B10 described above, and thus the description thereof is omitted here.
  • the pair of first side surfaces 631 are connected to both the top surface 61 and the bottom surface 62 and face the first direction x. From one side of the first side surface 631 in the first direction x, the terminal portion 312 of the first terminal 31A, the terminal portion 312 of the second terminal 31B, and the insulating member 39 are exposed. The terminal portion 322 of the output terminal 32 is exposed from the other side of the second side surface 632 in the first direction x.
  • the plurality of third side surfaces 633 are connected to both the top surface 61 and the bottom surface 62 and face the second direction y.
  • the multiple third side surfaces 633 include a pair of third side surfaces 633 located on one side in the first direction x and a pair of third side surfaces 633 located on the other side in the first direction x.
  • the pair of third side surfaces 633 are opposed to each other in the second direction y.
  • the pair of third side surfaces 633 are connected to both sides of the first side surface 631 in the second direction y.
  • the plurality of fourth side surfaces 634 are connected to both the top surface 61 and the bottom surface 62 and face the first direction x.
  • the plurality of fourth side surfaces 634 are located outside the semiconductor device B30 with respect to the pair of first side surfaces 631 in the first direction x.
  • the plurality of fourth side surfaces 634 includes a pair of fourth side surfaces 634 located on one side in the first direction x and a pair of fourth side surfaces 634 located on the other side in the first direction x. In each of one side and the other side of the first direction x, both sides of the pair of fourth side surfaces 634 in the second direction y are connected to the pair of second side surfaces 632 and the pair of third side surfaces 633.
  • the plurality of through holes 64 are positioned at the four corners of the sealing resin 60 as viewed along the thickness direction z. As shown in FIG. 31, the configuration of each of the plurality of through holes 64 is the same as the configuration of the through hole 64 of the semiconductor device B10.
  • the heat sink 70 has an upper surface 71 and a plurality of fastening members 72.
  • the upper surface 71 faces the side where the semiconductor device B30 in the thickness direction z is located.
  • Each of the plurality of fastening members 72 includes a bolt 721 and a nut 722.
  • the plurality of bolts 721 extend from the upper surface 71 in the thickness direction z.
  • the arrangement positions and diameters of the plurality of bolts 721 correspond to the plurality of through holes 64 provided in the sealing resin 60 of the semiconductor device B30.
  • each of the plurality of bolts 721 is configured to be inserted into one of the plurality of through holes 64.
  • a thread is cut at the tip of each of the plurality of bolts 721.
  • the nut 722 is engaged with the bolt 721.
  • the joining sheet 80 is interposed between the upper surface 71 of the heat sink 70 and the first back surface 12A of the pair of base materials 10 of the semiconductor device B30.
  • both the pair of first back surfaces 12 ⁇ / b> A and the bottom surface 62 of the sealing resin 60 are pressure bonded to the bonding sheet 80.
  • the surface treatment region 19 formed on the pair of first back surfaces 12A is in contact with the bonding sheet 80 uniformly. For this reason, the surface treatment region 19 is in a state of being engaged with the bonding sheet 80.
  • the semiconductor module A30 includes a semiconductor device B30 including a sealing resin 60 and a pair of base materials 10 having a first back surface 12A exposed from the sealing resin 60, a heat sink 70, and a bonding sheet 80.
  • the bonding sheet 80 has electrical insulation and flexibility, and is interposed between the heat sink 70 and the pair of first back surfaces 12A.
  • the thermal conductivity of the bonding sheet 80 is larger than the thermal conductivity of the sealing resin 60. Therefore, even with the semiconductor module A30, the heat dissipation of the semiconductor device B30 can be further improved.
  • the first terminal 31A and the second terminal 31B are separated from each other in the thickness direction z. As viewed along the thickness direction z, at least a part of the terminal portion 312 of the second terminal 31B overlaps the terminal portion 312 of the first terminal 31A. Thereby, in the use of the semiconductor device B30, the magnetic fields generated in the first terminal 31A and the second terminal 31B interfere with each other, thereby reducing the inductance of the first terminal 31A and the second terminal 31B. Therefore, since the surge voltage applied to the first terminal 31A and the second terminal 31B is reduced, the power loss of the semiconductor device B30 can be suppressed.
  • Appendix 1 A base material having a first main surface and a first back surface facing each other in the thickness direction, a conductive member disposed on the first main surface, and a plurality of semiconductors joined in a conductive state to the conductive member
  • a semiconductor device comprising: an element; and a sealing resin that covers the plurality of semiconductor elements such that the first back surface is exposed; A heat sink, A joining sheet interposed between the heat sink and the first back surface, The joining sheet has electrical insulation and flexibility, The semiconductor module whose thermal conductivity of the said joining sheet is larger than the thermal conductivity of the said sealing resin.
  • Appendix 2 The semiconductor module according to appendix 1, wherein the first back surface is pressure-bonded to the bonding sheet.
  • Appendix 3 The semiconductor module according to appendix 2, wherein a surface treatment region including a rough surface is formed in a portion in contact with the bonding sheet on the first back surface.
  • Appendix 4 The semiconductor module according to appendix 3, wherein the base material has electrical insulation.
  • Appendix 5 The semiconductor module according to appendix 4, wherein the base material is made of a material containing ceramics.
  • the base material includes a first base material having electrical insulation and a second base material having conductivity,
  • the first base material includes the first main surface and a second back surface facing the opposite side to the first main surface,
  • the second base material includes the first back surface, and a second main surface facing the side opposite to the first back surface,
  • Appendix 7 The semiconductor module according to appendix 6, wherein the second base material is made of a material containing copper.
  • Appendix 8 The semiconductor module according to any one of appendices 2 to 7, wherein the bonding sheet has a thermal conductivity of 10 W / (m ⁇ K) to 25 W / (m ⁇ K).
  • Appendix 9 The semiconductor module according to appendix 8, wherein the bonding sheet contains a filler containing boron nitride.
  • Appendix 10 The semiconductor module according to appendix 9, wherein the bonding sheet has a thickness of 0.2 mm to 0.6 mm.
  • the sealing resin has a bottom surface that faces the thickness direction and the first back surface is exposed, and a pair of side surfaces that are connected to the bottom surface and face a first direction orthogonal to the thickness direction.
  • Appendix 12 The semiconductor module according to appendix 11, wherein the bottom surface has a frame shape surrounding the first back surface.
  • the plurality of semiconductor elements include a first element and a second element
  • the conductive member includes a first conductive part joined in a state where the first element is conductive, and a second conductive part joined in a state where the second element is conductive
  • the semiconductor device further includes: a first terminal that conducts to the first conductive part; a second terminal that conducts to the second element; and an output terminal that conducts to the second conductive part.
  • Appendix 14 The semiconductor module according to appendix 13, wherein the conductive member is a metal plate.
  • Appendix 15 The first terminal and the second terminal are exposed from one surface of the pair of side surfaces, The semiconductor module according to appendix 13 or 14, wherein the output terminal is exposed from the other surface of the pair of side surfaces.
  • the first terminal and the second terminal are separated from each other in a second direction orthogonal to both the thickness direction and the first direction;
  • Each of the first terminal, the second terminal, and the output terminal has a terminal portion exposed from any one of the pair of side surfaces,
  • the terminal portion includes a base portion extending in the first direction from one of the pair of side surfaces, and a tip of the base portion in the first direction on a side where the first main surface faces in the thickness direction.
  • the semiconductor module according to appendix 15 further comprising an upright portion extending toward the surface.
  • Appendix 17 The first terminal and the second terminal are separated from each other in the thickness direction, Each of the first terminal and the second terminal has a terminal portion extending in the first direction from one surface of the pair of side surfaces, The semiconductor module according to appendix 15, wherein at least a part of the terminal portion of the second terminal overlaps the terminal portion of the first terminal as viewed along the thickness direction.

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  • Power Engineering (AREA)
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  • General Physics & Mathematics (AREA)
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Abstract

This semiconductor module includes a semiconductor device, a heat sink, and a connection sheet, as constituent elements thereof. The semiconductor device includes a substrate, a conductive member, a plurality of semiconductor elements, and a sealing resin. The substrate has a first major surface and a first rear surface which face opposite directions in a thickness direction. The conductive member is disposed on the first major surface. The plurality of semiconductor elements is connected, in electrical communication, to the conductive member. The sealing resin covers the plurality of semiconductor elements such that the first rear surface is exposed. The connection sheet is interposed between the heat sink and the first rear surface. The connection sheet is electrically insulating and flexible. The connection sheet has a thermal conductivity that is greater than the thermal conductivity of the sealing resin.

Description

半導体モジュールSemiconductor module
　本開示は、複数の半導体素子を備える半導体装置を、ヒートシンクに接合させた半導体モジュールに関する。 The present disclosure relates to a semiconductor module in which a semiconductor device including a plurality of semiconductor elements is bonded to a heat sink.
　特許文献１には、基板と、基板の上面に配置された金属箔と、金属箔に導通する状態で接合された複数のＩＧＢＴチップと、基板の下面に配置された放熱板とを備える半導体装置の一例が開示されている。当該半導体装置は、直流電力を交流電力に変換する電力変換を目的として利用される。放熱板と基板の下面との間には、基板と放熱板との間に形成される空隙を抑制するためのコンパウンド（シリコーングリス）が介在している。 Patent Document 1 discloses a semiconductor device including a substrate, a metal foil disposed on the upper surface of the substrate, a plurality of IGBT chips joined in a conductive state to the metal foil, and a heat sink disposed on the lower surface of the substrate. An example is disclosed. The semiconductor device is used for the purpose of power conversion for converting DC power into AC power. A compound (silicone grease) is interposed between the heat radiating plate and the lower surface of the substrate to suppress a gap formed between the substrate and the heat radiating plate.
　当該半導体装置の作動の際、複数のＩＧＢＴチップから熱が発生する。複数のＩＧＢＴチップから発生した熱は、金属箔、基板およびシリコーングリスを介して放熱板に伝導する。放熱板に伝導した熱は、大気中に放熱される。シリコーングリスは、比較的熱伝導率が高い材料ではあるものの、その熱伝導率は、１０Ｗ／（ｍ・Ｋ）未満である。近年、電力変換を目的とする半導体装置は、電気自動車などに利用されている。こうした半導体装置には、さらなる高出力化が要請されている。その要請を満たすためには、半導体装置の放熱性をより向上させることが課題となっている。 During the operation of the semiconductor device, heat is generated from the plurality of IGBT chips. Heat generated from the plurality of IGBT chips is conducted to the heat radiating plate through the metal foil, the substrate, and the silicone grease. The heat conducted to the heat sink is dissipated into the atmosphere. Silicone grease is a material having a relatively high thermal conductivity, but its thermal conductivity is less than 10 W / (m · K). In recent years, semiconductor devices intended for power conversion have been used in electric vehicles and the like. Such semiconductor devices are required to have higher output. In order to satisfy this requirement, it is an issue to further improve the heat dissipation of the semiconductor device.
特開２０００－２９９４１９号公報JP 2000-299419 A
　本開示は上記事情に鑑み、半導体装置の放熱性をより向上させることが可能な半導体モジュールを提供することをその課題とする。 In view of the above circumstances, it is an object of the present disclosure to provide a semiconductor module capable of further improving the heat dissipation of a semiconductor device.
　本開示によって提供される半導体モジュールは、厚さ方向において互いに反対側を向く第１主面および第１裏面を有する基材と、前記第１主面に配置された導電部材と、前記導電部材に導通する状態で接合された複数の半導体素子と、前記第１裏面が露出されるように前記複数の半導体素子を覆う封止樹脂と、を備える半導体装置と、ヒートシンクと、前記ヒートシンクと前記第１裏面との間に介在する接合シートと、を構成要素に含み、前記接合シートは、電気絶縁性および可とう性を有し、前記接合シートの熱伝導率が、前記封止樹脂の熱伝導率よりも大である。 A semiconductor module provided by the present disclosure includes: a base material having a first main surface and a first back surface facing opposite sides in the thickness direction; a conductive member disposed on the first main surface; and the conductive member. A semiconductor device comprising: a plurality of semiconductor elements joined in a conductive state; and a sealing resin that covers the plurality of semiconductor elements so that the first back surface is exposed; a heat sink; the heat sink; A joining sheet interposed between the back surface and the joining sheet, the joining sheet has electrical insulation and flexibility, and the thermal conductivity of the joining sheet is the thermal conductivity of the sealing resin. Is bigger than.
　本開示のその他の特徴および利点は、添付図面に基づき以下に行う詳細な説明によって、より明らかとなろう。 Other features and advantages of the present disclosure will become more apparent from the detailed description given below with reference to the accompanying drawings.
本開示の第１実施形態にかかる半導体モジュールの斜視図である。It is a perspective view of a semiconductor module concerning a 1st embodiment of this indication. 図１に示す半導体モジュールの構成要素に含まれる半導体装置の平面図である。It is a top view of the semiconductor device contained in the component of the semiconductor module shown in FIG. 図２に示す半導体装置の平面図であり、封止樹脂を透過している。FIG. 3 is a plan view of the semiconductor device shown in FIG. 2 and transmits a sealing resin. 図２に示す半導体装置の底面図である。FIG. 3 is a bottom view of the semiconductor device shown in FIG. 2. 図２に示す半導体装置の右側面図である。FIG. 3 is a right side view of the semiconductor device shown in FIG. 2. 図２に示す半導体装置の左側面図である。FIG. 3 is a left side view of the semiconductor device shown in FIG. 2. 図２に示す半導体装置の正面図である。FIG. 3 is a front view of the semiconductor device shown in FIG. 2. 図３のＶＩＩＩ－ＶＩＩＩ線に沿う断面図である。FIG. 4 is a sectional view taken along line VIII-VIII in FIG. 3. 図３のＩＸ－ＩＸ線に沿う断面図である。FIG. 4 is a cross-sectional view taken along line IX-IX in FIG. 3. 図３のＸ－Ｘ線に沿う断面図である。FIG. 4 is a cross-sectional view taken along line XX in FIG. 3. 図１０の部分拡大図である。It is the elements on larger scale of FIG. 図３の部分拡大図である。FIG. 4 is a partially enlarged view of FIG. 3. 図１２のＸＩＩＩ－ＸＩＩＩ線に沿う断面図である。FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 12. 図１に示す半導体モジュールの平面図である。It is a top view of the semiconductor module shown in FIG. 図１４のＸＶ－ＸＶ線に沿う断面図である。FIG. 15 is a sectional view taken along line XV-XV in FIG. 14. 図１５の部分拡大図である。It is the elements on larger scale of FIG. 図１５の部分拡大図である。It is the elements on larger scale of FIG. 本開示の第２実施形態にかかる半導体モジュールの構成要素に含まれる半導体装置の断面図である。It is sectional drawing of the semiconductor device contained in the component of the semiconductor module concerning 2nd Embodiment of this indication. 図１８に示す半導体装置の断面図である。It is sectional drawing of the semiconductor device shown in FIG. 図１９の部分拡大図である。It is the elements on larger scale of FIG. 本開示の第２実施形態にかかる半導体モジュールの断面図である。It is sectional drawing of the semiconductor module concerning 2nd Embodiment of this indication. 図２１の部分拡大図である。It is the elements on larger scale of FIG. 本開示の第３実施形態にかかる半導体モジュールの斜視図である。It is a perspective view of a semiconductor module concerning a 3rd embodiment of this indication. 図２３に示す半導体モジュールの構成要素に含まれる半導体装置の構成する半導体装置の平面図である。FIG. 24 is a plan view of the semiconductor device included in the semiconductor device included in the components of the semiconductor module illustrated in FIG. 23. 図２４に示す半導体装置の平面図であり、封止樹脂を透過している。FIG. 25 is a plan view of the semiconductor device shown in FIG. 24 and transmits the sealing resin. 図２５に対応する平面図であり、第２端子を透過している。FIG. 26 is a plan view corresponding to FIG. 25 and transmits the second terminal. 図２４に示す半導体装置の底面図である。FIG. 25 is a bottom view of the semiconductor device shown in FIG. 24. 図２４に示す半導体装置の右側面図である。FIG. 25 is a right side view of the semiconductor device shown in FIG. 24. 図２４に示す半導体装置の左側面図である。FIG. 25 is a left side view of the semiconductor device shown in FIG. 24. 図２４に示す半導体装置の正面図である。FIG. 25 is a front view of the semiconductor device shown in FIG. 24. 図２５のＸＸＸＩ－ＸＸＸＩ線に沿う断面図である。FIG. 26 is a sectional view taken along line XXXI-XXXI in FIG. 図２５のＸＸＸＩＩ－ＸＸＸＩＩ線に沿う断面図である。FIG. 26 is a sectional view taken along line XXXII-XXXII in FIG. 25. 図３２の部分拡大図である。It is the elements on larger scale of FIG. 図２５の部分拡大図である。It is the elements on larger scale of FIG. 図２３に示す半導体モジュールの平面図である。FIG. 24 is a plan view of the semiconductor module shown in FIG. 23. 図３５のＸＸＸＶＩ－ＸＸＸＶＩ線に沿う断面図である。FIG. 36 is a sectional view taken along line XXXVI-XXXVI in FIG. 35. 図３６の部分拡大図である。It is the elements on larger scale of FIG.
　本開示を実施するための形態について、添付図面に基づいて説明する。 DETAILED DESCRIPTION Embodiments for carrying out the present disclosure will be described with reference to the accompanying drawings.
　〔第１実施形態〕
　図１～図１６に基づき、本開示の第１実施形態にかかる半導体モジュールＡ１０について説明する。図１に示すように、半導体モジュールＡ１０は、半導体装置Ｂ１０、ヒートシンク７０および接合シート８０を、その構成要素に含む。なお、図３は、理解の便宜上、封止樹脂６０を透過している。図３においては、ＶＩＩＩ-ＶＩＩＩ線、ＩＸ－ＩＸ線およびＸ－Ｘ線を一点鎖線で示している。 [First Embodiment]
The semiconductor module A10 according to the first embodiment of the present disclosure will be described based on FIGS. As shown in FIG. 1, the semiconductor module A10 includes a semiconductor device B10, a heat sink 70, and a bonding sheet 80 as its components. In FIG. 3, the sealing resin 60 is transmitted for convenience of understanding. In FIG. 3, the VIII-VIII line, the IX-IX line, and the XX line are indicated by alternate long and short dash lines.
　＜半導体装置Ｂ１０＞
　以下、半導体モジュールＡ１０の構成要素に含まれる半導体装置Ｂ１０について説明する。図１に示す半導体装置Ｂ１０は、ＭＯＳＦＥＴなどの複数の半導体素子を搭載した電力変換装置（パワーモジュール）である。半導体装置Ｂ１０は、モータなどの駆動源や、様々な電気製品のインバータ装置に用いられる。半導体装置Ｂ１０は、基材１０、導電部材２０、補助導電部材２１、一対の入力端子３１、一対の出力端子３２、複数のゲート端子３３、複数の検出端子３４、複数の半導体素子４０、および封止樹脂６０を備える。 <Semiconductor device B10>
Hereinafter, the semiconductor device B10 included in the components of the semiconductor module A10 will be described. A semiconductor device B10 shown in FIG. 1 is a power conversion device (power module) on which a plurality of semiconductor elements such as MOSFETs are mounted. The semiconductor device B10 is used for a drive source such as a motor or an inverter device of various electric products. The semiconductor device B10 includes a base material 10, a conductive member 20, an auxiliary conductive member 21, a pair of input terminals 31, a pair of output terminals 32, a plurality of gate terminals 33, a plurality of detection terminals 34, a plurality of semiconductor elements 40, and a seal. A stop resin 60 is provided.
　半導体装置Ｂ１０の説明においては、便宜上、基材１０の厚さ方向を「厚さ方向ｚ」と呼ぶ。厚さ方向ｚに対して直交する方向を「第１方向ｘ」と呼ぶ。厚さ方向ｚおよび第１方向ｘの双方に対して直交する方向を「第２方向ｙ」と呼ぶ。半導体装置Ｂ１０は、厚さ方向ｚに沿って視て、すなわち平面視において矩形状である。第１方向ｘは、半導体装置Ｂ１０の短手方向に対応する。第２方向ｙは、半導体装置Ｂ１０の長手方向に対応する。また、半導体装置Ｂ１０の説明においては、便宜上、第１方向ｘのうち一対の入力端子３１が位置する側を「第１方向ｘの一方側」と呼ぶ。第１方向ｘのうち一対の出力端子３２が位置する側を「第１方向ｘの他方側」と呼ぶ。 In the description of the semiconductor device B10, for convenience, the thickness direction of the base material 10 is referred to as “thickness direction z”. A direction orthogonal to the thickness direction z is referred to as a “first direction x”. A direction orthogonal to both the thickness direction z and the first direction x is referred to as a “second direction y”. The semiconductor device B10 is rectangular when viewed along the thickness direction z, that is, when viewed in plan. The first direction x corresponds to the short direction of the semiconductor device B10. The second direction y corresponds to the longitudinal direction of the semiconductor device B10. In the description of the semiconductor device B10, for convenience, the side where the pair of input terminals 31 is located in the first direction x is referred to as “one side in the first direction x”. The side where the pair of output terminals 32 is located in the first direction x is referred to as “the other side in the first direction x”.
　基材１０は、図３、図８および図１０に示すように、導電部材２０が配置されている。基材１０は、導電部材２０および複数の半導体素子４０の支持部材をなす。基材１０は、電気絶縁性を有する。基材１０は、熱伝導性が比較的高いセラミックスを含む材料からなる。当該セラミックスの例として、窒化アルミニウム（ＡｌＮ）が挙げられる。基材１０は、第１主面１１Ａおよび第１裏面１２Ａを有する。第１主面１１Ａおよび第１裏面１２Ａは、厚さ方向ｚにおいて互いに反対側を向く。第１主面１１Ａは、厚さ方向ｚのうち導電部材２０が配置される側を向く。第１主面１１Ａは、導電部材２０および複数の半導体素子４０とともに封止樹脂６０に覆われている。図４に示すように、第１裏面１２Ａは、封止樹脂６０から露出している。 As shown in FIGS. 3, 8 and 10, the base member 10 is provided with a conductive member 20. The base material 10 serves as a support member for the conductive member 20 and the plurality of semiconductor elements 40. The base material 10 has electrical insulation. The base material 10 is made of a material containing ceramics having relatively high thermal conductivity. An example of the ceramic is aluminum nitride (AlN). The substrate 10 has a first main surface 11A and a first back surface 12A. The first main surface 11A and the first back surface 12A face opposite to each other in the thickness direction z. 11 A of 1st main surfaces face the side in which the electrically-conductive member 20 is arrange | positioned among the thickness directions z. The first main surface 11 </ b> A is covered with the sealing resin 60 together with the conductive member 20 and the plurality of semiconductor elements 40. As shown in FIG. 4, the first back surface 12 </ b> A is exposed from the sealing resin 60.
　図１１に示すように、第１裏面１２Ａには、粗面を含む表面処理領域１９が形成されている。表面処理領域１９は、サンドブラストなどにより形成することができる。半導体装置Ｂ１０では、第１裏面１２Ａの全体にわたって表面処理領域１９が形成されている。 As shown in FIG. 11, a surface treatment region 19 including a rough surface is formed on the first back surface 12A. The surface treatment region 19 can be formed by sandblasting or the like. In the semiconductor device B10, the surface treatment region 19 is formed over the entire first back surface 12A.
　導電部材２０は、図３、図８および図１０に示すように、基材１０の第１主面１１Ａに配置されている。導電部材２０は、補助導電部材２１、一対の入力端子３１および一対の出力端子３２とともに、複数の半導体素子４０と、半導体装置Ｂ１０に実装される配線基板との導電経路を構成している。導電部材２０は、金属板である。当該金属板は、銅（Ｃｕ）または銅合金からなる。導電部材２０は、たとえば銀（Ａｇ）ペーストのような接合材（図示略）により第１主面１１Ａに接合されている。導電部材２０の表面には、たとえば銀めっきを施してもよい。なお、導電部材２０は、金属板に替えて、銅箔などの金属箔でもよい。 The conductive member 20 is disposed on the first main surface 11A of the substrate 10 as shown in FIGS. The conductive member 20, together with the auxiliary conductive member 21, the pair of input terminals 31, and the pair of output terminals 32, constitutes a conductive path between the plurality of semiconductor elements 40 and the wiring board mounted on the semiconductor device B10. The conductive member 20 is a metal plate. The said metal plate consists of copper (Cu) or a copper alloy. The conductive member 20 is bonded to the first main surface 11A by a bonding material (not shown) such as silver (Ag) paste. For example, silver plating may be applied to the surface of the conductive member 20. The conductive member 20 may be a metal foil such as a copper foil instead of the metal plate.
　図３に示すように、半導体装置Ｂ１０が示す例においては、導電部材２０は、一対の第１導電部２０Ａおよび一対の第２導電部２０Ｂを含む。なお、導電部材２０の構成は本実施形態に限定されず、半導体装置Ｂ１０に要求される性能に応じて設定された複数の半導体素子４０の個数に基づき、自在に設定可能である。 As shown in FIG. 3, in the example shown by the semiconductor device B10, the conductive member 20 includes a pair of first conductive portions 20A and a pair of second conductive portions 20B. The configuration of the conductive member 20 is not limited to this embodiment, and can be freely set based on the number of the plurality of semiconductor elements 40 set according to the performance required for the semiconductor device B10.
　図３に示すように、一対の第１導電部２０Ａは、第１主面１１Ａにおいて第１方向ｘの一方側に位置する。厚さ方向ｚに沿って視て、一対の第１導電部２０Ａは矩形状である。一対の第１導電部２０Ａは、第２方向ｙにおいて互いに離間している。 As shown in FIG. 3, the pair of first conductive portions 20A is located on one side in the first direction x on the first main surface 11A. As viewed along the thickness direction z, the pair of first conductive portions 20A has a rectangular shape. The pair of first conductive portions 20A are separated from each other in the second direction y.
　図３に示すように、一対の第２導電部２０Ｂは、第１主面１１Ａにおいて第１方向ｘの他方側に位置する。一対の第１導電部２０Ａおよび一対の第２導電部２０Ｂは、第１方向ｘにおいて互いに離間している。厚さ方向ｚに沿って視て、一対の第２導電部２０Ｂは矩形状である。一対の第２導電部２０Ｂは、第２方向ｙにおいて互いに離間している。 As shown in FIG. 3, the pair of second conductive portions 20B are located on the other side in the first direction x on the first main surface 11A. The pair of first conductive portions 20A and the pair of second conductive portions 20B are separated from each other in the first direction x. As viewed along the thickness direction z, the pair of second conductive portions 20B has a rectangular shape. The pair of second conductive portions 20B are separated from each other in the second direction y.
　補助導電部材２１は、図３および図１０に示すように、基材１０の第１主面１１Ａに配置されている。補助導電部材２１は、第１主面１１Ａにおいて第１方向ｘの一方側に、かつ第２方向ｙにおいて一対の第１導電部２０Ａの間に位置する。厚さ方向ｚに沿って視て、補助導電部材２１は矩形状である。補助導電部材２１は、導電部材２０と同一の材料からなる金属板である。補助導電部材２１は、たとえば銀（Ａｇ）ペーストのような接合材（図示略）により第１主面１１Ａに接合されている。補助導電部材２１の表面には、たとえば銀めっきを施してもよい。なお、補助導電部材２１は、金属板に替えて、銅箔などの金属箔でもよい。 The auxiliary conductive member 21 is disposed on the first main surface 11A of the base material 10 as shown in FIGS. The auxiliary conductive member 21 is located on one side of the first main surface 11A in the first direction x and between the pair of first conductive portions 20A in the second direction y. Viewed along the thickness direction z, the auxiliary conductive member 21 has a rectangular shape. The auxiliary conductive member 21 is a metal plate made of the same material as that of the conductive member 20. The auxiliary conductive member 21 is bonded to the first main surface 11A by a bonding material (not shown) such as silver (Ag) paste. For example, silver plating may be applied to the surface of the auxiliary conductive member 21. The auxiliary conductive member 21 may be a metal foil such as a copper foil instead of the metal plate.
　図３および図１０に示すように、半導体装置Ｂ１０は、連絡部材２９をさらに備える。連絡部材２９は、導電性を有する。連絡部材２９は、第２方向ｙに沿って延び、かつ補助導電部材２１を跨いだ状態で一対の第１導電部２０Ａの表面に接続されている。これにより、一対の第１導電部２０Ａは、連絡部材２９を介して相互に導通している。連絡部材２９は、複数のワイヤから構成される。当該複数のワイヤは、たとえばアルミニウム（Ａｌ）からなる。なお、連絡部材２９は、複数のワイヤに替えて、厚さ方向ｚに沿って視て第２方向ｙに延びる金属片でもよい。 As shown in FIGS. 3 and 10, the semiconductor device B <b> 10 further includes a connecting member 29. The connecting member 29 has conductivity. The connecting member 29 extends along the second direction y and is connected to the surfaces of the pair of first conductive portions 20 </ b> A while straddling the auxiliary conductive member 21. As a result, the pair of first conductive portions 20 </ b> A are electrically connected to each other via the connecting member 29. The connecting member 29 is composed of a plurality of wires. The plurality of wires are made of, for example, aluminum (Al). The connecting member 29 may be a metal piece that extends in the second direction y when viewed along the thickness direction z, instead of a plurality of wires.
　一対の入力端子３１は、図２～図４に示すように、半導体装置Ｂ１０において第１方向ｘの一方側に位置する。一対の入力端子３１は、第２方向ｙにおいて互いに離間している。一対の入力端子３１には、外部からの直流電源が供給される。半導体装置Ｂ１０においては、一対の入力端子３１は、一対の出力端子３２、複数のゲート端子３３および複数の検出端子３４とともに、同一のリードフレームから構成される。当該リードフレームは、銅または銅合金からなる。一対の入力端子３１は、第１端子３１Ａおよび第２端子３１Ｂを含む。第１端子３１Ａおよび第２端子３１Ｂの各々は、パッド部３１１および端子部３１２を有する。 The pair of input terminals 31 are located on one side in the first direction x in the semiconductor device B10, as shown in FIGS. The pair of input terminals 31 are separated from each other in the second direction y. The pair of input terminals 31 is supplied with external DC power. In the semiconductor device B <b> 10, the pair of input terminals 31 is composed of the same lead frame together with the pair of output terminals 32, the plurality of gate terminals 33, and the plurality of detection terminals 34. The lead frame is made of copper or a copper alloy. The pair of input terminals 31 includes a first terminal 31A and a second terminal 31B. Each of the first terminal 31A and the second terminal 31B has a pad portion 311 and a terminal portion 312.
　図３に示すように、パッド部３１１は、厚さ方向ｚに沿って視て基材１０に対して離間しており、かつ封止樹脂６０に覆われている。これにより、一対の入力端子３１は、封止樹脂６０に支持されている。パッド部３１１の表面には、第１接続ワイヤ５１が接続されている。第１接続ワイヤ５１は、たとえばアルミニウムからなる。なお、パッド部３１１の表面には、たとえば銀めっきを施してもよい。 As shown in FIG. 3, the pad portion 311 is separated from the base material 10 as viewed along the thickness direction z, and is covered with the sealing resin 60. As a result, the pair of input terminals 31 are supported by the sealing resin 60. A first connection wire 51 is connected to the surface of the pad portion 311. The first connection wire 51 is made of aluminum, for example. Note that the surface of the pad portion 311 may be subjected to, for example, silver plating.
　第１端子３１Ａは、一対の入力端子３１の正極（Ｐ端子）をなしている。図３および図８に示すように、第１端子３１Ａのパッド部３１１の表面に接続された第１接続ワイヤ５１は、一方の第１導電部２０Ａの表面に接続されている。これにより、第１端子３１Ａは、一対の第１導電部２０Ａに導通している。 The first terminal 31A is the positive electrode (P terminal) of the pair of input terminals 31. As shown in FIGS. 3 and 8, the first connection wire 51 connected to the surface of the pad portion 311 of the first terminal 31A is connected to the surface of one first conductive portion 20A. Thereby, the first terminal 31A is electrically connected to the pair of first conductive portions 20A.
　第２端子３１Ｂは、一対の入力端子３１の負極（Ｎ端子）をなしている。図３に示すように、第２端子３１Ｂのパッド部３１１の表面に接続された第１接続ワイヤ５１は、補助導電部材２１の表面に接続されている。これにより、第２端子３１Ｂは、補助導電部材２１に導通している。 The second terminal 31B is the negative electrode (N terminal) of the pair of input terminals 31. As shown in FIG. 3, the first connection wire 51 connected to the surface of the pad portion 311 of the second terminal 31 </ b> B is connected to the surface of the auxiliary conductive member 21. Thereby, the second terminal 31 </ b> B is electrically connected to the auxiliary conductive member 21.
　図３に示すように、端子部３１２は、パッド部３１１につながり、かつ封止樹脂６０から露出している。端子部３１２は、半導体装置Ｂ１０を配線基板に実装する際に用いられる。端子部３１２は、基部３１２Ａおよび起立部３１２Ｂを有する。基部３１２Ａは、パッド部３１１につながり、かつ第１方向ｘの一方側に位置する封止樹脂６０の第１側面６３１（詳細は後述）から第１方向ｘに延びている。図６に示すように、起立部３１２Ｂは、基部３１２Ａの第１方向ｘにおける先端から、厚さ方向ｚの基材１０の第１主面１１Ａが向く側に向けて延びている。これにより、図７～図９に示すように、第２方向ｙに沿って視て、端子部３１２はＬ字状をなしている。 As shown in FIG. 3, the terminal portion 312 is connected to the pad portion 311 and is exposed from the sealing resin 60. The terminal portion 312 is used when the semiconductor device B10 is mounted on a wiring board. The terminal portion 312 has a base portion 312A and an upright portion 312B. The base 312A is connected to the pad 311 and extends in the first direction x from a first side surface 631 (details will be described later) of the sealing resin 60 located on one side in the first direction x. As shown in FIG. 6, the standing portion 312 </ b> B extends from the tip of the base portion 312 </ b> A in the first direction x toward the side where the first main surface 11 </ b> A of the base material 10 in the thickness direction z faces. As a result, as shown in FIGS. 7 to 9, the terminal portion 312 has an L shape when viewed in the second direction y.
　一対の出力端子３２は、図２～図４に示すように、半導体装置Ｂ１０において第１方向ｘの他方側に位置する。一対の出力端子３２は、第２方向ｙにおいて互いに離間している。一対の出力端子３２から、複数の半導体素子４０により電力変換された交流電力（電圧）が出力される。一対の出力端子３２の各々は、パッド部３２１および端子部３２２を有する。なお、出力端子３２の本数は本実施形態に限定されず、半導体装置Ｂ１０に要求される性能に応じて自在に設定可能である。 The pair of output terminals 32 are located on the other side in the first direction x in the semiconductor device B10, as shown in FIGS. The pair of output terminals 32 are separated from each other in the second direction y. From the pair of output terminals 32, AC power (voltage) converted by the plurality of semiconductor elements 40 is output. Each of the pair of output terminals 32 includes a pad portion 321 and a terminal portion 322. Note that the number of output terminals 32 is not limited to this embodiment, and can be freely set according to the performance required for the semiconductor device B10.
　図３に示すように、パッド部３２１は、厚さ方向ｚに沿って視て基材１０に対して離間しており、かつ封止樹脂６０に覆われている。これにより、一対の出力端子３２は、封止樹脂６０に支持されている。パッド部３２１の表面には、第２接続ワイヤ５２が接続されている。第２接続ワイヤ５２は、たとえばアルミニウムからなる。なお、パッド部３２１の表面には、たとえば銀めっきを施してもよい。図３および図８に示すように、一対のパッド部３２１の表面に接続された複数の第２接続ワイヤ５２は、一対の第２導電部２０Ｂの表面に接続されている。これにより、一対の出力端子３２は、一対の第２導電部２０Ｂに導通している。 As shown in FIG. 3, the pad portion 321 is separated from the base material 10 as viewed along the thickness direction z, and is covered with the sealing resin 60. Accordingly, the pair of output terminals 32 are supported by the sealing resin 60. A second connection wire 52 is connected to the surface of the pad portion 321. The second connection wire 52 is made of aluminum, for example. Note that the surface of the pad portion 321 may be subjected to, for example, silver plating. As shown in FIGS. 3 and 8, the plurality of second connection wires 52 connected to the surfaces of the pair of pad portions 321 are connected to the surfaces of the pair of second conductive portions 20B. Thereby, the pair of output terminals 32 is electrically connected to the pair of second conductive portions 20B.
　図３に示すように、端子部３２２は、パッド部３２１につながり、かつ封止樹脂６０から露出している。端子部３２２は、半導体装置Ｂ１０を配線基板に実装する際に用いられる。端子部３２２は、基部３２２Ａおよび起立部３２２Ｂを有する。基部３２２Ａは、パッド部３２１につながり、かつ第１方向ｘの他方側に位置する封止樹脂６０の第１側面６３１（詳細は後述）から第１方向ｘに延びている。図５に示すように、起立部３２２Ｂは、基部３２２Ａの第１方向ｘにおける先端から、厚さ方向ｚの基材１０の第１主面１１Ａが向く側に向けて延びている。これにより、図７～図９に示すように、第２方向ｙに沿って視て、端子部３２２はＬ字状をなしている。なお、端子部３２２の形状は、一対の入力端子３１の端子部３１２の形状と同一である。 As shown in FIG. 3, the terminal portion 322 is connected to the pad portion 321 and exposed from the sealing resin 60. The terminal portion 322 is used when the semiconductor device B10 is mounted on a wiring board. The terminal portion 322 has a base portion 322A and an upright portion 322B. The base portion 322A is connected to the pad portion 321 and extends in the first direction x from a first side surface 631 (details will be described later) of the sealing resin 60 located on the other side in the first direction x. As shown in FIG. 5, the upright portion 322 </ b> B extends from the tip of the base portion 322 </ b> A in the first direction x toward the side where the first main surface 11 </ b> A of the base material 10 in the thickness direction z faces. As a result, as shown in FIGS. 7 to 9, the terminal portion 322 is L-shaped when viewed in the second direction y. Note that the shape of the terminal portion 322 is the same as the shape of the terminal portion 312 of the pair of input terminals 31.
　複数の半導体素子４０は、図３、図８および図９に示すように、導電部材２０を構成する一対の第１導電部２０Ａおよび一対の第２導電部２０Ｂに導通する状態で接合されている。複数の半導体素子４０は、厚さ方向ｚに沿って視て矩形状（半導体装置Ｂ１０では正方形状）である。半導体装置Ｂ１０が示す例においては、複数の半導体素子４０は、一対の第１素子４０Ａおよび一対の第２素子４０Ｂを含む。一対の第１素子４０Ａは、半導体装置Ｂ１０の上アーム回路を構成している。一対の第２素子４０Ｂは、半導体装置Ｂ１０の下アーム回路を構成している。なお、複数の半導体素子４０の個数は、本構成に限定されず、半導体装置Ｂ１０に要求される性能に応じて自在に設定可能である。 As shown in FIGS. 3, 8, and 9, the plurality of semiconductor elements 40 are joined to the pair of first conductive portions 20 </ b> A and the pair of second conductive portions 20 </ b> B constituting the conductive member 20. . The plurality of semiconductor elements 40 have a rectangular shape (square shape in the semiconductor device B10) when viewed along the thickness direction z. In the example shown by the semiconductor device B10, the plurality of semiconductor elements 40 include a pair of first elements 40A and a pair of second elements 40B. The pair of first elements 40A constitute an upper arm circuit of the semiconductor device B10. The pair of second elements 40B constitutes the lower arm circuit of the semiconductor device B10. Note that the number of the plurality of semiconductor elements 40 is not limited to this configuration, and can be freely set according to the performance required for the semiconductor device B10.
　一対の第１素子４０Ａおよび一対の第２素子４０Ｂは、炭化ケイ素（ＳｉＣ）を主とする半導体材料を用いて構成されたＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）である。なお、一対の第１素子４０Ａおよび一対の第２素子４０Ｂは、ＭＯＳＦＥＴに限らずＭＩＳＦＥＴ（Metal-Insulator-Semiconductor Field-Effect Transistor）を含む電界効果トランジスタや、ＩＧＢＴ（Insulated Gate Bipolar Transistor）のようなバイポーラトランジスタでもよい。半導体装置Ｂ１０の説明においては、複数の半導体素子４０は、一対の第１素子４０Ａおよび一対の第２素子４０Ｂを含むとともに、これら全てがｎチャンネル型、かつ縦型構造のＭＯＳＦＥＴである場合を、その一例としている。 The pair of first elements 40A and the pair of second elements 40B are MOSFETs (Metal-Oxide-Semiconductor-Field-Effect-Transistors) configured using a semiconductor material mainly composed of silicon carbide (SiC). The pair of first elements 40A and the pair of second elements 40B are not limited to MOSFETs, but are field effect transistors including MISFETs (Metal-Insulator-Semiconductor-Field-Effect-Transistors) or IGBTs (Insulated-Gate-Bipolar-Transistors). A bipolar transistor may be used. In the description of the semiconductor device B10, the plurality of semiconductor elements 40 include a pair of first elements 40A and a pair of second elements 40B, all of which are n-channel type and vertical structure MOSFETs. It is an example.
　図１２および図１３に示すように、一対の第１素子４０Ａおよび一対の第２素子４０Ｂの各々は、第１面４０１、第２面４０２、第１電極４１、第２電極４２、ゲート電極４３および絶縁膜４４を有する。第１面４０１および第２面４０２は、厚さ方向ｚにおいて互いに反対側を向く。このうち第１面４０１は、基材１０の第１主面１１Ａが向く側を向く。 As shown in FIGS. 12 and 13, each of the pair of first elements 40A and the pair of second elements 40B includes a first surface 401, a second surface 402, a first electrode 41, a second electrode 42, and a gate electrode 43. And an insulating film 44. The first surface 401 and the second surface 402 face away from each other in the thickness direction z. Among these, the 1st surface 401 faces the side where 11 A of 1st main surfaces of the base material 10 face.
　図１２および図１３に示すように、第１電極４１は、第１面４０１に設けられている。第１電極４１には、ソース電流が流れる。半導体装置Ｂ１０が示す例においては、第１電極４１は、４つの領域に分割されている。 As shown in FIGS. 12 and 13, the first electrode 41 is provided on the first surface 401. A source current flows through the first electrode 41. In the example shown by the semiconductor device B10, the first electrode 41 is divided into four regions.
　図１２に示すように、一対の第１素子４０Ａの第１電極４１の各々においては、分割された４つの領域に複数の第１ワイヤ５０１が個別に接続されている。複数の第１ワイヤ５０１は、たとえばアルミニウムからなる。一対の第１素子４０Ａの第１電極４１に接続された複数の第１ワイヤ５０１は、一対の第２導電部２０Ｂの表面に接続されている。これにより、一対の第１素子４０Ａの第１電極４１は、一対の第２導電部２０Ｂに導通している。 As shown in FIG. 12, in each of the first electrodes 41 of the pair of first elements 40A, a plurality of first wires 501 are individually connected to the four divided regions. The plurality of first wires 501 are made of aluminum, for example. The plurality of first wires 501 connected to the first electrodes 41 of the pair of first elements 40A are connected to the surfaces of the pair of second conductive portions 20B. Thereby, the first electrodes 41 of the pair of first elements 40A are electrically connected to the pair of second conductive portions 20B.
　図１２に示すように、一対の第２素子４０Ｂの第１電極４１の各々においては、分割された４つの領域に複数の第２ワイヤ５０２が個別に接続されている。複数の第２ワイヤ５０２は、たとえばアルミニウムからなる。一対の第２素子４０Ｂの第１電極４１に接続された複数の第２ワイヤ５０２は、補助導電部材２１の表面に接続されている。これにより、一対の第２素子４０Ｂの第１電極４１は、補助導電部材２１に導通している。したがって、第２端子３１Ｂは、補助導電部材２１を介して一対の第２素子４０Ｂに導通している。 As shown in FIG. 12, in each of the first electrodes 41 of the pair of second elements 40B, a plurality of second wires 502 are individually connected to the four divided regions. The plurality of second wires 502 are made of aluminum, for example. The plurality of second wires 502 connected to the first electrodes 41 of the pair of second elements 40 </ b> B are connected to the surface of the auxiliary conductive member 21. Thereby, the first electrodes 41 of the pair of second elements 40 </ b> B are electrically connected to the auxiliary conductive member 21. Therefore, the second terminal 31B is electrically connected to the pair of second elements 40B via the auxiliary conductive member 21.
　図１３に示すように、第２電極４２は、第２面４０２の全体にわたって設けられている。第２電極４２には、ドレイン電流が流れる。図１３に示すように、一対の第１素子４０Ａの第２電極４２の各々は、導電性を有する導電接合層４９により一対の第１導電部２０Ａのいずれかに導通する状態でその表面に接合されている。導電接合層４９は、たとえば錫（Ｓｎ）を主成分とする鉛フリーはんだである。図１３に示す一対の第１素子４０Ａの第２電極４２の各々と同様に、一対の第２素子４０Ｂの第２電極４２の各々は、導電接合層４９により一対の第２導電部２０Ｂのいずれかに導通する状態でその表面に接合されている。 As shown in FIG. 13, the second electrode 42 is provided over the entire second surface 402. A drain current flows through the second electrode 42. As shown in FIG. 13, each of the second electrodes 42 of the pair of first elements 40 </ b> A is bonded to the surface thereof in a state of being electrically connected to one of the pair of first conductive portions 20 </ b> A by the conductive bonding layer 49 having conductivity. Has been. The conductive bonding layer 49 is, for example, lead-free solder mainly composed of tin (Sn). Similarly to each of the second electrodes 42 of the pair of first elements 40 </ b> A shown in FIG. 13, each of the second electrodes 42 of the pair of second elements 40 </ b> B is connected to any of the pair of second conductive portions 20 </ b> B by the conductive bonding layer 49. It is joined to the surface in a state of electrical conduction.
　図１２に示すように、ゲート電極４３は、第１面４０１に設けられている。ゲート電極４３には、一対の第１素子４０Ａおよび一対の第２素子４０Ｂの各々が駆動するためのゲート電圧が印加される。ゲート電極４３の大きさは、第１電極４１の大きさよりも小とされている。 As shown in FIG. 12, the gate electrode 43 is provided on the first surface 401. A gate voltage for driving each of the pair of first elements 40A and the pair of second elements 40B is applied to the gate electrode 43. The size of the gate electrode 43 is smaller than the size of the first electrode 41.
　図１２および図１３に示すように、絶縁膜４４は、第１面４０１に設けられている。絶縁膜４４は、厚さ方向ｚに沿って視て第１電極４１を囲んでいる。絶縁膜４４は、たとえば二酸化ケイ素（ＳｉＯ2）層、窒化ケイ素（Ｓｉ3Ｎ4）層、ポリベンゾオキサゾール（ＰＢＯ）層が第１面４０１からこの順番で積層されたものである。なお、絶縁膜４４においては、当該ポリベンゾオキサゾール層に代えてポリイミド層でもよい。 As shown in FIGS. 12 and 13, the insulating film 44 is provided on the first surface 401. The insulating film 44 surrounds the first electrode 41 when viewed along the thickness direction z. The insulating film 44 is formed by laminating, for example, a silicon dioxide (SiO 2) layer, a silicon nitride (Si 3 N 4) layer, and a polybenzoxazole (PBO) layer in this order from the first surface 401. Insulating film 44 may be a polyimide layer instead of the polybenzoxazole layer.
　複数のゲート端子３３は、図２～図４に示すように、半導体装置Ｂ１０において第１方向ｘの両側に位置する。複数のゲート端子３３は、一対の第１素子４０Ａおよび一対の第２素子４０Ｂの個数に対応して配置されている。複数のゲート端子３３の各々には、それが対応する一対の第１素子４０Ａおよび一対の第２素子４０Ｂのいずれかが駆動するためのゲート電圧が印加される。複数のゲート端子３３の各々は、パッド部３３１および端子部３３２を有する。 The plurality of gate terminals 33 are located on both sides of the first direction x in the semiconductor device B10 as shown in FIGS. The plurality of gate terminals 33 are arranged corresponding to the number of the pair of first elements 40A and the pair of second elements 40B. A gate voltage for driving one of the pair of first elements 40A and the pair of second elements 40B corresponding thereto is applied to each of the plurality of gate terminals 33. Each of the plurality of gate terminals 33 includes a pad portion 331 and a terminal portion 332.
　図３に示すように、パッド部３３１は、厚さ方向ｚに沿って視て基材１０に対して離間しており、かつ封止樹脂６０に覆われている。これにより、複数のゲート端子３３は、封止樹脂６０に支持されている。パッド部３３１の表面には、複数のゲートワイヤ５０３のいずれかが接続されている。複数のゲートワイヤ５０３は、たとえばアルミニウムからなる。なお、パッド部３３１の表面には、たとえば銀めっきを施してもよい。図３および図１２に示すように、複数のパッド部３３１の表面に接続された複数のゲートワイヤ５０３の各々は、対応する一対の第１素子４０Ａおよび一対の第２素子４０Ｂのいずれかのゲート電極４３に接続されている。これにより、複数のゲート端子３３の各々は、一対の第１素子４０Ａのゲート電極４３、および一対の第２素子４０Ｂのゲート電極４３のいずれかに導通している。 As shown in FIG. 3, the pad portion 331 is separated from the base material 10 as viewed along the thickness direction z, and is covered with the sealing resin 60. Accordingly, the plurality of gate terminals 33 are supported by the sealing resin 60. One of a plurality of gate wires 503 is connected to the surface of the pad portion 331. The plurality of gate wires 503 are made of aluminum, for example. Note that the surface of the pad portion 331 may be subjected to, for example, silver plating. As shown in FIG. 3 and FIG. 12, each of the plurality of gate wires 503 connected to the surfaces of the plurality of pad portions 331 is a gate of one of the corresponding pair of first elements 40A and the pair of second elements 40B. It is connected to the electrode 43. Thereby, each of the plurality of gate terminals 33 is electrically connected to either the gate electrode 43 of the pair of first elements 40A or the gate electrode 43 of the pair of second elements 40B.
　図３に示すように、端子部３３２は、パッド部３３１につながり、かつ封止樹脂６０から露出している。端子部３３２は、半導体装置Ｂ１０を配線基板に実装する際に用いられる。端子部３３２は、基部３３２Ａおよび起立部３３２Ｂを有する。基部３３２Ａは、パッド部３３１につながり、かつ封止樹脂６０の一対の第１側面６３１（詳細は後述）のいずれかから第１方向ｘに延びている。基部３３２Ａの第１方向ｘにおける寸法は、一対の入力端子３１の基部３１２Ａ、および一対の出力端子３２の基部３２２Ａの各々の第１方向ｘにおける寸法よりも小である。図５および図６に示すように、起立部３３２Ｂは、基部３３２Ａの第１方向ｘにおける先端から、厚さ方向ｚの基材１０の第１主面１１Ａが向く側に向けて延びている。これにより、図７～図９に示すように、第２方向ｙに沿って視て、端子部３３２はＬ字状をなしている。 As shown in FIG. 3, the terminal portion 332 is connected to the pad portion 331 and exposed from the sealing resin 60. The terminal portion 332 is used when the semiconductor device B10 is mounted on a wiring board. The terminal portion 332 has a base portion 332A and an upright portion 332B. The base portion 332 </ b> A is connected to the pad portion 331 and extends in a first direction x from one of a pair of first side surfaces 631 (details will be described later) of the sealing resin 60. The dimension of the base portion 332A in the first direction x is smaller than the dimensions of the base portion 312A of the pair of input terminals 31 and the base portions 322A of the pair of output terminals 32 in the first direction x. As shown in FIGS. 5 and 6, the standing portion 332 </ b> B extends from the tip of the base portion 332 </ b> A in the first direction x toward the side where the first main surface 11 </ b> A of the base material 10 in the thickness direction z faces. Accordingly, as shown in FIGS. 7 to 9, the terminal portion 332 is L-shaped when viewed along the second direction y.
　図３に示すように、一対の第１素子４０Ａに対応する一対のゲート端子３３は、半導体装置Ｂ１０において第１方向ｘの他方側に位置する。当該一対のゲート端子３３は、第２方向ｙにおいて一対の出力端子３２の間に位置する。また、一対の第２素子４０Ｂに対応する一対のゲート端子３３は、半導体装置Ｂ１０において第１方向ｘの一方側に位置する。当該一対のゲート端子３３は、第２方向ｙにおいて一対の入力端子３１の間に位置する。 As shown in FIG. 3, the pair of gate terminals 33 corresponding to the pair of first elements 40A are located on the other side in the first direction x in the semiconductor device B10. The pair of gate terminals 33 are located between the pair of output terminals 32 in the second direction y. The pair of gate terminals 33 corresponding to the pair of second elements 40B are located on one side in the first direction x in the semiconductor device B10. The pair of gate terminals 33 are located between the pair of input terminals 31 in the second direction y.
　複数の検出端子３４は、図２～図４に示すように、半導体装置Ｂ１０において第１方向ｘの両側に位置する。複数の検出端子３４は、一対の第１素子４０Ａおよび一対の第２素子４０Ｂの個数に対応して配置されている。複数の検出端子３４の各々は、それが対応する一対の第１素子４０Ａおよび一対の第２素子４０Ｂのいずれかのゲート電極４３に導通するゲート端子３３の隣に位置する。複数の検出端子３４の各々には、一対の第１素子４０Ａおよび一対の第２素子４０Ｂのいずれかの第１電極４１に流れるソース電流に対応した電圧が印加される。複数の検出端子３４の各々に印加された電圧に基づき、半導体装置Ｂ１０の外部回路において第１電極４１に流れるソース電流が検出される。複数の検出端子３４の各々は、パッド部３４１および端子部３４２を有する。 The plurality of detection terminals 34 are located on both sides of the first direction x in the semiconductor device B10 as shown in FIGS. The plurality of detection terminals 34 are arranged corresponding to the number of the pair of first elements 40A and the pair of second elements 40B. Each of the plurality of detection terminals 34 is located next to the gate terminal 33 that is electrically connected to the gate electrode 43 of one of the pair of first elements 40A and the pair of second elements 40B to which it corresponds. A voltage corresponding to the source current flowing through the first electrode 41 of one of the pair of first elements 40A and the pair of second elements 40B is applied to each of the plurality of detection terminals 34. Based on the voltage applied to each of the plurality of detection terminals 34, the source current flowing through the first electrode 41 is detected in the external circuit of the semiconductor device B10. Each of the plurality of detection terminals 34 includes a pad portion 341 and a terminal portion 342.
　図３に示すように、パッド部３４１は、厚さ方向ｚに沿って視て基材１０に対して離間しており、かつ封止樹脂６０に覆われている。これにより、複数の検出端子３４は、封止樹脂６０に支持されている。パッド部３４１の表面には、複数の検出ワイヤ５０４のいずれかが接続されている。複数の検出ワイヤ５０４は、たとえばアルミニウムからなる。なお、パッド部３４１の表面には、たとえば銀めっきを施してもよい。図３および図１２に示すように、複数のパッド部３４１の表面に接続された複数の検出ワイヤ５０４の各々は、対応する一対の第１素子４０Ａおよび一対の第２素子４０Ｂのいずれかの第１電極４１に接続されている。これにより、複数の検出端子３４の各々は、一対の第１素子４０Ａの第１電極４１、および一対の第２素子４０Ｂの第１電極４１のいずれかに導通している。 As shown in FIG. 3, the pad portion 341 is separated from the base material 10 as viewed along the thickness direction z, and is covered with the sealing resin 60. Thereby, the plurality of detection terminals 34 are supported by the sealing resin 60. One of a plurality of detection wires 504 is connected to the surface of the pad portion 341. The plurality of detection wires 504 are made of aluminum, for example. The surface of the pad portion 341 may be subjected to silver plating, for example. As shown in FIG. 3 and FIG. 12, each of the plurality of detection wires 504 connected to the surfaces of the plurality of pad portions 341 has the first of the corresponding pair of first elements 40A and the pair of second elements 40B. One electrode 41 is connected. Thereby, each of the plurality of detection terminals 34 is electrically connected to one of the first electrode 41 of the pair of first elements 40A and the first electrode 41 of the pair of second elements 40B.
　図３に示すように、端子部３４２は、パッド部３４１につながり、かつ封止樹脂６０から露出している。端子部３４２は、半導体装置Ｂ１０を配線基板に実装する際に用いられる。端子部３４２は、基部３４２Ａおよび起立部３４２Ｂを有する。基部３４２Ａは、パッド部３４１につながり、かつ封止樹脂６０の一対の第１側面６３１（詳細は後述）のいずれかから第１方向ｘに延びている。基部３４２Ａの第１方向ｘにおける寸法は、一対の入力端子３１の基部３１２Ａ、および一対の出力端子３２の基部３２２Ａの各々の第１方向ｘにおける寸法よりも小である。図５および図６に示すように、起立部３４２Ｂは、基部３４２Ａの第１方向ｘにおける先端から、厚さ方向ｚの基材１０の第１主面１１Ａが向く側に向けて延びている。これにより、図７～図９に示すように、第２方向ｙに沿って視て、端子部３４２はＬ字状をなしている。なお、端子部３４２の形状は、複数のゲート端子３３の端子部３３２の形状と同一である。 As shown in FIG. 3, the terminal portion 342 is connected to the pad portion 341 and exposed from the sealing resin 60. The terminal portion 342 is used when the semiconductor device B10 is mounted on a wiring board. The terminal part 342 has a base part 342A and an upright part 342B. The base portion 342A is connected to the pad portion 341, and extends in any of the first direction x from any one of a pair of first side surfaces 631 (details will be described later) of the sealing resin 60. The dimension in the first direction x of the base portion 342A is smaller than the dimensions in the first direction x of the base portions 312A of the pair of input terminals 31 and the base portions 322A of the pair of output terminals 32. As shown in FIGS. 5 and 6, the standing portion 342 </ b> B extends from the tip of the base portion 342 </ b> A in the first direction x toward the side where the first main surface 11 </ b> A of the base material 10 in the thickness direction z faces. As a result, as shown in FIGS. 7 to 9, the terminal portion 342 has an L shape when viewed in the second direction y. Note that the shape of the terminal portion 342 is the same as the shape of the terminal portion 332 of the plurality of gate terminals 33.
　封止樹脂６０は、図２～図４に示すように、基材１０（ただし、第１裏面１２Ａを除く。）、導電部材２０、補助導電部材２１、連絡部材２９、複数の半導体素子４０（一対の第１素子４０Ａおよび一対の第２素子４０Ｂ）を覆っている。封止樹脂６０は、複数の第１ワイヤ５０１、複数の第２ワイヤ５０２、複数のゲートワイヤ５０３、複数の検出ワイヤ５０４、複数の第１接続ワイヤ５１および複数の第２接続ワイヤ５２をさらに覆っている。封止樹脂６０は、たとえばエポキシ樹脂を含む材料からなる。図２に示すように、封止樹脂６０は、頂面６１、底面６２、一対の第１側面６３１、一対の第２側面６３２、および一対の貫通孔６４を有する。 As shown in FIGS. 2 to 4, the sealing resin 60 includes the base material 10 (except the first back surface 12A), the conductive member 20, the auxiliary conductive member 21, the connecting member 29, and a plurality of semiconductor elements 40 ( A pair of first elements 40A and a pair of second elements 40B) are covered. The sealing resin 60 further covers the plurality of first wires 501, the plurality of second wires 502, the plurality of gate wires 503, the plurality of detection wires 504, the plurality of first connection wires 51, and the plurality of second connection wires 52. ing. The sealing resin 60 is made of a material containing, for example, an epoxy resin. As shown in FIG. 2, the sealing resin 60 has a top surface 61, a bottom surface 62, a pair of first side surfaces 631, a pair of second side surfaces 632, and a pair of through holes 64.
　図８～図１０に示すように、頂面６１は、厚さ方向ｚの基材１０の第１主面１１Ａが向く側を向く。底面６２は、厚さ方向ｚの基材１０の第１裏面１２Ａが向く側を向く。図４に示すように、第１裏面１２Ａは、底面６２から露出している。底面６２は、第１裏面１２Ａを囲む枠状である。 As shown in FIGS. 8 to 10, the top surface 61 faces the side to which the first main surface 11A of the substrate 10 in the thickness direction z faces. The bottom surface 62 faces the side on which the first back surface 12A of the substrate 10 in the thickness direction z faces. As shown in FIG. 4, the first back surface 12 </ b> A is exposed from the bottom surface 62. The bottom surface 62 has a frame shape surrounding the first back surface 12A.
　図２および図４～図６に示すように、一対の第１側面６３１は、頂面６１および底面６２の双方につながり、かつ第１方向ｘを向く。第１側面６３１の第１方向ｘの一方側からは、一対の入力端子３１の端子部３１２と、一対の第２素子４０Ｂに対応して配置された一対のゲート端子３３の端子部３３２、および一対の検出端子３４の端子部３４２とが露出している。第１側面６３１の第１方向ｘの他方側からは、一対の出力端子３２の端子部３２２と、一対の第１素子４０Ａに対応して配置された一対のゲート端子３３の端子部３３２、および一対の検出端子３４の端子部３４２とが露出している。 2 and FIGS. 4 to 6, the pair of first side surfaces 631 are connected to both the top surface 61 and the bottom surface 62 and face the first direction x. From one side in the first direction x of the first side surface 631, the terminal portions 312 of the pair of input terminals 31, the terminal portions 332 of the pair of gate terminals 33 disposed corresponding to the pair of second elements 40B, and The terminal portions 342 of the pair of detection terminals 34 are exposed. From the other side of the first side surface 631 in the first direction x, the terminal portions 322 of the pair of output terminals 32, the terminal portions 332 of the pair of gate terminals 33 disposed corresponding to the pair of first elements 40A, and The terminal portions 342 of the pair of detection terminals 34 are exposed.
　図２、図４および図７に示すように、一対の第２側面６３２は、頂面６１および底面６２の双方につながり、かつ第２方向ｙを向く。 As shown in FIGS. 2, 4 and 7, the pair of second side surfaces 632 are connected to both the top surface 61 and the bottom surface 62 and face the second direction y.
　図２、図４および図１０に示すように、一対の貫通孔６４は、厚さ方向ｚにおいて頂面６１から底面６２に至って封止樹脂６０を貫通している。厚さ方向ｚに沿って視て、一対の貫通孔６４の孔縁は円形状である。一対の貫通孔６４は、基材１０の第２方向ｙの両側に位置する。 As shown in FIGS. 2, 4 and 10, the pair of through holes 64 penetrates the sealing resin 60 from the top surface 61 to the bottom surface 62 in the thickness direction z. When viewed along the thickness direction z, the hole edges of the pair of through holes 64 are circular. The pair of through holes 64 are located on both sides of the base material 10 in the second direction y.
　＜半導体モジュールＡ１０＞
　以下、半導体モジュールＡ１０について説明する。 <Semiconductor module A10>
Hereinafter, the semiconductor module A10 will be described.
　ヒートシンク７０は、半導体装置Ｂ１０の作動の際、複数の半導体素子４０から発生した熱を大気中に放熱させる。図１に示すように、半導体モジュールＡ１０が示す例においては、ヒートシンク７０は直方体状であるが、ヒートシンク７０の形状はこれに限定されない。ヒートシンク７０は、熱伝導率が比較的大である金属からなる。当該金属として、銅、鉄（Ｆｅ）およびアルミニウムが挙げられる。 The heat sink 70 dissipates heat generated from the plurality of semiconductor elements 40 into the atmosphere during the operation of the semiconductor device B10. As shown in FIG. 1, in the example shown by the semiconductor module A10, the heat sink 70 has a rectangular parallelepiped shape, but the shape of the heat sink 70 is not limited to this. The heat sink 70 is made of a metal having a relatively high thermal conductivity. Examples of the metal include copper, iron (Fe), and aluminum.
　図１４および図１５に示すように、ヒートシンク７０は、上面７１および一対の締結部材７２を有する。上面７１は、厚さ方向ｚの半導体装置Ｂ１０が位置する側を向く。一対の締結部材７２の各々は、ボルト７２１およびナット７２２により構成される。一対のボルト７２１は、上面７１から厚さ方向ｚに向けて延びている。一対のボルト７２１の配置間隔（第２方向ｙにおける間隔）および直径は、半導体装置Ｂ１０の封止樹脂６０に設けられた一対の貫通孔６４に対応している。これにより、一対のボルト７２１の各々は、一対の貫通孔６４のいずれかに挿入される構成となる。一対のボルト７２１の各々の先端には、ねじ切りがなされている。これにより、ナット７２２がボルト７２１に噛み合わされる。ナット７２２は、半導体装置Ｂ１０の封止樹脂６０の頂面６１に接している。 14 and 15, the heat sink 70 has an upper surface 71 and a pair of fastening members 72. The upper surface 71 faces the side where the semiconductor device B10 in the thickness direction z is located. Each of the pair of fastening members 72 includes a bolt 721 and a nut 722. The pair of bolts 721 extend from the upper surface 71 in the thickness direction z. The arrangement interval (interval in the second direction y) and the diameter of the pair of bolts 721 correspond to the pair of through holes 64 provided in the sealing resin 60 of the semiconductor device B10. Thereby, each of the pair of bolts 721 is configured to be inserted into one of the pair of through holes 64. The tip of each of the pair of bolts 721 is threaded. As a result, the nut 722 is engaged with the bolt 721. The nut 722 is in contact with the top surface 61 of the sealing resin 60 of the semiconductor device B10.
　接合シート８０は、図１５に示すように、ヒートシンク７０の上面７１と、半導体装置Ｂ１０の基材１０の第１裏面１２Ａとの間に介在している。接合シート８０は、電気絶縁性および可とう性を有する弾性シートである。接合シート８０の熱伝導率は、１０Ｗ／（ｍ・Ｋ）以上２５Ｗ／（ｍ・Ｋ）以下である。このため、接合シート８０の熱伝導率は、半導体装置Ｂ１０の封止樹脂６０の熱伝導率（エポキシ樹脂を含む材料からなる封止樹脂６０の熱伝導率は０．２～０．５Ｗ／（ｍ・Ｋ））よりも大である。接合シート８０の厚さは、０．２ｍｍ以上０．６ｍｍ以下である。接合シート８０には、窒化ホウ素（ＢＮ）を含むフィラーが含有されている。 As shown in FIG. 15, the bonding sheet 80 is interposed between the upper surface 71 of the heat sink 70 and the first back surface 12A of the base material 10 of the semiconductor device B10. The joining sheet 80 is an elastic sheet having electrical insulation and flexibility. The thermal conductivity of the bonding sheet 80 is 10 W / (m · K) or more and 25 W / (m · K) or less. Therefore, the thermal conductivity of the bonding sheet 80 is the thermal conductivity of the sealing resin 60 of the semiconductor device B10 (the thermal conductivity of the sealing resin 60 made of a material containing an epoxy resin is 0.2 to 0.5 W / ( m · K)). The thickness of the joining sheet 80 is 0.2 mm or more and 0.6 mm or less. The bonding sheet 80 contains a filler containing boron nitride (BN).
　図１５に示すように、半導体装置Ｂ１０においては、基材１０の第１裏面１２Ａ、および封止樹脂６０の底面６２の双方が接合シート８０に圧着されている。ヒートシンク７０に設けられた一対の締結部材７２において、ナット７２２をボルト７２１により強固に締め付けると、ヒートシンク７０の上面７１と、第１裏面１２Ａおよび底面６２とにより接合シート８０が押し当てられるため、当該圧着をなすことができる。図１６に示すように、第１裏面１２Ａに形成された表面処理領域１９は、接合シート８０に一様に接している。このため、表面処理領域１９は、接合シート８０に噛み合った状態となっている。 As shown in FIG. 15, in the semiconductor device B <b> 10, both the first back surface 12 </ b> A of the base material 10 and the bottom surface 62 of the sealing resin 60 are pressure-bonded to the bonding sheet 80. In the pair of fastening members 72 provided on the heat sink 70, when the nut 722 is firmly tightened with the bolt 721, the joining sheet 80 is pressed by the upper surface 71 of the heat sink 70, the first back surface 12A, and the bottom surface 62. Crimping can be performed. As shown in FIG. 16, the surface treatment region 19 formed on the first back surface 12 </ b> A is in uniform contact with the bonding sheet 80. For this reason, the surface treatment region 19 is in a state of being engaged with the bonding sheet 80.
　次に、半導体モジュールＡ１０の作用効果について説明する。 Next, functions and effects of the semiconductor module A10 will be described.
　半導体モジュールＡ１０では、封止樹脂６０、および封止樹脂６０から露出する第１裏面１２Ａを有する基材１０を備える半導体装置Ｂ１０と、ヒートシンク７０と、接合シート８０とを備える。接合シート８０は、ヒートシンク７０と第１裏面１２Ａとの間に介在している。これにより、半導体装置Ｂ１０の使用の際、複数の半導体素子４０から発せられた熱は、導電部材２０を介して第１裏面１２Ａに到達する。第１裏面１２Ａに到達した熱は、接合シート８０によりヒートシンク７０に伝熱される。接合シート８０の熱伝導率は、封止樹脂６０の熱伝導率よりも大であるため、第１裏面１２Ａに到達した熱を効率よくヒートシンク７０に伝熱させることができる。また、接合シート８０は、可とう性を有するため、図１６に示すように、ヒートシンク７０の上面７１に凹凸が存在する場合であっても、接合シート８０が凹凸に追随し、ヒートシンク７０と接合シート８０との間に空隙が形成されることを抑制できる。これにより、接合シート８０からヒートシンク７０に向けて熱を、より効率的に伝熱させることができる。したがって、半導体モジュールＡ１０によれば、半導体装置Ｂ１０の放熱性をより向上させることができる。 The semiconductor module A10 includes the semiconductor device B10 including the sealing resin 60 and the base material 10 having the first back surface 12A exposed from the sealing resin 60, the heat sink 70, and the bonding sheet 80. The joining sheet 80 is interposed between the heat sink 70 and the first back surface 12A. Thereby, when using the semiconductor device B <b> 10, the heat generated from the plurality of semiconductor elements 40 reaches the first back surface 12 </ b> A via the conductive member 20. The heat that has reached the first back surface 12 </ b> A is transferred to the heat sink 70 by the bonding sheet 80. Since the thermal conductivity of the bonding sheet 80 is larger than the thermal conductivity of the sealing resin 60, the heat reaching the first back surface 12 </ b> A can be efficiently transferred to the heat sink 70. In addition, since the joining sheet 80 has flexibility, as shown in FIG. 16, even if there is unevenness on the upper surface 71 of the heat sink 70, the joining sheet 80 follows the unevenness and joins the heat sink 70. It can suppress that a space | gap is formed between the sheets 80. Thereby, heat can be more efficiently transferred from the bonding sheet 80 toward the heat sink 70. Therefore, according to the semiconductor module A10, the heat dissipation of the semiconductor device B10 can be further improved.
　半導体装置Ｂ１０の使用により、基材１０およびヒートシンク７０は、熱膨張および熱収縮を繰り返す。半導体モジュールＡ１０において、接合シート８０の代わりにコンパウンドを用いた場合、これらの熱膨張および熱収縮により徐々にコンパウンドが流出され、ヒートシンク７０と半導体装置Ｂ１０との間に空隙が形成される現象（ポンプアウト現象）が生じることがある。空隙が形成されると、半導体装置Ｂ１０の放熱性が低下する。そこで、可とう性を有する接合シート８０によれば、基材１０およびヒートシンク７０の熱膨張および熱収縮に対して接合シート８０が追随するため、ヒートシンク７０と半導体装置Ｂ１０との間に空隙が形成されることを防止できる。 By using the semiconductor device B10, the base material 10 and the heat sink 70 repeat thermal expansion and thermal contraction. In the semiconductor module A10, when a compound is used instead of the bonding sheet 80, the compound gradually flows out due to the thermal expansion and contraction, and a gap is formed between the heat sink 70 and the semiconductor device B10 (pump (Out phenomenon) may occur. When the gap is formed, the heat dissipation of the semiconductor device B10 is lowered. Therefore, according to the bonding sheet 80 having flexibility, since the bonding sheet 80 follows the thermal expansion and contraction of the base material 10 and the heat sink 70, a gap is formed between the heat sink 70 and the semiconductor device B10. Can be prevented.
　基材１０の第１裏面１２Ａは、接合シート８０に圧着されている。第１裏面１２Ａにおいて、接合シート８０に接する部分には、粗面を含む表面処理領域１９が形成されている。これにより、第１裏面１２Ａの表面積が増加するため、接合シート８０に対する基材１０の接合強度が向上する。また、第１裏面１２Ａの放熱性が向上するため、第１裏面１２Ａから接合シート８０に、より効率的に熱を伝熱させることができる。 The first back surface 12A of the base material 10 is pressure-bonded to the bonding sheet 80. In the first back surface 12 </ b> A, a surface treatment region 19 including a rough surface is formed in a portion in contact with the bonding sheet 80. Thereby, since the surface area of 12 A of 1st back surfaces increases, the joining strength of the base material 10 with respect to the joining sheet 80 improves. Moreover, since the heat dissipation of the first back surface 12A is improved, heat can be more efficiently transferred from the first back surface 12A to the bonding sheet 80.
　接合シート８０の熱伝導率は、コンパウンドの熱伝導率よりも大である１０Ｗ／（ｍ・Ｋ）以上２５Ｗ／（ｍ・Ｋ）であることが好ましい。これにより、半導体装置Ｂ１０の放熱性をより向上させることができる。また、窒化ホウ素を含むフィラーが接合シート８０に含有されていることが、このような接合シート８０の熱伝導率を得る上で好適である。 The thermal conductivity of the bonding sheet 80 is preferably 10 W / (m · K) or more and 25 W / (m · K), which is larger than the thermal conductivity of the compound. Thereby, the heat dissipation of semiconductor device B10 can be improved more. In addition, it is preferable that a filler containing boron nitride is contained in the bonding sheet 80 in order to obtain the thermal conductivity of the bonding sheet 80.
　図１７に示すように、半導体装置Ｂ１０には反りＣ（基材１０の第１裏面１２Ａと、封止樹脂６０の底面６２と第２側面６３２（または第１側面６３１）との境界と、の間における厚さ方向ｚの寸法）が生じることがある。この反りＣは、最大で０．１ｍｍ程度とされている。そこで、ヒートシンク７０と半導体装置Ｂ１０との間の空隙の形成を抑制すべく、反りＣにより形成されるヒートシンク７０と半導体装置Ｂ１０との間の隙間を接合シート８０が埋めるためには、接合シート８０の厚さが０．２ｍｍ以上０．６ｍｍ以下であることが好ましい。 As shown in FIG. 17, the semiconductor device B10 includes warpage C (the first back surface 12A of the base material 10, the boundary between the bottom surface 62 of the sealing resin 60 and the second side surface 632 (or the first side surface 631)). (Dimension in the thickness direction z) may occur. The warp C is about 0.1 mm at the maximum. Therefore, in order to suppress the formation of the gap between the heat sink 70 and the semiconductor device B10, the bonding sheet 80 is used to fill the gap between the heat sink 70 and the semiconductor device B10 formed by the warp C. The thickness is preferably 0.2 mm or more and 0.6 mm or less.
　半導体モジュールＡ１０においては、封止樹脂６０の底面６２が接合シート８０に圧着されている。これにより、接合シート８０に対する半導体装置Ｂ１０の接合強度をより向上させることができる。底面６２は、基材１０の第１裏面１２Ａを囲む枠状である。このような形状をとる底面６２を接合シート８０に圧着させることにより、接合シート８０に対する第１裏面１２Ａの密着性がより高まるため、半導体装置Ｂ１０の放熱性をより向上させることができる。 In the semiconductor module A10, the bottom surface 62 of the sealing resin 60 is pressure-bonded to the bonding sheet 80. Thereby, the joining strength of the semiconductor device B10 to the joining sheet 80 can be further improved. The bottom surface 62 has a frame shape surrounding the first back surface 12 </ b> A of the base material 10. By pressure-bonding the bottom surface 62 having such a shape to the bonding sheet 80, the adhesion of the first back surface 12 </ b> A to the bonding sheet 80 is further increased, so that the heat dissipation of the semiconductor device B <b> 10 can be further improved.
　〔第２実施形態〕
　図１８～図２２に基づき、本開示の第２実施形態にかかる半導体モジュールＡ２０について説明する。これらの図において、先述した半導体モジュールＡ１０と同一または類似の要素には同一の符号を付して、重複する説明を省略する。半導体モジュールＡ２０は、半導体装置Ｂ２０、ヒートシンク７０および接合シート８０を備える。これらのうち、半導体装置Ｂ２０の構成が、先述した半導体モジュールＡ１０に対して異なる。なお、図１８に示す半導体装置Ｂ２０の断面位置は、図８に示す半導体装置Ｂ１０の断面位置と同一である。図１９に示す半導体装置Ｂ２０の断面位置は、図１０に示す半導体装置Ｂ１０の断面位置と同一である。図２１に示す半導体モジュールＡ２０の断面位置は、図１５に示す半導体モジュールＡ１０の断面位置と同一である。 [Second Embodiment]
A semiconductor module A20 according to the second embodiment of the present disclosure will be described with reference to FIGS. In these drawings, the same or similar elements as those of the semiconductor module A10 described above are denoted by the same reference numerals, and redundant description is omitted. The semiconductor module A20 includes a semiconductor device B20, a heat sink 70, and a bonding sheet 80. Among these, the configuration of the semiconductor device B20 is different from the semiconductor module A10 described above. Note that the cross-sectional position of the semiconductor device B20 illustrated in FIG. 18 is the same as the cross-sectional position of the semiconductor device B10 illustrated in FIG. The cross-sectional position of the semiconductor device B20 shown in FIG. 19 is the same as the cross-sectional position of the semiconductor device B10 shown in FIG. The cross-sectional position of the semiconductor module A20 shown in FIG. 21 is the same as the cross-sectional position of the semiconductor module A10 shown in FIG.
　＜半導体装置Ｂ２０＞
　以下、半導体モジュールＡ２０を構成する半導体装置Ｂ２０について説明する。半導体装置Ｂ２０においては、基材１０の構成が先述した半導体モジュールＡ１０の半導体装置Ｂ１０と異なる。なお、半導体装置Ｂ２０の外形および回路構成は、図２～図７に示す半導体装置Ｂ１０の外形および回路構成と同一である。 <Semiconductor device B20>
Hereinafter, the semiconductor device B20 constituting the semiconductor module A20 will be described. In the semiconductor device B20, the configuration of the substrate 10 is different from the semiconductor device B10 of the semiconductor module A10 described above. The external shape and circuit configuration of the semiconductor device B20 are the same as the external shape and circuit configuration of the semiconductor device B10 shown in FIGS.
　図１８および図１９に示すように、基材１０は、第１基材１０Ａおよび第２基材１０Ｂを有する。第１基材１０Ａは、第１主面１１Ａおよび第２裏面１２Ｂを含む。このうち、第２裏面１２Ｂは、第１主面１１Ａとは反対側を向く。第１基材１０Ａは、電気絶縁性を有する。第１基材１０Ａは、熱伝導性に優れたセラミックスを含む材料からなる。当該セラミックスとして、たとえば窒化アルミニウム（ＡｌＮ）が挙げられる。第２基材１０Ｂは、第１裏面１２Ａおよび第２主面１１Ｂを含む。このうち、第２主面１１Ｂは、第１裏面１２Ａとは反対側を向く。第２基材１０Ｂは、導電性を有する。第２基材１０Ｂは、たとえば銅からなる。第２主面１１Ｂは、第２裏面１２Ｂに接合されている。このように、基材１０は、異なる材料からなる複合部材となっている。 As shown in FIGS. 18 and 19, the substrate 10 has a first substrate 10A and a second substrate 10B. The first base material 10A includes a first main surface 11A and a second back surface 12B. Among these, the second back surface 12B faces the side opposite to the first main surface 11A. The first base material 10A has electrical insulation. The first base material 10A is made of a material containing ceramics having excellent thermal conductivity. Examples of the ceramic include aluminum nitride (AlN). The second base material 10B includes a first back surface 12A and a second main surface 11B. Among these, the 2nd main surface 11B faces the opposite side to 12 A of 1st back surfaces. The second base material 10B has conductivity. Second substrate 10B is made of copper, for example. The second main surface 11B is joined to the second back surface 12B. Thus, the base material 10 is a composite member made of different materials.
　図２０に示すように、半導体装置Ｂ２０においても、第２基材１０Ｂの第１裏面１２Ａには、粗面を含む表面処理領域１９が形成されている。半導体装置Ｂ２０では、第１裏面１２Ａの全体にわたって表面処理領域１９が形成されている。 As shown in FIG. 20, also in the semiconductor device B20, a surface treatment region 19 including a rough surface is formed on the first back surface 12A of the second base material 10B. In the semiconductor device B20, the surface treatment region 19 is formed over the entire first back surface 12A.
　＜半導体モジュールＡ２０＞
　以下、半導体モジュールＡ２０について説明する。なお、ヒートシンク７０の構成は、先述した半導体モジュールＡ１０における構成と同一であるため、ここでの説明は省略する。 <Semiconductor module A20>
Hereinafter, the semiconductor module A20 will be described. The configuration of the heat sink 70 is the same as that of the semiconductor module A10 described above, and a description thereof is omitted here.
　接合シート８０は、図２１に示すように、ヒートシンク７０の上面７１と、半導体装置Ｂ２０の第２基材１０Ｂの第１裏面１２Ａとの間に介在している。半導体装置Ｂ２０においては、第２基材１０Ｂの第１裏面１２Ａ、および封止樹脂６０の底面６２の双方が接合シート８０に圧着されている。図２２に示すように、第２基材１０Ｂの第１裏面１２Ａにおいて形成された表面処理領域１９は、接合シート８０に一様に接している。このため、表面処理領域１９は、接合シート８０に噛み合った状態となっている。 21, the bonding sheet 80 is interposed between the upper surface 71 of the heat sink 70 and the first back surface 12A of the second base material 10B of the semiconductor device B20. In the semiconductor device B20, both the first back surface 12A of the second base material 10B and the bottom surface 62 of the sealing resin 60 are pressure-bonded to the bonding sheet 80. As shown in FIG. 22, the surface treatment region 19 formed on the first back surface 12 </ b> A of the second base material 10 </ b> B is uniformly in contact with the bonding sheet 80. For this reason, the surface treatment region 19 is in a state of being engaged with the bonding sheet 80.
　次に、半導体モジュールＡ２０の作用効果について説明する。 Next, the function and effect of the semiconductor module A20 will be described.
　半導体モジュールＡ２０では、封止樹脂６０、および封止樹脂６０から露出する第１裏面１２Ａを有する基材１０を備える半導体装置Ｂ２０と、ヒートシンク７０と、接合シート８０とを備える。接合シート８０は、電気絶縁性および可とう性を有し、かつヒートシンク７０と第１裏面１２Ａとの間に介在している。接合シート８０の熱伝導率は、封止樹脂６０の熱伝導率よりも大である。したがって、半導体モジュールＡ２０のよっても、半導体装置Ｂ２０の放熱性をより向上させることができる。 The semiconductor module A20 includes the semiconductor device B20 including the sealing resin 60 and the base material 10 having the first back surface 12A exposed from the sealing resin 60, the heat sink 70, and the bonding sheet 80. The joining sheet 80 has electrical insulation and flexibility, and is interposed between the heat sink 70 and the first back surface 12A. The thermal conductivity of the bonding sheet 80 is larger than the thermal conductivity of the sealing resin 60. Therefore, even with the semiconductor module A20, the heat dissipation of the semiconductor device B20 can be further improved.
　半導体装置Ｂ２０の基材１０は、第１基材１０Ａおよび第２基材１０Ｂを有する。基材１０は、第２基材１０Ｂの第１主面１１Ａが第１基材１０Ａの第２裏面１２Ｂに接合されている。第２基材１０Ｂの材料として銅などの金属を採用することにより、基材１０全体の熱伝導率を、半導体装置Ｂ１０の基材１０の熱伝導率よりも大とすることができる。したがって、半導体装置Ｂ２０の放熱性を、半導体装置Ｂ１０の放熱性よりも大とすることができる。 The base material 10 of the semiconductor device B20 has a first base material 10A and a second base material 10B. In the base material 10, the first main surface 11A of the second base material 10B is joined to the second back surface 12B of the first base material 10A. By adopting a metal such as copper as the material of the second base material 10B, the thermal conductivity of the whole base material 10 can be made larger than the thermal conductivity of the base material 10 of the semiconductor device B10. Therefore, the heat dissipation of the semiconductor device B20 can be made larger than that of the semiconductor device B10.
　〔第３実施形態〕
　図２３～図３７に基づき、本開示の第３実施形態にかかる半導体モジュールＡ３０について説明する。これらの図において、先述した半導体モジュールＡ１０と同一または類似の要素には同一の符号を付して、重複する説明を省略する。図２３に示すように、半導体モジュールＡ３０は、半導体装置Ｂ３０、ヒートシンク７０および接合シート８０を備える。これらのうち、半導体装置Ｂ３０およびヒートシンク７０の構成が、先述した半導体モジュールＡ１０に対して異なる。なお、図２５は、理解の便宜上、封止樹脂６０を透過している。図２５においては、ＸＸＸＩ－ＸＸＸＩ線およびＸＸＸＩＩ－ＸＸＸＩＩ線を一点鎖線で示している。図２６は、理解の便宜上、封止樹脂６０および第２端子３１Ｂを透過している。 [Third Embodiment]
A semiconductor module A30 according to the third embodiment of the present disclosure will be described with reference to FIGS. In these drawings, the same or similar elements as those of the semiconductor module A10 described above are denoted by the same reference numerals, and redundant description is omitted. As shown in FIG. 23, the semiconductor module A30 includes a semiconductor device B30, a heat sink 70, and a bonding sheet 80. Among these, the configurations of the semiconductor device B30 and the heat sink 70 are different from the semiconductor module A10 described above. In FIG. 25, the sealing resin 60 is transmitted for the sake of convenience. In FIG. 25, the XXXXI-XXXI line and the XXXII-XXXII line are indicated by a one-dot chain line. FIG. 26 passes through the sealing resin 60 and the second terminal 31 </ b> B for convenience of understanding.
　＜半導体装置Ｂ３０＞
　以下、半導体モジュールＡ３０を構成する半導体装置Ｂ３０について説明する。半導体装置Ｂ３０は、半導体装置Ｂ１０に対して、一対の絶縁基板２２、一対のゲート層２３、一対の検出層２４、複数のダミー端子３５、絶縁部材３９、一対の第３接続ワイヤ５３および一対の第４接続ワイヤ５４をさらに備える。半導体装置Ｂ３０は、半導体装置Ｂ１０と異なり、補助導電部材２１、連絡部材２９、複数の第１接続ワイヤ５１および複数の第２接続ワイヤ５２を備えない。また、半導体装置Ｂ３０の説明においては、便宜上、第１方向ｘのうち第１端子３１Ａおよび第２端子３１Ｂが位置する側を「第１方向ｘの一方側」と呼ぶ。第１方向ｘのうち出力端子３２が位置する側を「第１方向ｘの他方側」と呼ぶ。 <Semiconductor device B30>
Hereinafter, the semiconductor device B30 constituting the semiconductor module A30 will be described. The semiconductor device B30 has a pair of insulating substrates 22, a pair of gate layers 23, a pair of detection layers 24, a plurality of dummy terminals 35, an insulating member 39, a pair of third connection wires 53, and a pair of semiconductor devices B10. A fourth connection wire 54 is further provided. Unlike the semiconductor device B10, the semiconductor device B30 does not include the auxiliary conductive member 21, the connecting member 29, the plurality of first connection wires 51, and the plurality of second connection wires 52. In the description of the semiconductor device B30, for convenience, the side where the first terminal 31A and the second terminal 31B are located in the first direction x is referred to as “one side in the first direction x”. The side where the output terminal 32 is located in the first direction x is referred to as “the other side in the first direction x”.
　半導体装置Ｂ３０は、図２５および図２６に示すように、一対の基材１０を備える。一対の基材１０は、第１方向ｘにおいて互いに離間している。厚さ方向ｚに沿って視て、一対の基材１０は、第２方向ｙを長辺とする矩形状である。一対の基材１０の材料は、半導体装置Ｂ１０の基材１０の材料と同一である。 The semiconductor device B30 includes a pair of base materials 10 as shown in FIGS. The pair of base materials 10 are separated from each other in the first direction x. Viewed along the thickness direction z, the pair of base materials 10 has a rectangular shape with the second direction y as a long side. The material of the pair of base materials 10 is the same as the material of the base material 10 of the semiconductor device B10.
　図３３に示すように、一対の基材１０の各々において、第１裏面１２Ａには、粗面を含む表面処理領域１９が形成されている。半導体装置Ｂ３０では、第１裏面１２Ａの全体にわたって表面処理領域１９が形成されている。 33, in each of the pair of base materials 10, a surface treatment region 19 including a rough surface is formed on the first back surface 12A. In the semiconductor device B30, the surface treatment region 19 is formed over the entire first back surface 12A.
　半導体装置Ｂ３０は、図２５、図２６、図３１および図３２に示すように、導電部材２０を備える。導電部材２０は、第１導電部２０Ａおよび第２導電部２０Ｂを含む。厚さ方向ｚに沿って視て、第１導電部２０Ａおよび第２導電部２０Ｂは、第２方向ｙを長辺とする矩形状である。第１導電部２０Ａは、第１方向ｘの一方側に位置する基材１０の第１主面１１Ａに接合されている。第１導電部２０Ａにおいては、複数の第１素子４０Ａが第１導電部２０Ａに導通する状態でその表面に接合されている。第２導電部２０Ｂは、第１方向ｘの他方側に位置する基材１０の第１主面１１Ａに接合されている。第２導電部２０Ｂにおいては、複数の第２素子４０Ｂが第２導電部２０Ｂに導通する状態でその表面に接合されている。導電部材２０の材料は、半導体装置Ｂ１０の導電部材２０の材料と同一である。 The semiconductor device B30 includes a conductive member 20, as shown in FIGS. 25, 26, 31, and 32. The conductive member 20 includes a first conductive portion 20A and a second conductive portion 20B. Viewed along the thickness direction z, the first conductive portion 20A and the second conductive portion 20B have a rectangular shape with the second direction y as a long side. 20 A of 1st electroconductive parts are joined to 11 A of 1st main surfaces of the base material 10 located in the one side of the 1st direction x. In the first conductive portion 20A, the plurality of first elements 40A are joined to the surface thereof in a state of being electrically connected to the first conductive portion 20A. The second conductive portion 20B is joined to the first main surface 11A of the base material 10 located on the other side in the first direction x. In the second conductive portion 20B, the plurality of second elements 40B are joined to the surface thereof in a state of being electrically connected to the second conductive portion 20B. The material of the conductive member 20 is the same as the material of the conductive member 20 of the semiconductor device B10.
　一対の絶縁基板２２は、図２５、図２６、図３１および図３２に示すように、その一方が第１導電部２０Ａの表面に接合され、その他方が第２導電部２０Ｂの表面に接合されている。一対の絶縁基板２２は、第２方向ｙに延びる帯状である。第１導電部２０Ａの表面に接合された絶縁基板２２は、複数の第１素子４０Ａに対して第１方向ｘの他方側に位置する。第２導電部２０Ｂの表面に接合された絶縁基板２２は、複数の第２素子４０Ｂに対して第１方向ｘの一方側に位置する。一対の絶縁基板２２は、たとえばガラスエポキシ樹脂を含む材料からなる。 As shown in FIG. 25, FIG. 26, FIG. 31, and FIG. 32, the pair of insulating substrates 22 is bonded to the surface of the first conductive portion 20A and the other is bonded to the surface of the second conductive portion 20B. ing. The pair of insulating substrates 22 has a strip shape extending in the second direction y. The insulating substrate 22 bonded to the surface of the first conductive portion 20A is located on the other side in the first direction x with respect to the plurality of first elements 40A. The insulating substrate 22 bonded to the surface of the second conductive portion 20B is located on one side in the first direction x with respect to the plurality of second elements 40B. The pair of insulating substrates 22 is made of a material containing, for example, a glass epoxy resin.
　一対のゲート層２３は、図２５、図２６、図３１および図３２に示すように、その一方が第１導電部２０Ａの表面に接合された絶縁基板２２に配置され、その他方が第２導電部２０Ｂの表面に接合された絶縁基板２２に配置されている。一対のゲート層２３は、第２方向ｙに延びる帯状である。一対のゲート層２３は、導電性を有している。一対のゲート層２３は、たとえば銅からなる。 As shown in FIGS. 25, 26, 31, and 32, the pair of gate layers 23 is disposed on the insulating substrate 22 bonded to the surface of the first conductive portion 20A, and the other is the second conductive layer. It arrange | positions at the insulating substrate 22 joined to the surface of the part 20B. The pair of gate layers 23 has a strip shape extending in the second direction y. The pair of gate layers 23 has conductivity. The pair of gate layers 23 is made of, for example, copper.
　一対の検出層２４は、図２５、図２６、図３１および図３２に示すように、その一方が第１導電部２０Ａの表面に接合された絶縁基板２２に配置され、その他方が第２導電部２０Ｂの表面に接合された絶縁基板２２に配置されている。一対の検出層２４は、第２方向ｙに延びる帯状である。一対の検出層２４は、導電性を有している。一対の検出層２４は、たとえば銅からなる。 As shown in FIGS. 25, 26, 31, and 32, the pair of detection layers 24 is disposed on the insulating substrate 22 bonded to the surface of the first conductive portion 20A, and the other is the second conductive layer. It arrange | positions at the insulating substrate 22 joined to the surface of the part 20B. The pair of detection layers 24 has a strip shape extending in the second direction y. The pair of detection layers 24 have conductivity. The pair of detection layers 24 is made of copper, for example.
　半導体装置Ｂ３０は、図２４～図２７および図３２に示すように、第１端子３１Ａおよび第２端子３１Ｂを備える。第１端子３１Ａおよび第２端子３１Ｂは、第１方向ｘの一方側に位置する。第１端子３１Ａおよび第２端子３１Ｂは、厚さ方向ｚにおいて互いに離間している。第１端子３１Ａおよび第２端子３１Ｂは、金属板である。当該金属板は、たとえば銅または銅合金からなる。 The semiconductor device B30 includes a first terminal 31A and a second terminal 31B, as shown in FIGS. The first terminal 31A and the second terminal 31B are located on one side in the first direction x. The first terminal 31A and the second terminal 31B are separated from each other in the thickness direction z. The first terminal 31A and the second terminal 31B are metal plates. The said metal plate consists of copper or a copper alloy, for example.
　図２６に示すように、第１端子３１Ａは、パッド部３１１および端子部３１２を有する。第１端子３１Ａにおいて、パッド部３１１と端子部３１２との境界は、第２方向ｙおよび厚さ方向ｚに沿った面であって、かつ第１方向ｘの一方側に位置する封止樹脂６０の第１側面６３１を含む面である。パッド部３１１は、その全てが封止樹脂６０に覆われている。パッド部３１１の第１方向ｘの他方側は、櫛歯状となっている。この櫛歯状の部分が、第１導電部２０Ａに導通する状態でその表面に接合されている。当該接合は、はんだ接合、または超音波接合などにより行われる。これにより、第１端子３１Ａは、第１導電部２０Ａに導通している。図２７に示すように、端子部３１２は、第１側面６３１から第１方向ｘに延びている。厚さ方向ｚに沿って視て、端子部３１２は矩形状である。半導体装置Ｂ３０が示す例においては、端子部３１２の第２方向ｙにおける両側が封止樹脂６０に覆われている。それ以外の端子部３１２の部分は、第１側面６３１から露出している。これにより、第１端子３１Ａは、封止樹脂６０に支持されている。また、第１方向ｘの一方側に位置する基材１０は、第１導電部２０Ａを介して第１端子３１Ａに支持されている。 As shown in FIG. 26, the first terminal 31A includes a pad portion 311 and a terminal portion 312. In the first terminal 31A, the boundary between the pad portion 311 and the terminal portion 312 is a surface along the second direction y and the thickness direction z, and the sealing resin 60 located on one side in the first direction x. This is a surface including the first side surface 631. The pad portion 311 is entirely covered with the sealing resin 60. The other side of the pad portion 311 in the first direction x has a comb shape. This comb-like portion is joined to the surface thereof in a state of being electrically connected to the first conductive portion 20A. The joining is performed by solder joining or ultrasonic joining. Thereby, the first terminal 31A is electrically connected to the first conductive portion 20A. As shown in FIG. 27, the terminal portion 312 extends from the first side surface 631 in the first direction x. As viewed along the thickness direction z, the terminal portion 312 has a rectangular shape. In the example shown by the semiconductor device B <b> 30, both sides of the terminal portion 312 in the second direction y are covered with the sealing resin 60. Other portions of the terminal portion 312 are exposed from the first side surface 631. Thereby, the first terminal 31 </ b> A is supported by the sealing resin 60. Further, the base material 10 positioned on one side in the first direction x is supported by the first terminal 31A via the first conductive portion 20A.
　図２５に示すように、第２端子３１Ｂは、パッド部３１１および端子部３１２を有する。第２端子３１Ｂにおいて、パッド部３１１と端子部３１２との境界は、第１端子３１Ａにおけるこれらの境界と一致している。パッド部３１１は、連結部３１１Ａおよび複数の延出部３１１Ｂを有する。連結部３１１Ａは、第２方向ｙに延びる帯状である。連結部３１１Ａは、端子部３１２につながっている。複数の延出部３１１Ｂは、連結部３１１Ａから第１方向ｘの他方側に向けて延びている。複数の延出部３１１Ｂは、第２方向ｙにおいて互いに離間している。図３２に示すように、複数の延出部３１１Ｂは、厚さ方向ｚに屈曲している。複数の延出部３１１Ｂの表面には、たとえば銀めっきを施してもよい。図２４に示すように、端子部３１２は、第１側面６３１から第１方向ｘに延びる帯状である。厚さ方向ｚに沿って視て、端子部３１２は矩形状である。半導体装置Ｂ３０が示す例においては、端子部３１２の第２方向ｙにおける両側が封止樹脂６０に覆われている。それ以外の端子部３１２の部分は、第１側面６３１から露出している。図２５、図２６および図３２に示すように、厚さ方向ｚに沿って視て、端子部３１２の少なくとも一部が、第１端子３１Ａの端子部３１２に重なっている。なお、半導体装置Ｂ３０が示す例においては、端子部３１２の形状は第１端子３１Ａの形状と同一であり、かつ厚さ方向ｚに沿って視て、端子部３１２の全部が第１端子３１Ａの端子部３１２に重なっている。 As shown in FIG. 25, the second terminal 31B has a pad portion 311 and a terminal portion 312. In the second terminal 31B, the boundary between the pad portion 311 and the terminal portion 312 coincides with these boundaries in the first terminal 31A. The pad portion 311 has a connecting portion 311A and a plurality of extending portions 311B. The connecting portion 311A has a strip shape extending in the second direction y. The connecting portion 311A is connected to the terminal portion 312. The plurality of extending portions 311B extend from the connecting portion 311A toward the other side in the first direction x. The plurality of extending portions 311B are separated from each other in the second direction y. As shown in FIG. 32, the plurality of extending portions 311B are bent in the thickness direction z. For example, silver plating may be applied to the surfaces of the plurality of extending portions 311B. As shown in FIG. 24, the terminal portion 312 has a strip shape extending from the first side surface 631 in the first direction x. As viewed along the thickness direction z, the terminal portion 312 has a rectangular shape. In the example shown by the semiconductor device B <b> 30, both sides of the terminal portion 312 in the second direction y are covered with the sealing resin 60. Other portions of the terminal portion 312 are exposed from the first side surface 631. As shown in FIGS. 25, 26, and 32, at least a part of the terminal portion 312 overlaps the terminal portion 312 of the first terminal 31 </ b> A as viewed along the thickness direction z. In the example shown by the semiconductor device B30, the shape of the terminal portion 312 is the same as the shape of the first terminal 31A, and when viewed along the thickness direction z, the entire terminal portion 312 is the first terminal 31A. It overlaps with the terminal portion 312.
　絶縁部材３９は、図２４～図２８および図３２に示すように、厚さ方向ｚにおいて第１端子３１Ａと第２端子３１Ｂとの間に介在している。絶縁部材３９は平板である。絶縁部材３９は、たとえば絶縁紙である。厚さ方向ｚに沿って視て、第１端子３１Ａの全部が絶縁部材３９に重なっている。第２端子３１Ｂにおいては、厚さ方向ｚに沿って視て、パッド部３１１の一部と、端子部３１２の全部とが絶縁部材３９に重なっている。厚さ方向ｚに沿って視て絶縁部材３９に重なるこれらの部分は、絶縁部材３９に接している。絶縁部材３９により、第１端子３１Ａおよび第２端子３１Ｂが互いに絶縁されている。絶縁部材３９の一部は、封止樹脂６０に覆われている。 As shown in FIGS. 24 to 28 and 32, the insulating member 39 is interposed between the first terminal 31A and the second terminal 31B in the thickness direction z. The insulating member 39 is a flat plate. The insulating member 39 is, for example, insulating paper. As viewed along the thickness direction z, the entire first terminal 31 </ b> A overlaps the insulating member 39. In the second terminal 31 </ b> B, a part of the pad portion 311 and the entire terminal portion 312 overlap the insulating member 39 when viewed along the thickness direction z. These portions that overlap the insulating member 39 when viewed along the thickness direction z are in contact with the insulating member 39. The first terminal 31A and the second terminal 31B are insulated from each other by the insulating member 39. A part of the insulating member 39 is covered with the sealing resin 60.
　半導体装置Ｂ３０は、図２４～図２７および図３２に示すように、出力端子３２を備える。出力端子３２は、第１方向ｘの他方側に位置する。出力端子３２は、金属板である。当該金属板は、たとえば銅または銅合金からなる。出力端子３２は、パッド部３２１および端子部３２２を有する。パッド部３２１と端子部３２２との境界は、第２方向ｙおよび厚さ方向ｚに沿った面であって、かつ第１方向ｘの他方側に位置する封止樹脂６０の第１側面６３１を含む面である。パッド部３２１は、その全てが封止樹脂６０に覆われている。パッド部３２１の第１方向ｘの一方側は、櫛歯状となっている。この櫛歯状の部分が、第２導電部２０Ｂに導通する状態でその表面に接合されている。当該接合は、はんだ接合、または超音波接合などにより行われる。これにより、出力端子３２は、第２導電部２０Ｂに導通している。図２４に示すように、端子部３２２は、第１側面６３１から第１方向ｘに延びている。厚さ方向ｚに沿って視て、端子部３２２は矩形状である。半導体装置Ｂ３０が示す例においては、端子部３２２の第２方向ｙにおける両側が封止樹脂６０に覆われている。それ以外の端子部３２２の部分は、第１側面６３１から露出している。これにより、出力端子３２は、封止樹脂６０に支持されている。また、第１方向ｘの他方側に位置する基材１０は、第２導電部２０Ｂを介して出力端子３２に支持されている。 The semiconductor device B30 includes an output terminal 32 as shown in FIGS. 24 to 27 and FIG. The output terminal 32 is located on the other side in the first direction x. The output terminal 32 is a metal plate. The said metal plate consists of copper or a copper alloy, for example. The output terminal 32 has a pad portion 321 and a terminal portion 322. The boundary between the pad portion 321 and the terminal portion 322 is a surface along the second direction y and the thickness direction z and the first side surface 631 of the sealing resin 60 located on the other side in the first direction x. It is a surface to include. The pad portion 321 is entirely covered with the sealing resin 60. One side of the pad portion 321 in the first direction x has a comb shape. The comb-like portion is joined to the surface thereof in a state of conducting to the second conductive portion 20B. The joining is performed by solder joining or ultrasonic joining. Thereby, the output terminal 32 is electrically connected to the second conductive portion 20B. As shown in FIG. 24, the terminal portion 322 extends from the first side surface 631 in the first direction x. Viewed along the thickness direction z, the terminal portion 322 has a rectangular shape. In the example shown by the semiconductor device B30, both sides of the terminal portion 322 in the second direction y are covered with the sealing resin 60. Other portions of the terminal portion 322 are exposed from the first side surface 631. Thereby, the output terminal 32 is supported by the sealing resin 60. The base material 10 positioned on the other side in the first direction x is supported by the output terminal 32 via the second conductive portion 20B.
　半導体装置Ｂ３０は、図２４～図２７に示すように、一対のゲート端子３３および一対の検出端子３４を備える。半導体装置Ｂ３０においては、一対のゲート端子３３および一対の検出端子３４は、複数のダミー端子３５とともに、同一のリードフレームから構成される。当該リードフレームは、銅または銅合金からなる。 The semiconductor device B30 includes a pair of gate terminals 33 and a pair of detection terminals 34, as shown in FIGS. In the semiconductor device B30, the pair of gate terminals 33 and the pair of detection terminals 34 are configured from the same lead frame together with the plurality of dummy terminals 35. The lead frame is made of copper or a copper alloy.
　図２５、図２６および図３４に示すように、一対のゲート端子３３は、第２方向ｙにおいて一対の基材１０の隣に位置する。一方のゲート端子３３は、第１方向ｘの一方側に位置する基材１０の隣に位置する。他方のゲート端子３３は、第１方向ｘの他方側に位置する基材１０の隣に位置する。一対のゲート端子３３の各々は、パッド部３３１および端子部３３２を有する。パッド部３３１は、封止樹脂６０に覆われている。これにより、一対のゲート端子３３は、封止樹脂６０に支持されている。なお、パッド部３３１の表面には、たとえば銀めっきを施してもよい。端子部３３２は、パッド部３３１につながり、かつ封止樹脂６０の第２側面６３２から露出している（図３０参照）。第１方向ｘに沿って視て、端子部３３２はＬ字状をなしている。 25, FIG. 26, and FIG. 34, the pair of gate terminals 33 is located next to the pair of base materials 10 in the second direction y. One gate terminal 33 is located next to the substrate 10 located on one side in the first direction x. The other gate terminal 33 is located next to the base material 10 located on the other side in the first direction x. Each of the pair of gate terminals 33 includes a pad portion 331 and a terminal portion 332. The pad portion 331 is covered with the sealing resin 60. Thereby, the pair of gate terminals 33 are supported by the sealing resin 60. Note that the surface of the pad portion 331 may be subjected to, for example, silver plating. The terminal portion 332 is connected to the pad portion 331 and exposed from the second side surface 632 of the sealing resin 60 (see FIG. 30). When viewed along the first direction x, the terminal portion 332 has an L shape.
　図２５、図２６および図３４に示すように、一対の検出端子３４は、第１方向ｘにおいて一対のゲート端子３３の隣に位置する。一対の検出端子３４の各々は、パッド部３４１および端子部３４２を有する。パッド部３４１は、封止樹脂６０に覆われている。これにより、一対の検出端子３４は、封止樹脂６０に支持されている。なお、パッド部３４１の表面には、たとえば銀めっきを施してもよい。端子部３４２は、パッド部３４１につながり、かつ封止樹脂６０の第２側面６３２から露出している（図３０参照）。第１方向ｘに沿って視て、端子部３４２はＬ字状をなしている。 25, 26 and 34, the pair of detection terminals 34 are located next to the pair of gate terminals 33 in the first direction x. Each of the pair of detection terminals 34 includes a pad portion 341 and a terminal portion 342. The pad portion 341 is covered with the sealing resin 60. Thereby, the pair of detection terminals 34 are supported by the sealing resin 60. The surface of the pad portion 341 may be subjected to silver plating, for example. The terminal portion 342 is connected to the pad portion 341 and exposed from the second side surface 632 of the sealing resin 60 (see FIG. 30). When viewed along the first direction x, the terminal portion 342 has an L shape.
　複数のダミー端子３５は、図２５、図２６および図３４に示すように、第１方向ｘにおいて一対の検出端子３４に対して一対のゲート端子３３とは反対側に位置する。半導体装置Ｂ３０が示す例においては、ダミー端子３５の数は６つである。このうち３つのダミー端子３５は、第１方向ｘの一方側に位置する。残り３つのダミー端子３５は、第１方向ｘの他方側に位置する。なお、複数のダミー端子３５の数はこれに限定されない。さらに、半導体装置Ｂ３０において、複数のダミー端子３５を備えない構成としてもよい。複数のダミー端子３５の各々は、パッド部３５１および端子部３５２を有する。パッド部３５１は、封止樹脂６０に覆われている。これにより、複数のダミー端子３５は、封止樹脂６０に支持されている。なお、パッド部３５１の表面には、たとえば銀めっきを施してもよい。端子部３５２は、パッド部３５１につながり、かつ封止樹脂６０の第２側面６３２から露出している（図３０参照）。図２８および図２９に示すように、第１方向ｘに沿って視て、端子部３５２はＬ字状をなしている。なお、一対のゲート端子３３の端子部３３２、および一対の検出端子３４の端子部３４２のそれぞれの形状は、端子部３５２の形状と同一である。 The plurality of dummy terminals 35 are positioned on the opposite side of the pair of gate terminals 33 with respect to the pair of detection terminals 34 in the first direction x, as shown in FIGS. 25, 26 and 34. In the example shown by the semiconductor device B30, the number of dummy terminals 35 is six. Of these, the three dummy terminals 35 are located on one side in the first direction x. The remaining three dummy terminals 35 are located on the other side in the first direction x. The number of the dummy terminals 35 is not limited to this. Further, the semiconductor device B30 may be configured not to include a plurality of dummy terminals 35. Each of the plurality of dummy terminals 35 has a pad portion 351 and a terminal portion 352. The pad portion 351 is covered with the sealing resin 60. Accordingly, the plurality of dummy terminals 35 are supported by the sealing resin 60. Note that the surface of the pad portion 351 may be subjected to silver plating, for example. The terminal portion 352 is connected to the pad portion 351 and exposed from the second side surface 632 of the sealing resin 60 (see FIG. 30). As shown in FIGS. 28 and 29, the terminal portion 352 is L-shaped when viewed along the first direction x. Note that the shapes of the terminal portions 332 of the pair of gate terminals 33 and the terminal portions 342 of the pair of detection terminals 34 are the same as the shapes of the terminal portions 352.
　複数の半導体素子４０は、図２５および図２６に示すように、厚さ方向ｚに沿って視て、第２方向ｙに対して千鳥配置となるように導電部材２０に導通する状態で接合されている。 As shown in FIGS. 25 and 26, the plurality of semiconductor elements 40 are joined in a state of conducting to the conductive member 20 so as to be staggered with respect to the second direction y when viewed along the thickness direction z. ing.
　図３４に基づき、第１導電部２０Ａに導通する状態で接合された複数の第１素子４０Ａの各々について説明する。第１電極４１に接続された複数の第１ワイヤ５０１は、第２導電部２０Ｂの表面に接続されている。これにより、複数の第１素子４０Ａは、第２導電部２０Ｂに導通している。複数の第１ワイヤ５０１は、第１方向ｘに延びている。ゲート電極４３に接続されたゲートワイヤ５０３は、第１導電部２０Ａに接合された絶縁基板２２に配置されたゲート層２３に接続されている。第１電極４１のいずれかの領域に接続された検出ワイヤ５０４は、第１導電部２０Ａに接合された絶縁基板２２に配置された検出層２４に接続されている。 34, each of the plurality of first elements 40A joined in a state of conducting to the first conductive portion 20A will be described. The plurality of first wires 501 connected to the first electrode 41 are connected to the surface of the second conductive portion 20B. Thereby, the plurality of first elements 40A are electrically connected to the second conductive portion 20B. The multiple first wires 501 extend in the first direction x. The gate wire 503 connected to the gate electrode 43 is connected to the gate layer 23 disposed on the insulating substrate 22 bonded to the first conductive portion 20A. The detection wire 504 connected to any region of the first electrode 41 is connected to the detection layer 24 disposed on the insulating substrate 22 bonded to the first conductive portion 20A.
　図３４に基づき、第２導電部２０Ｂに導通する状態で接合された複数の第２素子４０Ｂの各々について説明する。第１電極４１に接続された複数の第２ワイヤ５０２は、第２端子３１Ｂのパッド部３１１の延出部３１１Ｂに接続されている。これにより、複数の第２素子４０Ｂは、第２端子３１Ｂに導通している。複数の第２ワイヤ５０２は、第１方向ｘに延びている。ゲート電極４３に接続されたゲートワイヤ５０３は、第２導電部２０Ｂに接合された絶縁基板２２に配置されたゲート層２３に接続されている。第１電極４１のいずれかの領域に接続された検出ワイヤ５０４は、第２導電部２０Ｂに接合された絶縁基板２２に配置された検出層２４に接続されている。 34, each of the plurality of second elements 40B joined in a state of conducting to the second conductive portion 20B will be described. The plurality of second wires 502 connected to the first electrode 41 are connected to the extending portion 311B of the pad portion 311 of the second terminal 31B. Thereby, the plurality of second elements 40B are electrically connected to the second terminal 31B. The plurality of second wires 502 extend in the first direction x. The gate wire 503 connected to the gate electrode 43 is connected to the gate layer 23 disposed on the insulating substrate 22 bonded to the second conductive portion 20B. The detection wire 504 connected to any region of the first electrode 41 is connected to the detection layer 24 disposed on the insulating substrate 22 bonded to the second conductive portion 20B.
　一対の第３接続ワイヤ５３は、図２５および図３４に示すように、一対のゲート層２３と一対のゲート端子３３とに接続されている。一対のゲート端子３３においては、一対の第３接続ワイヤ５３は、一対のパッド部３３１の表面に接続されている。一対の第３接続ワイヤ５３は、たとえばアルミニウムからなる。これにより、第１方向ｘの一方側に位置するゲート端子３３は、複数の第１素子４０Ａのゲート電極４３に導通している。第１方向ｘの他方側に位置するゲート端子３３は、複数の第２素子４０Ｂのゲート電極４３に導通している。一対の第３接続ワイヤ５３は、封止樹脂６０に覆われている。 The pair of third connection wires 53 are connected to the pair of gate layers 23 and the pair of gate terminals 33 as shown in FIGS. In the pair of gate terminals 33, the pair of third connection wires 53 are connected to the surfaces of the pair of pad portions 331. The pair of third connection wires 53 is made of, for example, aluminum. Thereby, the gate terminal 33 located on one side in the first direction x is electrically connected to the gate electrodes 43 of the plurality of first elements 40A. The gate terminal 33 located on the other side in the first direction x is electrically connected to the gate electrodes 43 of the plurality of second elements 40B. The pair of third connection wires 53 are covered with the sealing resin 60.
　一対の第４接続ワイヤ５４は、図２５および図３４に示すように、一対の検出層２４と一対の検出端子３４とに接続されている。一対の検出端子３４においては、一対の第４接続ワイヤ５４は、一対のパッド部３４１の表面に接続されている。一対の第４接続ワイヤ５４は、たとえばアルミニウムからなる。これにより、第１方向ｘの一方側に位置する検出端子３４は、複数の第１素子４０Ａの第１電極４１に導通している。第１方向ｘの他方側に位置する検出端子３４は、複数の第２素子４０Ｂの第１電極４１に導通している。一対の第４接続ワイヤ５４は、封止樹脂６０に覆われている。 The pair of fourth connection wires 54 are connected to the pair of detection layers 24 and the pair of detection terminals 34 as shown in FIGS. 25 and 34. In the pair of detection terminals 34, the pair of fourth connection wires 54 are connected to the surfaces of the pair of pad portions 341. The pair of fourth connection wires 54 is made of, for example, aluminum. Thereby, the detection terminal 34 located on one side in the first direction x is electrically connected to the first electrodes 41 of the plurality of first elements 40A. The detection terminal 34 located on the other side in the first direction x is electrically connected to the first electrodes 41 of the plurality of second elements 40B. The pair of fourth connection wires 54 are covered with the sealing resin 60.
　封止樹脂６０は、図２４～図２７に示すように、頂面６１、底面６２、一対の第１側面６３１、一対の第２側面６３２、複数の第３側面６３３、複数の第４側面６３４、および複数の貫通孔６４を有する。なお、これらのうち、頂面６１、底面６２および一対の第２側面６３２の構成は、先述した半導体装置Ｂ１０における構成と同様であるため、ここでの説明は省略する。 24 to 27, the sealing resin 60 includes a top surface 61, a bottom surface 62, a pair of first side surfaces 631, a pair of second side surfaces 632, a plurality of third side surfaces 633, and a plurality of fourth side surfaces 634. And a plurality of through holes 64. Note that, among these, the configurations of the top surface 61, the bottom surface 62, and the pair of second side surfaces 632 are the same as those in the semiconductor device B10 described above, and thus the description thereof is omitted here.
　図２４～図２９に示すように、一対の第１側面６３１は、頂面６１および底面６２の双方につながり、かつ第１方向ｘを向く。第１側面６３１の第１方向ｘの一方側からは、第１端子３１Ａの端子部３１２と、第２端子３１Ｂの端子部３１２と、絶縁部材３９とが露出している。第２側面６３２の第１方向ｘの他方側からは、出力端子３２の端子部３２２が露出している。 24 to 29, the pair of first side surfaces 631 are connected to both the top surface 61 and the bottom surface 62 and face the first direction x. From one side of the first side surface 631 in the first direction x, the terminal portion 312 of the first terminal 31A, the terminal portion 312 of the second terminal 31B, and the insulating member 39 are exposed. The terminal portion 322 of the output terminal 32 is exposed from the other side of the second side surface 632 in the first direction x.
　図２４～図２９に示すように、複数の第３側面６３３は、頂面６１および底面６２の双方につながり、かつ第２方向ｙを向く。複数の第３側面６３３は、第１方向ｘの一方側に位置する一対の第３側面６３３と、第１方向ｘの他方側に位置する一対の第３側面６３３とを含む。第１方向ｘの一方側および他方側の各々において、一対の第３側面６３３は、第２方向ｙにおいて対向している。また、第１方向ｘの一方側および他方側の各々において、一対の第３側面６３３は、第１側面６３１の第２方向ｙにおける両側につながっている。 24 to 29, the plurality of third side surfaces 633 are connected to both the top surface 61 and the bottom surface 62 and face the second direction y. The multiple third side surfaces 633 include a pair of third side surfaces 633 located on one side in the first direction x and a pair of third side surfaces 633 located on the other side in the first direction x. On each of one side and the other side in the first direction x, the pair of third side surfaces 633 are opposed to each other in the second direction y. In each of the one side and the other side in the first direction x, the pair of third side surfaces 633 are connected to both sides of the first side surface 631 in the second direction y.
　図２４～図３０に示すように、複数の第４側面６３４は、頂面６１および底面６２の双方につながり、かつ第１方向ｘを向く。複数の第４側面６３４は、第１方向ｘにおいて一対の第１側面６３１よりも半導体装置Ｂ３０の外側に位置する。複数の第４側面６３４は、第１方向ｘの一方側に位置する一対の第４側面６３４と、第１方向ｘの他方側に位置する一対の第４側面６３４とを含む。第１方向ｘの一方側および他方側の各々において、一対の第４側面６３４の第２方向ｙにおける両側は、一対の第２側面６３２と一対の第３側面６３３とにつながっている。 As shown in FIGS. 24 to 30, the plurality of fourth side surfaces 634 are connected to both the top surface 61 and the bottom surface 62 and face the first direction x. The plurality of fourth side surfaces 634 are located outside the semiconductor device B30 with respect to the pair of first side surfaces 631 in the first direction x. The plurality of fourth side surfaces 634 includes a pair of fourth side surfaces 634 located on one side in the first direction x and a pair of fourth side surfaces 634 located on the other side in the first direction x. In each of one side and the other side of the first direction x, both sides of the pair of fourth side surfaces 634 in the second direction y are connected to the pair of second side surfaces 632 and the pair of third side surfaces 633.
　図２４および図２７に示すように、複数の貫通孔６４は、厚さ方向ｚに沿って視て封止樹脂６０の四隅に位置する。なお、図３１に示すように、複数の貫通孔６４の各々の構成は、半導体装置Ｂ１０の貫通孔６４の構成と同様である。 24 and 27, the plurality of through holes 64 are positioned at the four corners of the sealing resin 60 as viewed along the thickness direction z. As shown in FIG. 31, the configuration of each of the plurality of through holes 64 is the same as the configuration of the through hole 64 of the semiconductor device B10.
　＜半導体モジュールＡ３０＞
　以下、半導体モジュールＡ３０について説明する。 <Semiconductor module A30>
Hereinafter, the semiconductor module A30 will be described.
　図３５および図３６に示すように、ヒートシンク７０は、上面７１および複数の締結部材７２を有する。上面７１は、厚さ方向ｚの半導体装置Ｂ３０が位置する側を向く。複数の締結部材７２の各々は、ボルト７２１およびナット７２２により構成される。複数のボルト７２１は、上面７１から厚さ方向ｚに向けて延びている。複数のボルト７２１の配置位置および直径は、半導体装置Ｂ３０の封止樹脂６０に設けられた複数の貫通孔６４に対応している。これにより、複数のボルト７２１の各々は、複数の貫通孔６４のいずれかに挿入される構成となる。複数のボルト７２１の各々の先端には、ねじ切りがなされている。これにより、ナット７２２がボルト７２１に噛み合わされる。 35 and 36, the heat sink 70 has an upper surface 71 and a plurality of fastening members 72. The upper surface 71 faces the side where the semiconductor device B30 in the thickness direction z is located. Each of the plurality of fastening members 72 includes a bolt 721 and a nut 722. The plurality of bolts 721 extend from the upper surface 71 in the thickness direction z. The arrangement positions and diameters of the plurality of bolts 721 correspond to the plurality of through holes 64 provided in the sealing resin 60 of the semiconductor device B30. Thereby, each of the plurality of bolts 721 is configured to be inserted into one of the plurality of through holes 64. A thread is cut at the tip of each of the plurality of bolts 721. As a result, the nut 722 is engaged with the bolt 721.
　接合シート８０は、図３６に示すように、ヒートシンク７０の上面７１と、半導体装置Ｂ３０の一対の基材１０の第１裏面１２Ａとの間に介在している。半導体装置Ｂ３０においては、一対の第１裏面１２Ａ、および封止樹脂６０の底面６２の双方が接合シート８０に圧着されている。図３７に示すように、一対の第１裏面１２Ａにおいて形成された表面処理領域１９は、接合シート８０に一様に接している。このため、表面処理領域１９は、接合シート８０に噛み合った状態となっている。 36, the joining sheet 80 is interposed between the upper surface 71 of the heat sink 70 and the first back surface 12A of the pair of base materials 10 of the semiconductor device B30. In the semiconductor device B <b> 30, both the pair of first back surfaces 12 </ b> A and the bottom surface 62 of the sealing resin 60 are pressure bonded to the bonding sheet 80. As shown in FIG. 37, the surface treatment region 19 formed on the pair of first back surfaces 12A is in contact with the bonding sheet 80 uniformly. For this reason, the surface treatment region 19 is in a state of being engaged with the bonding sheet 80.
　次に、半導体モジュールＡ３０の作用効果について説明する。 Next, functions and effects of the semiconductor module A30 will be described.
　半導体モジュールＡ３０では、封止樹脂６０、および封止樹脂６０から露出する第１裏面１２Ａを有する一対の基材１０を備える半導体装置Ｂ３０と、ヒートシンク７０と、接合シート８０とを備える。接合シート８０は、電気絶縁性および可とう性を有し、かつヒートシンク７０と一対の第１裏面１２Ａとの間に介在している。接合シート８０の熱伝導率は、封止樹脂６０の熱伝導率よりも大である。したがって、半導体モジュールＡ３０のよっても、半導体装置Ｂ３０の放熱性をより向上させることができる。 The semiconductor module A30 includes a semiconductor device B30 including a sealing resin 60 and a pair of base materials 10 having a first back surface 12A exposed from the sealing resin 60, a heat sink 70, and a bonding sheet 80. The bonding sheet 80 has electrical insulation and flexibility, and is interposed between the heat sink 70 and the pair of first back surfaces 12A. The thermal conductivity of the bonding sheet 80 is larger than the thermal conductivity of the sealing resin 60. Therefore, even with the semiconductor module A30, the heat dissipation of the semiconductor device B30 can be further improved.
　半導体装置Ｂ３０においては、第１端子３１Ａおよび第２端子３１Ｂは、厚さ方向ｚにおいて互いに離間している。厚さ方向ｚに沿って視て、第２端子３１Ｂの端子部３１２の少なくとも一部が、第１端子３１Ａの端子部３１２に重なっている。これにより、半導体装置Ｂ３０の使用において、第１端子３１Ａおよび第２端子３１Ｂのそれぞれにおいて発生する磁界が互いに干渉することにより、第１端子３１Ａおよび第２端子３１Ｂのそれぞれのインダクタンスが低減する。したがって、第１端子３１Ａおよび第２端子３１Ｂに印加されるサージ電圧などが低減されるため、半導体装置Ｂ３０の電力損失を抑制することができる。 In the semiconductor device B30, the first terminal 31A and the second terminal 31B are separated from each other in the thickness direction z. As viewed along the thickness direction z, at least a part of the terminal portion 312 of the second terminal 31B overlaps the terminal portion 312 of the first terminal 31A. Thereby, in the use of the semiconductor device B30, the magnetic fields generated in the first terminal 31A and the second terminal 31B interfere with each other, thereby reducing the inductance of the first terminal 31A and the second terminal 31B. Therefore, since the surge voltage applied to the first terminal 31A and the second terminal 31B is reduced, the power loss of the semiconductor device B30 can be suppressed.
　本開示は、先述した実施形態に限定されるものではない。本開示の各部の具体的な構成は、種々に設計変更自在である。 The present disclosure is not limited to the above-described embodiment. The specific configuration of each part of the present disclosure can be modified in various ways.
　本開示における種々の実施形態は、以下の付記として規定しうる。 Various embodiments in the present disclosure may be defined as the following supplementary notes.
　付記１．厚さ方向において互いに反対側を向く第１主面および第１裏面を有する基材と、前記第１主面に配置された導電部材と、前記導電部材に導通する状態で接合された複数の半導体素子と、前記第１裏面が露出されるように前記複数の半導体素子を覆う封止樹脂と、を備える半導体装置と、
　ヒートシンクと、
　前記ヒートシンクと前記第１裏面との間に介在する接合シートと、を構成要素に含み、
　前記接合シートは、電気絶縁性および可とう性を有し、
　前記接合シートの熱伝導率が、前記封止樹脂の熱伝導率よりも大である、半導体モジュール。 Appendix 1. A base material having a first main surface and a first back surface facing each other in the thickness direction, a conductive member disposed on the first main surface, and a plurality of semiconductors joined in a conductive state to the conductive member A semiconductor device comprising: an element; and a sealing resin that covers the plurality of semiconductor elements such that the first back surface is exposed;
A heat sink,
A joining sheet interposed between the heat sink and the first back surface,
The joining sheet has electrical insulation and flexibility,
The semiconductor module whose thermal conductivity of the said joining sheet is larger than the thermal conductivity of the said sealing resin.
　付記２．前記第１裏面は、前記接合シートに圧着されている、付記１に記載の半導体モジュール。 Appendix 2. The semiconductor module according to appendix 1, wherein the first back surface is pressure-bonded to the bonding sheet.
　付記３．前記第１裏面において、前記接合シートに接する部分には、粗面を含む表面処理領域が形成されている、付記２に記載の半導体モジュール。 Appendix 3. The semiconductor module according to appendix 2, wherein a surface treatment region including a rough surface is formed in a portion in contact with the bonding sheet on the first back surface.
　付記４．前記基材は、電気絶縁性を有する、付記３に記載の半導体モジュール。 Appendix 4. The semiconductor module according to appendix 3, wherein the base material has electrical insulation.
　付記５．前記基材は、セラミックスを含む材料からなる、付記４に記載の半導体モジュール。 Appendix 5. The semiconductor module according to appendix 4, wherein the base material is made of a material containing ceramics.
　付記６．前記基材は、電気絶縁性を有する第１基材と、導電性を有する第２基材と、を含み、
　前記第１基材は、前記第１主面、および前記第１主面とは反対側を向く第２裏面を含み、
　前記第２基材は、前記第１裏面、および前記第１裏面とは反対側を向く第２主面を含み、
　前記第２主面が前記第２裏面に接合されている、付記３に記載の半導体モジュール。 Appendix 6. The base material includes a first base material having electrical insulation and a second base material having conductivity,
The first base material includes the first main surface and a second back surface facing the opposite side to the first main surface,
The second base material includes the first back surface, and a second main surface facing the side opposite to the first back surface,
The semiconductor module according to appendix 3, wherein the second main surface is bonded to the second back surface.
　付記７．前記第２基材は、銅を含む材料からなる、付記６に記載の半導体モジュール。 Appendix 7 The semiconductor module according to appendix 6, wherein the second base material is made of a material containing copper.
　付記８．前記接合シートの熱伝導率は、１０Ｗ／（ｍ・Ｋ）以上２５Ｗ／（ｍ・Ｋ）以下である、付記２ないし７のいずれかに記載の半導体モジュール。 Appendix 8 The semiconductor module according to any one of appendices 2 to 7, wherein the bonding sheet has a thermal conductivity of 10 W / (m · K) to 25 W / (m · K).
　付記９．前記接合シートには、窒化ホウ素を含むフィラーが含有されている、付記８に記載の半導体モジュール。 Appendix 9 The semiconductor module according to appendix 8, wherein the bonding sheet contains a filler containing boron nitride.
　付記１０．前記接合シートの厚さは、０．２ｍｍ以上０．６ｍｍ以下である、付記９に記載の半導体モジュール。 Appendix 10. The semiconductor module according to appendix 9, wherein the bonding sheet has a thickness of 0.2 mm to 0.6 mm.
　付記１１．前記封止樹脂は、前記厚さ方向を向き、かつ前記第１裏面が露出する底面と、前記底面につながり、かつ前記厚さ方向に対して直交する第１方向を向く一対の側面と、を有し、
　前記底面の少なくとも一部が、前記接合シートに圧着されている、付記８ないし１０のいずれかに記載の半導体モジュール。 Appendix 11. The sealing resin has a bottom surface that faces the thickness direction and the first back surface is exposed, and a pair of side surfaces that are connected to the bottom surface and face a first direction orthogonal to the thickness direction. Have
The semiconductor module according to any one of appendices 8 to 10, wherein at least a part of the bottom surface is pressure-bonded to the joining sheet.
　付記１２．前記底面は、前記第１裏面を囲む枠状である、付記１１に記載の半導体モジュール。 Appendix 12. The semiconductor module according to appendix 11, wherein the bottom surface has a frame shape surrounding the first back surface.
　付記１３．前記複数の半導体素子は、第１素子および第２素子を含み、
　前記導電部材は、前記第１素子が導通する状態で接合された第１導電部と、前記第２素子が導通する状態で接合された第２導電部と、を含み、
　前記半導体装置は、前記第１導電部に導通する第１端子と、前記第２素子に導通する第２端子と、前記第２導電部に導通する出力端子と、をさらに備える、付記１１または１２に記載の半導体モジュール。 Appendix 13. The plurality of semiconductor elements include a first element and a second element,
The conductive member includes a first conductive part joined in a state where the first element is conductive, and a second conductive part joined in a state where the second element is conductive,
The semiconductor device further includes: a first terminal that conducts to the first conductive part; a second terminal that conducts to the second element; and an output terminal that conducts to the second conductive part. The semiconductor module described in 1.
　付記１４．前記導電部材は、金属板である、付記１３に記載の半導体モジュール。 Appendix 14. The semiconductor module according to appendix 13, wherein the conductive member is a metal plate.
　付記１５．前記第１端子および前記第２端子は、前記一対の側面のうち一方の面から露出し、
　前記出力端子は、前記一対の側面のうち他方の面から露出している、付記１３または１４に記載の半導体モジュール。 Appendix 15. The first terminal and the second terminal are exposed from one surface of the pair of side surfaces,
The semiconductor module according to appendix 13 or 14, wherein the output terminal is exposed from the other surface of the pair of side surfaces.
　付記１６．前記第１端子および前記第２端子は、前記厚さ方向および前記第１方向の双方に対して直交する第２方向において互いに離間し、
　前記第１端子、前記第２端子および前記出力端子の各々は、前記一対の側面のいずれかの面から露出する端子部を有し、
　前記端子部は、前記一対の側面のいずれかの面から前記第１方向に延びる基部と、前記基部の前記第１方向における先端から、前記厚さ方向のうち前記第１主面が向く側に向けて延びる起立部と、を有する、付記１５に記載の半導体モジュール。 Appendix 16. The first terminal and the second terminal are separated from each other in a second direction orthogonal to both the thickness direction and the first direction;
Each of the first terminal, the second terminal, and the output terminal has a terminal portion exposed from any one of the pair of side surfaces,
The terminal portion includes a base portion extending in the first direction from one of the pair of side surfaces, and a tip of the base portion in the first direction on a side where the first main surface faces in the thickness direction. The semiconductor module according to appendix 15, further comprising an upright portion extending toward the surface.
　付記１７．前記第１端子および前記第２端子は、前記厚さ方向において互いに離間し、
　前記第１端子および前記第２端子の各々は、前記一対の側面のうち一方の面から前記第１方向に延びる端子部を有し、
　前記厚さ方向に沿って視て、前記第２端子の前記端子部の少なくとも一部が、前記第１端子の前記端子部に重なっている、付記１５に記載の半導体モジュール。 Appendix 17. The first terminal and the second terminal are separated from each other in the thickness direction,
Each of the first terminal and the second terminal has a terminal portion extending in the first direction from one surface of the pair of side surfaces,
The semiconductor module according to appendix 15, wherein at least a part of the terminal portion of the second terminal overlaps the terminal portion of the first terminal as viewed along the thickness direction.

Claims (17)

  1. 　厚さ方向において互いに反対側を向く第１主面および第１裏面を有する基材と、前記第１主面に配置された導電部材と、前記導電部材に導通する状態で接合された複数の半導体素子と、前記第１裏面が露出されるように前記複数の半導体素子を覆う封止樹脂と、を備える半導体装置と、
    　ヒートシンクと、
    　前記ヒートシンクと前記第１裏面との間に介在する接合シートと、を構成要素に含み、
    　前記接合シートは、電気絶縁性および可とう性を有し、
    　前記接合シートの熱伝導率が、前記封止樹脂の熱伝導率よりも大である、半導体モジュール。     A base material having a first main surface and a first back surface facing each other in the thickness direction, a conductive member disposed on the first main surface, and a plurality of semiconductors joined in a conductive state to the conductive member A semiconductor device comprising: an element; and a sealing resin that covers the plurality of semiconductor elements such that the first back surface is exposed;
    A heat sink,
    A joining sheet interposed between the heat sink and the first back surface,
    The joining sheet has electrical insulation and flexibility,
    The semiconductor module whose thermal conductivity of the said joining sheet is larger than the thermal conductivity of the said sealing resin.
  2. 　前記第１裏面は、前記接合シートに圧着されている、請求項１に記載の半導体モジュール。 The semiconductor module according to claim 1, wherein the first back surface is pressure-bonded to the joining sheet.
  3. 　前記第１裏面において、前記接合シートに接する部分には、粗面を含む表面処理領域が形成されている、請求項２に記載の半導体モジュール。 3. The semiconductor module according to claim 2, wherein a surface treatment region including a rough surface is formed in a portion in contact with the bonding sheet on the first back surface.
  4. 　前記基材は、電気絶縁性を有する、請求項３に記載の半導体モジュール。 4. The semiconductor module according to claim 3, wherein the base material has electrical insulation.
  5. 　前記基材は、セラミックスを含む材料からなる、請求項４に記載の半導体モジュール。 The semiconductor module according to claim 4, wherein the base material is made of a material containing ceramics.
  6. 　前記基材は、電気絶縁性を有する第１基材と、導電性を有する第２基材と、を含み、
    　前記第１基材は、前記第１主面、および前記第１主面とは反対側を向く第２裏面を含み、
    　前記第２基材は、前記第１裏面、および前記第１裏面とは反対側を向く第２主面を含み、
    　前記第２主面が前記第２裏面に接合されている、請求項３に記載の半導体モジュール。     The base material includes a first base material having electrical insulation and a second base material having conductivity,
    The first base material includes the first main surface and a second back surface facing the opposite side to the first main surface,
    The second base material includes the first back surface, and a second main surface facing the side opposite to the first back surface,
    The semiconductor module according to claim 3, wherein the second main surface is bonded to the second back surface.
  7. 　前記第２基材は、銅を含む材料からなる、請求項６に記載の半導体モジュール。 The semiconductor module according to claim 6, wherein the second base material is made of a material containing copper.
  8. 　前記接合シートの熱伝導率は、１０Ｗ／（ｍ・Ｋ）以上２５Ｗ／（ｍ・Ｋ）以下である、請求項２ないし７のいずれかに記載の半導体モジュール。 The semiconductor module according to any one of claims 2 to 7, wherein the thermal conductivity of the bonding sheet is 10 W / (m · K) or more and 25 W / (m · K) or less.
  9. 　前記接合シートには、窒化ホウ素を含むフィラーが含有されている、請求項８に記載の半導体モジュール。 The semiconductor module according to claim 8, wherein the bonding sheet contains a filler containing boron nitride.
  10. 　前記接合シートの厚さは、０．２ｍｍ以上０．６ｍｍ以下である、請求項９に記載の半導体モジュール。 10. The semiconductor module according to claim 9, wherein the thickness of the bonding sheet is 0.2 mm or greater and 0.6 mm or less.
  11. 　前記封止樹脂は、前記厚さ方向を向き、かつ前記第１裏面が露出する底面と、前記底面につながり、かつ前記厚さ方向に対して直交する第１方向を向く一対の側面と、を有し、
    　前記底面の少なくとも一部が、前記接合シートに圧着されている、請求項８ないし１０のいずれかに記載の半導体モジュール。     The sealing resin has a bottom surface that faces the thickness direction and the first back surface is exposed, and a pair of side surfaces that are connected to the bottom surface and face a first direction orthogonal to the thickness direction. Have
    The semiconductor module according to claim 8, wherein at least a part of the bottom surface is pressure-bonded to the bonding sheet.
  12. 　前記底面は、前記第１裏面を囲む枠状である、請求項１１に記載の半導体モジュール。 12. The semiconductor module according to claim 11, wherein the bottom surface has a frame shape surrounding the first back surface.
  13. 　前記複数の半導体素子は、第１素子および第２素子を含み、
    　前記導電部材は、前記第１素子が導通する状態で接合された第１導電部と、前記第２素子が導通する状態で接合された第２導電部と、を含み、
    　前記半導体装置は、前記第１導電部に導通する第１端子と、前記第２素子に導通する第２端子と、前記第２導電部に導通する出力端子と、をさらに備える、請求項１１または１２に記載の半導体モジュール。     The plurality of semiconductor elements include a first element and a second element,
    The conductive member includes a first conductive part joined in a state where the first element is conductive, and a second conductive part joined in a state where the second element is conductive,
    The semiconductor device further comprises: a first terminal that conducts to the first conductive part; a second terminal that conducts to the second element; and an output terminal that conducts to the second conductive part. 12. The semiconductor module according to 12.
  14. 　前記導電部材は、金属板である、請求項１３に記載の半導体モジュール。 The semiconductor module according to claim 13, wherein the conductive member is a metal plate.
  15. 　前記第１端子および前記第２端子は、前記一対の側面のうち一方の面から露出し、
    　前記出力端子は、前記一対の側面のうち他方の面から露出している、請求項１３または１４に記載の半導体モジュール。     The first terminal and the second terminal are exposed from one surface of the pair of side surfaces,
    The semiconductor module according to claim 13 or 14, wherein the output terminal is exposed from the other surface of the pair of side surfaces.
  16. 　前記第１端子および前記第２端子は、前記厚さ方向および前記第１方向の双方に対して直交する第２方向において互いに離間し、
    　前記第１端子、前記第２端子および前記出力端子の各々は、前記一対の側面のいずれかの面から露出する端子部を有し、
    　前記端子部は、前記一対の側面のいずれかの面から前記第１方向に延びる基部と、前記基部の前記第１方向における先端から、前記厚さ方向のうち前記第１主面が向く側に向けて延びる起立部と、を有する、請求項１５に記載の半導体モジュール。     The first terminal and the second terminal are separated from each other in a second direction orthogonal to both the thickness direction and the first direction;
    Each of the first terminal, the second terminal, and the output terminal has a terminal portion exposed from any one of the pair of side surfaces,
    The terminal portion includes a base portion extending in the first direction from one of the pair of side surfaces, and a tip of the base portion in the first direction on a side where the first main surface faces in the thickness direction. The semiconductor module according to claim 15, further comprising an upright portion extending toward the surface.
  17. 　前記第１端子および前記第２端子は、前記厚さ方向において互いに離間し、
    　前記第１端子および前記第２端子の各々は、前記一対の側面のうち一方の面から前記第１方向に延びる端子部を有し、
    　前記厚さ方向に沿って視て、前記第２端子の前記端子部の少なくとも一部が、前記第１端子の前記端子部に重なっている、請求項１５に記載の半導体モジュール。     The first terminal and the second terminal are separated from each other in the thickness direction,
    Each of the first terminal and the second terminal has a terminal portion extending in the first direction from one surface of the pair of side surfaces,
    The semiconductor module according to claim 15, wherein at least a part of the terminal portion of the second terminal overlaps the terminal portion of the first terminal as viewed along the thickness direction.
PCT/JP2019/019109 2018-06-08 2019-05-14 Semiconductor module WO2019235146A1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116825768A (en) * 2020-10-14 2023-09-29 罗姆股份有限公司 Semiconductor module
CN116936561A (en) * 2020-10-14 2023-10-24 罗姆股份有限公司 Semiconductor module
JP7483814B2 (en) 2021-11-18 2024-05-15 台達電子企業管理（上海）有限公司 Switch Module

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009088215A (en) * 2007-09-28 2009-04-23 Dowa Metaltech Kk Semiconductor device
JP2014207430A (en) * 2013-03-21 2014-10-30 ローム株式会社 Semiconductor device
JP2018026370A (en) * 2014-11-13 2018-02-15 株式会社日立製作所 Power semiconductor module
JP2018029201A (en) * 2017-10-13 2018-02-22 ローム株式会社 Semiconductor device
JP2018050084A (en) * 2009-05-14 2018-03-29 ローム株式会社 Semiconductor module
WO2018056205A1 (en) * 2016-09-20 2018-03-29 住友ベークライト株式会社 Method for producing heat dissipation structure

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009088215A (en) * 2007-09-28 2009-04-23 Dowa Metaltech Kk Semiconductor device
JP2018050084A (en) * 2009-05-14 2018-03-29 ローム株式会社 Semiconductor module
JP2014207430A (en) * 2013-03-21 2014-10-30 ローム株式会社 Semiconductor device
JP2018026370A (en) * 2014-11-13 2018-02-15 株式会社日立製作所 Power semiconductor module
WO2018056205A1 (en) * 2016-09-20 2018-03-29 住友ベークライト株式会社 Method for producing heat dissipation structure
JP2018029201A (en) * 2017-10-13 2018-02-22 ローム株式会社 Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116825768A (en) * 2020-10-14 2023-09-29 罗姆股份有限公司 Semiconductor module
CN116936561A (en) * 2020-10-14 2023-10-24 罗姆股份有限公司 Semiconductor module
CN116825768B (en) * 2020-10-14 2024-02-23 罗姆股份有限公司 Semiconductor module
CN116936561B (en) * 2020-10-14 2024-05-03 罗姆股份有限公司 Semiconductor module
JP7483814B2 (en) 2021-11-18 2024-05-15 台達電子企業管理（上海）有限公司 Switch Module

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