WO2023216965A1 - Mémoire ferroélectrique, son procédé de formation et dispositif électronique - Google Patents

Mémoire ferroélectrique, son procédé de formation et dispositif électronique Download PDF

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Publication number
WO2023216965A1
WO2023216965A1 PCT/CN2023/092103 CN2023092103W WO2023216965A1 WO 2023216965 A1 WO2023216965 A1 WO 2023216965A1 CN 2023092103 W CN2023092103 W CN 2023092103W WO 2023216965 A1 WO2023216965 A1 WO 2023216965A1
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ferroelectric
electrode
ferroelectric layer
concentration
layer
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PCT/CN2023/092103
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English (en)
Chinese (zh)
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孙一鸣
张恒
李悦
于方舟
张禹
吕杭炳
许俊豪
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华为技术有限公司
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Publication of WO2023216965A1 publication Critical patent/WO2023216965A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for

Definitions

  • the present application relates to the field of semiconductor memory technology, and in particular to a ferroelectric memory, a method of forming a ferroelectric memory, and an electronic device including the ferroelectric memory.
  • Ferroelectric random access memory is a memory that utilizes the unique non-volatile electrical properties of ferroelectric materials for data storage. Generally, the function of FeRAM to access data relies on the ferroelectric capacitor it contains.
  • FIG. 1 is a schematic structural diagram of a ferroelectric capacitor.
  • the ferroelectric capacitor includes a first electrode 01 and a second electrode 02 arranged oppositely, and a ferroelectric layer 03 formed between the first electrode 01 and the second electrode 02 .
  • a crystal in the ferroelectric phase is formed in the ferroelectric layer.
  • the central atoms of the crystal stop in a low energy state along the electric field.
  • the electric field is reversed and is applied to the ferroelectric layer, The central atom moves in the crystal along the direction of the electric field and stops in another low-energy state.
  • a large number of central atoms move and couple in the crystal unit cell to form ferroelectric domains.
  • the ferroelectric domains form polarization charges under the action of the electric field.
  • the polarization charges formed before and after the ferroelectric domains are reversed under the electric field have different energy levels. This is This binary stable state will cause the ferroelectric capacitor to charge and discharge, which can then be recognized by the external circuit and achieve a "0" or "1" storage state.
  • the ferroelectric film layer used in non-volatile memory must have stable ferroelectric switching properties so that the ferroelectric capacitor can have good endurance performance.
  • the ferroelectric layer 03 is in direct contact with the first electrode 01 and the second electrode 02, and the first electrode 01 and the second electrode 02 are usually made of materials containing metal.
  • the metal in the electrode 02 will take away the oxygen in the ferroelectric layer 03 , causing oxygen vacancies to be generated inside the ferroelectric layer 03 .
  • the gradual accumulation of oxygen vacancies is detrimental to the durability of ferroelectric capacitors. For example, on the one hand, it will cause pinning of the domain wall of the ferroelectric domain, resulting in polarization fatigue (fatigue), which will affect the durability of the ferroelectric capacitor; on the other hand, it will cause the symmetry of the hysteresis loop of the ferroelectric layer.
  • the property changes that is, the imprint effect (imprint) occurs.
  • imprint the imprint effect
  • the polarization flip of the ferroelectric layer will be hindered, that is, the ferroelectricity and durability of the ferroelectric capacitor decrease; on the other hand, the ferroelectric layer Conductive filaments (also called leakage channels) are formed in the layer, causing the ferroelectric capacitor to breakdown, thus affecting the durability of the ferroelectric capacitor.
  • the present application provides a ferroelectric memory, a method for forming the same, and an electronic device including the ferroelectric memory.
  • the main purpose is to provide an iron that can inhibit the migration of oxygen ions in the ferroelectric layer, thereby inhibiting the generation of oxygen vacancies in the ferroelectric layer, slow down or even avoid polarization fatigue, imprinting effects and breakdown phenomena, and thus have better durability.
  • electric capacitor to improve the storage performance of ferroelectric memory.
  • the present application provides a ferroelectric memory, which is a ferroelectric random access memory.
  • the ferroelectric memory includes: a substrate and a plurality of memory cells formed on the substrate; each memory cell includes a ferroelectric capacitor; the ferroelectric capacitor includes a stacked first electrode and a second electrode formed on the first electrode and the second electrode.
  • the preset gradient change here can make the ferroelectric phase crystal structure formed by crystallization in the ferroelectric layer be distributed as continuously as possible between the first side and the second side of the ferroelectric layer, showing a distribution effect close to penetrating the ferroelectric layer, or That is to say, it shows a distribution effect close to connecting the first electrode and the second electrode. Even if the ferroelectric phase crystal structure contains almost no other phase crystal structures, there is no layered distribution phenomenon between crystal phases, and it has relatively high integrity. It should be noted that when the distribution of the concentration of doping elements in the ferroelectric layer reaches a certain condition, the ferroelectric layer can be crystallized to form a completely continuously distributed ferroelectric phase crystal structure.
  • the ferroelectric phase crystal structure distributed in this way means that its initial content in the ferroelectric layer is relatively high, and correspondingly, the initial content of other phase crystal structures (such as antiferroelectric phase crystal structure and dielectric phase crystal structure) lower. Since the higher the crystal structure of the ferroelectric phase, it means that during the polarization flipping process, the content of the crystal structure of the dielectric phase increases more slowly, the slower the polarization fatigue occurs, and the slower the residual polarization intensity decreases. After the number of flips, the smaller the degree of polarization fatigue, the greater the residual polarization intensity. Therefore, such a ferroelectric layer has better ferroelectricity.
  • the concentration of the doping element exhibits the same gradient change from the preset position in the ferroelectric layer to the first side and the second side.
  • the concentration of hafnium element also shows the same gradient change from the preset position in the ferroelectric to the first side and the second side.
  • the concentration of the doping element gradually increases or decreases from a preset position in the ferroelectric layer toward the first side and the second side.
  • the concentration of the hafnium element gradually increases or decreases from the preset position in the ferroelectric to the first side and the second side.
  • the element distribution of this application can make the ferroelectric phase crystal structure crystallized in the ferroelectric layer as much as possible on the first side and the second side of the ferroelectric layer.
  • the two sides are continuously distributed, that is, the ferroelectric phase crystal structure does not include or includes as little as possible other phase crystal structures.
  • the ferroelectric layer is formed using a zirconium element-doped hafnium oxide-based material Hf 1-x Zr x O 2 , where X represents the concentration of zirconium element, specifically Hf 1-x Zr x The proportion of the number of zirconium atoms in O 2 to the total number of zirconium atoms and hafnium atoms in Hf 1-x Zr x O 2 ; the concentration of zirconium elements from the preset position in the ferroelectric layer to the first side and the When the two sides gradually increase, the minimum concentration X min of the zirconium element at the preset position is between 0-0.50, and the maximum concentration X max on the first and second sides is between 0.50-0.99; in When the concentration of zirconium element gradually decreases from the preset position to the first side and the second side, the maximum concentration X max of zirconium element at the preset position is between 0.50-0.99, and between the first side and the
  • the ferroelectric layer includes a doping element and a hafnium oxide-based material; the ratio of the concentration of the doping element to the concentration of the hafnium element is preset along the stacking direction of the first electrode and the second electrode. Gradient changes. Optionally, the ratio of the two concentrations shows the same gradient change from the preset position in the ferroelectric layer to the first side and the second side.
  • the ferroelectric layer is formed of a zirconium-doped hafnium oxide-based material Hf 1-x Zr x O 2 , where X represents the concentration of zirconium element, (1-X) is the concentration of hafnium element, X/(1 -X) is the concentration ratio of zirconium element to hafnium element.
  • X represents the concentration of zirconium element
  • (1-X) is the concentration of hafnium element
  • X/(1 -X) is the concentration ratio of zirconium element to hafnium element.
  • the value of X/(1-X) may gradually increase or decrease from the preset position in the ferroelectric layer toward the first side and the second side.
  • the ferroelectric layer has a residual polarization intensity greater than a preset value, and the preset value is greater than zero.
  • the ferroelectric memory including the ferroelectric capacitor can be made to have strong non-volatile properties.
  • the thickness of the ferroelectric layer in the stacking direction of the first electrode and the second electrode is 0.5nm-50nm.
  • this application provides a method for forming a ferroelectric memory.
  • the forming method includes:
  • a first electrode and a second electrode are formed on one side of the substrate, and the first electrode and the second electrode are stacked; a ferroelectric layer is formed between the first electrode and the second electrode, and the ferroelectric layer includes doping elements and hafnium oxide.
  • Base material the concentration of the doping element presents a first preset gradient change along the stacking direction of the first electrode and the second electrode, and correspondingly, the concentration of the hafnium element presents a second preset gradient along the stacking direction of the first electrode and the second electrode. Gradient change, wherein the first preset gradient change corresponds to the second preset gradient change.
  • the ferroelectric layer can be crystallized to form ferroelectric.
  • the phase crystal structure is distributed continuously between the first side and the second side of the ferroelectric layer as much as possible, showing a distribution effect that is close to penetrating the ferroelectric layer, or in other words, a distribution effect that is close to connecting the first electrode and the second electrode. Even if the ferroelectric phase crystal structure contains almost no other phase crystal structures, there is no layered distribution phenomenon between crystal phases, and it has relatively high integrity.
  • the ferroelectric layer can be crystallized to form a completely continuously distributed ferroelectric phase crystal structure.
  • Such a ferroelectric layer can make the ferroelectric capacitor have better durability and ferroelectricity.
  • the thickness of the ferroelectric layer is thinned to 10nm and below, it can also show better ferroelectricity and durability.
  • forming the ferroelectric layer between the first electrode and the second electrode includes: first using doping elements and hafnium oxide-based materials to deposit the ferroelectric layer on the first electrode or the second electrode. layer.
  • the ferroelectric layer is subjected to a crystallization process to form a continuous ferroelectric phase crystal structure between the first side and the second side in the ferroelectric layer.
  • the concentration distribution of the doping element (or hafnium element) in the ferroelectric layer is controlled to control the crystallization in the ferroelectric layer to form a continuous ferroelectric phase crystal structure.
  • the concentration X of the zirconium element can first be controlled to be higher, then the proportion of the concentration As the concentration Or, first control the concentration X of the zirconium element to be low, then increase the proportion of the gradient-controlled concentration Decreasing" gradient change rule.
  • the ferroelectric layer is deposited using deposition processes such as physical vapor deposition, chemical vapor deposition, and atomic layer deposition.
  • deposition processes such as physical vapor deposition, chemical vapor deposition, and atomic layer deposition.
  • the present application provides a method for forming a ferroelectric memory.
  • the forming method includes:
  • a first doped region and a second doped region are formed in the substrate, and a ferroelectric layer and a gate are formed on the substrate, and the ferroelectric layer is formed between the first doped region and the second doped region.
  • the gate electrode is formed on the side of the ferroelectric layer away from the substrate.
  • the ferroelectric layer includes doping elements and hafnium oxide-based materials; the gate electrode and the ferroelectric layer are annealed to A ferroelectric phase crystal structure is formed in the ferroelectric layer, and the ferroelectric phase crystal structure is continuously distributed between a first side close to the gate electrode and a second side far away from the gate electrode.
  • the ferroelectric phase crystal structure is continuously distributed between a first side close to the gate and a second side far away from the gate. Such a ferroelectric phase crystal structure can make ferroelectric capacitors have better durability and ferroelectricity.
  • this application also provides an electronic device, including a processor and the ferroelectric memory in any implementation manner of the first aspect, the second aspect, or the third aspect, and the processor is electrically connected to the ferroelectric memory.
  • the electronic device provided by the embodiment of the present application includes the ferroelectric memory of the first embodiment, the second embodiment or the third embodiment. Therefore, the electronic device provided by the embodiment of the present application and the ferroelectric memory of the above technical solution can solve the problem of Same technical issues, and achieve the same desired results.
  • Figure 1 is a schematic structural diagram of a ferroelectric capacitor
  • Figure 2 is a schematic diagram of the oxidation reaction between the ferroelectric layer 03 in Figure 1 and the first electrode 01 and the second electrode 02 to generate oxygen vacancies;
  • Figure 3 is a schematic diagram of the imprinting effect caused by oxygen vacancies in the ferroelectric layer
  • Figure 4 is a schematic diagram of the breakdown phenomenon caused by oxygen vacancies in the ferroelectric layer
  • FIG. 5 is a schematic diagram of another ferroelectric capacitor structure
  • Figure 6 is a schematic diagram of another ferroelectric capacitor structure
  • Figure 7 is a circuit diagram of an electronic device provided by an embodiment of the present application.
  • Figure 8 is a circuit diagram of a ferroelectric memory provided by an embodiment of the present application.
  • Figure 9 is a circuit diagram of a memory unit in a ferroelectric memory provided by an embodiment of the present application.
  • Figure 10 is a circuit diagram of a memory array formed by multiple memory cells in a ferroelectric memory provided by an embodiment of the present application
  • Figure 11 is a circuit diagram of a memory unit in a ferroelectric memory provided by an embodiment of the present application.
  • Figure 12 is a circuit diagram of a memory array formed by multiple memory cells in a ferroelectric memory provided by an embodiment of the present application
  • Figure 13 is a schematic diagram of the positional relationship between a ferroelectric capacitor and a substrate in a ferroelectric memory provided by an embodiment of the present application;
  • Figure 14 is a schematic diagram of the positional relationship between a ferroelectric capacitor and a substrate in a ferroelectric memory provided by an embodiment of the present application;
  • Figure 15 is a view in direction F of Figure 14;
  • Figure 16 is a transmission electron microscope image of a cross-section of a ferroelectric layer in the stacking direction of the first electrode and the second electrode in the prior art
  • Figure 17 is a transmission electron microscope image of a cross-section of the ferroelectric layer provided in the embodiment of the present application in the stacking direction of the first electrode and the second electrode;
  • Figure 18 is a schematic diagram of the relationship between the polarization intensity of the ferroelectric capacitor and the applied electric field provided by the embodiment of the present application;
  • Figure 19 is a schematic diagram of the distribution of zirconium element concentration X in the ferroelectric layer provided by the embodiment of the present application.
  • Figure 20 is a schematic diagram of the distribution of zirconium element concentration X in the ferroelectric layer provided by the embodiment of the present application.
  • Figure 21 is a schematic diagram of the concentration distribution of zirconium element and hafnium element in the ferroelectric layer provided by the embodiment of the present application;
  • Figure 22 is a flow chart of manufacturing a ferroelectric capacitor in a ferroelectric memory provided by an embodiment of the present application.
  • Figure 23 is a process structure diagram of a memory unit in a ferroelectric memory provided by an embodiment of the present application.
  • Figure 24 is a circuit diagram of a memory array formed by multiple memory cells in a ferroelectric memory provided by an embodiment of the present application.
  • Figure 25 is a flow chart of manufacturing a memory unit in a ferroelectric memory provided by an embodiment of the present application.
  • Unit cell It is a structure composed of a large number of microscopic material units (atoms, ions, molecules, etc.) arranged in an orderly manner according to certain rules.
  • Crystal grains During the growth process of crystalline materials, they crystallize into granular shapes, which are called crystal grains. The direction and position of the internal unit cells of the crystal grains are basically the same.
  • Grain boundary The contact interface between grains is called grain boundary.
  • Ferroelectric phase crystal The structure of the unit cell causes the positive and negative charge centers to not overlap and an electric dipole moment appears, resulting in an electric polarization intensity that is not equal to zero, making the crystal spontaneously polarized, and the direction of the electric dipole moment can be changed by an external electric field. , showing characteristics similar to ferromagnets.
  • Ferroelectric materials They can maintain spontaneous polarization by aligning their internal electric dipole moments with an applied electric field, even when the externally applied electric field is removed.
  • a ferroelectric is a material in which the polarization value (or electric field) remains semi-permanently, even after a constant voltage is applied and the voltage returns to zero volts.
  • Ferroelectric memory stores data based on the ferroelectric effect of ferroelectric materials.
  • Ferroelectric memory is expected to become the main competitor of dynamic random access memory (DRAM) due to its ultra-high storage density, low power consumption and high speed.
  • the memory unit in the ferroelectric memory includes a ferroelectric capacitor.
  • the ferroelectric capacitor includes two electrodes and a ferroelectric material, such as a ferroelectric layer, disposed between the two electrodes. Due to the nonlinear characteristics of ferroelectric materials, the dielectric constant of ferroelectric materials can not only be adjusted, but also the difference before and after the polarization state of the ferroelectric layer flips is very large, which makes ferroelectric capacitors smaller than other capacitors. For example, it is much smaller than the capacitor used to store charge in DRAM.
  • the ferroelectric layer in ferroelectric capacitors, can be formed using common ferroelectric materials. After crystallization, a ferroelectric phase crystal structure can be formed in the ferroelectric layer.
  • the central atoms in the ferroelectric phase crystal structure stop in a low energy state along the electric field.
  • the electric field When inversion is applied to the ferroelectric layer, the central atom moves through the crystal in the direction of the electric field and stops in another low-energy state. A large number of central atoms move and couple in the crystal unit cell to form ferroelectric domains, which form polarized charges under the action of an electric field.
  • the polarization charge formed by the reversal of the ferroelectric domain under the electric field is high, and the polarization charge formed by the non-reversal of the ferroelectric domain under the electric field is low.
  • the binary stable state of this ferroelectric material allows it to be used in memory.
  • ferroelectric layer For ferroelectric capacitors used in non-volatile memories, the ferroelectric layer must have stable ferroelectric switching properties so that the ferroelectric capacitor can have good durability. Factors that affect the durability performance of ferroelectric capacitors include but are not limited to: polarization fatigue, imprinting effect, and breakdown phenomena.
  • the ferroelectric capacitor structure can Called “MIM" (metal-insulation-metal) ferroelectric capacitor structure.
  • MIM metal-insulation-metal
  • the ferroelectric layer 03 acts as an oxygen ion donor
  • the first electrode 01 and the second electrode 02 act as oxygen ion acceptors.
  • An oxidation reaction occurs, and the positively charged oxygen ion vacancies ( (abbreviated as oxygen vacancies) are generated near the contact surface between the ferroelectric layer 03 and the electrode and inside the ferroelectric layer 03 .
  • FIG. 2 is a schematic diagram of the oxidation reaction between the ferroelectric layer 03 in FIG. 1 and the first electrode 01 and the second electrode 02 to generate oxygen vacancies.
  • an oxidation reaction occurs between the ferroelectric layer 03 and the first electrode 01 and the second electrode 02.
  • the oxygen ions in the ferroelectric layer 03 migrate to the first electrode 01 and the second electrode 02.
  • Oxygen vacancies are formed in 03.
  • Polarization fatigue refers to the phenomenon that the polarization strength of ferroelectrics decreases after multiple polarization cycles.
  • Ferroelectric memory will perform a large number of erasing/rewriting operations when reading and writing information.
  • the ferroelectric layer continuously flips polarization. After many repetitions, the residual polarization intensity (Pr) of the ferroelectric layer decreases and the coercive field ( Ec) increases, the two states "0" or "1" get closer and closer, and finally become difficult to distinguish.
  • charged defects such as oxygen vacancies in the ferroelectric layer can cause pinning of domain walls, thereby causing polarization fatigue.
  • the ferroelectric layer generally includes randomly distributed ferroelectric phase crystal structures, antiferroelectric phase crystal structures and dielectric phase crystal structures.
  • the ferroelectric phase crystal structure will be transformed into The dielectric phase crystal structure, which means that the content of the ferroelectric phase crystal structure gradually decreases based on its initial content, and the content of the dielectric phase crystal structure gradually increases based on its initial content. Since the residual polarization intensity of the ferroelectric layer is closely related to the content of ferroelectric phase crystals in the ferroelectric layer, the gradual reduction in the content of the ferroelectric phase crystal structure will inevitably reduce the residual polarization intensity of the ferroelectric layer and cause polarization fatigue.
  • the embodiments of the present application relate to the initial contents of various crystal phase structures, which can be understood as the contents of various crystal phase structures before the first polarization flip occurs in the ferroelectric layer.
  • the imprinting effect means that the charge injected by the electrode will generate a built-in electric field in the ferroelectric layer, hindering the flipping of the ferroelectric dipole. Under the influence of the imprinting effect, the polarization flip of the ferroelectric layer will be hindered, which is manifested as the drift of the coercive field and the increase in ferroelectric flip time. At the same time, the residual polarization intensity will also decrease. Once the coercive field drift exceeds the threshold voltage of the "0" state and "1" state of the memory, data read and write errors will occur, and the attenuation of the residual polarization intensity will weaken the storage signal and increase the error rate of data readout.
  • Figure 3 shows a schematic diagram of the imprinting effect caused by oxygen vacancies in the ferroelectric layer.
  • the abscissa represents the electric field intensity E applied to the ferroelectric layer, and the ordinate represents the polarization intensity P of the ferroelectric layer;
  • the black solid line represents The hysteresis loop of the ferroelectric layer when no oxygen vacancies are generated, and the black dotted line represents the hysteresis loop of the ferroelectric layer after oxygen vacancies are generated. It can be seen that after the oxygen vacancies are generated, the symmetry of the hysteresis loop of the ferroelectric layer becomes worse, and the ferroelectricity becomes worse.
  • the breakdown phenomenon means that the charging and discharging voltage of the ferroelectric capacitor causes the dielectric material to be broken down.
  • Figure 4 shows a schematic diagram of the breakdown phenomenon caused by oxygen vacancies in the ferroelectric layer, in which the abscissa represents the number of polarization flips, and the ordinate corresponds to 2 times the residual polarization intensity Pr of each flip process. It can be seen that the gradual accumulation of oxygen vacancies in the ferroelectric layer causes the formation of conductive filaments (also called leakage channels) in the ferroelectric layer, resulting in breakdown after a certain number of polarization flips.
  • conductive filaments also called leakage channels
  • the ferroelectric layer 03 in Figure 1 is replaced with HfO 2 with a thickness of 1 nm as a period.
  • -ZrO 2 periodic layered structure 04 in which HfO 2 layers and ZrO 2 layers appear alternately, that is, there is a ZrO 2 layer between two adjacent HfO 2 layers, and/or, There is an HfO 2 layer between two adjacent ZrO 2 layers to inhibit the migration of oxygen ions and the generation of oxygen vacancies, thereby improving the durability of the ferroelectric capacitor.
  • the HfO 2 -ZrO 2 periodic layered structure when the HfO 2 -ZrO 2 periodic layered structure is selected as the ferroelectric layer in the "MIM" ferroelectric capacitor, the HfO 2 layer itself will not easily crystallize the ferroelectric phase and must cooperate with the ZrO 2 layer. The effect of crystallization. This means that such a HfO 2 -ZrO 2 periodic layered structure is not essentially different from Zr-doped HZO. Moreover, when the thickness of the ferroelectric layer is small (such as ⁇ 10nm), the effect of the HfO 2 -ZrO 2 periodic layered structure is very limited.
  • a layer of oxygen-rich material (such as TiO 2 ) is inserted between the two electrodes 02 as a transition layer 05 between the electrodes and the ferroelectric layer.
  • oxygen-rich material such as TiO 2
  • the thermal expansion coefficient and crystallization temperature of the newly introduced dielectric layer are greatly different from those of the ferroelectric layer, it is easy to produce mismatch stress with the ferroelectric layer during the crystallization process ( mismatch strain) problem, causing the lattice dislocation of the ferroelectric layer and producing more defects.
  • the introduction of other non-ferroelectric layers will cause additional voltage division, which may result in an unnecessary increase in the applied electric field and the associated power consumption.
  • An embodiment of the present application provides an electronic device including a ferroelectric memory, where the ferroelectric memory includes a ferroelectric capacitor.
  • the ferroelectric capacitor structure provided in the embodiment of the present application can not only produce better suppression effects on ferroelectric polarization fatigue, imprinting effects and breakdown phenomena, but also Improve the durability of ferroelectric capacitors.
  • the ferroelectric capacitor can also show better ferroelectricity and durability.
  • FIG. 7 shows an electronic device 200 provided by an embodiment of the present application.
  • the electronic device 200 can be a terminal device, such as a mobile phone, a tablet, a smart bracelet, or a personal computer (PC), server, workstation, etc. .
  • the electronic device 200 includes a bus 205, a system on chip (SOC) 210 and a read-only memory (ROM) 220 connected to the bus 205.
  • SOC210 can be used to process data, such as processing application data, processing image data, and caching temporary data.
  • ROM 220 can be used to save non-volatile data, such as audio files, video files, etc.
  • ROM 220 can be PROM (programmable read-only memory, programmable read-only memory), EPROM (erasable programmable read-only memory, erasable programmable read-only memory), flash memory (flash memory), etc.
  • the electronic device 200 may also include a communication chip 230 and a power management chip 240.
  • the communication chip 230 can be used to process the protocol stack, or to amplify and filter analog radio frequency signals, or to implement the above functions at the same time.
  • the power management chip 240 can be used to power other chips.
  • the SOC 210 may include an application processor (AP) 211 for processing applications, a graphics processing unit (GPU) 212 for processing image data, and a cache data Random access memory (RAM) 213.
  • AP application processor
  • GPU graphics processing unit
  • RAM cache data Random access memory
  • the above-mentioned AP211, GPU212 and RAM213 can be integrated into one die, or integrated into multiple die, and packaged in a packaging structure, such as 2.5D (dimension) or 3D packaging. , or other advanced packaging technologies.
  • the above-mentioned AP211 and GPU212 are integrated In one die, RAM 213 is integrated in another die, and the two dies are packaged in a packaging structure to obtain faster inter-die data transmission rate and higher data transmission bandwidth.
  • FIG. 8 is a schematic structural diagram of a ferroelectric memory 300 provided by an embodiment of the present application.
  • the ferroelectric memory 300 may be RAM 213 as shown in Figure 7, which belongs to FeRAM.
  • the ferroelectric memory 300 may also be a RAM disposed outside the SOC 210 . This application does not limit the position of the ferroelectric memory 300 in the device and its positional relationship with the SOC 210 .
  • the ferroelectric memory 300 includes a memory array 310 , a decoder 320 , a driver 330 , a timing controller 340 , a buffer 350 and an input/output driver 360 .
  • the storage array 310 includes a plurality of storage units 400 arranged in an array, where each storage unit 400 can be used to store 1 bit or multiple bits of data.
  • the memory array 310 also includes signal lines such as word lines (WL) and bit lines (BL). Each memory cell 400 is electrically connected to the corresponding word line WL and bit line BL.
  • One or more of the above-mentioned word lines WL and bit lines BL are used to select the memory cells 400 to be read and written in the memory array by receiving the control level output by the control circuit, so as to change the polarity of the ferroelectric capacitor in the memory cells 400. direction to realize data reading and writing operations.
  • the decoder 320 is used to decode according to the received address to determine the memory unit 400 that needs to be accessed.
  • the driver 330 is used to control the level of the signal line according to the decoding result generated by the decoder 320, thereby achieving access to the designated storage unit 400.
  • the buffer 350 is used to cache the read data. For example, first-in first-out (FIFO) may be used for caching.
  • the timing controller 340 is used to control the timing of the buffer 350 and control the driver 330 to drive the signal lines in the memory array 310 .
  • the input and output driver 360 is used to drive transmission signals, such as driving received data signals and driving data signals to be sent, so that the data signals can be transmitted over long distances.
  • the above-mentioned memory array 310, decoder 320, driver 330, timing controller 340, buffer 350 and input/output driver 360 can be integrated into one chip, or can be integrated into multiple chips respectively.
  • the ferroelectric memory 300 involved in this application may be a ferroelectric random access memory (ferroelectric random access memory, FeRAM) or a ferroelectric field effect transistor memory (ferroelectric field effect transistor, FeFET).
  • FeRAM ferroelectric random access memory
  • FeFET ferroelectric field effect transistor
  • Figure 9 shows a circuit structure diagram of one of the memory units 400 of FeRAM.
  • the memory unit 400 includes at least two ferroelectric capacitors C and one transistor Tr.
  • Figure 9 exemplarily shows With three ferroelectric capacitors (ferroelectric capacitor C1, ferroelectric capacitor C2 and ferroelectric capacitor C3 in Figure 9), such a memory cell can be called a 1TnC memory cell.
  • the transistor Tr here may be a metal-oxide-semiconductor field-effect transistor (MOSFET).
  • the memory unit 400 also includes a word line (WL), a bit line (BL) and a plate line (PL) signal line, and in the memory unit 400, the first terminal of the transistor Tr
  • the terminal of the transistor Tr is electrically connected to the bit line BL
  • the control terminal of the transistor Tr is electrically connected to the word line WL
  • the second terminal of the transistor Tr is electrically connected to the first electrode of the ferroelectric capacitor C
  • the second electrode of the ferroelectric capacitor C is electrically connected to the plate line PL.
  • Electrical connection one of the drain or source of the transistor Tr is called the first terminal
  • the corresponding other terminal is called the second terminal
  • the control terminal of the transistor Tr is the gate.
  • a storage unit 400 shown in FIG. 9 can be used to store multi-bit data to increase the storage capacity of each storage unit.
  • these ferroelectric capacitors C share one transistor Tr, which further reduces the number of transistors in each memory cell 400 to increase storage density.
  • a memory array 310 By arranging the above-mentioned memory cells 400 shown in Figure 9 in an array, a memory array 310 can be obtained, in which each memory unit 400 has the same circuit structure.
  • an exemplary A memory array of four memory cells including memory unit 401, memory unit 402, memory unit 403, and memory unit 404.
  • the storage array 310 may further include more storage units 400, and the storage units 400 may be arranged in the X, Y, and Z directions that are perpendicular to each other to form a three-dimensional storage array.
  • FIG. 11 shows a circuit structure diagram of another memory unit 400 of FeRAM.
  • the memory unit 400 includes a first transistor Tr1 and a second transistor Tr2, and at least two ferroelectric capacitors.
  • FIG. 11 shows an example of a memory unit 400 including two ferroelectric capacitors, respectively.
  • Ferroelectric capacitor C2 and ferroelectric capacitor C1 have the same structure, including two electrodes and a ferroelectric layer between the two electrodes.
  • One electrode of the ferroelectric capacitor C1 can be called the first electrode, and the other electrode can be called the second electrode.
  • One electrode of the ferroelectric capacitor C2 can be called the third electrode, and the other electrode can be called the fourth electrode.
  • the memory unit 400 also includes a word line (word line, WL), a write bit line (write bit line, WBL), a read bit line (read bit line, RBL), and a source line (source line, SL). and control line (CL).
  • word line, WL word line
  • WBL write bit line
  • RBL read bit line
  • source line source line
  • CL control line
  • the control terminal of the first transistor Tr1 is electrically connected to the control line CL
  • the first terminal of the first transistor Tr1 is electrically connected to the first electrode of the ferroelectric capacitor C1 and the third electrode of the ferroelectric capacitor C2 respectively.
  • the first transistor Tr1 The second end of the ferroelectric capacitor C1 is electrically connected to the write bit line WBL, and the second electrode of the ferroelectric capacitor C1 and the fourth electrode of the ferroelectric capacitor C2 are electrically connected to the corresponding word line WL.
  • the first end of the second transistor Tr2 is electrically connected to the source line SL, the second end is electrically connected to the read bit line RBL, and the control end of the second transistor T2 is respectively connected to the first pole and the ferroelectric capacitor C1.
  • the third pole of the capacitor C2 is electrically connected.
  • the memory cells 400 shown in FIG. 11 are arranged in an array to obtain the memory array 310 shown in FIG. 12.
  • the memory array 310 shown in FIG. 12 an exemplary A memory array of four memory cells including memory unit 401, memory unit 402, memory unit 403 and memory unit 404 is given.
  • control line CL0 the control line
  • control line CL1 the control line
  • control line CL2 the control line
  • control line CL3 the control line
  • the memory array 310 includes two write bit lines, namely write bit line WBL0 and write bit line WBL1, and each write bit line extends along the X direction.
  • write bit line WBL0 When it also includes more write bit lines WBL , these write bit lines WBL are arranged in parallel along the Y direction perpendicular to the WBL1, memory cell 403 and memory cell 404 share write bit line WBL0.
  • the read bit line RBL and the write bit line WBL are set up in the same manner, which will not be described again here.
  • the source line SL in this memory array not only the multiple memory cells arranged along the The source lines SL are shared, and the source lines SL of multiple memory cells arranged along the Y direction are also shared.
  • the source line SL of the memory unit 401 here and the source line SL of the memory unit 404 are shared.
  • the source line SL of the memory unit 401 is also shared.
  • SL and the source line SL of the memory unit 402 are also shared, that is, the source lines SL of the memory unit 401, the memory unit 402, the memory unit 403 and the memory unit 404 here are connected to each other.
  • a source line SL layer structure parallel to the substrate can be formed to electrically connect the source lines parallel to the substrate.
  • the word line WL in this memory array is not only shared by the plurality of memory cells arranged in the X direction, but also shared by the plurality of memory cells arranged in the Y direction. , for example, here the word line WL0 connected to the ferroelectric capacitor C0 of the memory unit 401 is shared with the word line WL0 connected to the ferroelectric capacitor C0 of the memory unit 402.
  • the word line WL0 connected to the ferroelectric capacitor C0 of the unit 404 is also shared, that is, the word lines WL0 of the four ferroelectric capacitors C0 of the memory unit 401, memory unit 402, memory unit 403 and memory unit 404 are connected to each other, and the memory unit 401 , WL1 of the four ferroelectric capacitors C1 of the storage unit 402, the storage unit 403 and the storage unit 404 are connected to each other.
  • a word line layer structure parallel to the substrate can be provided to connect word lines located on the same layer to each other.
  • the overall structure of the ferroelectric capacitor can be a "MIM" structure as shown in FIG. 1 , including stacked first electrodes 01 and second electrodes 02 , and a Ferroelectric layer 03 between first electrode 01 and second electrode 02 .
  • the first electrode 01 , the ferroelectric layer 03 and the second electrode 02 may be arranged on the substrate 100 as shown in FIG. 13 , that is, the first electrode 01 , the ferroelectric layer 03 and the second electrode 02 Stacked in a direction perpendicular to the substrate 100 . That is, each layer structure of the first electrode 01, the ferroelectric layer 03, and the second electrode 02 is arranged parallel to the substrate 100.
  • Such a ferroelectric capacitor can be called a planar ferroelectric capacitor structure.
  • the first electrode 01 , the ferroelectric layer 03 and the second electrode 02 may be arranged on the substrate 100 as shown in FIG. 14 , that is, the first electrode 01 , the ferroelectric layer 03 and the second electrode 02 Stacked in a direction parallel to the substrate 100 .
  • Such ferroelectric capacitors can be called vertical capacitor structures. When using a vertical capacitor structure, three-dimensional stacking can be achieved to increase storage density and storage capacity.
  • Figure 15 shows one of the achievable structures in the vertical ferroelectric capacitor structure, and Figure 15 is the F-direction view in Figure 14.
  • the first electrode 01 extends in a direction perpendicular to the substrate 100
  • the ferroelectric layer 03 and the second electrode 02 sequentially surround the periphery of the first electrode 01 in a direction parallel to the substrate 100 .
  • This forms a ferroelectric capacitor with a cylindrical structure.
  • the cross-section of the ferroelectric capacitor with a cylindrical structure may be circular as shown in Figure 15, or may be rectangular, or may be other shapes.
  • planar ferroelectric capacitor structure such as the above-mentioned "MIM" structure
  • the first electrode 01 and the second electrode 02 may be made of metal-containing materials, such as metal, metal nitride, metal carbide, conductive metal nitride, conductive metal oxide or combinations thereof.
  • the first electrode 01 may include, for example, titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir) , ruthenium oxide (RuO 2 ), iridium oxide (IrO 2 ), niobium nitride (NbN), molybdenum nitride (MoN) or combinations thereof.
  • the second electrode 02 may include, for example, titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium carbonitride (TiCN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO 2 ), niobium nitride (NbN), molybdenum nitride (MoN), iridium oxide (IrO 2 ), silicon (Si), germanium (Ge) ), silicon germanium (SiGe) or a combination thereof. and, The materials of the first electrode 01 and the second electrode 02 may be the same or different.
  • the thickness of the first electrode 01 and the second electrode 02 along the stacking direction may be, but is not limited to, 1 nm to 100 nm. Furthermore, the thickness of the first electrode 01 and the thickness of the second electrode 02 may be equal or unequal.
  • the above-mentioned ferroelectric layer 03 has ferroelectricity, so that it has spontaneous polarization within a certain temperature range, and its spontaneous polarization direction can be reversed due to the reverse direction of the external electric field. In this case, when its polarization orientation is reversed, the ferroelectric capacitor will be charged and discharged, which can then be recognized by the external circuit and achieve a "0" or "1" storage state.
  • the above ferroelectric layer 03 can be made of hafnium oxide-based material. Compared with other ferroelectric materials, the thickness of hafnium oxide-based ferroelectric capacitors can be reduced to ten nanometers or even sub-ten nanometers. In this case, high-density integration and even three-dimensional integration can be achieved, which has great advantages in building ultra-high-density memory chips. In addition, the preparation process of hafnium oxide-based ferroelectric capacitors can have good compatibility with silicon-based semiconductor processes, so that mature manufacturing processes can be used to manufacture the ferroelectric capacitors without increasing manufacturing costs.
  • hafnium oxide-based materials refer to materials based on the hafnium oxide material system and having ferroelectricity.
  • it can be zirconium (Zr) doped hafnium dioxide (HfO 2 ), silicon (Si) doped HfO 2 , aluminum (Al) doped HfO 2 , lanthanum (La) doped HfO 2 , yttrium (Y)-doped HfO 2 , gadolinium (Gd)-doped HfO 2 , strontium (Sr)-doped HfO 2 , etc.; or it can also be a hafnium zirconium oxide (HZO) system, for example, it can be Lanthanum (La)-doped HZO, yttrium (Y)-doped HZO, strontium (Sr)-doped HZO, gadolinium (Gd)-doped HZO, gadolinium
  • titanium nitride TiN can be selected to make the first electrode 01 and the second electrode 02, and zirconium (Zr)-doped hafnium dioxide (HZO) can be used to make the ferroelectric layer 03, thereby making full use of the HZO layer to provide Tensile stress is conducive to the formation of ferroelectric phases, and the TiN material is compatible with the semiconductor CMOS process.
  • Zr zirconium
  • HZO hafnium dioxide
  • the migration of oxygen ions in the ferroelectric layer 03 is effectively suppressed, which can slow down or even avoid the above-mentioned polarization fatigue, imprinting effect and breakdown phenomenon, so that the ferroelectric capacitor shows better durability performance.
  • the following describes the technical solution of the present application from the perspective of crystal phase distribution in the ferroelectric layer 03 and element concentration distribution in the ferroelectric layer.
  • a continuous ferroelectric phase crystal structure is formed in the ferroelectric layer 03 .
  • the continuous ferroelectric phase crystal structure extends from the side of the ferroelectric layer 03 close to the first electrode 01 to the ferroelectric layer 03 The side close to the second electrode 02.
  • the side of the ferroelectric layer 03 close to the first electrode 01 is called the first side
  • the side of the ferroelectric layer 03 close to the second electrode 02 is called the second side.
  • the continuous ferroelectric phase crystal structure can be understood as the ferroelectric phase crystal structure is continuously distributed between the first side and the second side of the ferroelectric layer, showing a distribution effect close to penetrating the ferroelectric layer, or in other words, It shows a distribution effect that is close to connecting the first electrode and the second electrode.
  • the continuous ferroelectric phase crystal structure can be further understood as the ferroelectric phase crystal structure contains almost no other phase crystal structures, and there is no stratified distribution phenomenon between crystal phases, so it has relatively high integrity.
  • ferroelectric layer shown in FIG. 6 above randomly distributed ferroelectric phase crystal structures, antiferroelectric phase crystal structures and dielectric phase crystal structures are formed. Since the distribution of ferroelectric phase crystal structure, antiferroelectric phase crystal structure and dielectric phase crystal structure is highly random, there are a large number of grain boundaries of different crystal phases in the ferroelectric layer as a whole. Since the grain boundaries in the ferroelectric layer will provide channels for the migration of oxygen ions, they will intensify the migration of oxygen ions and lead to the generation of more oxygen vacancies, which will in turn aggravate the above-mentioned polarization fatigue, imprinting effects and breakdown phenomena, which is not good for iron. Capacitor Durability able.
  • the initial content of the antiferroelectric phase crystal structure and the dielectric phase crystal structure is relatively high, while the initial content of the ferroelectric phase crystal structure is relatively low.
  • this is one of the reasons for the random distribution of the ferroelectric phase crystal structure, antiferroelectric phase crystal structure and dielectric phase crystal structure in the ferroelectric layer.
  • it is also one of the reasons for the poor flipping properties of the ferroelectric layer. .
  • the initial content of the antiferroelectric phase crystal structure and the dielectric phase crystal structure is higher, while the initial content of the ferroelectric phase crystal structure is lower” here does not refer to the antiferroelectric phase crystal structure and the dielectric phase.
  • the initial content of the crystal structure is greater than the initial content of the ferroelectric phase crystal structure, but relative to the ferroelectric layer provided in this application, the initial content of the antiferroelectric phase crystal structure and the dielectric phase crystal structure is higher, and the ferroelectric phase The initial content of the crystal structure is low.
  • Figure 16 is a transmission electron microscope image of a cross-section of a ferroelectric layer in the prior art.
  • the transmission electron microscope image shows the cross-sectional structure of the ferroelectric layer in the stacking direction of the first electrode and the second electrode.
  • the ferroelectric layer is made of zirconium-doped material. Made from hafnium oxide-based material HZO.
  • a ferroelectric phase (O phase) crystal structure and a dielectric phase (M phase) crystal structure are formed inside the ferroelectric layer, and there are obvious grain boundaries inside the ferroelectric layer. Or it can be understood that within the ferroelectric layer, the ferroelectric phase crystal structure is not continuously distributed between the first electrode and the second electrode.
  • Figure 17 is a transmission electron microscope image of a cross-section of a ferroelectric layer in an embodiment of the present application.
  • the ferroelectric layer is made of zirconium-doped hafnium oxide-based material (Hf 1-x Zr x O 2 ).
  • This transmission electron microscope image shows the cross-sectional structure of the ferroelectric layer in the stacking direction of the first electrode and the second electrode.
  • a continuous ferroelectric phase crystal structure is formed in the ferroelectric layer, and the continuous ferroelectric phase crystal structure is composed of ferroelectric
  • the first side of the layer extends to the second side, and there are no grain boundaries of different crystal phases in the ferroelectric phase crystal structure, and there is no layered distribution phenomenon between crystal phases, that is, it has high continuity and integrity. .
  • ferroelectric layer As shown in Figure 17, on the one hand, since a continuously distributed and complete ferroelectric phase crystal structure is formed between the first side and the second side, there are no different crystal structures in the ferroelectric phase crystal structure. There is no layered distribution phenomenon between crystal phases at the grain boundaries of the phases. This is equivalent to reducing the migration channels of oxygen ions, which can inhibit the migration of oxygen ions and reduce the generation of oxygen vacancies, thereby slowing down or even avoiding the above extremes. Chemical fatigue, imprinting effect and breakdown phenomenon make ferroelectric capacitors have better durability performance.
  • the distribution of the ferroelectric phase crystal structure between the first side and the second side of the ferroelectric layer is continuous, which means that the ferroelectric phase crystal structure in the ferroelectric layer has a higher initial content.
  • other Phase crystal structures such as antiferroelectric phase crystal structure and dielectric phase crystal structure
  • have lower initial content The higher the initial content of the ferroelectric phase crystal structure in the ferroelectric layer, the better the ferroelectricity of the ferroelectric layer.
  • the higher the initial content of the ferroelectric phase crystal structure in the ferroelectric layer means that during the polarization flipping process, the content of the dielectric phase crystal structure increases more slowly, and the slower the generation rate of polarization fatigue, the remaining The slower the polarization intensity decreases, the smaller the degree of polarization fatigue and the greater the residual polarization intensity after a certain number of flips.
  • FIG. 18 is a schematic diagram showing the relationship between the polarization intensity of the ferroelectric capacitor and the applied electric field according to the embodiment of the present application.
  • the ferroelectric layer when the applied electric field to the ferroelectric layer is removed, the ferroelectric layer has a high residual polarization intensity. At the same time, after a certain number of polarization flips, it still has a high residual polarization intensity.
  • the ferroelectric memory including the ferroelectric capacitor can be made to have strong non-volatile properties.
  • element-doped hafnium oxide-based materials can be used to form the ferroelectric layer.
  • concentration of the doping element is the same everywhere in the ferroelectric layer.
  • concentration of hafnium element is the same everywhere in the ferroelectric layer.
  • concentration profile of the doping elements (and hafnium) often results in the formation of crystals in the ferroelectric layer.
  • Ferroelectric phase crystal structures, antiferroelectric phase crystal structures, and dielectric phase crystal structures are randomly distributed.
  • the ferroelectric layer includes doping elements and hafnium oxide-based materials.
  • the concentration of the doping element presents a first preset gradient change along the stacking direction of the first electrode and the second electrode, and correspondingly, the concentration of the hafnium element presents a second preset gradient along the stacking direction of the first electrode and the second electrode. Change, wherein the first preset gradient change corresponds to the second preset gradient change. For example, if the concentration of the doping element gradually increases, then the concentration of the hafnium element gradually decreases; if the concentration of the doping element gradually decreases, then the concentration of the hafnium element gradually increases.
  • the preset gradient change here can make the ferroelectric phase crystal structure formed by crystallization in the ferroelectric layer be distributed as continuously as possible between the first side and the second side of the ferroelectric layer, that is, the ferroelectric phase crystal structure almost does not include other phases. There is no stratified distribution phenomenon between crystal phases in the crystal structure. It should be noted that when the distribution of the concentration of doping elements in the ferroelectric layer reaches a certain condition, the ferroelectric layer can be crystallized to form a completely continuously distributed ferroelectric phase crystal structure.
  • the concentration distribution of the doping element or the hafnium element in the thickness direction of the ferroelectric layer is controlled to control the crystallization in the ferroelectric layer to form a continuous ferroelectric phase crystal structure.
  • a continuous ferroelectric phase crystal structure such as the ferroelectric phase crystal structure shown in Figure 17.
  • the thickness direction of the ferroelectric layer here is the stacking direction of the first electrode and the second electrode. It should be understood that for non-"MIM" ferroelectric capacitors, the thickness direction of the ferroelectric layer here may be other directions.
  • the concentration of the doping element exhibits the same gradient change from the predetermined position in the ferroelectric layer to the first side and the second side.
  • the concentration of hafnium element also shows the same gradient change from the preset position in the ferroelectric to the first side and the second side.
  • the concentration of the doping element gradually increases or decreases from a preset position in the ferroelectric layer toward the first side and the second side.
  • the concentration of the hafnium element gradually increases or decreases from the preset position in the ferroelectric to the first side and the second side.
  • the preset position here refers to a position between the first side and the second side.
  • the preset position may be a position where the first distance and the second distance are equal. Simply put, the preset position can be the "midpoint position" of the ferroelectric layer in the thickness direction.
  • the above-mentioned first preset gradient change may be: in the thickness direction of the ferroelectric layer, the concentration of the doping element gradually increases from the “midpoint position" to the first side of the ferroelectric layer, and from the “midpoint position” position” also gradually increases toward the second side of the ferroelectric layer; or, in the thickness direction of the ferroelectric layer, the concentration of the doping element gradually decreases from the "midpoint position" toward the first side of the ferroelectric layer, and from The "midpoint position” also gradually decreases toward the second side of the ferroelectric layer.
  • the element distribution of this application can make the ferroelectric phase crystal structure crystallized in the ferroelectric layer as much as possible on the first side and the second side of the ferroelectric layer.
  • the continuous distribution between the two sides means that the ferroelectric phase crystal structure almost does not include other phase crystal structures, and no layered distribution phenomenon between crystal phases occurs.
  • the ferroelectric layer is formed using a zirconium element-doped hafnium oxide-based material Hf 1-x Zr x O 2 , where X represents the concentration of zirconium element, specifically Hf 1-x Zr x
  • X represents the concentration of zirconium element, specifically Hf 1-x Zr x
  • the number of zirconium atoms in O 2 accounts for the total number of zirconium atoms and hafnium atoms in Hf 1-x Zr x O 2 .
  • Figure 19 illustrates an example of the zirconium element concentration X distribution in the ferroelectric layer.
  • the zirconium element gradually decreases from the preset position A to the first side B of the ferroelectric layer, and from the preset position A to the second side C of the ferroelectric layer Gradually decrease, showing a "opening downward" curve change. That is to say, in the area of the ferroelectric layer close to the two electrodes, the zirconium element content is low and the hafnium element content is high; in the area near the center of the ferroelectric layer, the zirconium element content is high and the hafnium element content is low .
  • the maximum concentration X max of zirconium element at the preset position can be between 0.50-0.99 between, and the minimum concentration X min on the first side and the second side can be between 0-0.50.
  • Figure 20 illustrates another distribution of zirconium element concentration in the ferroelectric layer. It can be intuitively seen from Figure 20 that along the thickness direction of the ferroelectric layer, the zirconium element gradually increases from the preset position A to the first side B of the ferroelectric layer, and from the preset position A to the second side of the ferroelectric layer B gradually increases, showing an "opening upward" curve change. That is to say, in the area of the ferroelectric layer close to the two electrodes, the zirconium element content is higher and the hafnium element content is lower; in the area near the center of the ferroelectric layer, the zirconium element content is lower and the hafnium element content is higher .
  • the minimum concentration X min of the zirconium element at the preset position is between 0-0.50, and the maximum concentration X max on the first side and the second side is between 0.50-0.99.
  • the concentration distribution rules of the zirconium element shown in the above-mentioned FIG. 19 and FIG. 20 are specific implementation methods and do not constitute a limitation on the scope of the embodiments of the present application.
  • the concentration change of the zirconium element in the ferroelectric layer in the thickness direction can also be: first increase, then decrease, then increase, then decrease, or it can also be: first decrease, then increase, then decrease , and then increase.
  • the concentration change of the zirconium element in the ferroelectric layer in the thickness direction may not be completely consistent with the smooth curve as shown in FIGS. 19 and 20 .
  • the concentration of zirconium element in the ferroelectric layer can show an overall "opening upward” or “opening downward” curve change, and a certain degree of concentration fluctuation is allowed within a smaller range.
  • Persons skilled in the art can easily think of other implementation methods according to the inventive concept of this application, "By controlling the concentration distribution of doping elements in the thickness direction of the ferroelectric layer, the distribution of the ferroelectric phase crystal structure in the ferroelectric layer is controlled.” No creative work is required. These implementation methods all fall within the protection scope of this application.
  • the “other direction” here may be a direction perpendicular to the stacking direction of the first electrode and the second electrode. Embodiments obtained based on such a concept also belong to the protection scope of this application.
  • the ratio of the concentration of the doping element to the concentration of the hafnium element exhibits a preset gradient change along the thickness direction of the ferroelectric layer. More specifically, in the thickness direction of the ferroelectric layer, the ratio of the concentration of the doping element to the concentration of the hafnium element is the same from the preset position to the first side of the ferroelectric layer and the second side of the ferroelectric layer. gradient changes.
  • the ratio of the two concentrations gradually increases from the preset position to the first side of the ferroelectric layer, and also gradually increases from the preset position to the first side of the ferroelectric layer; or, the ratio of the two concentrations, It gradually decreases from the preset position toward the first side of the ferroelectric layer, and also gradually decreases from the preset position toward the first side of the ferroelectric layer.
  • the ferroelectric phase crystal structure in the ferroelectric layer is controlled by controlling the concentration distribution of the ratio of the concentration of the doping element to the concentration of the hafnium element in the thickness direction of the ferroelectric layer. distribution in.
  • Figure 21 shows a schematic diagram of the concentration distribution of zirconium element and hafnium element in the ferroelectric layer of the present application obtained by using X-ray energy spectroscopy (EDS) analysis method.
  • EDS X-ray energy spectroscopy
  • FIG. 21 shows the change in the concentration ratio of zirconium element and hafnium element in the ferroelectric layer along the thickness direction of the ferroelectric layer. It can be seen that the ratio of the two increases first, then decreases, and then increases again as a whole. Big, last minus Small changing patterns.
  • Embodiments of the ferroelectric layer conceived based on the changing law of the concentration ratio of the hafnium element and the zirconium element also belong to the protection scope of the present application.
  • the thickness of the first electrode and the second electrode of the ferroelectric layer in the stacking direction is 0.5nm-50nm.
  • this application controls the distribution of the concentration of the doping element, the concentration of the hafnium element and/or the ratio of the two concentrations in the thickness direction of the ferroelectric layer or other directions to control the formation of the first side in the ferroelectric layer. and a continuously distributed ferroelectric phase crystal structure between the second side.
  • the grain boundary content in the ferroelectric layer and the stratified distribution phenomenon between crystal phases can be reduced, thereby reducing the migration channels of oxygen ions, inhibiting the migration of oxygen ions, reducing the generation of oxygen vacancies, and thus slowing down or even avoiding the above extremes.
  • Chemical fatigue, imprinting effect and breakdown phenomenon make ferroelectric capacitors have better durability performance.
  • the ferroelectric capacitor of the present application does not have the problem of difficulty in ferroelectric crystallization, and when the thickness of the ferroelectric layer is reduced to 10 nm or less, the ferroelectric capacitor also Can show better durability performance and ferroelectricity.
  • embodiments of the present application provide a method of forming the above-mentioned ferroelectric capacitor, and FIG. 22 shows an achievable flow chart of the forming method. Among them, the specific steps are as follows:
  • Step S01 Form a first electrode and a second electrode on one side of the substrate, and the first electrode and the second electrode are stacked.
  • Step S02 Form a ferroelectric layer between the first electrode and the second electrode.
  • the ferroelectric layer includes a doping element and a hafnium oxide-based material; the concentration of the doping element is preset along the stacking direction of the first electrode and the second electrode. Gradient changes. It should be noted that the above steps S01 and S02 do not limit the order of forming the first electrode, the second electrode and the ferroelectric formation. For example, when fabricating a planar ferroelectric capacitor structure on a substrate, a first electrode, a ferroelectric layer and a second electrode can be sequentially prepared on one side of the substrate in a direction perpendicular to the substrate.
  • the ferroelectric layer can be crystallized to form ferroelectric.
  • the phase crystal structure is distributed continuously between the first side and the second side of the ferroelectric layer as much as possible, showing a distribution effect that is close to penetrating the ferroelectric layer, or in other words, a distribution effect that is close to connecting the first electrode and the second electrode. Even if the ferroelectric phase crystal structure contains almost no other phase crystal structures, there is no layered distribution phenomenon between crystal phases, and it has relatively high integrity.
  • the ferroelectric layer can be crystallized to form a completely continuously distributed ferroelectric phase crystal structure.
  • Such a ferroelectric layer can make the ferroelectric capacitor have better durability and ferroelectricity.
  • the thickness of the ferroelectric layer is thinned to 10nm and below, it can also show better ferroelectricity and durability.
  • magnetron sputtering can be used for deposition, or a thin film deposition method can be used, such as chemical vapor deposition (CVD), physical vapor deposition (physical vapor deposition) deposition (PVD), or atomic layer deposition (ALD) and other deposition processes.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • the prepared first electrode, second electrode or ferroelectric layer can be relatively uniform, have high flatness and high conformability, that is, the shape and surface flatness of each layer structure are basically the same.
  • the specific steps when forming the ferroelectric layer are as follows:
  • Step S021 Use doping elements and hafnium oxide-based materials to deposit a ferroelectric layer on the first electrode or the second electrode,
  • the concentration of the doping element in the ferroelectric layer exhibits a first preset gradient change in the stacking direction of the first electrode and the second electrode.
  • the concentration of the hafnium element exhibits a second preset gradient change along the stacking direction of the first electrode and the second electrode, wherein the first preset gradient change corresponds to the second preset gradient change.
  • Step S022 Perform a crystallization process on the ferroelectric layer deposited in step S021 to form a continuous ferroelectric phase crystal structure in the ferroelectric layer between the first side and the second side of the ferroelectric layer.
  • the concentration distribution of the doping element (or hafnium element) in the ferroelectric layer is controlled, so that the ferroelectric phase crystal structure formed by crystallization in the ferroelectric layer is as much as possible in the ferroelectric layer.
  • the ferroelectric phase crystal structure formed by crystallization in the ferroelectric layer is as much as possible in the ferroelectric layer.
  • There is a continuous distribution between the first side and the second side even if the ferroelectric phase crystal structure almost does not include other phase crystal structures, there is no layered distribution phenomenon between crystal phases.
  • the ferroelectric layer can be crystallized to form a completely continuously distributed ferroelectric phase crystal structure.
  • the concentration X of the zirconium element can first be controlled to be higher, and then the gradient The proportion of the controlled concentration Alternatively, the concentration X of the zirconium element is first controlled to be low, then the gradient-controlled concentration
  • high-temperature annealing may be used to crystallize the ferroelectric layer deposited in step S021.
  • the ferroelectric layer formed by the method provided in this application has a ferroelectric phase crystal structure that exhibits a distribution effect that is close to penetrating the ferroelectric layer, or that is, a distribution effect that is close to connecting the first electrode and the second electrode.
  • the ferroelectric phase crystal structure contains almost no other phase crystal structures, and there is no layered distribution phenomenon between crystal phases, so it has relatively high integrity. In this way, the migration channels of oxygen ions can be reduced, the migration of oxygen ions can be inhibited, the generation of oxygen vacancies can be reduced, polarization fatigue, imprinting effects and breakdown phenomena can be slowed down or even avoided, making the ferroelectric capacitor have better durability.
  • the ferroelectric phase crystal structure distributed in this way means that its initial content in the ferroelectric layer is relatively high, and correspondingly, the initial content of other phase crystal structures (such as antiferroelectric phase crystal structure and dielectric phase crystal structure) lower. Since the higher the crystal structure of the ferroelectric phase, it means that during the polarization flipping process, the content of the crystal structure of the dielectric phase increases more slowly, the slower the polarization fatigue occurs, and the slower the residual polarization intensity decreases. After the number of flips, the smaller the degree of polarization fatigue, the greater the residual polarization intensity. Therefore, such a ferroelectric layer has better ferroelectricity.
  • the ferroelectric capacitor shown in Figure 22 can be formed through a back end of line (BEOL) process. Then, the control circuit for controlling the ferroelectric capacitor can be produced through a back end of line (BEOL) process. It is fabricated on the substrate using a front end of line (FEOL) process. That is to say, first through the front-end process in A control circuit is formed on the substrate, and the ferroelectric capacitor is manufactured using subsequent processes and the method shown in Figure 22.
  • BEOL back end of line
  • FEOL front end of line
  • Figure 23 shows a process structure diagram of a memory unit in a ferroelectric field-effect transistor memory (ferroelectric field-effect-transistor, FeFET) in a ferroelectric memory.
  • the memory cell includes a first doped region 100a and a second doped region 100b formed in the substrate 100, a channel region 100c located between the first doped region 100a and the second doped region 100b, a The ferroelectric layer 03 on the channel region 100c, and the gate electrode 06 formed on a side of the ferroelectric layer 03 away from the substrate 100.
  • the substrate 100 may be a semiconductor substrate, such as a P-type silicon substrate.
  • a first doped region 100a and a second doped region 100b with the same doping type can be formed through a doping process.
  • the first doped region 100a and the second doped region 100b can both be N. type.
  • One of the first doped region 100a and the second doped region 100b forms a source (Source), and the other doped region forms a drain (Drain).
  • the distribution of crystal phases and the distribution of elements in the ferroelectric layer 03 please refer to the above structural description of the ferroelectric capacitor of the present application, and will not be described again here.
  • the gate 06 can be made of poly-Si (p-Si, polysilicon), or can be made of metal materials.
  • the gate electrode 06 is made of metal material
  • the structure shown in Figure 23 can be called a metal-isolation passivation-ferroelectric-isolation passivation-semiconductor (metal-passivation-ferroelectric-passivation-semiconductor, MPFPS) memory cell structure.
  • MPFPS metal-passivation-ferroelectric-passivation-semiconductor
  • the memory cell shown in FIG. 23 also includes a word line WL, a bit line BL and a source line SL.
  • the gate electrode 06 is electrically connected to the word line WL
  • the first doped region 100a is electrically connected to the bit line BL
  • the second doped region 100a is electrically connected to the bit line BL.
  • the doped region 100b is electrically connected to the source line SL.
  • Figure 24 provides a circuit diagram of the memory array 310 including the memory cells shown in Figure 23, and in the memory array 310 shown in Figure 23, four memory cells are exemplarily provided, namely memory unit 401, memory unit 402. Memory unit 403 and memory unit 404, and the word line WL extends along the X direction. Furthermore, the gates of multiple memory cells arranged along the X direction are electrically connected to the same word line WL. In addition, the bit line BL extends along the Y direction perpendicular to the X direction. In this case, the first doped regions 100a of the plurality of memory cells arranged along the Y direction are electrically connected to the same bit line BL.
  • the source line SL extends along the Y direction perpendicular to the X direction, and the second doped regions 100b of the plurality of memory cells arranged along the Y direction are electrically connected to the same source line SL.
  • This application also provides a method for forming the memory unit shown in FIG. 23, and FIG. 25 shows an achievable flow chart of the formation method. Among them, the specific steps are as follows:
  • Step S11 forming a first doped region and a second doped region in the substrate, forming a ferroelectric layer and a gate electrode on the substrate, and the ferroelectric layer is formed in the first doped region and the second doped region On the channel region between them, the gate is formed on the side of the ferroelectric layer away from the substrate.
  • the ferroelectric layer includes doping elements and hafnium oxide-based materials.
  • the concentration of the doping element is controlled to change in a preset gradient along the stacking direction of the ferroelectric layer and the gate electrode.
  • the concentration of the doping element is controlled to exhibit the same gradient change from a preset position to a first side close to the gate and a second side far away from the gate, and the preset position is a position in the ferroelectric layer.
  • magnetron sputtering method can be used for deposition, or thin film deposition method can be used.
  • deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).
  • Step S12 Perform annealing treatment on the gate electrode and the ferroelectric layer to form a ferroelectric phase crystal structure in the ferroelectric layer.
  • the ferroelectric phase crystal structure is continuously distributed on a first side close to the gate electrode and a second side far away from the gate electrode. between sides.

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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

La présente demande concerne une mémoire ferroélectrique, son procédé de formation et un dispositif électronique. La mémoire ferroélectrique comprend : un substrat et une pluralité de cellules de stockage formées sur le substrat; chaque cellule de stockage comprend un condensateur ferroélectrique; le condensateur ferroélectrique comprend une première électrode et une seconde électrode qui sont empilées, et une couche ferroélectrique formée entre la première électrode et la seconde électrode et servant de support de stockage; la couche ferroélectrique comprend un élément dopé et un matériau à base d'oxyde de hafnium; la concentration de l'élément dopé présente un changement de gradient prédéfini le long d'une direction d'empilement de la première électrode et de la seconde électrode. Par conséquent, des canaux de migration d'ions oxygène peuvent être réduits, la migration d'ions oxygène est inhibée, la génération de lacunes d'oxygène est réduite, et la fatigue de polarisation, un effet d'impression et un phénomène de claquage sont atténués ou même évités, de telle sorte que le condensateur ferroélectrique présente de bonnes performances d'endurance, et la mémoire ferroélectrique comprenant les condensateurs ferroélectriques présente de bonnes performances de stockage.
PCT/CN2023/092103 2022-05-09 2023-05-04 Mémoire ferroélectrique, son procédé de formation et dispositif électronique WO2023216965A1 (fr)

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Citations (5)

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Publication number Priority date Publication date Assignee Title
CN101752237A (zh) * 2008-12-16 2010-06-23 国际商业机器公司 在半导体器件中形成高k栅极叠层的方法
US20140070289A1 (en) * 2012-09-10 2014-03-13 Kabushiki Kaisha Toshiba Ferroelectric memory and manufacturing method thereof
US20190074295A1 (en) * 2017-09-05 2019-03-07 Namlab Ggmbh Ferroelectric Memory Cell for an Integrated Circuit
CN110504274A (zh) * 2018-05-18 2019-11-26 瑞萨电子株式会社 半导体装置及其制造方法
CN110957359A (zh) * 2018-09-27 2020-04-03 台湾积体电路制造股份有限公司 半导体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101752237A (zh) * 2008-12-16 2010-06-23 国际商业机器公司 在半导体器件中形成高k栅极叠层的方法
US20140070289A1 (en) * 2012-09-10 2014-03-13 Kabushiki Kaisha Toshiba Ferroelectric memory and manufacturing method thereof
US20190074295A1 (en) * 2017-09-05 2019-03-07 Namlab Ggmbh Ferroelectric Memory Cell for an Integrated Circuit
CN110504274A (zh) * 2018-05-18 2019-11-26 瑞萨电子株式会社 半导体装置及其制造方法
CN110957359A (zh) * 2018-09-27 2020-04-03 台湾积体电路制造股份有限公司 半导体装置

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