WO2023216061A1 - 接收机、射频收发器和终端 - Google Patents

接收机、射频收发器和终端 Download PDF

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Publication number
WO2023216061A1
WO2023216061A1 PCT/CN2022/091702 CN2022091702W WO2023216061A1 WO 2023216061 A1 WO2023216061 A1 WO 2023216061A1 CN 2022091702 W CN2022091702 W CN 2022091702W WO 2023216061 A1 WO2023216061 A1 WO 2023216061A1
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signal
phase
amplifier
differential circuit
intermediate frequency
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PCT/CN2022/091702
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English (en)
French (fr)
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邓至贤
钱慧珍
罗讯
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华为技术有限公司
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Priority to PCT/CN2022/091702 priority Critical patent/WO2023216061A1/zh
Publication of WO2023216061A1 publication Critical patent/WO2023216061A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits

Definitions

  • the present application relates to the field of integrated circuit technology, and in particular to a receiver, radio frequency transceiver and terminal.
  • the working frequency of wireless communication systems has become higher and higher. Come higher and higher.
  • phased-array technology is widely used in radar, communications and other wireless communication systems, such as phased array receivers.
  • the traditional phased array receiver includes vector synthesis phase shifter, variable gain amplifier (Variable gain amplifier, VGA) and mixer.
  • Vector synthesis phase shifters adjust signals received through different antennas to the same phase and add them to enhance the signal-to-noise ratio of the received signal mixer.
  • Variable gain amplifiers can be used to achieve amplitude and phase control of the signals on each receive path.
  • the mixer downmixes the RF signal to baseband for signal demodulation.
  • the vector synthesis phase shifter and variable gain amplifier work independently, resulting in increased power consumption in the circuit where the receiver is located.
  • this application provides a receiver, a radio frequency transceiver and a terminal, which can use existing devices in the receiver to replace the traditional vector synthesis phase shifter to adjust the phase of the received radio frequency signal.
  • the present application provides a receiver, which includes a first adjustable radio frequency amplifier, a second adjustable radio frequency amplifier, a first in-phase mixer, a first quadrature mixer, a second quadrature mixer, and a second quadrature mixer. a mixer, a second in-phase mixer, a first adder and subtractor, and a second adder and subtractor.
  • the receiver is used to receive radio frequency signals.
  • the radio frequency signal is amplified by the first adjustable radio frequency amplifier and then a first radio frequency amplified signal is output.
  • the radio frequency signal is amplified by the second adjustable radio frequency amplifier and then a second radio frequency amplified signal is output.
  • the first radio frequency amplified signal is mixed by the first in-phase mixer and outputs a first in-phase intermediate frequency signal, and is mixed by the first quadrature mixer and then outputs a first quadrature intermediate frequency signal;
  • the second radio frequency amplified signal is mixed by the first quadrature mixer and then outputs a first quadrature intermediate frequency signal.
  • the two quadrature mixers output a second quadrature intermediate frequency signal after mixing, and the second in-phase mixer outputs a second in-phase intermediate frequency signal after mixing.
  • the first in-phase intermediate frequency signal and the second quadrature intermediate frequency signal are selectively added or subtracted through the first adder and subtractor and then the first composite signal is output; the first quadrature intermediate frequency signal and the second in-phase intermediate frequency signal are passed through the second The adder and subtractor performs selectable addition or subtraction and then outputs the second composite signal.
  • the working principle of the vector synthesis phase shifter 1012 is to achieve the phase shifting function by changing the ratio of two orthogonal signals.
  • the first adder-subtractor receives a quadrature first in-phase intermediate frequency signal and a second quadrature intermediate frequency signal. Furthermore, since the radio frequency signal forming the first in-phase intermediate frequency signal is amplified by the first adjustable radio frequency amplifier, the radio frequency signal forming the second quadrature intermediate frequency signal is amplified by the second adjustable radio frequency amplifier. Therefore, by adjusting the gains of the first adjustable radio frequency amplifier and the second adjustable radio frequency amplifier, on the basis of adjusting the amplitudes of the first in-phase intermediate frequency signal and the second quadrature intermediate frequency signal, the quadrature first in-phase intermediate frequency signal can be adjusted. The ratio of the intermediate frequency signal and the second orthogonal intermediate frequency signal can replace the existing vector synthesis phase shifter to realize the phase shifting function.
  • the second adder-subtractor receives the orthogonal first quadrature intermediate frequency signal and the second in-phase intermediate frequency signal. Furthermore, since the radio frequency signal forming the first quadrature intermediate frequency signal is amplified by the first adjustable radio frequency amplifier, the radio frequency signal forming the second in-phase intermediate frequency signal is amplified by the second adjustable radio frequency amplifier. Therefore, by adjusting the gains of the first adjustable radio frequency amplifier and the second adjustable radio frequency amplifier, on the basis of adjusting the amplitudes of the first quadrature intermediate frequency signal and the second in-phase intermediate frequency signal, the orthogonal first quadrature intermediate frequency can be adjusted. The ratio of the signal to the second in-phase intermediate frequency signal, thereby replacing the existing vector synthesis phase shifter to achieve the phase shifting function.
  • this application can utilize the existing first adjustable RF amplifier, second adjustable RF amplifier, first in-phase mixer, first quadrature mixer, second quadrature mixer, second The in-phase mixer, the first adder and subtractor and the second adder and subtractor replace the traditional vector synthesis phase shifter to adjust the phase of the received radio frequency signal, saving the layout area and power consumption of the receiver.
  • the present application will realize the first adjustable radio frequency amplifier, the second adjustable radio frequency amplifier, the first in-phase mixer, the first quadrature mixer, and the second frequency mixing function.
  • the quadrature mixer, the second in-phase mixer, the first adder and subtractor and the second adder and subtractor are integrated into one, which greatly improves the integration of the receiver, thus reducing the parasitic capacitance and parasitic inductance in the receiver.
  • the first adjustable radio frequency amplifier and the second adjustable radio frequency amplifier can also adjust the amplitude of the radio frequency signal.
  • the first adder and subtractor can selectively add or subtract the first in-phase intermediate frequency signal and the second quadrature intermediate frequency signal through vector synthesis;
  • the second adder and subtractor can selectively add or subtract the first in-phase intermediate frequency signal and the second quadrature intermediate frequency signal through vector synthesis.
  • a quadrature intermediate frequency signal and a second in-phase intermediate frequency signal are added or subtracted.
  • the first in-phase intermediate frequency signal and the first quadrature intermediate frequency signal are amplified by the first adjustable radio frequency amplifier, and the second quadrature intermediate frequency signal and the second in-phase intermediate frequency signal are amplified by the second adjustable radio frequency amplifier.
  • the vector synthesis result of the first in-phase intermediate frequency signal and the second quadrature intermediate frequency signal is the same as the first quadrature intermediate frequency signal and the second quadrature intermediate frequency signal.
  • the amplitude of the resultant vector synthesis of in-phase IF signals is always the same.
  • the first adjustable radio frequency amplifier amplifies the radio frequency signal with an adjustable first gain; the second adjustable radio frequency amplifier amplifies the radio frequency signal with an adjustable second gain.
  • the number of bits of the first gain and the second gain can be designed according to the actual required amplitude and phase. Because the bit numbers of the first gain and the second gain themselves contain multiple states. Therefore, when adjusting the phase of the radio frequency signal by adjusting the magnitude of the first gain and the second gain, there is no need to additionally increase the number of bits of the control circuit.
  • the number of bits of the first gain is 3, including 8 states such as 000, 001, 010, 011, 100, 101, 110, and 111.
  • the number of bits of the second gain is 3, including 8 states such as 000, 001, 010, 011, 100, 101, 110, and 111.
  • the first radio frequency amplified signal may be mixed with the first local oscillator signal through a first in-phase mixer, and then a first in-phase intermediate frequency signal may be output.
  • a first quadrature intermediate frequency signal is output.
  • a second orthogonal intermediate frequency signal is output.
  • a second in-phase intermediate frequency signal is output.
  • the first local oscillator signal is orthogonal to the second local oscillator signal, so that the first in-phase intermediate frequency signal is orthogonal to the second orthogonal intermediate frequency signal, and the first orthogonal intermediate frequency signal is orthogonal to the second in-phase intermediate frequency signal;
  • the first The phase of the in-phase intermediate frequency signal is the same as the phase of the second in-phase intermediate frequency signal, and the phase of the first quadrature intermediate frequency signal is the same as the phase of the second quadrature intermediate frequency signal.
  • the receiver further includes a control circuit.
  • the control circuit includes a control code generator.
  • the control code generator is configured to input a first gain to the first adjustable radio frequency amplifier and input a second gain to the second adjustable radio frequency amplifier. gain.
  • the control circuit can use the first gain and the second gain of the output to enable the first adjustable radio frequency amplifier and the second adjustable radio frequency amplifier to have a variable gain function to adjust the amplitude and phase of the radio frequency signal.
  • control circuit further includes a symbol code generator, which is used to input the first digital signal and the third digital signal to the first adder and subtractor, and to input the second digital signal to the second adder and subtractor. and a fourth digital signal.
  • the first digital signal is used to determine whether the phase of the first in-phase intermediate frequency signal is positive or negative;
  • the second digital signal is used to determine whether the phase of the first quadrature intermediate frequency signal is positive or negative;
  • the third digital signal is used to determine whether the phase of the first quadrature intermediate frequency signal is positive or negative.
  • the phase of the two orthogonal intermediate frequency signals is positive or negative;
  • fourth digital signal is used to determine whether the phase of the second in-phase intermediate frequency signal is positive or negative.
  • the first digital signal is 1 and the phase of the first in-phase intermediate frequency signal is positive; the first digital signal is 0 and the phase of the first in-phase intermediate frequency signal is negative; the second digital signal is 1 and the first quadrature intermediate frequency signal is negative.
  • the phase of the signal is positive; the second digital signal is 0, and the phase of the first quadrature intermediate frequency signal is negative; the third digital signal is 1, and the phase of the second quadrature intermediate frequency signal is positive; the third digital signal is 0, and the phase of the second quadrature intermediate frequency signal is positive.
  • the phase of the quadrature intermediate frequency signal is negative; the fourth digital signal is 1, and the phase of the second in-phase intermediate frequency signal is positive; the fourth digital signal is 0, and the phase of the second in-phase intermediate frequency signal is negative.
  • the first adder-subtractor compares a first in-phase intermediate frequency signal with a positive/negative phase and a second quadrature intermediate frequency signal with a positive/negative phase. Perform vector synthesis to obtain the first synthesized signal. It can also be said that the first adder and subtractor adds or subtracts the first in-phase intermediate frequency signal with a positive phase and the second quadrature intermediate frequency signal with a positive phase, or the first adder and subtractor adds or subtracts the first in-phase intermediate frequency signal with a negative phase. The in-phase intermediate frequency signal and the second orthogonal intermediate frequency signal with a positive phase are added or subtracted to obtain a first composite signal.
  • the second adder and subtractor performs vector synthesis on the first quadrature intermediate frequency signal with positive/negative phase and the second in-phase intermediate frequency signal with positive/negative phase to obtain a second synthesized signal.
  • the second adder and subtractor adds or subtracts the first quadrature intermediate frequency signal with a positive phase and the second in-phase intermediate frequency signal with a positive phase, or the second adder and subtractor adds or subtracts the first quadrature intermediate frequency signal with a negative phase.
  • the quadrature intermediate frequency signal is added or subtracted from the second in-phase intermediate frequency signal with a positive phase to obtain a second composite signal.
  • the receiver also includes differential circuits and phase shifters.
  • the phase shifter is coupled between the first adder and subtractor and the differential circuit for 90° phase shifting of the first composite signal; or the phase shifter is coupled between the second adder and subtractor and the differential circuit for performing 90° phase shift on the first composite signal.
  • the second composite signal is phase shifted by 90°.
  • the differential circuit is used to add the second composite signal and the phase-shifted first composite signal, or the first composite signal and the phase-shifted second composite signal, to filter out the first composite signal and the second composite signal. image interference signal.
  • the phase shifter can be coupled to the positive input end of the differential circuit; or the phase shifter can also be coupled to the negative input end of the differential circuit. If the phase shifter is coupled to the first adder and subtractor for phase shifting the first composite signal, and the negative input terminal of the differential circuit is coupled to the phase shifter, and the positive input terminal is coupled to the second adder and subtractor, then it can be calculated according to Quadrant control codes and image suppression modes determine a set of truth tables.
  • phase shifter is coupled to the first adder and subtractor for phase shifting the first composite signal, and the positive input terminal of the differential circuit is coupled to the phase shifter, and the negative input terminal is coupled to the second adder and subtractor, then it can be Determine another set of truth tables based on the quadrant control code and image suppression mode. If the phase shifter is coupled to the second adder and subtractor for phase shifting the second composite signal, and the negative input terminal of the differential circuit is coupled to the phase shifter, and the positive input terminal is coupled to the first adder and subtractor, then it can Another set of truth tables is determined based on the quadrant control code and image suppression mode.
  • phase shifter is coupled to the second adder and subtractor for phase shifting the second composite signal, and the positive input terminal of the differential circuit is coupled to the phase shifter, and the negative input terminal is coupled to the first adder and subtractor, then Another set of truth tables is determined based on the quadrant control code and image suppression mode. Afterwards, it is determined that the first digital signal, the second digital signal, the third digital signal and the fourth digital signal are 0 or 1 according to the data in the truth table.
  • the radio frequency signal includes a first radio frequency signal and a second radio frequency signal, and the first radio frequency signal and the second radio frequency signal are mirror symmetrical with respect to the first local oscillator signal or the second local oscillator signal; the first composite signal and The second synthesized signals each include a first signal and a second signal; the first signal is obtained by amplifying and mixing the first radio frequency signal, and the second signal is obtained by amplifying and mixing the second radio frequency signal.
  • the first signal is a useful signal and the second signal is an image interference signal; or the first signal is an image interference signal and the second signal is a useful signal.
  • the first digital signal, the second digital signal, the third digital signal and the fourth digital signal are determined, and based on the first digital signal, the second digital signal, the third digital signal and a fourth digital signal, filtering out the first signal or the second signal to solve the image interference problem.
  • the quadrant where the retained second signal and the first signal are located can also be selected based on the first digital signal, the second digital signal, the third digital signal and the fourth digital signal. It can also be said that the retained third signal is selected. The phase of the second signal and the first signal.
  • control code generator is coupled to the symbolic code generator.
  • symbol code generator is also used to receive the image suppression control code and the quadrant control code sent by the control code generator, and according to the quadrant control code, the image suppression control code, the phase shifter and the first adder and subtractor and the second adder and subtractor.
  • the coupling relationship, and the coupling relationship between the phase shifter and the input end of the differential circuit, the first digital signal and the third digital signal are input to the first adder and subtractor, and the second digital signal and the fourth digital signal are input to the second adder and subtractor ( It can also be said that the above truth table is determined).
  • the quadrant control code is used to characterize the quadrant where the useful signal is located; the image suppression mode is used to characterize the first signal as a useful signal or the second signal as a useful signal.
  • the symbol code generator generates a signal based on the quadrant control code, the image suppression control code, the coupling relationship between the phase shifter and the first adder and subtractor and the second adder and subtractor, and the coupling relationship between the phase shifter and the input end of the differential circuit.
  • the first adder and subtractor inputs the first digital signal and the third digital signal
  • the method of inputting the second digital signal and the fourth digital signal to the second adder and subtractor may include the following two methods:
  • the symbol code generator includes a first switch, a second switch, a third switch, a fourth switch, a first inverter and a second inverter; the first adder and subtractor includes a first differential circuit and a second Differential circuit.
  • the symbol code generator is used to generate a first initial digital signal; the first switch is connected in parallel with the second switch; the first switch is used to receive the first in-phase intermediate frequency signal and the first initial digital signal; the second switch is coupled to the first inverter , used to receive the first in-phase intermediate frequency signal and the inverted first initial digital signal.
  • the symbol code generator is also used to generate a third initial digital signal; the third switch is connected in parallel with the fourth switch; the third switch is used to receive the second quadrature intermediate frequency signal and the third initial digital signal; the fourth switch is inverted with the second
  • the device is coupled to receive the second orthogonal intermediate frequency signal and the inverted third initial digital signal.
  • the output sides of the first switch and the second switch are coupled to the input side of the first differential circuit, the output sides of the third switch and the fourth switch are coupled to the input side of the second differential circuit, and the first differential circuit and the second differential circuit are coupled to each other.
  • the output sides are both coupled to the input side of the differential circuit.
  • the symbol code generator also includes a fifth switch, a sixth switch, a seventh switch, an eighth switch, a third inverter and a fourth inverter; the second adder and subtractor includes a third differential circuit and a fourth differential circuit.
  • the symbol code generator is used to generate a second initial digital signal; the fifth switch is connected in parallel with the sixth switch; the fifth switch is used to receive the first quadrature intermediate frequency signal and the second initial digital signal; the sixth switch is coupled to the third inverter , used to receive the first orthogonal intermediate frequency signal and the inverted second initial digital signal.
  • the symbol code generator is also used to generate a fourth initial digital signal; the seventh switch is connected in parallel with the eighth switch; the seventh switch is used to receive the second in-phase intermediate frequency signal and the fourth initial digital signal; the eighth switch and the fourth inverter Coupling, used to receive the second in-phase intermediate frequency signal and the inverted fourth initial digital signal.
  • the output sides of the fifth switch and the sixth switch are coupled with the input side of the third differential circuit, the output sides of the seventh switch and the eighth switch are coupled with the input side of the fourth differential circuit, and the third differential circuit and the fourth differential circuit are coupled with each other. The output sides are both coupled to the input side of the differential circuit.
  • the specific processes between the symbol code generator and the first adder and subtractor and the second adder and subtractor may include the following to achieve the first in-phase intermediate frequency signal and the second quadrature intermediate frequency signal through the first adder and subtractor. Selectable addition or subtraction is performed, and the first quadrature intermediate frequency signal and the second in-phase intermediate frequency signal are optionally added or subtracted through the second adder and subtractor:
  • the first switch is coupled to the positive input terminal of the first differential circuit and the second switch is coupled to the negative input terminal of the first differential circuit
  • the first initial digital signal input to the first switch and the second switch is 1.
  • the first switch can be controlled to be turned on and the second switch to be turned off.
  • the first in-phase intermediate frequency signal is input to the positive input end of the first differential circuit through the first switch and is passed from the first switch to the positive input end of the first differential circuit.
  • a differential circuit output if the required first digital signal is 0, the first switch can be controlled to be turned off and the second switch turned on, and the first in-phase intermediate frequency signal is input to the negative input of the first differential circuit through the second switch. terminal, the first differential circuit inverts the first in-phase intermediate frequency signal and outputs it.
  • the first switch is coupled to the negative input terminal of the first differential circuit and the second switch is coupled to the positive input terminal of the first differential circuit
  • the first initial digital signal input to the first switch and the second switch is 0. If the required first digital signal is 1, the first switch can be controlled to be turned off and the second switch turned on.
  • the first in-phase intermediate frequency signal is input to the positive input end of the first differential circuit through the second switch and is passed from the second switch to the positive input end of the first differential circuit.
  • a differential circuit output if the required first digital signal is 0, the first switch can be controlled to be turned on and the second switch turned off, and the first in-phase intermediate frequency signal is input to the negative input of the first differential circuit through the first switch terminal, the first differential circuit inverts the first in-phase intermediate frequency signal and outputs it.
  • the third switch is coupled to the positive input terminal of the second differential circuit, and the fourth switch is coupled to the negative input terminal of the second differential circuit, then the third initial digital signal input to the third switch and the fourth switch is 1. If the required third digital signal is 1, the third switch can be controlled to be turned on and the fourth switch to be turned off. The second quadrature intermediate frequency signal is input to the positive input end of the second differential circuit through the third switch and is passed from the third switch to the positive input terminal of the second differential circuit. Two differential circuit outputs; if the required third digital signal is 0, the third switch can be controlled to be turned off and the fourth switch turned on, and the second orthogonal intermediate frequency signal is input to the negative input of the second differential circuit through the fourth switch. terminal, the second differential circuit inverts the second orthogonal intermediate frequency signal and outputs it.
  • the third switch is coupled to the negative input terminal of the second differential circuit and the fourth switch is coupled to the positive input terminal of the second differential circuit
  • the third initial digital signal input to the third switch and the fourth switch is 0. If the required third digital signal is 1, the third switch can be controlled to be turned off and the fourth switch turned on.
  • the second quadrature intermediate frequency signal is input to the positive input end of the second differential circuit through the fourth switch and is passed from the fourth switch to the positive input terminal of the second differential circuit.
  • Two differential circuit outputs if the required third digital signal is 0, the third switch can be controlled to be turned on, the fourth switch can be turned off, and the second orthogonal intermediate frequency signal is input to the negative input of the second differential circuit through the third switch terminal, the second differential circuit inverts the second orthogonal intermediate frequency signal and outputs it.
  • a first composite signal is obtained by vector summing the signals output by the first differential circuit and the second differential circuit.
  • the second initial digital signal received by the fifth switch and the sixth switch is 1. If the required second digital signal is 1, the fifth switch can be controlled to be turned on and the sixth switch to be turned off. The first quadrature intermediate frequency signal is input to the positive input end of the third differential circuit through the fifth switch and is passed from the Three differential circuit outputs; if the required second digital signal is 0, the fifth switch can be controlled to be off and the sixth switch to be on, and the first orthogonal intermediate frequency signal is input to the negative input of the third differential circuit through the sixth switch. terminal, the third differential circuit inverts the first orthogonal intermediate frequency signal and outputs it.
  • the second initial digital signal received by the fifth switch and the sixth switch is 0. If the required second digital signal is 1, the fifth switch can be controlled to be turned off and the sixth switch turned on. The first quadrature intermediate frequency signal is input to the positive input end of the third differential circuit through the sixth switch and is passed from the sixth switch to the positive input end of the third differential circuit. Three differential circuit outputs; if the required second digital signal is 0, the fifth switch can be controlled to be turned on, the sixth switch can be turned off, and the first orthogonal intermediate frequency signal is input to the negative input of the third differential circuit through the fifth switch. terminal, the third differential circuit inverts the first orthogonal intermediate frequency signal and outputs it.
  • the fourth initial digital signal received by the seventh switch and the eighth switch is 1. If the required fourth digital signal is 1, the seventh switch can be controlled to be turned on and the eighth switch to be turned off. The second in-phase intermediate frequency signal is input to the positive input end of the fourth differential circuit through the seventh switch and is passed from the fourth Differential circuit output; if the required fourth digital signal is 0, the seventh switch can be controlled to be turned off and the eighth switch is turned on, and the second in-phase intermediate frequency signal is input to the negative input end of the fourth differential circuit through the eighth switch. The fourth differential circuit inverts the second in-phase intermediate frequency signal and outputs it.
  • the fourth initial digital signal received by the seventh switch and the eighth switch is 0. If the required fourth digital signal is 1, the seventh switch can be controlled to be turned off and the eighth switch is turned on. The second in-phase intermediate frequency signal is input to the positive input end of the fourth differential circuit through the eighth switch and is passed from the fourth Differential circuit output. If the required fourth digital signal is 0, the seventh switch can be controlled to be turned on and the eighth switch to be turned off. The second in-phase intermediate frequency signal is input to the negative input end of the fourth differential circuit through the seventh switch. The fourth differential circuit The second in-phase intermediate frequency signal is inverted and output.
  • a second composite signal is obtained by vector summing the signals output by the third differential circuit and the fourth differential circuit.
  • the receiver further includes a third adjustable radio frequency amplifier, a fourth adjustable radio frequency amplifier, a fifth adjustable radio frequency amplifier, and a sixth adjustable radio frequency amplifier.
  • the first in-phase intermediate frequency signal amplified by the third adjustable radio frequency amplifier with the third gain and the second orthogonal intermediate frequency signal amplified by the fifth adjustable radio frequency amplifier with the fourth gain are processed through the first adder and subtractor.
  • the first combined signal is output after optional addition or subtraction.
  • the first quadrature intermediate frequency signal amplified by the fourth adjustable radio frequency amplifier with the third gain and the second in-phase intermediate frequency signal amplified by the sixth adjustable radio frequency amplifier with the fourth gain are added and subtracted through the second adder and subtractor.
  • the second composite signal is output after the selected addition or subtraction.
  • the receiver which only includes a first adjustable radio frequency amplifier and a second adjustable radio frequency amplifier, it also includes a third adjustable radio frequency amplifier, a fourth adjustable radio frequency amplifier, a fifth adjustable radio frequency amplifier and a sixth adjustable radio frequency amplifier. , a high variable gain range can be achieved.
  • the third adjustable radio frequency amplifier includes a first sub-amplifier and a second sub-amplifier
  • the fourth adjustable radio frequency amplifier includes a third sub-amplifier and a fourth sub-amplifier
  • the fifth adjustable radio frequency amplifier includes a fifth sub-amplifier and a sixth sub-amplifier.
  • the sixth adjustable radio frequency amplifier includes a seventh sub-amplifier and an eighth sub-amplifier.
  • the symbol code generator includes a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth inverter, and a sixth inverter
  • the first adder and subtractor includes a fifth differential circuit and a sixth Differential circuit.
  • the first AND gate is used to receive the third gain and the first initial digital signal; the output side of the first AND gate is coupled to the first sub-amplifier; the input side of the first sub-amplifier receives the first in-phase intermediate frequency signal, and the output side is coupled to the first sub-amplifier.
  • the second AND gate is used to receive the fourth gain and the third initial digital signal; the output side of the second AND gate is coupled to the fifth sub-amplifier; the input side of the fifth sub-amplifier receives the second orthogonal intermediate frequency signal, and the output side is coupled to the fifth sub-amplifier.
  • the third AND gate is used to receive the fourth gain and the third initial digital signal inverted through the fifth inverter; the output side of the third AND gate is coupled to the sixth sub-amplifier; the input side of the sixth sub-amplifier receives the third initial digital signal. Two quadrature intermediate frequency signals, the output side is coupled with the fifth differential circuit.
  • the fourth AND gate is used to receive the third gain and the first initial digital signal inverted by the sixth inverter; the output side of the fourth AND gate is coupled to the second sub-amplifier; the input side of the second sub-amplifier receives the third A common-phase intermediate frequency signal, the output side is coupled to the sixth differential circuit.
  • the output side of the fifth differential circuit and the output side of the sixth differential circuit are both coupled to the input side of the differential circuit.
  • the symbolic code generator also includes a fifth AND gate, a sixth AND gate, a seventh AND gate, an eighth AND gate, a seventh inverter, and an eighth inverter; the second adder and subtractor includes a seventh differential circuit and a Eight differential circuits.
  • the fifth AND gate is used to receive the third gain and the second initial digital signal; the output side of the fifth AND gate is coupled to the third sub-amplifier; the input side of the third sub-amplifier receives the first orthogonal intermediate frequency signal, and the output side is coupled to the third sub-amplifier. Seven differential circuit couplings.
  • the sixth AND gate is used to receive the fourth gain and the fourth initial digital signal; the output side of the sixth AND gate is coupled to the seventh sub-amplifier; the input side of the seventh sub-amplifier receives the second in-phase intermediate frequency signal, and the output side is connected to Sohu Eighth differential circuit coupling.
  • the seventh AND gate is used to receive the second gain and the fourth initial digital signal inverted by the seventh inverter; the output side of the seventh AND gate is coupled to the eighth sub-amplifier; the input side of the eighth sub-amplifier receives the third Two in-phase intermediate frequency signals, the output side is coupled with the seventh differential circuit.
  • the eighth AND gate is used to receive the first gain and the second initial digital signal inverted by the eighth inverter; the output side of the eighth AND gate is coupled to the fourth sub-amplifier; the input side of the fourth sub-amplifier receives the A quadrature intermediate frequency signal, the output side is coupled to the eighth differential circuit.
  • the output side of the seventh differential circuit and the output side of the eighth differential circuit are both coupled to the input side of the differential circuit.
  • the specific processes between the symbol code generator and the first adder and subtractor and the second adder and subtractor may include the following to achieve the first in-phase intermediate frequency signal and the second quadrature intermediate frequency signal through the first adder and subtractor. Selectable addition or subtraction is performed, and the first quadrature intermediate frequency signal and the second in-phase intermediate frequency signal are optionally added or subtracted through the second adder and subtractor:
  • the first AND gate and the fourth AND gate receive the An initial digital signal is 1. If the required first digital signal is 1, enable can be input to the first sub-amplifier but not to the second sub-amplifier, so that the first sub-amplifier operates normally and the second sub-amplifier does not operate.
  • the first initial digital signal (which can also be said to be the first digital signal) with a third gain sum of 1 is input to the first sub-amplifier through the first AND gate, and the first in-phase intermediate frequency signal is input to the fifth differential signal through the first sub-amplifier.
  • the positive input of the circuit and the output from the fifth differential circuit If the required first digital signal is 0, you can input enable to the second sub-amplifier without inputting enable to the first sub-amplifier, so that the first sub-amplifier does not work and the second sub-amplifier works normally.
  • the first initial digital signal sum of 1 is inverted to obtain the first digital signal of 0.
  • the third gain sum of the first digital signal of 0 is input to the second sub-amplifier through the fourth AND gate.
  • the first in-phase intermediate frequency signal It is input to the negative input end of the sixth differential circuit through the second sub-amplifier, is inverted in the sixth differential circuit, and then output from the sixth differential circuit.
  • the first AND gate and the fourth AND gate receive The first initial digital signal is 0. If the required first digital signal is 1, you can input enable to the second sub-amplifier without inputting enable to the first sub-amplifier, so that the first sub-amplifier does not work and the second sub-amplifier works normally. The first initial digital signal sum of 0 is inverted to obtain the first digital signal of 1. The third gain sum of the first digital signal of 1 is input to the second sub-amplifier through the fourth AND gate.
  • the first in-phase intermediate frequency signal It is input to the positive input terminal of the sixth differential circuit through the second sub-amplifier, and is output from the sixth differential circuit. If the required first digital signal is 0, enable can be input to the first sub-amplifier but not to the second sub-amplifier, so that the first sub-amplifier operates normally and the second sub-amplifier does not operate.
  • the first initial digital signal (which can also be said to be the first digital signal) with a third gain sum of 0 is input to the first sub-amplifier through the first AND gate, and the first in-phase intermediate frequency signal is input to the fifth differential signal through the first sub-amplifier.
  • the negative input terminal of the circuit is inverted in the fifth differential circuit and then output from the fifth differential circuit.
  • the second AND gate and the third AND gate receive the Three initial digital signals are 1. If the required third digital signal is 1, enable can be input to the fifth sub-amplifier but not to the sixth sub-amplifier, so that the fifth sub-amplifier operates normally and the sixth sub-amplifier does not operate.
  • the third initial digital signal (which can also be said to be the third digital signal) with a fourth gain sum of 1 is input to the fifth sub-amplifier through the second AND gate, and the second quadrature intermediate frequency signal is input to the sixth differential signal through the fifth sub-amplifier.
  • the positive input of the circuit and the output from the sixth differential circuit If the required third digital signal is 0, enable can be input to the sixth sub-amplifier but not to the fifth sub-amplifier, so that the fifth sub-amplifier does not work and the sixth sub-amplifier works normally.
  • the third initial digital signal sum of 1 is inverted to obtain a third digital signal of 0.
  • the third digital signal with a fourth gain sum of 0 is input to the sixth sub-amplifier through the third AND gate, and the second quadrature intermediate frequency signal It is input to the negative input end of the fifth differential circuit through the sixth sub-amplifier, is inverted in the fifth differential circuit, and then output from the fifth differential circuit.
  • the second AND gate and the third AND gate receive The third initial digital signal is 0. If the required third digital signal is 1, enable can be input to the sixth sub-amplifier but not to the fifth sub-amplifier, so that the fifth sub-amplifier does not work and the sixth sub-amplifier works normally.
  • the third initial digital signal sum of 0 is inverted to obtain a third digital signal of 1.
  • the third digital signal with a fourth gain sum of 1 is input to the sixth sub-amplifier through the third AND gate, and the second quadrature intermediate frequency signal It is input to the positive input terminal of the fifth differential circuit through the sixth sub-amplifier, and is output from the fifth differential circuit. If the required third digital signal is 0, enable can be input to the fifth sub-amplifier but not to the sixth sub-amplifier, so that the fifth sub-amplifier operates normally and the sixth sub-amplifier does not operate.
  • the third initial digital signal (which can also be said to be the third digital signal) with a fourth gain sum of 0 is input to the fifth sub-amplifier through the second AND gate, and the second quadrature intermediate frequency signal is input to the sixth differential signal through the fifth sub-amplifier.
  • the negative input terminal of the circuit is inverted in the sixth differential circuit and then output from the sixth differential circuit.
  • the first composite signal is obtained by vector summing the signals output by the fifth differential circuit and the sixth differential circuit.
  • the fifth AND gate and the eighth AND gate receive the The second initial digital signal is 1. If the required second digital signal is 1, enable can be input to the third sub-amplifier but not to the fourth sub-amplifier, so that the third sub-amplifier operates normally and the fourth sub-amplifier does not work.
  • the second initial digital signal (which can also be said to be the second digital signal) with a third gain sum of 1 is input to the third sub-amplifier through the fifth AND gate, and the first quadrature intermediate frequency signal is input to the seventh differential signal through the third sub-amplifier.
  • the positive input of the circuit and the output from the seventh differential circuit If the required second digital signal is 0, enable can be input to the fourth sub-amplifier but not to the third sub-amplifier, so that the third sub-amplifier does not work and the fourth sub-amplifier works normally.
  • the second initial digital signal sum of 1 is inverted to obtain a second digital signal of 0.
  • the third gain sum of the second digital signal of 0 is input to the fourth sub-amplifier through the eighth AND gate.
  • the first quadrature intermediate frequency signal It is input to the negative input end of the eighth differential circuit through the fourth sub-amplifier, is inverted in the eighth differential circuit, and then output from the eighth differential circuit.
  • the fifth AND gate and the eighth AND gate receive The second initial digital signal is 0. If the required second digital signal is 1, enable can be input to the fourth sub-amplifier but not to the third sub-amplifier, so that the third sub-amplifier does not work and the fourth sub-amplifier works normally.
  • the second initial digital signal sum of 0 is inverted to obtain a second digital signal of 1.
  • the second digital signal with a third gain sum of 1 is input to the fourth sub-amplifier through the eighth AND gate.
  • the first quadrature intermediate frequency signal It is input to the positive input end of the eighth differential circuit through the fourth sub-amplifier, and is output from the eighth differential circuit. If the required second digital signal is 0, enable can be input to the third sub-amplifier but not to the fourth sub-amplifier, so that the third sub-amplifier operates normally and the fourth sub-amplifier does not operate.
  • the second initial digital signal (which can also be said to be the second digital signal) with a third gain sum of 0 is input to the third sub-amplifier through the fifth AND gate, and the first quadrature intermediate frequency signal is input to the seventh differential signal through the third sub-amplifier.
  • the negative input terminal of the circuit is inverted in the seventh differential circuit and then output from the seventh differential circuit.
  • the sixth AND gate and the seventh AND gate receive Four initial digital signals are 1. If the required fourth digital signal is 1, enable can be input to the seventh sub-amplifier but not to the eighth sub-amplifier, so that the seventh sub-amplifier operates normally and the eighth sub-amplifier does not operate.
  • the fourth initial digital signal (which can also be said to be the fourth digital signal) with a fourth gain sum of 1 is input to the seventh sub-amplifier through the sixth AND gate, and the second in-phase intermediate frequency signal is input to the eighth differential circuit through the seventh sub-amplifier.
  • the positive input terminal and the output from the eighth differential circuit If the required fourth digital signal is 0, enable can be input to the eighth sub-amplifier but not to the seventh sub-amplifier, so that the seventh sub-amplifier does not work and the eighth sub-amplifier works normally.
  • the fourth initial digital signal sum of 1 is inverted to obtain a fourth digital signal of 0.
  • the fourth digital signal with a fourth gain sum of 0 is input to the eighth sub-amplifier through the seventh AND gate, and the second in-phase intermediate frequency signal passes through
  • the eighth sub-amplifier is input to the negative input end of the seventh differential circuit, is inverted in the seventh differential circuit, and is then output from the seventh differential circuit.
  • the sixth AND gate and the seventh AND gate receive The fourth initial digital signal is 0. If the required fourth digital signal is 1, enable can be input to the eighth sub-amplifier but not to the seventh sub-amplifier, so that the seventh sub-amplifier does not work and the eighth sub-amplifier works normally.
  • the fourth initial digital signal sum of 0 is inverted to obtain a fourth digital signal of 1.
  • the fourth digital signal with a fourth gain sum of 1 is input to the eighth sub-amplifier through the seventh AND gate, and the second in-phase intermediate frequency signal passes through The eighth sub-amplifier is input to the positive input terminal of the seventh differential circuit and is output from the seventh differential circuit. If the required fourth digital signal is 0, enable can be input to the seventh sub-amplifier but not to the eighth sub-amplifier, so that the seventh sub-amplifier operates normally and the eighth sub-amplifier does not operate.
  • the fourth initial digital signal (which can also be said to be the fourth digital signal) with a fourth gain sum of 0 is input to the seventh sub-amplifier through the sixth AND gate, and the second in-phase intermediate frequency signal is input to the eighth differential circuit through the seventh sub-amplifier.
  • the negative input terminal is inverted in the eighth differential circuit and then output from the eighth differential circuit.
  • a second composite signal is obtained by vector summing the signals output by the seventh differential circuit and the eighth differential circuit.
  • this application provides a radio frequency transceiver, which includes a transmitter and the receiver described in the first aspect.
  • the implementation manner of the second aspect corresponds to any implementation manner of the first aspect.
  • the technical effects corresponding to the implementation of the second aspect can be found in the above-mentioned first aspect and the technical effects corresponding to any implementation of the first aspect, and will not be described again here.
  • this application provides a terminal, which includes an antenna and the radio frequency transceiver described in the second aspect.
  • the implementation manner of the third aspect corresponds to any implementation manner of the first aspect.
  • the technical effects corresponding to the implementation of the third aspect can be found in the above-mentioned first aspect and the technical effects corresponding to any implementation of the first aspect, and will not be described again here.
  • Figure 1a is a structural frame diagram of a terminal provided by an embodiment of the present application.
  • Figure 1b is a diagram showing the relationship between the first radio frequency signal, the second radio frequency signal and the local oscillator signal provided by the embodiment of the present application;
  • Figure 2 is a circuit structure diagram of a receiver provided by related technologies
  • Figure 3a is a circuit structure diagram of a receiver provided by an embodiment of the present application.
  • Figure 3b is a circuit structure diagram of another receiver provided by an embodiment of the present application.
  • Figure 3c is a circuit structure diagram of another receiver provided by an embodiment of the present application.
  • Figure 3d is a circuit structure diagram of another receiver provided by an embodiment of the present application.
  • Figure 3e is a circuit structure diagram of another receiver provided by an embodiment of the present application.
  • Figure 3f is a circuit structure diagram of another receiver provided by an embodiment of the present application.
  • Figure 4a is a circuit structure diagram of a control circuit provided by an embodiment of the present application.
  • Figure 4b is a gain change diagram provided by an embodiment of the present application.
  • Figure 4c is a phase change diagram provided by an embodiment of the present application.
  • Figure 5a is a phase diagram of the first radio frequency signal and the second radio frequency signal provided by the embodiment of the present application;
  • Figure 5b is a phase diagram of the first radio frequency signal and the second radio frequency signal provided by the embodiment of the present application after amplification with the first gain;
  • Figure 5c is a two-bit diagram of the first radio frequency signal and the second radio frequency signal provided by the embodiment of the present application after amplification with the second gain;
  • Figure 5d is a phase diagram of the first in-phase intermediate frequency signal provided by the embodiment of the present application.
  • Figure 5e is a phase diagram of the first orthogonal intermediate frequency signal provided by the embodiment of the present application.
  • Figure 5f is a phase diagram of the second orthogonal intermediate frequency signal provided by the embodiment of the present application.
  • Figure 5g is a phase diagram of the second in-phase intermediate frequency signal provided by the embodiment of the present application.
  • Figure 5h is a mode for filtering image interference signals provided by the embodiment of the present application.
  • Figure 5i is a phase diagram of the first composite signal provided by the embodiment of the present application.
  • Figure 5j is a phase diagram of the second composite signal provided by the embodiment of the present application.
  • Figure 5k is a phase diagram after 90° phase shifting of the first composite signal provided by the embodiment of the present application.
  • Figure 5l is a schematic diagram of the process of adding the first synthesized signal and the second synthesized signal provided by the embodiment of the present application;
  • Figure 6a is a circuit structure diagram of another receiver provided by an embodiment of the present application.
  • Figure 6b is a circuit structure diagram of another receiver provided by an embodiment of the present application.
  • Figure 6c is a circuit structure diagram of another receiver provided by an embodiment of the present application.
  • Figure 7a is another mode for filtering image interference signals provided by an embodiment of the present application.
  • Figure 7b is a circuit structure diagram of another receiver provided by an embodiment of the present application.
  • Figure 7c is a circuit structure diagram of another receiver provided by an embodiment of the present application.
  • Figure 7d is a circuit structure diagram of another receiver provided by an embodiment of the present application.
  • Figure 7e is a circuit structure diagram of another receiver provided by an embodiment of the present application.
  • Figure 8a is a circuit structure diagram of a control circuit and a first adder and subtractor provided by an embodiment of the present application;
  • Figure 8b is a circuit structure diagram of another control circuit and a first adder-subtractor provided by an embodiment of the present application;
  • Figure 8c is a circuit structure diagram of a control circuit and a second adder and subtractor provided by an embodiment of the present application;
  • Figure 8d is a circuit structure diagram of another control circuit and a second adder-subtractor provided by the embodiment of the present application;
  • Figure 9a is a circuit structure diagram of another receiver provided by an embodiment of the present application.
  • Figure 9b is a circuit structure diagram of the control circuit, amplifier and first adder-subtractor provided by the embodiment of the present application;
  • Figure 9c is a circuit structure diagram of the control circuit, amplifier and first adder-subtractor provided by the embodiment of the present application.
  • Figure 9d is a circuit structure diagram of the control circuit, amplifier and second adder and subtractor provided by the embodiment of the present application.
  • Figure 9e is a circuit structure diagram of the control circuit, amplifier and second adder and subtractor provided by the embodiment of the present application.
  • a and/or B can mean: A exists alone, A and B exist simultaneously, and they exist alone. B these three situations.
  • first and second in the description and claims of the embodiments of this application are used to distinguish different objects, rather than to describe a specific order of objects.
  • first target object, the second target object, etc. are used to distinguish different target objects, rather than to describe a specific order of the target objects.
  • multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.
  • Embodiments of the present application provide a terminal, which may be a radar, a base station, a server, a mobile phone, or other equipment including a radio frequency transceiver, which is not limited in the embodiments of the present application.
  • the terminal is taken as a mobile phone as an example below.
  • FIG. 1a shows a schematic diagram of an application scenario of a mobile phone provided by an embodiment of the present application.
  • the mobile phone includes a radio frequency transceiver and an antenna 103.
  • a radio frequency transceiver may include a receiver 101 and a transmitter 102.
  • the antenna 103 is coupled to the receiver 101 and the transmitter 102 respectively, and is used for sending radio frequency signals to the receiver 101 and receiving radio frequency signals sent by the transmitter 102.
  • the radio frequency signal includes a first radio frequency signal and a second radio frequency signal.
  • the frequency of the first radio frequency signal is f1
  • the frequency of the second radio frequency signal is f2
  • the frequency of the local oscillator signal is f LO .
  • f1+f IF f LO
  • the intermediate frequency signal IF can be output, thereby causing an image frequency interference problem.
  • Figure 2 shows a typical receiver 101 with amplitude, phase control and image suppression functions.
  • the amplitude control of the radio frequency signal is realized by the variable gain amplifier 1011, and the phase control of the radio frequency signal is realized by the vector synthesis phase shifter 1012.
  • Image rejection is achieved by the mixer 1013 of the quadrature architecture.
  • the amplitude and phase of the radio frequency signal are controlled separately.
  • the amplitude control circuit independently controls the amplitude of the radio frequency signal by controlling the variable gain amplifier 1011; the phase control circuit independently controls the phase of the radio frequency signal by controlling the vector synthesis phase shifter 1012. If high-precision phase shifting is achieved, for the passive vector synthesis phase shifter 1012, the size and loss of the circuit where the receiver 101 is located will increase; for the active vector synthesis phase shifter 1012, the receiver 101 will The power consumption of the circuit increases.
  • the embodiment of the present application provides a receiver 101.
  • the receiver 101 can use an amplifier, a mixer and an image suppression circuit to replace the traditional vector synthesis phase shifter 1012 to adjust the phase of the received radio frequency signal.
  • the layout area and power consumption of the receiver 101 can be saved.
  • the receiver 101 includes a first adjustable radio frequency amplifier VGA1, a second adjustable radio frequency amplifier VGA2, a first in-phase mixer H1, a first quadrature mixer H2, a second Quadrature mixer H3, second in-phase mixer H4, first adder and subtractor 11, and second adder and subtractor 12.
  • the receiver 101 is used for receiving radio frequency signals RF.
  • the radio frequency signal RF is amplified by the first adjustable radio frequency amplifier VGA1 and then outputs a first radio frequency amplified signal RFr.
  • the radio frequency signal RF is amplified by the second adjustable radio frequency amplifier VGA2 and then outputs a second radio frequency amplified signal RFi.
  • the first radio frequency amplified signal RFr is mixed by the first in-phase mixer H1 and then outputs the first in-phase intermediate frequency signal IFIr. After being mixed by the first quadrature mixer H2, the first quadrature intermediate frequency signal IFQr is output. .
  • the second radio frequency amplified signal RFi is mixed by the second quadrature mixer H3 and then outputs the second quadrature intermediate frequency signal IFQi. After being mixed by the second in-phase mixer H4, the second in-phase intermediate frequency signal IFIi is output.
  • the first in-phase intermediate frequency signal IFQr and the second quadrature intermediate frequency signal IFQi are selectively added or subtracted through the first adder and subtractor 11 and then the first composite signal IFI is output.
  • the first quadrature intermediate frequency signal IFQr and the second in-phase intermediate frequency signal IFIi are optionally added or subtracted through the second adder and subtractor 12 and then the second composite signal IFQ is output.
  • the first adjustable radio frequency amplifier VGA1 can amplify the radio frequency signal RF with an adjustable first gain r1
  • the second adjustable radio frequency amplifier VGA2 can amplify the radio frequency signal with an adjustable second gain i1.
  • RF amplifies.
  • the first radio frequency amplified signal RFr can be mixed with the first local oscillator signal LOI through the first in-phase mixer H1, and then the first in-phase intermediate frequency signal IFIr can be output.
  • the first radio frequency amplified signal RFr can be mixed with the second local oscillator signal LOQ through the first quadrature mixer M2, and then the first quadrature intermediate frequency signal IFQr can be output.
  • the second radio frequency amplified signal RFi can be mixed with the second local oscillator signal LOQ through the second quadrature mixer H3 to output a second quadrature intermediate frequency signal IFQi.
  • the second radio frequency amplified signal RFi can be mixed with the first local oscillator signal LOI through the second in-phase mixer H4, and then the second in-phase intermediate frequency signal IFIi can be output.
  • the first local oscillator signal LOI and the second local oscillator signal LOQ are orthogonal, so that the first in-phase intermediate frequency signal IFIr and the second orthogonal intermediate frequency signal IFQi are orthogonal, and the first orthogonal intermediate frequency signal IFQr and the second in-phase intermediate frequency signal are orthogonal.
  • the phase of the first in-phase intermediate frequency signal IFIr is the same as the phase of the second in-phase intermediate frequency signal IFIi
  • the phase of the first orthogonal intermediate frequency signal IFQr is the same as the phase of the second orthogonal intermediate frequency signal IFQi.
  • the working principle of the vector synthesis phase shifter 1012 is to achieve the phase shifting function by changing the ratio of two orthogonal signals.
  • the first adder and subtractor 11 receives the orthogonal first in-phase intermediate frequency signal IFIr and the second orthogonal intermediate frequency signal IFQi. Moreover, since the radio frequency signal RF forming the first in-phase intermediate frequency signal IFIr is amplified by the first adjustable radio frequency amplifier VGA1 with the adjustable first gain r1, the radio frequency signal RF forming the second orthogonal intermediate frequency signal IFQi is amplified by the second adjustable radio frequency amplifier VGA1. The RF amplifier VGA2 amplifies with an adjustable second gain i.
  • the orthogonal first in-phase intermediate frequency signal can be adjusted.
  • the ratio of IFIr to the second orthogonal intermediate frequency signal IFQi replaces the existing vector synthesis phase shifter 1012 to implement the phase shifting function.
  • the second adder and subtractor 12 receives the orthogonal first quadrature intermediate frequency signal IFQr and the second in-phase intermediate frequency signal IFIi. Moreover, since the radio frequency signal RF forming the first orthogonal intermediate frequency signal IFQr is amplified by the first adjustable radio frequency amplifier VGA1 with the adjustable first gain r1, the radio frequency signal RF forming the second in-phase intermediate frequency signal IFIi is amplified by the second adjustable radio frequency amplifier VGA1. The RF amplifier VGA2 amplifies with an adjustable second gain i1.
  • the orthogonal first orthogonal intermediate frequency signal IFQr can be adjusted. and the second in-phase intermediate frequency signal IFIi, thereby replacing the existing vector synthesis phase shifter 1012 to achieve the phase shifting function.
  • this application can utilize the existing first adjustable RF amplifier VGA1, the second adjustable RF amplifier VGA2, the first in-phase mixer H1, the first quadrature mixer H2, and the second quadrature mixer.
  • H3, the second in-phase mixer H4, the first adder and subtractor 11 and the second adder and subtractor 12 replace the traditional vector synthesis phase shifter 1012 to adjust the phase of the received radio frequency signal and save the time of the receiver 101. Layout area and power consumption.
  • this application will implement the first adjustable radio frequency amplifier VGA1, the second adjustable radio frequency amplifier VGA2, the first in-phase mixer H1, and the first quadrature mixer with the amplification function, the phase shift function and the mixing function H2, the second quadrature mixer H3, the second in-phase mixer H4, the first adder and subtractor 11 and the second adder and subtractor 12 are integrated into one, which greatly improves the integration level of the receiver 101, thus reducing the cost of the receiver. Parasitic capacitance and parasitic inductance in 101.
  • first adjustable radio frequency amplifier and the second adjustable radio frequency amplifier can also adjust the amplitude of the radio frequency signal.
  • first adder and subtractor 11 can selectively add or subtract the first in-phase intermediate frequency signal IFIr and the second orthogonal intermediate frequency signal IFQi through vector synthesis;
  • the second adder and subtractor 12 can selectively add or subtract the first in-phase intermediate frequency signal IFIr and the second orthogonal intermediate frequency signal IFQi through vector synthesis.
  • the first quadrature intermediate frequency signal IFQr and the second in-phase intermediate frequency signal IFIi are selectively added or subtracted.
  • the first in-phase intermediate frequency signal IFIr and the first quadrature intermediate frequency signal IFQr are amplified by the first gain r1, and the second quadrature intermediate frequency signal IFQi and the second in-phase intermediate frequency signal IFIi are amplified by the second gain i1. Therefore, even if the first gain r1 and/or the second gain i1 is changed, the vector synthesis result of the first in-phase intermediate frequency signal IFIr and the second quadrature intermediate frequency signal IFQi is the same as the first quadrature intermediate frequency signal IFQr and the second in-phase intermediate frequency signal The magnitude of IFIi's vector synthesis results is always the same.
  • the receiver 101 can input the same radio frequency signal RF to the first adjustable radio frequency amplifier VGA1 and the second adjustable radio frequency amplifier VGA2.
  • the signal amount, amplitude and phase of the radio frequency signal RF input to the first adjustable radio frequency amplifier VGA1 and the second adjustable radio frequency amplifier VGA2 may be the same.
  • the first adjustable radio frequency amplifier VGA1 amplifies the radio frequency signal with the first gain r1, which means: the first adjustable radio frequency amplifier VGA1 amplifies the radio frequency signal input to the first amplifier with the first gain r1.
  • RF is amplified, and the ratio of the first radio frequency amplified signal RFr output from the first adjustable radio frequency amplifier VGA1 and the radio frequency signal RF input to the first adjustable radio frequency amplifier VGA1 is the first gain r1; the second adjustable radio frequency amplifier VGA2
  • the radio frequency signal RF input to the second adjustable radio frequency amplifier VGA2 is amplified with the second gain i1, and the second radio frequency amplified signal RFi output from the second adjustable radio frequency amplifier VGA2 is the same as the second radio frequency amplified signal RFi input to the second adjustable radio frequency amplifier VGA2.
  • the ratio of the radio frequency signal RF is the second gain i1.
  • this application can use a single-stage amplifier to amplify the radio frequency signal RF.
  • this embodiment of the present application shows that the first adjustable radio frequency amplifier VGA1 and the second adjustable radio frequency amplifier VGA2 are coupled to the input terminal IN of the receiver 101 and the first in-phase mixer H1, the first The situation between the quadrature mixer H2, the second quadrature mixer H3, and the second in-phase mixer H4.
  • the radio frequency signal RF received by the receiver 101 can first be amplified by the first adjustable radio frequency amplifier VGA1 and the second adjustable radio frequency amplifier VGA2, and then pass through the first in-phase mixer H1 and the first quadrature mixer H2, the second quadrature mixer H3, and the second in-phase mixer H4 mix.
  • the first in-phase mixer H1, the first quadrature mixer H2, the second quadrature mixer H3, and the second in-phase mixer H4 can also be coupled to the receiver 101.
  • the radio frequency signal RF received by the receiver 101 may first be mixed by the first in-phase mixer H1, the first quadrature mixer H2, the second quadrature mixer H3, and the second in-phase mixer H4. frequency, and then amplified by the first adjustable RF amplifier VGA1 and the second adjustable RF amplifier VGA2.
  • this application can also use a multi-stage amplifier to amplify the radio frequency signal RF.
  • the first adjustable radio frequency amplifier VGA1 and the second adjustable radio frequency amplifier VGA2 are coupled between the input terminal IN of the receiver 101 and the first in-phase mixer H1, the first quadrature mixer H2, and the third Between the two quadrature mixers H3 and the second in-phase mixer H4.
  • the receiver 101 may also include a third adjustable radio frequency amplifier VGA2, a fourth adjustable radio frequency amplifier VGA4, a fifth adjustable radio frequency amplifier VGA5, and a sixth adjustable radio frequency amplifier VGA6.
  • the third adjustable radio frequency amplifier VGA2, the fourth adjustable radio frequency amplifier VGA4, the fifth adjustable radio frequency amplifier VGA5, and the sixth adjustable radio frequency amplifier VGA6 may be coupled to the first in-phase mixer H1 and the first quadrature mixer between the device H2, the second quadrature mixer H3, the second in-phase mixer H4 and the output terminal OUT of the receiver 101.
  • the third adjustable radio frequency amplifier VGA2 amplifies the first in-phase intermediate frequency signal IFQr with the third gain r2
  • the fourth adjustable radio frequency amplifier VGA4 amplifies the second orthogonal intermediate frequency signal IFQi with the third gain r2
  • the fifth adjustable radio frequency amplifier VGA4 amplifies the second quadrature intermediate frequency signal IFQi with the third gain r2.
  • the radio frequency amplifier VGA5 amplifies the first quadrature intermediate frequency signal IFQr with a fourth gain i2
  • the sixth adjustable radio frequency amplifier VGA6 amplifies the second in-phase intermediate frequency signal IFIi with a fourth gain i2.
  • FIGS. 3a to 3c are only examples, and the number of amplifiers in the receiver 101 can also be other, which is not limited in this embodiment of the present application.
  • multi-stage amplifiers can achieve a high variable gain range. Compared with multi-stage amplifiers, single-stage amplifiers can improve linearity and reduce power consumption and layout area of the receiver 101. Regardless of whether a single-stage amplifier or a multi-stage amplifier is used, the traditional vector synthesis phase shifter 1012 can be omitted, thereby saving the layout area and power consumption of the receiver 101.
  • the receiver 101 may also include a control circuit 15.
  • the control circuit 15 may include a control code generator.
  • the output side of the control code generator is connected to the first adjustable radio frequency amplifier VGA1 and the second Adjustable RF amplifier VGA2 coupling.
  • the control code generator can input the first gain r1 to the first adjustable radio frequency amplifier VGA1 and the second gain i1 to the second adjustable radio frequency amplifier VGA2 according to the preset gain control code and phase control code.
  • the control code generator can be based on the preset The gain control code and phase control code input the third gain r2 to the third adjustable RF amplifier VGA3 and the fourth adjustable RF amplifier VGA4, and input the fourth gain r2 to the fifth adjustable RF amplifier VGA5 and the sixth adjustable RF amplifier VGA6.
  • Gain i2 the third adjustable radio frequency amplifier VGA3 and the fourth adjustable radio frequency amplifier VGA4
  • the fifth adjustable radio frequency amplifier VGA5 and the sixth adjustable RF amplifier VGA6 the control code generator can be based on the preset The gain control code and phase control code input the third gain r2 to the third adjustable RF amplifier VGA3 and the fourth adjustable RF amplifier VGA4, and input the fourth gain r2 to the fifth adjustable RF amplifier VGA5 and the sixth adjustable RF amplifier VGA6.
  • the embodiments of the present application do not limit the number of bits of the first gain r1, the second gain i1, the third gain r2, and the fourth gain i2.
  • the third gain can be designed according to the actual required amplitude and phase.
  • the bit numbers of the first gain r1, the second gain i1, the third gain r2, and the fourth gain i2 themselves include multiple states. Therefore, when adjusting the phase of the radio frequency signal by adjusting the magnitudes of the first gain r1, the second gain i1, the third gain r2, and the fourth gain i2, there is no need to additionally increase the number of bits of the control circuit 15.
  • the first gain r1 and the third gain r2 include a total of 000, 001, 010, 011, and 100 , 101, 110, 111 and other 8 states.
  • the total number of bits of the second gain i1 and the fourth gain i2 is 3, recorded as i code ⁇ 0:m>, then the second gain i1 and the fourth gain i2 include a total of 000, 001, 010, 011, 100, 101 , 110, 111 and other 8 states.
  • m is a positive integer.
  • the number of bits of the first gain r1 of the first adjustable radio frequency amplifier VGA1 may be n-1, recorded as r1code ⁇ 0:n-1>, and the third bit number of the third adjustable radio frequency amplifier VGA3 and the fourth adjustable radio frequency amplifier VGA4
  • the number of bits of the second gain i1 of the second adjustable radio frequency amplifier VGA2 can be n-1, recorded as i1code ⁇ 0:n-1>, and the fourth of the fifth adjustable radio frequency amplifier VGA5 and the sixth adjustable radio frequency amplifier VGA6
  • n is a positive integer less than m.
  • the receiver 101 includes the first adjustable radio frequency amplifier VGA1 and the second adjustable radio frequency amplifier VGA2, it does not include the third adjustable radio frequency amplifier VGA3, the fourth adjustable radio frequency amplifier VGA4, the fifth adjustable radio frequency amplifier VGA5, and
  • the first gain r1 includes 8 states such as 000, 001, 010, 011, 100, 101, 110, and 111.
  • the second gain i1 includes 8 states such as 000, 001, 010, 011, 100, 101, 110, and 111.
  • the total number of bits of the first gain r1 and the third gain r2 is the same as the total number of bits of the second gain i1 and the fourth gain i2.
  • the first gain r1 and the third gain r1 are equal to the total number of bits of the second gain i1 and the fourth gain i2.
  • the total number of bits of the third gain r2 may be different from the total number of bits of the second gain i1 and the fourth gain i2, which is not limited in the embodiment of the present application.
  • the above-mentioned control circuit 15 may also include a symbolic code generator.
  • the symbol code generator is used to input the first digital signal S1r and the third digital signal S1i to the first adder and subtractor 11 , and to input the second digital signal S2r and the fourth digital signal S2i to the second adder and subtractor 12 .
  • the first digital signal S1r is used to determine whether the phase of the first in-phase intermediate frequency signal IFIr is positive or negative.
  • the second digital signal S2r is used to determine whether the phase of the first quadrature intermediate frequency signal IFQr is positive or negative.
  • the third digital signal S1i is used to determine whether the phase of the second orthogonal intermediate frequency signal IFQi is positive or negative, and the fourth digital signal S2i is used to determine whether the phase of the second in-phase intermediate frequency signal IFIi is positive or negative.
  • the first digital signal S1r is 1, and the phase of the first in-phase intermediate frequency signal IFIr is negative; the first digital signal S1r is 0, and the phase of the first in-phase intermediate frequency signal IFIr is positive.
  • the second digital signal S2r is 1, and the phase of the first quadrature intermediate frequency signal IFQr is negative; the second digital signal S2r is 0, and the phase of the first quadrature intermediate frequency signal IFQr is positive.
  • the third digital signal S1i is 1, and the phase of the second quadrature intermediate frequency signal IFQi is negative; the third digital signal S1i is 0, and the phase of the second quadrature intermediate frequency signal IFQi is positive.
  • the fourth digital signal S2i is 1, and the phase of the second in-phase intermediate frequency signal IFIi is negative; the fourth digital signal S2i is 0, and the phase of the second in-phase intermediate frequency signal IFIi is positive.
  • the first digital signal S1r is 1 and the phase of the first in-phase intermediate frequency signal IFIr is positive; the first digital signal S1r is 0 and the phase of the first in-phase intermediate frequency signal IFIr is negative.
  • the second digital signal S2r is 1, and the phase of the first quadrature intermediate frequency signal IFQr is positive; the second digital signal S2r is 0, and the phase of the first quadrature intermediate frequency signal IFQr is negative.
  • the third digital signal S1i is 1, and the phase of the second quadrature intermediate frequency signal IFQi is positive; the third digital signal S1i is 0, and the phase of the second quadrature intermediate frequency signal IFQi is negative.
  • the fourth digital signal S2i is 1, and the phase of the second in-phase intermediate frequency signal IFIi is positive; the fourth digital signal S2i is 0, and the phase of the second in-phase intermediate frequency signal IFIi is negative.
  • the following is used as an example for convenience of description.
  • the first adder and subtractor 11 compares the first in-phase intermediate frequency signal IFIr with a positive phase (or the first in-phase intermediate frequency signal IFIr with a negative phase). ) is vector combined with the second orthogonal intermediate frequency signal IFQi with a positive phase (or the second orthogonal intermediate frequency signal IFQi with a negative phase) to obtain the first combined signal IFI.
  • the second adder and subtractor 12 compares the first quadrature intermediate frequency signal IFQr with a positive phase (or the first quadrature intermediate frequency signal IFQr with a negative phase) and the first quadrature intermediate frequency signal IFQr with a positive phase.
  • the second in-phase intermediate frequency signal IFIi (or the second in-phase intermediate frequency signal IFIi with a negative phase) is vector synthesized to obtain a second synthesized signal IFQ.
  • the receiver 101 may also include a differential circuit 14 and an existing phase shifter 13.
  • the first composite signal IFI and the second composite signal IFQ are further processed to filter out image interference signals in the first composite signal IFI and the second composite signal IFQ.
  • the phase shifter 13 is used to perform a 90° phase shift on the first composite signal IFI or the second composite signal IFQ.
  • the differential circuit 14 is used to add the second composite signal IFQ and the phase-shifted first composite signal IFI, or to add the first composite signal IFI and the phase-shifted second composite signal IFQ, to filter out the first composite signal. IFI and the image interference signal in the second composite signal IFQ.
  • the phase shifter 13 may be a polyphase filter or a quadrature coupler.
  • first in-phase intermediate frequency signal IFIr and the second in-phase intermediate frequency signal IFIi are both mirrored by the first local oscillator signal LOI and the frequency between the first local oscillator signal LOI.
  • the first radio frequency signal and the second radio frequency signal which have the same difference and different frequencies, are amplified and mixed with the first local oscillator signal LOI.
  • For the first orthogonal intermediate frequency signal IFQr and the second orthogonal intermediate frequency signal IFQi they are both mirrored by the second local oscillator signal LOQ, and the frequency difference between the second local oscillator signal LOQ and the second local oscillator signal LOQ is the same, and the two frequencies are different.
  • the first radio frequency signal and the second radio frequency signal are amplified and mixed with the second local oscillator signal LOQ.
  • the first in-phase intermediate frequency signal IFIr, the first quadrature intermediate frequency signal IFQr, the second quadrature intermediate frequency signal IFQi and the second in-phase intermediate frequency signal IFIi include both the amplified first radio frequency signal and the first local oscillator.
  • the first signal obtained by mixing the signal LOI or the second local oscillator signal LOQ also includes the second signal obtained by mixing the amplified second radio frequency signal and the first local oscillator signal LOI or the second local oscillator signal LOQ.
  • One of the first signal and the second signal is a useful signal, and the other is an image interference signal.
  • the embodiment of the present application does not limit the digital logic of the first digital signal S1r, the second digital signal S2r, the third digital signal S1i and the fourth digital signal S2i when filtering the image interference signal.
  • the image suppression circuit 14 may select the first signal as the useful signal according to the first digital signal S1r, the second digital signal S2r, the third digital signal S1i and the fourth digital signal S2i input to the image suppression circuit 14 by the symbol code generator, so as to Filter out the second signal; or select the second signal as a useful signal to filter out the first signal.
  • the symbol code generator can be coupled with the control code generator for receiving the image suppression control code and the quadrant control code input by the control code generator, and based on the quadrant control code, image suppression control code,
  • the coupling relationship between the phase shifter 13 and the first adder and subtractor 11 and the second adder and subtractor 12, as well as the coupling relationship between the phase shifter 13 and the input end of the differential circuit 14, determine the first number input to the first adder and subtractor 11.
  • the signal S1r and the third digital signal S1i, as well as the second digital signal S2r and the fourth digital signal S2i input to the second adder and subtractor 12 are 0 or 1.
  • the quadrant control code is used to characterize the quadrant where the useful signal is located.
  • the image suppression mode is used to characterize the first signal as a useful signal and the second signal as an image interference signal; or the image suppression mode is used to characterize the first signal as an image interference signal and the second signal as a useful signal.
  • 360° can be divided into four quadrants according to the phase of the input radio frequency signal RF. Among them, 0°-90° is the first quadrant, 90°-180° is the second quadrant, 180°-270° is the third quadrant, and 270°-360° is the fourth quadrant.
  • the quadrant control code is 0°-90°, the useful signal is located in the first quadrant; if the quadrant control code is 90°-18/0°, the useful signal is located in the second quadrant; if the quadrant control code is 180°-270° , the useful signal is located in the third quadrant; if the quadrant control code is 270°-360°, the useful signal is located in the fourth quadrant.
  • the image suppression mode MC When the image suppression mode MC is 0, it means that the first signal is a useful signal and the second signal is an image interference signal; when the image suppression mode MC is 1, it means that the first signal is an image interference signal and the second signal is a useful signal.
  • the method can be based on the quadrant control code, the image suppression mode, the coupling relationship between the phase shifter 13 and the first adder and subtractor 11 or the second adder and subtractor 12, and the input side of the differential circuit 14 and the phase shifter.
  • the coupling relationship of the device 13 four sets of truth tables are preset, and according to the data in the truth tables, it is determined that the first digital signal S1r, the second digital signal S2r, the third digital signal S1i and the fourth digital signal S2i are 0 or 0. 1.
  • the first set of truth tables can be determined according to the quadrant control code and the image suppression mode, as shown in Tables 1 and 2.
  • the first set of truth tables namely Table 1 and Table 2, are used as examples below.
  • phase shifter 13 is coupled to the first adder and subtractor 11, it is used to phase shift the first composite signal IFI, and the positive input end of the differential circuit 14 is coupled to the negative input of the phase shifter 13.
  • the terminal is coupled with the second adder and subtractor 12, then the second set of truth tables can be determined according to the quadrant control code and the image suppression mode.
  • phase shifter 13 is coupled to the second adder and subtractor 12, it is used to phase shift the second composite signal IFQ, and the negative input end of the differential circuit 14 is coupled to the positive input of the phase shifter 13.
  • the terminal is coupled with the first adder and subtractor 11, then the third set of truth tables can be determined according to the quadrant control code and the image suppression mode.
  • phase shifter 13 is coupled to the second adder and subtractor 12, it is used to phase shift the second composite signal IFQ, and the positive input end of the differential circuit 14 is coupled to the negative input of the phase shifter 13.
  • the terminal is coupled with the first adder and subtractor 11, then the fourth set of truth tables can be determined according to the quadrant control code and the image suppression mode.
  • this application can not only use the first adjustable radio frequency amplifier VGA1 and the second adjustable radio frequency amplifier VGA2 (or the first adjustable radio frequency amplifier VGA1, the second adjustable radio frequency amplifier VGA2, the third adjustable radio frequency amplifier
  • the amplifier VGA3, the fourth adjustable radio frequency amplifier VGA4, the fifth adjustable radio frequency amplifier VGA5 and the sixth adjustable radio frequency amplifier VGA6) are configured according to the variable first gain r1 and the second gain i1 (or, the first gain r1, the second gain i1).
  • the gain i1, the third gain r2 and the fourth gain i2) amplify the radio frequency signal RF to varying degrees.
  • the useful signal after filtering out the image interference signal is located in the second quadrant Q2 or the fourth quadrant Q4, the larger the second gain i1 (or the second gain i1 and the fourth gain i2), the smaller the phase of the useful signal; The smaller the second gain i1 (or the second gain i1 and the fourth gain i2), the larger the phase of the useful signal.
  • phase change and gain change is based on the first set of truth tables mentioned above. If it is based on other truth tables, the relationship between phase change and gain change can be other.
  • the first radio frequency signal A1 and the second radio frequency signal A2 are input to the first adjustable radio frequency amplifier VGA1 and the second adjustable radio frequency amplifier VGA2 with the same phase. Assume that the first radio frequency signal A1 and the second The phase of radio frequency signal A2 is 0°.
  • the first adjustable radio frequency amplifier VGA1 receives the first radio frequency signal A1 and the second radio frequency signal A2, it amplifies the first radio frequency signal A1 and the second radio frequency signal A2 with the first gain r1, And output the first radio frequency amplified signal RFr.
  • the first radio frequency amplified signal RFr includes the first amplified signal A1Ar1 and the second amplified signal A2Ar1, and the phases of the first amplified signal A1Ar1 and the second amplified signal A2Ar1 have not changed and are still 0°. .
  • the second adjustable radio frequency amplifier VGA2 receives the first radio frequency signal A1 and the second radio frequency signal A2, it amplifies the first radio frequency signal A1 and the second radio frequency signal A2 with the second gain i1, And output a second radio frequency amplified signal RFi.
  • the second radio frequency amplified signal RFi includes the third amplified signal A1Ai1 and the fourth amplified signal A2Ai1, and the phases of the third amplified signal A1Ai1 and the fourth amplified signal A2Ai1 have not changed and are still 0°. .
  • a first in-phase intermediate frequency signal IFIr is output.
  • the first in-phase intermediate frequency signal IFIr includes a first in-phase intermediate frequency signal jA1Ar1 obtained by mixing the first amplified signal A1Ar1 and the first local oscillator signal LOI, and a first in-phase intermediate frequency signal jA1Ar1 obtained by mixing the second amplified signal A2Ar1 and the first local oscillator signal LOI.
  • the first in-phase intermediate frequency signal jA2Ar1 obtained from the frequency.
  • the first local oscillator signal LOI is sin( ⁇ LO t)
  • IF (A 1 A r1 sin ⁇ 1 t+A 2 A r1 sin ⁇ 2 t)sin ⁇ LO t
  • the product of the first in-phase intermediate frequency signal IFIr is Including the first in-phase intermediate frequency signal jA1Ar1 and the first in-phase intermediate frequency signal jA2Ar1.
  • ⁇ IF represents the angular frequency of the intermediate frequency signal.
  • ⁇ IF can be the angular frequency of the first in-phase intermediate frequency signal IFIr;
  • ⁇ 1 represents the angular frequency of the first radio frequency signal A1;
  • ⁇ 2 is the angular frequency of the second radio frequency signal A2.
  • ⁇ LO represents the angular frequency of the first local oscillator signal LOI;
  • sin ⁇ 1 t is the expression of the first radio frequency signal A1, and sin ⁇ 2 t is the expression of the second radio frequency signal A2.
  • the first orthogonal intermediate frequency signal IFQr includes a first orthogonal intermediate frequency signal -A1Ar1 obtained by mixing the first amplified signal A1Ar1 and the second local oscillator signal LOQ, and a first orthogonal intermediate frequency signal -A1Ar1 obtained by mixing the second amplified signal A2Ar1 and the second local oscillator signal LOQ.
  • the first orthogonal intermediate frequency signal A2Ar1 obtained by mixing.
  • the second local oscillator signal LOQ is cos( ⁇ LO t) orthogonal to the first local oscillator signal LOI.
  • the product of the first orthogonal intermediate frequency signal IFQr is Including the first orthogonal intermediate frequency signal -A1Ar1 and the first orthogonal intermediate frequency signal A2Ar1.
  • the second orthogonal intermediate frequency signal IFQi includes a second orthogonal intermediate frequency signal -A1Ai1 obtained by mixing the third amplified signal A1Ai1 and the second local oscillator signal LOQ, and a second orthogonal intermediate frequency signal -A1Ai1 obtained by mixing the fourth amplified signal A2Ai1 and the second local oscillator signal LOQ.
  • the second orthogonal intermediate frequency signal A2Ai1 obtained by mixing.
  • the second local oscillator signal LOQ is cos( ⁇ LO t) orthogonal to the first local oscillator signal LOI.
  • IF (A 1 A i1 sin ⁇ 1 t+A 2 A i1 sin ⁇ 2 t)cos ⁇ LO t
  • the product of the second orthogonal intermediate frequency signal IFQi is It can be seen that it includes the second orthogonal intermediate frequency signal -A1Ai1 and the second orthogonal intermediate frequency signal A2Ai1.
  • a second in-phase intermediate frequency signal IFIi is output.
  • the second in-phase intermediate frequency signal IFIi includes a second in-phase intermediate frequency signal jA1Ai1 obtained by mixing the third amplified signal A1Ai1 and the first local oscillator signal LOI, and a second in-phase intermediate frequency signal jA1Ai1 obtained by mixing the fourth amplified signal A2Ai1 and the first local oscillator signal LOI.
  • the first local oscillator signal LOI is sin( ⁇ LO t)
  • the mixing formula IF (A 1 A i1 sin ⁇ 1 t+A 2 A i1 sin ⁇ 2 t)sin ⁇ LO t
  • the product of the second in-phase intermediate frequency signal IFIi is Including the second in-phase intermediate frequency signal jA1Ai1 and the second in-phase intermediate frequency signal jA2Ai1.
  • both the first composite signal IFI and the second composite signal IFQ include parameters Ar1 and Ai1, the first composite signal IFI and the second composite signal IFQ have the same amplitude.
  • the first composite signal IFI and the second composite signal IFQ can be controlled to have orthogonal phases.
  • the differential circuit 14 can be used to add the second composite signal IFQ and the 90° phase-shifted first composite signal IFI to filter out the image interference signal and output the useful signal IF OUT . Since the phase shifter 13 is coupled to the negative input terminal of the differential circuit 14 and the second adder-subtractor 12 is coupled to the positive input terminal of the differential circuit 14, the differential circuit 14 can be used to compare the second composite signal IFQ with the phase-shifted signal IFQ by 90°.
  • the first signal is the useful signal
  • the second signal is the image interference signal
  • the quadrant where the useful signal is located is the first quadrant.
  • symbol code The first digital signal and the third digital signal input by the generator to the first adder and subtractor 11 are both 1, and the phases of the first in-phase intermediate frequency signal IFIr and the second quadrature intermediate frequency signal IFQi are both positive.
  • the second digital signal input by the symbol code generator to the second adder and subtractor 12 is 0, the fourth digital signal is 1, the phase of the first quadrature intermediate frequency signal IFQr is negative, and the phase of the second in-phase intermediate frequency signal IFIi is positive.
  • the first adder and subtractor 11 can control the vector addition of the first in-phase intermediate frequency signal IFIr with a positive phase and the second orthogonal intermediate frequency signal IFQi with a positive phase to obtain the first composite signal IFI.
  • the vector sum of the two is the first composite signal IFI is jA1Ar1-A1Ai1, and the phase of jA1Ar1-A1Ai1 is located in the second quadrant.
  • the vector sum of the two and the first composite signal IFI is jA2Ar1+A2Ai1, jA2Ar1+A2Ai1
  • the phase is in the first quadrant.
  • the second adder and subtractor 12 can control the vector addition of the first orthogonal intermediate frequency signal IFQr with a negative phase and the second in-phase intermediate frequency signal IFIi with a positive phase to obtain the second composite signal IFQ.
  • the phase is 0°
  • the first orthogonal intermediate frequency signal A2Ar1 with a phase of 0°, after inversion, has a phase of 180°, and after vector addition with the second in-phase intermediate frequency signal jA2Ai1 with a phase of 90°, the vector sum of the two and the second composite signal IFQ is
  • the phases of jA2Ai1-A2Ar1 and jA2Ai1-A2Ar1 are located in the second quadrant.
  • the first combined signal IFI and the second combined signal IFQ include parameters Ar1 and Ai1
  • the first combined signal IFI and the second combined signal IFQ have the same amplitude.
  • the first composite signal IFI and the second composite signal IFQ can be controlled to have orthogonal phases. .
  • the phase shifter 13 can be used to perform a 90° phase shift on jA1Ar1-A1Ai1 and jA2Ar1+A2Ai1 in the first composite signal IFI. It can also be said that the phase shifter 13 is used to perform a 90° phase shift on the first composite signal IFI.
  • the phases of jA1Ar1-A1Ai1 and jA2Ar1+A2Ai1 in IFI add 90°. Please refer to Figure 5i and Figure 5k.
  • the differential circuit 14 can be used to synthesize the second
  • the second signal obtained by mixing the second radio frequency signal A2 with the first local oscillator signal LOI and the second local oscillator signal LOQ can be filtered out, and the first signal can be retained as a useful signal.
  • the retained first signal has the same phase as jA1Ai1+A1Ar1 in the second composite signal IFQ, and is located in the first quadrant.
  • the first signal is the useful signal
  • the second signal is the image interference signal
  • the quadrant where the useful signal is located is the second quadrant.
  • symbol code The first digital signal input by the generator to the first adder and subtractor 11 is 0, the third digital signal is 1, the phase of the first in-phase intermediate frequency signal IFIr is negative, and the phase of the second quadrature intermediate frequency signal IFQi is positive.
  • the second digital signal and the fourth digital signal input by the symbol code generator to the second adder and subtractor 12 are both 1, and the phases of the first quadrature intermediate frequency signal IFQr and the second in-phase intermediate frequency signal IFIi are both positive.
  • the first adder and subtractor 11 can control the vector addition of the first in-phase intermediate frequency signal IFIr with a negative phase and the second orthogonal intermediate frequency signal IFQi with a positive phase to obtain the first composite signal IFI.
  • the phase is 270°
  • the vector sum of the two is the first
  • the composite signal IFI is -jA1Ar1-A1Ai1
  • the phase of -jA1Ar1-A1Ai1 is located in the third quadrant.
  • the phase is 270°.
  • the vector sum of the two is the first composite signal IFI. It is -jA2Ar1+A2Ai1, and the phase of -jA2Ar1+A2Ai1 is located in the fourth quadrant.
  • the second adder and subtractor 12 can control the vector addition of the first orthogonal intermediate frequency signal IFQr with a positive phase and the second in-phase intermediate frequency signal IFIi with a positive phase to obtain the second composite signal IFQ.
  • the vector sum of the two and the second composite signal IFQ is jA1Ai1-A1Ar1, jA1Ai1- The phase of A1Ar1 is in the second quadrant.
  • the vector sum of the two and the second composite signal IFQ is jA2Ai1+A2Ar1, and the phase of jA2Ai1+A2Ar1 Located in the first quadrant.
  • both the first composite signal IFI and the second composite signal IFQ include parameters Ar1 and Ai1, the first composite signal IFI and the second composite signal IFQ have the same amplitude.
  • the first composite signal IFI and the second composite signal IFQ can be controlled to have orthogonal phases. .
  • the phase shifter 13 can be used to perform a 90° phase shift on -jA1Ar1-A1Ai1 and -jA2Ar1+A2Ai1 in the first composite signal IFI. It can also be said that the phase shifter 13 can be used to perform a 90° phase shift on -jA1Ar1 in the first composite signal IFI.
  • the phases of -A1Ai1 and -jA2Ar1+A2Ai1 add 90°.
  • the differential circuit 14 can be used to combine the second composite signal IFQ and
  • the second signal obtained by mixing the second radio frequency signal A2 with the first local oscillator signal LOI and the second local oscillator signal LOQ can be filtered out, and the first signal can be retained as a useful signal.
  • the retained first signal has the same phase as jA1Ai1-A1Ar1 in the second composite signal IFQ, and is located in the second quadrant.
  • the first signal is the useful signal
  • the second signal is the image interference signal
  • the quadrant where the useful signal is located is the third quadrant.
  • symbol code The first digital signal and the third digital signal input by the generator to the first adder and subtractor 11 are both 0, and the phases of the first in-phase intermediate frequency signal IFIr and the second quadrature intermediate frequency signal IFQi are both negative.
  • the second digital signal input by the symbol code generator to the second adder and subtractor 12 is 1, the fourth digital signal is 0, the phase of the first quadrature intermediate frequency signal IFQr is positive, and the phase of the second in-phase intermediate frequency signal IFIi is negative.
  • the first adder and subtractor 11 can control the vector addition of the first in-phase intermediate frequency signal IFIr with a negative phase and the second orthogonal intermediate frequency signal IFQi with a negative phase to obtain the first composite signal IFI.
  • the first in-phase intermediate frequency signal jA1Ar1 with a phase of 90° is inverted, and the phase is 270°;
  • the second orthogonal intermediate frequency signal -A1Ai1 with a phase of 180° is inverted, and the phase is 0°.
  • the phase is 270°; after the second orthogonal intermediate frequency signal A2Ai1 with a phase of 0° is inverted, the phase is 180°.
  • the vector sum of the two and the first composite signal IFI is -jA2Ar1-A2Ai1, the phase of -jA2Ar1-A2Ai1 Located in the third quadrant.
  • the second adder and subtractor 12 can control the vector addition of the first orthogonal intermediate frequency signal IFQr with a positive phase and the second in-phase intermediate frequency signal IFIi with a negative phase to obtain the second composite signal IFQ.
  • the phase is 270°
  • the vector sum of the two is the second composite
  • the phase is 270°.
  • the vector sum of the two and the second composite signal IFQ is The phases of A2Ar1-jA2Ai1 and A2Ar1-jA2Ai1 are located in the fourth quadrant.
  • both the first composite signal IFI and the second composite signal IFQ include parameters Ar1 and Ai1, the first composite signal IFI and the second composite signal IFQ have the same amplitude.
  • the first composite signal IFI and the second composite signal IFQ can be controlled to have orthogonal phases. .
  • the phase shifter 13 can be used to perform a 90° phase shift on A1Ai1-jA1Ar1 and -jA2Ar1-A2Ai1 in the first composite signal IFI. It can also be said that the phase shifter 13 can be used to perform a 90° phase shift on A1Ai1-jA1Ar1 in the first composite signal IFI. Add 90° to the phase of -jA2Ar1-A2Ai1.
  • the second signal obtained by mixing the second radio frequency signal A2 with the first local oscillator signal LOI and the second local oscillator signal LOQ can be filtered out, and the first signal can be retained as a useful signal.
  • the retained first signal has the same phase as -jA1Ai1-A1Ar1 in the second composite signal IFQ, and is located in the third quadrant.
  • the fourth case takes the first signal as the useful signal, the second signal as the image interference signal, and the quadrant where the useful signal is located as the fourth quadrant.
  • symbol code The first digital signal input by the generator to the first adder and subtractor 11 is 1, the third digital signal is 0, the phase of the first in-phase intermediate frequency signal IFIr is positive, and the phase of the second quadrature intermediate frequency signal IFQi is negative.
  • the second digital signal and the fourth digital signal input by the symbol code generator to the second adder and subtractor 12 are both 0, and the phases of the first quadrature intermediate frequency signal IFQr and the second in-phase intermediate frequency signal IFIi are both negative.
  • the first adder and subtractor 11 can control the vector addition of the first in-phase intermediate frequency signal IFIr with a positive phase and the second orthogonal intermediate frequency signal IFQi with a negative phase to obtain the first composite signal IFI.
  • the phase is 0°
  • the vector sum of the two is the first
  • the phase of jA1Ar1+A1Ai1 is located in the first quadrant.
  • the phase is 180°.
  • the vector sum of the two is the first composite signal IFI. is jA2Ar1-A2Ai1, and the phase of jA2Ar1-A2Ai1 is located in the second quadrant.
  • the second adder and subtractor 12 can control the vector addition of the first orthogonal intermediate frequency signal IFQr with a negative phase and the second in-phase intermediate frequency signal IFIi with a negative phase to obtain the second composite signal IFQ.
  • the phase is 0°; after the second in-phase intermediate frequency signal jA1Ai1 with a phase of 90° is inverted, the phase is 270°.
  • the phase of -jA1Ai1+A1Ar1 is located in the fourth quadrant.
  • the first orthogonal intermediate frequency signal A2Ar1 with a phase of 0° has a phase of 180° after inversion; the second in-phase intermediate frequency signal jA2Ai1 with a phase of 90° has a phase of 270° after inversion.
  • the vector sum of the two and the second composite signal IFQ is -jA2Ai1-A2Ar1
  • the phase of -jA2Ai1-A2Ar1 is at The third quadrant.
  • both the first composite signal IFI and the second composite signal IFQ include parameters Ar1 and Ai1, the first composite signal IFI and the second composite signal IFQ have the same amplitude.
  • the first composite signal IFI and the second composite signal IFQ can be controlled to have orthogonal phases. .
  • the phase shifter 13 can be used to perform a 90° phase shift on jA1Ar1+A1Ai1 and jA2Ar1-A2Ai1 in the first composite signal IFI. It can also be said that the phase shifter 13 can be used to perform a 90° phase shift on jA1Ar1+A1Ai1 and jA1Ar1+A1Ai1 in the first composite signal IFI. Add 90° to the phase of jA2Ar1-A2Ai1.
  • the second signal obtained by mixing the second radio frequency signal A2 with the first local oscillator signal LOI and the second local oscillator signal LOQ can be filtered out, and the first signal can be retained as a useful signal.
  • the retained first signal has the same phase as -jA1Ai1+A1Ar1 in the second composite signal IFQ, and is located in the fourth quadrant.
  • the fifth case takes the first signal as the image interference signal, the second signal as the useful signal, and the quadrant where the useful signal is located as the first quadrant.
  • symbol code The first digital signal input by the generator to the first adder and subtractor 11 is 1, the third digital signal is 0, the phase of the first in-phase intermediate frequency signal IFIr is positive, and the phase of the second quadrature intermediate frequency signal IFQi is negative.
  • the second digital signal and the fourth digital signal input by the symbol code generator to the second adder and subtractor 12 are both 1, and the phases of the first quadrature intermediate frequency signal IFQr and the second in-phase intermediate frequency signal IFIi are both positive.
  • the first adder and subtractor 11 can control the vector addition of the first in-phase intermediate frequency signal IFIr with a positive phase and the second orthogonal intermediate frequency signal IFQi with a negative phase to obtain the first composite signal IFI.
  • the phase is 0°
  • the vector sum of the two is the first
  • the phase of jA1Ar1+A1Ai1 is located in the first quadrant.
  • the phase is 180°.
  • the vector sum of the two is the first composite signal IFI. is jA2Ar1-A2Ai1, and the phase of jA2Ar1-A2Ai1 is located in the second quadrant.
  • the second adder and subtractor 12 can control the vector addition of the first orthogonal intermediate frequency signal IFQr with a positive phase and the second in-phase intermediate frequency signal IFIi with a positive phase to obtain the second composite signal IFQ.
  • the vector sum of the two and the second composite signal IFQ is jA1Ai1-A1Ar1, jA1Ai1- The phase of A1Ar1 is in the second quadrant.
  • the vector sum of the two and the second composite signal IFQ is jA2Ai1+A2Ar1, and the phase of jA2Ai1+A2Ar1 Located in the first quadrant.
  • both the first composite signal IFI and the second composite signal IFQ include parameters Ar1 and Ai1, the first composite signal IFI and the second composite signal IFQ have the same amplitude.
  • the first composite signal IFI and the second composite signal IFQ can be controlled to have orthogonal phases. .
  • the phase shifter 13 can be used to perform a 90° phase shift on jA1Ar1+A1Ai1 and jA2Ar1-A2Ai1 in the second composite signal IFQ. It can also be said that the phase shifter 13 can be used to perform a 90° phase shift on jA1Ar1+A1Ai1 and jA1Ar1+A1Ai1 in the second composite signal IFQ. Add 90° to the phase of jA2Ar1-A2Ai1.
  • the first signal obtained by mixing the first radio frequency signal A1 with the first local oscillator signal LOI and the second local oscillator signal LOQ can be filtered out, and the second signal can be retained as a useful signal.
  • the retained second signal has the same phase as jA2Ai1+A2Ar1 in the second composite signal IFQ, and is located in the first quadrant.
  • the sixth case takes the first signal as the image interference signal, the second signal as the useful signal, and the quadrant where the useful signal is located as the fourth quadrant.
  • symbol code The first digital signal and the third digital signal input by the generator to the first adder and subtractor 11 are both 0, and the first in-phase intermediate frequency signal IFIr and the second quadrature intermediate frequency signal IFQi are both negative.
  • the second digital signal input by the symbol code generator to the second adder and subtractor 12 is 0, the fourth digital signal is 1, the phase of the first quadrature intermediate frequency signal IFQr is negative, and the phase of the second in-phase intermediate frequency signal IFIi is positive.
  • the first adder and subtractor 11 can control the vector addition of the first in-phase intermediate frequency signal IFIr with a negative phase and the second orthogonal intermediate frequency signal IFQi with a negative phase to obtain the first composite signal IFI.
  • the first in-phase intermediate frequency signal jA1Ar1 with a phase of 90° is inverted, and the phase is 270°;
  • the second orthogonal intermediate frequency signal -A1Ai1 with a phase of 180° is inverted, and the phase is 0°.
  • the phase is 270°; after the second orthogonal intermediate frequency signal A2Ai1 with a phase of 0° is inverted, the phase is 180°.
  • the vector sum of the two and the first composite signal IFI is -jA2Ar1-A2Ai1, the phase of -jA2Ar1-A2Ai1 Located in the third quadrant.
  • the second adder and subtractor 12 can control the vector addition of the first orthogonal intermediate frequency signal IFQr with a negative phase and the second in-phase intermediate frequency signal IFIi with a positive phase to obtain the second composite signal IFQ.
  • the phase is 0°
  • the first orthogonal intermediate frequency signal A2Ar1 with a phase of 0°, after inversion, has a phase of 180°, and after vector addition with the second in-phase intermediate frequency signal jA2Ai1 with a phase of 90°, the vector sum of the two and the second composite signal IFQ is
  • the phases of jA2Ai1-A2Ar1 and jA2Ai1-A2Ar1 are located in the second quadrant.
  • both the first composite signal IFI and the second composite signal IFQ include parameters Ar1 and Ai1, the first composite signal IFI and the second composite signal IFQ have the same amplitude.
  • the first composite signal IFI and the second composite signal IFQ can be controlled to have orthogonal phases. .
  • the phase shifter 13 can be used to perform a 90° phase shift on A1Ai1-jA1Ar1 and -jA2Ar1-A2Ai1 in the first composite signal IFI. It can also be said that the phase shifter 13 can be used to perform a 90° phase shift on A1Ai1-jA1Ar1 in the first composite signal IFI. Add 90° to the phase of -jA2Ar1-A2Ai1.
  • the first signal obtained by mixing the first radio frequency signal A1 with the first local oscillator signal LOI and the second local oscillator signal LOQ can be filtered out, and the second signal can be retained as a useful signal. Furthermore, the retained second signal has the same phase as jA2Ai1-A2Ar1 in the second composite signal IFQ, and is located in the second quadrant.
  • the seventh case takes the first signal as the image interference signal, the second signal as the useful signal, and the quadrant where the useful signal is located as the third quadrant.
  • symbol code The first digital signal input by the generator to the first adder and subtractor 11 is 0, the third digital signal is 1, the phase of the first in-phase intermediate frequency signal IFIr is negative, and the phase of the second quadrature intermediate frequency signal IFQi is positive.
  • the second digital signal and the fourth digital signal input by the symbol code generator to the second adder and subtractor 12 are both 0, and the phases of the first quadrature intermediate frequency signal IFQr and the second in-phase intermediate frequency signal IFIi are both negative.
  • the first adder and subtractor 11 can control the vector addition of the first in-phase intermediate frequency signal IFIr with a negative phase and the second orthogonal intermediate frequency signal IFQi with a positive phase to obtain the first composite signal IFI.
  • the phase is 270°
  • the vector sum of the two is the first
  • the composite signal IFI is -jA1Ar1-A1Ai1
  • the phase of -jA1Ar1-A1Ai1 is located in the third quadrant.
  • the phase is 270°.
  • the vector sum of the two is the first composite signal IFI. It is -jA2Ar1+A2Ai1, and the phase of -jA2Ar1+A2Ai1 is located in the fourth quadrant.
  • the second adder and subtractor 12 can control the vector addition of the negative first quadrature intermediate frequency signal IFQr and the negative second in-phase intermediate frequency signal IFIi to obtain the second composite signal IFQ.
  • the phase is 0°; after the second in-phase intermediate frequency signal jA1Ai1 with a phase of 90° is inverted, the phase is 270°.
  • the phase of A1Ar1, -jA1Ai1+A1Ar1 is located in the fourth quadrant.
  • the first orthogonal intermediate frequency signal A2Ar1 with a phase of 0° has a phase of 180° after inversion; the second in-phase intermediate frequency signal jA2Ai1 with a phase of 90° has a phase of 270° after inversion.
  • the vector sum of the two and the second composite signal IFQ is -jA2Ai1-A2Ar1
  • the phase of -jA2Ai1-A2Ar1 is at The third quadrant.
  • both the first composite signal IFI and the second composite signal IFQ include parameters Ar1 and Ai1, the first composite signal IFI and the second composite signal IFQ have the same amplitude.
  • the first composite signal IFI and the second composite signal IFQ can be controlled to have orthogonal phases. .
  • the phase shifter 13 can be used to perform a 90° phase shift on -jA1Ar1-A1Ai1 and -jA2Ar1+A2Ai1 in the first composite signal IFI. It can also be said that the phase shifter 13 can be used to perform a 90° phase shift on -jA1Ar1 in the first composite signal IFI.
  • the phases of -A1Ai1 and -jA2Ar1+A2Ai1 add 90°.
  • the first signal obtained by mixing the first radio frequency signal A1 with the first local oscillator signal LOI and the second local oscillator signal LOQ can be filtered out, and the second signal can be retained as a useful signal.
  • the retained second signal has the same phase as -jA2Ai1-A2Ar1 in the second composite signal IFQ, and is located in the third quadrant.
  • the eighth case takes the first signal as the image interference signal, the second signal as the useful signal, and the quadrant where the useful signal is located as the second quadrant.
  • symbol code The first digital signal and the third digital signal input by the generator to the first adder and subtractor 11 are both 1, and the phases of the first in-phase intermediate frequency signal IFIr and the second quadrature intermediate frequency signal IFQi are both positive.
  • the second digital signal input by the symbol code generator to the second adder and subtractor 12 is 1, the fourth digital signal is 0, the phase of the first quadrature intermediate frequency signal IFQr is positive, and the phase of the second in-phase intermediate frequency signal IFIi is negative.
  • the first adder and subtractor 11 can control the vector addition of the first in-phase intermediate frequency signal IFIr with a positive phase and the second orthogonal intermediate frequency signal IFQi with a positive phase to obtain the first composite signal IFI.
  • the vector sum of the two is the first composite signal IFI is jA1Ar1-A1Ai1, and the phase of jA1Ar1-A1Ai1 is located in the second quadrant.
  • the vector sum of the two and the first composite signal IFI is jA2Ar1+A2Ai1, jA2Ar1+A2Ai1
  • the phase is in the first quadrant.
  • the second adder and subtractor 12 can control the vector addition of the first orthogonal intermediate frequency signal IFQr with a positive phase and the second in-phase intermediate frequency signal IFIi with a negative phase to obtain the second composite signal IFQ.
  • the phase is 270°
  • the vector sum of the two is the second composite
  • the phase is 270°.
  • the vector sum of the two and the second composite signal IFQ is The phases of A2Ar1-jA2Ai1 and A2Ar1-jA2Ai1 are located in the fourth quadrant.
  • both the first composite signal IFI and the second composite signal IFQ include parameters Ar1 and Ai1, the first composite signal IFI and the second composite signal IFQ have the same amplitude.
  • the first composite signal IFI and the second composite signal IFQ can be controlled to have orthogonal phases. .
  • the phase shifter 13 can be used to perform a 90° phase shift on jA1Ar1-A1Ai1 and jA2Ar1+A2Ai1 in the first composite signal IFI. It can also be said that the phase shifter 13 can be used to perform a 90° phase shift on jA1Ar1-A1Ai1 and jA1Ar1-A1Ai1 in the first composite signal IFI. The phase of jA2Ar1+A2Ai1 is added by 90°.
  • the first signal obtained by mixing the first radio frequency signal A1 with the first local oscillator signal LOI and the second local oscillator signal LOQ can be filtered out, and the second signal can be retained as a useful signal.
  • the retained second signal has the same phase as A2Ar1-jA2Ai1 in the second composite signal IFQ, and is located in the fourth quadrant.
  • the above example takes the first local oscillator signal LOI as sin( ⁇ LO t) and the second local oscillator signal LOQ as cos( ⁇ LO t) to list various situations of filtering out image interference signals.
  • the first local oscillator signal LOI and the second local oscillator signal LOQ can also be other, as long as the first local oscillator signal LOI and the second local oscillator signal LOQ are orthogonal.
  • the embodiments of the present application do not limit the specific circuit structures of the first adder and subtractor 11 , the second adder and subtractor 12 and the differential circuit 14 mentioned above.
  • the symbol code generator may include a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a first inverter D1, and a second inverter D2.
  • the first adder and subtractor 11 may include a first differential circuit OP1 and a second differential circuit OP2.
  • the first differential circuit OP1 and the second differential circuit OP2 may be, for example, operational amplifiers.
  • the symbol code generator is used to generate the first initial digital signal S1; the first switch K1 and the second switch K2 are connected in parallel, and the first switch K1 is used to receive the first in-phase intermediate frequency signal IFIr and the first initial digital signal S1.
  • the second switch K2 is coupled to the first inverter D1 and is used for receiving the first in-phase intermediate frequency signal IFIr and the inverted first initial digital signal S1.
  • the symbol code generator is also used to generate a third initial digital signal S3; the third switch K3 is connected in parallel with the fourth switch K4, and the third switch K3 is used to receive the second orthogonal intermediate frequency signal IFQi and the third initial digital signal S3.
  • the fourth switch K4 is coupled to the second inverter D2 and is used for receiving the second quadrature intermediate frequency signal IFQi and the inverted third initial digital signal S3.
  • the output sides of the first switch K1 and the second switch K2 are coupled to the input side of the first differential circuit OP1, the output sides of the third switch K3 and the fourth switch K4 are coupled to the input side of the second differential circuit OP2, and the first differential circuit The output sides of both OP1 and the second differential circuit OP2 are coupled to the input side of the differential circuit 14 .
  • the first switch K1 is coupled to the positive input terminal of the first differential circuit OP1, and the second switch K2 is coupled to the negative input terminal of the first differential circuit OP1, then the input to the first switch K1 and the second switch
  • the first initial digital signal S1 of K2 is 1. If the required first digital signal S1r is 1, the first switch K1 can be controlled to be turned on and the second switch K2 to be turned off.
  • the first in-phase intermediate frequency signal IFIr is input to the positive terminal of the first differential circuit OP1 through the first switch K1.
  • the first differential circuit OP1 inverts the first in-phase intermediate frequency signal IFIr and outputs it.
  • the first switch K1 is coupled to the negative input terminal of the first differential circuit OP1, and the second switch K2 is coupled to the positive input terminal of the first differential circuit OP1, then the input to the first switch K1 and the first differential circuit OP1
  • the first initial digital signal S1 of the second switch K2 is 0. If the required first digital signal S1r is 1, the first switch K1 can be controlled to be turned off, the second switch K2 can be controlled to be turned on, and the first in-phase intermediate frequency signal IFIr is input to the positive terminal of the first differential circuit OP1 through the second switch K2.
  • the first differential circuit OP1 inverts the first in-phase intermediate frequency signal IFIr and outputs it.
  • the third switch K3 is coupled to the positive input terminal of the second differential circuit OP2, and the fourth switch K4 is coupled to the negative input terminal of the second differential circuit OP2, then the input to the third switch K3 and the fourth switch
  • the third initial digital signal S3 of K4 is 1. If the required third digital signal S1i is 1, the third switch K3 can be controlled to be turned on, the fourth switch K4 can be turned off, and the second orthogonal intermediate frequency signal IFQi is input to the positive terminal of the second differential circuit OP2 through the third switch K3.
  • the third switch K3 can be controlled to be turned off, the fourth switch K4 can be controlled to be turned on, and the second orthogonal intermediate frequency signal IFQi passes through the
  • the four-switch K4 is input to the negative input terminal of the second differential circuit OP2, and the second differential circuit OP2 inverts the second orthogonal intermediate frequency signal IFQi and outputs it.
  • the third switch K3 is coupled to the negative input terminal of the second differential circuit OP2, and the fourth switch K4 is coupled to the positive input terminal of the second differential circuit OP2, then the input to the third switch K3 and the second differential circuit OP2
  • the third initial digital signal S3 of the four-switch K4 is 0. If the required third digital signal S1i is 1, the third switch K3 can be controlled to be turned off, the fourth switch K4 can be controlled to be turned on, and the second orthogonal intermediate frequency signal IFQi is input to the positive terminal of the second differential circuit OP2 through the fourth switch K4.
  • the third switch K3 can be controlled to be turned on, the fourth switch K4 can be turned off, and the second orthogonal intermediate frequency signal IFQi passes through the
  • the three switches K3 are input to the negative input terminal of the second differential circuit OP2, and the second differential circuit OP2 inverts the second orthogonal intermediate frequency signal IFQi and outputs it.
  • the first composite signal IFI is obtained by vector summing the signals output by the first differential circuit OP1 and the second differential circuit OP2.
  • the symbol code generator may include a fifth switch K5, a sixth switch K6, a seventh switch K7, an eighth switch K8, a third inverter D3, and a fourth inverter D4.
  • the second adder and subtractor 12 may include a third differential circuit OP3 and a fourth differential circuit OP4.
  • the third differential circuit OP3 and the fourth differential circuit OP4 may be, for example, operational amplifiers.
  • the symbol code generator is used to generate the second initial digital signal S2; the fifth switch K5 and the sixth switch K6 are connected in parallel.
  • the fifth switch K5 is used to receive the first orthogonal intermediate frequency signal IFQr and the second initial digital signal S2.
  • the sixth switch K6 is coupled to the third inverter D3 for receiving the first quadrature intermediate frequency signal IFQr and the inverted second initial digital signal S2.
  • the symbol code generator is also used to generate a fourth initial digital signal S4; the seventh switch K7 and the eighth switch K8 are connected in parallel.
  • the seventh switch K7 is used to receive the second in-phase intermediate frequency signal IFIi and the fourth initial digital signal S4.
  • the eighth switch K8 is coupled to the fourth inverter D4 and is used for receiving the second in-phase intermediate frequency signal IFIi and the inverted fourth initial digital signal S4.
  • the output sides of the fifth switch K5 and the sixth switch K6 are coupled to the input side of the third differential circuit OP3, the output sides of the seventh switch K7 and the eighth switch K8 are coupled to the input side of the fourth differential circuit OP4, and the third differential circuit The output sides of OP3 and the fourth differential circuit OP4 are both coupled to the input side of the differential circuit 14 .
  • the fifth switch K5 is coupled to the positive input terminal of the third differential circuit OP3, and the sixth switch K6 is coupled to the negative input terminal of the third differential circuit OP3, then the fifth switch K5 and the sixth switch K6 receive The second initial digital signal S2 is 1. If the required second digital signal S2r is 1, the fifth switch K5 can be controlled to be turned on and the sixth switch K6 to be turned off.
  • the first orthogonal intermediate frequency signal IFQr is input to the positive terminal of the third differential circuit OP3 through the fifth switch K5.
  • the third differential circuit OP3 inverts the first orthogonal intermediate frequency signal IFQr and outputs it.
  • the fifth switch K5 is coupled to the negative input terminal of the third differential circuit OP3, and the sixth switch K6 is coupled to the positive input terminal of the third differential circuit OP3, then the fifth switch K5 and the sixth switch
  • the second initial digital signal S2 received by K6 is 0. If the required second digital signal S2r is 1, the fifth switch K5 can be controlled to be turned off, the sixth switch K6 can be controlled to be turned on, and the first orthogonal intermediate frequency signal IFQr is input to the positive terminal of the third differential circuit OP3 through the sixth switch K6.
  • the fifth switch K5 can be controlled to be turned on, the sixth switch K6 can be turned off, and the first orthogonal intermediate frequency signal IFQr passes through the
  • the fifth switch K5 is input to the negative input terminal of the third differential circuit OP3, and the third differential circuit OP3 inverts the first orthogonal intermediate frequency signal IFQr and outputs it.
  • the seventh switch K7 can be controlled to be turned on, the eighth switch K8 can be turned off, and the second in-phase intermediate frequency signal IFIi is input to the positive input of the fourth differential circuit OP4 through the seventh switch K7 terminal, and output from the fourth differential circuit OP4; if the required fourth digital signal S2i is 0, the seventh switch K7 can be controlled to be turned off, the eighth switch K8 can be controlled to be turned on, and the second in-phase intermediate frequency signal IFIi passes through the eighth switch K8 is input to the negative input terminal of the fourth differential circuit OP4, and the fourth differential circuit OP4 inverts the second in-phase intermediate frequency signal IFIi and outputs it.
  • the seventh switch K7 is coupled to the negative input terminal of the fourth differential circuit OP4, and the eighth switch K8 is coupled to the positive input terminal of the fourth differential circuit OP4, then the seventh switch K7 and the eighth switch
  • the fourth initial digital signal S4 received by K8 is 0. If the required fourth digital signal S2i is 1, the seventh switch K7 can be controlled to be turned off, the eighth switch K8 can be controlled to be turned on, and the second in-phase intermediate frequency signal IFIi is input to the positive input of the fourth differential circuit OP4 through the eighth switch K8. terminal, and output from the fourth differential circuit OP4.
  • the seventh switch K7 can be controlled to be turned on, the eighth switch K8 can be turned off, and the second in-phase intermediate frequency signal IFIi is input to the negative input of the fourth differential circuit OP4 through the seventh switch K7 terminal, the fourth differential circuit OP4 inverts the second in-phase intermediate frequency signal IFIi and outputs it.
  • the second composite signal IFQ is obtained by vector summing the signals output by the third differential circuit OP3 and the fourth differential circuit OP4.
  • the embodiment of the present application can determine that the first digital signal S1r, the second digital signal S2r, the third digital signal S1i and the fourth digital signal S2r are 1 or 1 based on the quadrant control code and the image suppression mode. 0, to control the first switch K1, the second switch K2, the third switch K3, the fourth switch K4, the fifth switch K5, the sixth switch K6, the seventh switch K7 and the eighth switch K8 to be on or off, and Execute one of the four sets of truth tables previously described.
  • the third adjustable radio frequency amplifier VGA3, the fourth adjustable radio frequency amplifier VGA4, the fifth adjustable radio frequency amplifier VGA5, and the sixth adjustable radio frequency amplifier VGA6 can be combined with the symbol code generator integrated together.
  • the third adjustable radio frequency amplifier VGA3 includes a first sub-amplifier and a second sub-amplifier
  • the fourth adjustable radio frequency amplifier VGA4 includes a third sub-amplifier and a fourth sub-amplifier
  • the fifth adjustable radio frequency amplifier VGA5 includes a fifth sub-amplifier and a fourth sub-amplifier.
  • Six sub-amplifiers, the sixth adjustable radio frequency amplifier VGA6 includes a seventh sub-amplifier and an eighth sub-amplifier.
  • the symbol code generator includes a first AND gate M1, a second AND gate M2, a third AND gate M3, a fourth AND gate M4, a fifth inverter, and a sixth inverter.
  • the first adder and subtractor 11 includes a fifth differential circuit OP5 and a sixth differential circuit OP6.
  • the first AND gate M1 is used to receive the third gain r2 and the first initial digital signal S1; the output side of the first AND gate M1 is coupled to the first sub-amplifier.
  • the input side of the first sub-amplifier receives the first in-phase intermediate frequency signal IFIr, and the output side is coupled to the fifth differential circuit OP5.
  • the second AND gate M2 is used to receive the fourth gain i2 and the third initial digital signal S3; the output side of the second AND gate M2 is coupled to the fifth sub-amplifier.
  • the input side of the fifth sub-amplifier receives the second quadrature intermediate frequency signal IFQi, and the output side is coupled to the sixth differential circuit OP6.
  • the third AND gate M3 is used to receive the fourth gain i2 and the third initial digital signal S3 inverted through the fifth inverter; the output side of the third AND gate M3 is coupled to the sixth sub-amplifier.
  • the input side of the sixth sub-amplifier receives the second quadrature intermediate frequency signal IFQi, and the output side is coupled to the fifth differential circuit OP5.
  • the fourth AND gate M4 is used to receive the third gain r2 and the first initial digital signal S1 inverted through the sixth inverter; the output side of the fourth AND gate M4 is coupled to the second sub-amplifier.
  • the input side of the second sub-amplifier receives the first in-phase intermediate frequency signal IFIr, and the output side is coupled to the sixth differential circuit OP6.
  • the output side of the fifth differential circuit OP5 and the output side of the sixth differential circuit OP6 are both coupled to the input side of the differential circuit 14 .
  • the first initial digital signal S1 (which can also be said to be the first digital signal S1r) with a third gain r2 and a sum of 1 is input to the first sub-amplifier through the first AND gate M1, and the first in-phase intermediate frequency signal IFIr passes through the first sub-amplifier. Input to the positive input terminal of the fifth differential circuit OP5, and output from the fifth differential circuit OP5. If the required first digital signal S1r is 0, enable can be input to the second sub-amplifier without inputting enable to the first sub-amplifier, so that the first sub-amplifier does not work and the second sub-amplifier works normally.
  • the first initial digital signal S1 of 1 and the first digital signal S1r of 0 are obtained after inversion.
  • the third gain r2 and the first digital signal S1r of 0 are input to the second sub-amplifier through the fourth AND gate M4.
  • the in-phase intermediate frequency signal IFIr is input to the negative input terminal of the sixth differential circuit OP6 through the second sub-amplifier, is inverted in the sixth differential circuit OP6, and then output from the sixth differential circuit OP6.
  • the first initial digital signal S1 received by the AND gate M1 and the fourth AND gate M4 is 0. If the required first digital signal S1r is 1, enable can be input to the second sub-amplifier without inputting enable to the first sub-amplifier, so that the first sub-amplifier does not work and the second sub-amplifier works normally.
  • the first initial digital signal S1 of 0 and the first digital signal S1r of 1 are obtained after inversion.
  • the third gain r2 and the first digital signal S1r of 1 are input to the second sub-amplifier through the fourth AND gate M4.
  • the in-phase intermediate frequency signal IFIr is input to the positive input terminal of the sixth differential circuit OP6 through the second sub-amplifier, and is output from the sixth differential circuit OP6. If the required first digital signal S1r is 0, enable can be input to the first sub-amplifier but not to the second sub-amplifier, so that the first sub-amplifier operates normally and the second sub-amplifier does not operate.
  • the first initial digital signal S1 (which can also be said to be the first digital signal S1r) with the sum of the third gain r2 and 0 is input to the first sub-amplifier through the first AND gate M1, and the first in-phase intermediate frequency signal IFIr passes through the first sub-amplifier.
  • the negative input terminal input to the fifth differential circuit OP5 is inverted in the fifth differential circuit OP5 and then output from the fifth differential circuit OP5.
  • the third initial digital signal S3 (which can also be said to be the third digital signal S1i) with the sum of the fourth gain i2 and 1 is input to the fifth sub-amplifier through the second AND gate M2, and the second orthogonal intermediate frequency signal IFQi passes through the fifth sub-amplifier. Input to the positive input terminal of the sixth differential circuit OP6, and output from the sixth differential circuit OP6. If the required third digital signal S1i is 0, enable can be input to the sixth sub-amplifier but not to the fifth sub-amplifier, so that the fifth sub-amplifier does not work and the sixth sub-amplifier works normally.
  • the third initial digital signal S3 of 1 and the third digital signal S1i of 0 are obtained after inversion.
  • the fourth gain i2 and the third digital signal S1i of 0 are input to the sixth sub-amplifier through the third AND gate M3.
  • the two orthogonal intermediate frequency signals IFQi are input to the negative input terminal of the fifth differential circuit OP5 through the sixth sub-amplifier, are inverted in the fifth differential circuit OP5, and then output from the fifth differential circuit OP5.
  • the fourth gain i2 and the third digital signal S1i of 1 are input to the sixth sub-amplifier through the third AND gate M3.
  • the two orthogonal intermediate frequency signals IFQi are input to the positive input end of the fifth differential circuit OP5 through the sixth sub-amplifier, and are output from the fifth differential circuit OP5. If the required third digital signal S1i is 0, enable can be input to the fifth sub-amplifier but not to the sixth sub-amplifier, so that the fifth sub-amplifier operates normally and the sixth sub-amplifier does not operate.
  • the third initial digital signal S3 (which can also be said to be the third digital signal S1i) with the sum of the fourth gain i2 and 0 is input to the fifth sub-amplifier through the second AND gate M2, and the second orthogonal intermediate frequency signal IFQi passes through the fifth sub-amplifier.
  • the negative input terminal input to the sixth differential circuit OP6 is inverted in the sixth differential circuit OP6 and then output from the sixth differential circuit OP6.
  • the first composite signal IFI is obtained by vector summing the signals output by the fifth differential circuit OP5 and the sixth differential circuit OP6.
  • control circuit 15 will not input enable to the second sub-amplifier when the first sub-amplifier input is enabled; and when the fifth sub-amplifier input is enabled, the control circuit 15 will not enable the input to the sixth sub-amplifier. Amplifier input enabled. Therefore, compared with the previous embodiment, at the same time, the power consumption of the receiver 101 will not be additionally increased.
  • the symbol code generator includes a fifth AND gate M5, a sixth AND gate M6, a seventh AND gate M7, an eighth AND gate M8, a seventh inverter, and an eighth inverter.
  • the second adder-subtractor 12 includes a seventh differential circuit OP7 and an eighth differential circuit OP8.
  • the fifth AND gate M5 is used to receive the third gain r2 and the second initial digital signal S2; the output side of the fifth AND gate M5 is coupled to the third sub-amplifier.
  • the input side of the third sub-amplifier receives the first quadrature intermediate frequency signal IFQr, and the output side is coupled to the seventh differential circuit OP7.
  • the sixth AND gate M6 is used to receive the fourth gain i2 and the fourth initial digital signal S4; the output side of the sixth AND gate M6 is coupled to the seventh sub-amplifier.
  • the input side of the seventh sub-amplifier receives the second in-phase intermediate frequency signal IFIi, and the output side is coupled to the eighth differential circuit OP8.
  • the seventh AND gate M7 is used to receive the fourth gain i2 and the fourth initial digital signal S4 inverted through the seventh inverter; the output side of the seventh AND gate M7 is coupled to the eighth sub-amplifier.
  • the input side of the eighth sub-amplifier receives the second in-phase intermediate frequency signal IFIi, and the output side is coupled to the seventh differential circuit OP7.
  • the eighth AND gate M8 is used to receive the third gain r2 and the second initial digital signal S2 inverted through the eighth inverter; the output side of the eighth AND gate M8 is coupled to the fourth sub-amplifier.
  • the input side of the fourth sub-amplifier receives the first quadrature intermediate frequency signal IFQr, and the output side is coupled to the eighth differential circuit OP8.
  • the output side of the seventh differential circuit OP7 and the output side of the eighth differential circuit OP8 are both coupled to the input side of the differential circuit 14 .
  • the output side of the third sub-amplifier is coupled to the positive input terminal of the seventh differential circuit OP7, and the output side of the fourth sub-amplifier is coupled to the negative input terminal of the eighth differential circuit OP8, then the fifth AND gate
  • the second initial digital signal S2 received by M5 and the eighth AND gate M8 is 1. If the required second digital signal S2r is 1, enable can be input to the third sub-amplifier but not to the fourth sub-amplifier, so that the third sub-amplifier operates normally and the fourth sub-amplifier does not operate.
  • the second initial digital signal S2 (which can also be said to be the second digital signal S2r) with a third gain r2 sum of 1 is input to the third sub-amplifier through the fifth AND gate M5, and the first quadrature intermediate frequency signal IFQr passes through the third sub-amplifier. Input to the positive input terminal of the seventh differential circuit OP7, and output from the seventh differential circuit OP7. If the required second digital signal S2r is 0, enable can be input to the fourth sub-amplifier but not to the third sub-amplifier, so that the third sub-amplifier does not work and the fourth sub-amplifier works normally.
  • the second initial digital signal S2 of 1 and the second digital signal S2r of 0 are obtained after inversion.
  • the third gain r2 and the second digital signal S2r of 0 are input to the fourth sub-amplifier through the eighth AND gate M8.
  • a quadrature intermediate frequency signal IFQr is input to the negative input terminal of the eighth differential circuit OP8 through the fourth sub-amplifier, is inverted in the eighth differential circuit OP8, and then output from the eighth differential circuit OP8.
  • the output side of the third sub-amplifier is coupled to the negative input terminal of the seventh differential circuit OP7, and the output side of the fourth sub-amplifier is coupled to the positive input terminal of the eighth differential circuit OP8, then the fifth The second initial digital signal S2 received by the AND gate M5 and the eighth AND gate M8 is 0. If the required second digital signal S2r is 1, enable can be input to the fourth sub-amplifier but not to the third sub-amplifier, so that the third sub-amplifier does not work and the fourth sub-amplifier works normally. The second initial digital signal S2 of 0 and the second digital signal S2r of 1 are obtained after inversion.
  • the third gain r2 and the second digital signal S2r of 1 are input to the fourth sub-amplifier through the eighth AND gate M8.
  • a quadrature intermediate frequency signal IFQr is input to the positive input end of the eighth differential circuit OP8 through the fourth sub-amplifier, and is output from the eighth differential circuit OP8. If the required second digital signal S2r is 0, enable can be input to the third sub-amplifier but not to the fourth sub-amplifier, so that the third sub-amplifier operates normally and the fourth sub-amplifier does not operate.
  • the second initial digital signal S2 (which can also be said to be the second digital signal S2r) with the sum of the third gain r2 and 0 is input to the third sub-amplifier through the fifth AND gate M5, and the first orthogonal intermediate frequency signal IFQr passes through the third sub-amplifier.
  • the negative input terminal input to the seventh differential circuit OP7 is inverted in the seventh differential circuit OP7 and then output from the seventh differential circuit OP7.
  • the sixth AND gate The fourth initial digital signal S4 received by M6 and the seventh AND gate M7 is 1. If the required fourth digital signal S2i is 1, enable can be input to the seventh sub-amplifier but not to the eighth sub-amplifier, so that the seventh sub-amplifier operates normally and the eighth sub-amplifier does not operate.
  • the fourth initial digital signal S4 (which can also be said to be the fourth digital signal S2i) with the sum of the fourth gain i2 and 1 is input to the seventh sub-amplifier through the sixth AND gate M6, and the second in-phase intermediate frequency signal IFIi is input through the seventh sub-amplifier. to the positive input terminal of the eighth differential circuit OP8, and is output from the eighth differential circuit OP8. If the required fourth digital signal S2i is 0, enable can be input to the eighth sub-amplifier but not to the seventh sub-amplifier, so that the seventh sub-amplifier does not work and the eighth sub-amplifier works normally.
  • the fourth initial digital signal S4 of 1 and the fourth digital signal S2i of 0 are obtained after inversion.
  • the fourth gain i2 and the fourth digital signal S2i of 0 are input to the eighth sub-amplifier through the seventh AND gate M7.
  • the two in-phase intermediate frequency signals IFIi are input to the negative input terminal of the seventh differential circuit OP7 through the eighth sub-amplifier, are inverted in the seventh differential circuit OP7, and then output from the seventh differential circuit OP7.
  • the sixth The fourth initial digital signal S4 received by the AND gate M6 and the seventh AND gate M7 is 0. If the required fourth digital signal S2i is 1, enable can be input to the eighth sub-amplifier but not to the seventh sub-amplifier, so that the seventh sub-amplifier does not work and the eighth sub-amplifier works normally.
  • the fourth initial digital signal S4 of 0 and the fourth digital signal S2i of 1 are obtained after inversion.
  • the fourth gain i2 and the fourth digital signal S2i of 1 are input to the eighth sub-amplifier through the seventh AND gate M7.
  • the two in-phase intermediate frequency signals IFIi are input to the positive input terminal of the seventh differential circuit OP7 through the eighth sub-amplifier, and are output from the seventh differential circuit OP7. If the required fourth digital signal S2i is 0, enable can be input to the seventh sub-amplifier but not to the eighth sub-amplifier, so that the seventh sub-amplifier operates normally and the eighth sub-amplifier does not operate.
  • the fourth initial digital signal S4 (which can also be said to be the fourth digital signal S2i) with a sum of the fourth gain i2 and 0 is input to the seventh sub-amplifier through the sixth AND gate M6, and the second in-phase intermediate frequency signal IFIi is input through the seventh sub-amplifier.
  • the negative input terminal of the eighth differential circuit OP8 after being inverted in the eighth differential circuit OP8, it is output from the eighth differential circuit OP8.
  • the second composite signal IFQ is obtained by vector summing the signals output by the seventh differential circuit OP7 and the eighth differential circuit OP8.
  • control circuit 15 since the control circuit 15 will not input enable to the fourth sub-amplifier when the input of the third sub-amplifier is enabled; and when the input of the seventh sub-amplifier is enabled, the control circuit 15 will not enable the input to the eighth sub-amplifier. Amplifier input enabled. Therefore, compared with the previous embodiment, at the same time, the power consumption of the receiver 101 will not be additionally increased.
  • the above two embodiments show that the two symbol code controllers input the first digital signal S1r, the second digital signal S2r, the third digital signal S1i and the fourth digital signal to the first adder and subtractor 11 and the second adder and subtractor 12
  • S2i of course, other circuit structures can also be used to input the first digital signal S1r, the second digital signal S2r, the third digital signal S1i and the fourth digital signal S2i to the first adder and subtractor 11 and the second adder and subtractor 12.
  • the embodiment of the present application does not limit this, as long as it inputs the first digital signal S1r, the second digital signal S2r, the third digital signal S1i and the fourth digital signal S2i to the first adder and subtractor 11 and the second adder and subtractor 12
  • the rules are consistent with the aforementioned four sets of truth tables, and they all fall within the protection of this application.

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Abstract

本申请实施例提供了一种接收机、射频收发器和终端，涉及集成电路技术领域，可以利用接收机中既有的器件，代替矢量合成移相器调节射频信号的相位。接收机接收的射频信号经第一可调射频放大器放大后输出第一射频放大信号，经第二可调射频放大器放大后输出第二射频放大信号。第一射频放大信号经第一同相混频器混频后输出第一同相中频信号，经第一正交混频器混频后输出第一正交中频信号；第二射频放大信号经第二正交混频器混频后输出第二正交中频信号，经第二同相混频器混频后输出第二同相中频信号。第一同相中频信号和第二正交中频信号通过第一加减器进行可选择的加或减；第一正交中频信号和所述第二同相中频信号通过第二加减器进行可选择的加或减。

Description

接收机、射频收发器和终端 技术领域
本申请涉及集成电路技术领域，尤其涉及一种接收机、射频收发器和终端。
背景技术
应现代无线通讯高速率的需求，例如，第五代移动通信技术(5th Generation Mobile Communication Technology，5G)通信的毫米波段，太赫兹(Tera Hertz，THz)成像等，使得无线通讯系统的工作频率越来越高。
为克服高频无线传输的高路径损耗，相控阵(phased-array)技术被广泛应用于雷达、通信等无线通讯系统中，例如，相控阵接收机。其中，传统的相控阵接收机包括矢量合成移相器、可变增益放大器(Variable gain amplifier，VGA)和混频器。矢量合成移相器将通过不同天线接收到的信号调整至相同相位并进行叠加，以增强接收到的信号混频器的信噪比。可变增益放大器可以用来实现对每条接收路径上的信号的幅相控制。混频器可以将射频信号下混频至基带，以实现信号解调。
然而，矢量合成移相器和可变增益放大器独立工作，导致接收机所在的电路功耗增加。
发明内容
为了解决上述技术问题，本申请提供一种接收机、射频收发器和终端，可以利用接收机中既有的器件，代替传统的矢量合成移相器，来调节接收到的射频信号的相位。
第一方面，本申请提供一种接收机，该接收机包括第一可调射频放大器、第二可调射频放大器、第一同相混频器、第一正交混频器、第二正交混频器、第二同相混频器、第一加减器、以及第二加减器。接收机用于接收射频信号。射频信号经过第一可调射频放大器放大后输出第一射频放大信号，射频信号经过第二可调射频放大器放大后输出第二射频放大信号。第一射频放大信号经过第一同相混频器混频后输出第一同相中频信号，经过第一正交混频器混频后输出第一正交中频信号；第二射频放大信号经过第二正交混频器混频后输出第二正交中频信号，经过第二同相混频器混频后输出第二同相中频信号。第一同相中频信号和第二正交中频信号通过第一加减器进行可选择的加或者减后输出第一合成信号；第一正交中频信号和所述第二同相中频信号通过第二加减器进行可选择的加或者减后输出第二合成信号。
本领域的技术人员应该知道，矢量合成移相器1012的工作原理是通过改变正交的两路信号的比值，以实现移相功能。
对于第一加减器，其接收正交的第一同相中频信号和第二正交中频信号。并且，由于形成第一同相中频信号的射频信号经第一可调射频放大器进行放大，形成第二正交中频信号的射频信号经第二可调射频放大器进行放大。因此，可以通过调节第一可调射频 放大器和第二可调射频放大器的增益，在调节第一同相中频信号和第二正交中频信号的幅度的基础上，调节正交的第一同相中频信号和第二正交中频信号的比值，从而代替现有的矢量合成移相器，实现移相功能。
对于第二加减器，其接收正交的第一正交中频信号和第二同相中频信号。并且，由于形成第一正交中频信号的射频信号经第一可调射频放大器进行放大，形成第二同相中频信号的射频信号经第二可调射频放大器进行放大。因此，可以通过调节第一可调射频放大器和第二可调射频放大器的增益，在调节第一正交中频信号和第二同相中频信号的幅度的基础上，调节正交的第一正交中频信号和第二同相中频信号的比值，从而代替现有的矢量合成移相器，实现移相功能。
综上，本申请可以利用既有的第一可调射频放大器、第二可调射频放大器、第一同相混频器、第一正交混频器、第二正交混频器、第二同相混频器、第一加减器和第二加减器，代替传统的矢量合成移相器，来调节接收到的射频信号的相位，节省接收机的版图面积和功耗。并且，由于本申请将实现放大功能、移相功能和混频功能的第一可调射频放大器、第二可调射频放大器、第一同相混频器、第一正交混频器、第二正交混频器、第二同相混频器、第一加减器和第二加减器合为一体，大幅提高了接收机的集成度，从而降低接收机中的寄生电容和寄生电感。
此外，第一可调射频放大器和第二可调射频放大器还可以对射频信号的幅度进行调节。并且，由于第一加减器通过矢量合成，可选择地对第一同相中频信号和第二正交中频信号进行相加或相减；第二加减器通过矢量合成，可选择地对第一正交中频信号和第二同相中频信号进行相加或相减。而第一同相中频信号和第一正交中频信号经第一可调射频放大器放大得到，第二正交中频信号和第二同相中频信号经第二可调射频放大器放大得到。因此，即使改变第一可调射频放大器和/或第二可调射频放大器的增益，第一同相中频信号和第二正交中频信号的矢量合成结果，与第一正交中频信号和第二同相中频信号的矢量合成结果的幅度始终相同。
在一些可能的实现方式中，第一可调射频放大器以可调的第一增益对射频信号进行放大；第二可调射频放大器以可调的第二增益对射频信号进行放大。可以根据实际需要的幅度和相位，设计第一增益和第二增益的比特数。由于第一增益和第二增益的比特数本身包含多个状态。因此，在通过调节第一增益和第二增益的大小，实现调节射频信号的相位时，可以无需额外增加控制电路的比特数。
例如，第一增益的比特数为3，包括000、001、010、011、100、101、110、111等8个状态。第二增益的比特数为3，包括000、001、010、011、100、101、110、111等8个状态。
在一些可能实现的方式中，第一射频放大信号可和第一本振信号经过第一同相混频器混频后，输出第一同相中频信号。第一射频放大信号和第二本振信号经过第一正交混频器混频后，输出第一正交中频信号。第二射频放大信号和第二本振信号经过第二正交混频器混频后，输出第二正交中频信号。第二射频放大信号和第一本振信号经过第二同相混频器混频后，输出第二同相中频信号。并且，第一本振信号与第二本振信号正交，使得第一同相中频信号与第二正交中频信号正交，第一正交中频信号与第二同相中频信 号正交；第一同相中频信号的相位与第二同相中频信号的相位相同，第一正交中频信号的相位与第二正交中频信号的相位相同。
在一些可能实现的方式中，接收机还包括控制电路，控制电路包括控制码生成器，控制码生成器用于向第一可调射频放大器输入第一增益，向第二可调射频放大器输入第二增益。一方面，控制电路可以通过输出的第一增益和第二增益，使第一可调射频放大器和第二可调射频放大器具有可变增益的功能，以调节射频信号的幅度和相位。
在一些可能实现的方式中，控制电路还包括符号码生成器，符号码生成器用于向第一加减器输入第一数字信号和第三数字信号，向第二加减器输入第二数字信号和第四数字信号。第一数字信号用于决定第一同相中频信号的相位为正或为负；第二数字信号用于决定第一正交中频信号的相位为正或为负；第三数字信号用于决定第二正交中频信号的相位为正或为负；第四数字信号用于决定第二同相中频信号的相位为正或为负。
例如，第一数字信号为1，第一同相中频信号的相位为正；第一数字信号为0，第一同相中频信号的相位为负；第二数字信号为1，第一正交中频信号的相位为正；第二数字信号为0，第一正交中频信号的相位为负；第三数字信号为1，第二正交中频信号相位为正；第三数字信号为0，第二正交中频信号相位为负；第四数字信号为1，第二同相中频信号相位为正；第四数字信号为0，第二同相中频信号相位为负。
在一些可能实现的方式中，根据第一数字信号和第三数字信号，第一加减器对相位为正/负的第一同相中频信号与相位为正/负的第二正交中频信号进行矢量合成，得到第一合成信号。也可以说，第一加减器对相位为正的第一同相中频信号与相位为正的第二正交中频信号相加或相减，或者，第一加减器对相位为负的第一同相中频信号与相位为正的第二正交中频信号相加或相减，得到第一合成信号。
根据第二数字信号和第四数字信号，第二加减器对相位为正/负的第一正交中频信号与相位为正/负的第二同相中频信号进行矢量合成，得到第二合成信号。也可以说，第二加减器对相位为正的第一正交中频信号与相位为正的第二同相中频信号相加或相减，或者，第二加减器对相位为负的第一正交中频信号与相位为正的第二同相中频信号相加或相减，得到第二合成信号。
进一步的，由于第一合成信号和第二合成信号均包括以第一增益和第二增益放大得到的中频信号，因此，第一合成信号和第二合成信号具有相同的幅度。基于第一数字信号、第二数字信号、第三数字信号和第四数字信号，可以控制第一合成信号与第二合成信号具有正交的相位。因此，接收机还包括差分电路和移相器。移相器耦合于第一加减器与差分电路之间，用于对第一合成信号进行90°移相；或者，移相器耦合于第二加减器与差分电路之间，用于对第二合成信号进行90°移相。差分电路用于对第二合成信号和移相后的第一合成信号，或者对第一合成信号和移相后的第二合成信号进行相加，以滤除第一合成信号和第二合成信号中的镜像干扰信号。
在一些可能实现的方式中，移相器可以与差分电路的正输入端耦合；或者，移相器也可以与差分电路的负输入端耦合。若移相器与第一加减器耦合，用于对第一合成信号进行移相，且差分电路的负输入端与移相器耦合、正输入端与第二加减器耦合，则可以根据象限控制码和镜像抑制模式确定一套真值表。若移相器与第一加减器耦合，用于对 第一合成信号进行移相，且差分电路的正输入端与移相器的耦合、负输入端与第二加减器耦合，则可以根据象限控制码和镜像抑制模式确定另一套真值表。若移相器与第二加减器耦合，用于对第二合成信号进行移相，且差分电路的负输入端与移相器的耦合、正输入端与第一加减器耦合，则可以根据象限控制码和镜像抑制模式确定又一套真值表。若移相器与第二加减器耦合，用于对第二合成信号进行移相，且差分电路的正输入端与移相器的耦合、负输入端与第一加减器耦合，则可以根据象限控制码和镜像抑制模式确定又一套真值表。之后，根据真值表中的数据确定第一数字信号、第二数字信号、第三数字信号和第四数字信号为0或为1。
在一些可能实现的方式中，射频信号包括第一射频信号和第二射频信号，第一射频信号和第二射频信号关于第一本振信号或者第二本振信号镜像对称；第一合成信号和第二合成信号均包括第一信号和第二信号；第一信号经第一射频信号放大、混频得到，第二信号经第二射频信号放大、混频得到。第一信号为有用信号，第二信号为镜像干扰信号；或者，第一信号为镜像干扰信号，第二信号为有用信号。
在本申请中，通过预先选取前述真值表，确定第一数字信号、第二数字信号、第三数字信号和第四数字信号，并根据第一数字信号、第二数字信号、第三数字信号和第四数字信号，滤除第一信号或第二信号，以解决镜像干扰问题。在此基础上，还可以根据第一数字信号、第二数字信号、第三数字信号和第四数字信号，选择保留的第二信号和第一信号所在的象限，也可以说，选择保留的第二信号和第一信号的相位。
在一些可能实现的方式中，控制码生成器与符号码生成器耦合。符号码生成器还用于接收镜像抑制控制码以及控制码生成器发送的象限控制码，并根据象限控制码、镜像抑制控制码、移相器与第一加减器和第二加减器的耦合关系、以及移相器与差分电路的输入端的耦合关系，向第一加减器输入第一数字信号和第三数字信号，向第二加减器输入第二数字信号和第四数字信号(也可以说，确定上述真值表)。象限控制码用于表征有用信号所在的象限；镜像抑制模式用于表征第一信号为有用信号，或者第二信号为有用信号。
具体的，符号码生成器根据象限控制码、镜像抑制控制码、移相器与第一加减器和第二加减器的耦合关系、以及移相器与差分电路的输入端的耦合关系，向第一加减器输入第一数字信号和第三数字信号，向第二加减器输入第二数字信号和第四数字信号的方式可以包括以下两种：
第一种，符号码生成器包括第一开关、第二开关、第三开关、第四开关、第一反相器和第二反相器；第一加减器包括第一差分电路和第二差分电路。符号码生成器用于生成第一初始数字信号；第一开关与第二开关并联；第一开关用于接收第一同相中频信号和第一初始数字信号；第二开关与第一反相器耦合，用于接收第一同相中频信号和取反后的第一初始数字信号。符号码生成器还用于生成第三初始数字信号；第三开关与第四开关并联；第三开关用于接收第二正交中频信号和第三初始数字信号；第四开关与第二反相器耦合，用于接收第二正交中频信号和取反后的第三初始数字信号。第一开关和第二开关的输出侧与第一差分电路的输入侧耦合，第三开关和第四开关的输出侧与第二差分电路的输入侧耦合，第一差分电路和第二差分电路的输出侧均与差分电路的输入侧耦 合。
符号码生成器还包括第五开关、第六开关、第七开关、第八开关、第三反相器和第四反相器；第二加减器包括第三差分电路和第四差分电路。符号码生成器用于生成第二初始数字信号；第五开关与第六开关并联；第五开关用于接收第一正交中频信号和第二初始数字信号；第六开关与第三反相器耦合，用于接收第一正交中频信号和取反后的第二初始数字信号。符号码生成器还用于生成第四初始数字信号；第七开关与第八开关并联；第七开关用于接收第二同相中频信号和第四初始数字信号；第八开关与第四反相器耦合，用于接收第二同相中频信号和取反后的第四初始数字信号。第五开关和第六开关的输出侧与第三差分电路的输入侧耦合，第七开关和第八开关的输出侧与第四差分电路的输入侧耦合，第三差分电路和第四差分电路的输出侧均与差分电路的输入侧耦合。
基于此电路，符号码生成器与第一加减器和第二加减器的具体过程可以包括以下几种，以实现第一同相中频信号和第二正交中频信号通过第一加减器进行可选择的加或者减，第一正交中频信号和第二同相中频信号通过第二加减器进行可选择的相加或者相减：
若第一开关与第一差分电路的正输入端耦合，第二开关与第一差分电路的负输入端耦合，则输入至第一开关和第二开关的第一初始数字信号为1。若所需的第一数字信号为1，则可以控制第一开关导通、第二开关断开，第一同相中频信号通过第一开关输入至第一差分电路的正输入端，并从第一差分电路输出；若所需的第一数字信号为0，则可以控制第一开关断开、第二开关导通，第一同相中频信号通过第二开关输入至第一差分电路的负输入端，第一差分电路对第一同相中频信号取反后输出。
或者，若第一开关与第一差分电路的负输入端耦合，第二开关与第一差分电路的正输入端耦合，则输入至第一开关和第二开关的第一初始数字信号为0。若所需的第一数字信号为1，则可以控制第一开关断开、第二开关导通，第一同相中频信号通过第二开关输入至第一差分电路的正输入端，并从第一差分电路输出；若所需的第一数字信号为0，则可以控制第一开关导通、第二开关断开，第一同相中频信号通过第一开关输入至第一差分电路的负输入端，第一差分电路对第一同相中频信号取反后输出。
若第三开关与第二差分电路的正输入端耦合，第四开关与第二差分电路的负输入端耦合，则输入至第三开关和第四开关的第三初始数字信号为1。若所需的第三数字信号为1，则可以控制第三开关导通、第四开关断开，第二正交中频信号通过第三开关输入至第二差分电路的正输入端，并从第二差分电路输出；若所需的第三数字信号为0，则可以控制第三开关断开、第四开关导通，第二正交中频信号通过第四开关输入至第二差分电路的负输入端，第二差分电路对第二正交中频信号取反后输出。
或者，若第三开关与第二差分电路的负输入端耦合，第四开关与第二差分电路的正输入端耦合，则输入至第三开关与第四开关的第三初始数字信号为0。若所需的第三数字信号为1，则可以控制第三开关断开、第四开关导通，第二正交中频信号通过第四开关输入至第二差分电路的正输入端，并从第二差分电路输出；若所需的第三数字信号为0，则可以控制第三开关导通、第四开关断开，第二正交中频信号通过第三开关输入至第二差分电路的负输入端，第二差分电路对第二正交中频信号取反后输出。
进一步的，通过对第一差分电路和第二差分电路输出的信号进行矢量求和，以得到 第一合成信号。
若第五开关与第三差分电路的正输入端耦合，第六开关与第三差分电路的负输入端耦合，则第五开关和第六开关接收的第二初始数字信号为1。若所需的第二数字信号为1，则可以控制第五开关导通、第六开关断开，第一正交中频信号通过第五开关输入至第三差分电路的正输入端，并从第三差分电路输出；若所需的第二数字信号为0，则可以控制第五开关断开、第六开关导通，第一正交中频信号通过第六开关输入至第三差分电路的负输入端，第三差分电路对第一正交中频信号取反后输出。
或者，若第五开关与第三差分电路的负输入端耦合，第六开关与第三差分电路的正输入端耦合，则第五开关和第六开关接收的第二初始数字信号为0。若所需的第二数字信号为1，则可以控制第五开关断开、第六开关导通，第一正交中频信号通过第六开关输入至第三差分电路的正输入端，并从第三差分电路输出；若所需的第二数字信号为0，则可以控制第五开关导通、第六开关断开，第一正交中频信号通过第五开关输入至第三差分电路的负输入端，第三差分电路对第一正交中频信号取反后输出。
若第七开关与第四差分电路的正输入端耦合，第八开关与第四差分电路的负输入端耦合，则第七开关和第八开关接收的第四初始数字信号为1。若所需的第四数字信号为1，则可以控制第七开关导通、第八开关断开，第二同相中频信号通过第七开关输入至第四差分电路的正输入端，并从第四差分电路输出；若所需的第四数字信号为0，则可以控制第七开关断开、第八开关导通，第二同相中频信号通过第八开关输入至第四差分电路的负输入端，第四差分电路对第二同相中频信号取反后输出。
或者，若第七开关与第四差分电路的负输入端耦合，第八开关与第四差分电路的正输入端耦合，则第七开关和第八开关接收的第四初始数字信号为0。若所需的第四数字信号为1，则可以控制第七开关断开、第八开关导通，第二同相中频信号通过第八开关输入至第四差分电路的正输入端，并从第四差分电路输出。若所需的第四数字信号为0，则可以控制第七开关导通、第八开关断开，第二同相中频信号通过第七开关输入至第四差分电路的负输入端，第四差分电路对第二同相中频信号取反后输出。
进一步的，通过对第三差分电路和第四差分电路输出的信号进行矢量求和，以得到第二合成信号。
第二种，接收机还包括第三可调射频放大器、第四可调射频放大器、第五可调射频放大器、第六可调射频放大器。经过第三可调射频放大器以第三增益放大后的第一同相中频信号，与经过第五可调射频放大器以第四增益放大后的第二正交中频信号，通过第一加减器进行可选择的加或者减后输出第一合成信号。经过第四可调射频放大器以第三增益放大后的第一正交中频信号，与经过第六可调射频放大器以第四增益放大后的第二同相中频信号，通过第二加减器进行可选择的加或者减后输出第二合成信号。相较于接收机只包括第一可调射频放大器和第二射频可调放大器，还包括第三可调射频放大器、第四可调射频放大器、第五可调射频放大器、第六可调射频放大器，可以实现高可变增益范围。
第三可调射频放大器包括第一子放大器和第二子放大器、第四可调射频放大器包括第三子放大器和第四子放大器、第五可调射频放大器包括第五子放大器和第六子放大器、 第六可调射频放大器包括第七子放大器和第八子放大器。符号码生成器包括第一与门、第二与门、第三与门、第四与门、第五反相器、第六反相器；第一加减器包括第五差分电路和第六差分电路。第一与门用于接收第三增益和第一初始数字信号；第一与门的输出侧与第一子放大器耦合；第一子放大器的输入侧接收第一同相中频信号，输出侧与第五差分电路耦合。第二与门用于接收第四增益和第三初始数字信号；第二与门的输出侧与第五子放大器耦合；第五子放大器的输入侧接收第二正交中频信号，输出侧与第六差分电路耦合。第三与门用于接收第四增益和通过第五反相器取反后的第三初始数字信号；第三与门的输出侧与第六子放大器耦合；第六子放大器的输入侧接收第二正交中频信号，输出侧与第五差分电路耦合。第四与门用于接收第三增益和通过第六反相器取反后的第一初始数字信号；第四与门的输出侧与第二子放大器耦合；第二子放大器的输入侧接收第一同相中频信号，输出侧与第六差分电路耦合。第五差分电路的输出侧和第六差分电路的输出侧均与差分电路的输入侧耦合。
符号码生成器还包括第五与门、第六与门、第七与门、第八与门、第七反相器、第八反相器；第二加减器包括第七差分电路和第八差分电路。第五与门用于接收第三增益和第二初始数字信号；第五与门的输出侧与第三子放大器耦合；第三子放大器的输入侧接收第一正交中频信号，输出侧与第七差分电路耦合。第六与门用于接收第四增益和第四初始数字信号；第六与门的输出侧与第七子放大器耦合；第七子放大器的输入侧接收第二同相中频信号，输出侧与索虎第八差分电路耦合。第七与门用于接收第二增益和通过第七反相器取反后的第四初始数字信号；第七与门的输出侧与第八子放大器耦合；第八子放大器的输入侧接收第二同相中频信号，输出侧与第七差分电路耦合。第八与门用于接收第一增益和通过第八反相器取反后的第二初始数字信号；第八与门的输出侧与第四子放大器耦合；第四子放大器的输入侧接收第一正交中频信号，输出侧与第八差分电路耦合。第七差分电路的输出侧和第八差分电路的输出侧均与差分电路的输入侧耦合。
基于此电路，符号码生成器与第一加减器和第二加减器的具体过程可以包括以下几种，以实现第一同相中频信号和第二正交中频信号通过第一加减器进行可选择的加或者减，第一正交中频信号和第二同相中频信号通过第二加减器进行可选择的相加或者相减：
若第一子放大器的输出侧与第五差分电路的正输入端耦合，第二子放大器的输出侧与第六差分电路的负输入端耦合，则第一与门和第四与门接收的第一初始数字信号为1。若所需的第一数字信号为1，则可以向第一子放大器输入使能，而不向第二子放大器输入使能，使第一子放大器正常工作、第二子放大器不工作。第三增益和为1的第一初始数字信号(也可以说，第一数字信号)通过第一与门输入至第一子放大器，第一同相中频信号通过第一子放大器输入至第五差分电路的正输入端，并从第五差分电路输出。若所需的第一数字信号为0，则可以向第二子放大器输入使能，而不向第一子放大器输入使能，使第一子放大器不工作、第二子放大器正常工作。为1的第一初始数字信号和取反后得到为0的第一数字信号，第三增益和为0的第一数字信号通过第四与门输入至第二子放大器，第一同相中频信号通过第二子放大器输入至第六差分电路的负输入端，在第六差分电路中取反后，从第六差分电路输出。
或者，若第一子放大器的输出侧与第五差分电路的负输入端耦合，第二子放大器的 输出侧与第六差分电路的正输入端耦合，则第一与门和第四与门接收的第一初始数字信号为0。若所需的第一数字信号为1，则可以向第二子放大器输入使能，而不向第一子放大器输入使能，使第一子放大器不工作、第二子放大器正常工作。为0的第一初始数字信号和取反后得到为1的第一数字信号，第三增益和为1的第一数字信号通过第四与门输入至第二子放大器，第一同相中频信号通过第二子放大器输入至第六差分电路的正输入端，并从第六差分电路输出。若所需的第一数字信号为0，则可以向第一子放大器输入使能，而不向第二子放大器输入使能，使第一子放大器正常工作、第二子放大器不工作。第三增益和为0的第一初始数字信号(也可以说，第一数字信号)通过第一与门输入至第一子放大器，第一同相中频信号通过第一子放大器输入至第五差分电路的负输入端，在第五差分电路中取反后，从第五差分电路输出。
若第五子放大器的输出侧与第六差分电路的正输入端耦合，第六子放大器的输出侧与第五差分电路的负输入端耦合，则第二与门和第三与门接收的第三初始数字信号为1。若所需的第三数字信号为1，则可以向第五子放大器输入使能，而不向第六子放大器输入使能，使第五子放大器正常工作、第六子放大器不工作。第四增益和为1的第三初始数字信号(也可以说，第三数字信号)通过第二与门输入至第五子放大器，第二正交中频信号通过第五子放大器输入至第六差分电路的正输入端，并从第六差分电路输出。若所需的第三数字信号为0，则可以向第六子放大器输入使能，而不向第五子放大器输入使能，使第五子放大器不工作、第六子放大器正常工作。为1的第三初始数字信号和取反后得到为0的第三数字信号，第四增益和为0的第三数字信号通过第三与门输入至第六子放大器，第二正交中频信号通过第六子放大器输入至第五差分电路的负输入端，在第五差分电路中取反后，从第五差分电路输出。
或者，若第五子放大器的输出侧与第六差分电路的负输入端耦合，第六子放大器的输出侧与第五差分电路的正输入端耦合，则第二与门和第三与门接收的第三初始数字信号为0。若所需的第三数字信号为1，则可以向第六子放大器输入使能，而不向第五子放大器输入使能，使第五子放大器不工作、第六子放大器正常工作。为0的第三初始数字信号和取反后得到为1的第三数字信号，第四增益和为1的第三数字信号通过第三与门输入至第六子放大器，第二正交中频信号通过第六子放大器输入至第五差分电路的正输入端，并从第五差分电路输出。若所需的第三数字信号为0，则可以向第五子放大器输入使能，而不向第六子放大器输入使能，使第五子放大器正常工作、第六子放大器不工作。第四增益和为0的第三初始数字信号(也可以说，第三数字信号)通过第二与门输入至第五子放大器，第二正交中频信号通过第五子放大器输入至第六差分电路的负输入端，在第六差分电路中取反后，从第六差分电路输出。
进一步的，通过对第五差分电路和第六差分电路输出的信号进行矢量求和，以得到第一合成信号。
若第三子放大器的输出侧与第七差分电路的正输入端耦合，第四子放大器的输出侧与第八差分电路的负输入端耦合，则第五与门和第八与门接收的第二初始数字信号为1。若所需的第二数字信号为1，则可以向第三子放大器输入使能，而不向第四子放大器输入使能，使第三子放大器正常工作、第四子放大器不工作。第三增益和为1的第二初始数 字信号(也可以说，第二数字信号)通过第五与门输入至第三子放大器，第一正交中频信号通过第三子放大器输入至第七差分电路的正输入端，并从第七差分电路输出。若所需的第二数字信号为0，则可以向第四子放大器输入使能，而不向第三子放大器输入使能，使第三子放大器不工作、第四子放大器正常工作。为1的第二初始数字信号和取反后得到为0的第二数字信号，第三增益和为0的第二数字信号通过第八与门输入至第四子放大器，第一正交中频信号通过第四子放大器输入至第八差分电路的负输入端，在第八差分电路中取反后，从第八差分电路输出。
或者，若第三子放大器的输出侧与第七差分电路的负输入端耦合，第四子放大器的输出侧与第八差分电路的正输入端耦合，则第五与门和第八与门接收的第二初始数字信号为0。若所需的第二数字信号为1，则可以向第四子放大器输入使能，而不向第三子放大器输入使能，使第三子放大器不工作、第四子放大器正常工作。为0的第二初始数字信号和取反后得到为1的第二数字信号，第三增益和为1的第二数字信号通过第八与门输入至第四子放大器，第一正交中频信号通过第四子放大器输入至第八差分电路的正输入端，并从第八差分电路输出。若所需的第二数字信号为0，则可以向第三子放大器输入使能，而不向第四子放大器输入使能，使第三子放大器正常工作、第四子放大器不工作。第三增益和为0的第二初始数字信号(也可以说，第二数字信号)通过第五与门输入至第三子放大器，第一正交中频信号通过第三子放大器输入至第七差分电路的负输入端，在第七差分电路中取反后，从第七差分电路输出。
若第七子放大器的输出侧与第八差分电路的正输入端耦合，第八子放大器的输出侧与第七差分电路的负输入端耦合，则第六与门和第七与门接收的第四初始数字信号为1。若所需的第四数字信号为1，则可以向第七子放大器输入使能，而不向第八子放大器输入使能，使第七子放大器正常工作、第八子放大器不工作。第四增益和为1的第四初始数字信号(也可以说，第四数字信号)通过第六与门输入至第七子放大器，第二同相中频信号通过第七子放大器输入至第八差分电路的正输入端，并从第八差分电路输出。若所需的第四数字信号为0，则可以向第八子放大器输入使能，而不向第七子放大器输入使能，使第七子放大器不工作、第八子放大器正常工作。为1的第四初始数字信号和取反后得到为0的第四数字信号，第四增益和为0的第四数字信号通过第七与门输入至第八子放大器，第二同相中频信号通过第八子放大器输入至第七差分电路的负输入端，在第七差分电路中取反后，从第七差分电路输出。
或者，若第七子放大器的输出侧与第八差分电路的负输入端耦合，第八子放大器的输出侧与第七差分电路的正输入端耦合，则第六与门和第七与门接收的第四初始数字信号为0。若所需的第四数字信号为1，则可以向第八子放大器输入使能，而不向第七子放大器输入使能，使第七子放大器不工作、第八子放大器正常工作。为0的第四初始数字信号和取反后得到为1的第四数字信号，第四增益和为1的第四数字信号通过第七与门输入至第八子放大器，第二同相中频信号通过第八子放大器输入至第七差分电路的正输入端，并从第七差分电路输出。若所需的第四数字信号为0，则可以向第七子放大器输入使能，而不向第八子放大器输入使能，使第七子放大器正常工作、第八子放大器不工作。第四增益和为0的第四初始数字信号(也可以说，第四数字信号)通过第六与门输入至 第七子放大器，第二同相中频信号通过第七子放大器输入至第八差分电路的负输入端，在第八差分电路中取反后，从第八差分电路输出。
进一步的，通过对第七差分电路和第八差分电路输出的信号进行矢量求和，以得到第二合成信号。
第二方面，本申请提供一种射频收发器，该接收机包括发射机和第一方面所述的接收机。
第二方面的实现方式与第一方面的任意一种实现方式相对应。第二方面的实现方式所对应的技术效果可参见上述第一方面以及第一方面的任意一种实现方式所对应的技术效果，此处不再赘述。
第三方面，本申请提供一种终端，该终端包括天线和第二方面所述的射频收发器。
第三方面的实现方式与第一方面的任意一种实现方式相对应。第三方面的实现方式所对应的技术效果可参见上述第一方面以及第一方面的任意一种实现方式所对应的技术效果，此处不再赘述。
附图说明
图1a为本申请实施例提供的一种终端的结构框架图；
图1b为本申请实施例提供的第一射频信号和第二射频信号与本振信号的关系图；
图2为相关技术提供的一种接收机的电路结构图；
图3a为本申请实施例提供的一种接收机的电路结构图；
图3b为本申请实施例提供的另一种接收机的电路结构图；
图3c为本申请实施例提供的又一种接收机的电路结构图；
图3d为本申请实施例提供的又一种接收机的电路结构图；
图3e为本申请实施例提供的又一种接收机的电路结构图；
图3f为本申请实施例提供的又一种接收机的电路结构图；
图4a为本申请实施例提供的一种控制电路的电路结构图；
图4b为本申请实施例提供的一种增益变化图；
图4c为本申请实施例提供的一种相位变化图；
图5a为本申请实施例提供的第一射频信号和第二射频信号的相位图；
图5b为本申请实施例提供的第一射频信号和第二射频信号以第一增益放大后的相位图；
图5c为本申请实施例提供的第一射频信号和第二射频信号以第二增益放大后的两位图；
图5d为本申请实施例提供的第一同相中频信号的相位图；
图5e为本申请实施例提供的第一正交中频信号的相位图；
图5f为本申请实施例提供的第二正交中频信号的相位图；
图5g为本申请实施例提供的第二同相中频信号的相位图；
图5h为本申请实施例提供的滤除镜像干扰信号的一种模式；
图5i为本申请实施例提供的第一合成信号的相位图；
图5j为本申请实施例提供的第二合成信号的相位图；
图5k为本申请实施例提供的对第一合成信号进行90°移相后的相位图；
图5l为本申请实施例提供的对第一合成信号和第二合成信号进行相加的过程示意图；
图6a为本申请实施例提供的又一种接收机的电路结构图；
图6b为本申请实施例提供的又一种接收机的电路结构图；
图6c为本申请实施例提供的又一种接收机的电路结构图；
图7a为本申请实施例提供的滤除镜像干扰信号的另一种模式；
图7b为本申请实施例提供的又一种接收机的电路结构图；
图7c为本申请实施例提供的又一种接收机的电路结构图；
图7d为本申请实施例提供的又一种接收机的电路结构图；
图7e为本申请实施例提供的又一种接收机的电路结构图；
图8a为本申请实施例提供的一种控制电路和第一加减器的电路结构图；
图8b为本申请实施例提供的另一种控制电路和第一加减器的电路结构图；
图8c为本申请实施例提供的一种控制电路和第二加减器的电路结构图；
图8d为本申请实施例提供的另一种控制电路和第二加减器的电路结构图；
图9a为本申请实施例提供的又一种接收机的电路结构图；
图9b为本申请实施例提供的控制电路和放大器与第一加减器的电路结构图；
图9c为本申请实施例提供的控制电路和放大器与第一加减器的电路结构图；
图9d为本申请实施例提供的控制电路和放大器与第二加减器的电路结构图；
图9e为本申请实施例提供的控制电路和放大器与第二加减器的电路结构图。
附图标记：
101-接收机；102-发射机；103-天线；1011-可变增益放大器；1012-矢量合成移相器；11-第一加减器；12-第二加减器；13-移相器；14-差分电路；15-控制电路。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。
本申请实施例的说明书和权利要求书中的术语“第一”和“第二”等是用于区别不同的对象，而不是用于描述对象的特定顺序。例如，第一目标对象和第二目标对象等是用于区别不同的目标对象，而不是用于描述目标对象的特定顺序。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例 如”等词旨在以具体方式呈现相关概念。
在本申请实施例的描述中，除非另有说明，“多个”的含义是指两个或两个以上。例如，多个处理单元是指两个或两个以上的处理单元；多个系统是指两个或两个以上的系统。
本申请实施例提供一种终端，该终端可以是雷达、基站、服务器、手机等包括射频收发器的设备，本申请实施例对此不作限定。为了方便说明，下文以终端为手机进行举例说明。
图1a示出了本申请实施例提供的手机的一种应用场景示意图，手机包括射频收发器和天线103。射频收发器可以包括接收器101和发射机102。天线103分别与接收机101和发射机102耦合，用于向接收机101发送射频信号，以及，接收发射机102发送的射频信号。
如图1b所示，假设射频信号包括第一射频信号和第二射频信号，第一射频信号的频率为f1，第二射频信号的频率为f2，本振信号的频率为f LO。其中，f1+f IF＝f LO，f2-f LO＝f IF。即，第一射频信号和第二射频信号与本振信号之间的频率差均为f IF。第一射频信号和第二射频信号分别与本振信号混频后，均可以输出中频信号IF，从而产生镜像频率干扰问题。
相关技术可以利用正交架构的混频器进行镜像抑制。图2示出了一种典型的具有幅度、相位控制以及镜像抑制功能的接收机101，射频信号的幅度控制由可变增益放大器1011实现，射频信号的相位控制由矢量合成移相器1012实现，镜像抑制由正交架构的混频器1013实现。
然而，图2示出的接收机101中，射频信号的幅度和相位分开控制。其中，幅度控制电路通过控制可变增益放大器1011，独立控制射频信号的幅度；相位控制电路通过控制矢量合成移相器1012，独立控制射频信号的相位。而若实现高精度的移相，对于无源的矢量合成移相器1012，会导致接收机101所在电路的尺寸和损耗增大；对于有源的矢量合成移相器1012，会导致接收机101所在电路的功耗增加。
基于此，本申请实施例提供一种接收机101，该接收机101可以利用放大器、混频器和镜像抑制电路，代替传统的矢量合成移相器1012，来调节接收到的射频信号的相位，可以节省接收机101的版图面积和功耗。
下面结合附图，对接收机101的电路结构进行详细说明。
如图3a和图3b所示，该接收机101包括第一可调射频放大器VGA1、第二可调射频放大器VGA2、第一同相混频器H1、第一正交混频器H2、第二正交混频器H3、第二同相混频器H4、第一加减器11、以及第二加减器12。
接收机101用于接收射频信号RF。射频信号RF经过第一可调射频放大器VGA1放大后输出第一射频放大信号RFr，射频信号RF经过第二可调射频放大器VGA2放大后输出第二射频放大信号RFi。第一射频放大信号RFr，经过所述第一同相混频器H1混频后输出第一同相中频信号IFIr，经过第一正交混频器H2混频后输出第一正交中频信号IFQr。第二射频放大信号RFi经过第二正交混频器H3混频后输出第二正交中频信号IFQi，经过第二同相混频器H4混频后输出第二同相中频信号IFIi。
第一同相中频信号IFQr和第二正交中频信号IFQi通过第一加减器11进行可选择的加或者减后输出第一合成信号IFI。第一正交中频信号IFQr和第二同相中频信号IFIi通过第二加减器12进行可选择的加或者减后输出第二合成信号IFQ。
在一些可能实现的方式中，第一可调射频放大器VGA1可以以可调的第一增益r1对射频信号RF进行放大，第二可调射频放大器VGA2可以以可调的第二增益i1对射频信号RF进行放大。
在一些可能实现的方式中，第一射频放大信号RFr可以和第一本振信号LOI经过第一同相混频器H1混频后，输出第一同相中频信号IFIr。第一射频放大信号RFr可以和第二本振信号LOQ经过第一正交混频器混频M2后，输出第一正交中频信号IFQr。第二射频放大信号RFi可以和第二本振信号LOQ经过第二正交混频器H3混频后，输出第二正交中频信号IFQi。第二射频放大信号RFi可以和第一本振信号LOI经过第二同相混频器H4混频后，输出第二同相中频信号IFIi。并且，第一本振信号LOI与第二本振信号LOQ正交，使得第一同相中频信号IFIr与第二正交中频信号IFQi正交，第一正交中频信号IFQr与第二同相中频信号IFIi正交；第一同相中频信号IFIr的相位与第二同相中频信号IFIi的相位相同，第一正交中频信号IFQr的相位与第二正交中频信号IFQi的相位相同。
本领域的技术人员应该知道，矢量合成移相器1012的工作原理是通过改变正交的两路信号的比值，以实现移相功能。
对于第一加减器11，其接收正交的第一同相中频信号IFIr和第二正交中频信号IFQi。并且，由于形成第一同相中频信号IFIr的射频信号RF经第一可调射频放大器VGA1以可调的第一增益r1进行放大，形成第二正交中频信号IFQi的射频信号RF经第二可调射频放大器VGA2以可调的第二增益i进行放大。因此，可以通过调节第一增益r1和第二增益i1的大小，在调节第一同相中频信号IFIr和第二正交中频信号IFQi的幅度的基础上，调节正交的第一同相中频信号IFIr和第二正交中频信号IFQi的比值，从而代替现有的矢量合成移相器1012，实现移相功能。
对于第二加减器12，其接收正交的第一正交中频信号IFQr和第二同相中频信号IFIi。并且，由于形成第一正交中频信号IFQr的射频信号RF经第一可调射频放大器VGA1以可调的第一增益r1进行放大，形成第二同相中频信号IFIi的射频信号RF经第二可调射频放大器VGA2以可调的第二增益i1进行放大。因此，可以通过调节第一增益r1和第二增益i1的大小，在调节第一正交中频信号IFQr和第二同相中频信号IFIi的幅度的基础上，调节正交的第一正交中频信号IFQr和第二同相中频信号IFIi的比值，从而代替现有的矢量合成移相器1012，实现移相功能。
综上，本申请可以利用既有的第一可调射频放大器VGA1、第二可调射频放大器VGA2、第一同相混频器H1、第一正交混频器H2、第二正交混频器H3、第二同相混频器H4、第一加减器11和第二加减器12，代替传统的矢量合成移相器1012，来调节接收到的射频信号的相位，节省接收机101的版图面积和功耗。并且，由于本申请将实现放大功能、移相功能和混频功能的第一可调射频放大器VGA1、第二可调射频放大器VGA2、第一同相混频器H1、第一正交混频器H2、第二正交混频器H3、第二同相混频器H4、第一加减器11和第二加减器12合为一体，大幅提高了接收机101的集成度，从而降低 接收机101中的寄生电容和寄生电感。
此外，第一可调射频放大器和第二可调射频放大器还可以对射频信号的幅度进行调节。并且，由于第一加减器11通过矢量合成，可选择地对第一同相中频信号IFIr和第二正交中频信号IFQi进行相加或相减；第二加减器12通过矢量合成，可选择地对第一正交中频信号IFQr和第二同相中频信号IFIi进行相加或相减。而第一同相中频信号IFIr和第一正交中频信号IFQr经第一增益r1放大得到，第二正交中频信号IFQi和第二同相中频信号IFIi经第二增益i1放大得到。因此，即使改变第一增益r1和/或第二增益i1，第一同相中频信号IFIr和第二正交中频信号IFQi的矢量合成结果，与第一正交中频信号IFQr和第二同相中频信号IFIi的矢量合成结果的幅度始终相同。
在一些可能实现的方式中，接收机101接收射频信号RF后，可以向第一可调射频放大器VGA1和第二可调射频放大器VGA2输入相同的射频信号RF。具体的，输入至第一可调射频放大器VGA1、第二可调射频放大器VGA2的射频信号RF的信号量、幅度和相位可以均相同。
在一些可能实现的方式中，第一可调射频放大器VGA1以第一增益r1对射频信号进行放大，是指：第一可调射频放大器VGA1以第一增益r1对输入至第一放大器的射频信号RF进行放大，且从第一可调射频放大器VGA1输出的第一射频放大信号RFr与输入至第一可调射频放大器VGA1的射频信号RF的比值为第一增益r1；第二可调射频放大器VGA2以第二增益i1对输入至第二可调射频放大器VGA2的射频信号RF进行放大，且从第二可调射频放大器VGA2输出的第二射频放大信号RFi与输入至第二可调射频放大器VGA2的射频信号RF的比值为第二增益i1。
在一些可能实现的方式中，本申请可以利用单级放大器对射频信号RF进行放大。例如，如图3a所示，本申请实施例示出了第一可调射频放大器VGA1和第二可调射频放大器VGA2耦合于接收机101的输入端IN与第一同相混频器H1、第一正交混频器H2、第二正交混频器H3、第二同相混频器H4之间的情况。此情况下，接收机101接收的射频信号RF可以先经过第一可调射频放大器VGA1和第二可调射频放大器VGA2放大，再经过第一同相混频器H1、第一正交混频器H2、第二正交混频器H3、第二同相混频器H4混频。
或者，如图3b所示，第一同相混频器H1、第一正交混频器H2、第二正交混频器H3、第二同相混频器H4也可以耦合于接收机101的输入端IN与第一可调射频放大器VGA1和第二可调射频放大器VGA2之间。此情况下，接收机101接收的射频信号RF可以先经过第一同相混频器H1、第一正交混频器H2、第二正交混频器H3、第二同相混频器H4混频，再经过第一可调射频放大器VGA1和第二可调射频放大器VGA2放大。
在另一些可能实现的方式中，本申请也可以利用多级放大器对射频信号RF进行放大。如图3c所示，第一可调射频放大器VGA1和第二可调射频放大器VGA2耦合于接收机101的输入端IN与第一同相混频器H1、第一正交混频器H2、第二正交混频器H3、第二同相混频器H4之间。除此以外，接收机101还可以包括第三可调射频放大器VGA2、第四可调射频放大器VGA4、第五可调射频放大器VGA5、以及第六可调射频放大器VGA6。第三可调射频放大器VGA2、第四可调射频放大器VGA4、第五可调射频放大器VGA5、 以及第六可调射频放大器VGA6可以耦合于第一同相混频器H1、第一正交混频器H2、第二正交混频器H3、第二同相混频器H4与接收机101的输出端OUT之间。第三可调射频放大器VGA2以第三增益r2对第一同相中频信号IFQr进行放大，第四可调射频放大器VGA4以第三增益r2对第二正交中频信号IFQi进行放大，第五可调射频放大器VGA5以第四增益i2对第一正交中频信号IFQr进行放大，第六可调射频放大器VGA6以第四增益i2对第二同相中频信号IFIi进行放大。
当然，前述图3a-图3c示出的情况仅为示例，接收机101中放大器的个数还可以是其他，本申请实施例对此不作限定。
相较于单级放大器，多级放大器可以实现高可变增益范围。相较于多级放大器，单级放大器可以提高线性度，并降低接收机101的功耗和版图面积。而不论采用单级放大器，还是多级放大器，均可以省去传统的矢量合成移相器1012，节省接收机101的版图面积和功耗。
在一些实施例中，如图4a所示，接收机101还可以包括控制电路15，控制电路15可以包括控制码生成器，控制码生成器的输出侧与第一可调射频放大器VGA1和第二可调射频放大器VGA2耦合。控制码生成器可以根据预设的增益控制码和相位控制码，向第一可调射频放大器VGA1输入第一增益r1，向第二可调射频放大器VGA2输入第二增益i1。在接收机101还包括第三可调射频放大器VGA3、第四可调射频放大器VGA4、第五可调射频放大器VGA5、以及第六可调射频放大器VGA6的情况下，控制码生成器可以根据预设的增益控制码和相位控制码，向第三可调射频放大器VGA3和第四可调射频放大器VGA4输入第三增益r2，向第五可调射频放大器VGA5和第六可调射频放大器VGA6输入第四增益i2。
在一些可能实现的方式中，本申请实施例不对第一增益r1、第二增益i1、第三增益r2、以及第四增益i2的比特数进行限定，可以根据实际需要的幅度和相位，设计第一增益r1、第二增益i1、第三增益r2、以及第四增益i2的比特数。并且，由于第一增益r1、第二增益i1、第三增益r2、以及第四增益i2的比特数本身包含多个状态。因此，在通过调节第一增益r1、第二增益i1、第三增益r2、以及第四增益i2的大小，实现调节射频信号的相位时，可以无需额外增加控制电路15的比特数。
例如，假设第一增益r1与第三增益r2的总比特数为3，记作r code＜0：m＞，则第一增益r1和第三增益r2总共包括000、001、010、011、100、101、110、111等8个状态。假设第二增益i1和第四增益i2的总比特数为3，记作i code＜0：m＞，则第二增益i1和第四增益i2总共包括000、001、010、011、100、101、110、111等8个状态。其中，m为正整数。
第一可调射频放大器VGA1的第一增益r1的比特数可以为n-1，记作r1code＜0：n-1＞，第三可调射频放大器VGA3和第四可调射频放大器VGA4的第三增益r2的比特数可以为m-n+1，第一增益r1和第三增益r2的总比特数为n-1+m-n+1＝m。第二可调射频放大器VGA2的第二增益i1的比特数可以为n-1，记作i1code＜0：n-1＞，第五可调射频放大器VGA5和第六可调射频放大器VGA6的第四增益i2的比特数可以为m-n+1，第二增益i1和第四增益i2的的总比特数为n-1+m-n+1＝m。其中，n为小于m的正整数。
此外，若接收机101包括第一可调射频放大器VGA1和第二可调射频放大器VGA2，不包括第三可调射频放大器VGA3、第四可调射频放大器VGA4、第五可调射频放大器VGA5、以及第六可调射频放大器VGA6，则第一增益r1包括000、001、010、011、100、101、110、111等8个状态。第二增益i1包括000、001、010、011、100、101、110、111等8个状态。
前述示例以第一增益r1和第三增益r2的总比特数，与第二增益i1和第四增益i2的总比特数相同进行举例说明，在一些可能实现的方式中，第一增益r1和第三增益r2的总比特数，与第二增益i1和第四增益i2的总比特数也可以不相同，本申请实施例对此不作限定。
在一些实施例中，上述控制电路15还可以包括符号码生成器。符号码生成器用于向第一加减器11输入第一数字信号S1r和第三数字信号S1i，向第二加减器12输入第二数字信号S2r和第四数字信号S2i。第一数字信号S1r用于决定第一同相中频信号IFIr的相位为正或为负，第二数字信号S2r用于决定第一正交中频信号IFQr的相位为正或为负，第三数字信号S1i用于决定第二正交中频信号IFQi的相位为正或为负，第四数字信号S2i用于决定第二同相中频信号IFIi的相位为正或为负。
例如，第一数字信号S1r为1，第一同相中频信号IFIr的相位为负；第一数字信号S1r为0，第一同相中频信号IFIr的相位为正。第二数字信号S2r为1，第一正交中频信号IFQr的相位为负；第二数字信号S2r为0，第一正交中频信号IFQr的相位为正。第三数字信号S1i为1，第二正交中频信号IFQi的相位为负；第三数字信号S1i为0，所述第二正交中频信号IFQi的相位为正。第四数字信号S2i为1，第二同相中频信号IFIi的相位为负；第四数字信号S2i为0，第二同相中频信号IFIi的相位为正。
或者，第一数字信号S1r为1，第一同相中频信号IFIr的相位为正；第一数字信号S1r为0，第一同相中频信号IFIr的相位为负。第二数字信号S2r为1，第一正交中频信号IFQr的相位为正；第二数字信号S2r为0，第一正交中频信号IFQr的相位为负。第三数字信号S1i为1，第二正交中频信号IFQi的相位为正；第三数字信号S1i为0，所述第二正交中频信号IFQi的相位为负。第四数字信号S2i为1，第二同相中频信号IFIi的相位为正；第四数字信号S2i为0，第二同相中频信号IFIi的相位为负。下文为方便描述，均以此为例进行说明。
在一些实施例中，根据第一数字信号S1r和第三数字信号S1i，第一加减器11对相位为正的第一同相中频信号IFIr(或者相位为负的第一同相中频信号IFIr)与相位为正的第二正交中频信号IFQi(或者相位为负的第二正交中频信号IFQi)进行矢量合成，得到第一合成信号IFI。根据第二数字信号S2r和第四数字信号S2i，第二加减器12对相位为正的第一正交中频信号IFQr(或者相位为负的第一正交中频信号IFQr)与相位为正的第二同相中频信号IFIi(或者相位为负的第二同相中频信号IFIi)进行矢量合成，得到第二合成信号IFQ。
在上述基础上，接收机101还可以包括差分电路14和既有的移相器13。通过对第一合成信号IFI和第二合成信号IFQ进行进一步处理，以滤除第一合成信号IFI和第二合成信号IFQ中的镜像干扰信号。
具体的，移相器13用于对第一合成信号IFI或第二合成信号IFQ进行90°移相。差分电路14用于对第二合成信号IFQ和移相后的第一合成信号IFI，或者对第一合成信号IFI和移相后的第二合成信号IFQ进行相加，以滤除第一合成信号IFI和第二合成信号IFQ中的镜像干扰信号。其中，移相器13可以是多相滤波器或正交耦合器等。
前文描述了镜像频率干扰问题的由来，对于第一同相中频信号IFIr和第二同相中频信号IFIi，其均由以第一本振信号LOI为镜像，和第一本振信号LOI之间的频率差相同、且二者频率不同的第一射频信号和第二射频信号，经放大后与第一本振信号LOI混频得到。对于第一正交中频信号IFQr和第二正交中频信号IFQi，其均由以第二本振信号LOQ为镜像，和第二本振信号LOQ之间的频率差相同、且二者频率不同的第一射频信号和第二射频信号，经放大后与第二本振信号LOQ混频得到。
也可以说，第一同相中频信号IFIr、第一正交中频信号IFQr、第二正交中频信号IFQi和第二同相中频信号IFIi中既包括由放大后的第一射频信号与第一本振信号LOI或第二本振信号LOQ混频得到的第一信号，也包括由放大后的第二射频信号与第一本振信号LOI或第二本振信号LOQ混频得到的第二信号。第一信号和第二信号中的一个为有用信号，另一个为镜像干扰信号。需要滤除第一同相中频信号IFIr、第一正交中频信号IFQr、第二正交中频信号IFQi和第二同相中频信号IFIi中的镜像干扰信号，保留有用信号，以解决镜像干扰问题。
本申请实施例不对滤除镜像干扰信号时，第一数字信号S1r、第二数字信号S2r、第三数字信号S1i和第四数字信号S2i的数字逻辑进行限定。镜像抑制电路14可以根据符号码生成器向镜像抑制电路14输入的第一数字信号S1r、第二数字信号S2r、第三数字信号S1i和第四数字信号S2i，选择第一信号为有用信号，以滤除第二信号；或者，选择第二信号为有用信号，以滤除第一信号。
具体的，如图4a所示，符号码生成器可以与控制码生成器耦合，用于接收镜像抑制控制码以及控制码生成器输入的象限控制码，并根据象限控制码、镜像抑制控制码、移相器13与第一加减器11和第二加减器12的耦合关系、以及移相器13与差分电路14的输入端的耦合关系，确定向第一加减器11输入的第一数字信号S1r和第三数字信号S1i，以及向第二加减器12输入的第二数字信号S2r和第四数字信号S2i为0或为1。
象限控制码用于表征有用信号所在的象限。镜像抑制模式用于表征第一信号为有用信号，第二信号为镜像干扰信号；或者，镜像抑制模式用于表征第一信号为镜像干扰信号，第二信号为有用信号。可以根据输入的射频信号RF的相位，将360°等分为四个象限。其中，0°-90°为第一象限，90°-180°为第二象限，180°-270°为第三象限，270°-360°为第四象限。若象限控制码为0°-90°，则有用信号位于第一象限；若象限控制码为90°-18/0°，则有用信号位于第二象限；若象限控制码为180°-270°，则有用信号位于第三象限；若象限控制码为270°-360°，有用信号位于第四象限。
镜像抑制模式MC为0时，表示第一信号为有用信号，第二信号为镜像干扰信号；镜像抑制模式MC为1时，表示第一信号为镜像干扰信号，第二信号为有用信号。
在一些可能实现的方式中，可以根据象限控制码、镜像抑制模式、移相器13与第一加减器11或第二加减器12的耦合关系、以及差分电路14的输入侧与移相器13的耦合 关系，预先设置四套真值表，并根据真值表中的数据确定第一数字信号S1r、第二数字信号S2r、第三数字信号S1i和第四数字信号S2i为0或为1。
如图3a所示，若移相器13与第一加减器11耦合，用于对第一合成信号IFI进行移相，且差分电路14的负输入端与移相器13耦合、正输入端与第二加减器12耦合，则可以根据象限控制码和镜像抑制模式确定第一套真值表，如表1和表2所示。为了方便描述，下文均以第一套真值表，即，表1和表2，进行举例说明。
表1
象限控制码 MC S1r S2r S1i S2i
第一象限 0 1 0 1 1
第二象限 0 0 1 1 1
第三象限 0 0 1 0 0
第四象限 0 1 0 0 0
表2
象限控制码 MC S1r S2r S1i S2i
第一象限 1 1 1 0 1
第二象限 1 0 0 0 1
第三象限 1 0 0 1 0
第四象限 1 1 1 1 0
如图3d所示，若移相器13与第一加减器11耦合，用于对第一合成信号IFI进行移相，且差分电路14的正输入端与移相器13的耦合、负输入端与第二加减器12耦合，则可以根据象限控制码和镜像抑制模式确定第二套真值表。
如图3e所示，若移相器13与第二加减器12耦合，用于对第二合成信号IFQ进行移相，且差分电路14的负输入端与移相器13的耦合、正输入端与第一加减器11耦合，则可以根据象限控制码和镜像抑制模式确定第三套真值表。
如图3f所示，若移相器13与第二加减器12耦合，用于对第二合成信号IFQ进行移相，且差分电路14的正输入端与移相器13的耦合、负输入端与第一加减器11耦合，则可以根据象限控制码和镜像抑制模式确定第四套真值表。
此外，前文提到，本申请不但可以利用第一可调射频放大器VGA1和第二可调射频放大器VGA2(或者，第一可调射频放大器VGA1、第二可调射频放大器VGA2、第三可调射频放大器VGA3、第四可调射频放大器VGA4、第五可调射频放大器VGA5和第六可调射频放大器VGA6)根据可变的第一增益r1和第二增益i1(或者，第一增益r1、第二增益i1、第三增益r2和第四增益i2)对射频信号RF进行不同程度的放大，还可以利用第一可调射频放大器VGA1和第二可调射频放大器VGA2(或者，第一可调射频放大器VGA1、第二可调射频放大器VGA2、第三可调射频放大器VGA3、第四可调射频放大器VGA4、第五可调射频放大器VGA5和第六可调射频放大器VGA6)根据可变的第一增益r1和第二增益i1(或者，第一增益r1、第二增益i1、第三增益r2和第四增益i2)，配合第一同相混频器H1、第一正交混频器H2、第二正交混频器H3、第二同相混频器 H4、第一加减器11和第二加减器12来调节射频信号RF的相位。
如图4b所示，对于根据可变的第一增益r1和第二增益i1对射频信号RF进行放大这一功能，无论滤除镜像干扰信号后的有用信号位于第一象限Q1、或第二象限Q2、或第三象限Q3、或第四象限Q4，第一增益r1和第二增益i1(或者，第一增益r1、第二增益i1、第三增益r2和第四增益i2)越大，放大后的有用信号越大；第一增益r1和第二增益i1(或者，第一增益r1、第二增益i1、第三增益r2和第四增益i2)越小，放大后的有用信号越小。
如图4c所示，对于根据可变的第一增益r1和第二增益i1调节射频信号的相位，若滤除镜像干扰信号后的有用信号位于第一象限Q1或第三象限Q3，则第二增益i1(或者，第二增益i和第四增益i2)越大，有用信号的相位越大；第二增益i1(或者，第二增益i和第四增益i2)越小，有用信号的相位越小。若滤除镜像干扰信号后的有用信号位于第二象限Q2或第四象限Q4，则第二增益i1(或者，第二增益i1和第四增益i2)越大，有用信号的相位越小；第二增益i1(或者，第二增益i1和第四增益i2)越小，有用信号的相位越大。
当然，上述相位变化与增益变化的关系是基于前述第一套真值表，若基于其他真值表，相位变化与增益变化的关系还可以是其他。
下面结合接收机101的电路图，参考上述表1和表2，对接收机101滤除镜像干扰信号的过程进行详细说明。
如图3a和图5a所示，第一射频信号A1和第二射频信号A2以相同相位输入至第一可调射频放大器VGA1和第二可调射频放大器VGA2，假设第一射频信号A1和第二射频信号A2的相位为0°。
如图3a和图5b所示，第一可调射频放大器VGA1接收第一射频信号A1和第二射频信号A2后，以第一增益r1对第一射频信号A1和第二射频信号A2进行放大，并输出第一射频放大信号RFr，第一射频放大信号RFr包括第一放大信号A1Ar1和第二放大信号A2Ar1，且第一放大信号A1Ar1和第二放大信号A2Ar1的相位没有发生变化，仍为0°。
如图3a和图5c所示，第二可调射频放大器VGA2接收第一射频信号A1和第二射频信号A2后，以第二增益i1对第一射频信号A1和第二射频信号A2进行放大，并输出第二射频放大信号RFi，第二射频放大信号RFi包括第三放大信号A1Ai1和第四放大信号A2Ai1，且第三放大信号A1Ai1和第四放大信号A2Ai1的相位没有发生变化，仍为0°。
如图3a和图5d所示，第一放大信号A1Ar1和第二放大信号A2Ar1与第一本振信号LOI经第一同相混频器H1混频后，输出第一同相中频信号IFIr。其中，第一同相中频信号IFIr包括由第一放大信号A1Ar1与第一本振信号LOI混频得到的第一同相中频信号jA1Ar1，以及由第二放大信号A2Ar1与第一本振信号LOI混频得到的第一同相中频信号jA2Ar1。假设第一本振信号LOI为sin(ω LOt)，取混频产物中的第一同相中频信号IFIr，即，ω IF＝ω 2-ω LO＝ω LO-ω 1，根据混频公式IF＝(A 1A r1sinω 1t+A 2A r1sinω 2t)sinω LOt可知， 第一同相中频信号IFIr的产物为
Figure PCTCN2022091702-appb-000001
包括第一同相中频信号jA1Ar1和第一同相中频信号jA2Ar1。假设ω IFt为0°，则cosω IFt为90°，第一同相中频信号jA1Ar1和第一同相中频信号jA2Ar1的相位均为90°。其中，ω IF表示中频信号的角频率，此处，ω IF可以是第一同相中频信号IFIr的角频率；ω 1表示第一射频信号A1的角频率；ω 2是第二射频信号A2的角频率；ω LO表示第一本振信号LOI的角频率；sinω 1t是第一射频信号A1的表达式，sinω 2t是第二射频信号A2的表达式。
如图3a和图5e所示，第一放大信号A1Ar1和第二放大信号A2Ar1与第二本振信号LOQ经第一正交混频器H2混频后，输出第一正交中频信号IFQr。其中，第一正交中频信号IFQr包括由第一放大信号A1Ar1与第二本振信号LOQ混频得到的第一正交中频信号-A1Ar1，以及由第二放大信号A2Ar1与第二本振信号LOQ混频得到的第一正交中频信号A2Ar1。假设第二本振信号LOQ是与第一本振信号LOI正交的cos(ω LOt)。取混频产物中的第一正交中频信号IFQr，即，ω IF＝ω 2-ω LO＝ω LO-ω 1，根据混频公式IF＝(A 1A r1sinω 1t+A 2A r1sinω 2t)cosω LOt可知，第一正交中频信号IFQr的产物为
Figure PCTCN2022091702-appb-000002
包括第一正交中频信号-A1Ar1和第一正交中频信号A2Ar1。假设ω IFt为0°，则sinω IFt为0°，第一正交中频信号-A1Ar1的相位变为180°，第一正交中频信号A2Ar1的相位不变，仍为0°。
如图3a和图5f所示，第三放大信号A1Ai1和第四放大信号A2Ai1与第二本振信号LOQ经第二正交混频器H3混频后，输出第二正交中频信号IFQi。其中，第二正交中频信号IFQi包括由第三放大信号A1Ai1与第二本振信号LOQ混频得到的第二正交中频信号-A1Ai1，以及由第四放大信号A2Ai1与第二本振信号LOQ混频得到的第二正交中频信号A2Ai1。假设第二本振信号LOQ是与第一本振信号LOI正交的cos(ω LOt)。取混频产物中的第二正交中频信号IFQi，即，ω IF＝ω 2-ω LO＝ω LO-ω 1，根据混频公式IF＝(A 1A i1sinω 1t+A 2A i1sinω 2t)cosω LOt可知，第二正交中频信号IFQi的产物为
Figure PCTCN2022091702-appb-000003
可知，包括第二正交中频信号-A1Ai1和第二正交中频信 号A2Ai1。假设ω IFt为0°，则sinω IFt为0°，第二正交中频信号-A1Ai1的相位变为180°，第二正交中频信号A2Ai1的相位不变，仍为0°。
如图3a和图5g所示，第三放大信号A1Ai1和第四放大信号A2Ai1与第二本振信号LOQ经第二同相混频器H4混频后，输出第二同相中频信号IFIi。其中，第二同相中频信号IFIi包括由第三放大信号A1Ai1与第一本振信号LOI混频得到的第二同相中频信号jA1Ai1，以及由第四放大信号A2Ai1与第一本振信号LOI混频得到的第二同相中频信号jA2Ai1。假设第一本振信号LOI为sin(ω LOt)，取混频产物中的第二同相中频信号IFIi，即，ω IF＝ω 2-ω LO＝ω LO-ω 1，根据混频公式IF＝(A 1A i1sinω 1t+A 2A i1sinω 2t)sinω LOt可知，第二同相中频信号IFIi的产物为
Figure PCTCN2022091702-appb-000004
包括第二同相中频信号jA1Ai1和第二同相中频信号jA2Ai1。假设ω IFt为0°，则cosω IFt为90°，第二同相中频信号jA1Ai1和第二同相中频信号jA2Ai1的相位均变为90°。
接着，结合第一数字信号S1r和第三数字信号S1i，第一加减器11对第一同相中频信号IFIr和第二正交中频信号IFQi进行矢量相加，得到第一合成信号IFI，IFI＝S1r*Ar1(jA1+jA2)+S1i*Ai1(-A1+A2)；结合第二数字信号S2r和第四数字信号S2i，第二加减器12对第一正交中频信号IFQr和第二同相中频信号IFIi进行矢量相加，得到第二合成信号IFQ，IFQ＝S2r*Ar1(-A1+A2)+S2i*Ai1(jA1+jA2)。
由于第一合成信号IFI和第二合成信号IFQ均包括参数Ar1和Ai1，因此，第一合成信号IFI和第二合成信号IFQ具有相同的幅度。基于表1和表2中的第一数字信号、第二数字信号、第三数字信号和第四数字信号，可以控制第一合成信号IFI与第二合成信号IFQ具有正交的相位。
因此，可以通过将移相器13耦合在第一加减器11与差分电路14之间，利用移相器13对第一合成信号IFI进行90°移相，也可以说，利用移相器13对第一合成信号IFI中S1r*Ar1(jA1+jA2)+S1i*Ai1(-A1+A2)的相位加90°。这样一来，IFI+90°＝j*(S1r*Ar1(jA1+jA2)+S1i*Ai1(-A1+A2))＝jS1i*Ai1(-A1+A2)-S1r*Ar1(A1+A2)。
之后，可以利用差分电路14对第二合成信号IFQ和90°移相后的第一合成信号IFI进行相加，以滤除镜像干扰信号，输出有用信号IF OUT。由于移相器13与差分电路14的负输入端耦合，第二加减器12与差分电路14的正输入端耦合，因此，可以利用差分电路14对第二合成信号IFQ与移相90°后的第一合成信号IFI作差，IF OUT＝S2r*Ar1(-A1+A2)+S2i*Ai1(jA1+jA2)-(jS1i*Ai1(-A1+A2)-S1r*Ar1(A1+A2))＝A1(jAi1*(S2i+S1i)+Ar1*(S1r-S2r))+A2(-jAi1*(S1i-S2i)+Ar1(S1r+S2r))。
设定当S1i＝S2i，S1r＝-S2r时，即，第三数字信号S1i的符号与第四数字信号S2i的符号相同，第一数字信号S1r的符号与第二数字信号S2r的符号相反时，保留第一信号 作为有用信号，滤除第二信号。当S1i＝-S2i，S1r＝S2r时，即，第三数字信号S1i的符号与第四数字信号S2i的符号相反，第一数字信号S1r的符号与第二数字信号S2r的符号相同时，保留第二信号作为有用信号，滤除第一信号。
而根据前述表1和表2，不论保留第一信号，还是保留第二信号，通过调节第一数字信号S1r、第二数字信号S2r、第三数字信号S1i和第四数字信号S2r为1或为0，还可以调节第一信号所在的象限。具体可以包括如下八种情况：
第一种情况，如图3a和图5h所示，以第一信号为有用信号，第二信号为镜像干扰信号，且有用信号所在的象限为第一象限为例，参考上述表1，符号码生成器向第一加减器11输入的第一数字信号和第三数字信号均为1，第一同相中频信号IFIr和第二正交中频信号IFQi的相位均为正。符号码生成器向第二加减器12输入的第二数字信号为0、第四数字信号为1，第一正交中频信号IFQr的相位为负，第二同相中频信号IFIi的相位为正。
这样一来，第一加减器11可以控制相位为正的第一同相中频信号IFIr与相位为正的第二正交中频信号IFQi矢量相加，得到第一合成信号IFI。其中，如图5i所示，相位为90°的第一同相中频信号jA1Ar1，与相位为180°的第二正交中频信号-A1Ai1矢量相加后，二者的矢量和第一合成信号IFI为jA1Ar1-A1Ai1，jA1Ar1-A1Ai1的相位位于第二象限。相位为90°的第一同相中频信号jA2Ar1，与相位为0°的第二正交中频信号A2Ai1矢量相加后，二者的矢量和第一合成信号IFI为jA2Ar1+A2Ai1，jA2Ar1+A2Ai1的相位位于第一象限。
同理，第二加减器12可以控制相位为负的第一正交中频信号IFQr与相位为正的第二同相中频信号IFIi矢量相加，得到第二合成信号IFQ。其中，如图5j所示，相位为180°的第一正交中频信号-A1Ar1取反后，相位为0°，其与相位为90°的第二同相中频信号jA1Ai1矢量相加后，二者的矢量和第二合成信号IFQ为-(-A1Ar1)+jA1Ai1＝jA1Ai1+A1Ar1，jA1Ai1+A1Ar1的相位位于第一象限。相位为0°的第一正交中频信号A2Ar1，取反后，相位为180°，与相位为90°的第二同相中频信号jA2Ai1矢量相加后，二者的矢量和第二合成信号IFQ为jA2Ai1-A2Ar1，jA2Ai1-A2Ar1的相位位于第二象限。
如图5i和图5j所示，由于第一合成信号IFI和第二合成信号IFQ均包括参数Ar1和Ai1，因此，第一合成信号IFI和第二合成信号IFQ具有相同的幅度。基于表1和表2中的第一数字信号S1r、第二数字信号S2r、第三数字信号S1i和第四数字信号S2r，可以控制第一合成信号IFI与第二合成信号IFQ具有正交的相位。
基于此，如图5k所示，可以利用移相器13对第一合成信号IFI中的jA1Ar1-A1Ai1和jA2Ar1+A2Ai1进行90°移相，也可以说，利用移相器13对第一合成信号IFI中jA1Ar1-A1Ai1和jA2Ar1+A2Ai1的相位加90°。请参考图5i和图5k，将第一合成信号jA1Ar1-A1Ai1和第一合成信号jA2Ar1+A2Ai1顺时针旋转90°后，jA1Ar1-A1Ai1转变为j(jA1Ar1-A1Ai1)＝-A1Ar1-jA1Ai1，jA2Ar1+A2Ai1转变为j(jA2Ar1+A2Ai1)＝jA2Ai1-A2Ar1。
如图3a和图5l所示，由于移相器13与差分电路14的负输入端耦合，第二加减器 12与差分电路的正输入端耦合，因此，可以利用差分电路14对第二合成信号IFQ与移相90°后的第一合成信号IFI作差，即，jA1Ai1+A1Ar1-(-A1Ar1-jA1Ai1)＝2(jA1Ai1+A1Ar1)，jA2Ai1-A2Ar1-(jA2Ai1-A2Ar1)＝0。这样一来，即可滤除由第二射频信号A2与第一本振信号LOI和第二本振信号LOQ混频得到的第二信号，保留第一信号作为有用信号。并且，保留的第一信号与第二合成信号IFQ中jA1Ai1+A1Ar1的相位相同，位于第一象限。
第二种情况，如图5h和图6a所示，以第一信号为有用信号，第二信号为镜像干扰信号，且有用信号所在的象限为第二象限为例，参考上述表1，符号码生成器向第一加减器11输入的第一数字信号为0、第三数字信号为1，第一同相中频信号IFIr的相位为负，第二正交中频信号IFQi的相位为正。符号码生成器向第二加减器12输入的第二数字信号和第四数字信号均为1，第一正交中频信号IFQr和第二同相中频信号IFIi的相位均为正。
这样一来，第一加减器11可以控制相位为负的第一同相中频信号IFIr与相位为正的第二正交中频信号IFQi矢量相加，得到第一合成信号IFI。其中，相位为90°的第一同相中频信号jA1Ar1取反后，相位为270°，其与相位为180°的第二正交中频信号-A1Ai1矢量相加后，二者的矢量和第一合成信号IFI为-jA1Ar1-A1Ai1，-jA1Ar1-A1Ai1的相位位于第三象限。相位为90°的第一同相中频信号jA2Ar1取反后，相位为270°，其与相位为0°的第二正交中频信号A2Ai1矢量相加后，二者的矢量和第一合成信号IFI为-jA2Ar1+A2Ai1，-jA2Ar1+A2Ai1的相位位于第四象限。
同理，第二加减器12可以控制相位为正的第一正交中频信号IFQr与相位为正的第二同相中频信号IFIi矢量相加，得到第二合成信号IFQ。其中，相位为180°的第一正交中频信号-A1Ar1，与相位为90°的第二同相中频信号jA1Ai1矢量相加后，二者的矢量和第二合成信号IFQ为jA1Ai1-A1Ar1，jA1Ai1-A1Ar1的相位位于第二象限。相位为0°的第一正交中频信号A2Ar1，与相位为90°的第二同相中频信号jA2Ai1矢量相加后，二者的矢量和第二合成信号IFQ为jA2Ai1+A2Ar1，jA2Ai1+A2Ar1的相位位于第一象限。
由于第一合成信号IFI和第二合成信号IFQ均包括参数Ar1和Ai1，因此，第一合成信号IFI和第二合成信号IFQ具有相同的幅度。基于表1和表2中的第一数字信号S1r、第二数字信号S2r、第三数字信号S1i和第四数字信号S2r，可以控制第一合成信号IFI与第二合成信号IFQ具有正交的相位。
基于此，可以利用移相器13对第一合成信号IFI中的-jA1Ar1-A1Ai1和-jA2Ar1+A2Ai1进行90°移相，也可以说，利用移相器13对第一合成信号IFI中-jA1Ar1-A1Ai1和-jA2Ar1+A2Ai1的相位加90°。将第一合成信号-jA1Ar1-A1Ai1和第一合成信号-jA2Ar1+A2Ai1顺时针旋转90°后，-jA1Ar1-A1Ai1转变为j(-jA1Ar1-A1Ai1)＝A1Ar1-jA1Ai1，-jA2Ar1+A2Ai1转变为j(-jA2Ar1+A2Ai1)＝A2Ar1+jA2Ai1。
如图6a所示，由于移相器13与差分电路14的负输入端耦合，第二加减器12与差分电路的正输入端耦合，因此，可以利用差分电路14对第二合成信号IFQ与移相90°后的第一合成信号IFI作差，jA1Ai1-A1Ar1-(A1Ar1-jA1Ai1)＝2(jA1Ai1-A1Ar1)， jA2Ai1+A2Ar1-(A2Ar1+jA2Ai1)＝0。这样一来，即可滤除由第二射频信号A2与第一本振信号LOI和第二本振信号LOQ混频得到的第二信号，保留第一信号作为有用信号。并且，保留的第一信号与第二合成信号IFQ中jA1Ai1-A1Ar1的相位相同，位于第二象限。
第三种情况，如图5h和图6b所示，以第一信号为有用信号，第二信号为镜像干扰信号，且有用信号所在的象限为第三象限为例，参考上述表1，符号码生成器向第一加减器11输入的第一数字信号和第三数字信号均为0，第一同相中频信号IFIr和第二正交中频信号IFQi的相位均为负。符号码生成器向第二加减器12输入的第二数字信号为1、第四数字信号为0，第一正交中频信号IFQr的相位为正，第二同相中频信号IFIi的相位为负。
这样一来，第一加减器11可以控制相位为负的第一同相中频信号IFIr与相位为负的第二正交中频信号IFQi矢量相加，得到第一合成信号IFI。其中，相位为90°的第一同相中频信号jA1Ar1取反后，相位为270°；相位为180°的第二正交中频信号-A1Ai1取反后，相位为0°。取反后的第一同相中频信号jA1Ar1和取反后的第二正交中频信号-A1Ai1矢量相加后，二者的矢量和第一合成信号IFI为-jA1Ar1-(-A1Ai1)＝A1Ai1-jA1Ar1，A1Ai1-jA1Ar1位于第四象限。相位为90°的第一同相中频信号jA2Ar1取反后，相位为270°；相位为0°的第二正交中频信号A2Ai1取反后，相位为180°。取反后的第一同相中频信号jA2Ar1和取反后的第二正交中频信号A2Ai1矢量相加后，二者的矢量和第一合成信号IFI为-jA2Ar1-A2Ai1，-jA2Ar1-A2Ai1的相位位于第三象限。
同理，第二加减器12可以控制相位为正的第一正交中频信号IFQr与相位为负的第二同相中频信号IFIi矢量相加，得到第二合成信号IFQ。其中，相位为90°的第二同相中频信号jA1Ai1取反后，相位为270°，其与相位为180°的第一正交中频信号-A1Ar1矢量相加后，二者的矢量和第二合成信号IFQ为-jA1Ai1+(-A1Ar1)＝-jA1Ai1-A1Ar1，-jA1Ai1-A1Ar1的相位位于第三象限。相位为90°的第二同相中频信号jA2Ai1取反后，相位为270°，其与相位为0°的第一正交中频信号A2Ar1矢量相加后，二者的矢量和第二合成信号IFQ为A2Ar1-jA2Ai1，A2Ar1-jA2Ai1的相位位于第四象限。
由于第一合成信号IFI和第二合成信号IFQ均包括参数Ar1和Ai1，因此，第一合成信号IFI和第二合成信号IFQ具有相同的幅度。基于表1和表2中的第一数字信号S1r、第二数字信号S2r、第三数字信号S1i和第四数字信号S2r，可以控制第一合成信号IFI与第二合成信号IFQ具有正交的相位。
基于此，可以利用移相器13对第一合成信号IFI中的A1Ai1-jA1Ar1和-jA2Ar1-A2Ai1进行90°移相，也可以说，利用移相器13对第一合成信号IFI中A1Ai1-jA1Ar1和-jA2Ar1-A2Ai1的相位加90°。将第一合成信号A1Ai1-jA1Ar1和第一合成信号-jA2Ar1-A2Ai1顺时针旋转90°后，A1Ai1-jA1Ar1转变为j(A1Ai1-jA1Ar1)＝jA1Ai1+A1Ar1，-jA2Ar1-A2Ai1转变为j(-jA2Ar1-A2Ai1)＝A2Ar1-jA2Ai1。
如图6b所示，由于移相器13与差分电路14的负输入端耦合，第二加减器12与差分电路的正输入端耦合，因此，可以利用差分电路14对第二合成信号IFQ与移相90°后的第一合成信号IFI作差，即，-jA1Ai1-A1Ar1-(jA1Ai1+A1Ar1)＝2(-jA1Ai1-A1Ar1)， A2Ar1-jA2Ai1-(A2Ar1-jA2Ai1)＝0。这样一来，即可滤除由第二射频信号A2与第一本振信号LOI和第二本振信号LOQ混频得到的第二信号，保留第一信号作为有用信号。并且，保留的第一信号与第二合成信号IFQ中-jA1Ai1-A1Ar1的相位相同，位于第三象限。
第四种情况，如图5h和图6c所示，以第一信号为有用信号，第二信号为镜像干扰信号，且有用信号所在的象限为第四象限为例，参考上述表1，符号码生成器向第一加减器11输入的第一数字信号为1、第三数字信号为0，第一同相中频信号IFIr的相位为正，第二正交中频信号IFQi的相位为负。符号码生成器向第二加减器12输入的第二数字信号和第四数字信号均为0，第一正交中频信号IFQr和第二同相中频信号IFIi的相位均为负。
这样一来，第一加减器11可以控制相位为正的第一同相中频信号IFIr与相位为负的第二正交中频信号IFQi矢量相加，得到第一合成信号IFI。其中，相位为180°的第二正交中频信号-A1Ai1取反后，相位为0°，其与相位为90°的第一同相中频信号jA1Ar1矢量相加后，二者的矢量和第一合成信号IFI为jA1Ar1-(-A1Ai1)＝jA1Ar1+A1Ai1，jA1Ar1+A1Ai1的相位位于第一象限。相位为0°的第二正交中频信号A2Ai1取反后，相位为180°，其与相位为90°的第一同相中频信号jA2Ar1矢量相加后，二者的矢量和第一合成信号IFI为jA2Ar1-A2Ai1，jA2Ar1-A2Ai1的相位位于第二象限。
同理，第二加减器12可以控制相位为负的第一正交中频信号IFQr与相位为负的第二同相中频信号IFIi矢量相加，得到第二合成信号IFQ。其中，相位为180°的第一正交中频信号-A1Ar1取反后，相位为0°；相位为90°的第二同相中频信号jA1Ai1取反后，相位为270°。取反后的第一正交中频信号-A1Ar1和取反后的第二同相中频信号jA1Ai1相加后，二者的矢量和第二合成信号IFQ为-(-A1Ar1)-jA1Ai1＝-jA1Ai1+A1Ar1，-jA1Ai1+A1Ar1的相位位于第四象限。相位为0°的第一正交中频信号A2Ar1，取反后，相位为180°；相位为90°的第二同相中频信号jA2Ai1取反后，相位为270°。取反后的第一正交中频信号A2Ar1和取反后的第二同相中频信号jA2Ai1矢量相加后，二者的矢量和第二合成信号IFQ为-jA2Ai1-A2Ar1，-jA2Ai1-A2Ar1的相位位于第三象限。
由于第一合成信号IFI和第二合成信号IFQ均包括参数Ar1和Ai1，因此，第一合成信号IFI和第二合成信号IFQ具有相同的幅度。基于表1和表2中的第一数字信号S1r、第二数字信号S2r、第三数字信号S1i和第四数字信号S2r，可以控制第一合成信号IFI与第二合成信号IFQ具有正交的相位。
基于此，可以利用移相器13对第一合成信号IFI中的jA1Ar1+A1Ai1和jA2Ar1-A2Ai1进行90°移相，也可以说，利用移相器13对第一合成信号IFI中jA1Ar1+A1Ai1和jA2Ar1-A2Ai1的相位加90°。将第一合成信号jA1Ar1+A1Ai1和第一合成信号jA2Ar1-A2Ai1顺时针旋转90°后，jA1Ar1+A1Ai1转变为j(jA1Ar1+A1Ai1)＝jA1Ai1-A1Ar1，jA2Ar1+A2Ai1转变为j(jA2Ar1-A2Ai1)＝-A2Ar1-jA2Ai1。
如图6c所示，由于移相器13与差分电路14的负输入端耦合，第二加减器12与差分电路的正输入端耦合，因此，可以利用差分电路14对第二合成信号IFQ与移相90°后的第一合成信号IFI作差，即，-jA1Ai1+A1Ar1-(jA1Ai1-A1Ar1)＝2(A1Ar1-jA1Ai1)， -jA2Ai1-A2Ar1-(-A2Ar1-jA2Ai1)＝0。这样一来，即可滤除由第二射频信号A2与第一本振信号LOI和第二本振信号LOQ混频得到的第二信号，保留第一信号作为有用信号。并且，保留的第一信号与第二合成信号IFQ中-jA1Ai1+A1Ar1的相位相同，位于第四象限。
第五种情况，如图7a和图7b所示，以第一信号为镜像干扰信号，第二信号为有用信号，且有用信号所在的象限为第一象限为例，参考上述表2，符号码生成器向第一加减器11输入的第一数字信号为1、第三数字信号为0，第一同相中频信号IFIr的相位为正，第二正交中频信号IFQi的相位为负。符号码生成器向第二加减器12输入的第二数字信号和第四数字信号均为1，第一正交中频信号IFQr和第二同相中频信号IFIi的相位均为正。
这样一来，第一加减器11可以控制相位为正的第一同相中频信号IFIr与相位为负的第二正交中频信号IFQi矢量相加，得到第一合成信号IFI。其中，相位为180°的第二正交中频信号-A1Ai1取反后，相位为0°，其与相位为90°的第一同相中频信号jA1Ar1矢量相加后，二者的矢量和第一合成信号IFI为jA1Ar1-(-A1Ai1)＝jA1Ar1+A1Ai1，jA1Ar1+A1Ai1的相位位于第一象限。相位为0°的第二正交中频信号A2Ai1取反后，相位为180°，其与相位为90°的第一同相中频信号jA2Ar1矢量相加后，二者的矢量和第一合成信号IFI为jA2Ar1-A2Ai1，jA2Ar1-A2Ai1的相位位于第二象限。
同理，第二加减器12可以控制相位为正的第一正交中频信号IFQr与相位为正的第二同相中频信号IFIi矢量相加，得到第二合成信号IFQ。其中，相位为180°的第一正交中频信号-A1Ar1，与相位为90°的第二同相中频信号jA1Ai1矢量相加后，二者的矢量和第二合成信号IFQ为jA1Ai1-A1Ar1，jA1Ai1-A1Ar1的相位位于第二象限。相位为0°的第一正交中频信号A2Ar1，与相位为90°的第二同相中频信号jA2Ai1矢量相加后，二者的矢量和第二合成信号IFQ为jA2Ai1+A2Ar1，jA2Ai1+A2Ar1的相位位于第一象限。
由于第一合成信号IFI和第二合成信号IFQ均包括参数Ar1和Ai1，因此，第一合成信号IFI和第二合成信号IFQ具有相同的幅度。基于表1和表2中的第一数字信号S1r、第二数字信号S2r、第三数字信号S1i和第四数字信号S2r，可以控制第一合成信号IFI与第二合成信号IFQ具有正交的相位。
基于此，可以利用移相器13对第二合成信号IFQ中的jA1Ar1+A1Ai1和jA2Ar1-A2Ai1进行90°移相，也可以说，利用移相器13对第二合成信号IFQ中jA1Ar1+A1Ai1和jA2Ar1-A2Ai1的相位加90°。将第二合成信号jA1Ar1+A1Ai1和第二合成信号jA2Ar1-A2Ai1顺时针旋转90°后，jA1Ar1+A1Ai1转变为j(jA1Ar1+A1Ai1)＝jA1Ai1-A1Ar1，jA2Ar1-A2Ai1转变为j(jA2Ar1-A2Ai1)＝-A2Ar1-jA2Ai1。
如图7b所示，由于移相器13与差分电路14的负输入端耦合，第二加减器12与差分电路的正输入端耦合，因此，可以利用差分电路14对第二合成信号IFQ与移相90°后的第一合成信号IFI作差，即，jA1Ai1-A1Ar1-(jA1Ai1-A1Ar1)＝0，jA2Ai1+A2Ar1-(-A2Ar1-jA2Ai1)＝2(jA2Ai1+A2Ar1)。这样一来，即可滤除由第一射频信号A1与第一本振信号LOI和第二本振信号LOQ混频得到的第一信号，保留第二信号作为有用信号。 并且，保留的第二信号与第二合成信号IFQ中jA2Ai1+A2Ar1的相位相同，位于第一象限。
第六种情况，如图7a和图7c所示，以第一信号为镜像干扰信号，第二信号为有用信号，且有用信号所在的象限为第四象限为例，参考上述表2，符号码生成器向第一加减器11输入的第一数字信号和第三数字信号均为0，第一同相中频信号IFIr和第二正交中频信号IFQi均为负。符号码生成器向第二加减器12输入的第二数字信号为0、第四数字信号为1，第一正交中频信号IFQr的相位为负，第二同相中频信号IFIi的相位为正。
这样一来，第一加减器11可以控制相位为负的第一同相中频信号IFIr与相位为负的第二正交中频信号IFQi矢量相加，得到第一合成信号IFI。其中，相位为90°的第一同相中频信号jA1Ar1取反后，相位为270°；相位为180°的第二正交中频信号-A1Ai1取反后，相位为0°。取反后的第一同相中频信号jA1Ar1和取反后的第二正交中频信号-A1Ai1矢量相加后，二者的矢量和第一合成信号IFI为-jA1Ar1-(-A1Ai1)＝A1Ai1-jA1Ar1，A1Ai1-jA1Ar1位于第四象限。相位为90°的第一同相中频信号jA2Ar1取反后，相位为270°；相位为0°的第二正交中频信号A2Ai1取反后，相位为180°。取反后的第一同相中频信号jA2Ar1和取反后的第二正交中频信号A2Ai1矢量相加后，二者的矢量和第一合成信号IFI为-jA2Ar1-A2Ai1，-jA2Ar1-A2Ai1的相位位于第三象限。
同理，第二加减器12可以控制相位为负的第一正交中频信号IFQr与相位为正的第二同相中频信号IFIi矢量相加，得到第二合成信号IFQ。其中，如图5j所示，相位为180°的第一正交中频信号-A1Ar1取反后，相位为0°，其与相位为90°的第二同相中频信号jA1Ai1矢量相加后，二者的矢量和第二合成信号IFQ为-(-A1Ar1)+jA1Ai1＝jA1Ai1+A1Ar1，jA1Ai1+A1Ar1的相位位于第一象限。相位为0°的第一正交中频信号A2Ar1，取反后，相位为180°，与相位为90°的第二同相中频信号jA2Ai1矢量相加后，二者的矢量和第二合成信号IFQ为jA2Ai1-A2Ar1，jA2Ai1-A2Ar1的相位位于第二象限。
由于第一合成信号IFI和第二合成信号IFQ均包括参数Ar1和Ai1，因此，第一合成信号IFI和第二合成信号IFQ具有相同的幅度。基于表1和表2中的第一数字信号S1r、第二数字信号S2r、第三数字信号S1i和第四数字信号S2r，可以控制第一合成信号IFI与第二合成信号IFQ具有正交的相位。
基于此，可以利用移相器13对第一合成信号IFI中的A1Ai1-jA1Ar1和-jA2Ar1-A2Ai1进行90°移相，也可以说，利用移相器13对第一合成信号IFI中A1Ai1-jA1Ar1和-jA2Ar1-A2Ai1的相位加90°。将第一合成信号A1Ai1-jA1Ar1和第一合成信号-jA2Ar1-A2Ai1顺时针旋转90°后，A1Ai1-jA1Ar1转变为j(A1Ai1-jA1Ar1)＝jA1Ai1+A1Ar1，-jA2Ar1-A2Ai1转变为j(-jA2Ar1-A2Ai1)＝A2Ar1-jA2Ai1。
如图7c所示，由于移相器13与差分电路14的负输入端耦合，第二加减器12与差分电路的正输入端耦合，因此，可以利用差分电路14对第二合成信号IFQ与移相90°后的第一合成信号IFI作差，即，jA1Ai1+A1Ar1-(jA1Ai1+A1Ar1)＝0，jA2Ai1-A2Ar1-(A2Ar1-jA2Ai1)＝2(jA2Ai1-A2Ar1)。这样一来，即可滤除由第一射频信号A1与第一 本振信号LOI和第二本振信号LOQ混频得到的第一信号，保留第二信号作为有用信号。并且，保留的第二信号与第二合成信号IFQ中jA2Ai1-A2Ar1的相位相同，位于第二象限。
第七种情况，如图7a和图7d所示，以第一信号为镜像干扰信号，第二信号为有用信号，且有用信号所在的象限为第三象限为例，参考上述表2，符号码生成器向第一加减器11输入的第一数字信号为0、第三数字信号为1，第一同相中频信号IFIr的相位为负，第二正交中频信号IFQi的相位为正。符号码生成器向第二加减器12输入的第二数字信号和第四数字信号均为0，第一正交中频信号IFQr和第二同相中频信号IFIi的相位均为负。
这样一来，第一加减器11可以控制相位为负的第一同相中频信号IFIr与相位为正的第二正交中频信号IFQi矢量相加，得到第一合成信号IFI。其中，相位为90°的第一同相中频信号jA1Ar1取反后，相位为270°，其与相位为180°的第二正交中频信号-A1Ai1矢量相加后，二者的矢量和第一合成信号IFI为-jA1Ar1-A1Ai1，-jA1Ar1-A1Ai1的相位位于第三象限。相位为90°的第一同相中频信号jA2Ar1取反后，相位为270°，其与相位为0°的第二正交中频信号A2Ai1矢量相加后，二者的矢量和第一合成信号IFI为-jA2Ar1+A2Ai1，-jA2Ar1+A2Ai1的相位位于第四象限。
同理，第二加减器12可以控制负的第一正交中频信号IFQr与负的第二同相中频信号IFIi矢量相加，得到第二合成信号IFQ。其中，相位为180°的第一正交中频信号-A1Ar1取反后，相位为0°；相位为90°的第二同相中频信号jA1Ai1取反后，相位为270°。取反后的第一正交中频信号-A1Ar1和取反后的第二同相中频信号jA1Ai1矢量相加后，二者的矢量和第二合成信号IFQ为-(-A1Ar1)-jA1Ai1＝-jA1Ai1+A1Ar1，-jA1Ai1+A1Ar1的相位位于第四象限。相位为0°的第一正交中频信号A2Ar1，取反后，相位为180°；相位为90°的第二同相中频信号jA2Ai1取反后，相位为270°。取反后的第一正交中频信号A2Ar1和取反后的第二同相中频信号jA2Ai1矢量相加后，二者的矢量和第二合成信号IFQ为-jA2Ai1-A2Ar1，-jA2Ai1-A2Ar1的相位位于第三象限。
由于第一合成信号IFI和第二合成信号IFQ均包括参数Ar1和Ai1，因此，第一合成信号IFI和第二合成信号IFQ具有相同的幅度。基于表1和表2中的第一数字信号S1r、第二数字信号S2r、第三数字信号S1i和第四数字信号S2r，可以控制第一合成信号IFI与第二合成信号IFQ具有正交的相位。
基于此，可以利用移相器13对第一合成信号IFI中的-jA1Ar1-A1Ai1和-jA2Ar1+A2Ai1进行90°移相，也可以说，利用移相器13对第一合成信号IFI中-jA1Ar1-A1Ai1和-jA2Ar1+A2Ai1的相位加90°。将第二合成信号-jA1Ar1-A1Ai1和第二合成信号-jA2Ar1+A2Ai1顺时针旋转90°后，-jA1Ar1-A1Ai1转变为j(-jA1Ar1-A1Ai1)＝A1Ar1-jA1Ai1，-jA2Ar1+A2Ai1转变为j(-jA2Ar1+A2Ai1)＝A2Ar1+jA2Ai1。
如图7d所示，由于移相器13与差分电路14的负输入端耦合，第二加减器12与差分电路的正输入端耦合，因此，可以利用差分电路14对第二合成信号IFQ与移相90°后的第一合成信号IFI作差，即，A1Ar1-jA1Ai1-(A1Ar1-jA1Ai1)＝0，-jA2Ai1-A2Ar1-(A2Ar1+jA2Ai1)＝2(-jA2Ai1-A2Ar1)。这样一来，即可滤除由第一射频信号A1与第 一本振信号LOI和第二本振信号LOQ混频得到的第一信号，保留第二信号作为有用信号。并且，保留的第二信号与第二合成信号IFQ中-jA2Ai1-A2Ar1的相位相同，位于第三象限。
第八种情况，如图7a和图7e所示，以第一信号为镜像干扰信号，第二信号为有用信号，且有用信号所在的象限为第二象限为例，参考上述表2，符号码生成器向第一加减器11输入的第一数字信号和第三数字信号均为1，第一同相中频信号IFIr和第二正交中频信号IFQi的相位均为正。符号码生成器向第二加减器12输入的第二数字信号为1、第四数字信号为0，第一正交中频信号IFQr的相位为正，第二同相中频信号IFIi的相位为负。
这样一来，第一加减器11可以控制相位为正的第一同相中频信号IFIr与相位为正的第二正交中频信号IFQi矢量相加，得到第一合成信号IFI。其中，如图5i所示，相位为90°的第一同相中频信号jA1Ar1，与相位为180°的第二正交中频信号-A1Ai1矢量相加后，二者的矢量和第一合成信号IFI为jA1Ar1-A1Ai1，jA1Ar1-A1Ai1的相位位于第二象限。相位为90°的第一同相中频信号jA2Ar1，与相位为0°的第二正交中频信号A2Ai1矢量相加后，二者的矢量和第一合成信号IFI为jA2Ar1+A2Ai1，jA2Ar1+A2Ai1的相位位于第一象限。
同理，第二加减器12可以控制相位为正的第一正交中频信号IFQr与相位为负的第二同相中频信号IFIi矢量相加，得到第二合成信号IFQ。其中，相位为90°的第二同相中频信号jA1Ai1取反后，相位为270°，其与相位为180°的第一正交中频信号-A1Ar1矢量相加后，二者的矢量和第二合成信号IFQ为-jA1Ai1+(-A1Ar1)＝-jA1Ai1-A1Ar1，-jA1Ai1-A1Ar1的相位位于第三象限。相位为90°的第二同相中频信号jA2Ai1取反后，相位为270°，其与相位为0°的第一正交中频信号A2Ar1矢量相加后，二者的矢量和第二合成信号IFQ为A2Ar1-jA2Ai1，A2Ar1-jA2Ai1的相位位于第四象限。
由于第一合成信号IFI和第二合成信号IFQ均包括参数Ar1和Ai1，因此，第一合成信号IFI和第二合成信号IFQ具有相同的幅度。基于表1和表2中的第一数字信号S1r、第二数字信号S2r、第三数字信号S1i和第四数字信号S2r，可以控制第一合成信号IFI与第二合成信号IFQ具有正交的相位。
基于此，可以利用移相器13对第一合成信号IFI中的jA1Ar1-A1Ai1和jA2Ar1+A2Ai1进行90°移相，也可以说，利用移相器13对第一合成信号IFI中jA1Ar1-A1Ai1和jA2Ar1+A2Ai1的相位加90°。将第一合成信号jA1Ar1-A1Ai1和第一合成信号jA2Ar1+A2Ai1顺时针旋转90°后，jA1Ar1-A1Ai1转变为j(jA1Ar1-A1Ai1)＝-A1Ar1-jA1Ai1，jA2Ar1+A2Ai1转变为j(jA2Ar1+A2Ai1)＝-A2Ar1+jA2Ai1。
如图7e所示，由于移相器13与差分电路14的负输入端耦合，第二加减器12与差分电路的正输入端耦合，因此，可以利用差分电路14对第二合成信号IFQ与移相90°后的第一合成信号IFI作差，即，-jA1Ai1-A1Ar1-(-A1Ar1-jA1Ai1)＝0，A2Ar1-jA2Ai1-(-A2Ar1+jA2Ai1)＝2(A2Ar1-jA2Ai1)。这样一来，即可滤除由第一射频信号A1与第一本振信号LOI和第二本振信号LOQ混频得到的第一信号，保留第二信号作为有用信号。 并且，保留的第二信号与第二合成信号IFQ中A2Ar1-jA2Ai1的相位相同，位于第四象限。
上述示例是以第一本振信号LOI为sin(ω LOt)，第二本振信号LOQ为cos(ω LOt)为例，列出的多种滤除镜像干扰信号的情况。当然，第一本振信号LOI和第二本振信号LOQ也可以是其他，只要第一本振信号LOI与第二本振信号LOQ正交即可。
此外，图3d、图3e和图3f示出的接收机101对应的三套真值表的计算方式，与前述实施例中第一套真值表的计算方式相同，也在本申请实施例的保护范围内。
对于上文中的第一加减器11、第二加减器12和差分电路14的具体电路结构，本申请实施例对此不作限定。
一个实施例中，如图8a所示，符号码生成器可以包括第一开关K1、第二开关K2、第三开关K3、第四开关K4、第一反相器D1、第二反相器D2。第一加减器11可以包括第一差分电路OP1和第二差分电路OP2。其中，第一差分电路OP1和第二差分电路OP2例如可以是运算放大器。
符号码生成器用于生成第一初始数字信号S1；第一开关K1与第二开关K2并联，第一开关K1用于接收第一同相中频信号IFIr和第一初始数字信号S1。第二开关K2与第一反相器D1耦合，用于接收第一同相中频信号IFIr和取反后的第一初始数字信号S1。
符号码生成器还用于生成第三初始数字信号S3；第三开关K3与第四开关K4并联，第三开关K3用于接收第二正交中频信号IFQi和第三初始数字信号S3。第四开关K4与第二反相器D2耦合，用于接收第二正交中频信号IFQi和取反后的第三初始数字信号S3。
第一开关K1和第二开关K2的输出侧与第一差分电路OP1的输入侧耦合，第三开关K3和第四开关K4的输出侧与第二差分电路OP2的输入侧耦合，第一差分电路OP1和第二差分电路OP2的输出侧均与差分电路14的输入侧耦合。
如图8a所示，若第一开关K1与第一差分电路OP1的正输入端耦合，第二开关K2与第一差分电路OP1的负输入端耦合，则输入至第一开关K1和第二开关K2的第一初始数字信号S1为1。若所需的第一数字信号S1r为1，则可以控制第一开关K1导通、第二开关K2断开，第一同相中频信号IFIr通过第一开关K1输入至第一差分电路OP1的正输入端，并从第一差分电路OP1输出；若所需的第一数字信号S1r为0，则可以控制第一开关K1断开、第二开关K2导通，第一同相中频信号IFIr通过第二开关K2输入至第一差分电路OP1的负输入端，第一差分电路OP1对第一同相中频信号IFIr取反后输出。
或者，如图8b所示，若第一开关K1与第一差分电路OP1的负输入端耦合，第二开关K2与第一差分电路OP1的正输入端耦合，则输入至第一开关K1和第二开关K2的第一初始数字信号S1为0。若所需的第一数字信号S1r为1，则可以控制第一开关K1断开、第二开关K2导通，第一同相中频信号IFIr通过第二开关K2输入至第一差分电路OP1的正输入端，并从第一差分电路OP1输出；若所需的第一数字信号S1r为0，则可以控制第一开关K1导通、第二开关K2断开，第一同相中频信号IFIr通过第一开关K1输入至第一差分电路OP1的负输入端，第一差分电路OP1对第一同相中频信号IFIr取反后输出。
如图8a所示，若第三开关K3与第二差分电路OP2的正输入端耦合，第四开关K4 与第二差分电路OP2的负输入端耦合，则输入至第三开关K3和第四开关K4的第三初始数字信号S3为1。若所需的第三数字信号S1i为1，则可以控制第三开关K3导通、第四开关K4断开，第二正交中频信号IFQi通过第三开关K3输入至第二差分电路OP2的正输入端，并从第二差分电路OP2输出；若所需的第三数字信号S1i为0，则可以控制第三开关K3断开、第四开关K4导通，第二正交中频信号IFQi通过第四开关K4输入至第二差分电路OP2的负输入端，第二差分电路OP2对第二正交中频信号IFQi取反后输出。
或者，如图8b所示，若第三开关K3与第二差分电路OP2的负输入端耦合，第四开关K4与第二差分电路OP2的正输入端耦合，则输入至第三开关K3与第四开关K4的第三初始数字信号S3为0。若所需的第三数字信号S1i为1，则可以控制第三开关K3断开、第四开关K4导通，第二正交中频信号IFQi通过第四开关K4输入至第二差分电路OP2的正输入端，并从第二差分电路OP2输出；若所需的第三数字信号S1i为0，则可以控制第三开关K3导通、第四开关K4断开，第二正交中频信号IFQi通过第三开关K3输入至第二差分电路OP2的负输入端，第二差分电路OP2对第二正交中频信号IFQi取反后输出。
进一步的，通过对第一差分电路OP1和第二差分电路OP2输出的信号进行矢量求和，以得到第一合成信号IFI。
如图8c所示，符号码生成器可以包括第五开关K5、第六开关K6、第七开关K7、第八开关K8、第三反相器D3、第四反相器D4。第二加减器12可以包括第三差分电路OP3和第四差分电路OP4。其中，第三差分电路OP3和第四差分电路OP4例如可以是运算放大器。
符号码生成器用于生成第二初始数字信号S2；第五开关K5与第六开关K6并联。第五开关K5用于接收第一正交中频信号IFQr和第二初始数字信号S2。第六开关K6与第三反相器D3耦合，用于接收第一正交中频信号IFQr和取反后的第二初始数字信号S2。
符号码生成器还用于生成第四初始数字信号S4；第七开关K7与第八开关K8并联。第七开关K7用于接收第二同相中频信号IFIi和第四初始数字信号S4。第八开关K8与第四反相器D4耦合，用于接收第二同相中频信号IFIi和取反后的第四初始数字信号S4。
第五开关K5和第六开关K6的输出侧与第三差分电路OP3的输入侧耦合，第七开关K7和第八开关K8的输出侧与第四差分电路OP4的输入侧耦合，第三差分电路OP3和第四差分电路OP4的输出侧均与差分电路14的输入侧耦合。
如图8c所示，若第五开关K5与第三差分电路OP3的正输入端耦合，第六开关K6与第三差分电路OP3的负输入端耦合，则第五开关K5和第六开关K6接收的第二初始数字信号S2为1。若所需的第二数字信号S2r为1，则可以控制第五开关K5导通、第六开关K6断开，第一正交中频信号IFQr通过第五开关K5输入至第三差分电路OP3的正输入端，并从第三差分电路OP3输出；若所需的第二数字信号S2r为0，则可以控制第五开关K5断开、第六开关K6导通，第一正交中频信号IFQr通过第六开关K6输入至第三差分电路OP3的负输入端，第三差分电路OP3对第一正交中频信号IFQr取反后输出。
或者，如图8d所示，若第五开关K5与第三差分电路OP3的负输入端耦合，第六开关K6与第三差分电路OP3的正输入端耦合，则第五开关K5和第六开关K6接收的第二 初始数字信号S2为0。若所需的第二数字信号S2r为1，则可以控制第五开关K5断开、第六开关K6导通，第一正交中频信号IFQr通过第六开关K6输入至第三差分电路OP3的正输入端，并从第三差分电路OP3输出；若所需的第二数字信号S2r为0，则可以控制第五开关K5导通、第六开关K6断开，第一正交中频信号IFQr通过第五开关K5输入至第三差分电路OP3的负输入端，第三差分电路OP3对第一正交中频信号IFQr取反后输出。
如图8c所示，若第七开关K7与第四差分电路OP4的正输入端耦合，第八开关K8与第四差分电路OP4的负输入端耦合，则第七开关K7和第八开关K8接收的第四初始数字信号S4为1。若所需的第四数字信号S2i为1，则可以控制第七开关K7导通、第八开关K8断开，第二同相中频信号IFIi通过第七开关K7输入至第四差分电路OP4的正输入端，并从第四差分电路OP4输出；若所需的第四数字信号S2i为0，则可以控制第七开关K7断开、第八开关K8导通，第二同相中频信号IFIi通过第八开关K8输入至第四差分电路OP4的负输入端，第四差分电路OP4对第二同相中频信号IFIi取反后输出。
或者，如图8d所示，若第七开关K7与第四差分电路OP4的负输入端耦合，第八开关K8与第四差分电路OP4的正输入端耦合，则第七开关K7和第八开关K8接收的第四初始数字信号S4为0。若所需的第四数字信号S2i为1，则可以控制第七开关K7断开、第八开关K8导通，第二同相中频信号IFIi通过第八开关K8输入至第四差分电路OP4的正输入端，并从第四差分电路OP4输出。若所需的第四数字信号S2i为0，则可以控制第七开关K7导通、第八开关K8断开，第二同相中频信号IFIi通过第七开关K7输入至第四差分电路OP4的负输入端，第四差分电路OP4对第二同相中频信号IFIi取反后输出。
进一步的，通过对第三差分电路OP3和第四差分电路OP4输出的信号进行矢量求和，以得到第二合成信号IFQ。
在一些可能实现的方式中，本申请实施例可以基于象限控制码、镜像抑制模式，确定第一数字信号S1r、第二数字信号S2r、第三数字信号S1i和第四数字信号S2r为1或为0，以控制第一开关K1、第二开关K2、第三开关K3、第四开关K4、第五开关K5、第六开关K6、第七开关K7和第八开关K8导通或断开，并执行前述四套真值表中的其中一种。
另一个实施例中，如图9a所示，第三可调射频放大器VGA3、第四可调射频放大器VGA4、第五可调射频放大器VGA5、以及第六可调射频放大器VGA6可以与符号码生成器集成在一起。第三可调射频放大器VGA3包括第一子放大器和第二子放大器，第四可调射频放大器VGA4包括第三子放大器和第四子放大器，第五可调射频放大器VGA5包括第五子放大器和第六子放大器，第六可调射频放大器VGA6包括第七子放大器和第八子放大器。
如图9b所示，符号码生成器包括第一与门M1、第二与门M2、第三与门M3、第四与门M4、第五反相器、第六反相器。第一加减器11包括第五差分电路OP5和第六差分电路OP6。
第一与门M1用于接收第三增益r2和第一初始数字信号S1；第一与门M1的输出侧与第一子放大器耦合。第一子放大器的输入侧接收第一同相中频信号IFIr，输出侧与第五差分电路OP5耦合。
第二与门M2用于接收第四增益i2和第三初始数字信号S3；第二与门M2的输出侧与第五子放大器耦合。第五子放大器的输入侧接收第二正交中频信号IFQi，输出侧与第六差分电路OP6耦合。
第三与门M3用于接收第四增益i2和通过第五反相器取反后的第三初始数字信号S3；第三与门M3的输出侧与第六子放大器耦合。第六子放大器的输入侧接收第二正交中频信号IFQi，输出侧与第五差分电路OP5耦合。
第四与门M4用于接收第三增益r2和通过第六反相器取反后的第一初始数字信号S1；第四与门M4的输出侧与第二子放大器耦合。第二子放大器的输入侧接收第一同相中频信号IFIr，输出侧与第六差分电路OP6耦合。
在上述基础上，第五差分电路OP5的输出侧和第六差分电路OP6的输出侧均与差分电路14的输入侧耦合。
如图9b所示，若第一子放大器的输出侧与第五差分电路OP5的正输入端耦合，第二子放大器的输出侧与第六差分电路OP6的负输入端耦合，则第一与门M1和第四与门M4接收的第一初始数字信号S1为1。若所需的第一数字信号S1r为1，则可以向第一子放大器输入使能，而不向第二子放大器输入使能，使第一子放大器正常工作、第二子放大器不工作。第三增益r2和为1的第一初始数字信号S1(也可以说，第一数字信号S1r)通过第一与门M1输入至第一子放大器，第一同相中频信号IFIr通过第一子放大器输入至第五差分电路OP5的正输入端，并从第五差分电路OP5输出。若所需的第一数字信号S1r为0，则可以向第二子放大器输入使能，而不向第一子放大器输入使能，使第一子放大器不工作、第二子放大器正常工作。为1的第一初始数字信号S1和取反后得到为0的第一数字信号S1r，第三增益r2和为0的第一数字信号S1r通过第四与门M4输入至第二子放大器，第一同相中频信号IFIr通过第二子放大器输入至第六差分电路OP6的负输入端，在第六差分电路OP6中取反后，从第六差分电路OP6输出。
或者，如图9c所示，若第一子放大器的输出侧与第五差分电路OP5的负输入端耦合，第二子放大器的输出侧与第六差分电路OP6的正输入端耦合，则第一与门M1和第四与门M4接收的第一初始数字信号S1为0。若所需的第一数字信号S1r为1，则可以向第二子放大器输入使能，而不向第一子放大器输入使能，使第一子放大器不工作、第二子放大器正常工作。为0的第一初始数字信号S1和取反后得到为1的第一数字信号S1r，第三增益r2和为1的第一数字信号S1r通过第四与门M4输入至第二子放大器，第一同相中频信号IFIr通过第二子放大器输入至第六差分电路OP6的正输入端，并从第六差分电路OP6输出。若所需的第一数字信号S1r为0，则可以向第一子放大器输入使能，而不向第二子放大器输入使能，使第一子放大器正常工作、第二子放大器不工作。第三增益r2和为0的第一初始数字信号S1(也可以说，第一数字信号S1r)通过第一与门M1输入至第一子放大器，第一同相中频信号IFIr通过第一子放大器输入至第五差分电路OP5的负输入端，在第五差分电路OP5中取反后，从第五差分电路OP5输出。
如图9b所示，若第五子放大器的输出侧与第六差分电路OP6的正输入端耦合，第六子放大器的输出侧与第五差分电路OP5的负输入端耦合，则第二与门M2和第三与门M3接收的第三初始数字信号S3为1。若所需的第三数字信号S1i为1，则可以向第五子放大器输入使能，而不向第六子放大器输入使能，使第五子放大器正常工作、第六子放大器不工作。第四增益i2和为1的第三初始数字信号S3(也可以说，第三数字信号S1i)通过第二与门M2输入至第五子放大器，第二正交中频信号IFQi通过第五子放大器输入至第六差分电路OP6的正输入端，并从第六差分电路OP6输出。若所需的第三数字信号S1i为0，则可以向第六子放大器输入使能，而不向第五子放大器输入使能，使第五子放大器不工作、第六子放大器正常工作。为1的第三初始数字信号S3和取反后得到为0的第三数字信号S1i，第四增益i2和为0的第三数字信号S1i通过第三与门M3输入至第六子放大器，第二正交中频信号IFQi通过第六子放大器输入至第五差分电路OP5的负输入端，在第五差分电路OP5中取反后，从第五差分电路OP5输出。
或者，如图9c所示，若第五子放大器的输出侧与第六差分电路OP6的负输入端耦合，第六子放大器的输出侧与第五差分电路OP5的正输入端耦合，则第二与门M2和第三与门M3接收的第三初始数字信号S3为0。若所需的第三数字信号S1i为1，则可以向第六子放大器输入使能，而不向第五子放大器输入使能，使第五子放大器不工作、第六子放大器正常工作。为0的第三初始数字信号S3和取反后得到为1的第三数字信号S1i，第四增益i2和为1的第三数字信号S1i通过第三与门M3输入至第六子放大器，第二正交中频信号IFQi通过第六子放大器输入至第五差分电路OP5的正输入端，并从第五差分电路OP5输出。若所需的第三数字信号S1i为0，则可以向第五子放大器输入使能，而不向第六子放大器输入使能，使第五子放大器正常工作、第六子放大器不工作。第四增益i2和为0的第三初始数字信号S3(也可以说，第三数字信号S1i)通过第二与门M2输入至第五子放大器，第二正交中频信号IFQi通过第五子放大器输入至第六差分电路OP6的负输入端，在第六差分电路OP6中取反后，从第六差分电路OP6输出。
进一步的，通过对第五差分电路OP5和第六差分电路OP6输出的信号进行矢量求和，以得到第一合成信号IFI。
此外，由于控制电路15在第一子放大器输入使能的情况下，不会向第二子放大器输入使能；控制电路15在第五子放大器输入使能的情况下，不会向第六子放大器输入使能。因此，相较于前一实施例，在同一时间内，不会额外增加接收机101的功耗。
如图9d所示，符号码生成器包括第五与门M5、第六与门M6、第七与门M7、第八与门M8、第七反相器、第八反相器。第二加减器12包括第七差分电路OP7和第八差分电路OP8。
第五与门M5用于接收第三增益r2和第二初始数字信号S2；第五与门M5的输出侧与第三子放大器耦合。第三子放大器的输入侧接收第一正交中频信号IFQr，输出侧与第七差分电路OP7耦合。
第六与门M6用于接收第四增益i2和第四初始数字信号S4；第六与门M6的输出侧与第七子放大器耦合。第七子放大器的输入侧接收第二同相中频信号IFIi，输出侧与第八差分电路OP8耦合。
第七与门M7用于接收第四增益i2和通过第七反相器取反后的第四初始数字信号S4；第七与门M7的输出侧与第八子放大器耦合。第八子放大器的输入侧接收第二同相中频信号IFIi，输出侧与第七差分电路OP7耦合。
第八与门M8用于接收第三增益r2和通过第八反相器取反后的第二初始数字信号S2；第八与门M8的输出侧与第四子放大器耦合。第四子放大器的输入侧接收第一正交中频信号IFQr，输出侧与第八差分电路OP8耦合。
在上述基础上，第七差分电路OP7的输出侧和第八差分电路OP8的输出侧均与差分电路14的输入侧耦合。
如图9d所示，若第三子放大器的输出侧与第七差分电路OP7的正输入端耦合，第四子放大器的输出侧与第八差分电路OP8的负输入端耦合，则第五与门M5和第八与门M8接收的第二初始数字信号S2为1。若所需的第二数字信号S2r为1，则可以向第三子放大器输入使能，而不向第四子放大器输入使能，使第三子放大器正常工作、第四子放大器不工作。第三增益r2和为1的第二初始数字信号S2(也可以说，第二数字信号S2r)通过第五与门M5输入至第三子放大器，第一正交中频信号IFQr通过第三子放大器输入至第七差分电路OP7的正输入端，并从第七差分电路OP7输出。若所需的第二数字信号S2r为0，则可以向第四子放大器输入使能，而不向第三子放大器输入使能，使第三子放大器不工作、第四子放大器正常工作。为1的第二初始数字信号S2和取反后得到为0的第二数字信号S2r，第三增益r2和为0的第二数字信号S2r通过第八与门M8输入至第四子放大器，第一正交中频信号IFQr通过第四子放大器输入至第八差分电路OP8的负输入端，在第八差分电路OP8中取反后，从第八差分电路OP8输出。
或者，如图9e所示，若第三子放大器的输出侧与第七差分电路OP7的负输入端耦合，第四子放大器的输出侧与第八差分电路OP8的正输入端耦合，则第五与门M5和第八与门M8接收的第二初始数字信号S2为0。若所需的第二数字信号S2r为1，则可以向第四子放大器输入使能，而不向第三子放大器输入使能，使第三子放大器不工作、第四子放大器正常工作。为0的第二初始数字信号S2和取反后得到为1的第二数字信号S2r，第三增益r2和为1的第二数字信号S2r通过第八与门M8输入至第四子放大器，第一正交中频信号IFQr通过第四子放大器输入至第八差分电路OP8的正输入端，并从第八差分电路OP8输出。若所需的第二数字信号S2r为0，则可以向第三子放大器输入使能，而不向第四子放大器输入使能，使第三子放大器正常工作、第四子放大器不工作。第三增益r2和为0的第二初始数字信号S2(也可以说，第二数字信号S2r)通过第五与门M5输入至第三子放大器，第一正交中频信号IFQr通过第三子放大器输入至第七差分电路OP7的负输入端，在第七差分电路OP7中取反后，从第七差分电路OP7输出。
如图9d所示，若第七子放大器的输出侧与第八差分电路OP8的正输入端耦合，第八子放大器的输出侧与第七差分电路OP7的负输入端耦合，则第六与门M6和第七与门M7接收的第四初始数字信号S4为1。若所需的第四数字信号S2i为1，则可以向第七子放大器输入使能，而不向第八子放大器输入使能，使第七子放大器正常工作、第八子放大器不工作。第四增益i2和为1的第四初始数字信号S4(也可以说，第四数字信号S2i)通过第六与门M6输入至第七子放大器，第二同相中频信号IFIi通过第七子放大器输入 至第八差分电路OP8的正输入端，并从第八差分电路OP8输出。若所需的第四数字信号S2i为0，则可以向第八子放大器输入使能，而不向第七子放大器输入使能，使第七子放大器不工作、第八子放大器正常工作。为1的第四初始数字信号S4和取反后得到为0的第四数字信号S2i，第四增益i2和为0的第四数字信号S2i通过第七与门M7输入至第八子放大器，第二同相中频信号IFIi通过第八子放大器输入至第七差分电路OP7的负输入端，在第七差分电路OP7中取反后，从第七差分电路OP7输出。
或者，如图9e所示，若第七子放大器的输出侧与第八差分电路OP8的负输入端耦合，第八子放大器的输出侧与第七差分电路OP7的正输入端耦合，则第六与门M6和第七与门M7接收的第四初始数字信号S4为0。若所需的第四数字信号S2i为1，则可以向第八子放大器输入使能，而不向第七子放大器输入使能，使第七子放大器不工作、第八子放大器正常工作。为0的第四初始数字信号S4和取反后得到为1的第四数字信号S2i，第四增益i2和为1的第四数字信号S2i通过第七与门M7输入至第八子放大器，第二同相中频信号IFIi通过第八子放大器输入至第七差分电路OP7的正输入端，并从第七差分电路OP7输出。若所需的第四数字信号S2i为0，则可以向第七子放大器输入使能，而不向第八子放大器输入使能，使第七子放大器正常工作、第八子放大器不工作。第四增益i2和为0的第四初始数字信号S4(也可以说，第四数字信号S2i)通过第六与门M6输入至第七子放大器，第二同相中频信号IFIi通过第七子放大器输入至第八差分电路OP8的负输入端，在第八差分电路OP8中取反后，从第八差分电路OP8输出。
进一步的，通过对第七差分电路OP7和第八差分电路OP8输出的信号进行矢量求和，以得到第二合成信号IFQ。
此外，由于控制电路15在第三子放大器输入使能的情况下，不会向第四子放大器输入使能；控制电路15在第七子放大器输入使能的情况下，不会向第八子放大器输入使能。因此，相较于前一实施例，在同一时间内，不会额外增加接收机101的功耗。
上述两个实施例示出了两种符号码控制器向第一加减器11和第二加减器12输入第一数字信号S1r、第二数字信号S2r、第三数字信号S1i和第四数字信号S2i的情况，当然，还可以采用其他电路结构向第一加减器11和第二加减器12输入第一数字信号S1r、第二数字信号S2r、第三数字信号S1i和第四数字信号S2i，本申请实施例对此不作限定，只要其向第一加减器11和第二加减器12输入第一数字信号S1r、第二数字信号S2r、第三数字信号S1i和第四数字信号S2i的规律符合前述四套真值表，均属于本申请的保护之内。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。

Claims (26)

  1. 一种接收机，其特征在于，包括第一可调射频放大器、第二可调射频放大器、第一同相混频器、第一正交混频器、第二正交混频器、第二同相混频器、第一加减器、以及第二加减器；
    所述接收机用于接收射频信号；
    所述射频信号经过所述第一可调射频放大器放大后输出第一射频放大信号；
    所述射频信号经过所述第二可调射频放大器放大后输出第二射频放大信号；
    所述第一射频放大信号经过所述第一同相混频器混频后输出第一同相中频信号，经过所述第一正交混频器混频后输出第一正交中频信号；
    所述第二射频放大信号经过所述第二正交混频器混频后输出第二正交中频信号，经过所述第二同相混频器混频后输出第二同相中频信号；
    所述第一同相中频信号和所述第二正交中频信号通过所述第一加减器进行可选择的加或者减后输出第一合成信号；所述第一正交中频信号和所述第二同相中频信号通过所述第二加减器进行可选择的加或者减后输出第二合成信号。
  2. 根据权利1所述的接收机，其特征在于，所述第一可调射频放大器以可调的第一增益对所述射频信号进行放大；所述第二可调射频放大器以可调的第二增益对所述射频信号进行放大。
  3. 根据权利要求2所述的接收机，其特征在于，所述第一射频放大信号和第一本振信号经过所述第一同相混频器混频后，输出所述第一同相中频信号；
    所述第一射频放大信号和第二本振信号经过所述第一正交混频器混频后，输出所述第一正交中频信号；
    所述第二射频放大信号和所述第二本振信号经过所述第二正交混频器混频后，输出所述第二正交中频信号；
    所述第二射频放大信号和所述第一本振信号经过所述第二同相混频器混频后，输出所述第二同相中频信号；
    其中，所述第一本振信号与所述第二本振信号正交。
  4. 根据权利要求2或3所述的接收机，其特征在于，所述接收机还包括控制电路，所述控制电路包括控制码生成器，所述控制码生成器用于向所述第一可调射频放大器输入 所述第一增益，向所述第二可调射频放大器输入所述第二增益。
  5. 根据权利要求4所述的接收机，其特征在于，所述控制电路还包括符号码生成器，所述符号码生成器用于向所述第一加减器输入第一数字信号和第三数字信号，向所述第二加减器输入第二数字信号和第四数字信号；
    所述第一数字信号用于决定所述第一同相中频信号的相位为正或为负；所述第二数字信号用于决定所述第一正交中频信号的相位为正或为负；所述第三数字信号用于决定所述第二正交中频信号的相位为正或为负；所述第四数字信号用于决定所述第二同相中频信号的相位为正或为负。
  6. 根据权利要求5所述的接收机，其特征在于，所述第一数字信号为1，所述第一同相中频信号的相位为正；所述第一数字信号为0，所述第一同相中频信号的相位为负；
    所述第二数字信号为1，所述第一正交中频信号的相位为正；所述第二数字信号为0，所述第一正交中频信号的相位为负；
    所述第三数字信号为1，所述第二正交中频信号相位为正；所述第三数字信号为0，所述第二正交中频信号相位为负；
    所述第四数字信号为1，所述第二同相中频信号相位为正；所述第四数字信号为0，所述第二同相中频信号相位为负。
  7. 根据权利要求5或6所述的接收机，其特征在于，根据所述第一数字信号和所述第三数字信号，所述第一加减器对相位为正/负的所述第一同相中频信号与相位为正/负的所述第二正交中频信号进行矢量合成，得到第一合成信号；
    根据所述第二数字信号和所述第四数字信号，所述第二加减器对相位为正/负的所述第一正交中频信号与相位为正/负的所述第二同相中频信号进行矢量合成，得到第二合成信号。
  8. 根据权利要求7所述的接收机，其特征在于，所述镜像抑制电路还包括差分电路和移相器；
    所述移相器耦合于所述第一加减器与所述差分电路之间，用于对所述第一合成信号进行90°移相；或者，所述移相器耦合于所述第二加减器与所述差分电路之间，用于对所述第二合成信号进行90°移相；
    所述差分电路用于对所述第二合成信号和移相后的所述第一合成信号，或者对所述第一合成信号和移相后的所述第二合成信号进行相加，以滤除所述第一合成信号和所述第二合成信号中的镜像干扰信号。
  9. 根据权利要求8所述的接收机，其特征在于，所述移相器与所述差分电路的正输入端耦合；或者，
    所述移相器与所述差分电路的负输入端耦合。
  10. 根据权利要求8或9所述的接收机，其特征在于，所述射频信号包括第一射频信号和第二射频信号，所述第一射频信号和所述第二射频信号关于所述第一本振信号或者所述第二本振信号镜像对称；所述第一合成信号和所述第二合成信号均包括第一信号和第二信号；所述第一信号经所述第一射频信号放大、混频得到，所述第二信号经所述第二射频信号放大、混频得到；
    所述第一信号为有用信号，所述第二信号为所述镜像干扰信号；或者，
    所述第一信号为所述镜像干扰信号，所述第二信号为所述有用信号。
  11. 根据权利要求10所述的接收机，其特征在于，所述控制码生成器与所述符号码生成器耦合；
    所述符号码生成器还用于接收镜像抑制控制码以及所述控制码生成器发送的象限控制码，并根据所述象限控制码、所述镜像抑制控制码、所述移相器与所述第一加减器和所述第二加减器的耦合关系、以及所述移相器与所述差分电路的输入端的耦合关系，向所述第一加减器输入所述第一数字信号和所述第三数字信号，向所述第二加减器输入所述第二数字信号和所述第四数字信号；
    所述象限控制码用于表征所述有用信号所在的象限；所述镜像抑制模式用于表征所述第一信号为所述有用信号，或者所述第二信号为所述有用信号。
  12. 根据权利要求10所述的接收机，其特征在于，所述符号码生成器包括第一开关、第二开关、第三开关、第四开关、第一反相器和第二反相器；所述第一加减器包括第一差分电路和第二差分电路；
    所述符号码生成器用于生成第一初始数字信号；所述第一开关与所述第二开关并联；所述第一开关用于接收所述第一同相中频信号和所述第一初始数字信号；所述第二开关与所述第一反相器耦合，用于接收所述第一同相中频信号和取反后的所述第一初始数字信号；
    所述符号码生成器还用于生成第三初始数字信号；所述第三开关与所述第四开关并联；所述第三开关用于接收所述第二正交中频信号和所述第三初始数字信号；所述第四开关与所述第二反相器耦合，用于接收所述第二正交中频信号和取反后的所述第三初始数字信号；
    所述第一开关和所述第二开关的输出侧与所述第一差分电路的输入侧耦合，所述第三开关和所述第四开关的输出侧与所述第二差分电路的输入侧耦合，所述第一差分电路和所述第二差分电路的输出侧均与所述差分电路的输入侧耦合。
  13. 根据权利要求12所述的接收机，其特征在于，所述第一开关与所述第一差分电路的正输入端耦合，所述第二开关与所述第一差分电路的负输入端耦合，输入至所述第一开关和所述第二开关的所述第一初始数字信号为1；或者，
    所述第一开关与所述第一差分电路的负输入端耦合，所述第二开关与所述第一差分电路的正输入端耦合，输入至所述第一开关和所述第二开关的所述第一初始数字信号为0。
  14. 根据权利要求12或13所述的接收机，其特征在于，所述第三开关与所述第二差分电路的正输入端耦合，所述第四开关与所述第二差分电路的负输入端耦合，输入至所述第三开关和所述第四开关的所述第三初始数字信号为1；或者，
    所述第三开关与所述第二差分电路的负输入端耦合，所述第四开关与所述第二差分电路的正输入端耦合，输入至所述第三开关和所述第四开关的所述第三初始数字信号为0。
  15. 根据权利要求12-14任一项所述的接收机，其特征在于，所述符号码生成器包括第五开关、第六开关、第七开关、第八开关、第三反相器和第四反相器；所述第二加减器包括第三差分电路和第四差分电路；
    所述符号码生成器用于生成第二初始数字信号；所述第五开关与所述第六开关并联；所述第五开关用于接收所述第一正交中频信号和所述第二初始数字信号；所述第六开关与所述第三反相器耦合，用于接收所述第一正交中频信号和取反后的所述第二初始数字信号；
    所述符号码生成器还用于生成第四初始数字信号；所述第七开关与所述第八开关并联；所述第七开关用于接收所述第二同相中频信号和所述第四初始数字信号；所述第八开关与所述第四反相器耦合，用于接收所述第二同相中频信号和取反后的所述第四初始数字信号；
    所述第五开关和所述第六开关的输出侧与所述第三差分电路的输入侧耦合，所述第七开关和所述第八开关的输出侧与所述第四差分电路的输入侧耦合，所述第三差分电路和所述第四差分电路的输出侧均与所述差分电路的输入侧耦合。
  16. 根据权利要求14所述的接收机，其特征在于，所述第五开关与所述第三差分电路的正输入端耦合，所述第六开关与所述第三差分电路的负输入端耦合，输入至所述第五开关和所述第六开关的所述第二初始数字信号为1；或者，
    所述第五开关与所述第三差分电路的负输入端耦合，所述第六开关与所述第三差分 电路的正输入端耦合，输入至所述第五开关和所述第六开关的所述第二初始数字信号为0。
  17. 根据权利要求15或16所述的接收机，其特征在于，所述第七开关与所述第四差分电路的正输入端耦合，所述第八开关与所述第四差分电路的负输入端耦合，输入至所述第七开关和所述第八开关的所述第四初始数字信号为1；或者，
    所述第七开关与所述第四差分电路的负输入端耦合，所述第八开关与所述第四差分电路的正输入端耦合，输入至所述第七开关和所述第八开关的所述第四初始数字信号为0。
  18. 根据权利要求11所述的接收机，其特征在于，所述接收机还包括第三可调射频放大器、第四可调射频放大器、第五可调射频放大器、第六可调射频放大器；
    经过所述第三可调射频放大器以第三增益放大后的所述第一同相中频信号，与经过所述第五可调射频放大器以第四增益放大后的所述第二正交中频信号，通过所述第一加减器进行可选择的加或者减后输出所述第一合成信号；
    经过所述第四可调射频放大器以第三增益放大后的所述第一正交中频信号，与经过所述第六可调射频放大器以第四增益放大后的所述第二同相中频信号，通过所述第二加减器进行可选择的加或者减后输出所述第二合成信号。
  19. 根据权利要求18所述的接收机，其特征在于，所述第三可调射频放大器包括第一子放大器和第二子放大器、所述第四可调射频放大器包括第三子放大器和第四子放大器、所述第五可调射频放大器包括第五子放大器和第六子放大器、所述第六可调射频放大器包括第七子放大器和第八子放大器；
    所述符号码生成器包括第一与门、第二与门、第三与门、第四与门、第五反相器、第六反相器；所述第一加减器包括第五差分电路和第六差分电路；
    所述第一与门用于接收所述第三增益和第一初始数字信号；所述第一与门的输出侧与所述第一子放大器耦合；所述第一子放大器的输入侧接收所述第一同相中频信号，输出侧与所述第五差分电路耦合；
    所述第二与门用于接收所述第四增益和第三初始数字信号；所述第二与门的输出侧与所述第五子放大器耦合；所述第五子放大器的输入侧接收所述第二正交中频信号，输出侧与所述第六差分电路耦合；
    所述第三与门用于接收所述第四增益和通过所述第五反相器取反后的所述第三初始数字信号；所述第三与门的输出侧与所述第六子放大器耦合；所述第六子放大器的输入侧接收所述第二正交中频信号，输出侧与所述第五差分电路耦合；
    所述第四与门用于接收所述第三增益和通过所述第六反相器取反后的所述第一初始 数字信号；所述第四与门的输出侧与所述第二子放大器耦合；所述第二子放大器的输入侧接收所述第一同相中频信号，输出侧与所述第六差分电路耦合；
    所述第五差分电路的输出侧和所述第六差分电路的输出侧均与所述差分电路的输入侧耦合。
  20. 根据权利要求19所述的接收机，其特征在于，所述第一子放大器的输出侧与所述第五差分电路的正输入端耦合，所述第二子放大器的输出侧与所述第六差分电路的负输入端耦合，所述第一与门和所述第四与门接收的所述第一初始数字信号为1；或者，
    所述第一子放大器的输出侧与所述第五差分电路的负输入端耦合，所述第二子放大器的输出侧与所述第六差分电路的正输入端耦合，所述第一与门和所述第四与门接收的所述第一初始数字信号为0。
  21. 根据权利要求19或20所述的接收机，其特征在于，所述第五子放大器的输出侧与所述第六差分电路的正输入端耦合，所述第六子放大器的输出侧与所述第五差分电路的负输入端耦合，所述第二与门和所述第三与门接收的所述第三初始数字信号为1；或者，
    所述第五子放大器的输出侧与所述第六差分电路的负输入端耦合，所述第六子放大器的输出侧与所述第五差分电路的正输入端耦合，所述第二与门和所述第三与门接收的所述第三初始数字信号为0。
  22. 根据权利要求18-21任一项所述的接收机，其特征在于，所述符号码生成器还包括第五与门、第六与门、第七与门、第八与门、第七反相器、第八反相器；所述第二加减器包括第七差分电路和第八差分电路；
    所述第五与门用于接收所述第三增益和第二初始数字信号；所述第五与门的输出侧与所述第三子放大器耦合；所述第三子放大器的输入侧接收所述第一正交中频信号，输出侧与所述第七差分电路耦合；
    所述第六与门用于接收所述第四增益和第四初始数字信号；所述第六与门的输出侧与所述第七子放大器耦合；所述第七子放大器的输入侧接收所述第二同相中频信号，输出侧与索虎第八差分电路耦合；
    所述第七与门用于接收所述第二增益和通过所述第七反相器取反后的第四初始数字信号；所述第七与门的输出侧与所述第八子放大器耦合；所述第八子放大器的输入侧接收所述第二同相中频信号，输出侧与所述第七差分电路耦合；
    所述第八与门用于接收所述第一增益和通过所述第八反相器取反后的第二初始数字信号；所述第八与门的输出侧与所述第四子放大器耦合；所述第四子放大器的输入侧接收所述第一正交中频信号，输出侧与所述第八差分电路耦合；
    所述第七差分电路的输出侧和所述第八差分电路的输出侧均与所述差分电路的输入侧耦合。
  23. 根据权利要求22所述的接收机，其特征在于，所述第三子放大器的输出侧与所述第七差分电路的正输入端耦合，所述第四子放大器的输出侧与所述第八差分电路的负输入端耦合，所述第五与门和所述第八与门接收的第二初始数字信号为1；或者，
    所述第三子放大器的输出侧与所述第七差分电路的负输入端耦合，所述第四子放大器的输出侧与所述第八差分电路的正输入端耦合，所述第五与门和所述第八与门接收的第二初始数字信号为0。
  24. 根据权利要求22或23所述的接收机，其特征在于，所述第七子放大器的输出侧与所述第八差分电路的正输入端耦合，所述第八子放大器的输出侧与所述第七差分电路的负输入端耦合，所述第六与门和所述第七与门接收的第四初始数字信号为1；或者，
    所述第七子放大器的输出侧与所述第八差分电路的负输入端耦合，所述第八子放大器的输出侧与所述第七差分电路的正输入端耦合，所述第六与门和所述第七与门接收的第四初始数字信号为0。
  25. 一种射频收发器，其特征在于，包括发射机和权利要求1-24任一项所述的接收机。
  26. 一种终端，其特征在于，包括天线和权利要求25所述的射频收发器。
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