WO2023212988A1 - 半导体结构的制作方法及半导体结构 - Google Patents

半导体结构的制作方法及半导体结构 Download PDF

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WO2023212988A1
WO2023212988A1 PCT/CN2022/094659 CN2022094659W WO2023212988A1 WO 2023212988 A1 WO2023212988 A1 WO 2023212988A1 CN 2022094659 W CN2022094659 W CN 2022094659W WO 2023212988 A1 WO2023212988 A1 WO 2023212988A1
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Prior art keywords
contact hole
layer
semiconductor structure
semiconductor
manufacturing
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English (en)
French (fr)
Inventor
藏俊生
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Changxin Memory Technologies Inc
Changxin Jidian Beijing Memory Technologies Co Ltd
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Changxin Memory Technologies Inc
Changxin Jidian Beijing Memory Technologies Co Ltd
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Priority to US17/810,034 priority Critical patent/US20230360963A1/en
Publication of WO2023212988A1 publication Critical patent/WO2023212988A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/082—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/083—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being via holes penetrating underlying conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/23—Cleaning during device manufacture during, before or after processing of insulating materials
    • H10P70/234—Cleaning during device manufacture during, before or after processing of insulating materials the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/23—Cleaning during device manufacture during, before or after processing of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H10W20/0765—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches the thin functional dielectric layers being temporary, e.g. sacrificial layers

Definitions

  • the present disclosure relates to a method for manufacturing a semiconductor structure and a semiconductor structure.
  • the height of devices (such as capacitor structures) in semiconductor structures continues to increase, making the length of contact structures longer and longer.
  • a contact hole needs to be formed in the semiconductor structure.
  • the etching rates of the long side walls and short side walls of the contact holes are different, subsequent problems will occur.
  • the problem of bridging defects reduces the performance and yield of semiconductor structures.
  • the present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure.
  • a first aspect of the present disclosure provides a method for manufacturing a semiconductor structure, including:
  • a semiconductor substrate having a first contact hole, the first contact hole having a preset cross-sectional pattern including long side walls and short side walls;
  • the first contact hole is processed to form a second contact hole below the first contact hole, and the second contact hole is connected to the first contact hole, wherein the second contact hole is parallel to the semiconductor substrate.
  • the plane of the top surface is a cross-section, and the cross-sectional area of the second contact hole is smaller than the cross-sectional area of the partial area of the first contact hole, and the partial area is between the first contact hole and the second contact hole. The area above where the holes meet.
  • forming a sacrificial layer on the long sidewall includes:
  • the initial sacrificial layer located on the short sidewall is removed, and the retained initial sacrificial layer forms a sacrificial layer.
  • the method of manufacturing the semiconductor structure further includes:
  • removing the initial sacrificial layer located on the short sidewalls includes:
  • a wet etching process is used to remove the initial sacrificial layer located on the short sidewalls.
  • processing the first contact hole includes:
  • the bottom end of the first contact hole is etched through an etching process.
  • a semiconductor substrate is provided with a first contact hole, the pattern of the first contact hole at a preset cross-section includes long side walls and short side walls, including:
  • the semiconductor substrate including a substrate body and a support structure layer provided on the substrate body;
  • the first contact hole is formed in the support structure layer, and has a predetermined height between the bottom end of the first contact hole and the top surface of the semiconductor substrate.
  • a semiconductor substrate including a substrate body and a support structure layer disposed on the substrate body, including:
  • a stacked dielectric layer, isolation layer and hard mask layer are formed on the substrate body.
  • the dielectric layer is formed from the same material as the sacrificial layer.
  • the method of manufacturing the semiconductor structure further includes:
  • performing a second pre-cleaning process on the second contact hole includes:
  • the side walls of the first contact hole, the side walls and the bottom of the second contact hole are cleaned, wherein the first contact hole and the second contact hole form a contact through hole.
  • a second aspect of the present disclosure provides a semiconductor structure including:
  • the semiconductor substrate includes a substrate body and a support layer provided on the substrate body, wherein the support layer has a first contact hole, and the first contact hole has a preset cross-section pattern including long sides side walls and short side walls;
  • a second contact hole is located below the first contact hole, one end of the second contact hole is connected to the first contact hole, and the other end of the second contact hole exposes the top surface of the substrate body, wherein , taking a plane parallel to the top surface of the substrate body as a cross section, the cross-sectional area of the second contact hole is smaller than the cross-sectional area of a partial region of the first contact hole, and the partial region is the third contact hole.
  • the longitudinal cross-sectional shape of the first contact hole includes an inverted trapezoid
  • the second contact hole has a longitudinal cross-sectional shape including a square shape.
  • a minimum value of a hole diameter of the second contact hole is the same as a hole diameter of the first contact hole.
  • the substrate body includes a semiconductor substrate; or,
  • the substrate body includes a metal layer.
  • the support layer includes a dielectric layer and an isolation layer arranged in a stack, and the dielectric layer is provided on the substrate body.
  • a sacrificial layer is formed on the long side wall of the first contact hole to facilitate the subsequent formation of the second contact hole. , so that the etching rate on any side of the second contact hole remains consistent, effectively reducing the problem of inconsistent etching lengths of the long and short side walls of the contact hole, ensuring the quality of the formed second contact hole, and preventing Bridging defects are created, thereby improving the performance and yield of semiconductor structures.
  • FIG. 1 is a flowchart of a method of fabricating a semiconductor structure according to an exemplary embodiment.
  • FIG. 2 is a schematic diagram of forming a support structure layer in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • FIG. 3 is a schematic diagram showing residual particulate impurities in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • FIG. 4 is a schematic diagram of forming a first through hole in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • FIG. 5 is a schematic diagram of forming an initial sacrificial layer in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • FIG. 6 is a schematic diagram of forming a sacrificial layer on a long sidewall in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • FIG. 7 is a schematic diagram of forming a second through hole in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • FIG. 8 is a schematic diagram of forming a contact via hole and a support layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Second contact hole 20. Support structure layer;
  • Substrate body 101.
  • Substrate body 111. Long side wall;
  • the height of devices (such as capacitor structures) in semiconductor structures continues to increase, making the length of contact structures longer and longer.
  • a contact hole needs to be formed in the semiconductor structure.
  • the etching rate of the wall is less than the etching rate of the long sidewall of the contact hole, so that the cross-sectional shape of the formed contact hole approaches an ellipse.
  • the same contact structure may overlap with adjacent metal layers or active areas. Since the contact structure is made of metal conductive materials, there will be overlap between adjacent metal layers. The problem of bridging defects between layers or active regions reduces the performance and yield of semiconductor structures.
  • exemplary embodiments of the present disclosure provide a method for manufacturing a semiconductor structure.
  • the manufacturing method of the semiconductor structure is introduced below with reference to Figures 1-8.
  • This embodiment does not limit the semiconductor structure.
  • the following will take the semiconductor structure as a dynamic random access memory (DRAM) as an example.
  • DRAM dynamic random access memory
  • this embodiment is not limited to this.
  • the semiconductor structure in this embodiment Other structures are also possible.
  • an exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including the following steps:
  • Step S100 Provide a semiconductor substrate with a first contact hole.
  • the first contact hole has a preset cross-sectional pattern including long side walls and short side walls.
  • Step S200 Form a sacrificial layer on the long sidewall.
  • Step S300 Process the first contact hole to form a second contact hole below the first contact hole.
  • the second contact hole is connected to the first contact hole, wherein a plane parallel to the top surface of the semiconductor substrate is taken as the cross section.
  • the cross-sectional area of the second contact hole is smaller than the cross-sectional area of the partial area of the first contact hole, and the partial area is the area above the connecting position between the first contact hole and the second contact hole.
  • any cross section of the first contact hole 11 in the depth direction can be understood as a preset cross section, that is, That is, the preset cross section may be any cross section of the first contact hole 11 in the opposite direction along the first direction X and within a predetermined height range in the semiconductor substrate 100 .
  • the description in this embodiment takes the orientation shown in the figure as an example.
  • the first direction X is the extending direction from the top surface of the semiconductor substrate 100 to the bottom surface of the semiconductor substrate 100 .
  • the cross-sectional shape of the first contact hole 11 formed by the etching process includes an ellipse, and the sidewalls on both sides of the long axis of the ellipse are defined as the long sidewalls 111 , and the short side of the ellipse is The side walls on both sides of the shaft are short side walls 112 .
  • the etching rate of the long sidewall 111 will be lower than that of the short side.
  • the etching rate of the sidewalls 112 increases the ellipticity of the cross-sectional shape of the first contact hole 11 , which in turn leads to subsequent bridging defects. Therefore, in order to ensure the subsequent etching rate of each sidewall of the second contact hole 12 remain consistent, thereby forming the sacrificial layer 30 on the long sidewalls 111 .
  • the sacrificial layer 30 on the long sidewall 111 is removed.
  • the formation of the contact via (including the first contact hole and the second contact hole) is completed through a two-step etching process.
  • a sacrificial layer is deposited on the long sidewalls.
  • the etching rate of the short side wall of the first contact hole is reduced, so that any side of the second contact hole is The etching rate of the sides remains consistent, effectively reducing the problem of inconsistent etching lengths of the long and short side walls of the contact hole, ensuring the quality of the formed second contact hole, preventing bridging defects, thereby improving the quality of the semiconductor structure performance and yield.
  • this embodiment is a further explanation of step S100 above.
  • step S100 the following method may be used to provide the semiconductor substrate 100 with the first contact hole 11:
  • the semiconductor substrate 100 includes a substrate body 101 and a support structure layer 20 disposed on the substrate body 101 .
  • the substrate body 101 is used to support other components provided thereon.
  • the substrate body 101 may be electrically conductive, such as the base of a semiconductor structure or any metal layer in a semiconductor structure.
  • the base may be made of a semiconductor material, and the semiconductor material may be one or more of silicon, germanium, silicon germanium compounds, and silicon carbon compounds.
  • the substrate can be made of silicon material, and the use of silicon material as the base is to facilitate those skilled in the art to understand the subsequent formation method, and does not constitute a limitation. In the actual application process, a suitable substrate can be selected according to needs. s material.
  • the material of the substrate body 101 includes at least one of tungsten, copper, aluminum and polysilicon, wherein the number of metal layers may be one layer or multiple layers arranged in a stack.
  • the materials in the substrate body provided by the present disclosure may include but are not limited to the above-mentioned materials.
  • the available materials for the semiconductor substrate are not listed here, and those skilled in the art can make selections based on actual conditions.
  • the support structure layer 20 provided on the substrate body 101 can be used to form contact holes in the subsequent manufacturing process (in this embodiment, the contact holes include first contact holes and second contact holes). After the contact holes are formed, the support surrounding the contact holes The structural layer 20 may be used to subsequently form other semiconductor structures between adjacent contact holes. Wherein, when the substrate body 101 is a base, semiconductor structures such as bit line structures can be formed in the support structure layer 20; and when the substrate body 101 is a metal layer, a metal line layer, etc. can be formed in the support structure layer 20.
  • a stacked dielectric layer 21 , an isolation layer 22 and a hardened layer may be formed on the substrate body 101 through an atomic layer deposition process, a chemical vapor deposition process or a physical vapor deposition process.
  • the mask layer 23 and the dielectric layer 21 are in contact with the substrate body 101, and the isolation layer 22 and the hard mask layer 23 are sequentially disposed on the dielectric layer 21.
  • the thickness of the isolation layer 22 and the thickness of the dielectric layer 21 may be the same or different. In one example, the thickness of the isolation layer 22 is greater than the thickness of the dielectric layer 21 .
  • the material of the dielectric layer 21 may include but is not limited to silicon nitride, silicon oxynitride, etc.
  • the material of the isolation layer 22 may include but is not limited to oxide or nitride, such as silicon dioxide, to ensure that the support structure layer 20 has a better isolation function.
  • the material of the hard mask layer 23 may include but is not limited to carbon, silicon oxide, titanium nitride, silicon nitride, etc., to improve the quality of the subsequent formation of the first contact hole 11 and the second contact hole 12 .
  • the dielectric layer 21 and the isolation layer 22 can provide support for the subsequently formed contact holes to facilitate the formation of other semiconductor structures, and the hard mask layer 23 can be removed in subsequent semiconductor structure processes.
  • the first contact hole 11 is formed in the support structure layer 20 , and there is a preset height between the bottom end of the first contact hole 11 and the substrate body 101 .
  • the preset height is used for subsequent formation of the second contact hole 12, and its specific height can be flexibly selected according to the thickness of the contact structure to be formed subsequently.
  • the preset height of the second contact hole 12 is the same as or different from the height of the first contact hole 11 .
  • the preset height of the second contact hole 12 is greater than the height of the first contact hole 11 , or the second contact hole 12
  • the preset height is less than or equal to the height of the first contact hole 11
  • the first contact hole 11 can be formed in the support structure layer 20 through an etching process, and the etching end point of the first contact hole 11 can be located in the isolation layer 22 middle. It should be noted that along the first direction The process difficulty of forming the contact via hole 10 is reduced.
  • the support structure layer can support the formation process of the first contact hole and the subsequent formation of the second contact hole, to ensure the formation size of the first contact hole and the second contact hole, and improve the subsequent formation of the contact structure. Form quality.
  • the first contact hole 11 formed on the support structure layer 20 includes a long side wall 111 and a short side wall 112 in a preset cross-sectional pattern.
  • any cross section of the first contact hole 11 in its depth direction can be understood as a preset cross section, that is to say, the preset cross section It may be any cross-section of the first contact hole 11 within a predetermined height range in the isolation layer 22 in the opposite direction along the first direction X.
  • the cross-sectional shape of the first contact hole 11 formed by the etching process includes an ellipse.
  • the side walls on both sides of the long axis of the ellipse are defined as the long side walls 111
  • the side walls on both sides of the short axis of the ellipse are defined as the short sides.
  • the first contact hole 11 is formed through an etching process, and during the etching process, particulate impurities P such as oxides will remain on the bottom surface and side walls of the first contact hole 11 , the particulate impurities P will reduce the purity of the subsequently formed sacrificial layer 30 , thereby reducing the etching quality of the subsequent sacrificial layer 30 . Therefore, in some embodiments, the method for manufacturing the semiconductor structure further includes the following steps:
  • a first pre-cleaning process is performed on the first contact hole 11 .
  • the first pre-cleaning process can be carried out by bombarding the bottom end and side wall of the first contact hole 11 with argon ions; or, the first pre-cleaning process can be carried out by using a gas purging method, such as using nitrogen or argon to purge the first contact hole 11 , of course, the embodiment of the gas purging method is not limited to this, and the gas for the first pre-cleaning process can also be other inert gases.
  • the first pre-cleaning process is used to remove particulate impurities such as oxides in the first contact hole, reducing the remaining particulate impurities, preventing the remaining particulate impurities from affecting the resistance of the subsequent sacrificial layer, and improving the cleaning of the first contact hole. degree, as well as the subsequent formation purity and etching quality of the sacrificial layer, thereby improving the performance and yield of the semiconductor structure.
  • this embodiment is a further explanation of step S200 above.
  • a sacrificial layer 30 is formed on the long sidewall 111 .
  • the formation process of the sacrificial layer 30 may adopt the following method:
  • an initial sacrificial layer 31 is formed in the first contact hole 11 using an atomic layer deposition process, a chemical vapor deposition process or a physical vapor deposition process.
  • the initial sacrificial layer 31 covers the long side walls 111 and the short side walls 112 .
  • initial sacrificial layer 31 is formed using an atomic layer deposition process.
  • the atomic layer deposition process has the characteristics of slow deposition rate, high density of the deposited film layer and good step coverage.
  • the initial sacrificial layer 31 formed by the atomic layer deposition process can be uniformly deposited on the long side walls 111 and short side walls 112 of the first contact hole 11 under the condition of thin thickness, so as to avoid occupying a large space and have This facilitates the subsequent filling or formation of other structures, or facilitates the subsequent uniform removal of part of the initial sacrificial layer 31 using an etching process, thereby ensuring and improving the performance and yield of the semiconductor structure.
  • the material of the sacrificial layer 30 may include, but is not limited to, silicon nitride, silicon oxynitride, etc.
  • the initial sacrificial layer 31 on the short sidewalls 112 may be removed through a wet etching process. It should be noted that wet etching has anisotropy and a high etching selectivity. Therefore, when etching each sidewall of the first contact hole 11, the short side of the first contact hole 11 will be given priority.
  • the initial sacrificial layer 31 on the sidewall 112 is etched, and after the initial sacrificial layer 31 on the short sidewall 112 is etched, the initial sacrificial layer 31 on the long sidewall 111 is etched.
  • the wet etching process can be ended, thereby ensuring that the initial sacrificial layer on the short side wall 112 is completely removed. 31.
  • the initial sacrificial layer 31 on the long side wall 111 so that when the second contact hole 12 is subsequently formed, the initial sacrificial layer 31 on the long side wall 111 has a certain protective effect, thereby making the first contact hole 11
  • the etching rate of the support structure layer 20 under each side remains consistent, effectively reducing the problem of inconsistent etching lengths of the long sidewalls and short sidewalls of the contact holes, ensuring the etching quality of the second contact hole 12, and preventing Creating bridging defects, thereby improving the performance and yield of semiconductor structures.
  • the dielectric layer 21 is made of the same material as the sacrificial layer 30 .
  • the dielectric layer 21 and the sacrificial layer 30 are both made of silicon nitride, thereby simplifying the process. steps to reduce process costs.
  • this embodiment is a further explanation of step S300 above.
  • the bottom end of the first contact hole 11 is etched through an etching process to form a second contact hole 12 below the first contact hole 11 .
  • the second contact hole 12 is connected with the first contact hole 11 , and the etching end point of the second contact hole 12 is located on the top surface of the substrate body 101 .
  • the cross-sectional area of the second contact hole 12 is smaller than the cross-sectional area of the first contact hole 11 .
  • the first contact hole 11 and the second contact hole 12 form a contact through hole 10, which is used to subsequently form other semiconductor structures such as contact structures.
  • the contact structure may be a capacitive contact structure.
  • the capacitive contact structure is used to connect the capacitive structure and the substrate body 101 and realize the connection between the capacitive structure and the substrate body 101. Electrical connection; or the capacitive contact structure is used to electrically connect the capacitive structure and any metal layer in the substrate body 101 .
  • Performance and yield of semiconductor structures are used to yield of semiconductor structures.
  • a second pre-cleaning process is performed on the second contact hole 12 to remove the residual particulate impurities P etc. during the etching process of the second contact hole 12 , thereby reducing the residual particulate impurities and ensuring the second contact hole 12 to improve the purity of subsequently formed contact structures or other semiconductor structural components.
  • the second pre-cleaning process of the second contact hole 12 includes the following steps:
  • the hard mask layer 23 in the support structure layer 20 is removed using a dry glue removal process.
  • a dry glue removal process plasma is generated in the vacuum reaction system by degumming gas such as oxygen.
  • degumming gas such as oxygen.
  • the dry glue removal process is simple to operate, has high glue removal efficiency, and the surface of the isolation layer 22 after the glue is removed is clean, smooth and scratch-free, and is low cost and environmentally friendly.
  • the remaining sacrificial layer 30 located on the long sidewall 111 of the first contact hole 11 is removed through an etching process, such as a wet etching process.
  • the first contact hole 11 and the second contact hole 12 form the contact via hole 10 .
  • the side walls and bottoms of the first contact hole 11 and the second contact hole 12 are cleaned.
  • the cleaning process can be carried out by bombarding the side walls and bottom of the second contact hole 12 with argon ions, and bombarding the side walls of the first contact hole 11; or, the cleaning process can be carried out by gas purging, such as using nitrogen or argon gas to clean the first contact hole 11.
  • the first contact hole 11 and the second contact hole 12 are purged, and the purge gas can also be other inert gases.
  • a dry degumming process is used to remove the hard mask layer
  • a wet etching process is used to remove the remaining sacrificial layer
  • the contact via holes are cleaned to effectively remove particulate impurities in the contact via holes. Reduce the impact of particle impurities and improve the purity of subsequent contact structures (such as capacitive contacts) or other semiconductor structural components, thereby improving the performance and yield of semiconductor structures.
  • an exemplary embodiment of the present disclosure provides a semiconductor structure.
  • the semiconductor structure includes a semiconductor substrate 100 .
  • the semiconductor substrate 100 includes a substrate body 101 and a support layer 20a provided on the substrate body 101, wherein the support layer 20a has a first contact hole 11 therein.
  • the first contact hole 11 includes a long side wall 111 and a short side wall 112 in a preset cross-section.
  • any cross section of the first contact hole 11 in its depth direction can be understood as a preset cross section, that is to say, the preset cross section It may be any cross-section of the first contact hole 11 within a predetermined height range in the support layer 20a in the opposite direction along the first direction X.
  • a second contact hole 12 is provided below the first contact hole 11 .
  • One end of the second contact hole 12 is connected to the first contact hole 11 , and the other end of the second contact hole 12 exposes the top surface of the substrate body 101 .
  • the cross-sectional area of the second contact hole 12 is smaller than the cross-sectional area of the partial region of the first contact hole 11 and the first contact hole 11 and the second contact hole 11 . The area above where the two contact holes 12 meet.
  • the first contact hole and the second contact hole form a contact through hole, wherein, except for the contact position between the first contact hole and the second contact hole, the cross-sectional area of the first contact hole is larger than that of the second contact hole.
  • the cross-sectional area of the hole, the contact through hole is used to subsequently form other semiconductor structures such as contact structures, etc., so that the subsequently formed contact structure has a large top structure and a small bottom structure, so that the subsequent contact structure and capacitance structure can be smoothly formed. Alignment, improves the accuracy in subsequent alignment processes, and ensures the performance and yield of semiconductor structures.
  • the longitudinal cross-sectional shape of the first contact hole 11 includes an inverted trapezoid. That is, along the extension direction of the first direction This reduces the alignment difficulty in the subsequent self-alignment process of the semiconductor structure, improves the performance and yield of the semiconductor structure, and increases the productivity of the semiconductor structure.
  • the longitudinal cross-sectional shape of the second contact hole 12 includes a square shape to ensure the formation quality of the second contact hole 12 , thereby improving the subsequent location in the second contact hole 12 The formation quality of the contact structure.
  • the minimum diameter of the second contact hole 12 is the same as the minimum diameter of the first contact hole 11 , which reduces the difficulty of the manufacturing process of the contact through hole 10 and improves the efficiency of the contact through hole 10 . quality of formation.
  • the substrate body 101 includes a semiconductor substrate.
  • the semiconductor substrate may be made of a semiconductor material, and the semiconductor material may be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds.
  • the substrate can be made of silicon material, and the use of silicon material as the base is to facilitate those skilled in the art to understand the subsequent formation method, and does not constitute a limitation. In the actual application process, a suitable substrate can be selected according to needs. s material.
  • a semiconductor structure such as a bit line structure may be formed in the support layer 20a.
  • the material of the substrate body 101 includes at least one of tungsten, copper, aluminum and polysilicon, where the number of metal layers can be one or multiple layers arranged in a stack.
  • a metal line layer or the like can be formed in the support layer 20a.
  • the materials in the substrate body provided by the present disclosure may include but are not limited to the above-mentioned materials.
  • the available materials for the semiconductor substrate are not listed here, and those skilled in the art can select them according to the actual situation.
  • the support layer 20 a includes a stacked dielectric layer 21 and an isolation layer 22 , and the dielectric layer 21 is provided on the substrate body 101 .
  • the thickness of the isolation layer 22 is between one-third and two-thirds, thereby effectively ensuring the conductivity of the subsequent contact structure while reducing the difficulty of the subsequent self-alignment process of the semiconductor structure.
  • the manufacturing method of a semiconductor structure and the semiconductor structure provided by embodiments of the present disclosure by forming a sacrificial layer on the long sidewall of the first contact hole, the long sidewall and short sidewall in the formation process of the second contact hole are effectively reduced.
  • the problem of inconsistent wall etching length ensures the quality of the formed second contact hole, prevents bridging defects, and improves the performance and yield of the conductor structure.

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Abstract

本公开公布了一种半导体结构的制作方法及半导体结构，涉及半导体技术领域。该半导体结构的制作方法包括：提供具有第一接触孔的半导体基板，第一接触孔在预设截面的图形包括长边侧壁和短边侧壁；于长边侧壁上形成牺牲层；对第一接触孔进行处理，以在第一接触孔下方形成第二接触孔，第二接触孔与第一接触孔连通，以平行于半导体基板的顶面的平面为横截面，第二接触孔的横截面面积小于第一接触孔的部分区域的横截面面积。

Description

半导体结构的制作方法及半导体结构
本公开基于申请号为202210477973.9，申请日为2022年05月05日，申请名称为“半导体结构的制作方法及半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及一种半导体结构的制作方法及半导体结构。
背景技术
随着半导体结构的先进制作工艺的推进，半导体结构中的器件(比如电容结构)的高度不断增加，使得接触结构的长度越来越长。其中，接触结构在形成之前，需要在半导体结构中形成接触孔，但此类接触孔在刻蚀过程中，如果接触孔的长边侧壁和短边侧壁的刻蚀速率不同，后续会产生桥接缺陷的问题，降低了半导体结构的性能和良率。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种半导体结构的制作方法及半导体结构。
本公开的第一方面提供了一种半导体结构的制作方法，包括：
提供具有第一接触孔的半导体基板，所述第一接触孔在预设截面的图形包括长边侧壁和短边侧壁；
于所述长边侧壁上形成牺牲层；
对所述第一接触孔进行处理，以在所述第一接触孔下方形成第二接触孔，所述第二接触孔与所述第一接触孔连通，其中，以平行于所述半导体基板的顶面的平面为横截面，所述第二接触孔的横截面面积小于所述第一接触孔的部分区域的横截面面积，所述部分区域为所述第一接触孔与所述第二接触孔相接位置之上的区域。
根据本公开的一些实施例，于所述长边侧壁上形成牺牲层，包括：
于所述第一接触孔内形成初始牺牲层，所述初始牺牲层覆盖所述长边侧壁和所述短边侧壁；
去除位于所述短边侧壁上的所述初始牺牲层，被保留下来的所述初始牺牲层形成牺牲层。
根据本公开的一些实施例，所述半导体结构的制作方法还包括：
对所述第一接触孔进行第一预清洁处理。
根据本公开的一些实施例，去除位于所述短边侧壁上的所述初始牺牲层，包括：
利用湿法刻蚀工艺去除位于所述短边侧壁上的所述初始牺牲层。
根据本公开的一些实施例，所述对所述第一接触孔进行处理，包括：
通过刻蚀工艺对所述第一接触孔的底端进行刻蚀处理。
根据本公开的一些实施例，提供具有第一接触孔的半导体基板，所述第一接触孔在预设截面的图形包括长边侧壁和短边侧壁，包括：
提供半导体基板，所述半导体基板包括基板本体以及设在所述基板本体上的支撑结构层；
于所述支撑结构层内形成所述第一接触孔，所述第一接触孔的底端与所述半导 体基板的顶面之间具有预设高度。
根据本公开的一些实施例，提供半导体基板，所述半导体基板包括基板本体以及设在所述基板本体上的支撑结构层，包括：
于所述基板本体上形成层叠设置的介质层、隔离层和硬掩膜层。
根据本公开的一些实施例，所述介质层的形成材料与所述牺牲层的形成材料相同。
根据本公开的一些实施例，所述半导体结构的制作方法还包括：
对所述第二接触孔进行第二预清洁处理。
根据本公开的一些实施例，对所述第二接触孔进行第二预清洁处理，包括：
去除所述硬掩膜层；
去除剩余所述牺牲层；
对所述第一接触孔的侧壁、所述第二接触孔的侧壁和底部进行清洁处理，其中，所述第一接触孔和所述第二接触孔形成接触通孔。
本公开的第二方面提供了一种半导体结构，包括：
半导体基板，所述半导体基板包括基板本体以及设在所述基板本体上的支撑层，其中，所述支撑层内具有第一接触孔，所述第一接触孔在预设截面的图形包括长边侧壁和短边侧壁；
第二接触孔，位于所述第一接触孔下方，所述第二接触孔的一端与所述第一接触孔连通，所述第二接触孔的另一端暴露所述基板本体的顶面，其中，以平行于所述基板本体的顶面的平面为横截面，所述第二接触孔的横截面面积小于所述第一接触孔的部分区域的横截面面积，所述部分区域为所述第一接触孔与所述第二接触孔相接位置之上的区域。
根据本公开的一些实施例，所述第一接触孔的纵截面形状包括倒梯形；
所述第二接触孔的纵截面形状包括方形。
根据本公开的一些实施例，所述第二接触孔的孔径与所述第一接触孔的孔径的最小值相同。
根据本公开的一些实施例，所述基板本体包括半导体基底；或者，
所述基板本体包括金属层。
根据本公开的一些实施例，所述支撑层包括层叠设置的介质层和隔离层，所述介质层设在所述基板本体上。
本公开实施例所提供的半导体结构的制作方法和半导体结构中，在形成第一接触孔之后，在第一接触孔的长边侧壁形成牺牲层，以在后续形成第二接触孔的过程中，使得对第二接触孔的任意侧边的刻蚀速率保持一致性，有效减少接触孔长边侧壁和短边侧壁刻蚀长度不一致的问题，保证形成的第二接触孔的质量，防止产生桥接缺陷，从而提高了半导体结构的性能和良率。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是根据一示例性实施例示出的半导体结构的制作方法的流程图。
图2是根据一示例性实施例示出的半导体结构的制作方法中形成支撑结构层的示意图。
图3是根据一示例性实施例示出的半导体结构的制作方法中残留有颗粒杂质的示意图。
图4是根据一示例性实施例示出的半导体结构的制作方法中形成第一通孔的示意图。
图5是根据一示例性实施例示出的半导体结构的制作方法中形成初始牺牲层的示意图。
图6是根据一示例性实施例示出的半导体结构的制作方法中于长边侧壁上形成牺牲层的示意图。
图7是根据一示例性实施例示出的半导体结构的制作方法中形成第二通孔的示意图。
图8是根据一示例性实施例示出的半导体结构的制作方法中形成接触通孔和支撑层的示意图。
附图标记：
10、接触通孔；11、第一接触孔；
12、第二接触孔；20、支撑结构层；
21、介质层；22、隔离层；
23、硬掩膜层；30、牺牲层；
31、初始牺牲层；100、半导体基板；
101、基板本体；111、长边侧壁；
112、短边侧壁；20a、支撑层；
P、颗粒杂质。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
随着半导体结构的先进制作工艺的推进，半导体结构中的器件(比如电容结构)的高度不断增加，使得接触结构的长度越来越长。其中，接触结构在形成之前，需要在半导体结构中形成接触孔，但此类接触孔在刻蚀过程中，产生的杂质易于在接触孔的短边侧壁堆积，导致对接触孔的短边侧壁的刻蚀速率小于对接触孔的长边侧壁的刻蚀速率，使得所形成的接触孔的横截面形状趋近于椭圆形。而后在接触孔内形成接触结构的过程中，同一接触结构可能会与相邻的金属层或者有源区之间搭接，由于接触结构由金属导电材料制成，因此，会在相邻的金属层或有源区之间产生桥接缺陷的问题，降低了半导体结构的性能和良率。
为了解决上述技术问题之一，本公开示例性的实施例提供了一种半导体结构的制作方法。下面结合图1-图8对半导体结构的制作方法进行介绍。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(Dynamic Random Access Memory，简称DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
如图1所示，本公开一示例性的实施例提供的一种半导体结构的制作方法，包括如下的步骤：
步骤S100：提供具有第一接触孔的半导体基板，第一接触孔在预设截面的图形包括长边侧壁和短边侧壁。
步骤S200：于长边侧壁上形成牺牲层。
步骤S300：对第一接触孔进行处理，以在第一接触孔下方形成第二接触孔，第二接触孔与第一接触孔连通，其中，以平行于半导体基板的顶面的平面为横截面，第二接触孔的横截面面积小于第一接触孔的部分区域的横截面面积，部分区域为第一接触孔与第二接触孔相接位置之上的区域。
如图4和图8所示，其中，以平行于半导体基板100的顶面的平面为横截面，第一接触孔11在其深度方向上的任意横截面均可以理解为预设截面，也就是说，预设截面可以是第一接触孔11在沿第一方向X的相反方向，介于半导体基板100中预定高度范围内的任意横截面。本实施例中的描述以图中示出的方位为例，第一方向X为自半导体基板100的顶面至半导体基板100的底面的延伸方向。
参照图6并结合图4所示，其中，通过刻蚀工艺所形成的第一接触孔11的横截面形状包括椭圆，定义椭圆长轴两侧的侧壁为长边侧壁111，以椭圆短轴两侧的侧壁为短边侧壁112。
当第一接触孔11的长边侧壁111上无牺牲层30时，在后续刻蚀第二接触孔12(参考图7)的过程中，长边侧壁111的刻蚀速率会小于短边侧壁112的刻蚀速率，从而使得第一接触孔11的横截面形状的椭圆度增大，进而导致后续产生桥接缺陷，因此，为了保证后续第二接触孔12的各个侧壁的刻蚀速率保持一致，从而在长边侧壁111上形成牺牲层30。
待第二接触孔12形成之后，去除长边侧壁111上的牺牲层30。
本实施例中，将接触通孔(包括第一接触孔和第二接触孔)的形成通过两步刻蚀工艺完成，在第一接触孔形成之后，通过在长边侧壁上沉积牺牲层，以调整刻蚀窗口，通过调控刻蚀选择比，从而在后续形成第二接触孔的过程中，降低对第一接触孔的短边侧壁的刻蚀速率，使得对第二接触孔的任意侧边的刻蚀速率保持一致性，有效减少接触孔长边侧壁和短边侧壁刻蚀长度不一致的问题，保证形成的第二接触孔的质量，防止产生桥接缺陷，从而提高了半导体结构的性能和良率。
根据一个示例性实施例，本实施例是对上文中步骤S100的进一步说明。
如图2所示，在步骤S100中，提供具有第一接触孔11的半导体基板100可以采用以下方法：
提供半导体基板100，该半导体基板100包括基板本体101以及设在基板本体101上的支撑结构层20。
其中，基板本体101用于支撑设在其上的其他部件。基板本体101可以具有导电性，比如半导体结构的基底或者半导体结构中的任意金属层。其中，当基板本体101为基底时，基底可以由半导体材料制成，半导体材料可以为硅、锗、硅锗化合物以及硅碳化合物中的一种或多种。在一些实施例中，基底可以采用硅材料，且采用硅材料作为基底是为了方便本领域技术人员对后续形成方法的理解，并不构成限定，在实际应用过程中，可以根据需求选择合适的基底的材料。
当基板本体101为金属层时，基板本体101的材料包括钨、铜、铝和多晶硅中的至少一种，其中，金属层的层数可以为一层或层叠设置的多层。
需要说明的是，本公开提供的基板本体中的材料可以包括但不限于上述材料，半导 体基板可取材料在此不一一列举，本领域技术人员可根据实际情况进行选取。
基板本体101上设置的支撑结构层20可用于形成后续制作过程中的接触孔(本实施例中，接触孔包括第一接触孔和第二接触孔)，形成接触孔后，环绕接触孔的支撑结构层20可以用于后续在相邻的接触孔之间形成其他半导体结构。其中，当基板本体101为基底时，可以在支撑结构层20中形成位线结构等半导体结构；而当基板本体101为金属层时，可以在支撑结构层20中形成金属线层等。
参照图2所示，在支撑结构层20形成的过程中，可以通过原子层沉积工艺、化学气相沉积工艺或物理气相沉积工艺在基板本体101上形成层叠设置的介质层21、隔离层22和硬掩膜层23，介质层21与基板本体101接触，隔离层22和硬掩膜层23依次设置在介质层21上。
其中，隔离层22的厚度与介质层21的厚度可以相同或者不同。在一个示例中，隔离层22的厚度大于介质层21的厚度。介质层21的材料可以包括但不限于氮化硅、氮氧化硅等。隔离层22的材料可以包括但不限于氧化物或氮化物，比如二氧化硅等，以保证支撑结构层20具有较佳的隔离功能。硬掩膜层23的材料可以包括但不限于碳、氧化硅、氮化钛或者氮化硅等，以提高后续形成第一接触孔11以及第二接触孔12的质量。介质层21和隔离层22可以为后续所形成的接触孔提供支撑，便于形成其他半导体结构，而硬掩膜层23可以在后续的半导体结构制程中去除。
最后，于支撑结构层20内形成第一接触孔11，第一接触孔11的底端与基板本体101之间具有预设高度。该预设高度用于后续形成第二接触孔12，其具体高度可以依据后续所要形成的接触结构的厚度进行灵活选择。其中，第二接触孔12的预设高度与第一接触孔11的高度相同或者不同，比如，第二接触孔12的预设高度大于第一接触孔11的高度，或者，第二接触孔12的预设高度小于或等于第一接触孔11的高度
其中，参照图3和图4所示，在一些实施例中，可以通过刻蚀工艺在支撑结构层20内形成第一接触孔11，且第一接触孔11的刻蚀终点可以位于隔离层22中。需要说明的是，沿第一方向X，第一接触孔11的深度介于隔离层22厚度的三分之一至三分之二之间，在保证后续形成的接触结构的导电性能的同时，降低形成接触通孔10的工艺难度。
本实施例中，支撑结构层可以对第一接触孔的形成以及后续第二接触孔的形成过程进行支撑，用于保证第一接触孔和第二接触孔的形成尺寸，提高后续形成接触结构的形成质量。
参照图6所示，在支撑结构层20上形成的第一接触孔11在预设截面的图形包括长边侧壁111和短边侧壁112。在本实施例中，以平行于半导体基板100的顶面的平面为横截面，第一接触孔11在其深度方向上的任意横截面均可以理解为预设截面，也就是说，预设截面可以是第一接触孔11在沿第一方向X的相反方向，介于隔离层22中预定高度范围内的任意横截面。
其中，通过刻蚀工艺所形成的第一接触孔11的横截面形状包括椭圆，定义椭圆长轴两侧的侧壁为长边侧壁111，以椭圆短轴两侧的侧壁为短边侧壁112。
如图3和图6所示，第一接触孔11是通过刻蚀工艺形成的，而在刻蚀工艺中，会在第一接触孔11的底面和侧壁上残存有氧化物等颗粒杂质P，该颗粒杂质P会降低后续所形成的牺牲层30的纯度，从而降低后续牺牲层30的刻蚀质量。因此，在一些实施例中，该半导体结构的制作方法还包括以下步骤：
对第一接触孔11进行第一预清洁处理。其中，第一预清洁处理可以通过氩离子轰击第一接触孔11的底端和侧壁；或者，利用气体吹扫方式进行处理，比如利用氮气或氩气等对第一接触孔11进行吹扫，当然，该气体吹扫方式的实施例并不以此为限，第一预清 洁处理的气体也可以是其他惰性气体。
在本实施例中，通过第一预清洁处理将第一接触孔内的氧化物等颗粒杂质去除，减少颗粒杂质残留，避免残留颗粒杂质影响后续牺牲层的阻值，提高第一接触孔的清洁度、以及后续牺牲层的形成纯度和刻蚀质量，进而提高半导体结构的性能和良率。
根据一个示例性实施例，本实施例是对上文中步骤S200的进一步说明。
如图5和图6所示，于长边侧壁111上形成牺牲层30。其中，在一些实施例中，牺牲层30的形成过程可以采用以下方法：
待对第一接触孔11进行第一预清洁处理之后，参照图5所示，利用原子层沉积工艺、化学气相沉积工艺或物理气相沉积工艺在第一接触孔11内形成初始牺牲层31，该初始牺牲层31覆盖长边侧壁111和短边侧壁112。
在一个示例中，初始牺牲层31利用原子层沉积工艺形成。其中，原子层沉积工艺具有沉积速率慢，沉积形成的膜层致密性高以及阶梯覆盖率好的特点。利用原子层沉积工艺形成的初始牺牲层31能够在厚度较薄的条件下均匀的沉积在第一接触孔11的长边侧壁111和短边侧壁112上，避免占据较大的空间，有利于后续实现其他结构的填充或形成，或者便于后续利用刻蚀工艺等均匀的去除部分初始牺牲层31，从而保证并提高半导体结构的性能和良率。
待初始牺牲层31形成之后，利用刻蚀工艺去除位于短边侧壁112上的初始牺牲层31，被保留下来的初始牺牲层31形成牺牲层30。牺牲层30的材料可以包括但不限于氮化硅、氮氧化硅等。
在一个示例中，可以通过湿法刻蚀工艺去除短边侧壁112上的初始牺牲层31。需要说明的是，湿法刻蚀具有各向异性和较高的刻蚀选择比，因此在对第一接触孔11的各个侧壁进行刻蚀时，会优先对第一接触孔11的短边侧壁112上的初始牺牲层31进行刻蚀，而当短边侧壁112上的初始牺牲层31刻蚀完后，才会对长边侧壁111的初始牺牲层31进行刻蚀，因此，在具体的刻蚀过程中，只要将短边侧壁112上的初始牺牲层31刻蚀完成之后，即可结束该湿法刻蚀工艺，从而保证完全去除短边侧壁112上的初始牺牲层31，保留长边侧壁111上的初始牺牲层31，以便于后续形成第二接触孔12时，长边侧壁111上的初始牺牲层31具有一定的保护作用，从而使得对第一接触孔11各个边侧下方的支撑结构层20的刻蚀速率保持一致性，有效减少接触孔长边侧壁和短边侧壁刻蚀长度不一致的问题，保证第二接触孔12的刻蚀质量，防止产生桥接缺陷，进而提高半导体结构的性能和良率。
如图2至图6所示，在一些实施例中，介质层21的形成材料与牺牲层30的形成材料相同，比如介质层21和牺牲层30的材料均为氮化硅形成，从而简化工艺步骤，降低工艺制程成本。
根据一个示例性实施例，本实施例是对上文中步骤S300的进一步说明。
如图7所示，在一些实施例中，通过刻蚀工艺对第一接触孔11的底端进行刻蚀处理，以在第一接触孔11的下方形成第二接触孔12。第二接触孔12与第一接触孔11连通，并且第二接触孔12的刻蚀终点位于基板本体101的顶面。以平行于半导体基板100的顶面的平面为横截面，第二接触孔12的横截面面积小于第一接触孔11的横截面面积。
需要说明的是，沿第一方向X，除第一接触孔11与第二接触孔12的相接位置之外，第二接触孔12任意位置处的横截面面积均小于第一接触孔11任意位置处的横截面面积的最小值。在本实施例中，第一接触孔11和第二接触孔12形成接触通孔10，该接触通孔10用于后续形成其他半导体结构比如接触结构等。其中，当接触通孔10内形成的半导体结构为接触结构时，该接触结构可以是电容接触结构，电容接触结构用于连接电容结构 与基板本体101，并实现电容结构与基板本体101之间的电性连接；或者电容接触结构用于电连接电容结构和基板本体101中的任意金属层。沿第一方向X，该接触通孔所形成的接触结构呈上大下小结构，以便于后续所形成的接触结构与电容结构等进行良好的对准，提高后续对准制程中的精度，保证半导体结构的性能和良率。
待第二接触孔12形成之后，对第二接触孔12进行第二预清洁处理，去除第二接触孔12刻蚀过程中残留的颗粒杂质P等，减少颗粒杂质残留，保证第二接触孔12的清洁度，从而提高后续所形成的接触结构或其他半导体结构部件的纯度。
参照图6-8所示，在一些实施例中，第二接触孔12的第二预清洁处理过程包括以下步骤：
利用干法去胶工艺去除支撑结构层20中的硬掩膜层23。其中，在干法去胶工艺中，通过去胶气体比如氧气在真空反应系统中生成等离子体，通过调节真空反应系统的功率、去胶气体的流量等工艺参数，得到不同的去胶速率，从而快速的去除硬掩膜层23。该干法去胶工艺的操作简单，去胶效率高，去胶之后的隔离层22的表面干净光洁、无划痕，成本低且环保。
在去除硬掩膜层23之后，通过刻蚀工艺，比如湿法刻蚀工艺去除位于第一接触孔11的长边侧壁111上剩余的牺牲层30。
待牺牲层30去除之后，第一接触孔11和第二接触孔12形成接触通孔10。对第一接触孔11和第二接触孔12的侧壁和底部进行清洁处理。其中，清洁处理可以通过氩离子轰击第二接触孔12的侧壁和底部、以及轰击第一接触孔11的侧壁；或者，利用气体吹扫的方式进行处理，比如利用氮气或氩气对第一接触孔11和第二接触孔12进行吹扫，吹扫气体也可以是其他惰性气体。
在本实施例中，利用干法去胶工艺去除硬掩膜层，利用湿法刻蚀工艺去除剩余的牺牲层，而后再对接触通孔进行清洁处理，有效去除接触通孔内的颗粒杂质，减小颗粒杂质的影响，提高后续形成接触结构(比如电容接触)或其他半导体结构部件的纯度，从而提高半导体结构的性能和良率。
如图8所示，本公开一示例性的实施例提供了一种半导体结构。该半导体结构包括半导体基板100。
其中，半导体基板100包括基板本体101以及设在基板本体101上的支撑层20a，其中，支撑层20a内具有第一接触孔11。结合图6，第一接触孔11在预设截面的图形包括长边侧壁111和短边侧壁112。在本实施例中，以平行于基板本体101的顶面的平面为横截面，第一接触孔11在其深度方向上的任意横截面均可以理解为预设截面，也就是说，预设截面可以是第一接触孔11在沿第一方向X的相反方向，介于支撑层20a中预定高度范围内的任意横截面。
在第一接触孔11的下方设置有第二接触孔12。第二接触孔12的一端与第一接触孔11连通，第二接触孔12的另一端暴露基板本体101的顶面。其中，以平行于半导体基板100的顶面的平面为横截面，第二接触孔12的横截面面积小于第一接触孔11的部分区域的横截面面积，部分区域为第一接触孔11与第二接触孔12相接位置之上的区域。
在本实施例中，第一接触孔和第二接触孔形成接触通孔，其中，除了第一接触孔与第二接触孔的相接位置外，第一接触孔的横截面面积大于第二接触孔的横截面面积，该接触通孔用于后续形成其他半导体结构比如接触结构等，使得后续所形成的接触结构呈上大下小结构，以便于后续所形成的接触结构与电容结构等进行良好的对准，提高后续对准制程中的精度，保证半导体结构的性能和良率。
如图8所示，在一些实施例中，以平行于半导体基板100的前侧面的平面为纵截面， 第一接触孔11的纵截面形状包括倒梯形。即，沿第一方向X的延伸方向，第一接触孔11的孔径为渐缩式结构，以便于后续在第一接触孔11内所形成的部分接触结构的顶面大于该接触结构的底面，从而降低后续半导体结构自对准制程工艺中的对准难度，提高半导体结构的性能和良率，以及提高半导体结构的产能。
同样，以平行于半导体基板100的前侧面的平面为纵截面，第二接触孔12的纵截面形状包括方形，以保证第二接触孔12的形成质量，从而提高后续位于第二接触孔12中的接触结构的形成质量。
如图8所示，在一些实施例中，第二接触孔12的孔径与第一接触孔11的孔径的最小值相同，在降低接触通孔10的制作工艺难度的同时，提高接触通孔10的形成质量。
如图8所示，在一些实施例中，基板本体101包括半导体基底。其中，半导体基底可以由半导体材料制成，半导体材料可以为硅、锗、硅锗化合物以及硅碳化合物中的一种或多种。在一些实施例中，基底可以采用硅材料，且采用硅材料作为基底是为了方便本领域技术人员对后续形成方法的理解，并不构成限定，在实际应用过程中，可以根据需求选择合适的基底的材料。当基板本体101为半导体基底时，可以在支撑层20a中形成位线结构等半导体结构。
基板本体101为金属层时，基板本体101的材料包括钨、铜、铝和多晶硅中的至少一种，其中，金属层的层数可以为一层或层叠设置的多层。当基板本体101为金属层时，可以在支撑层20a中形成金属线层等。
需要说明的是，本公开提供的基板本体中的材料可以包括但不限于上述材料，半导体基板可取材料在此不一一列举，本领域技术人员可根据实际情况进行选取。
如图8所示，在一些实施例中，支撑层20a包括层叠设置的介质层21和隔离层22，介质层21设置基板本体101上。其中，沿第一方向X的延伸方向，第一接触孔11的深度可以介于支撑层20a厚度的三分之一至三分之二之间，或者，第一接触孔11的深度可以介于隔离层22厚度的三分之一至三分之二之间，从而在降低后续半导体结构自对准制程工艺难度的同时，有效保证后续所形成的接触结构的导电性。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的 细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的半导体结构的制作方法及半导体结构中，通过在第一接触孔的长边侧壁上形成牺牲层，有效减少第二接触孔形成过程中长边侧壁和短边侧壁刻蚀长度不一致的问题，保证形成的第二接触孔的质量，防止产生桥接缺陷，提高了导体结构的性能和良率。

Claims (15)

  1. 一种半导体结构的制作方法，包括：
    提供具有第一接触孔的半导体基板，所述第一接触孔在预设截面的图形包括长边侧壁和短边侧壁；
    于所述长边侧壁上形成牺牲层；
    对所述第一接触孔进行处理，以在所述第一接触孔下方形成第二接触孔，所述第二接触孔与所述第一接触孔连通，其中，以平行于所述半导体基板的顶面的平面为横截面，所述第二接触孔的横截面面积小于所述第一接触孔的部分区域的横截面面积，所述部分区域为所述第一接触孔与所述第二接触孔相接位置之上的区域。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，于所述长边侧壁上形成牺牲层，包括：
    于所述第一接触孔内形成初始牺牲层，所述初始牺牲层覆盖所述长边侧壁和所述短边侧壁；
    去除位于所述短边侧壁上的所述初始牺牲层，被保留下来的所述初始牺牲层形成牺牲层。
  3. 根据权利要求2所述的半导体结构的制作方法，其中，所述半导体结构的制作方法还包括：
    对所述第一接触孔进行第一预清洁处理。
  4. 根据权利要求2所述的半导体结构的制作方法，其中，去除位于所述短边侧壁上的所述初始牺牲层，包括：
    利用湿法刻蚀工艺去除位于所述短边侧壁上的所述初始牺牲层。
  5. 根据权利要求1所述的半导体结构的制作方法，其中，对所述第一接触孔进行处理，包括：
    通过刻蚀工艺对所述第一接触孔的底端进行刻蚀处理。
  6. 根据权利要求1-5任一项所述的半导体结构的制作方法，其中，提供具有第一接触孔的半导体基板，所述第一接触孔在预设截面的图形包括长边侧壁和短边侧壁，包括：
    提供半导体基板，所述半导体基板包括基板本体以及设在所述基板本体上的支撑结构层；
    于所述支撑结构层内形成所述第一接触孔，所述第一接触孔的底端与所述半导体基板的顶面之间具有预设高度。
  7. 根据权利要求6所述的半导体结构的制作方法，其中，提供半导体基板，所述半导体基板包括基板本体以及设在所述基板本体上的支撑结构层，包括：
    于所述基板本体上形成层叠设置的介质层、隔离层和硬掩膜层。
  8. 根据权利要求7所述的半导体结构的制作方法，其中，所述介质层的形成材料与所述牺牲层的形成材料相同。
  9. 根据权利要求7所述的半导体结构的制作方法，其中，所述半导体结构的制作方法还包括：
    对所述第二接触孔进行第二预清洁处理。
  10. 根据权利要求9所述的半导体结构的制作方法，其中，对所述第二接触孔进行第二预清洁处理，包括：
    去除所述硬掩膜层；
    去除剩余所述牺牲层；
    对所述第一接触孔的侧壁、所述第二接触孔的侧壁和底部进行清洁处理，其中，所述第一接触孔和所述第二接触孔形成接触通孔。
  11. 一种半导体结构，包括：
    半导体基板，所述半导体基板包括基板本体以及设在所述基板本体上的支撑层，其中，所述支撑层内具有第一接触孔，所述第一接触孔在预设截面的图形包括长边侧壁和短边侧壁；
    第二接触孔，位于所述第一接触孔下方，所述第二接触孔的一端与所述第一接触孔连通，所述第二接触孔的另一端暴露所述基板本体的顶面，其中，以平行于所述基板本体的顶面的平面为横截面，所述第二接触孔的横截面面积小于所述第一接触孔的部分区域的横截面面积，所述部分区域为第一接触孔与所述第二接触孔相接位置之上的区域。
  12. 根据权利要求11所述的半导体结构，其中，所述第一接触孔的纵截面形状包括倒梯形；
    所述第二接触孔的纵截面形状包括方形。
  13. 根据权利要求12所述的半导体结构，其中，所述第二接触孔的孔径与所述第一接触孔的孔径的最小值相同。
  14. 根据权利要求11所述的半导体结构，其中，所述基板本体包括半导体基底；或者，
    所述基板本体包括金属层。
  15. 根据权利要求14所述的半导体结构，其中，所述支撑层包括层叠设置的介质层和隔离层，所述介质层设在所述基板本体上。
PCT/CN2022/094659 2022-05-05 2022-05-24 半导体结构的制作方法及半导体结构 Ceased WO2023212988A1 (zh)

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