WO2023208149A1 - 一种探测基板及平板探测器 - Google Patents

一种探测基板及平板探测器 Download PDF

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Publication number
WO2023208149A1
WO2023208149A1 PCT/CN2023/091353 CN2023091353W WO2023208149A1 WO 2023208149 A1 WO2023208149 A1 WO 2023208149A1 CN 2023091353 W CN2023091353 W CN 2023091353W WO 2023208149 A1 WO2023208149 A1 WO 2023208149A1
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WIPO (PCT)
Prior art keywords
layer
bias voltage
voltage line
area
via hole
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PCT/CN2023/091353
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English (en)
French (fr)
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WO2023208149A9 (zh
Inventor
李金钰
张冠
于海博
侯学成
庞凤春
Original Assignee
京东方科技集团股份有限公司
北京京东方传感技术有限公司
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Priority to CN202380008846.7A priority Critical patent/CN117321782A/zh
Publication of WO2023208149A1 publication Critical patent/WO2023208149A1/zh
Publication of WO2023208149A9 publication Critical patent/WO2023208149A9/zh

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01T—MEASUREMENT OF NUCLEAR OR X-RADIATION
    • G01T7/00—Details of radiation-measuring instruments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/12—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
    • H01L31/16—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources
    • H01L31/167—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources the light sources and the devices sensitive to radiation all being semiconductor devices characterised by potential barriers
    • H01L31/173—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources the light sources and the devices sensitive to radiation all being semiconductor devices characterised by potential barriers formed in, or on, a common substrate
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/30—Transforming light or analogous information into electric information
    • H04N5/32—Transforming X-rays

Definitions

  • the present disclosure relates to the field of photoelectric detection technology, and in particular to a detection substrate and a flat panel detector.
  • FPXD X-ray Panel Detector
  • TFT Thin Film Transistor
  • X-ray flat panel detectors mainly include thin film transistors and photoelectric conversion devices. Under X-ray irradiation, the scintillator layer or phosphor layer of the indirect conversion X-ray flat panel detector converts X-ray photons into visible light, and then converts the visible light into electrical signals under the action of the photoelectric conversion device, which is finally read by a thin film transistor Get the electrical signal and output the electrical signal to obtain the display image.
  • Embodiments of the present disclosure provide a detection substrate and a flat panel detector.
  • the specific solutions are as follows:
  • Embodiments of the present disclosure provide a detection substrate, including a substrate substrate having a detection area and a peripheral area located at the periphery of the detection area, the detection area including a plurality of pixel units distributed in an array; Pixel units include:
  • a thin film transistor arranged on one side of the base substrate
  • a photoelectric conversion device is provided on a side of the thin film transistor away from the base substrate, and the bottom electrode of the photoelectric conversion device is electrically connected to the source electrode of the thin film transistor;
  • a first bias voltage line is provided on a side of the photoelectric conversion device facing away from the base substrate, and the first bias voltage line is electrically connected to the top electrode of the photoelectric conversion device;
  • the compensation capacitor includes: the bottom electrode, a dielectric layer disposed on the side of the bottom electrode facing the base substrate, and a compensation electrode disposed on the side of the dielectric layer facing the base substrate ;
  • the detection substrate includes in the peripheral area: a plurality of first conductive layers arranged in the same layer as the compensation electrode, and a second bias voltage line arranged in the same layer as the first bias voltage line; at least one The first conductive layer is electrically connected to at least one column of the compensation electrodes, the second bias voltage line is electrically connected to the first bias voltage line, and the first conductive layer and the second bias Voltage wire electrical connection.
  • the detection substrate further includes a device disposed between the first conductive layer and the second bias voltage line in the peripheral area.
  • a plurality of second conductive layers are spaced apart from each other, and the second conductive layer and the bottom electrode are arranged on the same layer; the first conductive layer and the second bias voltage line electrical connection through the second conductive layer.
  • At least one of the first conductive layers and at least one of the second conductive layers are provided correspondingly to a column of the compensation electrodes.
  • the above detection substrate provided by the embodiment of the present disclosure also includes:
  • the interlayer insulating layer is provided between the thin film transistor and the photoelectric converter between pieces;
  • the flat layer is disposed between the photoelectric conversion device and the first bias voltage line;
  • first passivation layer being disposed between the flat layer and the first bias voltage line
  • the via area includes: at least one first via hole that penetrates the interlayer insulating layer, at least one second via hole that penetrates the first passivation layer, and at least one first via hole that penetrates the planarization layer.
  • the orthographic projection of the second via hole on the base substrate is located within the orthographic projection range of the third via hole on the base substrate, and the first conductive layer and the second conductive layer are electrically connected through the first via hole, and the second conductive layer and the second bias voltage line are electrically connected through the second via hole and the third via hole.
  • the above detection substrate provided by the embodiment of the present disclosure also includes:
  • a second passivation layer is provided between the photoelectric conversion device and the flat layer, and the second via hole penetrates the second passivation layer and the first passivation layer.
  • the above-mentioned detection substrate provided by the embodiment of the present disclosure further includes: a shielding layer provided on the side of the first bias voltage line away from the base substrate, and a shielding layer provided on the side of the first bias voltage line away from the base substrate. a third passivation layer between the first bias voltage line and the shielding layer; the shielding layer covers the first overlapping area, and each via area also includes a through-hole third passivation layer. at least one fourth via hole of the shielding layer, the shielding layer is electrically connected to the second bias voltage line through the fourth via hole.
  • the orthographic projection of the first via hole on the base substrate is located on the third via hole.
  • Three via holes are within the orthographic projection range of the base substrate, the first via holes and the second via holes are alternately arranged along the extension direction of the first overlapping area, and the third via hole is in The orthographic projection on the base substrate is located within the orthographic projection range of the fourth via hole on the base substrate.
  • the The diameter of the first via hole is larger than the diameter of the second via hole.
  • the orthographic projection of the first via hole on the substrate substrate is the same as the orthographic projection of the first via hole on the substrate substrate.
  • the orthographic projections of the three via holes on the base substrate do not overlap, and the orthographic projection of the fourth via hole on the base substrate and the orthographic projection of the third via hole on the base substrate No overlap.
  • the first via hole, the second via hole and the fourth via hole are arranged in an array.
  • the first overlapping area further includes a light-transmitting area spaced apart from the via area, and the light-transmitting area includes a through-hole area.
  • a first through hole in the first conductive layer, a second through hole through the second conductive layer, and a third through hole through the second bias voltage line, the first through hole, the third through hole The second through hole and the third through hole are set holes.
  • the first through hole, the second through hole and the third through hole are located on the front side of the base substrate.
  • the projected area decreases successively.
  • the via areas and the light-transmitting areas are arranged alternately.
  • the thin film transistor includes a gate electrode, a gate insulation layer, an active layer, the source electrode and a drain electrode arranged in a stack, and the The compensation electrode is arranged in the same layer as the source electrode, and the dielectric layer is the interlayer insulating layer.
  • the thin film transistor includes a gate electrode, a gate insulation layer, an active layer, the source electrode and a drain electrode arranged in a stack, and the The compensation electrode is arranged in the same layer as the gate electrode, and the dielectric layer is the interlayer insulating layer and the gate insulating layer.
  • the detection area further includes a first signal line and a second signal line that are insulated and crossed, and each of the second signal line and The drains of the thin film transistors in the pixel units in two adjacent columns are electrically connected, and the drains of the thin film transistors in each row are The gates of the thin film transistors in the pixel unit are alternately electrically connected to the two first signal lines located on both sides of the pixel unit in the corresponding row; wherein,
  • the two columns of compensation electrodes between each two adjacent second signal lines form a group, and a compensation line is provided in the gap between the corresponding two adjacent columns of the pixel units in each group.
  • the compensation line extends to the peripheral area, and is arranged on the same layer as the compensation electrodes on both sides and is electrically connected; each group of the compensation electrodes corresponds to two first conductive layers.
  • the first via hole also penetrates the gate insulation layer.
  • the detection area further includes a first signal line and a second signal line that are insulated and crossed, and each of the second signal line and The drains of the thin film transistors in one column of the pixel units are electrically connected, and each of the first signal lines is electrically connected to the gates of the thin film transistors in one row of the pixel units;
  • a plurality of compensation electrodes arranged along the arrangement direction of the via area are connected in series, and the first conductive layer is electrically connected to the compensation electrode closest to the first conductive layer among the compensation electrodes connected in series.
  • the first signal line or the second signal line extends to the peripheral area
  • the second bias voltage line is connected to the peripheral area.
  • the orthographic overlapping area of the first signal line or the second signal line on the base substrate has a plurality of first hollow structures arranged at intervals
  • the orthographic overlapping area of the second signal line on the base substrate has a plurality of second hollow structures arranged at intervals.
  • the orthographic projection of the first hollow structure on the base substrate and the orthographic projection of the second hollow structure on the base substrate partially overlap.
  • the ratio between the width of the first overlapping area and the width of the pixel unit is 50% to 75%, and the The length of the first overlapping area is 2 to 6 times the length of the pixel unit.
  • the second bias voltage line At the connection point between the first bias voltage line and the second bias voltage line, the second bias voltage line The width is greater than the width of the first bias voltage line.
  • the width of the first conductive layer is larger than that of the compensation electrode. width.
  • the orthographic projection of the first bias voltage line on the substrate substrate is the same as the orthographic projection of the pixel unit on the substrate substrate.
  • the orthographic projection of the first bias voltage line on the base substrate is located between the pixel unit and the second signal lines between orthographic projections on the base substrate.
  • an embodiment of the present disclosure also provides a flat panel detector, including any of the above detection substrates provided by an embodiment of the present disclosure.
  • Figure 1 is a schematic plan view of a detection substrate provided by the present disclosure
  • Figure 2 is a schematic cross-sectional view along the CC’ direction in Figure 1;
  • Figure 3 is another schematic cross-sectional view along the CC’ direction in Figure 1;
  • Figure 4 is another schematic cross-sectional view along the CC’ direction in Figure 1;
  • Figure 5 is a specific plan view of a detection substrate provided by the present disclosure.
  • Figure 6 is a specific plan view of another detection substrate provided by the present disclosure.
  • Figure 7 is a specific plan view of another detection substrate provided by the present disclosure.
  • Figure 8 is a specific plan view of another detection substrate provided by the present disclosure.
  • Figure 9 is an enlarged schematic diagram of the dotted box EE in Figure 5;
  • Figure 10A is a schematic cross-sectional view along the DD' direction in Figure 9;
  • Figure 10B is another schematic cross-sectional view along the DD' direction in Figure 9;
  • Figure 11 is a schematic plan view of the first conductive layer and the compensation electrode in the solution shown in Figure 5;
  • Figure 12A is a schematic plan view of the first conductive layer in the peripheral area
  • Figure 12B is a schematic plan view of the second conductive layer in the peripheral area
  • Figure 12C is a schematic plan view of the second bias voltage line in the peripheral area
  • Figure 12D is a plan view of the shielding layer in the surrounding area
  • Figure 13 is a schematic plan view of the first conductive layer and the compensation electrode in the solution shown in Figure 6;
  • Figure 14 is a schematic cross-sectional view along the NN’ direction in Figure 7;
  • Figure 15 is a partial plan view of the shielding layer in Figures 5, 6, 7 and 8;
  • FIG. 16 is a schematic diagram of the equivalent circuit after adding a compensation capacitor in FIGS. 2-8 according to the embodiment of the present disclosure.
  • the present disclosure provides a detection substrate, as shown in Figure 1, including a substrate substrate 1.
  • the substrate substrate 1 has a detection area AA and a peripheral area BB located outside the detection area AA.
  • the detection area AA includes an array.
  • Distributed multiple pixel units P as shown in Figures 2 to 4.
  • Figure 2 is a schematic cross-sectional view along the CC' direction in Figure 1
  • Figure 3 is another schematic cross-sectional view along the CC' direction in Figure 1.
  • Figure 4 is another schematic cross-sectional view along the CC' direction in Figure 1.
  • the pixel unit P includes:
  • Thin film transistor 2 is provided on one side of the base substrate 1;
  • the photoelectric conversion device 3 is arranged on the side of the thin film transistor 2 facing away from the base substrate 1, and the bottom electrode 31 of the photoelectric conversion device 3 is electrically connected to the source electrode 21 of the thin film transistor 2;
  • the first bias voltage line 4 is provided on the side of the photoelectric conversion device 3 facing away from the base substrate 1, and the first bias voltage line 4 is electrically connected to the top electrode 32 of the photoelectric conversion device 3;
  • the compensation capacitor 5 includes: a bottom electrode 31, a dielectric layer 51 provided on the side of the bottom electrode 31 facing the base substrate 1, and a compensation electrode 52 provided on the side of the dielectric layer 51 facing the base substrate 1;
  • Figures 5-8 are schematic diagrams of several planar structures of the detection substrate respectively.
  • the detection substrate includes in the peripheral area BB: a plurality of first conductive layers 6 arranged in the same layer as the compensation electrode 52, and a second bias voltage line 7 arranged in the same layer as the first bias voltage line 4; at least one first conductive layer 6 is electrically connected to at least one column of compensation electrodes 52, and the second bias voltage line 7 is connected to the first bias voltage line 7.
  • Line 4 is electrically connected, and first conductive layer 6 and second bias voltage line 7 are electrically connected.
  • the above detection substrate provided by the embodiment of the present disclosure forms a compensation capacitor in the pixel unit that is shared with the bottom electrode of the photoelectric conversion device.
  • the compensation capacitor is connected to the top electrode and the bottom electrode of the photoelectric conversion device.
  • the formed storage capacitance is equivalent to a parallel connection, thereby increasing the capacitance of the photoelectric conversion device. Therefore, the present disclosure can increase the charge storage capacity of the pixel unit and improve the dynamic range of the output signal of the flat panel detector without losing resolution; and,
  • the compensation electrode of the compensation capacitor is not electrically connected to the first bias voltage line in the pixel unit, but is provided in the peripheral area with a first conductive layer in the same layer as the compensation electrode and electrically connected to the first bias voltage line.
  • the above-mentioned multiple first conductive layers 6 are arranged in the same layer as the compensation electrode 52.
  • the same layer here means that the two film layers of the compensation electrode 52 and the first conductive layer 6 are the same layer.
  • the two film layers of the electrode 52 and the first conductive layer 6 are prepared in the same process, and the two film layers of the compensation electrode 52 and the first conductive layer 6 are structurally located on the same plane.
  • the above-mentioned second bias voltage line 7 is arranged on the same layer as the first bias voltage line 4.
  • the same layer here refers to: the first bias voltage line 4 and the second bias voltage line. 7.
  • the two film layers are the same layer.
  • the first bias voltage line 4 and the second bias voltage line 7 are prepared in the same process, and the first bias voltage line 4 and the second bias voltage line 7 are prepared in the same process. 7
  • the two membrane layers are structurally located on the same plane.
  • the thin film transistor 2 includes a stacked gate electrode 22 , a gate insulating layer 23 , an active layer 24 , and a source electrode 21 and drain electrode 25, the photoelectric conversion device 3 also includes a photoelectric conversion layer 33 located between the bottom electrode 31 and the top electrode.
  • the photoelectric conversion layer 33 converts optical signals into electrical signals, and the bottom electrode 31 is used to conduct the electrical signals formed by the photoelectric conversion layer 33 after being illuminated. There is a facing area between the bottom electrode 31 and the top electrode 32.
  • a storage capacitor is formed between them, and the present disclosure also adds a compensation capacitor 5, which increases the capacitance of the photoelectric conversion device 3, so that the electrical signal converted by the photoelectric conversion layer 33 can be stored in the above-mentioned storage capacitor and compensation capacitor 5, improving detection.
  • the dynamic range of the substrate output signal When the detection substrate is working, for example, a voltage of -5 to -10 V is applied to the top electrode 32 through the first bias voltage line 4, so that the photoelectric conversion layer 33 operates under a negative bias voltage, and the photoelectric conversion layer 33 generates different electrical signals.
  • the telecommunications The signal is stored in the bottom electrode 31, and the electrical signal stored in the bottom electrode 31 is transmitted to the external IC through the thin film transistor 2 to save the image data.
  • the photoelectric conversion layer 33 may have a PN structure or a PIN structure.
  • the PIN structure includes an N-type doped N-type semiconductor layer, an undoped intrinsic semiconductor layer I, and a P-type doped P-type semiconductor layer.
  • the thickness of the intrinsic semiconductor layer I may be greater than the thickness of the P-type semiconductor layer and the N-type semiconductor layer.
  • the orthographic projection of the top electrode 32 on the base substrate 1 is located within the orthographic projection of the photoelectric conversion layer 33 on the base substrate 1 , that is, the area of the top electrode 32 is slightly smaller than the area of the photoelectric conversion layer 33 , which can reduce the photoelectric conversion rate. Leakage current caused by damage to the sidewall of the conversion layer 33 during etching.
  • the bottom electrode 31 may be formed of molybdenum, aluminum, silver, copper, titanium, platinum, tungsten, tantalum, tantalum nitride, alloys thereof, combinations thereof, or other suitable materials; and may be formed of indium tin oxide (ITO) or Indium zinc oxide (IZO) or other suitable transparent materials form the top electrode 32 to improve light transmission efficiency.
  • ITO indium tin oxide
  • IZO Indium zinc oxide
  • the above-mentioned detection substrate provided by the embodiment of the present disclosure also includes:
  • Interlayer insulating layer 8 interlayer insulating layer 8 is provided between the thin film transistor 2 and the photoelectric conversion device 3;
  • the flat layer 10 is provided between the photoelectric conversion device 3 and the first bias voltage line 4;
  • the first passivation layer 11 is provided between the flat layer 10 and the first bias voltage line 4 ; wherein the bottom electrode 31 communicates with the source electrode through the fifth via V5 that penetrates the interlayer insulating layer 8 21 electrical connections.
  • the above-mentioned detection substrate provided by the embodiment of the present disclosure also includes a second passivation layer 9 disposed between the photoelectric conversion device 3 and the flat layer 10; wherein, The first bias voltage line 4 is electrically connected to the top electrode 32 of the photoelectric conversion device through a sixth via hole V6 that sequentially penetrates the first passivation layer 11 , the planarization layer 10 and the second passivation layer 9 .
  • the compensation electrode 52 can be arranged in the same layer as the source electrode 21, and the dielectric layer 51 of the compensation capacitor 5 is is the interlayer insulating layer 8. In this way, only the original patterning pattern needs to be changed when forming the source electrode 21, and the patterns of the compensation electrode 52 and the source electrode 21 can be formed through one patterning process. There is no need to add a separate process for preparing the compensation electrode 52, and the preparation process can be simplified. Save production costs and improve production efficiency Rate.
  • the compensation electrode 52 can also be provided in the same layer as the gate electrode 22 , and the dielectric layer 51 of the compensation capacitor 5 is the layer. interlayer insulating layer 8 and gate insulating layer 23. In this way, it is only necessary to change the original patterning pattern when forming the gate electrode 22, and the patterns of the compensation electrode 52 and the gate electrode 22 can be formed through one patterning process. There is no need to add a separate process for preparing the compensation electrode 52, and the preparation process can be simplified. Save production costs and improve production efficiency. In addition, compared with the compensation capacitor 5 shown in FIGS.
  • the dielectric layer 51 of the compensation capacitor 5 shown in FIG. 3 is thicker, so for the compensation electrode 52 of the same area, the compensation capacitor shown in FIG. 3
  • the capacitance value of 5 increases by approximately 50% compared to the capacitance values shown in FIGS. 2 and 4 , and the specific increase in the capacitance value depends on the thickness of the gate insulating layer 23 .
  • the capacitance value can also be adjusted by adjusting the thickness of the interlayer insulating layer 8 and the gate insulating layer 23 .
  • the second bias voltage line 7 and the first conductive layer 6 located in the peripheral area BB are generally connected through via holes, because there are multiple layers between the second bias voltage line 7 and the first conductive layer 6
  • the detection substrate also includes a plurality of second conductive layers 12 disposed between the first conductive layer 6 and the second bias voltage line 7 in the peripheral area BB. The plurality of second conductive layers 12 are spaced apart from each other.
  • the two conductive layers 12 can be arranged in the same layer as the bottom electrode 31 in FIG. 2 ; the first conductive layer 6 and the second bias voltage line 7 are electrically connected through the second conductive layer 12 .
  • the second conductive layer 12 can serve as an overlapping film layer between the first conductive layer 6 and the second bias voltage line 7 , thereby avoiding electrical connection between the second bias voltage line 7 and the first conductive layer 6 Bad question.
  • the above-mentioned second conductive layer 12 can be provided in the same layer as the bottom electrode 31 in FIG. 2 .
  • the same layer here means that the second conductive layer 12 and the bottom electrode 31 are the same layer.
  • the two film layers of the second conductive layer 12 and the bottom electrode 31 are prepared in the same process, and the structure of the two film layers of the second conductive layer 12 and the bottom electrode 31 is located on the same plane.
  • a column of compensation electrodes 52 is provided with at least one first conductive layer 6 and at least one second conductive layer 12.
  • Figure 5 is based on a column of compensation electrodes 52.
  • the compensation electrode 52 is provided with a first conductive layer 6 and a second conductive layer 12.
  • A1 the first overlapping area A1 includes at least one via area V
  • the first conductive layer 6 and the second conductive layer 12 are electrically connected through at least one via area V
  • the second conductive layer 12 and the second bias voltage line 7 It is electrically connected through at least one via area V.
  • the first conductive layer 6 and the second conductive layer 12 can be electrically connected through a plurality of via hole areas V
  • the second conductive layer 12 and the second bias voltage line 7 can be electrically connected through a plurality of via hole areas V, which can increase
  • the contact area between the first conductive layer 6 and the second conductive layer 12 and the contact area between the second conductive layer 12 and the second bias voltage line 7 are increased, so that the first conductive layer 6 and the second bias voltage line 7 can be reduced.
  • the resistance of the conductive layer 12 and the second bias voltage line 7 improves the electrical performance of the flat panel detector.
  • Figure 9 is an enlarged schematic diagram within the dotted box EE in Figure 5
  • Figure 10A is the middle edge of Figure 9
  • the via area V includes: at least one first via V1 (two are taken as an example, it can also be one or more) that penetrates the interlayer insulating layer 8, At least one second via hole V2 (taking two as an example, it can also be one or more) of the flat layer 11, and at least one third via hole V3 (taking one as an example) that penetrates the planarization layer 10;
  • the orthographic projection of the second via hole V2 on the base substrate 1 is located within the orthographic projection range of the third via hole V3 on the base substrate 1.
  • the first conductive layer 6 and the second conductive layer 12 is electrically connected through the first via hole V1
  • the second conductive layer 12 and the second bias voltage line 7 are electrically connected through the second via hole V2 and the third via hole V3.
  • the first conductive layer 6 and the second conductive layer 12 are electrically connected through a plurality of first via holes V1, which can further increase the contact area of the first conductive layer 6 and the second conductive layer 12 and further reduce the first conductive layer.
  • the third via V3 is designed as a large hole, and the second bias voltage wire 7 can be laid
  • the third via hole V3 is filled and is electrically connected through the second via hole V2 that penetrates the first passivation layer 11, thereby preventing the second bias voltage line 7 from breaking due to excessive via hole gap; and,
  • the number of the two via holes V2 can be set to multiple, so that the contact resistance between the second conductive layer 12 and the second bias voltage line 7 can be further reduced.
  • the materials of the first conductive layer 6 , the second conductive layer 12 and the second bias voltage line 7 are metal materials, the adhesion between the resin material and the metal is low. It is easy to cause the flat layer 10 and the film layer formed thereon to peel off from the second conductive layer 12.
  • Figure 10B is along DD' in Figure 9 Another schematic cross-sectional view of the direction, the second passivation layer 9 is retained between the flat layer 10 and the second conductive layer 12, and the second passivation layer 9 and the first passivation layer 11 are in direct contact at the third via V3 , in this way, the second via hole V2 penetrates the second passivation layer 9 and the first passivation layer 11, which can avoid the problem of film peeling off.
  • the above-mentioned detection substrate provided by the embodiment of the present disclosure, as shown in Figures 2, 5, 9, 10A and 10B, also includes: a bias voltage line 4 facing away from the shielding layer 13 on the side of the substrate 1, and a third passivation layer 14 disposed between the first bias voltage line 4 and the shielding layer 13; the shielding layer 13 covers the first overlapping In the area A1, each via hole area V also includes at least one fourth via hole V4 penetrating the third passivation layer 14, and the shielding layer 13 is electrically connected to the second bias voltage line 7 through the fourth via hole V4.
  • the material of the shielding layer 13 is generally a transparent conductive material, such as indium tin oxide (ITO), boron-doped zinc oxide (BZO), aluminum-doped zinc oxide (AZO), etc.
  • ITO indium tin oxide
  • BZO boron-doped zinc oxide
  • AZO aluminum-doped zinc oxide
  • the first via V1 is on the base substrate 1
  • the orthographic projection on the substrate 1 may be located within the orthographic projection range of the third via hole V3 on the base substrate 1 .
  • the first via hole V1 and the second via hole V2 may be alternately arranged along the extension direction of the first overlapping area A1 .
  • the orthographic projection of the via hole V3 on the base substrate 1 is located within the orthographic projection range of the fourth via hole V4 on the base substrate 1 .
  • the transparent conductive material used in the shielding layer 13 has a large resistivity
  • the first via V1 and the second via V2 are designed to be orthogonally projected and located at the third via within the orthographic projection range of hole V3, in this way, when the size of the fourth via hole V4 is constant, there is no need to expand the size of the via hole area V, and the first overlapping area A1 can have more space to install a greater number of vias.
  • the hole area V further reduces the contact resistance between the conductive layers.
  • the distance between the orthogonal projection edges of the third via hole V3 and the fourth via hole V4 on the base substrate 1 is greater than 2.5 ⁇ m, and the third via hole V3 and the second through hole V2 are on the base substrate 1
  • the distance between orthographic projection edges is greater than 2.5 ⁇ m.
  • the size of the first via V1 is 10 ⁇ m*10 ⁇ m
  • the size of the second via V2 is 8 ⁇ m*8 ⁇ m
  • the size of the third via V3 is 20 ⁇ m*75 ⁇ m
  • the size of the fourth via V4 is 25 ⁇ m*. 80 ⁇ m.
  • the second via V2 and the sixth via V6 can be manufactured through a single patterning process.
  • the etching size of the sixth via V6 is smaller, so the size of the second via V2 is also smaller, because the thickness of the interlayer insulating layer 8 is generally much larger than the thickness of the passivation layer (9 and 11) , in order to ensure good contact and electrical connection between the second conductive layer 12 and the first conductive layer 6, the size of the first via hole V1 needs to be designed to be larger than the size of the second via hole V2.
  • the embodiment of the present disclosure provides In the above detection substrate, the aperture D1 of the first via hole V1 is larger than the aperture D2 of the second via hole V2.
  • the aperture diameter refers to the length along the arrangement direction of the first via hole V1 and the second via hole V2.
  • the materials of the second passivation layer 9, the first passivation layer 11, the third passivation layer 14, the gate insulating layer 23, and the interlayer insulating layer 8 can be inorganic materials, such as silicon nitride, silicon oxide, Silicon oxynitride, etc.
  • the detection substrate also includes: a scintillator layer 15 located on the side of the shielding layer 13 facing away from the base substrate 1 .
  • the material is a material that can convert X-rays into visible light. It is mainly composed of scintillator.
  • the scintillator itself is a type of material that can emit light after absorbing high-energy particles or rays. It is usually added in applications.
  • the artificial crystal is called a scintillation crystal; the embodiment of the present disclosure does not limit the specific material of the scintillation crystal of the scintillator layer 15, which can be cesium iodide (CsI), cadmium tungstate, barium fluoride, gadolinium oxysulfide ( GOS) etc.
  • CsI cesium iodide
  • GOS gadolinium oxysulfide
  • the working process of the detection substrate shown in FIG. 2 provided by the embodiment of the present disclosure is: under the impact of high-energy particles of X-rays, the scintillator layer 15 converts the kinetic energy of the high-energy particles into light energy and emits a flash (visible light signal). ), the optical signal can be converted into an electrical signal through the photoelectric conversion device 3, and read out through the thin film transistor 2, so as to obtain an X-ray image through subsequent signal processing (including amplification, conversion, etc.).
  • the scintillator layer 15 needs to be encapsulated, and the encapsulation layer and the base substrate 1 are generally fixed by UV glue.
  • the UV glue needs to be cured by ultraviolet light.
  • the encapsulation layer is opaque, the UV glue needs to be irradiated from the side of the substrate. Therefore, in the above detection substrate provided by the embodiment of the present disclosure, as shown in Figures 5 and 9, the first overlapping area A1 also includes A light-transmitting region T is spaced apart from the via-hole region V.
  • the light-transmitting region T includes a first through hole H1 penetrating the first conductive layer 6 , a second through hole H2 penetrating the second conductive layer 12 , and a second bias voltage penetrating
  • the third through hole H3, the first through hole H1, the second through hole H2 and the third through hole H3 of line 7 are set holes. In this way, the light-transmitting area T can be irradiated from one side of the base substrate 1 to solidify the UV glue, thereby encapsulating the scintillator layer 15 .
  • the first through hole H1 the second through hole H2 and the third The orthogonal projected area of the three-through hole H3 on the base substrate 1 gradually decreases.
  • the first through hole H1 and the second through hole H2 are between the orthographic projection edges on the substrate 1
  • the distance between the orthogonal projection edges of the second through hole H2 and the third through hole H3 on the base substrate 1 is greater than 2.5 ⁇ m.
  • the via area V and the light-transmitting area T can be alternately arranged, but of course it is not limited to this. In this way, multiple via hole areas V and multiple light-transmitting areas T can be set to minimize contact resistance and ensure the encapsulation effect of the scintillator layer by the encapsulation layer.
  • three via hole areas V and two light-transmitting areas T are provided as an example.
  • the number of the via-hole areas V and the light-transmitting areas T in the same column can be determined according to the actual wiring space and the first polarization.
  • the resistance of voltage line 4 requires adjustment.
  • the detection area AA also includes a first signal line 16 (such as a gate line) and a second signal line (such as a data line) that are insulated and crossed. line), each second signal line 17 is electrically connected to the drain electrode 25 of the thin film transistor 2 in one column of pixel units P, and each first signal line 16 is electrically connected to the gate electrode 22 of the thin film transistor 2 in one row of pixel units P;
  • the orthographic projection of a bias voltage line 4 on the base substrate 1 can overlap with the orthographic projection of the pixel unit P on the base substrate 1;
  • a plurality of compensation electrodes 52 arranged along the arrangement direction of the via area V (for example, the column direction of the pixel unit) are connected in series, and the first conductive layer 6 and the compensation electrode closest to the first conductive layer 6 among the series-connected compensation electrodes 52 52 electrical connections.
  • Figure 11 is a schematic plan view of the first conductive layer 6 and the compensation electrode 52 in the solution shown in Figure 5. Compared with Figure 11 In FIG. 5 , more pixel units in the detection area AA are shown to illustrate that a row of compensation electrodes 52 are connected in series.
  • the embodiment of the present disclosure realizes the second bias voltage on one side in the extension direction of the second signal line 17 (data line).
  • the second signal line 17 generally extends to the peripheral area BB and is electrically connected to the driver chip (IC) in the peripheral area BB.
  • IC driver chip
  • the overlapping capacitance between the data line and the shielding layer 13 is reduced, and the overlapping area of the second bias voltage line 7 and the second signal line 17 on the base substrate 1 has multiple spaced-apart intervals.
  • first hollow structure LK1 There is a first hollow structure LK1, and the orthographic overlap area of the shielding layer 13 and the second signal line 17 on the base substrate 1 has a plurality of second hollow structures LK2 arranged at intervals. This can reduce the overlapping capacitance between the data line and the second bias voltage line 7 and the overlapping capacitance between the data line and the shielding layer 13 , thereby avoiding mutual interference.
  • Figure 12A is Figure 12B is a schematic plan view of the second conductive layer 12 in the peripheral area BB.
  • Figure 12C is a schematic plan view of the second bias voltage line 7 in the peripheral area BB.
  • Figure 12D is a schematic plan view of the first conductive layer 6 in the peripheral area BB. Schematic plan view of the shielding layer 13 in the peripheral area BB.
  • the value of the width W1 of the first overlapping area A1 needs to be designed according to the size of the pixel unit P.
  • the width W1 exceeds The wider the better, optionally, the ratio between the width W1 of the first overlapping area A1 and the width W2 of the pixel unit P can be 50% to 75%, for example, the ratio is 50%, 55%, 60%, 65% , 70%, 75%, etc.; the value of the length L1 of the first overlapping area A1 needs to be designed according to the wiring space and the resistance requirements of the first bias voltage line 4.
  • the length L1 of the first overlapping area A1 can It is 2 to 6 times the length L2 of the pixel unit P.
  • the length L1 of the first overlapping area A1 is 2 times, 2.5 times, 3 times, 3.5 times, 4 times, 4.5 times, 5 times the length L2 of the pixel unit P. times, 5.5 times or 6 times, etc.
  • the second bias voltage line 7 At the connection point between the first bias voltage line 4 and the second bias voltage line 7 , the second bias voltage line 7 The width W3 is greater than the width W4 of the first bias voltage line 4 . In this way, the second bias voltage line 7 is designed to be widened in the peripheral area BB, which can reduce the resistance of the second bias voltage line 7.
  • the first bias voltage line 4 is reduced in the detection area AA according to the design requirements of the pixel unit, so as to Ensure that the overall RC load and pixel fill rate of the pixel unit meet specification requirements.
  • the width W5 of the first conductive layer 6 is larger than the width W5 of the compensation electrode 52 .
  • Width W6 is designed to be widened in the peripheral area BB, which can reduce the resistance of the first conductive layer 6.
  • the compensation electrode 52 is reduced in the detection area AA according to the design requirements of the pixel unit to ensure the overall RC load of the pixel unit and the pixel Filling rate, etc. meet specification requirements.
  • Figure 6 is another schematic plan view of the peripheral area corresponding to the structure shown in Figure 2
  • Figure 13 is a schematic plan view of the first conductive layer 6 and the compensation electrode 52 in the solution shown in FIG. 6.
  • the detection area AA also includes a first signal line 16 (for example, a gate line) and a second signal line 17 (for example, a data line) that are insulated and crossed.
  • each second signal line 17 is electrically connected to the drain electrodes 25 of the thin film transistors 2 in the pixel units P in two adjacent columns, and the gate electrodes 22 of the thin film transistors 2 in each row of pixel units P are alternately connected to the pixels in the corresponding row.
  • the two first signal lines 16 on both sides of the unit P are electrically connected; among them,
  • the two columns of compensation electrodes 52 between each two adjacent second signal lines 17 form a group of FF.
  • a compensation line 53 is provided in the gap between the corresponding two adjacent columns of pixel units P in each group of FF.
  • the compensation line 53 extends to the peripheral area BB, and the compensation line 53 is arranged on the same layer as the compensation electrodes 52 on both sides and is electrically connected; each set of compensation electrodes 52 corresponds to two first conductive layers 6 .
  • a data line simultaneously connects two columns of pixel units P on both sides of it, and a gate line only connects half of the pixel units P in its adjacent rows of pixels. This design can not only reduce the number of data lines, but also reduce the number of driver ICs.
  • One compensation line 53 can connect the compensation electrodes 52 of the two columns of pixel units on both sides of it, and then the compensation line 53 extends to the peripheral area BB and the two columns on both sides of it.
  • the first conductive layer is electrically connected.
  • the electrical connection design of the compensation electrode 52 and the first bias voltage line 4 in the peripheral area BB in the structure shown in FIG. 6 is basically the same as the electrical connection method shown in FIG. 5 .
  • the main differences are as follows: (1) Figure 6 uses two via areas V and two light-transmitting areas T in the same column of the peripheral area BB. Compared with Figure 5, three via areas V are used in the same column of the peripheral area BB. and 2 light-transmitting areas T.
  • Figure 6 reduces the length L1 of the first overlapping area A1 to meet the requirements of narrow-frame products; (2) The distance between the pixel unit P and the gate lines and data lines in Figures 5 and 6 The connection relationship is different (already introduced before); (3) The electrical connection method between the compensation electrode 52 and the first conductive layer 6 in Figures 5 and 6 is different.
  • the cross-sectional schematic diagram of the via area V and the light-transmitting area T is the same as that of Figure 10A or Figure 10A. 10B is the same; other designs can refer to the structure shown in Figure 5.
  • connection relationship between the pixel unit and the gate line and the data line is not limited to the connection relationship shown in Figure 5 and Figure 6, and can also be other connection relationships.
  • System as long as the method of increasing the compensation capacitance provided by the embodiment of the present disclosure can be adopted and the compensation capacitor is electrically connected to the first bias voltage line in the peripheral area, it falls within the scope of protection of the present disclosure.
  • Figure 7 is a schematic plan view of the structure shown in Figure 3 corresponding to the peripheral area BB, Figure 3 It is a schematic cross-sectional view along the GG' direction in Figure 7.
  • Figure 14 is a schematic cross-sectional view along the NN' direction in Figure 7.
  • the compensation electrode 52 and the gate electrode 22 are arranged in the same layer.
  • the dielectric layer 51 of the compensation capacitor 5 is the interlayer insulating layer. 8 and the gate insulating layer 23, so the first via V1 also penetrates the gate insulating layer 23.
  • the positional relationship between the first conductive layer 6, the second conductive layer 12, the second bias voltage line 7 and the shielding layer 13 and the pattern of each film layer are the same as the structure shown in Figure 5.
  • the first conductive layer 6 , the via connection arrangement between the second conductive layer 12, the second bias voltage line 7 and the shielding layer 13 is the same as that in Figure 7.
  • connection relationship between the pixel unit P and the gate line and the data line in the detection area AA is as shown in Figure 5
  • the connection relationship is the same.
  • the positions of the first conductive layer 6, the second conductive layer 12 and the second bias voltage line 7 in the peripheral area BB in Figure 7 are different from that in Figure 5.
  • the first conductive layer 6, the second conductive layer 12 and the second bias voltage line 7 are arranged on one side of the extension direction of the line) to realize the electrical connection between the second bias voltage line 7 and the first conductive layer 6, and Figure 7 is on the A first conductive layer 6, a second conductive layer 12 and a second bias voltage line 7 are provided on one side of the extension direction of a signal line 16 (gate line) to achieve electrical connection between the second bias voltage line 7 and the first conductive layer 6.
  • the second bias voltage line 7 and the first conductive layer 6 are electrically connected through three via hole areas V, and a light-transmitting area T is provided between two adjacent via hole areas V.
  • a plurality of first hollow structures LK1 are also provided at intervals in the overlapping area of the orthographic projection of the second bias voltage line 7 and the second signal line 17 on the base substrate 1.
  • the shielding layer 13 and the second signal line 17 are located in
  • a plurality of second hollow structures LK2 are also provided at intervals in the orthographic overlapping area on the base substrate 1 .
  • the main difference between Figure 7 and Figure 5 is that the first via hole V1, the second via hole V2, the third via hole V3 and the fourth via hole V4 in the same via hole area V are arranged differently.
  • the first via V1 is lined with The orthographic projection on the base substrate 1 does not overlap with the orthographic projection of the third via hole V3 on the base substrate 1.
  • the orthographic projection of the fourth via hole V4 on the base substrate 1 does not overlap with the orthographic projection of the third via hole V3 on the base substrate 1.
  • Orthographic projections on 1 do not overlap.
  • the third via V3 still adopts a large hole design to facilitate metal overlap and prevent the second bias voltage line 7 from breaking due to excessive via hole difference;
  • the first via V1, the second via V2 and The fourth vias V4 all adopt a small hole design, so that a greater number of first vias V1 and fourth vias V4 can be set outside the third via V3, and a greater number of second vias can also be set V2, thereby further reducing the contact resistance between metal layers.
  • the first via hole V1, the second via hole V2 and the fourth via hole V4 can all be arranged in an array,
  • the first via hole V1, the second via hole V2, and the fourth via hole V4 are all arranged in a 2*2 square shape as an example, but of course it is not limited to this.
  • the fourth via V4 can be moved directly above the first via V1, or it can be the first via V1 is moved below the fourth via hole V4, or the positions of the first via hole V1 and the fourth via hole V4 can be exchanged.
  • the via holes in the via hole area V in Figure 5 are arranged in long strips, and the via holes in the via hole area V in Figure 7 are arranged in strips.
  • the via holes are arranged in an array, which can ensure that the overall flatness of each area of the detection substrate is consistent, which is beneficial to the subsequent evaporation of the scintillator layer 15 .
  • Figure 5 is a schematic cross-sectional view along the MM' direction in Figure 8.
  • the orthographic projection of the first bias voltage line 4 on the base substrate 1 is located at the pixel unit P and the second signal line 17 (data lines) between the orthographic projections on the base substrate 1.
  • the entire first bias voltage line 4 is moved outside the photoelectric conversion device 3, and only the sixth via hole V6 overlaps with the photoelectric conversion device 3. This can reduce the light sensitivity of the first bias voltage line 4 to the photoelectric conversion device 3.
  • Area occlusion improves the filling rate of pixels, which in turn improves the sensitivity of the detection substrate and signal-to-noise ratio.
  • the film layer positional relationship between the first conductive layer 6, the second conductive layer 12, the second bias voltage line 7 and the shielding layer 13 as well as the graphics and figures of each film layer are The structure shown in Figure 5 is the same, and the via connection arrangement between the first conductive layer 6, the second conductive layer 12, the second bias voltage line 7 and the shielding layer 13 is the same as that in Figure 7.
  • the peripheral areas BB on both sides of the extending direction of the second signal line 17 are called the upper frame and the lower frame, and the first signal line 17 is called the upper frame and the lower frame.
  • the peripheral areas BB on both sides of the extension direction of the line 16 are called the left border and the right border.
  • the first conductive layer 6 and the second bias voltage line 7 in Figures 5, 6 and 8 are on the upper border.
  • the electrical connection can also be electrically connected at the lower frame, or both the upper and lower frames can be electrically connected; currently, the first conductive layer 6 and the second bias voltage line 7 in Figure 7 are electrically connected at the left frame, of course. It can be electrically connected on the right frame, or both left and right frames can be electrically connected.
  • the orthographic projection of the first bias voltage line 4 on the base substrate 1 is different from the orthographic projection of the compensation electrode 52 on the base substrate 1 .
  • Overlap can also overlap.
  • the size of the compensation electrode 52 is designed according to the size of the compensation capacitor 5 that needs to be increased.
  • a hollow structure needs to be provided in the area where the shielding layer 13 overlaps the data lines or gate lines in the peripheral area BB to reduce the interference between the shielding layer 13 and the data lines or gate lines.
  • Figure 15 is a partial plan view of the shielding layer 13 in Figures 5, 6, 7 and 8.
  • Figure 16 is a schematic diagram of the equivalent circuit after adding the compensation capacitor 5 in Figures 2 to 8 according to the embodiment of the present disclosure. It can be seen that the second bias voltage line 7 and the compensation electrode 52 are electrically connected in the peripheral area BB. connect.
  • the compensation capacitor added to the detection substrate provided by the embodiment of the present disclosure has one electrode shared with the bottom electrode of the photoelectric conversion device, and the other electrode (compensation electrode) is in the same layer as the source or gate of the thin film transistor. setting, so that there is no need to increase the number of masks and process; the size of the compensation capacitor can be flexibly adjusted by the overlap area of the compensation electrode and the bottom electrode.
  • the compensation electrode and The thickness and dielectric constant of the insulating layer between the bottom electrodes can also be adjusted through the process, thereby also achieving the purpose of adjusting the size of the compensation capacitor;
  • the compensation electrode of the compensation capacitor is not electrically connected to the first bias voltage line through holes in the pixel unit, but is electrically connected to the first bias voltage line by providing a conductive film layer in the peripheral area.
  • the process of punching holes is much less difficult than punching holes in the detection area, and it also saves the punching space in the pixel unit, avoiding further loss of the filling rate of the photoelectric conversion device of high-resolution products.
  • an embodiment of the present disclosure also provides a flat panel detector, including the above detection substrate provided by an embodiment of the present disclosure. Since the problem-solving principle of this flat-panel detector is similar to that of the aforementioned detection substrate, the implementation of this flat-panel detector can be referred to the implementation of the aforementioned detection substrate, and repeated details will not be repeated.
  • Embodiments of the present disclosure provide a detection substrate and a flat panel detector.
  • the compensation capacitance is equivalent to the storage capacitance formed by the top electrode and the bottom electrode of the photoelectric conversion device. Because of the parallel connection, the capacitance of the photoelectric conversion device is increased.
  • the present disclosure can increase the charge storage capacity of the pixel unit and improve the dynamic range of the output signal of the flat panel detector without losing resolution; and, the compensation of the compensation capacitance
  • the electrode is not electrically connected to the first bias voltage line in the pixel unit, but a first conductive layer on the same layer as the compensation electrode and electrically connected to it and a third conductive layer on the same layer as and electrically connected to the first bias voltage line are provided in the peripheral area.
  • the two bias voltage lines are then electrically connected to the first conductive layer and the second bias voltage line in the peripheral area. This is equivalent to the compensation electrode being electrically connected to the first bias voltage line in the peripheral area, thus saving the space inside the pixel unit.
  • the punching space avoids further loss of the filling rate of the photoelectric conversion device of high-resolution products.

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Abstract

本公开公开了一种探测基板及平板探测器，该探测基板的探测区域包括阵列分布的多个像素单元，像素单元包括薄膜晶体管、光电转换器件、第一偏置电压线和补偿电容，光电转换器件的底电极与薄膜晶体管的源极电连接，第一偏置电压线与光电转换器件的顶电极电连接；补偿电容包括：底电极，设置在底电极面向衬底基板一侧的介质层，以及设置在介质层面向衬底基板一侧的补偿电极；探测基板在周边区域包括：与补偿电极同层设置的多个第一导电层，以及与第一偏置电压线同层设置的第二偏置电压线；至少一个第一导电层与至少一列补偿电极电连接，第二偏置电压线与第一偏置电压线电连接，且第一导电层和第二偏置电压线电连接。

Description

一种探测基板及平板探测器
相关申请的交叉引用
本申请要求在2022年4月28日提交中国专利局、申请号为PCT/CN2022/089699、申请名称为“光电探测器及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及光电检测技术领域，特别涉及一种探测基板及平板探测器。
背景技术
基于薄膜晶体管(Thin Film Transistor，TFT)技术制作的X射线平板探测器(Flat X-ray Panel Detector，FPXD)是数字影像技术中至关重要的元件，由于其具有成像速度快，良好的空间及密度分辨率、高信噪比、直接数字输出等优点，广泛应用于医学影像(如X光胸透)、工业检测(如金属探伤)、安保检测、航空运输等领域。
X射线平板探测器主要包括薄膜晶体管与光电转换器件。在X射线照射下，间接转换型X射线平板探测器的闪烁体层或荧光体层将X射线光子转换为可见光，然后在光电转换器件的作用下将可见光转换为电信号，最终通过薄膜晶体管读取电信号并将电信号输出得到显示图像。
发明内容
本公开实施例提供了一种探测基板及平板探测器，具体方案如下：
本公开实施例提供了一种探测基板，包括衬底基板，所述衬底基板具有探测区域和位于所述探测区域外围的周边区域，所述探测区域包括阵列分布的多个像素单元；所述像素单元包括：
薄膜晶体管，设置在所述衬底基板的一侧；
光电转换器件，设置在所述薄膜晶体管背离所述衬底基板的一侧，所述光电转换器件的底电极与所述薄膜晶体管的源极电连接；
第一偏置电压线，设置在所述光电转换器件背离所述衬底基板的一侧，所述第一偏置电压线与所述光电转换器件的顶电极电连接；
补偿电容，所述补偿电容包括：所述底电极，设置在所述底电极面向所述衬底基板一侧的介质层，以及设置在所述介质层面向所述衬底基板一侧的补偿电极；
所述探测基板在所述周边区域包括：与所述补偿电极同层设置的多个第一导电层，以及与所述第一偏置电压线同层设置的第二偏置电压线；至少一个所述第一导电层与至少一列所述补偿电极电连接，所述第二偏置电压线与所述第一偏置电压线电连接，且所述第一导电层和所述第二偏置电压线电连接。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，所述探测基板在所述周边区域还包括设置在所述第一导电层和所述第二偏置电压线之间的多个第二导电层，所述多个第二导电层相互间隔，所述第二导电层与所述底电极同层设置；所述第一导电层和所述第二偏置电压线通过所述第二导电层电连接。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，一列所述补偿电极对应设置至少一个所述第一导电层和至少一个所述第二导电层，所述第一导电层、所述第二导电层和所述第二偏置电压线三者之间具有第一交叠区域，所述第一交叠区域包括至少一个过孔区域，所述第一导电层和所述第二导电层通过所述至少一个过孔区域电连接，所述第二导电层和所述第二偏置电压线通过所述至少一个过孔区域电连接。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，还包括：
层间绝缘层，所述层间绝缘层设置在所述薄膜晶体管和所述光电转换器 件之间；
平坦层，所述平坦层设置在所述光电转换器件和所述第一偏置电压线之间；
第一钝化层，所述第一钝化层设置在所述平坦层和所述第一偏置电压线之间；
其中，所述过孔区域包括：贯穿所述层间绝缘层的至少一个第一过孔，贯穿所述第一钝化层的至少一个第二过孔，以及贯穿所述平坦层的至少一个第三过孔；
在同一所述过孔区域内，所述第二过孔在所述衬底基板上的正投影位于所述第三过孔在所述衬底基板上的正投影范围内，所述第一导电层和所述第二导电层通过所述第一过孔电连接，所述第二导电层和所述第二偏置电压线通过所述第二过孔和所述第三过孔电连接。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，还包括：
设置在所述光电转换器件和所述平坦层之间的第二钝化层，所述第二过孔贯穿所述第二钝化层和所述第一钝化层。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，还包括：设置在所述第一偏置电压线背离所述衬底基板一侧的屏蔽层，以及设置在所述第一偏置电压线和所述屏蔽层之间的第三钝化层；所述屏蔽层覆盖所述第一交叠区域，每一所述过孔区域还包括贯穿所述第三钝化层的至少一个第四过孔，所述屏蔽层通过所述第四过孔与所述第二偏置电压线电连接。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，在同一所述过孔区域内，所述第一过孔在所述衬底基板上的正投影位于所述第三过孔在所述衬底基板上的正投影范围内，所述第一过孔和所述第二过孔沿所述第一交叠区域的延伸方向交替设置，所述第三过孔在所述衬底基板上的正投影位于所述第四过孔在所述衬底基板上的正投影范围内。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，所 述第一过孔的孔径大于所述第二过孔的孔径。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，在同一所述过孔区域内，所述第一过孔在所述衬底基板上的正投影与所述第三过孔在所述衬底基板上的正投影不交叠，所述第四过孔在所述衬底基板上的正投影与所述第三过孔在所述衬底基板上的正投影不交叠。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，所述第一过孔、所述第二过孔和所述第四过孔呈阵列排布。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，所述第一交叠区域还包括与所述过孔区域间隔设置的透光区域，所述透光区域包括贯穿所述第一导电层的第一通孔、贯穿所述第二导电层的第二通孔以及贯穿所述第二偏置电压线的第三通孔，所述第一通孔、所述第二通孔和所述第三通孔为套孔。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，所述第一通孔、所述第二通孔和所述第三通孔在所述衬底基板上的正投影面积依次减小。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，所述过孔区域与所述透光区域交替设置。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，所述薄膜晶体管包括层叠设置的栅极、栅绝缘层、有源层、所述源极和漏极，所述补偿电极与所述源极同层设置，所述介质层为所述层间绝缘层。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，所述薄膜晶体管包括层叠设置的栅极、栅绝缘层、有源层、所述源极和漏极，所述补偿电极与所述栅极同层设置，所述介质层为所述层间绝缘层和所述栅绝缘层。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，所述探测区域还包括绝缘交叉设置的第一信号线和第二信号线，每一条所述第二信号线与相邻两列所述像素单元内薄膜晶体管的漏极电连接，每一行所述 像素单元内薄膜晶体管的栅极分别交替的与位于对应行所述像素单元内两侧的两条所述第一信号线电连接；其中，
每相邻两条所述第二信号线之间的两列所述补偿电极为一组，每一组中对应的相邻两列所述像素单元之间间隙处设置有一条补偿线，所述补偿线延伸至所述周边区域，所述补偿线与两侧的所述补偿电极同层设置且电连接；每一组所述补偿电极对应两个所述第一导电层。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，所述第一过孔还贯穿所述栅绝缘层。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，所述探测区域还包括绝缘交叉设置的第一信号线和第二信号线，每一条所述第二信号线与一列所述像素单元内薄膜晶体管的漏极电连接，每一条所述第一信号线与一行所述像素单元内薄膜晶体管的栅极电连接；其中，
沿所述过孔区域的排列方向设置的多个所述补偿电极之间依次串联，所述第一导电层与串联的所述补偿电极中最靠近所述第一导电层的补偿电极电连接。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，所述第一信号线或所述第二信号线延伸至所述周边区域，所述第二偏置电压线与所述第一信号线或所述第二信号线在所述衬底基板上的正投影交叠区域具有间隔设置的多个第一镂空结构，所述屏蔽层与所述第一信号线或所述第二信号线在所述衬底基板上的正投影交叠区域具有间隔设置的多个第二镂空结构。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，所述第一镂空结构在所述衬底基板上的正投影和所述第二镂空结构在所述衬底基板上的正投影部分交叠。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，所述第一交叠区域的宽度与所述像素单元的宽度之间的比值为50％～75％，所述第一交叠区域的长度为所述像素单元的长度的2～6倍。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，在所述第一偏置电压线与所述第二偏置电压线连接处，所述第二偏置电压线的宽度大于所述第一偏置电压线的宽度。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，在所述第一导电层和所述补偿电极的连接处，所述第一导电层的宽度大于所述补偿电极的宽度。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，所述第一偏置电压线在所述衬底基板上的正投影与所述像素单元在所述衬底基板上的正投影相互交叠。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，所述第一偏置电压线在所述衬底基板上的正投影位于所述像素单元和所述第二信号线在所述衬底基板上的正投影之间。
相应地，本公开实施例还提供了一种平板探测器，包括本公开实施例提供的上述任一项所述的探测基板。
附图说明
图1为本公开提供的一种探测基板的平面示意图；
图2为图1中沿CC’方向的一种截面示意图；
图3为图1中沿CC’方向的又一种截面示意图；
图4为图1中沿CC’方向的又一种截面示意图；
图5为本公开提供的一种探测基板的具体平面示意图；
图6为本公开提供的又一种探测基板的具体平面示意图；
图7为本公开提供的又一种探测基板的具体平面示意图；
图8为本公开提供的又一种探测基板的具体平面示意图；
图9为图5中虚线框EE内的放大示意图；
图10A为图9中沿DD’方向的一种截面示意图；
图10B为图9中沿DD’方向的又一种截面示意图；
图11为图5所示的方案中第一导电层和补偿电极的平面示意图；
图12A为周边区域内第一导电层的平面示意图；
图12B为周边区域内第二导电层的平面示意图；
图12C为周边区域内第二偏置电压线的平面示意图；
图12D为周边区域内屏蔽层的平面示意图；
图13为图6所示的方案中第一导电层和补偿电极的平面示意图；
图14为图7中沿NN’方向的截面示意图；
图15为图5、图6、图7和图8中屏蔽层的局部平面示意图；
图16为本公开实施例图2-图8中增加补偿电容后的等效电路示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元 件或具有相同或类似功能的元件。
随着半导体制造工艺的不断进步和对图像分辨率要求的不断提高，平板探测器的像素单元尺寸日趋减小，然而小尺寸的像素单元不可避免的需要减少光电转换器件的有效面积，进而降低光电转换器件上的电容，电容的减少又会降低光电转换器件上下电极间的存储电荷能力，最终导致平板探测器实际使用过程中存在输出的信号动态范围偏低的问题，严重制约了采集图像的细节呈现能力。
为了解决上述问题，本公开提供了一种探测基板，如图1所示，包括衬底基板1，衬底基板1具有探测区域AA和位于探测区域AA外围的周边区域BB，探测区域AA包括阵列分布的多个像素单元P；如图2-图4所示，图2为图1中沿CC’方向的一种截面示意图，图3为图1中沿CC’方向的又一种截面示意图，图4为图1中沿CC’方向的又一种截面示意图，像素单元P包括：
薄膜晶体管2，设置在衬底基板1的一侧；
光电转换器件3，设置在薄膜晶体管2背离衬底基板1的一侧，光电转换器件3的底电极31与薄膜晶体管2的源极21电连接；
第一偏置电压线4，设置在光电转换器件3背离衬底基板1的一侧，第一偏置电压线4与光电转换器件3的顶电极32电连接；
补偿电容5，补偿电容5包括：底电极31，设置在底电极31面向衬底基板1一侧的介质层51，以及设置在介质层51面向衬底基板1一侧的补偿电极52；
如图5-图8所示，图5-图8分别为探测基板的几种平面结构示意图，该探测基板在周边区域BB包括：与补偿电极52同层设置的多个第一导电层6，以及与第一偏置电压线4同层设置的第二偏置电压线7；至少一个第一导电层6与至少一列补偿电极52电连接，第二偏置电压线7与第一偏置电压线4电连接，且第一导电层6和第二偏置电压线7电连接。
本公开实施例提供的上述探测基板，通过在像素单元内形成与光电转换器件的底电极共用的补偿电容，补偿电容与光电转换器件的顶电极和底电极 形成的存储电容相当于并联，从而增大光电转换器件的电容，因此本公开能够在不损失分辨率的前提下，增加像素单元的电荷存储容量，提高平板探测器输出信号的动态范围；并且，该补偿电容的补偿电极并非在像素单元内与第一偏置电压线电连接，而是在周边区域设置与补偿电极同层且电连接的第一导电层以及与第一偏置电压线同层且电连接的第二偏置电压线，然后在周边区域将第一导电层和第二偏置电压线电连接，这样相当于补偿电极是在周边区域与第一偏置电压线电连接，从而节省了像素单元内的打孔空间，避免了高分辨率产品的光电转换器件填充率的进一步损失。
需要说明的是，上述提及的与补偿电极52同层设置的多个第一导电层6，这里的同层是指：补偿电极52和第一导电层6两个膜层是同一层，补偿电极52和第一导电层6两个膜层是在同一工序下制备，并且补偿电极52和第一导电层6两个膜层在结构上，主体部分位于同一平面。
需要说明的是，上述提及的与第一偏置电压线4同层设置的第二偏置电压线7，这里的同层是指：第一偏置电压线4和第二偏置电压线7两个膜层是同一层，第一偏置电压线4和第二偏置电压线7两个膜层是在同一工序下制备，并且第一偏置电压线4和第二偏置电压线7两个膜层在结构上，主体部分位于同一平面。
在具体实施时，在本公开实施例提供的上述探测基板中，如图2-图8所示，薄膜晶体管2包括层叠设置的栅极22、栅绝缘层23、有源层24、源极21和漏极25，光电转换器件3还包括位于底电极31和顶电极之间的光电转换层33。具体地，光电转换层33将光信号转化为电信号，底电极31用于传导光电转换层33经光照后形成的电信号，底电极31和顶电极32之间存在正对面积，两者之间形成存储电容，并且本公开还增加了补偿电容5，增大了光电转换器件3的电容，这样经过光电转换层33转换后的电信号可以存储在上述存储电容和补偿电容5中，提高探测基板输出信号的动态范围。在探测基板工作时，例如通过第一偏置电压线4向顶电极32施加-5～-10V的电压，使光电转换层33工作在负偏压下，光电转换层33产生不同的电信号，该电信 号存储在底电极31内，底电极31内存储的电信号通过薄膜晶体管2传输至外部IC，以保存图像数据。
可选地，光电转换层33可以为PN结构或PIN结构。具体的，PIN结构包括N型掺杂的N型半导体层、不掺杂的本征半导体层I和P型掺杂的P型半导体层。本征半导体层I的厚度可以大于P型半导体层和N型半导体层的厚度。
另外，顶电极32在衬底基板1上的正投影位于光电转换层33在衬底基板1上的正投影内，即顶电极32的面积稍小于光电转换层33的面积，这样可减小光电转换层33的侧壁由于刻蚀时损伤而造成的漏电流。
可选地，可由钼、铝、银、铜、钛、铂、钨、钽、氮化钽、其合金及其组合或其它合适的材料形成底电极31；并可由铟锡氧化物(ITO)或铟锌氧化物(IZO)或其它合适的透明材料形成顶电极32，以提高光线透射效率。
在具体实施时，在本公开实施例提供的上述探测基板中，如图2-图4所示，还包括：
层间绝缘层8，层间绝缘层8设置在薄膜晶体管2和光电转换器件3之间；
平坦层10，平坦层10设置在光电转换器件3和第一偏置电压线4之间；
第一钝化层11，第一钝化层11设置在平坦层10和第一偏置电压线4之间；其中，底电极31通过贯穿层间绝缘层8的第五过孔V5与源极21电连接。
在具体实施时，在本公开实施例提供的上述探测基板中，如图2-图4所示，还包括设置在光电转换器件3和平坦层10之间的第二钝化层9；其中，第一偏置电压线4通过依次贯穿第一钝化层11、平坦层10和第二钝化层9的第六过孔V6与光电转换器件的顶电极32电连接的。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，如图2和图4所示，补偿电极52可以与源极21同层设置，补偿电容5的介质层51即为层间绝缘层8。这样，只需要在形成源极21时改变原有的构图图形，即可通过一次构图工艺形成补偿电极52与源极21的图形，不用增加单独制备补偿电极52的工艺，可以简化制备工艺流程，节省生产成本，提高生产效 率。
在一种可能的实现方式中，在本公开实施例提供的上述探测基板中，如图3所示，补偿电极52还可以与栅极22同层设置，补偿电容5的介质层51即为层间绝缘层8和栅绝缘层23。这样，只需要在形成栅极22时改变原有的构图图形，即可通过一次构图工艺形成补偿电极52与栅极22的图形，不用增加单独制备补偿电极52的工艺，可以简化制备工艺流程，节省生产成本，提高生产效率。另外，相比于图2和图4所示的补偿电容5，图3所示的补偿电容5的介质层51的厚度更厚，这样对于同样面积的补偿电极52，图3所示的补偿电容5的电容值相比图2和图4所示的电容值增加了大约50％左右，电容值增加的具体大小需视栅绝缘层23的厚度而定。并且，还可以通过调节层间绝缘层8和栅绝缘层23的厚度来调节电容值的大小。
下面以图2所示的结构为例，对补偿电极52和第一偏置电压线4通过在周边区域BB电连接进行详细介绍。
在具体实施时，位于周边区域BB的第二偏置电压线7和第一导电层6之间一般通过过孔连接，由于第二偏置电压线7和第一导电层6之间包括多层其它导电膜层以及绝缘膜层，为了避免同一过孔太深导致第二偏置电压线7和第一导电层6之间电连接不良，在本公开实施例提供的上述探测基板中，如图5和图6所示，探测基板在周边区域BB还包括设置在第一导电层6和第二偏置电压线7之间的多个第二导电层12，多个第二导电层12相互间隔，第二导电层12可以与图2中的底电极31同层设置；第一导电层6和第二偏置电压线7通过第二导电层12电连接。这样第二导电层12可以作为第一导电层6和第二偏置电压线7之间的搭接膜层，从而可以避免第二偏置电压线7和第一导电层6之间出现电连接不良的问题。
需要说明的是，上述提及的第二导电层12可以与图2中的底电极31同层设置，这里的同层是指：第二导电层12和底电极31两个膜层是同一层，第二导电层12和底电极31两个膜层是在同一工序下制备，并且第二导电层12和底电极31两个膜层在结构上，主体部分位于同一平面。
在具体实施时，在本公开实施例提供的上述探测基板中，如图5所示，一列补偿电极52对应设置至少一个第一导电层6和至少一个第二导电层12，图5是以一列补偿电极52对应设置一个第一导电层6和一个第二导电层12为例，第一导电层6、第二导电层12和第二偏置电压线7三者之间具有第一交叠区域A1，第一交叠区域A1包括至少一个过孔区域V，第一导电层6和第二导电层12通过至少一个过孔区域V电连接，第二导电层12和第二偏置电压线7通过至少一个过孔区域V电连接。这样第一导电层6和第二导电层12可以通过多个过孔区域V电连接，第二导电层12和第二偏置电压线7可以通过多个过孔区域V电连接，可以增大第一导电层6和第二导电层12之间的接触面积，以及增大第二导电层12和第二偏置电压线7之间的接触面积，从而可以降低第一导电层6、第二导电层12和第二偏置电压线7的电阻，提高平板探测器的电学性能。
在具体实施时，在本公开实施例提供的上述探测基板中，如图5、图9和图10A所示，图9为图5中虚线框EE内的放大示意图，图10A为图9中沿DD’方向的一种截面示意图，过孔区域V包括：贯穿层间绝缘层8的至少一个第一过孔V1(以两个为例，还可以为一个或更多个)，贯穿第一钝化层11的至少一个第二过孔V2(以两个为例，还可以为一个或更多个)，以及贯穿平坦层10的至少一个第三过孔V3(以一个为例)；
在同一过孔区域V内，第二过孔V2在衬底基板1上的正投影位于第三过孔V3在衬底基板1上的正投影范围内，第一导电层6和第二导电层12通过第一过孔V1电连接，第二导电层12和第二偏置电压线7通过第二过孔V2和第三过孔V3电连接。具体地，第一导电层6和第二导电层12通过多个第一过孔V1电连接，这样可以进一步增大第一导电层6和第二导电层12的接触面积，进一步降低第一导电层6和第二导电层12的接触电阻；另外，由于平坦层10的材料一般为树脂材料，起到平坦化的作用，厚度较厚(一般大于2μm)，若第二过孔V2和第三过孔V3的尺寸相同且正投影重叠设置，这样尺寸相同的第二过孔V2和第三过孔V3构成一深孔，容易导致第二偏置电压 线7在该深孔处断裂，因此为了便于第二偏置电压线7和第二导电层12良好搭接，将第三过孔V3设计成大孔，第二偏置电压线7就可以铺满第三过孔V3，并通过贯穿第一钝化层11的第二过孔V2电连接，从而可以防止由于过孔断差过大导致第二偏置电压线7断裂的问题；并且，第二过孔V2的数量可以设置为多个，从而可以进一步降低第二导电层12和第二偏置电压线7之间的接触电阻。
在具体实施时，如图10A所示，由于第一导电层6、第二导电层12和第二偏置电压线7的材料为金属材料，树脂材料与金属之间的粘附性较低，容易导致平坦层10及在其上制作的膜层从第二导电层12上脱落，因此在本公开实施例提供的上述探测基板中，如图10B所示，图10B为图9中沿DD’方向的又一种截面示意图，在平坦层10和第二导电层12之间保留第二钝化层9，第二钝化层9和第一钝化层11在第三过孔V3处直接接触，这样第二过孔V2贯穿第二钝化层9和第一钝化层11，可以避免膜层脱落的问题。
在具体实施时，为了保护探测基板表面以及屏蔽静电，在本公开实施例提供的上述探测基板中，如图2、图5、图9、图10A和图10B所示，还包括：设置在第一偏置电压线4背离衬底基板1一侧的屏蔽层13，以及设置在第一偏置电压线4和屏蔽层13之间的第三钝化层14；屏蔽层13覆盖第一交叠区域A1，每一过孔区域V还包括贯穿第三钝化层14的至少一个第四过孔V4，屏蔽层13通过第四过孔V4与第二偏置电压线7电连接。具体地，为了防止屏蔽层13影响透光率，屏蔽层13的材料一般为透明导电材料，例如氧化铟锡(ITO)、掺硼氧化锌(BZO)、掺铝氧化锌(AZO)等。
在具体实施时，在本公开实施例提供的上述探测基板中，如图5、图9、图10A和图10B所示，在同一过孔区域V内，第一过孔V1在衬底基板1上的正投影可以位于第三过孔V3在衬底基板1上的正投影范围内，第一过孔V1和第二过孔V2可以沿第一交叠区域A1的延伸方向交替设置，第三过孔V3在衬底基板1上的正投影位于第四过孔V4在衬底基板1上的正投影范围内。具体地，由于屏蔽层13采用的透明导电材料的电阻率较大，为了降低屏 蔽层13和第一偏置电压线4的接触电阻，因此将第四过孔V4设计成大孔；另外，通过将第一过孔V1和第二过孔V2均设计成正投影位于第三过孔V3的正投影范围内，这样在第四过孔V4尺寸一定的情况下，可以不用扩大过孔区域V的尺寸，第一交叠区域A1就可以有更多的空间设置更多数量的过孔区域V，更进一步降低导电层之间的接触电阻。
在具体实施时，为了实现第四过孔将第三过孔完全包裹，以及实现第三过孔将第二过孔完全包裹，在本公开实施例提供的上述探测基板中，如图10A和图10B所示，第三过孔V3和第四过孔V4在衬底基板1上的正投影边缘之间的距离大于2.5μm，第三过孔V3和第二过孔V2在衬底基板1上的正投影边缘之间的距离大于2.5μm。
可选地，第一过孔V1的尺寸为10μm*10μm，第二过孔V2的尺寸为8μm*8μm，第三过孔V3的尺寸为20μm*75μm，第四过孔V4的尺寸为25μm*80μm。
在具体实施时，如图2、图5、图9、图10A和图10B所示，为了简化制作工艺，第二过孔V2与第六过孔V6可以通过一次构图工艺制作，为了保证像素单元的填充率，第六过孔V6的刻蚀尺寸较小，因此第二过孔V2的尺寸也较小，由于层间绝缘层8的厚度一般比钝化层(9和11)的厚度大很多，为了保证第二导电层12和第一导电层6之间良好的接触电连接，需要将第一过孔V1的尺寸设计的比第二过孔V2的尺寸大，因此在本公开实施例提供的上述探测基板中，第一过孔V1的孔径D1大于第二过孔V2的孔径D2，例如孔径是指沿第一过孔V1和第二过孔V2排列方向上的长度。
可选地，第二钝化层9、第一钝化层11、第三钝化层14、栅绝缘层23、层间绝缘层8的材料可以为无机材料，例如氮化硅、氧化硅、氮氧化硅等。
在具体实施时，在本公开实施例提供的上述探测基板中，如图2所示，探测基板还包括：位于屏蔽层13背离衬底基板1一侧的闪烁体层15，闪烁体层15的材料为能够将X光转换为可见光的材料，其主要由闪烁体构成，闪烁体自身是一类吸收高能粒子或射线后能够发光的材料，通常在应用中将其加 工成晶体，称为闪烁晶体；本公开实施例对于闪烁体层15的闪烁晶体的具体材料不做限定，其可以为碘化铯(CsI)、钨酸镉、氟化钡、硫氧化钆(GOS)等。
具体地，本公开实施例提供的图2所示的探测基板的工作过程为：闪烁体层15在X射线的高能粒子的撞击下，将高能粒子的动能转变为光能而发出闪光(可见光信号)，通过光电转换器件3能够将该光信号转化为电信号，并通过薄膜晶体管2读出，以通过后续对信号的处理(包括放大、转换等)得到X射线影像。
在具体实施时，如图2所示，闪烁体层15在制作完之后，需要对闪烁体层封装，而封装层和衬底基板1之间一般通过UV胶固定，UV胶需要紫外光照射固化，由于封装层不透光，因此需要从衬底基板一侧照射UV胶，因此在本公开实施例提供的上述探测基板中，如图5和图9所示，第一交叠区域A1还包括与过孔区域V间隔设置的透光区域T，透光区域T包括贯穿第一导电层6的第一通孔H1、贯穿第二导电层12的第二通孔H2以及贯穿第二偏置电压线7的第三通孔H3，第一通孔H1、第二通孔H2和第三通孔H3为套孔。这样可以从衬底基板1一侧照射透光区域T，使UV胶固化，实现对闪烁体层15的封装。
在具体实施时，为了保证透光区域的透光率稳定，在本公开实施例提供的上述探测基板中，如图5和图9所示，第一通孔H1、第二通孔H2和第三通孔H3在衬底基板1上的正投影面积依次减小。
在具体实施时，为了保证UV胶和透光区域的对位精度，如图5和图9所示，第一通孔H1和第二通孔H2在衬底基板1上的正投影边缘之间的距离大于2.5μm，第二通孔H2和第三通孔H3在衬底基板1上的正投影边缘之间的距离大于2.5μm。
在具体实施时，在本公开实施例提供的上述探测基板中，如图5所示，过孔区域V与透光区域T可以交替设置，当然不限于此。这样可以设置多个过孔区域V和多个透光区域T，实现最大限度的降低接触电阻以及保证封装层对闪烁体层的封装效果。
具体地，图5的同一列是以设置3个过孔区域V及2个透光区域T为例，当然同一列过孔区域V和透光区域T的数量可以根据实际布线空间以及第一偏置电压线4的电阻要求进行调整。
在具体实施时，在本公开实施例提供的上述探测基板中，如图5所示，探测区域AA还包括绝缘交叉设置的第一信号线16(例如栅线)和第二信号线(例如数据线)，每一条第二信号线17与一列像素单元P内薄膜晶体管2的漏极25电连接，每一条第一信号线16与一行像素单元P内薄膜晶体管2的栅极22电连接；第一偏置电压线4在衬底基板1上的正投影可以与像素单元P在衬底基板1上的正投影相互交叠；其中，
沿过孔区域V的排列方向(例如像素单元的列方向)设置的多个补偿电极52之间依次串联，第一导电层6与串联的补偿电极52中最靠近第一导电层6的补偿电极52电连接。
为了清楚地示意第一导电层6和补偿电极52的连接关系，如图11所示，图11为图5所示的方案中第一导电层6和补偿电极52的平面示意图，图11相比于图5示意出了探测区域AA更多的像素单元，以示意一列补偿电极52之间依次串联。
在具体实施时，在本公开实施例提供的上述探测基板中，如图5所示，本公开实施例是以在第二信号线17(数据线)延伸方向的一侧实现第二偏置电压线7和第一导电层6电连接为例，第二信号线17一般延伸至周边区域BB与周边区域BB的驱动芯片(IC)电连接，为了降低数据线与第二偏置电压线7之间的交叠电容以及降低数据线与屏蔽层13之间的交叠电容，第二偏置电压线7与第二信号线17在衬底基板1上的正投影交叠区域具有间隔设置的多个第一镂空结构LK1，屏蔽层13与第二信号线17在衬底基板1上的正投影交叠区域具有间隔设置的多个第二镂空结构LK2。这样可以降低数据线与第二偏置电压线7之间的交叠电容以及降低数据线与屏蔽层13之间的交叠电容，从而避免相互干扰。
在具体实施时，在本公开实施例提供的上述探测基板中，如图5所示， 第一镂空结构LK1在衬底基板1上的正投影和第二镂空结构LK2在衬底基板1上的正投影部分交叠，当然，也可以重叠，还可以不交叠。
为了清楚的示意图5中位于周边区域BB内的第一导电层6、第二导电层12、第二偏置电压线7和屏蔽层13的结构，如图12A-图12D所示，图12A为周边区域BB内第一导电层6的平面示意图，图12B为周边区域BB内第二导电层12的平面示意图，图12C为周边区域BB内第二偏置电压线7的平面示意图，图12D为周边区域BB内屏蔽层13的平面示意图。
在具体实施时，在本公开实施例提供的上述探测基板中，如图5所示，第一交叠区域A1的宽度W1数值需根据像素单元P的尺寸进行搭配设计，一般来说宽度W1越宽越好，可选地，第一交叠区域A1的宽度W1与像素单元P的宽度W2之间的比值可以为50％～75％，例如比值为50％、55％、60％、65％、70％、75％等；第一交叠区域A1的长度L1数值需根据布线空间及第一偏置电压线4的电阻要求进行设计，可选地，第一交叠区域A1的长度L1可以为像素单元P的长度L2的2～6倍，例如第一交叠区域A1的长度L1为像素单元P的长度L2的2倍、2.5倍、3倍、3.5倍、4倍、4.5倍、5倍、5.5倍或6倍等。
在具体实施时，在本公开实施例提供的上述探测基板中，如图5所示，在第一偏置电压线4与第二偏置电压线7连接处，第二偏置电压线7的宽度W3大于第一偏置电压线4的宽度W4。这样第二偏置电压线7在周边区域BB做加宽设计，可以降低第二偏置电压线7的电阻，第一偏置电压线4在探测区域AA根据像素单元的设计需求进行缩减，以保证像素单元整体RC负载、像素填充率等满足规格要求。
在具体实施时，在本公开实施例提供的上述探测基板中，如图5所示，在第一导电层6和补偿电极52的连接处，第一导电层6的宽度W5大于补偿电极52的宽度W6。这样第一导电层6在周边区域BB做加宽设计，可以降低第一导电层6的电阻，补偿电极52在探测区域AA根据像素单元的设计需求进行缩减，以保证像素单元整体RC负载、像素填充率等满足规格要求。
在具体实施时，在本公开实施例提供的上述探测基板中，如图2、图6和图13所示，图6为图2所示的结构对应的周边区域的又一种平面示意图，图13为图6所示的方案中第一导电层6和补偿电极52的平面示意图，探测区域AA还包括绝缘交叉设置的第一信号线16(例如栅线)和第二信号线17(例如数据线)，每一条第二信号线17与相邻两列像素单元P内薄膜晶体管2的漏极25电连接，每一行像素单元P内薄膜晶体管2的栅极22分别交替的与位于对应行像素单元P内两侧的两条第一信号线16电连接；其中，
每相邻两条第二信号线17之间的两列补偿电极52为一组FF，每一组FF中对应的相邻两列像素单元P之间间隙处设置有一条补偿线53，补偿线53延伸至周边区域BB，补偿线53与两侧的补偿电极52同层设置且电连接；每一组补偿电极52对应两个第一导电层6。这样一条数据线同时连接其两侧的两列像素单元P，一条栅线只连接其相邻行像素中的半数像素单元P，这种设计不仅可以减少数据线的数量，减少驱动IC个数，降低成本，同时也可以为补偿线53提供走线空间，一条补偿线53可以连接其两侧的两列像素单元的补偿电极52，然后补偿线53通过延伸至周边区域BB与其两侧的两个第一导电层电连接。
需要说明的是，图6所示的结构对补偿电极52和第一偏置电压线4通过在周边区域BB的电连接设计与图5所示的电连接方式基本相同，图6与图5的主要区别如下：(1)图6在周边区域BB的同一列采用2个过孔区域V和2个透光区域T，相比于图5在周边区域BB的同一列采用3个过孔区域V及2个透光区域T，图6对第一交叠区域A1的长度L1进行了缩减，以适应窄边框产品要求；(2)图5和图6中像素单元P与栅线、数据线的连接关系不同(前面已介绍)；(3)图5和图6中补偿电极52与第一导电层6的电连接方式不同，过孔区域V及透光区域T的截面示意图与图10A或图10B相同；其它设计可以参见图5所示的结构。
需要说明的是，在本公开实施例提供的探测基板中，像素单元与栅线和数据线的连接关系不限于图5和图6所示的连接关系，还可以是其他连接关 系，只要能够采用本公开实施例提供的增加补偿电容的方式以及补偿电容是通过在周边区域与第一偏置电压线电连接，均属于本公开保护的范围。
下面以图3所示的结构为例，对补偿电极52和第一偏置电压线4通过在周边区域BB电连接进行详细介绍。
在具体实施时，在本公开实施例提供的上述探测基板中，如图3、图7和图14所示，图7为图3所示的结构对应在周边区域BB的平面结构示意图，图3为图7中沿GG’方向的截面示意图，图14为图7中沿NN’方向的截面示意图，补偿电极52与栅极22同层设置，补偿电容5的介质层51即为层间绝缘层8和栅绝缘层23，因此第一过孔V1还贯穿栅绝缘层23。
第一导电层6、第二导电层12、第二偏置电压线7和屏蔽层13之间的膜层位置关系以及各膜层的图形与图5所示的结构相同，第一导电层6、第二导电层12、第二偏置电压线7和屏蔽层13之间的过孔连接排布方式与图7相同。
在具体实施时，在本公开实施例提供的上述探测基板中，如图3、图7和图14所示，探测区域AA内像素单元P与栅线和数据线的连接关系与图5所示的连接关系相同，图7中的第一导电层6、第二导电层12和第二偏置电压线7在周边区域BB的位置与图5不同，图5是在第二信号线17(数据线)延伸方向的一侧设置第一导电层6、第二导电层12和第二偏置电压线7实现第二偏置电压线7和第一导电层6电连接，而图7是在第一信号线16(栅线)延伸方向的一侧设置第一导电层6、第二导电层12和第二偏置电压线7实现第二偏置电压线7和第一导电层6电连接，图7和图5中第二偏置电压线7和第一导电层6之间均是通过三个过孔区域V电连接，并且相邻两个过孔区域V之间设置透光区域T，图7中第二偏置电压线7与第二信号线17在衬底基板1上的正投影交叠区域也设置间隔的多个第一镂空结构LK1，屏蔽层13与第二信号线17在衬底基板1上的正投影交叠区域也设置间隔的多个第二镂空结构LK2。图7与图5的主要区别在于同一过孔区域V内第一过孔V1、第二过孔V2、第三过孔V3和第四过孔V4排列方式不同。
具体地，如图7和图14所示，在同一过孔区域V内，第一过孔V1在衬 底基板1上的正投影与第三过孔V3在衬底基板1上的正投影不交叠，第四过孔V4在衬底基板1上的正投影与第三过孔V3在衬底基板1上的正投影不交叠。可以看出，第三过孔V3仍采用大孔设计，便于金属搭接，防止由于过孔断差过大导致第二偏置电压线7断裂；第一过孔V1、第二过孔V2和第四过孔V4均采用小孔设计，这样可以在第三过孔V3的外侧设置更多数量的第一过孔V1和第四过孔V4，并且还可以设置更多数量的第二过孔V2，从而进一步降低金属层之间的接触电阻。
在具体实施时，在本公开实施例提供的上述探测基板中，如图7和图14所示，第一过孔V1、第二过孔V2和第四过孔V4可以均呈阵列排布，例如本公开是以第一过孔V1、第二过孔V2和第四过孔V4均为2*2方形排布为例，当然不限于此。
在具体实施时，在本公开实施例提供的上述探测基板中，如图7和图14所示，第四过孔V4可以挪至第一过孔V1的正上方，也可以是第一过孔V1挪至第四过孔V4的下方，也可以是第一过孔V1和第四过孔V4的位置交换。
在具体实施时，在本公开实施例提供的上述探测基板中，如图7所示，与图5中过孔区域V内的过孔采用长条排布，图7中过孔区域V内的过孔采用阵列排布，可以保证探测基板各个区域整体的平整度一致，有利于后续闪烁体层15的蒸镀。
在具体实施时，在本公开实施例提供的上述探测基板中，如图5、图6和图7所示，图5、图6和图7均是第一偏置电压线4在衬底基板1上的正投影与像素单元P在衬底基板1上的正投影相互交叠，这样第一偏置电压线4会占用一定的像素空间，降低像素填充率；为了进一步提高像素填充率，如图4和图8所示，图4为图8中沿MM’方向的截面示意图，第一偏置电压线4在衬底基板1上的正投影位于像素单元P和第二信号线17(数据线)在衬底基板1上的正投影之间。这样将第一偏置电压线4整体移到光电转换器件3外部，只有第六过孔V6与光电转换器件3有交叠，这样可以减少第一偏置电压线4对光电转换器件3的感光面积的遮挡，提高像素的填充率，进而可以提高探测基板的灵敏度及 信噪比。
需要说明的是，图8所示的结构中第一导电层6、第二导电层12、第二偏置电压线7和屏蔽层13之间的膜层位置关系以及各膜层的图形与图5所示的结构相同，第一导电层6、第二导电层12、第二偏置电压线7和屏蔽层13之间的过孔连接排布方式与图7相同。
在具体实施时，如图5、图6、图7和图8所示，将第二信号线17(数据线)延伸方向两侧的周边区域BB称为上边框和下边框，将第一信号线16(栅线)延伸方向两侧的周边区域BB称为左边框和右边框，目前图5、图6和图8中的第一导电层6和第二偏置电压线7是在上边框电连接，当然也可以是在下边框电连接，还可以是上、下边框均电连接；目前图7中的第一导电层6和第二偏置电压线7是在左边框电连接，当然也可以是在右边框电连接，还可以是左、右边框均电连接。
在具体实施时，如图5、图6、图7和图8所示，第一偏置电压线4在衬底基板1上的正投影与补偿电极52在衬底基板1上的正投影不交叠，当然也可以交叠，具体根据需要增加的补偿电容5的大小而设计补偿电极52的尺寸。
在具体实施时，如图5、图6、图7和图8所示，屏蔽层13在周边区域BB与数据线或栅线交叠的区域需要设置镂空结构来降低屏蔽层13与数据线或栅线的交叠电容；在探测区域AA，由于在屏蔽层13之后需要蒸镀闪烁体层，而屏蔽层13一般为ITO层，为了提高闪烁体层的蒸镀效果，需要将光电转换器件3上方的屏蔽层13去除，仅在光电转换器件3外围保留屏蔽层13，如图15所示，图15为图5、图6、图7和图8中屏蔽层13的局部平面示意图。
如图16所示，图16为本公开实施例图2-图8中增加补偿电容5后的等效电路示意图，可以看出，第二偏置电压线7与补偿电极52在周边区域BB电连接。
综上所述，本公开实施例提供的上述探测基板中增加的补偿电容，其一极与光电转换器件的底电极共用，另一极(补偿电极)与薄膜晶体管的源极或栅极同层设置，这样不用额外增加Mask数量及工艺过程；补偿电容的大小可以通过补偿电极与底电极交叠面积的大小来灵活调整，同时，补偿电极与 底电极之间的绝缘层(一般为SiNx或SiO2或本征a-Si或有机树脂材料等)的厚度、介电常数也可以通过工艺来进行调节，从而也达到调整补偿电容大小的目的；该补偿电容的补偿电极并非在像素单元内与第一偏置电压线打孔电连接，而是在周边区域通过设置转接的导电膜层实现与第一偏置电压线电连接，在探测区域外围打孔相对于在探测区域内打孔工艺难度要低很多，并且还节省了像素单元内的打孔空间，避免了高分辨率产品的光电转换器件填充率的进一步损失。
基于同一发明构思，本公开实施例还提供了一种平板探测器，包括本公开实施例提供的上述探测基板。由于该平板探测器解决问题的原理与前述一种探测基板相似，因此该平板探测器的实施可以参见前述探测基板的实施，重复之处不再赘述。
本公开实施例提供了一种探测基板及平板探测器，通过在像素单元内形成与光电转换器件的底电极共用的补偿电容，补偿电容与光电转换器件的顶电极和底电极形成的存储电容相当于并联，从而增大光电转换器件的电容，因此本公开能够在不损失分辨率的前提下，增加像素单元的电荷存储容量，提高平板探测器输出信号的动态范围；并且，该补偿电容的补偿电极并非在像素单元内与第一偏置电压线电连接，而是在周边区域设置与补偿电极同层且电连接的第一导电层以及与第一偏置电压线同层且电连接的第二偏置电压线，然后在周边区域将第一导电层和第二偏置电压线电连接，这样相当于补偿电极是在周边区域与第一偏置电压线电连接，从而节省了像素单元内的打孔空间，避免了高分辨率产品的光电转换器件填充率的进一步损失。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些 改动和变型在内。

Claims (26)

  1. 一种探测基板，其中，包括衬底基板，所述衬底基板具有探测区域和位于所述探测区域外围的周边区域，所述探测区域包括阵列分布的多个像素单元；所述像素单元包括：
    薄膜晶体管，设置在所述衬底基板的一侧；
    光电转换器件，设置在所述薄膜晶体管背离所述衬底基板的一侧，所述光电转换器件的底电极与所述薄膜晶体管的源极电连接；
    第一偏置电压线，设置在所述光电转换器件背离所述衬底基板的一侧，所述第一偏置电压线与所述光电转换器件的顶电极电连接；
    补偿电容，所述补偿电容包括：所述底电极，设置在所述底电极面向所述衬底基板一侧的介质层，以及设置在所述介质层面向所述衬底基板一侧的补偿电极；
    所述探测基板在所述周边区域包括：与所述补偿电极同层设置的多个第一导电层，以及与所述第一偏置电压线同层设置的第二偏置电压线；至少一个所述第一导电层与至少一列所述补偿电极电连接，所述第二偏置电压线与所述第一偏置电压线电连接，且所述第一导电层和所述第二偏置电压线电连接。
  2. 如权利要求1所述的探测基板，其中，所述探测基板在所述周边区域还包括设置在所述第一导电层和所述第二偏置电压线之间的多个第二导电层，所述多个第二导电层相互间隔，所述第二导电层与所述底电极同层设置；所述第一导电层和所述第二偏置电压线通过所述第二导电层电连接。
  3. 如权利要求2所述的探测基板，其中，一列所述补偿电极对应设置至少一个所述第一导电层和至少一个所述第二导电层，所述第一导电层、所述第二导电层和所述第二偏置电压线三者之间具有第一交叠区域，所述第一交叠区域包括至少一个过孔区域，所述第一导电层和所述第二导电层通过所述至少一个过孔区域电连接，所述第二导电层和所述第二偏置电压线通过所述 至少一个过孔区域电连接。
  4. 如权利要求3所述的探测基板，其中，还包括：
    层间绝缘层，所述层间绝缘层设置在所述薄膜晶体管和所述光电转换器件之间；
    平坦层，所述平坦层设置在所述光电转换器件和所述第一偏置电压线之间，
    第一钝化层，所述第一钝化层设置在所述平坦层和所述第一偏置电压线之间；
    其中，所述过孔区域包括：贯穿所述层间绝缘层的至少一个第一过孔，贯穿所述第一钝化层的至少一个第二过孔，以及贯穿所述平坦层的至少一个一个第三过孔；
    在同一所述过孔区域内，所述第二过孔在所述衬底基板上的正投影位于所述第三过孔在所述衬底基板上的正投影范围内，所述第一导电层和所述第二导电层通过所述第一过孔电连接，所述第二导电层和所述第二偏置电压线通过所述第二过孔和所述第三过孔电连接。
  5. 如权利要求4所述的探测基板，其中，还包括：
    设置在所述光电转换器件和所述平坦层之间的第二钝化层，所述第二过孔贯穿所述第二钝化层和所述第一钝化层。
  6. 如权利要求4或5所述的探测基板，其中，还包括：设置在所述第一偏置电压线背离所述衬底基板一侧的屏蔽层，以及设置在所述第一偏置电压线和所述屏蔽层之间的第三钝化层；所述屏蔽层覆盖所述第一交叠区域，每一所述过孔区域还包括贯穿所述第三钝化层的至少一个第四过孔，所述屏蔽层通过所述第四过孔与所述第二偏置电压线电连接。
  7. 如权利要求6所述的探测基板，其中，在同一所述过孔区域内，所述第一过孔在所述衬底基板上的正投影位于所述第三过孔在所述衬底基板上的正投影范围内，所述第一过孔和所述第二过孔沿所述第一交叠区域的延伸方向交替设置，所述第三过孔在所述衬底基板上的正投影位于所述第四过孔在 所述衬底基板上的正投影范围内。
  8. 如权利要求7所述的探测基板，其中，所述第一过孔的孔径大于所述第二过孔的孔径。
  9. 如权利要求6所述的探测基板，其中，在同一所述过孔区域内，所述第一过孔在所述衬底基板上的正投影与所述第三过孔在所述衬底基板上的正投影不交叠，所述第四过孔在所述衬底基板上的正投影与所述第三过孔在所述衬底基板上的正投影不交叠。
  10. 如权利要求9所述的探测基板，其中，所述第一过孔、所述第二过孔和所述第四过孔呈阵列排布。
  11. 如权利要求3-10任一项所述的探测基板，其中，所述第一交叠区域还包括与所述过孔区域间隔设置的透光区域，所述透光区域包括贯穿所述第一导电层的第一通孔、贯穿所述第二导电层的第二通孔以及贯穿所述第二偏置电压线的第三通孔，所述第一通孔、所述第二通孔和所述第三通孔为套孔。
  12. 如权利要求11所述的探测基板，其中，所述第一通孔、所述第二通孔和所述第三通孔在所述衬底基板上的正投影面积依次减小。
  13. 如权利要求11所述的探测基板，其中，所述过孔区域与所述透光区域交替设置。
  14. 如权利要求4-13任一项所述的探测基板，其中，所述薄膜晶体管包括层叠设置的栅极、栅绝缘层、有源层、所述源极和漏极，所述补偿电极与所述源极同层设置，所述介质层为所述层间绝缘层。
  15. 如权利要求4-13任一项所述的探测基板，其中，所述薄膜晶体管包括层叠设置的栅极、栅绝缘层、有源层、所述源极和漏极，所述补偿电极与所述栅极同层设置，所述介质层为所述层间绝缘层和所述栅绝缘层。
  16. 如权利要求14或15所述的探测基板，其中，所述探测区域还包括绝缘交叉设置的第一信号线和第二信号线，每一条所述第二信号线与相邻两列所述像素单元内薄膜晶体管的漏极电连接，每一行所述像素单元内薄膜晶体管的栅极分别交替的与位于对应行所述像素单元内两侧的两条所述第一信 号线电连接；其中，
    每相邻两条所述第二信号线之间的两列所述补偿电极为一组，每一组中对应的相邻两列所述像素单元之间间隙处设置有一条补偿线，所述补偿线延伸至所述周边区域，所述补偿线与两侧的所述补偿电极同层设置且电连接；每一组所述补偿电极对应两个所述第一导电层。
  17. 如权利要求15所述的探测基板，其中，所述第一过孔还贯穿所述栅绝缘层。
  18. 如权利要求14或15所述的探测基板，其中，所述探测区域还包括绝缘交叉设置的第一信号线和第二信号线，每一条所述第二信号线与一列所述像素单元内薄膜晶体管的漏极电连接，每一条所述第一信号线与一行所述像素单元内薄膜晶体管的栅极电连接；其中，
    沿所述过孔区域的排列方向设置的多个所述补偿电极之间依次串联，所述第一导电层与串联的所述补偿电极中最靠近所述第一导电层的补偿电极电连接。
  19. 如权利要求16或18所述的探测基板，其中，所述第一信号线或所述第二信号线延伸至所述周边区域，所述第二偏置电压线与所述第一信号线或所述第二信号线在所述衬底基板上的正投影交叠区域具有间隔设置的多个第一镂空结构，所述屏蔽层与所述第一信号线或所述第二信号线在所述衬底基板上的正投影交叠区域具有间隔设置的多个第二镂空结构。
  20. 如权利要求19所述的探测基板，其中，所述第一镂空结构在所述衬底基板上的正投影和所述第二镂空结构在所述衬底基板上的正投影部分交叠。
  21. 如权利要求3-20任一项所述的探测基板，其中，所述第一交叠区域的宽度与所述像素单元的宽度之间的比值为50％～75％，所述第一交叠区域的长度为所述像素单元的长度的2～6倍。
  22. 如权利要求1-21任一项所述的探测基板，其中，在所述第一偏置电压线与所述第二偏置电压线连接处，所述第二偏置电压线的宽度大于所述第一偏置电压线的宽度。
  23. 如权利要求1-22任一项所述的探测基板，其中，在所述第一导电层和所述补偿电极的连接处，所述第一导电层的宽度大于所述补偿电极的宽度。
  24. 如权利要求1-23任一项所述的探测基板，其中，所述第一偏置电压线在所述衬底基板上的正投影与所述像素单元在所述衬底基板上的正投影相互交叠。
  25. 如权利要求1-23任一项所述的探测基板，其中，所述第一偏置电压线在所述衬底基板上的正投影位于所述像素单元和所述第二信号线在所述衬底基板上的正投影之间。
  26. 一种平板探测器，其中，包括如权利要求1-25任一项所述的探测基板。
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