WO2023208135A1 - 一种服务器及其服务器管理系统 - Google Patents

一种服务器及其服务器管理系统 Download PDF

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Publication number
WO2023208135A1
WO2023208135A1 PCT/CN2023/091301 CN2023091301W WO2023208135A1 WO 2023208135 A1 WO2023208135 A1 WO 2023208135A1 CN 2023091301 W CN2023091301 W CN 2023091301W WO 2023208135 A1 WO2023208135 A1 WO 2023208135A1
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Prior art keywords
cpu
server
management system
bmc
interface
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PCT/CN2023/091301
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English (en)
French (fr)
Inventor
田硕
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苏州元脑智能科技有限公司
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Publication of WO2023208135A1 publication Critical patent/WO2023208135A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0042—Universal serial bus [USB]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • This application relates to the field of servers, and in particular to a server management system and a server.
  • the server management unit has been included in the server motherboard. Modularizing the server management unit and separating it from the server motherboard has obvious advantages. As server CPU technology continues to be updated and iterated, server applications continue to innovate. In the future, CPU (Central Processing Unit, central processing unit) The integration of the Southbridge chip and the CPU will result in the removal of low-speed interfaces such as USB (Universal Serial Bus). The application of CPU partitioning can allow the two CPUs to run the operating system independently. Faced with this new type of CPU design , there is a lack of a mature server management system in the existing technology.
  • CPU Central Processing Unit, central processing unit
  • the purpose of this application is to provide a server management system.
  • the server management system in this application can be suitable for CPU partition applications and remove the USB interface in future solutions. It has a simple structure and strong stability; another purpose of this application
  • the object is to provide a server including the above server management system.
  • the server management system in this application can be suitable for CPU partitioning applications and is a future solution that removes the USB interface. It has a simple structure and strong stability.
  • this application provides a server management system, including:
  • the baseboard management control device is used to receive the PCIe (Peripheral Component Interconnect express, high-speed serial computer expansion bus standard) signal sent by the CPU through the strobe switch, and send the keyboard and mouse instructions received through the first USB interface to the current state of the strobe switch.
  • PCIe Peripheral Component Interconnect express, high-speed serial computer expansion bus standard
  • the USB controller connected to the baseboard management control device is used to convert USB signals and PCIe signals to and from each other, so as to realize communication between the CPU currently connected to the strobe switch and the first USB interface;
  • the strobe switches are respectively connected to the two CPUs of the server, the baseboard management control device and the USB controller, and are used to One set of PCIe signals of the designated CPU among the two CPUs is connected to the baseboard management control device, and the other set of PCIe signals is connected to the USB controller;
  • the first USB interface is respectively connected to the baseboard management control device and the USB controller.
  • the substrate management control device includes:
  • the BMC Baseboard Management Controller
  • ESPI Enhanced Serial Peripheral Interface
  • the keyboard and mouse commands received by the first USB interface are sent to the CPU currently connected to the strobe switch, and the startup information sent by one of the CPUs is received through its own ESPI interface;
  • the control module is connected to the BMC, the ESPI interface of another CPU, and the strobe switch respectively, and is used to process the startup information sent by the other CPU through the ESPI interface using a preset program, and is also used to control the status of the strobe switch;
  • the trusted root security management device is connected to the two CPUs and the BMC respectively, and is used to provide a verified startup program for the CPU and the BMC during the server power-on phase.
  • control module is also connected to the LVDS (Low Voltage Differential Signaling) interface of the motherboard;
  • the control module is also used to decouple the LVDS signals sent by the motherboard, coupled with multiple specified types of low-speed signals, and send them to the BMC, and to couple the multiple specified types of low-speed signals sent by the BMC into LVDS signals and then send them to the motherboard.
  • the server management system further includes:
  • a protocol conversion device connected to BMC's UART (Universal Asynchronous Receiver/Transmitter, Universal Asynchronous Receiver/Transmitter) interface, used to convert USB protocol and UART protocol;
  • UART Universal Asynchronous Receiver/Transmitter
  • the BMC is also used to output the UART signal received from the control module from the UART interface and send the UART signal sent by the protocol conversion device to the control module.
  • control module is also connected to the I3C (Improved Inter Integrated Circuit) interface of the CPU;
  • Control modules are also used for:
  • the gating switch includes:
  • the first end is connected to the first PCIe signal channels of the two CPUs respectively, and the second end is connected to the first two-select PCIe switch of the USB controller, which is used to connect one of the first PCIe signals under the control of the control module. to USB controller;
  • the first end is connected to the second PCIe signal channel of the two CPUs respectively, and the second end is connected to the second one of the BMC.
  • PCIe switch used to connect one of the second PCIe signals to the BMC under the control of the control module;
  • the first end is connected to the clock signals of the two CPUs respectively, and the second end is connected to the USB controller and the BMC respectively, and is used to send the clock signals of the two CPUs to the USB controller and the BMC respectively.
  • the server management system further includes a third USB interface connected to the USB controller;
  • the USB controller is used to perform mutual conversion between the USB signal and the PCIe signal, so as to realize communication between the CPU currently connected to the strobe switch and the first USB interface and the third USB interface respectively.
  • control module is a Field Programmable Gate Array (FPGA).
  • FPGA Field Programmable Gate Array
  • the trusted root security management device includes:
  • the trusted root security management module Cerberus which is connected to the two CPUs and BMC respectively, is used to provide verified startup procedures for the CPU and BMC during the server power-on phase;
  • the first CPU Flash is used to store the startup program of one of the CPUs
  • the second CPU Flash is used to store the startup program of another CPU
  • BMC Flash is used to store the BMC startup program.
  • this application also provides a server, including the above server management system.
  • This application provides a server management system.
  • the server management system in this application can assist two CPUs in starting, and can receive PCIe signals sent by the two CPUs to display the operating system interface, and can also receive the PCIe signals sent by the two CPUs to display the operating system interface.
  • the keyboard and mouse instructions are sent to the CPU currently connected to the strobe switch through the USB controller, thereby realizing the application of the keyboard and mouse, and when the USB controller performs mutual conversion between the USB signal and the PCIe signal, the connection with the PCIe signal can be realized through the first USB interface.
  • the communication between the CPUs currently connected by the strobe switch shows that this application can be applied to CPU partitioning applications and is a future solution that removes the USB interface, and has a simple structure and strong stability.
  • This application also provides a server, which has the same beneficial effects as the above server management system.
  • Figure 1 is a schematic structural diagram of a server management system provided by this application in some embodiments.
  • Figure 2 is a schematic structural diagram of the existing server management system
  • FIG. 3 is a schematic structural diagram of another server management system provided by this application in some embodiments.
  • the core of this application is to provide a server management system.
  • the server management system in this application can be suitable for CPU partition applications and remove the USB interface in future solutions. It has a simple structure and strong stability; another core of this application
  • the object is to provide a server including the above server management system.
  • the server management system in this application can be suitable for CPU partitioning applications and is a future solution that removes the USB interface. It has a simple structure and strong stability.
  • FIG. 1 is a schematic structural diagram of a server management system provided by this application in some embodiments.
  • the server management system includes:
  • the baseboard management control device 1 is used to receive the PCIe signal sent by the CPU through the strobe switch 3, and send the keyboard and mouse instructions received through the first USB interface 4 to the CPU that the strobe switch 3 is currently connected to.
  • the auxiliary strobe switch 3 is currently connected to the CPU. Connected CPU to start;
  • the USB controller 2 connected to the substrate management control device 1 is used to perform mutual conversion between USB signals and PCIe signals, so as to realize communication between the CPU currently connected to the strobe switch 3 and the first USB interface 4;
  • the strobe switch 3 is respectively connected to the two CPUs of the server, the baseboard management control device 1 and the USB controller 2, and is used to connect one set of PCIe signals of the designated CPU among the two CPUs to the baseboard management control device 1, Another set of PCIe signals is connected to USB controller 2;
  • the first USB interface 4 is connected to the substrate management control device 1 and the USB controller 2 respectively.
  • FIG 2 is a schematic structural diagram of an existing server management system.
  • the existing 2-way universal server motherboard contains two CPUs, CPU0 and CPU1.
  • CPU0 only needs to complete independent startup and run the operating system.
  • CPU1 is mostly used to expand computing and expand PCIe resources without running the operating system.
  • CPU1 is booted by CPU0 to complete startup.
  • the BMC chip participates in the startup process of CPU0.
  • the PCIe bus of CPU0 is connected to the PCIe controller of the BMC chip for operating system interface display output.
  • the ESPI bus of the CPU0 Southbridge chip is connected to the BMC chip to transmit CPU0 serial port information.
  • the CPU0 Southbridge chip The USB bus is connected to the BMC chip to implement keyboard and mouse applications, etc.
  • the BMC's UART interface is externally connected to a serial COM connector to output serial port information.
  • the BMC communicates with the FPGA through the SGPIO (Serial General Purpose Input/Output, serial general purpose input/output) bus. connected, and interconnected with the SGPIO bus of the motherboard through the FPGA in this module to realize the IO (Input/Output, input/output) interface expansion function.
  • SGPIO Serial General Purpose Input/Output, serial general purpose input/output
  • PFR Platinum Firmware Resilience, Platform Firmware Resilience
  • PFR FPGA will verify the CPU FLASH, BMC FLASH and other storage units to determine whether the system is Has a bootable status.
  • PFR technology mainly relies on logic, which is complex, and the PFR circuit signal integrity risk is high. These characteristics greatly increase the difficulty of development, production, and maintenance.
  • Existing servers can only remotely debug the CPU through the COM (cluster communication port) port or BMC.
  • the CPU partition application can allow the two CPUs to run the operating system independently), due to The new generation CPU no longer has a USB interface.
  • the two CPUs (CPU0, CPU1) of the server each have two PCIe buses connected to the new server management system.
  • the strobe switch 3 uniformly controls the channels of the two CPUs for a total of four PCIe buses. , the strobe switch 3 can connect the two PCIe buses of the currently working CPU to the baseboard management control device 1 and the USB controller respectively, for example:
  • the strobe switch 3 can connect the two PCIe buses of the CPU0 to the baseboard management control device 1 and the USB control respectively.
  • the CPU can send PCIe signals through the PCIe bus connected to the baseboard management control device 1.
  • the signal for example, can send relevant data of the operating system interface, so that the baseboard management control device 1 can perform display control of the operating system interface, and the USB controller 2 connected to the first USB interface 4 can perform mutual conversion between USB signals and PCIe signals. In this way, the first USB interface 4 can realize USB communication through the CPU currently connected to the USB controller 2 and the strobe switch 3 .
  • the signals of the keyboard and mouse devices can be sent to the base board through the first USB interface 4
  • the management control device 1 and the substrate management control device 1 can, after processing the keyboard and mouse instructions, send them to the CPU currently connected to the strobe switch 3 through the USB controller 2 and the strobe switch 3, so as to realize the application of the keyboard and mouse.
  • the baseboard management control device 1 can also assist the CPU currently connected to the strobe switch 3 to start, including providing a verified startup program for the CPU during the server startup phase, and receiving startup information sent by the CPU.
  • the server management system in some embodiments of the present application can also be compatible with existing CPUs, and has strong compatibility and versatility.
  • the server management system can assist two CPUs in starting, and can receive PCIe signals sent by the two CPUs to display the operating system interface, and can also receive the PCIe signals sent by the two CPUs to display the operating system interface.
  • the keyboard and mouse commands are sent to the CPU currently connected to the strobe switch through the USB controller, thereby realizing the application of keyboard and mouse, and when the USB controller performs mutual conversion between USB signals and PCIe signals, it can be implemented through the first USB interface
  • the communication between the CPUs currently connected to the strobe switch can be suitable for CPU partitioning applications and the future solution that removes the USB interface, and has a simple structure and strong stability.
  • Figure 3 is a schematic structural diagram of another server management system provided by the present application in some embodiments. Based on the above embodiments:
  • the substrate management control device 1 includes:
  • the baseboard management controller BMC connected to the ESPI interface of one of the CPUs is used to receive the PCIe signal sent by the CPU through the strobe switch 3 and send the keyboard and mouse instructions received through the first USB interface 4 to the current connection of the strobe switch 3
  • the CPU receives the startup information sent by one of the CPUs through its own ESPI interface;
  • the control module is connected to the BMC, the ESPI interface of another CPU and the strobe switch 3 respectively, and is used to process the startup information sent by the other CPU through the ESPI interface using a preset program, and is also used to control the state of the strobe switch 3;
  • the trusted root security management device is connected to the two CPUs and the BMC respectively, and is used to provide a verified startup program for the CPU and the BMC during the server power-on phase.
  • composition of BMC, control module and trusted root security management module has the advantages of simple structure, low cost and high stability.
  • the substrate management control device 1 may also have other compositions.
  • CPU0 transmits UART information to the BMC through the ESPI bus and outputs it through the COM interface of the BMC.
  • the ESPI bus speed is high and the UART bus speed is low.
  • ESPI transmits UART information, which greatly reduces the utilization of the ESPI bus.
  • the new model The server management system has been improved to support CPU partitioning applications.
  • ESPI mainly runs CPU startup information, improving CPU startup efficiency. Since the BMC chip only supports one ESPI interface, in this application, the ESPI of one of the CPUs (CPU0) can be connected to the ESPI interface of the BMC to participate in CPU0 startup.
  • the ESPI of CPU1 is connected to the control module. Through the control module Participate in the independent startup of CPU1.
  • control module can also control the state of the strobe switch 3, and can control the state of the strobe switch 3 according to the instructions sent by the BMC.
  • control module is also connected to the LVDS interface of the motherboard;
  • the control module is also used to decouple the LVDS (Low-Voltage Differential Signaling, low-voltage differential signal) signal sent by the motherboard and send it to the BMC.
  • the low-speed signal is coupled into an LVDS signal and sent to the motherboard.
  • Some low-speed signals interconnected between the BMC and the motherboard can be logically coupled to the LVDS bus for transmission, and then through the motherboard side.
  • the control module is decoupled, so the information interaction between the BMC module and the mainboard is completed through the LVDS bus, which can increase the signal transmission rate and reduce the number of BMC-mainboard interface signals.
  • the server management system further includes:
  • the protocol conversion device connected to the UART interface of the BMC is used to convert the USB protocol and the UART protocol;
  • the BMC is also used to output the UART signal received from the control module from the UART interface and send the UART signal sent by the protocol conversion device to the control module.
  • the UART signal logically decoupled from the control module is output through the UART interface of the BMC and connected to the second server through the protocol conversion device (UART to USB chip, USB UART BRIDGE in Figure 3)
  • the USB interface can communicate with the UART signal on the motherboard through the second USB interface.
  • control module is also connected to the I3C interface of the CPU;
  • Control modules are also used for:
  • control module is also connected to the I3C interface of the CPU, and the control module can connect the I3C signals of the CPU to the BMC so that the BMC can debug the CPU through the I3C signals.
  • the I3C signal of the CPU can also be directly connected to the second USB interface (in this case, the second USB interface can be a TYPEC connector).
  • the serial port information can be debugged through the TYPEC interface, and the serial port information can also be debugged through the TYPEC interface. I3C debugs the CPU and improves testing efficiency.
  • the strobe switch 3 includes:
  • the first end is connected to the first PCIe signal channels of the two CPUs respectively, and the second end is connected to the first two-select PCIe switch of the USB controller 2, which is used to connect one of the first PCIe signals under the control of the control module. Pass to USB controller 2;
  • the first end is connected to the second PCIe signal channels of the two CPUs respectively, and the second end is connected to the second PCIe switch of the BMC, which is used to connect one of the second PCIe signals to the BMC under the control of the control module. ;
  • the first end is connected to the clock signals of the two CPUs respectively, and the second end is connected to the USB controller 2 and the BMC respectively. It is used to send the clock signals of the two CPUs to the USB controller 2 and the BMC respectively. BMC.
  • the strobe switch 3 includes two 2-to-1 PCIe switches and one 2-to-2 logic switch, which has a simple structure and low cost.
  • the strobe switch 3 can also have other structures.
  • the server management system also includes a third USB interface connected to the USB controller 2;
  • the USB controller 2 is used to perform mutual conversion between USB signals and PCIe signals, so as to realize communication between the CPU currently connected to the strobe switch 3 and the first USB interface 4 and the third USB interface respectively.
  • the server also has more connection requirements for USB devices, therefore, multiple USB interfaces can be provided.
  • the first USB interface 4 can be an interface of the USB2.0 protocol
  • the third USB interface It can be an interface with USB3.0 or higher version protocol to improve user experience.
  • control module is an FPGA.
  • FPGA has the advantages of small size, high performance and low cost.
  • control module can also be of other types.
  • the trusted root security management device includes:
  • the trusted root security management module Cerberus which is connected to the two CPUs and BMC respectively, is used to provide verified startup procedures for the CPU and BMC during the server power-on phase;
  • the first CPU Flash is used to store the startup program of one of the CPUs
  • the second CPU Flash is used to store the startup program of another CPU
  • BMC Flash is used to store the BMC startup program.
  • Cerberus is a root-of-trust security management module based on ARM processing. It provides multiple SPI interfaces to the outside world and can complete the verification and recovery of CPU, BMC and other chips during the server power-on process.
  • the Cerberus solution avoids the stacking of logic switches in the PFR solution and reduces the difficulty of PCB design. It also greatly reduces the difficulty of logic development and improves production efficiency.
  • the trusted root security management device can also be of other types.
  • this application also provides a server, including the server management system as in the foregoing embodiments.

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Abstract

一种服务器及其服务器管理系统，属于服务器领域，用于对服务器进行管理。服务器管理系统可以辅助两个CPU进行启动，并且可以接收两个CPU发送的PCIe信号以便进行操作系统界面的显示，还可以将接收到的键鼠指令通过USB控制器(2)发送至选通开关(3)当前连通的CPU，从而实现键鼠的应用，且在USB控制器(2)进行USB信号与PCIe信号的相互转换的情况下，可以通过第一USB接口(4)实现与选通开关(3)当前连通的CPU间的通信，可以适用于CPU分区应用且移除了USB接口的未来方案，且结构简单，稳定性较强。

Description

一种服务器及其服务器管理系统
相关申请的交叉引用
本申请要求于2022年04月29日提交中国专利局，申请号为202210466930.0，申请名称为“一种服务器及其服务器管理系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及服务器领域，特别是涉及一种服务器管理系统和一种服务器。
背景技术
此前服务器管理单元一直包含在服务器主板中，将服务器管理单元模块化，从服务器主板中剥离出来优势明显，随着服务器CPU技术不断更新迭代，服务器应用不断创新，未来CPU(Central Processing Unit，中央处理器)南桥芯片与CPU融合，导致USB(Universal Serial Bus，通用串行总线)等低速接口会被移除，CPU分区应用可使得两路CPU独立运行操作系统，面对这种新型的CPU设计，现有技术中缺少一种成熟的服务器管理系统。
发明内容
本申请的目的是提供一种服务器管理系统，本申请中的服务器管理系统可以适用于CPU分区应用且移除了USB接口的未来方案，且结构简单，稳定性较强；本申请的另一目的是提供一种包括上述服务器管理系统的服务器，本申请中的服务器管理系统可以适用于CPU分区应用且移除了USB接口的未来方案，且结构简单，稳定性较强。
为解决上述技术问题，本申请提供了一种服务器管理系统，包括：
基板管理控制装置，用于通过选通开关接收CPU发送的PCIe(Peripheral Component Interconnect express，高速串行计算机扩展总线标准)信号，将通过第一USB接口接收到的键鼠指令发送至选通开关当前连通的CPU，辅助选通开关当前连通的CPU进行启动；
与基板管理控制装置连接的USB控制器，用于进行USB信号与PCIe信号的相互转换，以便实现选通开关当前连通的CPU与第一USB接口间的通信；
分别与服务器的两个CPU、基板管理控制装置以及USB控制器连接的选通开关，用于将 两个CPU中的指定CPU的其中一组PCIe信号接通至基板管理控制装置，另一组PCIe信号接通至USB控制器；
分别与基板管理控制装置以及USB控制器连接的第一USB接口。
在一些实施例中，基板管理控制装置包括：
与其中一个CPU的ESPI(Enhanced Serial Peripheral Interface，增强型串行外设接口)接口连接的BMC(Baseboard Management Controller，基板管理控制器)，用于通过选通开关接收CPU发送的PCIe信号，将通过第一USB接口接收到的键鼠指令发送至选通开关当前连通的CPU，通过自身的ESPI接口接收其中一个CPU发送的启动信息；
分别与BMC、另一个CPU的ESPI接口以及选通开关连接的控制模块，用于采用预设程序处理另一个CPU通过ESPI接口发送的启动信息，还用于控制选通开关的状态；
分别与两个CPU以及BMC连接的可信根安全管理装置，用于在服务器上电阶段为CPU以及BMC提供经过验证的启动程序。
在一些实施例中，控制模块还与主板的LVDS(Low Voltage Differential Signaling，低电压差分信号)接口连接；
控制模块还用于将主板发送的由多种指定类型的低速信号耦合成的LVDS信号解耦后发送至BMC，将BMC发送的多种指定类型的低速信号偶合成LVDS信号后发送至主板。
在一些实施例中，该服务器管理系统还包括：
与BMC的UART(Universal Asynchronous Receiver/Transmitter，通用异步收发传输器)接口连接的协议转换装置，用于进行USB协议与UART协议的转换；
与协议转换装置连接的第二USB接口；
则BMC还用于，将从控制模块接收到的UART信号从UART接口输出，将协议转换装置发送的UART信号发送至控制模块。
在一些实施例中，控制模块还与CPU的I3C(Improved Inter Integrated Circuit，改进的内部集成电路)接口连接；
控制模块还用于：
将CPU的I3C信号接通至BMC，以便BMC通过I3C信号对CPU进行调试。
在一些实施例中，选通开关包括：
第一端分别与两个CPU的第一PCIe信号通道连接，第二端与USB控制器连接的第一二选一PCIe开关，用于在控制模块的控制下将其中一路第一PCIe信号接通至USB控制器；
第一端分别与两个CPU的第二PCIe信号通道连接，第二端与BMC连接的第二二选一 PCIe开关，用于在控制模块的控制下将其中一路第二PCIe信号接通至BMC；
第一端分别与两个CPU的时钟信号连接，第二端分别与USB控制器以及BMC连接的二选二逻辑开关，用于将两个CPU的时钟信号均分别发送至USB控制器以及BMC。
在一些实施例中，该服务器管理系统还包括与USB控制器连接的第三USB接口；
则USB控制器用于，进行USB信号与PCIe信号的相互转换，以便实现选通开关当前连通的CPU分别与第一USB接口以及第三USB接口间的通信。
在一些实施例中，控制模块为FPGA(Field Programmable Gate Array，现场可编程逻辑门阵列)。
在一些实施例中，可信根安全管理装置包括：
分别与两个CPU以及BMC连接的可信根安全管理模块Cerberus，用于在服务器上电阶段为CPU以及BMC提供经过验证的启动程序；
第一CPU Flash，用于存储其中一个CPU的启动程序；
第二CPU Flash，用于存储另一个CPU的启动程序；
BMC Flash，用于存储BMC的启动程序。
为解决上述技术问题，本申请还提供了一种服务器，包括如上的服务器管理系统。
本申请提供了一种服务器管理系统，本申请中的服务器管理系统可以辅助两个CPU进行启动，并且可以将接收两个CPU发送的PCIe信号以便进行操作系统界面的显示，还可以将接收到的键鼠指令通过USB控制器发送至选通开关当前连通的CPU，从而实现键鼠的应用，且在USB控制器进行USB信号与PCIe信号的相互转换的情况下，可以通过第一USB接口实现与选通开关当前连通的CPU间的通信，可见本申请可以适用于CPU分区应用且移除了USB接口的未来方案，且结构简单，稳定性较强。
本申请还提供了一种服务器，具有如上服务器管理系统相同的有益效果。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对现有技术和实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请在一些实施例中提供的一种服务器管理系统的结构示意图；
图2为现有服务器管理系统的结构示意图；
图3为本申请在一些实施例中提供的另一种服务器管理系统的结构示意图。
具体实施方式
本申请的核心是提供一种服务器管理系统，本申请中的服务器管理系统可以适用于CPU分区应用且移除了USB接口的未来方案，且结构简单，稳定性较强；本申请的另一核心是提供一种包括上述服务器管理系统的服务器，本申请中的服务器管理系统可以适用于CPU分区应用且移除了USB接口的未来方案，且结构简单，稳定性较强。
为使本申请的一些实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本申请的一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
参考图1，图1为本申请在一些实施例中提供的一种服务器管理系统的结构示意图，该服务器管理系统包括：
基板管理控制装置1，用于通过选通开关3接收CPU发送的PCIe信号，将通过第一USB接口4接收到的键鼠指令发送至选通开关3当前连通的CPU，辅助选通开关3当前连通的CPU进行启动；
与基板管理控制装置1连接的USB控制器2，用于进行USB信号与PCIe信号的相互转换，以便实现选通开关3当前连通的CPU与第一USB接口4间的通信；
分别与服务器的两个CPU、基板管理控制装置1以及USB控制器2连接的选通开关3，用于将两个CPU中的指定CPU的其中一组PCIe信号接通至基板管理控制装置1，另一组PCIe信号接通至USB控制器2；
分别与基板管理控制装置1以及USB控制器2连接的第一USB接口4。
参考图2，图2为现有服务器管理系统的结构示意图。现有2路通用服务器主板包含CPU0，CPU1两个CPU，仅需要CPU0完成独立启动并运行操作系统即可，CPU1多用于扩展计算和扩展PCIe资源，无需运行操作系统，CPU1由CPU0引导完成启动。BMC芯片参与到CPU0启动过程中，其中CPU0的PCIe总线连接到BMC芯片的PCIe控制器用于操作系统界面显示输出，CPU0南桥芯片的ESPI总线连接到BMC芯片以传递CPU0串口信息，CPU0南桥芯片USB总线连接到BMC芯片以实现键盘鼠标应用等。BMC的UART接口外接串口COM连接器以输出串口信息。BMC通过SGPIO(Serial General Purpose Input/Output，串行通用输入/输出)总线与FPGA相 连，并通过本模块中的FPGA与主板的SGPIO总线进行互联，以实现IO(Input/Output，输入/输出)接口扩展功能。PFR(Platform Firmware Resilience，平台固件弹性)是当前广泛应用的安全启动技术，主要通过FPGA实现，在上电初始阶段，PFR FPGA会对CPU FLASH，BMC FLASH等存储单元进行校验，以判定系统是否具备可启动状态。现有方案中因为CPU0，CPU1，BMC芯片均有连接到FLASH的需求，就导致需要大量的2进1出逻辑开关进行通道选通。当前PFR方案，多个逻辑开关的引入大大增加了链路分支，造成信号完整性风险；PFR校验逻辑程序冗杂，不易开发，且会造成生产烧录时间冗长，大大降低生产效率。
当前CPU产品更新迭代迅速，未来CPU南桥芯片与CPU融合，导致USB等低速接口会被移除，现有USB方案无法适配新一代CPU。随着数据中心低能耗应用，可靠性运行的需求不断提高，CPU分区应用概念得以提出，现有服务器管理方案并不支持CPU分区应用。CPU分区应用可使得2路CPU独立运行系统，具备如下有点：
1，满足用户多系统需要；
2，实现操作系统1+1备份，当一路故障，系统可快速切换至另一路系统；
3，提高资源利用率，当用户单系统下配置不高时，原2路服务器运行单系统会造成CPU1资源浪费。
PFR技术主要依托逻辑完成，逻辑冗杂，且PFR电路信号完整性风险高，这些特点，大大提高了开发，生产，维护难度。现有服务器只能通过COM(cluster communication port)串行通讯端口)口或者BMC远程调试CPU。
考虑到如上背景技术中的技术问题，为了应对新型的CPU设计(CPU南桥芯片与CPU融合，导致USB等低速接口会被移除，CPU分区应用可使得两路CPU独立运行操作系统)，由于新一代CPU不再具备USB接口，服务器的两个CPU(CPU0，CPU1)各出两路PCIe总线连接到新的服务器管理系统，选通开关3统一控制两路CPU的共四路PCIe总线的通道，选通开关3可以将当前正在工作的CPU的两路PCIe总线分别接通到基板管理控制装置1以及USB控制器中，例如：
当其中的CPU0工作时，选通开关3便可以将CPU0的两路PCIe总线分别接通到基板管理控制装置1以及USB控制，其中，CPU可以通过连通到基板管理控制装置1的PCIe总线发送PCIe信号，例如可以发送操作系统界面的相关数据，以便基板管理控制装置1进行操作系统界面的显示控制，而连接有第一USB接口4的USB控制器2可以进行USB信号与PCIe信号的相互转换，如此一来，第一USB接口4便可以通过USB控制器2与选通开关3当前连通的CPU实现USB通信。
其中，为了实现服务器的键鼠功能，键鼠设备的信号可以通过第一USB接口4发送至基板 管理控制装置1，基板管理控制装置1在对键鼠指令处理后可以通过USB控制器2以及选通开关3将其发送至选通开关3当前连通的CPU，以便实现键鼠的应用。
在一些实施例中，基板管理控制装置1同样可以辅助选通开关3当前连通的CPU进行启动，包括在服务器启动阶段为CPU提供经过验证的启动程序，并且接收CPU发送的启动信息等。
由于选通开关3的存在，本申请在一些实施例中的服务器管理系统也可以兼容现有CPU，兼容性以及通用性较强。
本申请在一些实施例中提供了一种服务器管理系统，服务器管理系统可以辅助两个CPU进行启动，并且可以将接收两个CPU发送的PCIe信号以便进行操作系统界面的显示，还可以将接收到的键鼠指令通过USB控制器发送至选通开关当前连通的CPU，从而实现键鼠的应用，且在USB控制器进行USB信号与PCIe信号的相互转换的情况下，可以通过第一USB接口实现与选通开关当前连通的CPU间的通信，可以适用于CPU分区应用且移除了USB接口的未来方案，且结构简单，稳定性较强。
为了更好地对本申请实施例进行介绍，请参考图3，图3为本申请在一些实施例中提供的另一种服务器管理系统的结构示意图，在上述实施例的基础上：
在一些实施例中，基板管理控制装置1包括：
与其中一个CPU的ESPI接口连接的基板管理控制器BMC，用于通过选通开关3接收CPU发送的PCIe信号，将通过第一USB接口4接收到的键鼠指令发送至选通开关3当前连通的CPU，通过自身的ESPI接口接收其中一个CPU发送的启动信息；
分别与BMC、另一个CPU的ESPI接口以及选通开关3连接的控制模块，用于采用预设程序处理另一个CPU通过ESPI接口发送的启动信息，还用于控制选通开关3的状态；
分别与两个CPU以及BMC连接的可信根安全管理装置，用于在服务器上电阶段为CPU以及BMC提供经过验证的启动程序。
BMC、控制模块以及可信根安全管理模块的组成具有结构简单、成本低以及稳定性高等优点。
当然，除了上述组成外，基板管理控制装置1还可以为其他组成。
考虑到现有2路服务器，CPU0通过ESPI总线向BMC传递UART信息，并通过BMC的COM接口输出，ESPI总线速度高，UART总线速度低，ESPI传输UART信息大大降低了ESPI总线的利用率，新型服务器管理系统进行了改进，支持CPU分区应用后，ESPI主要运行CPU启动信息，提高 CPU启动效率，由于BMC芯片仅支持一个ESPI接口，因此本申请中可以将其中一个CPU(CPU0)的ESPI连接至BMC的ESPI接口以参与CPU0启动，CPU1的ESPI连接至控制模块，通过控制模块来参与CPU1的独立启动。
另外，控制模块还可以控制选通开关3的状态，可以为根据BMC发送的指令控制选通开关3的状态。
在一些实施例中，控制模块还与主板的LVDS接口连接；
控制模块还用于将主板发送的由多种指定类型的低速信号耦合成的LVDS(Low-Voltage Differential Signaling，低电压差分信号)信号解耦后发送至BMC，将BMC发送的多种指定类型的低速信号偶合成LVDS信号后发送至主板。
由于CPU的PCIe总线以及ESPI总线的引入，必然造成BMC与主板接口紧张，BMC与主板互联的一些低速信号，诸如I2C、UART以及GPIO等信号可以通过逻辑耦合到LVDS总线进行传输，再通过主板端的控制模块进行解耦合，故通过LVDS总线来完成BMC模块与主板的信息交互，可提高信号传输速率，也可降低BMC-主板接口信号数量。
在一些实施例中，该服务器管理系统还包括：
与BMC的UART接口连接的协议转换装置，用于进行USB协议与UART协议的转换；
与协议转换装置连接的第二USB接口；
则BMC还用于，将从控制模块接收到的UART信号从UART接口输出，将协议转换装置发送的UART信号发送至控制模块。
在本申请一些实施例的服务器管理系统中，从控制模块逻辑解耦的UART信号通过BMC的UART接口输出，通过协议转换装置(UART转USB芯片，图3中的USB UART BRIDGE)连接至第二USB接口，可以通过第二USB接口实现与主板上的UART信号的通信。
在一些实施例中，控制模块还与CPU的I3C接口连接；
控制模块还用于：
将CPU的I3C信号接通至BMC，以便BMC通过I3C信号对CPU进行调试。
为了使得BMC可以通过I3C信号对CPU进行调试，控制模块还与CPU的I3C接口连接，且控制模块可以将CPU的I3C信号接通至BMC，以便BMC通过I3C信号对CPU进行调试。
另外，值得一提的是，还可以将CPU的I3C信号直接连接至第二USB接口(这种情况下第二USB接口可以为TYPEC连接器)，通过TYPEC接口既可以调试串口信息，也可通过I3C调试CPU，提高了测试效率。
在一些实施例中，选通开关3包括：
第一端分别与两个CPU的第一PCIe信号通道连接，第二端与USB控制器2连接的第一二选一PCIe开关，用于在控制模块的控制下将其中一路第一PCIe信号接通至USB控制器2；
第一端分别与两个CPU的第二PCIe信号通道连接，第二端与BMC连接的第二二选一PCIe开关，用于在控制模块的控制下将其中一路第二PCIe信号接通至BMC；
第一端分别与两个CPU的时钟信号连接，第二端分别与USB控制器2以及BMC连接的二选二逻辑开关，用于将两个CPU的时钟信号均分别发送至USB控制器2以及BMC。
本申请在一些实施例中的选通开关3包括两个二选一PCIe开关，一个二选二逻辑开关，结构简单且成本较低。
当然，选通开关3还可以为其他结构。
在一些实施例中，该服务器管理系统还包括与USB控制器2连接的第三USB接口；
则USB控制器2用于，进行USB信号与PCIe信号的相互转换，以便实现选通开关3当前连通的CPU分别与第一USB接口4以及第三USB接口间的通信。
考虑到除了键鼠之外，服务器还具备更多的USB设备的连接需求，因此，可以提供多个USB接口，其中，第一USB接口4可以为USB2.0协议的接口，第三USB接口则可以为USB3.0或者更高版本协议的接口，以便提升用户体验。
在一些实施例中，控制模块为FPGA。
FPGA具有体积小、性能高以及成本低等优点。
当然，除了FPGA外，控制模块还可以为其他类型。
在一些实施例中，可信根安全管理装置包括：
分别与两个CPU以及BMC连接的可信根安全管理模块Cerberus，用于在服务器上电阶段为CPU以及BMC提供经过验证的启动程序；
第一CPU Flash，用于存储其中一个CPU的启动程序；
第二CPU Flash，用于存储另一个CPU的启动程序；
BMC Flash，用于存储BMC的启动程序。
Cerberus是一款基于ARM处理的可信根安全管理模块，对外提供多个SPI接口，在服务器上电过程中可完成CPU、BMC等芯片校验和恢复。Cerberus方案避免了PFR方案中逻辑开关的堆叠，降低了PCB设计难度，同样也大大减少了逻辑开发难度，提供了生产效率。
当然，除了上述结构外，可信根安全管理装置还可以为其他类型。
本申请在一些实施例中还提供了一种服务器，包括如前述实施例中的服务器管理系统。
对于本申请在一些实施例中提供的服务器的介绍请参照前述的服务器管理系统的实施例。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。还需要说明的是，在本说明书中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者设备中还存在另外的相同要素。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其他实施例中实现。因此，本申请将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (20)

  1. 一种服务器管理系统，其特征在于，包括：
    基板管理控制装置，用于通过选通开关接收中央处理器CPU发送的高速串行计算机扩展总线标准PCIe信号，将通过第一USB接口接收到的键鼠指令发送至所述选通开关当前连通的CPU，辅助所述选通开关当前连通的CPU进行启动；
    与所述基板管理控制装置连接的通用串行总线USB控制器，用于进行USB信号与PCIe信号的相互转换，以便实现所述选通开关当前连通的CPU与第一USB接口间的通信；
    分别与服务器的两个CPU、所述基板管理控制装置以及所述USB控制器连接的所述选通开关，用于将两个CPU中的指定CPU的其中一组PCIe信号接通至所述基板管理控制装置，另一组PCIe信号接通至所述USB控制器；
    分别与所述基板管理控制装置以及所述USB控制器连接的所述第一USB接口。
  2. 根据权利要求1所述的服务器管理系统，其特征在于，所述基板管理控制装置包括：
    与其中一个CPU的增强型串行外设接口ESPI接口连接的基板管理控制器BMC，用于通过选通开关接收CPU发送的PCIe信号，将通过第一USB接口接收到的键鼠指令发送至所述选通开关当前连通的CPU，通过自身的ESPI接口接收其中一个CPU发送的启动信息；
    分别与所述BMC、另一个CPU的ESPI接口以及所述选通开关连接的控制模块，用于采用预设程序处理另一个CPU通过ESPI接口发送的启动信息，还用于控制所述选通开关的状态；
    分别与两个CPU以及所述BMC连接的可信根安全管理装置，用于在服务器上电阶段为所述CPU以及所述BMC提供经过验证的启动程序。
  3. 根据权利要求2所述的服务器管理系统，其特征在于，所述控制模块还与主板的低电压差分信号LVDS接口连接；
    所述控制模块还用于将主板发送的由多种指定类型的低速信号耦合成的LVDS信号解耦后发送至所述BMC，将所述BMC发送的多种所述指定类型的低速信号偶合成LVDS信号后发送至主板。
  4. 根据权利要求3所述的服务器管理系统，其特征在于，该服务器管理系统还包括：
    与所述BMC的通用异步收发传输器UART接口连接的协议转换装置，用于进行USB协议与UART协议的转换；
    与所述协议转换装置连接的第二USB接口；
    则所述BMC还用于，将从所述控制模块接收到的UART信号从所述UART接口输出，将所述协议转换装置发送的UART信号发送至所述控制模块。
  5. 根据权利要求4所述的服务器管理系统，其特征在于，所述控制模块还与所述CPU的I3C接口连接；
    所述控制模块还用于：
    将所述CPU的改进的内部集成电路I3C信号接通至所述BMC，以便所述BMC通过I3C信号对所述CPU进行调试。
  6. 根据权利要求2所述的服务器管理系统，其特征在于，所述选通开关包括：
    第一端分别与两个CPU的第一PCIe信号通道连接，第二端与所述USB控制器连接的第一二选一PCIe开关，用于在所述控制模块的控制下将其中一路第一PCIe信号接通至所述USB控制器；
    第一端分别与两个CPU的第二PCIe信号通道连接，第二端与所述BMC连接的第二二选一PCIe开关，用于在所述控制模块的控制下将其中一路第二PCIe信号接通至所述BMC；
    第一端分别与两个CPU的时钟信号连接，第二端分别与所述USB控制器以及所述BMC连接的二选二逻辑开关，用于将两个CPU的时钟信号均分别发送至所述USB控制器以及所述BMC。
  7. 根据权利要求2所述的服务器管理系统，其特征在于，该服务器管理系统还包括与所述USB控制器连接的第三USB接口；
    则所述USB控制器用于，进行USB信号与PCIe信号的相互转换，以便实现所述选通开关当前连通的CPU分别与第一USB接口以及所述第三USB接口间的通信。
  8. 根据权利要求3所述的服务器管理系统，其特征在于，所述控制模块为现场可编程逻辑门阵列FPGA。
  9. 根据权利要求2至8任一项所述的服务器管理系统，其特征在于，所述可信根安全管理装置包括：
    分别与两个CPU以及所述BMC连接的可信根安全管理模块Cerberus，用于在服务器上电阶段为所述CPU以及所述BMC提供经过验证的启动程序；
    第一CPU Flash，用于存储其中一个CPU的启动程序；
    第二CPU Flash，用于存储另一个CPU的启动程序；
    BMC Flash，用于存储所述BMC的启动程序。
  10. 根据权利要求1所述的服务器管理系统，其特征在于，所述选通开关用于将当前正在工作的CPU的两路PCIe总线分别接通到所述基板管理控制装置和所述USB控制器中。
  11. 根据权利要求1所述的服务器管理系统，其特征在于，所述基板管理控制装置用于在服务器启动阶段，为CPU提供经过验证的启动程序。
  12. 根据权利要求2所述的服务器管理系统，其特征在于，所述控制模块用于为根据BMC发送的指令控制选通开关的状态。
  13. 根据权利要求5所述的服务器管理系统，其特征在于，所述控制模块，还用于将CPU的I3C信号直接连接至所述第二USB接口；所述第二USB接口为TYPEC连接器。
  14. 根据权利要求1所述的服务器管理系统，其特征在于，所述第一USB接口为USB2.0协议的接口。
  15. 根据权利要求1所述的服务器管理系统，其特征在于，所述第三USB接口为USB3.0。
  16. 一种服务器，其特征在于，包括如权利要求1至15任一项所述的服务器管理系统。
  17. 根据权利要求16所述的服务器，其特征在于，所述服务器的两个CPU各出两路PCIe总线连接到所述服务器管理系统。
  18. 根据权利要求16所述的服务器，其特征在于，所述服务器的两个CPU出的四路PCIe总线的通道由所述服务器管理系统中的选通开关统一控制。
  19. 根据权利要求16所述的服务器，其特征在于，所述服务器中的CPU通过连通到所述服务器管理系统中的基板管理控制装置的PCIe总线发送PCIe信号。
  20. 根据权利要求19所述的服务器，其特征在于，所述PCIe信号包括操作系统界面的相关数据，所述操作系统界面的相关数据用于所述基板管理控制装置进行操作系统界面的显示控制。
PCT/CN2023/091301 2022-04-29 2023-04-27 一种服务器及其服务器管理系统 WO2023208135A1 (zh)

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