WO2023207956A1 - 开关电源的供电电路及其供电方法 - Google Patents

开关电源的供电电路及其供电方法 Download PDF

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Publication number
WO2023207956A1
WO2023207956A1 PCT/CN2023/090536 CN2023090536W WO2023207956A1 WO 2023207956 A1 WO2023207956 A1 WO 2023207956A1 CN 2023090536 W CN2023090536 W CN 2023090536W WO 2023207956 A1 WO2023207956 A1 WO 2023207956A1
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Prior art keywords
tube
power supply
switch tube
gate
pin
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PCT/CN2023/090536
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English (en)
French (fr)
Inventor
杨晨涛
陈伟
Original Assignee
深圳英集芯科技股份有限公司
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Publication of WO2023207956A1 publication Critical patent/WO2023207956A1/zh

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/06—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode
    • H02M7/068—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode mounted on a transformer
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the invention relates to the field of electronic equipment, and in particular to a power supply circuit of a switching power supply and a power supply method thereof.
  • switching power supplies are widely used in power supply systems for loads such as computers, electrical appliances, and portable electronic equipment. It converts general power into power more suitable for the load application. In common applications, the power input mainly comes from the mains (50Hz, 220V AC), and the switching power supply can convert this power into the low-voltage DC power required by the load. As the key to the normal operation of the switching power supply, the controller itself also requires a certain working voltage to maintain its basic functions.
  • the power supply of existing switching power supplies is generally based on the auxiliary winding power supply.
  • the power supply form based on the auxiliary winding is accompanied by the risk of chip pin overvoltage caused by the increase in output voltage. That is, as the output voltage increases, the voltage on the auxiliary winding will also increase. becomes larger and exceeds the voltage resistance requirements of the pin, causing safety hazards.
  • Embodiments of the present invention provide a power supply circuit of a switching power supply and a power supply method thereof, which can supply power to the switching power supply without using an auxiliary winding, thereby avoiding excessive voltage resistance of the pins and improving the safety performance of the power supply circuit.
  • inventions of the present invention provide a power supply circuit for a switching power supply.
  • the circuit includes: a control chip, a transformer, a bridge rectifier circuit, a switching tube, a capacitor and a resistor,
  • the control chip includes: main power tube, auxiliary power tube, second start resistor R start2 , delay module and selection module; wherein,
  • the DN pin of the control chip is connected to the output end of the primary winding L p of the transformer, the HV pin is connected to the other end of the first starting resistor R start1 , and one end of the first starting resistor R start1 is connected
  • the cathode of the second switch tube D2 and the anode of the second switch tube D2 are connected to the mains output terminal;
  • the control The VDD pin of the manufacturing chip is connected to one end of the capacitor C VDD , and the other end of the capacitor C VDD is connected to the equipotential point; inside the control chip, the HV pin is connected to one end of the second start-up resistor R start2 , and the second start-up resistor R start2
  • the other end of the main power tube is connected to the gate of the main power tube.
  • the gate of the main power tube is also connected to the output end of the delay module.
  • the drain of the main power tube is connected to the DN pin.
  • the source of the main power tube is connected to the first One end of the switch tube is connected to the drain of the auxiliary power tube, the other end of the first switch tube is connected to the VDD pin of the control chip, and the gate of the auxiliary power tube is connected to the output end of the selection module;
  • the input terminal of the delay module is connected to the PWM signal, one input terminal of the selection module is connected to the PWM signal, and the other input terminal is connected to the VDD signal;
  • the control chip also includes: a mirror current sampling circuit, the mirror current sampling circuit
  • the circuit includes a third switch tube, a fourth switch tube, a comparator, a fifth switch tube and a current mirror circuit; wherein,
  • the gates of the third switch tube and the fourth switch tube are both connected to the gate electrode of the auxiliary power tube, the drain electrode of the fourth switch tube is connected to the drain electrode of the auxiliary power tube, and the source electrode of the fourth switch tube is connected to the forward input of the comparator.
  • the source of the third switch tube is connected to the source of the auxiliary power tube
  • the drain of the third switch tube is connected to the reverse input terminal of the comparator
  • the output terminal of the comparator is connected to the gate of the fifth switch
  • the fifth switch The source of the tube is connected to one end of the resistor, the other end of the resistor is connected to the drain of the third switch tube, the drain of the fifth switch tube is connected to the input end of the current mirror circuit, and the output end of the current mirror circuit is connected to the CS of the control chip. pin;
  • the delay module is a module that delays the PWM signal for a set time period; the selection module is a module that selects whether to provide power.
  • a mirror current sampling circuit is provided.
  • the mirror current sampling circuit is applied to the switching power supply circuit provided in the first aspect;
  • the mirror current sampling circuit includes a third switch tube, a fourth switch tube, a comparator, The fifth switch tube and current mirror circuit;
  • the mirror current sampling circuit includes a third switch tube, a fourth switch tube, a comparator, a fifth switch tube and a current mirror circuit;
  • the gates of the third switch tube and the fourth switch tube are both connected to the gate electrode of the auxiliary power tube, the drain electrode of the fourth switch tube is connected to the drain electrode of the auxiliary power tube, and the source electrode of the fourth switch tube is connected to the forward input of the comparator.
  • the source of the third switch tube is connected to the source of the auxiliary power tube
  • the drain of the third switch tube is connected to the reverse input terminal of the comparator
  • the output terminal of the comparator is connected to the gate of the fifth switch
  • the fifth switch The source of the tube is connected to one end of the resistor, the other end of the resistor is connected to the drain of the third switch tube, the drain of the fifth switch tube is connected to the input end of the current mirror circuit, and the output end of the current mirror circuit is connected to the CS of the control chip. pin.
  • a power supply method for a power supply circuit of a switching power supply is provided.
  • the method is applied to the power supply circuit of a switching power supply provided in the first aspect.
  • the method includes the following steps:
  • V DD is less than the voltage threshold V m
  • the power supply is enabled, and the control PWM signal is input to the delay module and selection module, and the main power tube is turned on or off with a lag relative to the auxiliary power tube.
  • a fourth aspect provides a switching power supply system, which includes the circuits and methods described in the first two aspects.
  • the circuit provided by this application does not require an auxiliary winding for power supply.
  • the voltage on the auxiliary winding will also increase, thereby exceeding the withstand voltage requirements of the pin, thereby improving the safety of the circuit.
  • the charging process occurs when the current I p reaches the peak value (Peak1), so the charging efficiency is high and the voltage VDD can be effectively increased in a short period of time; on the other hand, due to the clamping effect of diode D3, the secondary The voltage the power tube withstands when turned off is similar to VDD, so there is no need for high withstand voltage characteristics, effectively reducing design costs.
  • the input of the starting circuit comes from the AC input, which can reduce the loss generated by this branch during startup and normal operation.
  • the mirror current sampling circuit significantly reduces the current flowing through the sampling resistor, effectively reducing the loss caused by the sampling resistor.
  • Figure 1 is a circuit schematic diagram of a switching power supply circuit
  • Figure 2 is a circuit schematic diagram of another switching power supply circuit
  • FIG. 3 is a circuit schematic diagram of a switching power supply circuit provided by this application.
  • FIG. 4 is a schematic structural diagram of the selection module provided by this application.
  • Figure 5 is a circuit schematic diagram of a mirror current sampling module provided by this application.
  • FIG. 6 is a circuit schematic diagram of another switching power supply circuit provided by this application.
  • Figure 7 is a schematic waveform diagram of the switching power supply circuit provided by this application.
  • an embodiment means that a particular feature, result or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention.
  • the appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art understand, both explicitly and implicitly, that the embodiments described herein may be combined with other embodiments.
  • Figure 1 shows a switching power supply circuit, which mainly includes a high-voltage power supply line composed of resistors R HV1 , R HV2 and a high-voltage switching tube 1, and a high-voltage power supply line composed of the auxiliary winding AUX and the second switching tube D2.
  • Auxiliary winding power supply circuit In the high-voltage power supply line, the current flows from V in through the resistor, pin HV, high voltage switch tube 1, pin VDD, and finally to the capacitor C VDD .
  • This method mainly charges the capacitor C VDD during the startup process until the chip startup is completed.
  • the auxiliary winding circuit supplies power to C VDD during normal operation. When the voltage on the auxiliary winding is insufficient to charge C VDD , the high-voltage switch tube 1 can be turned on to enable high-voltage power supply.
  • the resistors R HV1 and R HV2 cannot be too large, and the primary side voltage V in is always maintained at a high level, causing large losses in this high-voltage power supply method and reducing circuit efficiency.
  • the existence of high-voltage switch tubes also increases the design cost of the chip.
  • the voltage V AUX on the auxiliary winding is a multiple of the output voltage when the power tube is turned off, in the case of high output voltage, the voltage V DD easily exceeds the upper limit of the withstand voltage, causing the chip to malfunction. damage.
  • Figure 2 provides another switching power supply circuit, which includes a high-voltage power supply line from HV to VDD and an auxiliary winding power supply line composed of a rectifier 1, a series resistor, a high-voltage switch tube 2, and a diode D3.
  • the former is the main power supply method.
  • the high-voltage switch tube 2 controls the connection and shutdown of the high-voltage power supply line. During the power-on process, the high-voltage switch tube 2 is turned on until V DD reaches the preset value. normal During operation, the voltage V HV on the HV pin is monitored (which is similar to the rectified voltage V rec ).
  • the high-voltage switch tube 2 When it is less than a boundary value, it is judged to be the voltage valley interval, and the high-voltage switch tube 2 is turned on for high-voltage charging; when When V HV is greater than the boundary value again, the high voltage switch tube 2 is turned off to stop power supply. In addition, when V AUX is greater than V DD , the high-voltage power supply line can be turned off and only the auxiliary winding is powered.
  • V DD When charging in the valley interval, V DD rises in a fluctuating manner (charge when V rec is greater than V DD , not charge when less than V DD ), which reduces losses during high-voltage power supply.
  • V top and V bottom it is necessary to set the upper and lower boundaries of V DD (V top and V bottom ) and dynamically adjust the boundary value according to V DD to prevent V DD from exceeding the normal operating voltage range, and a high-voltage switch tube is still required to control the opening of the high-voltage power supply line. and shut down.
  • Figure 3 is a switching power supply circuit provided by this application.
  • the main power tube 1 and the auxiliary power tube 2 are integrated inside the chip.
  • the drain of the former is connected to the pin DN, and the gate
  • the pole is connected to the start resistor R start2 , and the source is connected to the drain of the latter.
  • the other end of R start2 is connected to the pin HV, and then the HV is externally connected to the start circuit composed of the start resistor R start1 and the second switch tube D2, and the start circuit is connected to the AC input.
  • the connection point of the two power tubes is connected to the diode D3, and then connected to the pin VDD to form a one-way charging line.
  • Module Delay 4 and module Select 5 are respectively connected to the gates of the main power tube 1 and the auxiliary power tube 2, and the other ends of the two are jointly connected to the control module PWM controller 3.
  • the module PWM controller 3 generates corresponding PWM control signals by obtaining the information of VS, VIN and FB.
  • the above-mentioned PWM control module can use a general PWM control module. This application does not limit the specific structure of the above-mentioned PWM control module.
  • the power supply method mainly includes two processes:
  • the AC input When powering on, the AC input first charges the gate of the main power tube 1 through the second switching tube D2 and the starting resistors R start1 and R start2 , causing the gate-source voltage to rise.
  • the gate-source voltage is greater than the critical value V th , the main power transistor is turned on.
  • the primary measured voltage V in will charge the capacitor C VDD through the primary side of the transformer, the main power transistor 1 and the diode D3.
  • the voltage V DD will start to rise until it reaches the preset value V PG . After that, the chip and the entire switching power supply began to work normally.
  • PWM controller 3 When working normally and V DD is less than the threshold V m , the power supply is enabled.
  • PWM controller 3 outputs PWM signals to Delay (delay module) 4 and Select (selection module) 5.
  • Module Delay 4 generates a fixed delay to lag the PWM signal.
  • Module Select 5 selects the input and output to be consistent, that is, there is no delay in the PWM signal. Therefore, at this time, the turning on and off of the main power tube will lag behind the auxiliary power tube for a fixed period of time.
  • the primary current reaches the peak value, and the auxiliary power transistor 2 is turned off first, which will form the same charging circuit as when powering on, that is, V in charges the capacitor C VDD through the primary side of the transformer, the main power transistor 1 and the diode D3. . subsequently The main power tube is turned off and charging stops.
  • the charging time is the fixed delay time of module Delay 4.
  • V DD is greater than the threshold V m , the power supply is disabled.
  • Module Select 5 will choose to output a high level, and the secondary power tube 2 remains in the on state. At this time, a charging loop cannot be formed, and C VDD is not charged.
  • the module Select 5 judges the magnitude of V DD and V m to determine whether the power supply is enabled (that is, the secondary switch tube acts with the PWM or remains on).
  • the circuit diagram of the module Select 5 is shown in Figure 4 shown.
  • PWM is the output of module PWM controller 3
  • PWM1 and PWM2 represent the gate-source control signals of main power tube 1 and auxiliary power tube 2 respectively
  • I p is the primary side current.
  • the charging process occurs when the current I p reaches the peak value (Peak1), so the charging efficiency is high and the voltage V DD can be effectively increased in a short period of time; on the other hand, it is clamped by the diode D3 Affected by the bit, the voltage that the secondary power transistor 2 withstands when turned off is similar to V DD , so there is no need for high withstand voltage characteristics, which effectively reduces the design cost.
  • the input of the starting circuit comes from the AC input, which can reduce the loss generated by this branch during startup and normal operation.
  • the circuit includes: a control chip, a transformer, a bridge rectifier circuit, a switch tube, a capacitor and a resistor.
  • the control chip includes: main power tube, auxiliary power tube, second start resistor R start2 , delay module and selection module; wherein,
  • the DN pin of the control chip is connected to the output end of the primary winding L p of the transformer, the HV pin is connected to the other end of the first starting resistor R start1 , and one end of the first starting resistor R start1 is connected
  • the cathode of the second switch tube D2 and the anode of the second switch tube D2 are connected to the mains output terminal;
  • the control The VDD pin of the chip is connected to one end of the capacitor C VDD , and the other end of the capacitor C VDD is connected to the equipotential point;
  • the HV pin is connected to one end of the second start resistor R start2 , and the other end of the second start resistor R start2 is connected to the gate of the main power tube.
  • the gate of the main power tube is also connected to the output of the delay module.
  • the drain of the main power tube is connected to the DN pin
  • the source of the main power tube is connected to one end of the first switch tube and the drain of the auxiliary power tube, and the other end of the first switch tube is connected to the
  • the VDD pin of the control chip the gate of the secondary power tube is connected to the output terminal of the selection module, and the source of the secondary power tube is connected to the CS pin
  • the input terminal of the delay module is connected to the PWM signal
  • One input terminal of the selection module is connected to the PWM signal, and the other input terminal is connected to the VDD signal
  • the delay module is a module that delays the PWM signal for a set time period; the selection module is a module that selects whether to provide power.
  • the CS pin of the control chip is connected to an equal potential point through a resistor R cs .
  • the first switch tube is a diode or a field effect tube.
  • the selection module includes: a comparator, a D flip-flop, an AND gate, a NOT gate and an OR gate, where,
  • the positive pin of the comparator is connected to the voltage threshold V m and the negative pin is connected to VDD; the output end of the comparator is connected to the D pin of the D flip-flop, and the CP pin of the D flip-flop is connected to the PWM signal.
  • the signal is also connected to one input terminal of the AND gate, and the other input terminal of the AND gate is connected to the Q output terminal Charge-en of the D flip-flop; the Q output terminal of the D flip-flop is also connected to the NOT gate.
  • the input end of the NOT gate is connected to the other input end of the OR gate, and one input end of the OR gate is connected to the output end of the AND gate.
  • the output end of the OR gate is the output end of the selection module. output terminal.
  • this application also provides a mirror current sampling circuit, which can be set inside the above-mentioned control chip.
  • the mirror current sampling circuit can also be called: mirror current sampling module SNS6.
  • Figure 5 provides a mirror current
  • Figure 6 is the circuit schematic diagram of adding SNS6.
  • the mirror current sampling circuit includes a third switch tube 7, a fourth switch tube 8, a comparator, a fifth switch tube and a current mirror circuit; where,
  • the gates of the third switching tube 7 and the fourth switching tube 8 are connected to the gate of the auxiliary power tube, the drain of the fourth switching tube 8 is connected to the drain of the auxiliary power tube, and the source of the fourth switching tube is connected to the comparator.
  • the forward input terminal of To the input end, the output end of the comparator is connected to the gate of the fifth switch tube, the source of the fifth switch tube is connected to one end of the resistor, the other end of the resistor is connected to the drain of the third switch, and the drain of the fifth switch.
  • the input terminal of the current mirror circuit 9 is connected, and the output terminal of the current mirror circuit 9 is connected to the CS pin of the control chip.
  • the on-resistances of the third switching tube 7 and the auxiliary power tube 2 are in a multiple relationship.
  • switch tubes 2, 7, and 8 are turned on.
  • the positive and negative input voltages of the op amp are equal, that is, the voltages of the third switch tube 7 and the secondary power tube 2 are The drain voltages are equal.
  • the on-resistance of the third switching tube 7 is amplified by a certain proportion compared to the on-resistance of the auxiliary power tube 2, the mirror current I psns flowing through the third switching tube 7 is compared with the power current I flowing through the auxiliary power tube 2. p is scaled down.
  • the current mirror circuit 9 generates another (enlarged, reduced or equal to a certain proportion) mirror current ISNS based on the mirror current I psns , and outputs it to the pin CS.
  • the current (I SNS ) flowing through the external sampling resistor R CS will be significantly reduced, so the loss generated on it is significantly reduced.
  • the third switch tube and the fourth switch tube are turned on, current sampling is enabled, and the mirror current is output to the CS pin of the control chip.
  • the magnitude of the mirror current is related to the magnitude of the current flowing through the secondary power transistor. Specifically, the first ratio between the mirror current and the current flowing through the auxiliary power tube is proportional to the second ratio between the on-resistance of the auxiliary power tube and the third switching tube.
  • This application also provides a power supply method for a power supply circuit of a switching power supply.
  • the method is applied to the power supply circuit of a switching power supply as shown in Figure 3.
  • the method includes the following steps:
  • V DD is less than the voltage threshold V m
  • the power supply is enabled, the PWM signal is controlled to be input to the delay module and the selection module, and the main power tube lags (turns on or off) relative to the auxiliary power tube. broken).
  • the above methods may also include:
  • V DD is greater than or equal to the voltage threshold V m , the power supply is disabled and the module is selected to output a high level.
  • the above method may also include: during the startup phase of the power supply circuit of the switching power supply, the AC input drives the main power transistor to conduct through the second switch transistor and the startup resistors R start1 and R start2 , so that V DD rises to the startup threshold and then the chip is controlled to operate. .
  • the embodiment of the present application also provides a switching power supply system.
  • the switching power supply system may include the power supply circuit of the switching power supply of the embodiment shown in Figure 3 or Figure 6, and may also include the mirror current sampling shown in Figure 5. circuit.
  • embodiments of the present application also provide a switching power supply system, which can provide power using the power supply method of the power supply circuit of the switching power supply described above.
  • the disclosed device can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or may be Integrated into another system, or some features can be ignored, or not implemented.
  • the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical or other forms.
  • the program can be stored in a computer-readable memory.
  • the memory can include: a flash disk. , read-only memory (English: Read-Only Memory, abbreviation: ROM), random access device (English: Random Access Memory, abbreviation: RAM), magnetic disk or optical disk, etc.

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Abstract

本申请提供一种开关电源的供电电路及其供电方法，该开关电源的供电电路包括：主功率管和副功率管集成在芯片内部，其中，前者的漏极连向引脚DN，栅极连向启动电阻，源极则与后者的漏极相连，后HV外部连向启动电阻Rstart1和第二开关管D2组成的启动电路，启动电路则与AC输入相连，两功率管的连接点与二极管D3相连，之后连向引脚VDD，构成单向充电线路，模块Delay 4和模块Select 5分别与主功率管1和副功率管2的栅极相连，两者的另一端共同连向控制模块PWM controller 3，生成PWM控制信号，PWM控制模块可以采用通用的PWM控制模块。本申请提供的技术方案具有安全性高的优点。

Description

开关电源的供电电路及其供电方法
本申请要求于2022年04月26日提交中国专利局、申请号为2022104430408、申请名称为“开关电源的供电电路及其供电方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及电子设备领域，具体涉及一种开关电源的供电电路及其供电方法。
背景技术
开关电源基于其效率高、体积小等优点，以广泛应用于计算机、电器、便携电子设备等负载的供电系统中。其能够将一般电力转换为更适合负载应用的电源。在常见应用中，电力输入主要来自市电(50Hz、220V的交流电)，开关电源则能够将该电力转换为负载所需的低压直流电源。作为开关电源正常工作的关键，控制器本身也需要一定的工作电压来维持其基本功能。
现有的开关电源的供电一般基于辅助绕组供电，基于辅助绕组的供电形式伴随着输出电压升高带来的芯片引脚过压风险，即输出电压的提高，辅助绕组上的电压也会随之变大，进而超过引脚的耐压要求，进而产生安全隐患。
发明内容
本发明实施例提供了一种开关电源的供电电路及其供电方法，可以不通过辅助绕组对开关电源进行供电，进而避免了引脚的耐压过高，提高供电电路的安全性能。
第一方面，本发明实施例提供一种开关电源的供电电路，所述电路包括：控制芯片、变压器、桥式整流电路、开关管、电容和电阻，
所述控制芯片包括：主功率管、副功率管、第二启动电阻Rstart2、延时模块和选择模块；其中，
在所述控制芯片外部，所述控制芯片的DN引脚连接变压器的原边绕组Lp的输出端，HV引脚连接第一启动电阻Rstart1的另一端，第一启动电阻Rstart1的一端连接第二开关管D2的阴极，第二开关管D2的阳极连接市电输出端；所述控 制芯片的VDD引脚连接电容CVDD的一端，电容CVDD的另一端连接等电势点；在所述控制芯片内部，HV引脚连接第二启动电阻Rstart2的一端，第二启动电阻Rstart2的另一端连接主功率管的栅极，主功率管的栅极还连接延时模块的输出端，主功率管的漏极连接所述DN引脚，所述主功率管的源极连接第一开关管的一端以及连接所述副功率管的漏极，第一开关管的另一端连接所述控制芯片的VDD引脚，所述副功率管的栅极连接所述选择模块的输出端；所述延时模块的输入端连接PWM信号，所述选择模块的一个输入端连接PWM信号，另一个输入端连接VDD信号；在所述控制芯片内部还包括：镜像电流采样电路，所述镜像电流采样电路包括第三开关管、第四开关管、比较器、第五开关管和电流镜电路；其中，
第三开关管、第四开关管的栅极均连接副功率管的栅极，第四开关管的漏极连接副功率管的漏极，第四开关管的源极连接比较器的正向输入端，第三开关管的源极连接副功率管的源极，第三开关管的漏极连接比较器的反向输入端，比较器的输出端连接第五开关管的栅极，第五开关管的源极连接电阻的一端，电阻的另一端连接第三开关管的漏极，第五开关管的漏极连接电流镜电路的输入端，电流镜电路的输出端连接所述控制芯片的CS引脚；
所述延时模块为将PWM信号延时一设定时长的模块；所述选择模块为选择是否供电的模块。
第二方面，提供一种镜像电流采样电路，所述镜像电流采样电路应用于第一方面提供的开关电源供电电路；所述镜像电流采样电路包括第三开关管、第四开关管、比较器、第五开关管和电流镜电路；所述镜像电流采样电路包括第三开关管、第四开关管、比较器、第五开关管和电流镜电路；其中，
第三开关管、第四开关管的栅极均连接副功率管的栅极，第四开关管的漏极连接副功率管的漏极，第四开关管的源极连接比较器的正向输入端，第三开关管的源极连接副功率管的源极，第三开关管的漏极连接比较器的反向输入端，比较器的输出端连接第五开关管的栅极，第五开关管的源极连接电阻的一端，电阻的另一端连接第三开关管的漏极，第五开关管的漏极连接电流镜电路的输入端，电流镜电路的输出端连接所述控制芯片的CS引脚。
第三方面，提供一种开关电源的供电电路的供电方法，所述方法应用于第一方面提供的开关电源的供电电路，所述方法包括如下步骤：
若所述控制芯片正常工作且VDD小于电压阈值Vm，供电使能，控制PWM信号输入到所述延时模块和选择模块，所述主功率管相对副功率管滞后导通或关断。
第四方面，提供一种开关电源系统，所述电源系统包含前两方面所述的电路及方法。
实施本发明实施例，具有如下有益效果：
可以看出，本申请提供的电路无需辅助绕组进行供电，不会因输出电压的提高，辅助绕组上的电压也会随之变大，进而超过引脚的耐压要求，进而提高电路的安全性。另外，一方面，充电过程发生在电流Ip达到峰值(Peak1)时，所以充电效率高，在较短的时间内即可有效提升电压VDD；另一方面，受二极管D3的钳位影响，副功率管在关断时承受的电压与VDD相近，所以无需高耐压的特性，有效降低设计成本。此外，启动电路(第二开关管D2和串联启动电阻)的输入来自AC输入，能够降低起机以及正常工作时该支路所产生的损耗。镜像电流采样电路使得流经采样电阻的电流显著减小，有效降低了采样电阻产生的损耗。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是一种开关电源供电电路的电路示意图；
图2是另一种开关电源供电电路的电路示意图；
图3是本申请提供的一种开关电源供电电路的电路示意图；
图4是本申请提供的选择模块的结构示意图；
图5是本申请提供的一种镜像电流采样模块的电路示意图；
图6是本申请提供的另一种开关电源供电电路的电路示意图；
图7是本申请提供的开关电源供电电路的波形示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部 的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明的说明书和权利要求书及所述附图中的术语“第一”、“第二”、“第三”和“第四”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结果或特性可以包含在本发明的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
参阅图1，图1中展示了一种开关电源供电电路，主要包括由电阻RHV1、RHV2和高耐压开关管1组成的高压供电线路和由辅助绕组AUX和第二开关管D2组成的辅助绕组供电线路。在高压供电线路中，电流从Vin开始依次流经电阻、引脚HV、高耐压开关管1、引脚VDD，直至电容CVDD。该方式主要在启动过程中对电容CVDD充电，直至芯片起机完成。辅助绕组线路则在正常工作时为CVDD供电，而当辅助绕组上的电压不足以为CVDD充电时，则可打开高耐压开关管1，启用高压供电。
由于对芯片上电速度有一定的要求，电阻RHV1和RHV2不能太大，一次侧电压Vin也始终维持在较高的水准，使得该高压供电方式存在较大的损耗，降低电路效率。同时高耐压开关管的存在也提升了芯片的设计成本。而对于辅助绕组的供电线路，由于在功率管关断时，辅助绕组上的电压VAUX与输出电压呈倍数关系，使得在高输出电压的情况下，电压VDD容易超过耐压上限，造成芯片损坏。
参阅图2，图2提供了另一种开关电源供电电路，其包括整流管1、串联电阻、高耐压开关管2、二极管D3组成的由HV至VDD的高压供电线路和辅助绕组供电线路，其中前者为主要供电方式。由高耐压开关管2控制高压供电线路的连通和关断。上电过程中高耐压开关管2长通直至VDD达到预设值。正常 工作时，监测HV引脚上的电压VHV(其与整流后的电压Vrec相近)，当其小于一边界值时，判断为电压谷底区间，打开高耐压开关管2进行高压充电；当VHV再次大于边界值时，关闭高耐压开关管2停止供电。此外，当VAUX大于VDD时，可关闭高压供电线路，仅由辅助绕组供电。
谷底区间充电时，VDD呈波动式上升(Vrec大于VDD时充电，小于VDD时不充电)，降低了高压供电时的损耗。但是需要设定VDD的上下边界(Vtop和Vbottom)以及根据VDD动态调整边界值，以避免VDD超出正常的工作电压范围，而且仍然需要高耐压开关管控制高压供电线路的开通与关断。
参阅图3，图3为本申请提供的一种开关电源供电电路，如图3所示，主功率管1和副功率管2集成在芯片内部，其中前者的漏极连向引脚DN，栅极连向启动电阻Rstart2，源极则与后者的漏极相连。Rstart2另一端连向引脚HV，之后HV外部连向启动电阻Rstart1和第二开关管D2组成的启动电路，启动电路则与AC输入相连。两功率管的连接点与二极管D3相连，之后连向引脚VDD，构成单向充电线路。模块Delay 4和模块Select 5分别与主功率管1和副功率管2的栅极相连，两者的另一端共同连向控制模块PWM controller 3。而模块PWM controller 3通过获取VS、VIN和FB的信息，生成相应的PWM控制信号，上述PWM控制模块可以采用通用的PWM控制模块，本申请并不限制上述PWM控制模块的具体结构。
供电方法主要包括两个过程：
1.上电时，AC输入首先经过第二开关管D2和启动电阻Rstart1、Rstart2向主功率管1的栅极充电，使栅源电压上升。当栅源电压大于临界值Vth时，主功率管导通，此时一次测电压Vin将通过变压器原边、主功率管1和二极管D3向电容CVDD充电。电压VDD将开始上升，直至达到预设值VPG。之后芯片以及整个开关电源开始正常工作。
2.正常工作且VDD小于阈值Vm时，供电使能。PWM controller 3输出PWM信号给Delay(延时模块)4和Select(选择模块)5。模块Delay 4产生一固定延时，将PWM信号滞后，模块Select 5选择输入与输出一致，即PWM信号无延时。所以此时主功率管的开通与关断将滞后副功率管一段固定时间。在关断阶段，原边电流达到峰值，副功率管2先关断，将形成与上电时相同的充电回路，即Vin经过变压器原边、主功率管1和二极管D3向电容CVDD充电。随后 主功率管关断，充电停止，充电时间即为模块Delay 4的固定延时时间。当VDD大于阈值Vm时，供电不使能。模块Select 5将选择输出高电平，副功率管2保持导通状态，此时无法形成充电回路，CVDD不被充电。
在每个周期开始时，由模块Select 5对VDD和Vm进行大小判断，来决定供电是否使能(即副开关管随PWM动作或保持导通)，模块Select 5的电路示意图如图4所示。在Select-in(PWM信号)的上升沿到来时，若此时Vm大于VDD，则Charge-en置1(高电平)，模块输出Select-out与输入Select-in相同；若此时Vm大于VDD，则模块输出Select-out恒为高电平。
正常工作时，相关信号波形如图7所示。其中PWM为模块PWM controller 3的输出，PWM1和PWM2分别表示主功率管1和副功率管2的栅源控制信号，Ip为原边电流。当充电使能(即Charge-en为高电平)且电流达到峰值Peak1时，PWM信号降为低电平，副功率管2关断，开始对CVDD充电，之后主功率管1关断。在充电的过程中，原边电流Ip将继续升高直至Peak2(充电结束)。当充电不使能时(即Charge-en为低电平)，由于主功率管1的控制信号PWM1相对PWM的滞后始终存在，所以Ip在PWM降为低电平后也会继续上升直至主功率管1关断。可见，实际峰值电流(Peak2)始终比希望的峰值电流(Peak1)要大，但是因为滞后(延时)时间固定，所以偏大的幅度基本一致。因此可以直接通过调整峰值电流相关的阈值进行补偿，无需额外措施。
本申请提供的电路一方面，充电过程发生在电流Ip达到峰值(Peak1)时，所以充电效率高，在较短的时间内即可有效提升电压VDD；另一方面，受二极管D3的钳位影响，副功率管2在关断时承受的电压与VDD相近，所以无需高耐压的特性，有效降低设计成本。此外，启动电路(第二开关管D2和串联启动电阻)的输入来自AC输入，能够降低起机以及正常工作时该支路所产生的损耗。
参阅图3所示的开关电源的供电电路，所述电路包括：控制芯片、变压器、桥式整流电路、开关管、电容和电阻，
所述控制芯片包括：主功率管、副功率管、第二启动电阻Rstart2、延时模块和选择模块；其中，
在所述控制芯片外部，所述控制芯片的DN引脚连接变压器的原边绕组Lp的输出端，HV引脚连接第一启动电阻Rstart1的另一端，第一启动电阻Rstart1的一端连接第二开关管D2的阴极，第二开关管D2的阳极连接市电输出端；所述控 制芯片的VDD引脚连接电容CVDD的一端，电容CVDD的另一端连接等电势点；
在所述控制芯片内部，HV引脚连接第二启动电阻Rstart2的一端，第二启动电阻Rstart2的另一端连接主功率管的栅极，主功率管的栅极还连接延时模块的输出端，主功率管的漏极连接所述DN引脚，所述主功率管的源极连接第一开关管的一端以及连接所述副功率管的漏极，第一开关管的另一端连接所述控制芯片的VDD引脚，所述副功率管的栅极连接所述选择模块的输出端，所述副功率管的源极连接CS引脚；所述延时模块的输入端连接PWM信号，所述选择模块的一个输入端连接PWM信号，另一个输入端连接VDD信号；
所述延时模块为将PWM信号延时一设定时长的模块；所述选择模块为选择是否供电的模块。
在一种可选的方案中，在所述控制芯片外部，所述控制芯片的CS引脚通过电阻Rcs连接等电势点。
在一种可选的方案中，
所述第一开关管为二极管或场效应管。
在一种可选的方案中，所述选择模块包括：比较器、D触发器、与门、非门以及或门，其中，
所述比较器的正脚连接电压阈值Vm，负脚连接VDD；所述比较器的输出端连接D触发器的D引脚，所述D触发器的CP引脚连接PWM信号，所述PWM信号还连接所述与门的一个输入端，所述与门的另一输入端连接所述D触发器的Q输出端Charge-en；所述D触发器的Q输出端还连接所述非门的输入端，所述非门的输出端连接或门的另一个输入端，所述或门的一个输入端连接所述与门的输出端，所述或门的输出端为所述选择模块的输出端。
示意的，本申请还提供一种镜像电流采样电路，其可以设置在上述控制芯片内部该镜像电流采样电路也可以称为：镜像电流采样模块SNS6，参阅图5，图5提供了一种镜像电流采样电路的电路示意图，参阅图6，图6为添加SNS6的电路示意图。如图5所示，镜像电流采样电路包括第三开关管7、第四开关管8、比较器、第五开关管和电流镜电路；其中，
第三开关管7、第四开关管8的栅极连接后连接副功率管的栅极，第四开关管8的漏极连接副功率管的漏极，第四开关管的源极连接比较器的正向输入端，第三开关管7的源极连接副功率管的源极，第三开关管的漏极连接比较器的反 向输入端，比较器的输出端连接第五开关管的栅极，第五开关管的源极连接电阻的一端，电阻的另一端连接第三开关管的漏极，第五开关管的漏极连接电流镜电路9的输入端，电流镜电路9的输出端连接所述控制芯片的CS引脚。
其中，第三开关管7和副功率管2的导通电阻呈倍数关系。当驱动gate置高时，开关管2、7、8导通，基于运放的“虚短虚断”特性，运放的正负输入电压相等，即第三开关管7和副功率管2的漏极电压相等。由于第三开关管7的导通电阻相比副功率管2的导通电阻按一定比例放大，那么流经第三开关管7的镜像电流Ipsns相比流经副功率管2的功率电流Ip等比例缩小。进一步的，电流镜电路9基于镜像电流Ipsns产生另一(按一定比例放大、缩小或相等)镜像电流ISNS，并输出给引脚CS。相比传统的采样方式，流经外部采样电阻RCS的电流(ISNS)将显著减小，所以其上产生的损耗明显降低。在一种可选的方案中，当副功率管导通时，第三开关管以及四开关管导通，电流采样使能，并输出镜像电流至所述控制芯片的CS引脚。
在一种可选的方案中，所述镜像电流的大小与流经所述副功率管的电流的大小相关。具体的，所述镜像电流和流经副功率管的电流之间的第一比例与副功率管和第三开关管的导通电阻之间的第二比例呈比例关系。
本申请还提供一种开关电源的供电电路的供电方法，所述方法应用于如图3所示的开关电源的供电电路，所述方法包括如下步骤：
若所述控制芯片正常工作且VDD小于电压阈值Vm，供电使能，控制PWM信号输入到所述延时模块和选择模块，所述主功率管相对副功率管滞后动作(导通或关断)。
示例的，上述方法还可以包括：
若VDD大于或等于电压阈值Vm，供电不使能，选择模块输出高电平。
示例的，上述方法还可以包括：开关电源的供电电路启动阶段，交流输入通过第二开关管以及启动电阻Rstart1和Rstart2驱动主功率管导通，使VDD上升至启动阈值后控制芯片工作。
示例的，本申请实施例还提供一种开关电源系统，该开关电源系统可以包括如图3或图6所示实施例的开关电源的供电电路，也可以包含如图5所示的镜像电流采样电路。示例的，本申请实施例还提供一种开关电源系统，该开关电源系统可以应用上述开关电源的供电电路的供电方法进行供电。
需要说明的是，对于前述的各方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本发明并不受所描述的动作顺序的限制，因为依据本发明，某些步骤可以接收其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于可选实施例，所涉及的动作和模块并不一定是本发明所必须的。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置，可通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性或其它的形式。
本领域普通技术人员可以理解上述实施例的各种方法中的全部或部分步骤是可以通过程序来指令相关的硬件来完成，该程序可以存储于一计算机可读存储器中，存储器可以包括：闪存盘、只读存储器(英文：Read-Only Memory，简称：ROM)、随机存取器(英文：Random Access Memory，简称：RAM)、磁盘或光盘等。
以上对本发明实施例进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (13)

  1. 一种开关电源的供电电路，所述电路包括：控制芯片、变压器、桥式整流电路、开关管、电容和电阻，其特征在于，
    所述控制芯片包括：主功率管、副功率管、第二启动电阻Rstart2、延时模块和选择模块；其中，
    在所述控制芯片外部，所述控制芯片的DN引脚连接变压器的原边绕组Lp的输出端，HV引脚连接第一启动电阻Rstart1的另一端，第一启动电阻Rstart1的一端连接第二开关管D2的阴极，第二开关管D2的阳极连接市电输出端；所述控制芯片的VDD引脚连接电容CVDD的一端，电容CVDD的另一端连接等电势点；在所述控制芯片内部，HV引脚连接第二启动电阻Rstart2的一端，第二启动电阻Rstart2的另一端连接主功率管的栅极，主功率管的栅极还连接延时模块的输出端，主功率管的漏极连接所述DN引脚，所述主功率管的源极连接第一开关管的一端以及连接所述副功率管的漏极，第一开关管的另一端连接所述控制芯片的VDD引脚，所述延时模块的输入端连接PWM信号，所述选择模块的一个输入端连接PWM信号，另一个输入端连接VDD信号；在所述控制芯片内部还包括：镜像电流采样电路，所述镜像电流采样电路包括第三开关管、第四开关管、比较器、第五开关管和电流镜电路；其中，
    第三开关管、第四开关管的栅极均连接副功率管的栅极，第四开关管的漏极连接副功率管的漏极，第四开关管的源极连接比较器的正向输入端，第三开关管的源极连接副功率管的源极，第三开关管的漏极连接比较器的反向输入端，比较器的输出端连接第五开关管的栅极，第五开关管的源极连接电阻的一端，电阻的另一端连接第三开关管的漏极，第五开关管的漏极连接电流镜电路的输入端，电流镜电路的输出端连接所述控制芯片的CS引脚；
    所述延时模块为将PWM信号延时一设定时长的模块；所述选择模块为选择是否供电的模块。
  2. 根据权利要求1所述的供电电路，其特征在于，
    在所述控制芯片外部，所述控制芯片的CS引脚通过电阻Rcs连接等电势点。
  3. 根据权利要求1所述的供电电路，其特征在于，
    所述第一开关管为二极管或场效应管。
  4. 根据权利要求1所述的供电电路，其特征在于，所述选择模块包括：比较器、D触发器、与门、非门以及或门，其中，
    所述比较器的正脚连接电压阈值Vm，负脚连接VDD；所述比较器的输出端连接D触发器的D引脚，所述D触发器的CP引脚连接PWM信号，所述PWM信号还连接所述与门的一个输入端，所述与门的另一输入端连接所述D触发器的Q输出端Charge-en；所述D触发器的Q输出端还连接所述非门的输入端，所述非门的输出端连接或门的另一个输入端，所述或门的一个输入端连接所述与门的输出端，所述或门的输出端为所述选择模块的输出端。
  5. 一种镜像电流采样电路，其特征在于，所述镜像电流采样电路包括第三开关管、第四开关管、比较器、第五开关管和电流镜电路；其中，
    第三开关管、第四开关管的栅极均连接副功率管的栅极，第四开关管的漏极连接副功率管的漏极，第四开关管的源极连接比较器的正向输入端，第三开关管的源极连接副功率管的源极，第三开关管的漏极连接比较器的反向输入端，比较器的输出端连接第五开关管的栅极，第五开关管的源极连接电阻的一端，电阻的另一端连接第三开关管的漏极，第五开关管的漏极连接电流镜电路的输入端，电流镜电路的输出端连接控制芯片的CS引脚。
  6. 根据权利要求5所述的镜像电流采样电路，其特征在于，当副功率管导通时，第三开关管以及四开关管导通，电流采样使能，并输出镜像电流至所述控制芯片的CS引脚。
  7. 根据权利要求5所述的镜像电流采样电路，其特征在于，所述镜像电流的大小与流经所述副功率管的电流的大小相关。
  8. 根据权利要求5所述的电路，其特征在于，所述镜像电流和流经副功率管的电流之间的第一比例与副功率管和第三开关管的导通电阻之间的第二比例呈比例关系。
  9. 一种开关电源的供电电路的供电方法，其特征在于，所述方法应用于如 权利要求1-4任意一项所述的开关电源的供电电路，所述方法包括如下步骤：
    若所述控制芯片正常工作且VDD小于电压阈值Vm，供电使能，控制PWM信号输入到所述延时模块和选择模块，所述主功率管相对副功率管滞后导通或关断。
  10. 根据权利要求9所述的方法，其特征在于，所述方法还包括：
    若VDD大于或等于电压阈值Vm，供电不使能，选择模块输出高电平。
  11. 根据权利要求9所述的方法，其特征在于，开关电源的供电电路启动阶段，交流输入通过第二开关管以及启动电阻Rstart1和Rstart2驱动主功率管导通，使VDD上升至启动阈值后控制芯片工作。
  12. 一种开关电源系统，其特征在于，所述开关电源系统包括如权利要求1-4任意一项所述的开关电源的供电电路或如权利要求5-8任意一项所述的镜像电流采样电路。
  13. 一种开关电源系统，其特征在于，所述开关电源系统应用如权利要求9-11任意一项所述方法供电。
PCT/CN2023/090536 2022-04-26 2023-04-25 开关电源的供电电路及其供电方法 WO2023207956A1 (zh)

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