WO2023207386A1 - 一种集成电路高速数字接口通用检测装置及方法 - Google Patents

一种集成电路高速数字接口通用检测装置及方法 Download PDF

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WO2023207386A1
WO2023207386A1 PCT/CN2023/081509 CN2023081509W WO2023207386A1 WO 2023207386 A1 WO2023207386 A1 WO 2023207386A1 CN 2023081509 W CN2023081509 W CN 2023081509W WO 2023207386 A1 WO2023207386 A1 WO 2023207386A1
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test
speed
interface
channel
medium
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PCT/CN2023/081509
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French (fr)
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毛国梁
李全任
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南京宏泰半导体科技股份有限公司
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Publication of WO2023207386A1 publication Critical patent/WO2023207386A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0416—Connectors, terminals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test

Definitions

  • the invention relates to a universal detection device and method for high-speed digital interfaces of integrated circuits, belonging to the field of chip detection technology.
  • TG Timing generator
  • MIPI or PCIe this type of interface has a complete set of complex sending and receiving protocols, and has very strict timing requirements. The timing error is at ps level.
  • DDR To be implemented in the traditional ATE Pattern Generator (PG for short) requires complex instruction set support, and the PG itself must be very fast.
  • the test graphics will be very complex, and there are high requirements on the tester's test program development capabilities.
  • ATE only needs to test the output of the paired chip and indirectly complete the test of the DUT (Device Under Test).
  • This type of test method is the simplest.
  • the paired chip converts the high-speed interface signal into a low-speed signal, and the requirements for ATE are also greatly reduced.
  • this method cannot directly test the AC and DC parameters of the DUT (because there is a paired chip between the ATE and the DUT).
  • ATE cannot directly apply the desired test signal to the DUT through Pattern, and can only generate test timing indirectly through the paired chip. Limited by the functions of the paired chip, some parameters or functions of the DUT may not be fully tested.
  • the second traditional solution is to use the FPGA to simulate the paired chip as a Receiver or Transceiver, that is, to design the same interface protocol and timing as the paired chip in the FPGA for communication between the PG and the DUT.
  • This method is similar to method one.
  • problems of method one there are also problems such as higher cost (the price of FPGA is relatively high) and higher requirements for test engineers (test engineers need to master FPGA development, debugging, etc. capabilities).
  • the advantage is that FPGA can be customized, which solves the problem that the DUT cannot be fully tested due to the functional limitations of the paired chip.
  • the third traditional solution is to use high-end ATE machines for direct testing (such as Advant’s Verigy 93K, etc.).
  • high-end ATE machines to develop complex test pattern programs and directly generate test signals required for high-speed testing through digital channels.
  • This method has the advantages of flexible testing, high test coverage, and convenient debugging.
  • high-end ATE machines often cost hundreds of thousands to millions of dollars, resulting in high testing costs.
  • the present invention provides a universal detection device and method for high-speed digital interfaces of integrated circuits. Considering that in most integrated circuit testing processes, in addition to the need to run high-speed digital signals on the high-speed interface, other The digital signal rate of the IO port is not high (generally tens of Mbps to hundreds of Mbps). In order to maintain the flexibility of high-speed digital interface testing and test integrity while also taking into account the lower cost of testing, the present invention is implemented.
  • the invention integrates the IO port of the mid- to low-end digital ATE machine with the high-speed digital interface test function to form a combinable test device.
  • each medium and low-speed test channel resource can also be switched to a dedicated high-speed test channel as needed.
  • the high-speed test channel and the medium-low speed test channel are synchronized through PG.
  • the high-speed digital channel is implemented through FPGA and front-end dedicated Pin Electronic. Through this device, it can not only meet the medium and low speed test requirements of general IO ports, but also meet the test of high-speed interfaces. Not only can you get the high flexibility of FPGA solutions, but you can also get the lower cost of mid- to low-end ATE machines.
  • corresponding interface template functions are designed so that test developers can complete the development and debugging of test programs without mastering FPGA.
  • a universal detection device for integrated circuit high-speed digital interfaces including a medium-low speed digital test channel motherboard and a high-speed digital interface test channel daughter board, wherein:
  • the medium and low speed digital test channel motherboard includes a motherboard bus interface, a test processor, and a medium and low speed test channel unit.
  • the motherboard bus interface is connected to the test processor and the medium and low speed test channel unit respectively.
  • the test processor is connected to Low and medium speed test channel unit connections.
  • the medium-low speed test channel unit includes more than one medium-low speed test channel group, and each medium-low speed test channel group is provided with a high-speed test channel daughter board interface.
  • the high-speed digital interface test channel daughter board includes a daughter board bus interface, a test processor motherboard interface, an FPGA code configuration generator, a high-speed test channel driver FPGA with a configurable interface protocol, a high-speed test channel unit, and reconfigurable test data processor, the FPGA code configuration generator is used to receive host computer data, complete the reconfiguration of the high-speed test channel driver FPGA of the configurable interface protocol, and the high-speed test channel driver FPGA of the configurable interface protocol is used to directly control the high-speed test channel unit.
  • the daughter board bus interface is respectively connected to the FPGA code configuration generator, the high-speed test channel driver FPGA of the configurable interface protocol, the high-speed test channel unit, and the reconfigurable test data processor
  • the test processor motherboard interface is respectively connected to A high-speed test channel daughter board interface, an FPGA code configuration generator, a high-speed test channel driver of a configurable interface protocol connected to an FPGA, a high-speed test channel unit, and a reconfigurable test data processor, the high-speed test channel driver of the configurable interface protocol
  • Use FPGA to connect to the FPGA code configuration generator, high-speed test channel unit, and reconfigurable test data processor respectively.
  • the test processor motherboard interface is connected to the high-speed test channel sub-board interface of the medium-low speed test channel group and is used to receive control and synchronization signals of the test processor.
  • the test processor is used to execute the test pattern to generate the timing signals required for the test and the control signals required for the test channel, and provide the timing signals required for the test and the control signals required for the test channel to the medium and low speed test channels. Group. At the same time, it is used to generate the control signals required by the high-speed digital interface test channel daughter board, and is used for the synchronization of the high-speed test channel driver FPGA and the test data processor of the configurable interface protocol for each channel driver on the high-speed test channel unit.
  • the medium and low speed test channel group includes channel electronic pins, an input and output level converter and a set of multiplexers.
  • the channel electronic pins are used to complete the DC test of the device to be tested.
  • the input and output levels The converter is used for level conversion of input and output, and the multiplexer is used for outputting multiplexed signals.
  • the high-speed test channel unit includes more than one high-speed test channel.
  • the high-speed test channel corresponds to the medium-low speed test channel group one-to-one.
  • a universal detection method for high-speed digital interfaces of integrated circuits including the following steps:
  • Step 1 write the test graphic pattern. Configure the high-speed interface test protocol in the integrated circuit automatic test equipment ATE software.
  • Step 2 download the test graphics Pattern to the test processor.
  • Step 3 download the high-speed interface test protocol to the FPGA code configuration generator. Download the test data processing program to the reconfigurable test data processor.
  • Step 4 start testing.
  • Step 5 Test the DC parameters of the equipment under test through the medium and low-speed test channel unit. If the test fails, return to step 4. If the test passes, the test processor is started.
  • Step 6 The test processor drives the medium and low speed test channels in the medium and low speed test channel unit, generates test signals to the device under test, and completes the medium and low speed test of the device under test. If the test fails, return to step 4. If the test passes, the test processor switches the multiplexer to the high-speed test channel unit.
  • Step 7 The test processor starts the high-speed test channel driver FPGA of the configurable interface protocol, so that the high-speed test channel unit generates test signals to the device under test, completing high-speed interface testing and data processing of the device under test. If the test fails, return to step 4. If passed, the test ends.
  • the reconfigurable test data processor performs real-time calculation and processing on the test data obtained by the FPGA of the high-speed test channel driver of the configurable interface protocol, and synchronizes the test results to the test processor.
  • the present invention has the following beneficial effects:
  • the present invention allows high-speed digital test channels and medium- and low-speed digital test channels to form a high-low match, which can meet the DUT's requirements for high-speed digital interface test channels to the greatest extent and obtain a relatively high-end test machine. Lower testing costs.
  • the present invention drives the FPGA design through the reconfigurable high-speed channel. While obtaining the high-speed digital interface driving capability of the FPGA, it also realizes the customized and flexible configuration of the driving protocol. At the same time, since the driving protocol is customized and developed for ATE, it can also be Get better test coverage.
  • the independent high-speed channel test daughter board has a built-in structure that can be configured with a dedicated computing processor and memory, so that the hardware has asynchronous data processing and computing capabilities.
  • By configuring multiple daughter cards multiple test stations can be tested simultaneously, which reduces the risk of testing.
  • the problem of system bus resource occupation greatly improves the chip testing efficiency.
  • Figure 1 is a schematic diagram of the medium and low-speed digital test channel motherboard.
  • Figure 2 is a schematic diagram of the high-speed digital interface test channel daughter board.
  • Figure 3 is a schematic diagram of the test processor structure.
  • Figure 4 is a schematic diagram of the test implementation.
  • Figure 5 is a schematic diagram of the process.
  • a universal detection device for high-speed digital interfaces of integrated circuits as shown in Figure 4. Based on the second test method, this embodiment focuses on solving the problem of high test development complexity and reducing test costs. To reduce the complexity of test development, an automatic generation mechanism for FPGA high-speed interface protocol code is needed so that test engineers do not need to develop FPGA. To reduce test costs, high-speed test channels need to be configured on low-speed channels as needed to achieve optimal cost performance, including medium and low-speed digital test channel motherboard 4 and high-speed digital interface test channel daughter board 10, including:
  • the medium and low speed digital test channel motherboard 4 includes a motherboard bus interface 1, a test processor 2, and a medium and low speed test channel unit 3.
  • the motherboard bus interface 1 is connected to the test processor 2 and the medium speed test channel unit 3 respectively.
  • the low-speed test channel unit 3 is connected, and the test processor 2 is connected to the medium-low speed test channel unit 3.
  • the medium-low speed test channel unit 3 includes more than one medium-low speed test channel group, and each medium-low-speed test channel group is provided with a high-speed test channel daughter board interface, wherein:
  • Mid Speed Digital Test Channel Board 4 (MSDTCB for short) is used to execute the test pattern pattern and complete the test signal generation and testing of the medium and low speed IO of the device under test; it also serves as a motherboard to interface with each HSTCB , complete the control and synchronization of each high-speed digital interface test channel sub-board.
  • the motherboard bus interface 1 (Bus Interface, BI for short) is used for data transmission and control between the host computer PC and each device on the board, specifically with the test processor 2, the medium and low speed test channel group 3, and the medium and low speed digital test Data transmission and control between channel boards 4;
  • Test Processor 2 (Test Processor, referred to as TP), as shown in Figure 3, Test Processor 2 includes graphics memory Pattern Memory, memory controller Memory Control, timing generator Timing Generator, pattern generator Pattern Generator, memory controller respectively Connected to graphics memory, timing generator, graphics generator.
  • the test processor 2 is used to execute the test pattern to generate the timing signals required for the test and the control signals required for the test channel, and provide the timing signals required for the test and the control signals required for the test channel to the medium and low-speed test channel group 3; At the same time, the control signals required by each test daughter board are also generated, which are used to synchronize the drive FPGA and test data processor of each channel on the test daughter board.
  • the medium and low speed test channel group is used to generate a set of test signals required for medium and low speed IO testing (generally tens of Hz to hundreds of Mhz), which are directly tested Controlled by Processor 2, it receives the output signal of Test Processor 2 to generate a set of test signals required for medium and low speed IO testing;
  • the medium and low speed test channel group includes a High Speed Test Channel Board (HSTCB for short) interface, channel electronics Pin Electronic (PE for short, composed of PPMU, Driver, Comparator, etc., used to complete DC testing of DUT, input and output level conversion, etc.) and a set of multiplexers Mux; the channel electronic tube
  • the pin is used to complete the DC test of the device under test
  • the input and output level converter is used to convert the input and output levels
  • the multiplexer Mux is used to output the multiplex selection signal.
  • the high-speed digital interface test channel daughter board 10 includes a daughter board bus interface 11, a test processor motherboard interface 5, an FPGA code configuration generator 6, a high-speed test channel driver FPGA 7 with a configurable interface protocol, High-speed test channel unit 8, reconfigurable test data processor 9, the FPGA code configuration generator 6 is used to receive host computer data, complete the reconfiguration of the high-speed test channel driver FPGA 7 of the configurable interface protocol, the configurable interface protocol high speed
  • the test channel driver FPGA7 is used to directly control the high-speed test channel unit 8.
  • the daughter board bus interface 11 is respectively connected to the FPGA code configuration generator 6, the high-speed test channel driver FPGA 7 of the configurable interface protocol, the high-speed test channel unit 8, and the reconfigurable test data processor 9.
  • the test processor mother The board interface 5 is respectively connected to the high-speed test channel daughter board interface, the FPGA code configuration generator 6, the high-speed test channel driver FPGA 7 of the configurable interface protocol, the high-speed test channel unit 8, and the reconfigurable test data processor 9.
  • the high-speed test channel driver FPGA 7 that configures the interface protocol is connected to the FPGA code configuration generator 6, the high-speed test channel unit 8, and the reconfigurable test data processor 9 respectively.
  • the daughter board bus interface 11 is used to test the processor motherboard interface 5, the FPGA code configuration generator 6, the FPGA 7 for high-speed test channel driver of the configurable interface protocol, the high-speed test channel unit 8, and the reconfigurable test data processor 9 data transmission and control between;
  • the test processor motherboard interface 5 is connected to the high-speed test channel sub-board interface of the medium and low-speed test channel group 3, and is used to receive control and synchronization signals of the test processor 2.
  • FPGA Code Config Generator 6 FPGA Code Config Generator, referred to as FCCG
  • FCCG FPGA Code Config Generator
  • FCCG FPGA Code Config Generator
  • HSTCD For example: If you need HSTCD to drive a high-speed test channel to output MIPI D-Phy protocol signals, you can download MIPI D-Phy protocol data to FCCG through PC, and then FCCG configures HSTCD, and HSTCD will become a test channel for MIPI D-Phy protocol. Control generator.
  • FPGA7 High Speed Test Channel Driver, referred to as HSTCD
  • HSTCD High Speed Test Channel Driver
  • FPGA7 for high-speed test channel drivers with configurable interface protocols can be reconfigured by FCCG to provide test channels for various high-speed interface protocols.
  • Universal drive capability is used by HSTCD to directly control the High Speed Test Channel (HSTC), so HSTC can output or match high-speed test signals (from hundreds of Mbps to several Gbps).
  • the high-speed test channel unit 8 includes more than one high-speed test channel (High Speed Test Channel, HSTC for short).
  • Each high-speed test channel consists of a high-speed electronic pin (High Speed Pin Electronic, HSPE for short), which is composed of PPMU, Driver, Comparator It is composed of, etc., used to complete the DC test of the DUT, and the level conversion of input and output, etc.), and the multiplexer Mux;
  • the reconfigurable test data processor 9 (Configable Test Data Processor, CTDP for short) consists of a data memory and a data processor.
  • the test data obtained by the high-speed test channel driver of the configurable interface protocol is calculated and processed in real time using FPGA7, and the test results are synchronized to the test processor.
  • the data processor is composed of multi-core Arm, and the processing program it runs can be downloaded and configured by the PC in real time. Test engineers can write data processing programs through ATE software and download them to CTDP along with the test programs.
  • High Speed Digital Interface Test Channel Daughter Board 10 (High Speed Digital Test Channel Board, referred to as HSDTCB) is used to complete the test signal generation and testing of the high speed digital interface on the DUT, as well as real-time data processing and analysis.
  • HSDTCB High Speed Digital Test Channel Board
  • the test processor motherboard interface 5 is connected to the high-speed test channel daughter board of the medium-low speed test channel group 3, so that the medium-low speed digital test channel motherboard 4 and the high-speed digital interface test channel daughter board 10 form a daughter-mother card relationship.
  • Each test channel output of the medium and low speed digital test channel motherboard 4 and each test channel output of the high speed digital interface test channel daughter board 10 are connected through their respective multiplexers Mux.
  • the test processor 2 switches the high-speed or medium-low speed test channels and outputs them to the device under test DUT according to the test needs, thereby completing the general test purpose of high-low matching.
  • the high-speed digital interface test channel daughter board 10 includes a group of high-speed digital interface test channels, which corresponds one-to-one to the medium- and low-speed test channel groups of the medium- and low-speed digital test channel motherboard 4 .
  • the test of the high-speed digital interface on the device under test DUT can be According to the channel requirements, select a corresponding number of high-speed digital interface test channel boards and install them on the medium- and low-speed digital test channel motherboard 4. This can maximize test performance while reducing test costs and obtaining the best price/performance ratio.
  • a universal detection method for high-speed digital interfaces of integrated circuits includes the following steps:
  • Step 1 write the test graphic pattern. Configure the high-speed interface test protocol in the integrated circuit automatic test equipment ATE software.
  • Step 2 download the test graphics Pattern to test processor 2.
  • Step 3 download the high-speed interface test protocol to the FPGA code configuration generator 6. Download the test data processing program to the reconfigurable test data processor 9.
  • Step 4 start testing.
  • Step 5 Test the Open Short and other DC parameters of the device under test through the medium and low-speed test channel unit 3. If the test fails, return to step 4. If the test passes, test processor 2 is started.
  • Step 6 The test processor 2 drives the medium-low speed test channel in the medium-low speed test channel unit 3, generates a test signal to the device under test, and completes the medium-low speed test of the device under test. If the test fails, return to step 4. If the test passes, the test processor 2 switches the multiplexer Mux to the high-speed test channel unit 8.
  • Step 7 The test processor 2 starts the high-speed test channel driver FPGA 7 of the configurable interface protocol, so that the high-speed test channel unit 8 generates test signals to the device under test to complete the high-speed interface test and data processing of the device under test.
  • the reconfigurable test data processor 9 performs real-time calculation processing on the test data obtained by the FPGA 7 of the high-speed test channel driver of the configurable interface protocol, and synchronously provides the test results to the test processor 2. If the test fails, return to step 4. If passed, the test ends.
  • a high-speed digital test channel sub-board is added to a medium-low speed test channel board to complete the testing of the medium-low speed IO and high-speed digital interface of the DUT at the same time.

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Abstract

一种集成电路高速数字接口通用检测装置及方法，包括中低速数字测试通道母板（4）和高速数字接口测试通道子板（10），中低速数字测试通道母板（4）包括测试处理器（2）、中低速测试通道单元（3），中低速测试通道组上设置有高速测试通道子板接口；高速数字接口测试通道子板（10）包括测试处理器母板接口（5）、FPGA代码配置发生器（6）、可配置接口协议的高速测试通道驱动用FPGA（7）、高速测试通道单元（8）、可重配置测试数据处理器（9），测试处理器母板接口（5）与中低速测试通道组的高速测试通道子板接口连接。该装置既可以满足一般IO口的中低速测试要求，也可以满足高速接口的测试。既可以获得FPGA方案的高灵活性，同时可以获得中低端ATE机台的较低成本。

Description

一种集成电路高速数字接口通用检测装置及方法 技术领域
本发明涉及一种集成电路高速数字接口通用检测装置及方法，属于芯片检测技术领域。
背景技术
由于现代数字集成电路越来越多的采用了高速数字接口进行设计，例如：MIPI,HDMI,Serdes,DDR,USB,PCIe等。该类数字接口数据传输速度从几百Mbps到几Gbps不等，物理接口类型从LVCMOS，LVDS，到LVPECL或CML等。在ATE(Auto Test Equipment，自动测试设备)中，要进行此类信号的检测面临比较大的挑战。一是超高的测试频率。动辄几百Mbps到上Gbps的数据传输速度，导致接口电平变化频率高达几百MHz到上GHz，如果采用传统ATE的Timing Generator(时序发生器，简称TG)进行测试，设备成本太高(基本需要最高端的ATE才能具备，或者需要牺牲大量测试通道换取更高的测试data rate)。二是复杂的接口时序与协议。例如MIPI或PCIe，该类接口都具有一整套复杂的收发协议，且对时序要求非常苛刻。时序误差在ps级别。对于DDR之类的接口还有异步并发测试要求。要在传统ATE的Pattern Generater(图形发生器，简称PG)中实现，需要复杂的指令集支持，而且PG本身速度要很高。测试图形会很复杂，对测试人员的测试程序开发能力也有很高的要求。三是种类多样的接口电平模式，一般的ATE数字测试IO口无法满足要求。
传统解决方法一，使用配对芯片作为Receiver或Transceiver，ATE只要测试配对芯片的输出，间接完成对DUT(Device Under Test)的测试。该类测试方法最简单，配对芯片将高速接口信号转为了低速信号，对ATE的要求也大大降低。但该类方法无法直接对DUT的交直流参数进行测试(因为ATE和DUT之间隔了一个配对芯片)。此外，ATE无法通过Pattern直接施加期望的测试信号给DUT，只能通过配对芯片间接产生测试时序。受限于配对芯片的功能，可能DUT的部分参数或功能无法完整测试。
传统解决方法二，使用FPGA模拟配对芯片作为Receiver或Transceiver，即在FPGA内设计与配对芯片相同的接口协议和时序，用以PG和DUT进行通讯。该方法与方法一类似，除了具有方法一的问题外，还有成本更高(FPGA的价格比较高)，对测试工程师要求更高(需要测试工程师掌握FPGA的开发，调试等能力)等问题。好处是FPGA可以定制，解决方法一因配对芯片功能限制导致对DUT无法完整测试的问题。
传统解决方法三，使用高端ATE机台直接测试(例如爱德万的Verigy 93K等)。使用高端ATE机台开发复杂的测试图形程序,通过数字通道直接产生高速测试所需的测试信号。该方法具有测试灵活，测试覆盖率高，调试方便等优点，但是缺点是高端ATE机台售价动辄几十万到上百万美金，导致测试成本太高。
由上可知，传统测试方法一，存在测试覆盖率低，测试效率低的问题。传统测试方法二，存在测试开发复杂度高的问题。传统测试方法三，存在测试成本太高的问题。总之，各个传统测试方案无法在测试的低成本、测试开发的高灵活性、测试开发低复杂度及测试方案的高覆盖率方面兼得。各方面问题都会推高设计公司在IC测试过程中的测试成本。
发明内容
发明目的：为了克服现有技术中存在的不足，本发明提供一种集成电路高速数字接口通用检测装置及方法，考虑到大多数集成电路测试过程中，除了高速接口上需要跑高速数字信号，其他IO口的数字信号速率要求不高(一般几十Mbps到几百Mbps)。为了保持对高速数字接口测试的灵活性，测试完整性的同时，还可以兼顾测试的较低成本，故实现了本发明。本发明将中低端数字ATE机台的IO口与高速数字接口测试功能进行整合，形成一个可组合的测试装置。即每个中低速测试通道资源，也可以根据需要切换到专用高速测试通道。高速测试通道与中低速测试通道通过PG进行同步。高速数字通道通过FPGA与前端专用Pin Electronic实现。通过该装置，既可以满足一般IO口的中低速测试要求，也可以满足高速接口的测试。既可以获得FPGA方案的高灵活性，同时可以获得中低端ATE机台的较低成本。为了解决FPGA方案的开发复杂度，设计了相应的接口模板功能，使得测试开发人员可以在不掌握FPGA的情况下完成测试程序的开发调试。
技术方案：为实现上述目的，本发明采用的技术方案为：
一种集成电路高速数字接口通用检测装置，包括中低速数字测试通道母板和高速数字接口测试通道子板，其中：
所述中低速数字测试通道母板包括母板总线接口、测试处理器、中低速测试通道单元，所述母板总线接口分别与测试处理器、中低速测试通道单元连接，所述测试处理器与中低速测试通道单元连接。所述中低速测试通道单元包括一组以上的中低速测试通道组，每组中低速测试通道组上设置有高速测试通道子板接口。
所述高速数字接口测试通道子板包括子板总线接口、测试处理器母板接口、FPGA代码配置发生器、可配置接口协议的高速测试通道驱动用FPGA、高速测试通道单元、可重配置测试数据处理器，所述FPGA代码配置发生器用于接收上位机数据，完成对可配置接口协议的高速测试通道驱动用FPGA的重配置，可配置接口协议的高速测试通道驱动用FPGA用于直接控制高速测试通道单元。所述子板总线接口分别与FPGA代码配置发生器、可配置接口协议的高速测试通道驱动用FPGA、高速测试通道单元、可重配置测试数据处理器连接，所述测试处理器母板接口分别与高速测试通道子板接口、FPGA代码配置发生器、可配置接口协议的高速测试通道驱动用FPGA、高速测试通道单元、可重配置测试数据处理器连接，所述可配置接口协议的高速测试通道驱动用FPGA分别与FPGA代码配置发生器、高速测试通道单元、可重配置测试数据处理器连接。所述测试处理器母板接口与中低速测试通道组的高速测试通道子板接口连接，用于接收测试处理器的控制与同步信号。
优选的：所述测试处理器用于执行测试图形产生测试所需的时序信号及测试通道所需的控制信号，并将测试所需的时序信号与测试通道所需的控制信号提供给中低速测试通道组。同时用于产生高速数字接口测试通道子板所需的控制信号，用于高速测试通道单元上各个通道驱动可配置接口协议的高速测试通道驱动用FPGA及测试数据处理器的同步。
优选的：所述中低速测试通道组包括通道电子管脚、输入输出电平转换器以及一组多路选择器，所述通道电子管脚用于完成待测试设备的直流测试，输入输出电平转换器用于输入输出的电平转换，多路选择器用于输出多路选择信号。
优选的：所述高速测试通道单元包括一个以上的高速测试通道。
优选的：所述高速测试通道与中低速测试通道组一一对应。
一种集成电路高速数字接口通用检测方法，包括以下步骤：
步骤1，编写测试图形Pattern。在集成电路自动测试设备ATE软件中配置高速接口测试协议。
步骤2，下载测试图形Pattern到测试处理器。
步骤3，下载高速接口测试协议到FPGA代码配置发生器。下载测试数据处理程序到可重配置测试数据处理器。
步骤4，开始测试。
步骤5，通过中低速测试通道单元测试待测试设备直流参数。如果测试失败，返回步骤4。如果测试通过，则启动测试处理器。
步骤6，测试处理器驱动中低速测试通道单元中的中低速测试通道，产生测试信号给待测试设备，完成待测试设备的中低速测试。如果测试失败，返回步骤4。如果测试通过，则测试处理器将多路选择器切换到高速测试通道单元。
步骤7，测试处理器启动可配置接口协议的高速测试通道驱动用FPGA，使得高速测试通道单元产生测试信号给待测试设备，完成待测试设备的高速接口测试及数据处理。如果测试失败，返回步骤4。如果通过，测试结束。
优选的：可重配置测试数据处理器对可配置接口协议的高速测试通道驱动用FPGA获取的测试数据进行实时的计算处理，并同步给测试处理器测试结果。
本发明相比现有技术，具有以下有益效果：
1.本发明通过高速通道测试子板的设计，让高速数字测试通道与中低速数字测试通道形成高低搭配，可以在最大程度满足DUT对高速数字接口测试通道要求的基础上，获得相对高端测试机台更低的测试成本。
2.本发明通过可重配置高速通道驱动FPGA设计，在获得FPGA的高速数字接口驱动能力的同时，也实现了驱动协议的自定义灵活配置，同时由于驱动协议是为ATE定制开发的，也可以获得较好的测试覆盖率。
3.通过ATE软件进行预制驱动协议的编辑，配置与下载，可以解决FPGA使用复杂度。使得测试工程师可以在不需要对FPGA进行RTL开发与调试的情况下，完成各类高速数字接口协议的测试程序开发。
4.独立高速通道测试子板内置可配置专用计算处理器与存储器的结构，使得硬件具备异步数据处理与计算能力，并且通过配置多块子卡可实现多测试站并测，降低了测试时对系统总线资源的占用问题，极大的提高了芯片的测试效率。
附图说明
图1为中低速数字测试通道母板示意图。
图2为高速数字接口测试通道子板示意图。
图3为测试处理器结构示意图。
图4为测试实施示意图。
图5为流程示意图。
具体实施方式
下面结合附图和具体实施例，进一步阐明本发明，应理解这些实例仅用于说明本发明而不用于限制本发明的范围，在阅读了本发明之后，本领域技术人员对本发明的各种等价形式的修改均落于本申请所附权利要求所限定的范围。
一种集成电路高速数字接口通用检测装置，如图4所示，本实施例在测试方法二的基础上，重点解决测试开发复杂度高的问题，及降低测试成本。要降低测试开发复杂度，就需要有一个FPGA高速接口协议代码的自动生成机制，让测试工程师不需要进行FPGA的开发。要降低测试成本，则需要让高速测试通道根据需要配置到低速通道上，实现最优的性价比，包括中低速数字测试通道母板4和高速数字接口测试通道子板10，其中：
如图1所示，所述中低速数字测试通道母板4包括母板总线接口1、测试处理器2、中低速测试通道单元3，所述母板总线接口1分别与测试处理器2、中低速测试通道单元3连接，所述测试处理器2与中低速测试通道单元3连接。所述中低速测试通道单元3包括一组以上的中低速测试通道组，每组中低速测试通道组上设置有高速测试通道子板接口，其中：
中低速数字测试通道板4(Mid Speed Digital Test Channel Board,简称MSDTCB)，用于执行测试图形Pattern，完成待测试设备的中低速IO的测试信号发生与测试；同时作为母板，与各个HSTCB接口，完成对各个高速数字接口测试通道子板的控制与同步。
所述母板总线接口1(Bus Interface,简称BI)，用于上位机PC与板上各个器件的数据传输与控制，具体为与测试处理器2、中低速测试通道组3、中低速数字测试通道板4之间的数据传输与控制；
测试处理器2(Test Processor,简称TP)，如图3所示，测试处理器2包括图形存储器Pattern Memory、存储控制器Memory Control、时序发生器Timing Generator、图形发生器Pattern Generator，存储控制器分别与图形存储器、时序发生器、图形发生器连接。测试处理器2用于执行测试图形产生测试所需的时序信号及测试通道所需的控制信号，并将测试所需的时序信号与测试通道所需的控制信号提供给中低速测试通道组3；同时也产生各个测试子板所需的控制信号，用于测试子板上各个通道驱动FPGA及测试数据处理器的同步。即用于产生高速数字接口测试通道子板10所需的控制信号，用于高速测试通道单元8上各个通道驱动可配置接口协议的高速测试通道驱动用FPGA7及测试数据处理器的同步。
中低速测试通道组(Mid Speed Test Channel Group,简称MSTCG)，中低速测试通道组用于产生一组中低速IO测试所需的测试信号(一般为几十Hz到几百Mhz)，直接受测试处理器2控制，接收测试处理器2输出信号产生一组中低速IO测试所需的测试信号；中低速测试通道组包括高速测试通道子板(High Speed Test Channel Board，简称HSTCB)接口、通道电子管脚(Pin Electronic，简称PE，由PPMU,Driver,Comparator等组成，用于完成DUT的直流测试，及输入输出的电平转换等)以及一组多路选择器Mux组成；所述通道电子管脚用于完成待测试设备的直流测试，输入输出电平转换器用于输入输出的电平转换，多路选择器Mux用于输出多路选择信号。
如图2所示，所述高速数字接口测试通道子板10包括子板总线接口11、测试处理器母板接口5、FPGA代码配置发生器6、可配置接口协议的高速测试通道驱动用FPGA7、高速测试通道单元8、可重配置测试数据处理器9，所述FPGA代码配置发生器6用于接收上位机数据，完成对可配置接口协议的高速测试通道驱动用FPGA7的重配置，可配置接口协议的高速 测试通道驱动用FPGA7用于直接控制高速测试通道单元8。所述子板总线接口11分别与FPGA代码配置发生器6、可配置接口协议的高速测试通道驱动用FPGA7、高速测试通道单元8、可重配置测试数据处理器9连接，所述测试处理器母板接口5分别与高速测试通道子板接口、FPGA代码配置发生器6、可配置接口协议的高速测试通道驱动用FPGA7、高速测试通道单元8、可重配置测试数据处理器9连接，所述可配置接口协议的高速测试通道驱动用FPGA7分别与FPGA代码配置发生器6、高速测试通道单元8、可重配置测试数据处理器9连接。
所述子板总线接口11用于测试处理器母板接口5、FPGA代码配置发生器6、可配置接口协议的高速测试通道驱动用FPGA7、高速测试通道单元8、可重配置测试数据处理器9之间的数据传输与控制；
所述测试处理器母板接口5与中低速测试通道组3的高速测试通道子板接口连接，用于接收测试处理器2的控制与同步信号。
FPGA代码配置发生器6(FPGA Code Config Generator,简称FCCG)，用于接收上位机PC数据，完成对可配置接口协议的高速测试通道驱动用FPGA7的重配置；PC上位机软件会为各类高速数字接口预制一系列相应的驱动协议的FPGA RTL代码，测试工程师只需要根据测试需求选择相应的协议代码进行配置与下载，就可以实现对各类高速数字接口的测试程序开发。例如：如果需要HSTCD驱动高速测试通道输出MIPI D-Phy协议信号，则可通过PC为FCCG下载MIPI D-Phy协议的数据，FCCG再配置HSTCD，HSTCD就会变成MIPI D-Phy协议的测试通道控制发生器。
可配置接口协议的高速测试通道驱动用FPGA7(High Speed Test Channel Driver,简称HSTCD)，可配置接口协议的高速测试通道驱动用FPGA7可由FCCG进行重配置，从而具备针对各类高速接口协议的测试通道通用驱动能力，用于HSTCD直接控制高速测试通道(High Speed Test Channel,简称HSTC)，所以HSTC可以输出或匹配高速的测试信号(可从几百Mbps到几Gbps)。
所述高速测试通道单元8包括一个以上的高速测试通道(High Speed Test Channel,简称HSTC)，每个高速测试通道由一个高速电子管脚(High Speed Pin Electronic，简称HSPE，由PPMU,Driver,Comparator等组成，用于完成DUT的直流测试，及输入输出的电平转换等)、多路选择器Mux组成；
可重配置测试数据处理器9(Configable Test Data Processor,简称CTDP)，由数据存储器及数据处理器组成。通过对可配置接口协议的高速测试通道驱动用FPGA7获取的测试数据进行实时的计算处理，并同步给测试处理器测试结果。数据处理器由多核Arm组成，其运行的处理程序可由PC进行实时下载配置。测试工程师可以通过ATE软件编写数据处理程序，随测试程序一同下载到CTDP。
高速数字接口测试通道子板10(High Speed Digital Test Channel Board，简称HSDTCB)用于完成DUT上高速数字接口的测试信号发生与测试，及实时数据处理分析。
其中所述测试处理器母板接口5与中低速测试通道组3的高速测试通道子板接口连接，使得中低速数字测试通道母板4和高速数字接口测试通道子板10形成子母卡关系。中低速数字测试通道母板4的各个测试通道输出，及高速数字接口测试通道子板10的各个测试通道输出通过各自的多路选择器Mux连接。由测试处理器2根据测试需要，切换高速或中低速测试通道输出给待测试设备DUT，从而完成高低搭配的通用测试目的。
高速数字接口测试通道子板10包含了一组高速数字接口测试通道，与中低速数字测试通道母板4的中低速测试通道组一一对应。鉴于高速数字接口测试通道子板10上的测试通道相对于中低速数字测试通道母板4上测试通道成本更高，所以在实际的测试方案中，可以根据待测试设备DUT上高速数字接口的测试通道要求，选择相应数量的高速数字接口测试通道板安装到中低速数字测试通道母板4上。这样可最大程度的提高测试性能，同时降低测试成本，获得最佳的性价比。
一种集成电路高速数字接口通用检测方法，如图5所示，包括以下步骤：
步骤1，编写测试图形Pattern。在集成电路自动测试设备ATE软件中配置高速接口测试协议。
步骤2，下载测试图形Pattern到测试处理器2。
步骤3，下载高速接口测试协议到FPGA代码配置发生器6。下载测试数据处理程序到可重配置测试数据处理器9。
步骤4，开始测试。
步骤5，通过中低速测试通道单元3测试待测试设备的Open Short等直流参数。如果测试失败，返回步骤4。如果测试通过，则启动测试处理器2。
步骤6，测试处理器2驱动中低速测试通道单元3中的中低速测试通道，产生测试信号给待测试设备，完成待测试设备的中低速测试。如果测试失败，返回步骤4。如果测试通过，则测试处理器2将多路选择器Mux切换到高速测试通道单元8。
步骤7，测试处理器2启动可配置接口协议的高速测试通道驱动用FPGA7，使得高速测试通道单元8产生测试信号给待测试设备，完成待测试设备的高速接口测试及数据处理。可重配置测试数据处理器9对可配置接口协议的高速测试通道驱动用FPGA7获取的测试数据进行实时的计算处理，并同步给测试处理器2测试结果。如果测试失败，返回步骤4。如果通过，测试结束。
本实施例在一个中低速测试通道板卡上，增加一个高速数字测试通道子板，即可同时完成DUT的中低速IO与高速数字接口的测试。
以上所述仅是本发明的优选实施方式，应当指出：对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (7)

  1. 一种集成电路高速数字接口通用检测装置，其特征在于：包括中低速数字测试通道母板(4)和高速数字接口测试通道子板(10)，其中：
    所述中低速数字测试通道母板(4)包括母板总线接口(1)、测试处理器(2)、中低速测试通道单元(3)，所述母板总线接口(1)分别与测试处理器(2)、中低速测试通道单元(3)连接，所述测试处理器(2)与中低速测试通道单元(3)连接；所述中低速测试通道单元(3)包括一组以上的中低速测试通道组，每组中低速测试通道组上设置有高速测试通道子板接口；
    所述高速数字接口测试通道子板(10)包括子板总线接口(11)、测试处理器母板接口(5)、FPGA代码配置发生器(6)、可配置接口协议的高速测试通道驱动用FPGA(7)、高速测试通道单元(8)、可重配置测试数据处理器(9)，所述FPGA代码配置发生器(6)用于接收上位机数据，完成对可配置接口协议的高速测试通道驱动用FPGA(7)的重配置，可配置接口协议的高速测试通道驱动用FPGA(7)用于直接控制高速测试通道单元(8)；所述子板总线接口(11)分别与FPGA代码配置发生器(6)、可配置接口协议的高速测试通道驱动用FPGA(7)、高速测试通道单元(8)、可重配置测试数据处理器(9)连接，所述测试处理器母板接口(5)分别与高速测试通道子板接口、FPGA代码配置发生器(6)、可配置接口协议的高速测试通道驱动用FPGA(7)、高速测试通道单元(8)、可重配置测试数据处理器(9)连接，所述可配置接口协议的高速测试通道驱动用FPGA(7)分别与FPGA代码配置发生器(6)、高速测试通道单元(8)、可重配置测试数据处理器(9)连接；所述测试处理器母板接口(5)与中低速测试通道组(3)的高速测试通道子板接口连接，用于接收测试处理器(2)的控制与同步信号。
  2. 根据权利要求1所述集成电路高速数字接口通用检测装置，其特征在于：所述测试处理器(2)用于执行测试图形产生测试所需的时序信号及测试通道所需的控制信号，并将测试所需的时序信号与测试通道所需的控制信号提供给中低速测试通道组(3)；同时用于产生高速数字接口测试通道子板(10)所需的控制信号，用于高速测试通道单元(8)上各个通道驱动可配置接口协议的高速测试通道驱动用FPGA(7)及测试数据处理器的同步。
  3. 根据权利要求2所述集成电路高速数字接口通用检测装置，其特征在于：所述中低速测试通道组包括通道电子管脚、输入输出电平转换器以及一组多路选择器，所述通道电子管脚用于完成待测试设备的直流测试，输入输出电平转换器用于输入输出的电平转换，多路选择器用于输出多路选择信号。
  4. 根据权利要求3所述集成电路高速数字接口通用检测装置，其特征在于：所述高速测试通道单元(8)包括一个以上的高速测试通道。
  5. 根据权利要求4所述集成电路高速数字接口通用检测装置，其特征在于：所述高速测试通道与中低速测试通道组一一对应。
  6. 一种基于权利要求1所述集成电路高速数字接口通用检测装置的检测方法，其特征在于，包括以下步骤：
    步骤1，编写测试图形Pattern；在集成电路自动测试设备ATE软件中配置高速接口测试协议；
    步骤2，下载测试图形Pattern到测试处理器(2)；
    步骤3，下载高速接口测试协议到FPGA代码配置发生器(6)；下载测试数据处理程序到可重配置测试数据处理器(9)；
    步骤4，开始测试；
    步骤5，通过中低速测试通道单元(3)测试待测试设备直流参数；如果测试失败，返回步骤4；如果测试通过，则启动测试处理器(2)；
    步骤6，测试处理器(2)驱动中低速测试通道单元(3)中的中低速测试通道，产生测试信号给待测试设备，完成待测试设备的中低速测试；如果测试失败，返回步骤4；如果测试通过，则测试处理器(2)将多路选择器切换到高速测试通道单元(8)；
    步骤7，测试处理器(2)启动可配置接口协议的高速测试通道驱动用FPGA(7)，使得高速测试通道单元(8)产生测试信号给待测试设备，完成待测试设备的高速接口测试及数据处理；如果测试失败，返回步骤4；如果通过，测试结束。
  7. 根据权利要求6所述的检测方法，其特征在于：可重配置测试数据处理器(9)对可配置接口协议的高速测试通道驱动用FPGA(7)获取的测试数据进行实时的计算处理，并同步给测试处理器(2)测试结果。
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