WO2023207318A9 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023207318A9
WO2023207318A9 PCT/CN2023/078983 CN2023078983W WO2023207318A9 WO 2023207318 A9 WO2023207318 A9 WO 2023207318A9 CN 2023078983 W CN2023078983 W CN 2023078983W WO 2023207318 A9 WO2023207318 A9 WO 2023207318A9
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WO
WIPO (PCT)
Prior art keywords
pixel
sub
light
substrate
emitting device
Prior art date
Application number
PCT/CN2023/078983
Other languages
English (en)
French (fr)
Other versions
WO2023207318A1 (zh
Inventor
刘珂
方飞
石领
郭丹
丁小琪
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2023207318A1 publication Critical patent/WO2023207318A1/zh
Publication of WO2023207318A9 publication Critical patent/WO2023207318A9/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • OLED organic light-emitting diode, organic light-emitting diode
  • OLED display devices are widely used because of their characteristics of self-illumination, fast response, wide viewing angle, and can be produced on flexible substrates.
  • OLED display devices include multiple sub-pixels. Each sub-pixel includes a pixel driving circuit and a light-emitting device. The pixel driving circuit drives the light-emitting device to emit light, thereby realizing display.
  • a display panel includes: a substrate and a plurality of first pixel units.
  • the plurality of first pixel units are located on one side of the substrate and are arranged in multiple rows and multiple columns; wherein the first pixel unit includes a plurality of sub-pixels, and the sub-pixels include a pixel driving circuit and a light emitting circuit. device; the light-emitting device is located on a side of the pixel driving circuit away from the substrate and is electrically connected to the pixel driving circuit; the pixel driving circuit includes a first reset transistor.
  • the plurality of sub-pixels include a first sub-pixel, a second sub-pixel and a third sub-pixel, and the area of the light-emitting device of the first sub-pixel is larger than the area of the light-emitting device of the second sub-pixel and larger than the area of the light-emitting device of the second sub-pixel.
  • the area of the light-emitting device of the third sub-pixel is larger than the area of the light-emitting device of the second sub-pixel and larger than the area of the light-emitting device of the second sub-pixel.
  • the orthographic projection of the first reset transistor in the second sub-pixel and/or the first reset transistor in the third sub-pixel on the substrate, and the light-emitting device located in the first sub-pixel is on the within the orthographic projection on the substrate.
  • the first reset transistor of the first subpixel, the first reset transistor of the second subpixel, and the first reset transistor of the third subpixel are all located in the first subpixel.
  • the light-emitting device is within the orthographic projection of the substrate.
  • At least two of the first reset transistor of the first subpixel, the first reset transistor of the second subpixel, and the first reset transistor of the third subpixel are the same transistor. .
  • the pixel driving circuit further includes a second reset transistor; a second reset transistor of the first subpixel, a second reset transistor of the second subpixel, and a third subpixel of the third subpixel.
  • the two reset transistors are the same transistor; the orthographic projection of the second reset transistor on the substrate is located within the orthographic projection of the light-emitting device of the first sub-pixel on the substrate; so The second reset transistor is connected in series with any of the first reset transistors.
  • the display panel also includes a reset signal line and an initialization signal line; the control electrodes of each of the first reset transistor and the second reset transistor are electrically connected to the reset signal line; the second reset transistor The first electrode of the second reset transistor is electrically connected to the initialization signal line, and the second electrode of the second reset transistor is electrically connected to the first electrode of each of the first reset transistors.
  • the pixel driving circuit further includes a driving transistor, and the control electrode of each driving transistor of the pixel driving circuit is electrically connected to the second electrode of each first reset transistor.
  • the light-emitting device of the second sub-pixel and the light-emitting device of the third sub-pixel are spaced apart along the column direction; the light-emitting device of the first sub-pixel is located on the light-emitting device of the second sub-pixel.
  • the device and the light-emitting device of the third sub-pixel are adjacent columns of the column; and the light-emitting device of the first sub-pixel crosses the light-emitting device of the second sub-pixel and the light-emitting device of the third sub-pixel. the gap area between.
  • the pixel driving circuit further includes a circuit main body; the orthographic projection of the circuit main body of the first sub-pixel on the substrate is located within the orthographic projection of the light-emitting device of the first sub-pixel on the substrate, The orthographic projection of the circuit body of the second sub-pixel on the substrate is located within the orthographic projection of the light-emitting device of the second sub-pixel on the substrate, and the circuit body of the third sub-pixel is within The orthographic projection on the substrate is located within the orthographic projection of the light-emitting device of the third sub-pixel on the substrate.
  • the second reset transistor, the first reset transistor of the third sub-pixel, and the first reset transistor of the second sub-pixel are located close to the first reset transistor of the first sub-pixel.
  • the reset signal line extends along the row direction, and one reset signal line is connected to the control electrode of the second reset transistor in the first pixel unit in one row and the control electrode of each first reset transistor.
  • the initialization signal line extends along the row direction, and one of the initialization signal lines is electrically connected to the first electrode of the second reset crystal in the first pixel unit of a row.
  • the orthographic projection of the second reset transistor and each of the first reset transistors on the substrate is located between the orthographic projection of the initialization signal line electrically connected to the second reset transistor on the substrate and the
  • the circuit main body of the third sub-pixel is between the orthographic projection of the reset signal line on the substrate, the orthographic projection of the reset signal line on the substrate, and the orthographic projection of the initialization signal line on the substrate.
  • the circuit body of the third sub-pixel is between the orthographic projections on the substrate.
  • the substrate includes a first display area, and the plurality of first pixel units are located in the first display area.
  • the display panel also includes: a plurality of signal lines located between the substrate and the light-emitting device; at least one signal line located in the first display area includes metal traces and transparent connections that are electrically connected to each other. Traces; the orthographic projection of at least part of the metal traces on the substrate is located within the orthographic projection of the light-emitting device on the substrate.
  • the display panel includes: a first gate metal layer and a first transparent wiring layer, both located between the substrate and the light-emitting device, the first transparent wiring layer is located on the A side of the first gate metal layer facing away from the substrate.
  • the at least one signal line includes a reset signal line, the reset signal line extends along the row direction, and one of the reset signal lines is connected to the control electrode of the second reset transistor in the first pixel unit in a row and each first reset The control electrode of the transistor is electrically connected.
  • the metal wiring of the reset signal line is located on the first gate metal layer, and at least part of the orthographic projection of the metal wiring of the reset signal line on the substrate is located on the light-emitting device of the first sub-pixel.
  • the transparent connection traces of the reset signal line are located on the first transparent trace layer; the orthographic projection of the transparent connection traces of the reset signal line on the substrate , located outside the orthographic projection of the light-emitting device of the second sub-pixel on the substrate, and located outside the orthographic projection of the light-emitting device of the third sub-pixel on the substrate; the reset signal
  • the transparent connecting trace of the line is connected to the metal trace of the reset signal line through a via hole.
  • the circuit body of the pixel driving circuit includes a writing transistor, a compensation transistor and a third reset transistor; the at least one signal line also includes a scanning signal line, and one of the scanning signal lines is connected to a row of the third reset transistor.
  • the control electrodes of the writing transistors, the control electrodes of the compensation transistors and the control electrodes of the third reset transistor of all the sub-pixels in a pixel unit are electrically connected.
  • the metal traces of the scanning signal lines are located on the first gate metal layer, and at least part of the orthographic projection of the metal traces of the scanning signal lines on the substrate is located on the substrate of the light-emitting device. Within the orthographic projection on connect.
  • the circuit body of the pixel driving circuit also includes a first light-emitting control transistor and a second light-emitting control transistor; the at least one signal line further includes a light-emitting control signal line, and one of the light-emitting control signal lines is connected to one row of light-emitting control transistors.
  • the control electrodes of the first light-emitting control transistors and the control electrodes of the second light-emitting control transistors of all the sub-pixels in the first pixel unit are electrically connected.
  • the metal wiring of the light-emitting control signal line is located on the first gate metal layer, and at least part of the orthographic projection of the metal wiring of the light-emitting control signal line on the substrate is located on the light-emitting device on the Within the orthographic projection on the substrate; the transparent connection traces of the light-emitting control signal lines are located on the third A transparent wiring layer, the transparent connecting wiring of the light-emitting control signal line and the metal wiring of the light-emitting control signal line are connected through via holes.
  • the display panel includes: a first source-drain metal layer and a first transparent wiring layer, both located between the substrate and the light-emitting device, and the first transparent wiring layer is located between the substrate and the light-emitting device. The side of the first source and drain metal layer facing away from the substrate.
  • the at least one signal line also includes: an initialization signal line, one of the initialization signal lines is electrically connected to the first pole of the second reset crystal in a row of the first pixel unit; the metal wiring of the initialization signal line Located on the first source and drain metal layer, at least part of the orthographic projection of the metal trace of the initialization signal line on the substrate is located on the orthographic projection of the light-emitting device of the first sub-pixel on the substrate.
  • the transparent connection wiring of the initialization signal line is located on the first transparent wiring layer; the orthographic projection of the transparent connection wiring of the initialization signal line on the substrate is located on the second sub-pixel.
  • the light-emitting device is outside the orthographic projection on the substrate, and is located outside the orthographic projection of the light-emitting device of the third sub-pixel on the substrate; the transparent connection wiring of the initialization signal line is connected to the orthographic projection of the light-emitting device of the third sub-pixel.
  • the metal traces of the initialization signal lines are connected through vias.
  • the display panel includes: a second gate metal layer, a second source-drain metal layer and a second transparent wiring layer, located between the substrate and the light-emitting device, the second source The drain metal layer is located on a side of the second gate metal layer facing away from the substrate, and the second transparent wiring layer is located on a side of the second source-drain metal layer facing away from the second gate metal layer.
  • the circuit body of the pixel driving circuit further includes a capacitor, the first plate of the capacitor is located on the second gate metal layer.
  • the at least one signal line further includes a first power signal line extending along the column direction, and one of the first power signal lines is connected to the second sub-pixel in the first pixel unit in a column.
  • the first plate of the capacitor is electrically connected to the first plate of the capacitor of the third sub-pixel.
  • the metal traces of the first power signal line are located on the second source and drain metal layer, and at least part of the orthographic projection of the metal traces of the first power signal line on the substrate is located on the second sub-substrate.
  • the light-emitting device of the pixel and the light-emitting device of the third sub-pixel are within the orthographic projection on the substrate; the transparent connection wiring of the first power supply signal line is located on the second transparent wiring layer, so The transparent connecting trace of the first power signal line and the metal trace of the first power signal line are connected through a via hole.
  • the at least one signal line further includes a second power signal line, the second power signal line extends along the column direction, and one of the second power signal lines is connected to each of the first pixel units in a column.
  • the first plate of the capacitor of the first sub-pixel is electrically connected.
  • the metal traces of the second power signal line are located on the second source and drain metal layer, and the orthographic projection of the metal traces of the second power signal line on the substrate is at least partially located on the first sub-pixel.
  • the light-emitting device is within the orthographic projection on the substrate; the transparent connection path of the second power signal line
  • the lines are located on the second transparent wiring layer, and the transparent connection wiring of the second power signal line and the metal wiring of the second power signal line are connected through via holes.
  • the display panel further includes: a plurality of data lines extending along a column direction, and a portion of the plurality of data lines located in the first display area is on the substrate.
  • the orthographic projection on the substrate is located outside the orthographic projection of the light-emitting device of any sub-pixel on the substrate, and the portion of at least one data line located in the first display area is located on the second transparent wiring layer.
  • the circuit main body of the pixel driving circuit includes: a writing transistor; in one of the first pixel units, the first pole of the writing transistor of the first sub-pixel and the first pole of the writing transistor of the second sub-pixel.
  • the first pole and the first pole of the writing transistor of the third sub-pixel are respectively connected to different data lines.
  • the portion of the at least one data line located in the first display area is a transparent wiring segment.
  • the orthographic projection of the transparent wiring segment of the data line electrically connected to the writing transistor in the first sub-pixel on the substrate is located in the circuit body of the first sub-pixel.
  • the orthographic projection on the substrate is away from the side of the orthographic projection of the circuit body of the second sub-pixel on the substrate; the orthographic projection of the light-emitting device of the second sub-pixel on the substrate and the orthographic projection of the light-emitting device of the third subpixel on the substrate, the orthographic projection of the transparent wiring segment on the substrate of the data line electrically connected to the writing transistor of the second subpixel, and the orthographic projection of the light-emitting device of the third subpixel on the substrate.
  • the transparent wiring segment of the data line electrically connected to the writing transistor of the third sub-pixel is between the orthographic projections on the substrate.
  • the circuit body of the pixel driving circuit further includes a compensation transistor and a third reset transistor.
  • the writing transistor, the compensation transistor and the third reset transistor in the first sub-pixel are sequentially away from the circuit body of the second sub-pixel; the writing transistor in the second sub-pixel
  • the input transistor, the compensation transistor and the third reset transistor are arranged in sequence along the first setting direction; the writing transistor, the compensation transistor and the third reset transistor in the third sub-pixel are arranged in sequence in the opposite direction of the first setting direction. set up.
  • the light-emitting device includes an anode, a light-emitting layer and a cathode, the anode is electrically connected to the pixel driving circuit, the light-emitting layer is located on a side of the anode away from the substrate, and the cathode Located on the side of the light-emitting layer facing away from the substrate.
  • the orthographic projection of the first reset transistor in the second sub-pixel and/or the first reset transistor in the third sub-pixel on the substrate, and the anode located on the first sub-pixel is on the substrate. Within the orthographic projection on the bottom.
  • the first sub-pixel is a blue sub-pixel
  • the second sub-pixel is a green sub-pixel
  • the third sub-pixel is a red sub-pixel
  • the display panel includes: a first display area and a second display area.
  • the first display area is provided with the first pixel unit;
  • the second display area is provided with a plurality of second pixel units, and the plurality of second pixel units are arranged in multiple rows and multiple columns;
  • the second The pixel unit includes a plurality of sub-pixels, the sub-pixel density of the first display area is equal to the sub-pixel density of the second display area; the area of the light-emitting device of the sub-pixel in the first display area is the second display area. 0.4 to 0.6 times the area of the light-emitting devices of sub-pixels of the same color in the area.
  • a display device in another aspect, includes: the display panel as described in any of the above embodiments.
  • Figure 1A is a structural diagram of a display device according to some embodiments.
  • Figure 1B is a structural diagram of a display device according to some embodiments.
  • Figure 2A is a structural diagram of a display device according to some embodiments.
  • Figure 2B is a structural diagram of a display panel according to some embodiments.
  • Figure 3A is a structural diagram of a display panel according to some embodiments.
  • Figure 3B is a structural diagram of a display panel according to some embodiments.
  • Figure 4A is a structural diagram of a pixel driving unit according to some embodiments.
  • Figure 4B is a timing diagram of a pixel driving circuit according to some embodiments.
  • Figure 4C is a structural diagram of a pixel driving unit according to some embodiments.
  • Figure 4D is a structural diagram of a pixel driving unit according to some embodiments.
  • Figure 4E is a structural diagram of a pixel driving unit according to some embodiments.
  • Figure 4F is a structural diagram of a pixel driving unit according to some embodiments.
  • Figure 5A is a structural diagram of a display panel according to some embodiments.
  • Figure 5B is a structural diagram of a display panel according to some embodiments.
  • Figure 5C is a structural diagram of a display panel according to some embodiments.
  • Figure 5D is a structural diagram of a display panel according to some embodiments.
  • Figure 6A is a structural diagram of a display panel according to some embodiments.
  • Figure 6B is a structural diagram of a display panel according to some embodiments.
  • Figure 7A is a structural diagram of a display panel according to some embodiments.
  • Figure 7B is a structural diagram of a display panel according to some embodiments.
  • Figure 7C is a structural diagram of a display panel according to some embodiments.
  • Figure 8A is a structural diagram of a display panel according to some embodiments.
  • Figure 8B is a structural diagram of a display panel according to some embodiments.
  • Figure 9A is a structural diagram of a display panel according to some embodiments.
  • Figure 9B is a structural diagram of a display panel according to some embodiments.
  • Figure 9C is a structural diagram of a display panel according to some embodiments.
  • Figure 10A is a structural diagram of a display panel according to some embodiments.
  • Figure 10B is a structural diagram of a display panel according to some embodiments.
  • Figure 11A is a structural diagram of a display panel according to some embodiments.
  • Figure 11B is a structural diagram of a display panel according to some embodiments.
  • Figure 11C is a structural diagram of a display panel according to some embodiments.
  • Figure 11D is a structural diagram of a display panel according to some embodiments.
  • Figure 11E is a structural diagram of a display panel according to some embodiments.
  • Figure 12A is a structural diagram of a display panel according to some embodiments.
  • Figure 12B is a structural diagram of a display panel according to some embodiments.
  • Figure 12C is a structural diagram of a display panel according to some embodiments.
  • Figure 13A is a structural diagram of a display panel according to some embodiments.
  • Figure 13B is a structural diagram of a display panel according to some embodiments.
  • Figure 14 is a structural diagram of a display panel according to some embodiments.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • connection and its derivatives may be used.
  • some embodiments may be described using the term “connected” to indicate that two or more components are in direct physical or electrical contact with each other.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the words 'a certain structure' is disposed under the anode' or 'a certain structure' is located under the anode' or 'a certain structure' is hidden under the anode' may be used, which means that a certain structure
  • the orthographic projection on the substrate lies within the orthographic projection of the anode on the substrate.
  • the area of a certain structure may be used, which means the area of the orthographic projection of a certain structure on the substrate.
  • parallel includes absolutely parallel and approximately parallel, and the acceptable deviation range of approximately parallel may be, for example, a deviation within 5°;
  • perpendicular includes absolutely vertical and approximately vertical, and the acceptable deviation range of approximately vertical may also be, for example, Deviation within 5°.
  • equal includes absolute equality and approximate equality etc., wherein the approximately equal acceptable deviation range may be equal, for example, the difference between the two is less than or equal to 5% of either one.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • FIG. 1A and 1B are structural diagrams of a display device according to some embodiments.
  • the display device 100 is a product with a function of displaying images (including static images or dynamic images, where the dynamic images may be videos).
  • the display device 100 can be: a watch, a monitor, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a personal digital assistant (PDA), a digital camera, a portable video recorder Machines, viewfinders, navigators, vehicles, large-area walls, home appliances, information query equipment (such as business query equipment in e-government, banks, hospitals, electric power and other departments), monitors, etc.
  • PDA personal digital assistant
  • a digital camera a portable video recorder Machines, viewfinders, navigators, vehicles, large-area walls, home appliances, information query equipment (such as business query equipment in e-government, banks, hospitals, electric power and other departments), monitors, etc.
  • information query equipment such as business query equipment in e-government, banks, hospitals, electric power and other departments
  • the display device 100 includes a display panel 200 and a sensor 300 .
  • FIG. 2B is a structural diagram of the display panel according to some embodiments.
  • the display panel 200 includes a display area AA and a peripheral area BB disposed on at least one side of the display area AA.
  • the display area AA is used for displaying pictures.
  • the peripheral area BB may be disposed on one or more sides of the display area AA.
  • the peripheral area BB is arranged around the display area AA.
  • the display panel 200 may be an OLED (organic light-emitting diode, organic light-emitting diode) display panel.
  • OLED display panels have the advantages of wide viewing angle, high contrast, fast response, low power consumption, foldability, and flexibility.
  • the display panel 200 includes a substrate 210 and a plurality of first pixel units 220 .
  • the plurality of first pixel units 220 are disposed on one side of the substrate 210 and are arranged in multiple rows and multiple columns.
  • the first pixel unit 220 includes a plurality of sub-pixels 230.
  • the sub-pixel 230 is the smallest unit of the display panel 200 for image display.
  • Each sub-pixel 230 can display a single color, such as red, green or blue.
  • the display area AA includes a first display area A1, and a plurality of first pixel units 220 are disposed in the first display area A1.
  • the display panel 200 includes a backlight side 201 and a display side 202 arranged oppositely, where the display side 202 is used for displaying images.
  • the sensor 300 is disposed on the backlight side 201 of the display panel 200 . and is located in the first display area A1 of the display panel 200 .
  • the sensor 300 is, for example, an image sensor or an infrared sensor.
  • the sensor 300 is configured to receive light from the display side 202 of the display panel 200, so that operations such as image capturing, distance sensing, and light intensity sensing can be performed. These light rays can pass through the first display area A1 and then illuminate the sensor 300 , thereby being sensed by the sensor 300 .
  • the sensor 300 By disposing the sensor 300 in the first display area A1 of the display panel 200 and on the backlight side 201 of the display panel, it is possible to avoid digging holes in the display screen, increase the screen-to-body ratio, and provide a better visual experience.
  • FIG. 3A is a structural diagram of a display panel in the first display area A1 according to some embodiments.
  • a sub-pixel 230 includes a pixel driving circuit 231 and a light-emitting device 232 .
  • the light-emitting device 232 is located on a side of the pixel driving circuit 231 away from the substrate 210 and is electrically connected to the pixel driving circuit 231 .
  • the pixel driving circuit 231 is used to drive the light-emitting device 232 to emit light.
  • FIG. 3B is a structural diagram of a display panel according to some embodiments.
  • FIG. 3B shows the structure of a sub-pixel.
  • the light-emitting device 232 includes an anode AND1, a light-emitting layer EL and a cathode CTD1.
  • the anode AND1 is located on a side of the pixel driving circuit 231 away from the substrate 210 and is electrically connected to the pixel driving circuit 231 .
  • the luminescent layer EL is located on the side of the anode AND1 facing away from the substrate 210
  • the cathode CTD1 is located on the side of the luminescent layer EL facing away from the substrate 210 .
  • the light emitting device 232 also includes an electron transporting layer (ETL), an electron injection layer (EIL), a hole transporting layer (HTL), and a hole injection layer.
  • ETL electron transporting layer
  • EIL electron injection layer
  • HTL hole transporting layer
  • HTL hole transporting layer
  • the orthographic projection of the anode AND1 on the substrate 210, the orthographic projection of the luminescent layer EL on the substrate 210, and the orthographic projection of the cathode CTD1 on the substrate 210 at least partially coincide.
  • a plurality of sub-pixels 230 in a first pixel unit 220 include a first sub-pixel 230B, a second sub-pixel 230G and a third sub-pixel 230R.
  • the area of the light-emitting device 232 of the first sub-pixel 230B is larger than the area of the light-emitting device 232 of the second sub-pixel 230G, and is larger than the area of the light-emitting device 232 of the third sub-pixel 230R.
  • the first The area of the anode AND-B of the sub-pixel 230B is larger than the area of the anode AND-G of the second sub-pixel 230G, and is larger than the area of the anode AND-R of the third sub-pixel 230R.
  • the area of the luminescent layer EL of the first sub-pixel 230B is larger than the area of the luminescent layer EL of the second sub-pixel 230G, and larger than the area of the luminescent layer EL of the third sub-pixel 230R.
  • the area of the cathode CTD1 of the first sub-pixel 230B is larger than the area of the cathode CTD1 of the second sub-pixel 230G, and is larger than the area of the cathode CTD1 of the third sub-pixel 230R.
  • the anode AND1 is in a block shape, and the anodes AND1 of different sub-pixels 230 are separated from each other.
  • the light-emitting layer EL is in a block shape, and the light-emitting layers EL of different sub-pixels 230 are separated from each other.
  • the cathodes CTD1 of the multiple sub-pixels 230 in the display panel 200 are connected to each other, and the cathodes CTD1 of the multiple sub-pixels 230 have a whole-layer structure.
  • the area of the cathode CTD1 of one sub-pixel 230 is equal to the area of the light-emitting layer EL or the area of the anode AND1.
  • the area of the larger one of the light-emitting layer EL and the anode AND1 is the area of the light-emitting device 232 .
  • the area of the light-emitting device 232 is the area of the anode AND1.
  • the area of the orthographic projection of the light-emitting layer EL on the substrate 210 is greater than the area of the orthographic projection of the anode AND1 on the substrate 210, then the area of the light-emitting device 232 is the area of the light-emitting layer EL.
  • the cathode CTD1 is in a block shape, and the cathodes CTD1 of the multiple sub-pixels 230 in the display panel 200 are separated from each other.
  • the area of the largest one among the cathode CTD1, the luminescent layer EL and the anode AND1 is: The area of the light emitting device 232.
  • the cathode CTD1 the light-emitting layer EL and the anode AND1 of a sub-pixel 230, if the area of the cathode CTD1 is the largest, then the area of the light-emitting device 232 is the area of the cathode CTD1.
  • the area of the light emitting device 232 is the area of the anode AND1. If the area of the light-emitting layer EL is the largest, then the area of the light-emitting device 232 is the area of the light-emitting layer EL.
  • the first sub-pixel 230B is a blue sub-pixel
  • the second sub-pixel 230G is a green sub-pixel
  • the third sub-pixel 230R is a red sub-pixel.
  • the light-emitting layer EL includes an effective light-emitting area.
  • the area of the light-emitting device 232 of the first sub-pixel 230B is larger than the area of the light-emitting device 232 of the second sub-pixel 230G, and is larger than the area of the light-emitting device 232 of the third sub-pixel 230R. area.
  • the area of the effective light-emitting area of the first sub-pixel 230B is larger than the area of the effective light-emitting area of the second sub-pixel 230G, and is larger than the area of the effective light-emitting area of the third sub-pixel 230R.
  • the light-emitting layer EL in the light-emitting device 232 includes a light-emitting material, and the efficiency of the light-emitting material of the blue sub-pixel is low.
  • the effective light-emitting area of the blue sub-pixel is maximized, which can reduce the color shift problem caused by the different light-emitting efficiencies of the red, green and blue sub-pixels.
  • the area of the light-emitting device 232 of the sub-pixel 230 and hiding the pixel driving circuit 231 under the light-emitting device 232 can be reduced. Furthermore, the area of the light-transmitting area can be increased, and the light transmittance of the first display area A1 can be improved. It should be noted that the area of the light-emitting device 232 refers to the area covered by the orthographic projection of the light-emitting device 232 on the substrate 210 .
  • the fact that the pixel driving circuit 231 is hidden under the light-emitting device 232 means that the pixel driving circuit 231 is located on the side of the light-emitting device 232 close to the substrate 210, and the orthographic projection of the pixel driving circuit 231 on the substrate 210 is located on the side of the light-emitting device 232. within the orthographic projection on substrate 210.
  • the areas of the light-emitting device 232 of the second sub-pixel 230G and the light-emitting device 232 of the third sub-pixel 230R are small, it is difficult to hide the pixel driving circuit 231-G of the second sub-pixel 230G in the second sub-pixel 230G. under the light-emitting device 232 of the third sub-pixel 230R, and it is difficult to hide the pixel driving circuit 231-R of the third sub-pixel 230R under the light-emitting device 232 of the third sub-pixel 230R. If the pixel driving circuit 231 is exposed outside the light-emitting device 232, the light transmittance of the first display area A1 will be reduced and diffraction will be aggravated, which is not conducive to imaging.
  • the present disclosure provides a pixel driving unit 400. Please refer to FIG. 4A.
  • the pixel driving unit 400 includes a plurality of pixel driving circuits 231.
  • the pixel driving circuit in the present disclosure includes a variety of structures, and the settings can be selected according to actual needs.
  • the structure of the pixel driving circuit 231 may include "6T1C", “7T1C”, “6T2C” or “7T2C”, etc.
  • T represents a thin film transistor, and the number in front of “T” represents the number of thin film transistors
  • C represents a storage capacitor C, and the number in front of “C” represents the number of storage capacitors C.
  • the following takes the 7T1C mode pixel driving circuit as an example to introduce.
  • a pixel driving circuit 231 includes a driving transistor T3 and a second reset transistor T12.
  • the second reset transistor T12 is electrically connected to the reset signal terminal Rst, the initialization signal terminal Vin and the control electrode of the driving transistor T3.
  • T12 is configured to: in response to the reset signal received at the reset signal terminal Rst, transmit the initialization signal received at the initialization signal terminal Vin to the control electrode of the driving transistor T3 to reset the control electrode of the driving transistor T3.
  • control electrode of the second reset transistor T12 is electrically connected to the reset signal terminal Rst
  • the first electrode is electrically connected to the initialization signal terminal Vin
  • the second electrode is electrically connected to the control electrode of the driving transistor T3.
  • the pixel driving circuit 231 in addition to the second reset transistor T12 and the driving transistor T3, the pixel driving circuit 231 also includes a compensation transistor T2, a writing transistor T4, a first light emitting control transistor T5, a third two light emission control transistors T6, a third reset transistor T7 and a capacitor Cst.
  • control electrode of the compensation transistor T2 is electrically connected to the scanning signal terminal Gt
  • first electrode of the compensation transistor T2 is electrically connected to the second electrode of the driving transistor T3
  • second electrode of the compensation transistor T2 is electrically connected to the control electrode of the driving transistor T3.
  • the control electrode of the writing transistor T4 is electrically connected to the scan signal terminal Gt, the first electrode of the writing transistor T4 is electrically connected to the data signal terminal Dt, and the second electrode of the writing transistor T4 is electrically connected to the first electrode of the driving transistor T3.
  • the control electrode of the first light-emitting control transistor T5 is electrically connected to the light-emitting control signal terminal Em.
  • the first electrode of the first light-emitting control transistor T5 is electrically connected to the first type power supply signal terminal Vdd.
  • the second electrode of the first light-emitting control transistor T5 is electrically connected to the light-emitting control signal terminal Em.
  • the first pole of the driving transistor T3 is electrically connected.
  • the control electrode of the second light-emitting control transistor T6 is electrically connected to the light-emitting control signal terminal Em.
  • the first electrode of the second light-emitting control transistor T6 is electrically connected to the second electrode of the driving transistor T3.
  • the second electrode of the second light-emitting control transistor T6 is electrically connected to the light-emitting control signal terminal Em.
  • the anode of the light emitting device 232 is electrically connected.
  • the cathode of the light emitting device 232 is electrically connected to the second type power supply signal terminal Vss. Wherein, the voltage of the first type power signal received at the first type power signal terminal Vdd is greater than the voltage of the second type power signal received at the second type power signal terminal Vss.
  • the control electrode of the third reset transistor T7 is electrically connected to the scanning signal terminal Gt, the first electrode of the third reset transistor T7 is electrically connected to the initialization signal terminal Vin, and the second electrode of the third reset transistor T7 is electrically connected to the anode of the light emitting device 232 .
  • the first plate of the capacitor Cst is electrically connected to the first type power supply signal terminal Vdd, and the second plate of the capacitor Cst is electrically connected to the control electrode of the driving transistor T3.
  • the second reset transistor T12, the compensation transistor T2, the driving transistor T3, the writing transistor T4, the first lighting control transistor T5, the second lighting control transistor T6 and the third reset transistor T7 may all be P-type transistors.
  • the conduction condition of an N-type transistor is that the gate-source voltage difference is greater than its threshold voltage, that is, the N-type transistor's conduction condition is If the gate voltage is greater than the sum of its source voltage and its threshold voltage, and the threshold voltage of the N-type transistor is positive, then the gate voltage signal that turns on the N-type transistor is called a high-voltage signal.
  • the conduction condition of the P-type transistor is The absolute value of the gate-source voltage difference is greater than its threshold voltage.
  • the threshold voltage of the P-type transistor is negative. That is, the gate voltage of the P-type transistor is less than the sum of its source voltage and its threshold voltage. It is said that the P-type transistor is turned on.
  • the gate voltage signal is a low voltage signal, and the "high voltage signal” and "low voltage signal” are relative to the source voltage.
  • the second reset transistor T12 , the compensation transistor T2 , the driving transistor T3 , the writing transistor T4 , the first lighting control transistor T5 , the second lighting control transistor T6 and the third reset transistor T7 may all The P-type transistors are all P-type transistors.
  • the timing diagram of the pixel driving circuit 231 is as shown in FIG. 4B.
  • the following describes the driving process of the pixel driving circuit 231 based on the fact that the transistors in the pixel driving circuit 231 are all P-type transistors.
  • the driving process of the pixel driving circuit 231 is: one frame period includes a reset phase t1, a data refresh and compensation phase t2, and a light emitting phase t3.
  • the reset signal is low voltage.
  • the second reset transistor T12 is turned on, and the second reset transistor T12 transmits the initialization signal to the control electrode of the driving transistor T3, thereby resetting the control electrode of the driving transistor T3.
  • the driving transistor T3 is turned on.
  • the compensation transistor T2, the writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the third reset transistor T7 are all in an off state, and the light-emitting device 232 does not emit light.
  • the reset signal received at the reset signal terminal Rst is a high voltage
  • the second reset transistor T12 is turned off.
  • the scan signal received at the scan signal terminal Gt is low voltage. Therefore, the third reset transistor T7 is turned on under the control of the scan signal, and then writes the initialization signal received at the initialization signal terminal Vin to the anode of the light emitting device 232 , to reset the anode of the light-emitting device 232 .
  • the writing transistor T4 and the compensation transistor T2 are turned on.
  • the driving transistor T3 maintains the conduction state of the reset stage t1. Therefore, the data signal received at the data signal terminal Dt can pass through the writing transistor in turn.
  • the driving transistor T3 and the compensation transistor T2 transmit to the control electrode of the driving transistor T3, causing the voltage of the control electrode of the driving transistor T3 to change until the voltage of the control electrode of the driving transistor T3 reaches the threshold voltage of the driving transistor T3 and the voltage of the data signal. The sum causes the drive transistor T3 to turn off.
  • the threshold voltage of the driving transistor T3 can be written to the control electrode of the driving transistor T3 to compensate for the threshold voltage drift of the driving transistor T3, thereby reducing the impact on the luminous intensity of the light-emitting device 232 .
  • the first light emission control transistor T5 and the second light emission control transistor T6 are in an off state under the control of the light emission control signal.
  • the second reset transistor T12, the compensation transistor T2, the writing transistor T4 and the third reset transistor T7 are turned off.
  • the capacitor Cst fixes the voltage of the control electrode of the driving transistor T3 to maintain the voltage of the control electrode of the driving transistor T3 at the data refresh and compensation stage t2.
  • the light-emitting control signal is low voltage, and the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on under the control of the light-emitting control signal, thereby causing the first-type light-emitting control transistor T5 and the second light-emitting control transistor T6 to be received at the first-type power supply signal terminal Vdd.
  • the power signal is written to the first electrode of the driving transistor T3, thereby turning on the driving transistor T3, thereby forming a path between the first type power signal terminal and the light-emitting device 232, causing the light-emitting device 232 to emit light.
  • the second reset transistors T12 of at least two pixel driving circuits 231 are the same transistor, which can reduce the area of the pixel driving unit 400 and is beneficial to The pixel driving circuit 231 in the pixel driving unit 400 is hidden under the light emitting device 232 .
  • the second reset transistors T12 of all pixel driving circuits 231 in one pixel driving unit 400 are the same transistor.
  • the plurality of pixel driving circuits 231 include a first pixel driving circuit 231B, a second pixel driving circuit 231G, and a third pixel driving circuit 231R.
  • the second reset transistor T12 of the first pixel driving circuit 231B, the second reset transistor T12 of the second pixel driving circuit 231G, and the second reset transistor T12 of the third pixel driving circuit 231R are the same transistor.
  • the first pixel driving circuit 231B, the second pixel driving circuit 231G and the third pixel driving circuit 231R share the second reset transistor T12, and one second reset transistor T12 can be the driving transistor in the pixel driving circuits 231B, 231G and 231R at the same time.
  • the control pole of T3 is reset.
  • the number of transistors in one pixel driving unit 400 can be reduced. Therefore, the area of the pixel driving unit 400 can be reduced, which is beneficial to hiding the pixel driving circuit 231 in the pixel driving unit 400 in the light-emitting device. Under 232.
  • the first sub-pixel 230B includes a first pixel driving circuit 231B and an anode AND-B. At this time, the first pixel driving circuit 231B and the anode AND-B are electrically connected.
  • the second sub-pixel 230G includes a second pixel driving circuit 231G and an anode AND-G. At this time, the second pixel driving circuit 231G and the anode AND-G are electrically connected.
  • the third sub-pixel 230R includes a third pixel driving circuit 231R and an anode AND-R. At this time, the third pixel driving circuit 231R and the anode AND-R are electrically connected.
  • the pixel driving circuit 231 also includes a first reset transistor T11; in the same pixel driving circuit 231, the first reset transistor T11 is connected in series to the control of the second reset transistor T12 and the driving transistor T3. between extremes.
  • the control electrode of the first reset transistor T11 is electrically connected to the reset signal terminal Rst.
  • the first reset transistor T11 and the second reset transistor T12 jointly reset the control electrode of the driving transistor T3, thereby preventing leakage.
  • At least The first reset transistors T11 of the two pixel driving circuits 231 are the same transistor.
  • the plurality of pixel driving circuits 231 include a first pixel driving circuit 231B, a second pixel driving circuit 231G and a third pixel driving circuit 231R.
  • the first reset transistor T11 -B of the first pixel driving circuit 231B, the first reset transistor T11 -G of the second pixel driving circuit 231G and the third pixel driving circuit 231R At least two of the first reset transistors T11-R are the same transistor.
  • the first reset transistor T11 -B of the first pixel driving circuit 231B and the first reset transistor T11 -G of the second pixel driving circuit 231G are the same transistor.
  • the first reset transistor T11 -B of the first pixel driving circuit 231B and the first reset transistor T11 -R of the third pixel driving circuit 231R are the same transistor.
  • the first reset transistor T11 -G of the second pixel driving circuit 231G and the first reset transistor T11 -R of the third pixel driving circuit 231R are the same transistor.
  • the first reset transistors T11 of multiple pixel driving circuits 231 are the same transistor.
  • the first reset transistor T11-B of the first pixel driving circuit 231B The first reset transistor T11-G of the second pixel driving circuit 231G and the first reset transistor T11-R of the third pixel driving circuit 231R are the same transistor.
  • the number of transistors in one pixel driving unit 400 can be reduced, thereby reducing the number of pixel driving circuits in the pixel driving unit 400.
  • the area of 231 is beneficial to hiding the pixel driving circuit 231 in the pixel driving unit 400 under the light-emitting device 232.
  • the first reset transistor T11-B of the first pixel driving circuit 231B, the first reset transistor T11-G of the second pixel driving circuit 231G and the third The first reset transistors T11-R of the pixel driving circuit 231R are all different transistors.
  • the control electrode of the driving transistor T3 is reset through different first reset transistors T11, thereby ensuring that the control electrode of the driving transistor T3 is reset. The reset effect of the control pole.
  • the display device 100 provided by some embodiments of the present disclosure includes: the pixel driving unit 400 provided by any of the above embodiments. Therefore, the display device 100 provided by some embodiments of the present disclosure has all the beneficial effects of the pixel driving unit 400 provided by any of the above embodiments, which will not be described again here.
  • Some embodiments of the present disclosure also provide a display panel 200.
  • the orthographic projection of the first reset transistor T11-G in the second sub-pixel 230G and/or the first reset transistor T11-R in the third sub-pixel 230R on the substrate 210 is located in the first sub-pixel 230B.
  • the light emitting device 232 is within the orthographic projection on the substrate 210 .
  • the orthographic projection of the light-emitting device 232 on the substrate 210 coincides with the orthographic projection of the anode AND1 on the substrate 210.
  • the orthographic projection of the light-emitting device 232 on the substrate 210 coincides with the orthographic projection of the light-emitting layer EL on the substrate 210 .
  • the orthographic projection of the light-emitting device 232 on the substrate 210 coincides with the orthographic projection of the cathode CTD1 on the substrate 210.
  • the area of the light-emitting device 232 of the first sub-pixel 230B is the largest, while the area of the light-emitting device 232 of the second sub-pixel 230G and the area of the light-emitting device 232 of the third sub-pixel 230R are the largest.
  • the areas are relatively small, and the first reset transistor T11-G in the second sub-pixel 230G and/or the first reset transistor T11-R in the third sub-pixel 230R is hidden in the light-emitting device 232 of the first sub-pixel 230B.
  • the first reset transistor T11 -G in the second subpixel 230G and/or the first reset transistor T11 -R in the third subpixel 230R may be blocked.
  • the area of the light-emitting device 232 of the first sub-pixel 230B is large, the structure of the pixel driving circuit 231 under the light-emitting device 232 of the first sub-pixel 230B will not be too compact, and the light emitting of the first sub-pixel 230B can be rationally utilized.
  • only the orthographic projection of the first reset transistor T11-G in the second sub-pixel 230G on the substrate 210 may be located within the orthographic projection of the light-emitting device 232 of the first sub-pixel 230B on the substrate 210 .
  • the area of the light-emitting device 232 of the second sub-pixel 230G is smaller.
  • the number of transistors in the pixel driving circuit 231 under the light-emitting device 232 of the second sub-pixel 230G can be reduced, thereby reducing the number of pixels under the light-emitting device 232 of the second sub-pixel 230G.
  • the area of the driving circuit 231 is conducive to the light-emitting device 232 of the second sub-pixel 230G shielding the pixel driving circuit 231 located below it.
  • only the orthographic projection of the first reset transistor T11-R in the third sub-pixel 230R on the substrate 210 may be located between the orthographic projection of the light-emitting device 232 of the first sub-pixel 230B on the substrate 210. Inside. By disposing the first reset transistor T11-R in the third sub-pixel 230R under the light-emitting device 232 of the first sub-pixel 230B, the pixel driving under the light-emitting device 232 of the third sub-pixel 230R can be reduced.
  • the number of transistors in the circuit 231 can further reduce the area of the pixel driving circuit 231 located under the light-emitting device 232 of the third sub-pixel 230R, which is beneficial to the use of the light-emitting device 232 of the third sub-pixel 230R against the pixel driving circuit located thereunder. 231 for occlusion.
  • the first reset transistor T11-B of the first sub-pixel 230B, the first reset transistor T11-G of the second sub-pixel 230G, and the first reset transistor of the third sub-pixel 230R T11-R, the light-emitting device 232 of the first sub-pixel 230B is within the orthographic projection of the substrate 210.
  • the first reset transistor T11-G of the second sub-pixel 230G and the first reset transistor T11-R of the third sub-pixel 230R are both arranged under the light-emitting device 232 of the first sub-pixel 230B, which can reduce the second
  • the area of the pixel driving circuit 231 under the light-emitting device 232 of the sub-pixel 230G can also be reduced, which is beneficial to the second sub-pixel 230G.
  • the pixel driving circuit 231 and the pixel driving circuit 231 in the third sub-pixel 230R perform shielding to reduce the diffraction phenomenon.
  • the first reset transistor T11-B of the first sub-pixel 230B is located under the light-emitting device 232 of the first sub-pixel 230B, which prevents the first reset transistor T11-B from occupying other space, thereby improving the light transmittance.
  • the first reset transistor T11 -B of the first subpixel 230B, the first reset transistor T11 -G of the second subpixel 230G, and the first reset transistor T11 -G of the third subpixel 230R At least two of the reset transistors T11-R are the same transistor.
  • the first reset transistors T11 of at least two sub-pixels 230 are the same transistor, which can reduce the number of the first reset transistors T11 in the first pixel unit 220.
  • the first reset transistor T11-B of the first sub-pixel 230B, the first reset transistor T11-G of the second sub-pixel 230G, and the first reset transistor T11-R of the third sub-pixel 230R are all disposed in the first sub-pixel.
  • the area of the pixel driving circuit 231 under the light-emitting device 232 of the first sub-pixel 230B can be reduced, thereby reducing the size of the first sub-pixel 230B.
  • the area of the light-emitting device 232 increases the light transmittance of the first display area A1.
  • the material of the anode AND1 includes a transparent conductive oxide material and a metal material, where the transparent conductive oxide material is, for example, ITO and IZO, and the metal material is, for example, Au, Ag, Ni, and Pt.
  • the anode layer AND can include a stacked composite structure of a layer of transparent conductive oxide, a layer of metal, and a layer of transparent conductive oxide. This structure can be recorded as transparent conductive oxide/metal/transparent conductive oxide.
  • the structure of an anode layer AND is: ITO/Ag/ITO. Among them, the light transmittance of anode AND1 is poor or opaque.
  • the areas of the light-emitting device 232 and the anode AND1 can be equal. It may not be equal, and it can also be understood that the orthographic projection of the light-emitting device 232 on the substrate 210 may completely or partially coincide with the orthographic projection of the anode AND1 on the substrate 210 .
  • the anode AND1 has poor light transmittance or is opaque, and the anode AND1 can block the pixel drive circuit 231 and signal lines located under the anode AND1, thereby reducing the exposure of the pixel drive circuit 231 and signal lines, thereby reducing the sensor 300 passes through the diffraction of the first display area A1 when taking pictures, and at the same time increases the light transmittance of the first display area A1.
  • the first reset transistor T11-B in the first sub-pixel 230B, the first reset transistor T11-G in the second sub-pixel 230G, and the first reset transistor T11-R in the third sub-pixel 230R are in The orthographic projections on the substrate 210 are all located within the orthographic projections of the anode AND-B of the first sub-pixel 230B on the substrate 210 .
  • the display panel 200 further includes a reset signal line RST and an initialization signal line VIN.
  • the pixel driving circuit 231 further includes a second reset transistor T12 , and the second reset transistor T12 is connected in series with any first reset transistor T11 .
  • the control electrode of each first reset transistor T11 and the control electrode of the second reset transistor T12 are both electrically connected to the reset signal line RST; the first electrode of the second reset transistor T12 is electrically connected to the initialization signal line VIN.
  • the second electrode of the second reset transistor T12 is electrically connected to the first electrode of each first reset transistor T11.
  • the pixel driving circuit 231 further includes a driving transistor T3.
  • the control electrode of the driving transistor T3 of each pixel driving circuit 231 is electrically connected to the second electrode of each first reset transistor T11.
  • the reset signal line RST is used to transmit the reset signal
  • the initialization signal line VIN is used to transmit the initialization signal.
  • the first reset transistor T11 and the second reset transistor T12 are both P-type transistors
  • the first reset transistor T11 and the second reset transistor T12 are turned on, and the first reset transistor T11 and the second reset transistor T12 are turned on.
  • the two reset transistors T12 can transmit the initialization signal to the control electrode of the driving transistor T3, thereby resetting the control electrode of the driving transistor T3.
  • two transistors are used to reset the control electrode of the driving transistor T3, which can prevent leakage.
  • the second reset transistor T12 of the first sub-pixel 230B, the second reset transistor T12 of the second sub-pixel 230G, and the second reset transistor T12 of the third sub-pixel 230R are the same transistor. ;
  • the orthographic projection of the second reset transistor T12 on the substrate 210 is located within the orthographic projection of the light-emitting device 232 of the first sub-pixel 230B on the substrate 210.
  • the second reset transistor T12 of the first sub-pixel 230B, the second reset transistor T12 of the second sub-pixel 230G and the second reset transistor T12 of the third sub-pixel 230R are the same transistor, which can be reduced the number of transistors under the light-emitting device 232 of the first sub-pixel 230B, thereby reducing the area of the pixel driving circuit 231 under the light-emitting device 232 of the first sub-pixel 230B, It is advantageous for the light-emitting device 232 of the first sub-pixel 230B to block the pixel driving circuit 231 located below it to prevent the pixel driving circuit 231 from being exposed, thereby reducing the diffraction phenomenon.
  • the area of the light-emitting device 232 of the first sub-pixel 230B can be reduced, thereby increasing the light transmittance.
  • the orthographic projection of the second reset transistor T12 on the substrate 210 is located within the orthographic projection of the anode AND-B of the first sub-pixel 230B on the substrate 210 .
  • the anode AND-B of the first sub-pixel 230B is opaque and has a better shielding effect on the second reset transistor T12, thereby reducing the diffraction phenomenon when the sensor 300 takes pictures through the first display area A1.
  • the light-emitting device 232 of the second sub-pixel 230G and the light-emitting device 232 of the third sub-pixel 230R are spaced apart along the column direction Y.
  • the direction pointed by the arrow Y is the column direction Y.
  • the light-emitting device 232 of the second sub-pixel 230G and the light-emitting device 232 of the third sub-pixel 230R are sequentially arranged along the column direction Y, so the light-emitting device 232 of the second sub-pixel 230G and the third sub-pixel 230R in a column of first pixel units 220
  • the light-emitting devices 232 may be arranged in a row.
  • the light-emitting devices 232 of the first sub-pixels 230B in a column of first pixel units 220 may be arranged in one column. Please refer to FIG. 5B and FIG. 5C.
  • the light-emitting device 232 of the first sub-pixel 230B is located in an adjacent column of the column where the light-emitting device 232 of the second sub-pixel 230G and the light-emitting device 232 of the third sub-pixel 230R are located; and the first sub-pixel
  • the light-emitting device 232 of 230B spans the gap area between the light-emitting device 232 of the second sub-pixel 230G and the light-emitting device 232 of the third sub-pixel 230R.
  • the direction pointed by the arrow X is the row direction X.
  • the row direction X is perpendicular to the column direction Y.
  • the light-emitting devices 232 of the third sub-pixels 230R in the first pixel unit 220 of a row may be aligned in a row.
  • the light-emitting devices 232 of the second sub-pixels 230G in the first pixel unit 220 of a row may be aligned in a row.
  • the light-emitting devices 232 of the first sub-pixels 230B in a row of first pixel units 220 may be aligned in a row.
  • the gap area between the light-emitting device 232 of the second sub-pixel 230G and the light-emitting device 232 of the third sub-pixel 230R refers to the gap between the light-emitting device 232 of the adjacent row of third sub-pixels 230R and the row of second sub-pixels 230G.
  • the gap area between the light emitting devices 232 refers to the gap between the light emitting devices 232 .
  • the light-emitting device 232 of the first sub-pixel 230B spans the gap area between the light-emitting device 232 of the second sub-pixel 230G and the light-emitting device 232 of the third sub-pixel 230R. It can also be understood as the light-emitting device of the first sub-pixel 230B.
  • the projection of 232 in the row direction X overlaps with both the light-emitting device 232 of the second sub-pixel 230G and the light-emitting device 232 of the third sub-pixel 230R.
  • the arrangement of sub-pixels 230 disclosed in some of the above embodiments can be called "REAL pixel arrangement".
  • the PPI pixels per inch
  • the number of pixels per inch is low (for example, below 400)
  • the graininess can be reduced and the display effect improved.
  • the above display panel 200 can be applied to a watch device.
  • the pixel driving circuit 231 further includes a circuit body 2311 .
  • the circuit body 2311 of each sub-pixel 230 includes a compensation transistor T2, a driving transistor T3, a writing transistor T4, a first emission control transistor T5, a second emission control transistor T6, a third reset transistor T7 and a capacitor Cst.
  • the orthographic projection of the circuit body 2311-B of the first sub-pixel 230B on the substrate 210 is located within the orthographic projection of the light-emitting device 232 of the first sub-pixel 230B on the substrate 210, and the circuit body 2311-B of the second sub-pixel 230G
  • the orthographic projection of G on the substrate 210 is located within the orthographic projection of the light-emitting device 232 of the second sub-pixel 230G on the substrate 210
  • the orthographic projection of the circuit body 2311-R of the third sub-pixel 230R on the substrate 210 is located within
  • the light emitting device 232 of the third subpixel 230R is within the orthographic projection on the substrate 210 .
  • the circuit body 2311 electrically connected to it is shielded by the light-emitting device 232, thereby preventing the circuit body 2311 from being exposed to the light-emitting device 232 and reducing the diffraction phenomenon.
  • the light transmittance of the first display area A1 can also be improved.
  • the orthographic projection of the circuit body 2311 of each sub-pixel 230 on the substrate 210 is located within the orthographic projection of the anode AND1 of the sub-pixel 230B on the substrate 210 .
  • the orthographic projection of the circuit body 2311-B of the first sub-pixel 230B on the substrate 210 is located within the orthographic projection of the anode AND-B of the first sub-pixel 230B on the substrate 210, and the second sub-pixel 230G
  • the orthographic projection of the circuit main body 2311-G on the substrate 210 is located within the orthographic projection of the anode AND-G of the second sub-pixel 230G on the substrate 210, and the circuit main body 2311-R of the third sub-pixel 230R is on the substrate.
  • the orthographic projection on 210 is within the orthographic projection of the anode AND-R of the third sub-pixel 230R on the substrate 210 .
  • the anode AND1 of the sub-pixel 230B is opaque and has a better shielding effect on each circuit body 2311, thereby reducing the diffraction phenomenon when the sensor 300 takes pictures through the first display area A1.
  • the direction in which the second sub-pixel 230G points to the third sub-pixel 230 is the second designated direction C2
  • the direction pointed by the arrow C2 is the second designated direction C2
  • the second designated direction C2 is the same as the column.
  • Direction Y is parallel.
  • the second reset transistor T12 and the plurality of first reset transistors T11 are located in the circuit body 2311-R of the third sub-pixel 230R away from the second sub-pixel.
  • the direction in which the circuit body 2311-R of the third sub-pixel 230R points to the second reset transistor T12 and the plurality of first reset transistors T11 is the second designated direction C2.
  • the second reset transistor T12 , the first reset transistor T11 -R of the third subpixel 230R, and the first reset transistor T11 -G of the second subpixel 230G are located in the first subpixel.
  • the first reset transistor T11-B of 230B is close to one side of the circuit body 2311-R of the third sub-pixel 230R, and is sequentially away from the circuit body 2311-R of the third sub-pixel 230R.
  • the direction in which the third sub-pixel 230R points to the first sub-pixel 230B is the first specified direction C1
  • the direction pointed by the arrow C1 is the first specified direction C1
  • the first specified direction C1 is the first specified direction C1.
  • the specified direction C1 is parallel to the row direction X.
  • the designated directions C1 are set in sequence, so as to facilitate the electrical connection between the first reset transistor T11-R of the third sub-pixel 230R and the driving transistor T3 of the third sub-pixel 230R, and at the same time facilitate the first reset transistor T11-R of the second sub-pixel 230G.
  • G is electrically connected to the driving transistor T3 of the second sub-pixel 230G.
  • the reset signal line RST extends along the row direction
  • the control electrode of transistor T11 is electrically connected.
  • the second reset transistor T12 is not shown in FIG. 5B and FIG. 5C. Please refer to FIG. 5A.
  • the pattern of the reset signal line RST may be a straight line pattern or an approximately straight line pattern.
  • the above reset signal line RST "extends along the row direction X" means that the main pattern of the reset signal line RST extends along a certain row direction X. the trend of.
  • Reset transistor T11-R receives the same reset signal. Therefore, the control electrodes of the driving transistors T3 in each sub-pixel 230 in the first pixel unit 220 of a row are reset simultaneously.
  • the initialization signal line VIN extends along the row direction X, and is electrically connected to the first electrode of the second reset transistor T12 in the first pixel unit 220 of a row.
  • the second reset crystal T12 is not shown in FIG. 5B, please refer to FIG. 5A.
  • the pattern of the initialization signal line VIN may be a straight line pattern or an approximately straight line pattern.
  • the above-mentioned initialization signal line VIN "extends along the row direction X" means that the main pattern of the initialization signal line VIN extends along a certain row direction X. the trend of.
  • the initialization signal line VIN is used to transmit an initialization signal.
  • the initialization signal is transmitted to each first reset transistor T11 through the second reset transistor T12, and then transmitted to the control electrode of the driving transistor T3 of each sub-pixel 230.
  • the control electrode of the driving transistor T3 is reset.
  • the orthographic projection of the second reset transistor T12 and each first reset transistor T11 on the substrate 210 is located at the orthographic projection of the initialization signal line VIN electrically connected to the second reset transistor T12 on the substrate 210. and the orthographic projection of the circuit body 2311-R of the third sub-pixel 230R on the substrate 210; the orthographic projection of the reset signal line RST on the substrate 210 is located at the orthogonal projection of the initialization signal line VIN on the substrate 210. between the projection and the orthographic projection of the circuit body 2311 -G of the third sub-pixel 230R on the substrate 210 .
  • the second reset transistor T12 and each first reset transistor T11 are defined as the first type of reset transistor.
  • the circuit body 2311-R of the third sub-pixel 230R, the first-type reset transistor and the initialization signal line VIN are sequentially arranged along the second designated direction C2.
  • the control electrodes of the second reset transistor T12 and each first reset transistor T11 are located on the reset signal line RST.
  • the following describes the position of the control electrode of the first reset transistor T11 in combination with the multiple film layers in the display panel 200 .
  • the display panel 200 includes an active film layer 240 and a first gate metal layer Gate1 disposed on one side of the substrate 210 .
  • the active film layer 240 and the first gate metal layer Gate1 are both located on the substrate 210 .
  • the first gate metal layer Gate1 is located on the side of the active film layer 240 away from the substrate 210.
  • a first gate insulation layer is disposed between the active film layer 240 and the first gate metal layer Gate1.
  • the active film layer 240 includes the active layer of each transistor in the pixel driving circuit 231 , wherein the active layer of the transistor includes a first electrode region, a second electrode region, and a channel connecting the first electrode region and the second electrode region. district.
  • the active film layer 240 includes an active layer T12 -P of the second reset transistor T12 and an active layer T11 -P of each first reset transistor T11 .
  • the active layer T12 -P of the second reset transistor T12 extends along the row direction X, and the active layers T11 -P of each first reset transistor T11 extend along the column direction Y.
  • the active layer T11-RP of the first reset transistor T11-R of the third sub-pixel 230R, the active layer T11-GP of the first reset transistor T11-G of the second sub-pixel 230G, and the active layer T11-GP of the first reset transistor T11-G of the second sub-pixel 230B are sequentially arranged along the first designated direction C1.
  • the first gate metal layer Gate1 includes a reset signal line RST.
  • Reset signal line The RST is located on the side of the active film layer 240 away from the substrate 210 . 5D , the overlapping portion of the reset signal line RST with the active layer T12 -P of the second reset transistor T12 and the active layer T11 -P of each first reset transistor T11 is multiplexed as the second reset transistor T12 The control electrode of each first reset transistor T11.
  • the substrate 210 includes a first display area A1, and a plurality of first pixel units 220 are located in the first display area A1; the display panel 200 also includes: a plurality of signal lines located on the substrate. 210 and the light emitting device 232. It should be noted that the first display area A1 in the substrate 210 and the first display area A1 in the display panel 200 are the same area. The light-emitting device 232 is not shown in FIG. 2B. Please refer to FIG. 3A, FIG. 5A, and FIG. 5B.
  • the portion of at least one signal line located in the first display area A1 includes a metal trace 250 and a transparent connection trace 260 that are electrically connected to each other. At least part of the orthographic projection of the metal trace 250 on the substrate 210 is located within the orthographic projection of the light emitting device 232 on the substrate 210 .
  • the plurality of signal lines in the display panel 200 include a reset signal line RST, a scanning signal line GT, a light emission control signal line EM, an initialization signal line VIN, a first power signal line VDD1 and a second power supply line. Signal line VDD2.
  • the orthographic projection of all metal traces 250 on the substrate 210 is within the orthographic projection of the light emitting device 232 on the substrate 210 .
  • the orthographic projection of part of the metal traces 250 on the substrate 210 is located within the orthographic projection of the light-emitting device 232 on the substrate 210 , and the rest of the entire metal traces 250 are on the substrate.
  • the orthographic projection on the bottom 210 is located outside the orthographic projection of the light emitting device 232 on the substrate 210 .
  • the ends of the metal traces 250 are provided with metal connection portions 2501 .
  • a transparent connecting portion 2601 is provided at the end of the transparent connecting trace 260 .
  • the orthographic projection of the metal connecting portion 2501 on the substrate 210 at least partially coincides with the orthographic projection of the transparent connecting portion 2601 on the substrate 210 .
  • the orthographic projection of the metal connection portion 2501 on the substrate 210 is at least partially located within the orthographic projection of the light emitting device 232 on the substrate 210 .
  • the orthographic projection of the metal connection portion 2501 on the substrate 210 is entirely outside the orthographic projection of the light emitting device 232 on the substrate 210 .
  • the metal traces 250 in a signal line can be connected through transparent connection traces 260. At least part of the transparent connection traces 260 is exposed outside the light-emitting device 232, and the transparent connection traces 260 are transparent traces and can transmit light. Therefore, the light transmittance of the first display area A1 can be improved by connecting the metal traces 250 with the transparent connecting traces 260 .
  • At least a portion of the metal trace 250 is on the substrate 210 Orthographic projection, located within the orthographic projection of anode AND1 of sub-pixel 230 on substrate 210.
  • the reset signal line RST, the scanning signal line GT, the light emission control signal line EM, the initialization signal line VIN, the first power signal line VDD1 and the second power signal line VDD2 are introduced in sequence below.
  • the display panel 200 includes: a first transparent wiring layer 271 located between the substrate 210 and the light emitting device 232 , and the first transparent wiring layer 271 is located between the substrate 210 and the light emitting device 232 .
  • the material of the first gate metal layer Gate1 is metal, such as Al, Ag, Cu, Cr, etc.
  • the material of the first transparent wiring layer 271 is a transparent conductive oxide material, such as ITO, IZO, etc.
  • At least one signal line includes a reset signal line RST.
  • the reset signal line RST includes a metal trace 251 and a transparent connection trace 261 .
  • the metal wiring 251 of the reset signal line RST is located on the first gate metal layer Gate1
  • at least part of the orthographic projection of the metal wiring 251 of the reset signal line RST on the substrate 210 is located on the light-emitting device 232 of the first sub-pixel 230B. within the orthographic projection on substrate 210.
  • the light-emitting device 232 of the first sub-pixel 230B is not shown in FIG. 7B. Please refer to FIG. 5B.
  • a reset signal line RST includes a plurality of metal traces 251, and at least part of the metal trace 251 is located under the light-emitting device 232 of the first sub-pixel 230B. In some examples, the entire section of metal trace 251 is located under the light emitting device 232 of a first sub-pixel 230B. In other examples, a portion of a metal trace 251 is located under the light-emitting device 232 of a first sub-pixel 230B.
  • the metal trace 251 in the reset signal line RST includes a main trace segment 2511 and a connecting trace segment 2512.
  • the main trace segment 2511 extends along the row direction X, and the main trace segment 2511 is connected to each first reset on the substrate 210
  • the active layer T11 -P of the transistor T11 overlaps, wherein the control electrode of the first reset transistor T11 is located on the main wiring segment 2511 .
  • the connection trace segment 2512 extends along the column direction Y and overlaps with the active layer T12-P of the second reset transistor T12.
  • connection wiring section 2512 that overlaps the active layer T12 -P of the second reset transistor T12 is the control electrode of the second reset transistor T12 , that is, the control electrode of the second reset transistor T12 is located on the connection wiring section 2512 .
  • the active layer T12-P of the second reset transistor T12 is not shown in FIG. 6B. Please refer to FIG. 5D and FIG. 6A.
  • the transparent connection trace 261 of the reset signal line RST is located on the first transparent trace layer 271 , and the transparent connection trace 261 of the reset signal line RST is connected to the metal trace 251 of the reset signal line RST through a via hole.
  • the orthographic projection of the transparent connecting trace 261 of the reset signal line RST on the substrate 210 is located outside the orthographic projection of the light-emitting device 232 of the second sub-pixel 230G on the substrate 210 and is located in the third
  • the light emitting device 232 of the subpixel 230R is outside the orthographic projection on the substrate 210 . Therefore, the transparent connection trace 261 of the reset signal line RST will not occupy the space under the light-emitting device 232 of the second sub-pixel 230G and the light-emitting device 232 of the third sub-pixel 230R, thereby increasing the light emission of the second sub-pixel 230G.
  • the area of the device 232 and the pixel driving circuit 231 under the light-emitting device 232 of the third sub-pixel 230R avoids the area of the pixel driving circuit 231 under the light-emitting device 232 of the second sub-pixel 230G and the light-emitting device 232 of the third sub-pixel 230R.
  • the structure is too compact and coupling occurs.
  • the light-emitting device 232 of the third sub-pixel 230R is not shown in FIG. 7B. Please refer to FIG. 5A and FIG. 5B.
  • At least part of the orthographic projection of the metal trace 251 of the reset signal line RST on the substrate 210 is located at the anode of the first sub-pixel 230B AND the orthographic projection of -B on the substrate 210 within.
  • the orthographic projection of the transparent connection trace 261 of the reset signal line RST on the substrate 210 is located outside the orthographic projection of the anode AND-G of the second sub-pixel 230G on the substrate 210 and is located on the anode of the third sub-pixel 230R.
  • AND-R is outside the orthographic projection on substrate 210.
  • the anode AND1 of each sub-pixel 230 is not shown in FIG. 7B. Please refer to FIG. 5B.
  • the circuit body 2311 of the pixel driving circuit 231 includes a writing transistor T4, a compensation transistor T2, and a third reset transistor T7.
  • At least one signal line also includes a scanning signal line GT, which is connected with the control electrodes of the write transistor T4, the control electrode of the compensation transistor T2 and the third reset transistor T7 of all sub-pixels 230 in the first pixel unit 220 in a row.
  • the control electrode is electrically connected.
  • the scanning signal line GT is used to transmit scanning signals, and all sub-pixels 230 in a row of first pixel units 220 receive the same scanning signal.
  • the writing transistor T4 the compensation transistor T2 and the third reset transistor T7 are turned on simultaneously.
  • the metal trace 252 of the scanning signal line GT is located on the first gate metal layer Gate1, and at least part of the orthographic projection of the metal trace 252 of the scanning signal line GT on the substrate 210 is located on the substrate where the light emitting device 232 is located. Within the orthographic projection on 210.
  • the transparent connection wiring 262 of the scanning signal line GT is located on the first transparent wiring layer 271 , and the transparent connection wiring 262 of the scanning signal line GT is connected to the metal wiring 252 of the scanning signal line GT through a via hole.
  • the scanning signal line GT includes a plurality of metal traces 252 , and the orthographic projection of a metal trace 252 on the substrate 210 is at least partially located within the orthographic projection of a light-emitting device 232 on the substrate 210 .
  • the entirety of each section of metal trace 252 is disposed under the light emitting device 232 .
  • a portion of each metal trace 252 is disposed under the light emitting device 232 .
  • At least part of the orthographic projection of the metal trace 252 of the scanning signal line GT on the substrate 210 is located within the orthographic projection of the anode AND1 of the sub-pixel 230 on the substrate 210 . .
  • a section of metal trace 252 in the scanning signal line GT is connected with the control electrode of the write transistor T4, the control electrode of the compensation transistor T2 and the control electrode of the third reset transistor T7 in one sub-pixel 230. Electrical connection.
  • the active film layer 240 includes an active layer T4-P of the write transistor T4, an active layer T2-P of the compensation transistor T2, and an active layer T7-P of the third reset transistor T7. P.
  • the overlapping portion of a section of metal trace 252 and the active layer T4 -P of the write transistor T4 is multiplexed as the control electrode of the write transistor T4 .
  • the overlapping portion of a section of metal trace 252 and the active layer T2-P of the compensation transistor T2 is multiplexed as a control electrode of the compensation transistor T2.
  • the overlapping portion of a section of metal trace 252 and the active layer T7-P of the third reset transistor T7 is multiplexed as the control electrode of the third reset transistor T7. That is, the control electrode of the writing transistor T4, the control electrode of the compensation transistor T2, and the control electrode of the third reset transistor T7 in one sub-pixel 230 are located on a section of metal trace 252.
  • the compensation transistor T2 of each sub-pixel 230 includes a first compensation transistor T21 and a second compensation transistor T22. Among them, the first compensation transistor T21 and the second compensation transistor T22 are connected in series.
  • control electrode of the first compensation transistor T21 is electrically connected to the scanning signal line GT
  • first electrode of the first compensation transistor T21 is electrically connected to the second electrode of the driving transistor T3 and the first electrode of the second light emission control transistor T6.
  • the second electrode of a compensation transistor T21 is electrically connected to the first electrode of the second compensation transistor T22.
  • the control electrode of the second compensation transistor T22 is electrically connected to the scanning signal line GT, and the second electrode of the second compensation transistor T22 is electrically connected to the second electrode of the first reset transistor T11 and the control electrode of the driving transistor T3.
  • the compensation transistor T2 By arranging the compensation transistor T2 as the first compensation transistor T21 and the second compensation transistor T22 connected in series, the effect of preventing current leakage can be achieved.
  • the metal trace 252 of the scanning signal line GT includes a body trace segment 2521 and a connection trace segment 2522.
  • the main trace segment 2521 extends along the row direction X
  • the connecting trace segment 2522 extends along the column direction
  • one end of the connecting trace segment 2522 is connected to the main trace segment 2521.
  • the overlapping portion connecting the wiring segment 2522 and the active layer T2-P of the compensation transistor T2 is multiplexed as the control electrode of the second compensation transistor T22.
  • the overlapping resets of the body trace section 2521 and the active layer T4-P of the write transistor T4, the active layer T2-P of the compensation transistor T2, and the active layer T7-P of the third reset transistor T7 are multiplexed as write The control electrode of the transistor T4, the control electrode of the first compensation transistor T21 and the control electrode of the third reset transistor T7.
  • the active layers of each transistor are not shown in FIG. 6B. Please refer to FIG. 5D and FIG. 6A.
  • a scanning signal line GT includes multiple sections of metal traces 252 and multiple sections of transparent connection traces 262 .
  • the multi-section metal traces 252 include a first section of metal traces 252A, a second section of metal traces 252B and a third section of metal traces 252C. Among them, the metal traces 252 and the multi-section transparent connecting traces 262 are not shown in FIG. 7C. Please refer to FIG. 7B.
  • the orthographic projection of the first section of metal trace 252A on the substrate 210 is at least partially located within the orthographic projection of the light-emitting device 232 of the first sub-pixel 230B on the substrate 210 .
  • the orthographic projection of the second section of metal trace 252B on the substrate 210 is at least partially located within the orthographic projection of the light-emitting device 232 of the second sub-pixel 230G on the substrate 210 .
  • the orthographic projection of the third section of metal trace 252C on the substrate 210 is at least partially located within the orthographic projection of the light emitting device 232 of the third sub-pixel 230R on the substrate 210 .
  • the display panel 200 further includes a second transparent wiring layer 272 .
  • the second transparent wiring layer 272 is located on the side of the first transparent wiring layer 271 away from the substrate 210 , or on the side facing the substrate 210 .
  • the multiple sections of transparent connection wires 262 in one scanning signal line GT include a first section of transparent connection wires 262A, a second section of transparent connection wires 262B, a third section of transparent connection wires 262C and a fourth section of transparent connection wires 262D.
  • the first transparent connecting wire section 262A, the second transparent connecting wire section 262B and the third transparent connecting wire section 262C are located on the first transparent wiring layer 271 .
  • the fourth section of transparent connection wiring 262D is located on the second transparent wiring layer 272.
  • the first section of metal trace 252A electrically connected to the first sub-pixel 230B in each first pixel unit 220 and the third section of metal trace 252C electrically connected to the third sub-pixel 230R are connected through the first section of transparent Trace 262A electrical connection.
  • the first section of metal trace 252A electrically connected to the first sub-pixel 230B in a first pixel unit 220 is electrically connected to the third section of metal trace 252A electrically connected to the third sub-pixel 230R in the adjacent first pixel unit 220 in the row direction X.
  • the section of metal trace 252C is electrically connected through the second section of transparent connecting trace 262B.
  • One end of the third section of transparent connection traces 262C is electrically connected to an end of the second section of metal traces 252B away from the first sub-pixel 230B, and the other end is electrically connected to the fourth section of transparent connection traces 262D.
  • the fourth section of transparent connection traces 262D One end of line 262D away from the third section of transparent connecting wire 262C is electrically connected to the second section of transparent connecting wire 262B.
  • the circuit body 2311 of the pixel driving circuit 231 further includes a first light emission control transistor T5 and a second light emission control transistor T6.
  • At least one signal line also includes a light-emitting control signal line EM.
  • a light-emitting control signal line EM is connected with the control electrodes of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 of all sub-pixels 230 in the first pixel unit 220 in a row. Electrical connection.
  • the luminescence control signal line EM is used to transmit the luminescence control signal, and all the sub-pixels 230 in the first pixel unit 220 in a row receive the same luminescence control signal.
  • the first light-emitting control transistor T5 and the second light-emitting control transistor T6 in the first pixel unit 220 of a row are turned on at the same time.
  • the metal trace 253 of the light emission control signal line EM is located on the first gate metal layer Gate1. At least part of the orthographic projection of the metal trace 253 of the light-emitting control signal line EM on the substrate 210 is located within the orthographic projection of the light-emitting device 232 on the substrate 210 .
  • the transparent connection wiring 263 of the light-emitting control signal line EM is located on the first transparent wiring layer 271. The transparent connection wiring 263 of the light-emitting control signal line EM is connected to the metal wiring 253 of the light-emitting control signal line EM through a via hole.
  • the light-emitting device 232 is not shown in FIG. 7B and FIG. 7C, please refer to FIG. 5A.
  • At least part of the orthographic projection of the metal trace 253 of the emission control signal line EM on the substrate 210 is located within the orthographic projection of the anode AND1 of the sub-pixel 230 on the substrate 210 .
  • the light-emitting control signal line EM includes a plurality of metal traces 253.
  • the orthographic projection of a metal trace 253 on the substrate 210 is at least partially located between the orthographic projection of a light-emitting device 232 on the substrate 210. Inside. In some examples, the entirety of each section of metal trace 253 is disposed under the light emitting device 232 . In other examples, a portion of each metal trace 253 is disposed under the light emitting device 232 .
  • a section of metal trace 253 in the light-emitting control signal line EM is electrically connected to the control electrode of the first light-emitting control transistor T5 and the control electrode of the second light-emitting control transistor T6 in one sub-pixel 230 .
  • the active film layer 240 includes an active layer T5 -P of the first emission control transistor T5 and an active layer T6 -P of the second emission control transistor T6 .
  • the overlapping portion of a section of metal trace 253 and the active layer T5 -P of the first light-emitting control transistor T5 is multiplexed as the control electrode of the first light-emitting control transistor T5 .
  • the overlapping portion of a section of metal trace 253 and the active layer T6 -P of the second light-emitting control transistor T6 is multiplexed as the control electrode of the second light-emitting control transistor T6. That is, the control electrode of the first light-emitting control transistor T5 and the control electrode of the second light-emitting control transistor T6 in one sub-pixel 230 are located on a section of metal trace 252 .
  • the active film layer 240 also includes an active layer T3-P of the driving transistor T3.
  • the first gate metal layer Gate1 also includes a second plate Cst2 of the capacitor Cst.
  • the orthographic projection of the second plate Cst2 on the substrate 210 partially overlaps the orthographic projection of the active layer T3-P of the driving transistor T3 on the substrate 210, wherein the second plate Cst2 and the driving transistor T3 are partially overlapped.
  • the overlapping portion of the active layer T3-P of the transistor T3 serves as the control electrode of the driving transistor T3.
  • a light-emitting control signal line EM includes multiple sections of metal Trace 253 and multiple sections of transparent connection trace 263.
  • the multi-segment metal trace 253 includes a fourth metal trace 253D, a fifth metal trace 253E and a sixth metal trace 253F.
  • the light-emitting control signal line EM, the metal wiring 253 and the transparent connecting wiring 263 are not shown in FIG. 7C. Please refer to FIG. 7B.
  • the orthographic projection of the fourth section of metal trace 253D on the substrate 210 is at least partially located within the orthographic projection of the light-emitting device 232 of the first sub-pixel 230B on the substrate 210 .
  • the orthographic projection of the fifth section of metal trace 253E on the substrate 210 is at least partially located within the orthographic projection of the light emitting device 232 of the second sub-pixel 230G on the substrate 210 .
  • the orthographic projection of the sixth section of metal trace 253F on the substrate 210 is at least partially located within the orthographic projection of the light emitting device 232 of the third sub-pixel 230R on the substrate 210 .
  • the multiple transparent connection traces 263 in a light-emitting control signal line EM include a fifth transparent connection trace 263E, a sixth transparent connection trace 263F and a seventh transparent connection trace 263G, and are all located at The first transparent wiring layer 271.
  • the fourth section of metal trace 253D electrically connected to the first sub-pixel 230B in a first pixel unit 220 is electrically connected to the third sub-pixel 230R in the adjacent first pixel unit 220 in the first specified direction C1.
  • the sixth section of metal traces 253F is electrically connected through the sixth section of transparent connecting traces 263F.
  • One end of the seventh transparent connecting wire 263G is electrically connected to an end of the fifth metal wire 253E electrically connected to the second sub-pixel 230G away from the first sub-pixel 230B, and the other end is electrically connected to the sixth transparent connecting wire 263F. connect.
  • the display panel 200 also includes: a second gate metal layer Gate2.
  • the second gate metal layer Gate2 is located in the active film layer 240 and the light emitting layer. between devices 232.
  • the material of the second gate metal layer Gate2 is metal, such as Al, Ag, Cu, Cr, etc.
  • the circuit body 2311 of the pixel driving circuit 231 also includes: a capacitor Cst.
  • the first plate Cst1 of the capacitor Cst is located on the second gate metal layer Gate2.
  • the second gate metal layer Gate2 is located on a side of the first gate metal layer Gate1 away from the substrate 210 .
  • the orthographic projection of the first plate Cst1 of the capacitor Cst on the substrate 210 and the orthographic projection of the second plate Cst2 on the substrate 210 at least partially overlap.
  • the display panel 200 includes: a first source-drain metal layer SD1 , the first source-drain metal layer SD1 is located between the substrate 210 and the light-emitting device 232 , the first source-drain metal layer SD1 The layer SD1 is located on the side of the second gate metal layer Gate1 facing away from the substrate 210.
  • the first transparent wiring layer 271 is located on the side of the first source-drain metal layer SD1 facing away from the substrate 210.
  • the first transparent wiring layer 271 is located on the side of the first source-drain metal layer SD1 facing away from the substrate 210. between the source-drain metal layer SD1 and the light-emitting device 232.
  • An interlayer dielectric layer ILD is provided between the second gate metal layer Gate1 and the first source-drain metal layer SD1.
  • a plurality of vias ILDO are provided in the interlayer dielectric layer ILD.
  • the interlayer dielectric layer The locations of multiple vias in layer ILD are shown in Figure 9C.
  • the material of the first source-drain metal layer SD1 is metal, such as Al, Ag, Cu, Cr, etc.
  • At least one signal line also includes: an initialization signal line VIN.
  • An initialization signal line VIN is electrically connected to the first pole of the second reset transistor T12 in the first pixel unit 220 of a row.
  • the metal trace 254 of the initialization signal line VIN is located on the first source-drain metal layer SD1.
  • at least part of the orthographic projection of the metal trace 254 of the initialization signal line VIN on the substrate 210 is located within the orthographic projection of the light-emitting device 232 of the first sub-pixel 230B on the substrate 210 .
  • an initialization signal line VIN includes multiple sections of metal traces 254, and a section of the metal traces 254 overlaps with the light-emitting device 232 of a first sub-pixel 230B.
  • a section of metal trace 254 in the initialization signal line VIN is entirely disposed under the light-emitting device 232 of the first sub-pixel 230B.
  • a portion of the metal trace 254 in the initialization signal line VIN is disposed under the light-emitting device 232 of the first sub-pixel 230B.
  • the transparent connection trace 264 of the initialization signal line VIN is partially located under the light-emitting device 232 of the first sub-pixel 230B.
  • the transparent connection trace 264 of the initialization signal line VIN is located on the first transparent trace layer 271 ; the transparent connection trace 264 of the initialization signal line VIN and the metal trace 254 of the initialization signal line VIN are connected through via holes.
  • the orthographic projection of the transparent connection trace 264 of the initialization signal line VIN on the substrate 210 is located outside the orthographic projection of the light-emitting device 232 of the second sub-pixel 230G on the substrate 210 and is located on the third sub-pixel 230R.
  • Light emitting device 232 is outside the orthographic projection on substrate 210 .
  • the transparent connection trace 264 of the initialization signal line VIN will not occupy the space under the light-emitting device 232 of the second sub-pixel 230G and the light-emitting device 232 of the third sub-pixel 230R, thereby increasing the light emission of the second sub-pixel 230G.
  • the area of the pixel driving circuit 231 under the device 232 and the light-emitting device 232 of the third sub-pixel 230R is thereby avoided.
  • the structure of circuit 231 is too compact and coupling occurs. Among them, the light-emitting device 232 and the third sub-pixel 230G of the second sub-pixel 230G are not shown in FIG. 7B.
  • the light-emitting device 232 of the pixel 230R please refer to FIG. 5B.
  • At least part of the orthographic projection of the metal trace 254 of the initialization signal line VIN on the substrate 210 is located on the orthogonal surface of the anode AND-B of the first sub-pixel 230B on the substrate 210 . within the projection.
  • the orthographic projection of the transparent connection trace 264 of the initialization signal line VIN on the substrate 210 is located outside the orthographic projection of the anode AND-G of the second sub-pixel 230G on the substrate 210 and is located on the anode of the third sub-pixel 230R.
  • AND-R is outside the orthographic projection on substrate 210.
  • the metal trace 254 in the initialization signal line VIN includes a body trace segment 2541 and a connection trace segment 2542, wherein the body trace segment 2541 extends along the row direction X, and the connection trace segment 2542 2542 extends along the column direction Y, and one end of the main wiring segment 2541 close to the third sub-pixel 230R is connected to the connecting wiring segment 2542.
  • One end of the active layer T12-P of the second reset transistor T12 close to the third sub-pixel 230R is connected to the middle part of the connecting wiring segment 2542 through a via hole, and the end of the connecting wiring segment 2542 away from the main wiring segment 2541 is connected to the middle part of the connecting wiring segment 2542.
  • the active layer T7-P of the third reset transistor T7 in the first sub-pixel 230B is connected through a via hole.
  • the display panel 200 further includes a first transparent connection 281 , the first transparent connection 281 is located on the first transparent wiring layer 271 , and one end of the first transparent connection 281 is connected to the wiring segment 2542 One end of the wiring segment 2541 away from the main body is electrically connected, and the other end is electrically connected to the active layer T7-P of the third reset transistor T7 in the third sub-pixel 230R.
  • the display panel 200 further includes a second transparent connection 282 and a third transparent connection 283 , where the second transparent connection 282 is located on the first transparent wiring layer 271 , and the third transparent connection 283 is located on the second transparent wiring layer 272.
  • one end of the second transparent connection 282 is electrically connected to the active layer T7-P of the third reset transistor T7 of the second sub-pixel 230G, and the other end is electrically connected to the third transparent connection 283, and the third transparent connection
  • the end of 283 away from the second transparent connection 282 is connected to the end of the first transparent connection 281 connected to the connecting trace section 2542 through a via hole.
  • the display panel 200 also includes fourth transparent connections 284 and fifth transparent connections 285 , where both the fourth transparent connections 284 and the fifth transparent connections 285 are located on the first transparent wiring layer 271 .
  • One end of the fifth transparent connection 285 is electrically connected to the active layer T11-GP of the first reset transistor T11-G in the second sub-pixel 230G, and the other end is connected to the control electrode of the driving transistor T3 in the second sub-pixel 230G, that is, the capacitor.
  • the second plate Cst2 of Cst is electrically connected.
  • One end of the fourth transparent connection 284 is electrically connected to the active layer T11-RP of the first reset transistor T11-R in the third sub-pixel 230R, and the other end is connected to the control electrode of the driving transistor T3 in the third sub-pixel 230R, that is, the capacitor.
  • the second plate Cst2 of Cst is electrically connected.
  • the first source-drain metal layer SD1 also includes It includes a plurality of bridge patterns, and the bridge patterns are connected to the active film layer 240, the first gate metal layer Gate1 and the second gate metal layer Gate2 through via holes.
  • the plurality of bridge patterns include a first bridge pattern 510 , and one end of the first bridge pattern 510 is connected to the active layer T6 -P of the second light emission control transistor T6 through a via hole. , the other end is connected to the active layer T7-P of the third reset transistor T7 through a via hole.
  • the plurality of bridge patterns include a second bridge pattern 520.
  • One end of the second bridge pattern 520 passes through the control electrode of the driving transistor T3, that is, the second plate Cst2 of the capacitor Cst.
  • the other end is connected to the active layer T2-P of the compensation transistor T2 through a via hole.
  • the plurality of bridge patterns include a third bridge pattern 530.
  • One end of the third bridge pattern 530 is connected to the first plate Cst1 of the capacitor Cst through a via hole, and the other end is connected to the first plate Cst1 of the capacitor Cst.
  • the active layer T5-P of a light emission control transistor T5 is connected through a via hole.
  • the orthographic projection of the plurality of bridge patterns on the substrate 210 is also located within the orthographic projection of the anode AND1 on the substrate 210 .
  • the display panel 200 includes: a second source-drain metal layer SD2 , the second source-drain metal layer SD2 is located between the substrate 210 and the light-emitting device 232 , and the second source-drain metal layer SD2 The metal layer SD2 is located on a side of the second gate metal layer Gate2 facing away from the substrate 210 .
  • the display panel 200 further includes: a second transparent wiring layer 272 , the second transparent wiring layer 272 is located between the substrate 210 and the light-emitting device 232 , and the second transparent wiring layer 272 is located between the substrate 210 and the light-emitting device 232 .
  • the second source-drain metal layer SD2 is located on a side of the first source-drain metal layer SD1 facing away from the substrate 210 .
  • the material of the second source-drain metal layer SD2 is metal, such as Al, Ag, Cu, Cr, etc.
  • the material of the second transparent wiring layer 272 is a transparent conductive oxide material, such as ITO, IZO, etc.
  • the display panel 200 further includes a first source-drain metal layer SD1 and a first transparent wiring layer 271
  • the wiring layer 271 and the second transparent wiring layer 272 are sequentially provided on the side of the second gate metal layer Gate2 facing away from the substrate 210 .
  • the first source-drain metal layer SD1, the first transparent wiring layer 271, the second source-drain metal layer SD2 and the second transparent wiring layer 272 are sequentially provided on the second gate metal layer Gate2 facing away from the substrate 210 side.
  • a passivation layer PVX is provided between the first source-drain metal layer SD1 and the first transparent wiring layer 271, and a plurality of via holes PVXO are provided in the passivation layer PVX.
  • a first planarization layer PLN1 is provided between the first transparent wiring layer 271 and the second source-drain metal layer SD2 , and a plurality of via holes PLNO1 is provided in the first planarization layer PLN1 .
  • a second planarization layer PLN2 is provided between the second source-drain metal layer SD2 and the second transparent wiring layer 272, and a plurality of via holes PLNO2 are provided in the second planarization layer PLN2.
  • At least one signal line also includes a first power signal line VDD1 extending along the column direction Y.
  • a first power signal line VDD1 is connected to the second sub-pixel 230G in a column of first pixel units 220
  • the first plate Cst1 of the capacitor Cst and the first plate Cst1 of the capacitor Cst of the third sub-pixel 230R are electrically connected.
  • the first power signal line VDD1 extends along the column direction Y, which means that the main pattern of the first power signal line VDD1 tends to extend along a certain column direction Y.
  • the pattern of the first power signal line VDD1 may be a straight line pattern or an approximately straight line pattern.
  • the first power signal line VDD1 is used to transmit the first type of power signal.
  • the first power signal line VDD1 is electrically connected to the first plate Cst1 of the capacitor Cst, thereby transmitting the first type of power signal to the first plate Cst1.
  • the metal trace 255 of the first power signal line VDD1 is located on the second source-drain metal layer SD2 . At least part of the orthographic projection of the metal trace 255 of the first power signal line VDD1 on the substrate 210 is located on the second source-drain metal layer SD2 .
  • the light-emitting device 232 of the sub-pixel 230G and the light-emitting device 232 of the third sub-pixel 230R are within orthographic projection on the substrate 210 .
  • the transparent connection traces 265 of the first power signal line VDD1 are located on the second transparent trace layer 272 .
  • the transparent connection traces 265 of the first power signal line VDD1 are connected to the metal traces 255 of the first power signal line VDD1 through via holes. Among them, the light-emitting device 232 of the second sub-pixel 230G and the light-emitting device 232 of the third sub-pixel 230R are not shown in FIG. 11B. Please refer to FIG. 5C.
  • At least part of the orthographic projection of the metal trace 255 of the first power signal line VDD1 on the substrate 210 is located at the anode AND-G of the second sub-pixel 230G and the third sub-pixel.
  • the anode AND-R of 230R is within the orthographic projection on the substrate 210 .
  • the anode AND-G of the second sub-pixel 230G and the anode AND-R of the third sub-pixel 230R are not shown in FIG. 11B, please refer to FIG. 5C.
  • the first power supply signal line VDD1 includes multiple sections of metal traces 255 , wherein the multiple sections of metal traces 255 in the first power signal line VDD1 include a seventh section of metal traces 255G and an eighth section. Segment metal trace 255H.
  • the entire orthographic projection of the seventh section of metal trace 255G on the substrate 210 is located within the orthographic projection of the light emitting device 232 of the second sub-pixel 230G on the substrate 210 .
  • the entire orthographic projection of the eighth section of metal trace 255H on the substrate 210 is located within the orthographic projection of the light-emitting device 232 of the third sub-pixel 230R on the substrate 210 .
  • the seventh section of metal trace 255G and the eighth section of metal trace 255H are electrically connected through a transparent connection trace 265, and the transparent connection trace 265 extends to the third sub-image. under the light-emitting device 232 of the pixel 230R and under the light-emitting device 232 of the second sub-pixel 230G.
  • the part of the orthographic projection of the seventh section of metal trace 255G on the substrate 210 is located within the orthographic projection of the light-emitting device 232 of the second sub-pixel 230G on the substrate 210, and the remaining part is located on the second sub-pixel 230G.
  • Light emitting device 232 of pixel 230G is outside the orthographic projection on substrate 210 .
  • the part of the orthographic projection of the eighth section of metal trace 255H on the substrate 210 is located within the orthographic projection of the light-emitting device 232 of the third sub-pixel 230R on the substrate 210, and the remaining part is located on the light-emitting device 232 of the third sub-pixel 230R. outside the orthographic projection on substrate 210.
  • the first power signal line VDD1 includes multiple segments of transparent connection traces 265 , and the multiple segments of transparent connection traces 265 include an eighth segment of transparent connection traces 265H and a ninth segment of transparent connection traces 265I. .
  • the seven sections of metal traces 255G are electrically connected through the ninth section of transparent connection traces 265I.
  • the seventh section of metal trace 255G of the first power signal line VDD1 is connected to the third bridge pattern 530 located under the light emitting device 232 of the second sub-pixel 230G through a via hole.
  • the first type power signal line is transmitted to the first plate Cst1 of the capacitor Cst and the active layer T5-P of the first light emission control transistor T5 in the second sub-pixel 230G through the third bridge pattern 530.
  • the eighth section of metal trace 255H of the first power signal line VDD1 is connected to the third bridge pattern 530 located under the light emitting device 232 of the third sub-pixel 230R through a via hole.
  • the first type power supply signal line is transmitted to the first plate Cst1 of the capacitor Cst and the active layer T5-P of the first light emission control transistor T5 in the third sub-pixel 230R through the third bridge pattern 530.
  • At least one signal line also includes a second power signal line VDD2 extending along the column direction Y, and a second power signal line VDD2 is connected to a column of first pixel units 220
  • the first plate Cst1 of the capacitor Cst of the first sub-pixel 230B is electrically connected.
  • the second power signal line VDD2 extends along the column direction Y, which means that the main pattern of the second power signal line VDD2 tends to extend along a certain column direction Y.
  • the pattern of the second power signal line VDD2 may be a straight line pattern or an approximately straight line pattern.
  • the second power signal line VDD2 is used to transmit the first type of power signal.
  • the second power signal line VDD2 is electrically connected to the first plate Cst1 of the capacitor Cst of the first sub-pixel 230B, thereby transmitting the first type of power signal to the first plate Cst1 of the first sub-pixel 230B.
  • the metal trace 256 of the second power signal line VDD2 is located on the second source-drain metal layer SD2 , and the orthographic projection of the metal trace 256 of the second power signal line VDD2 on the substrate 210 is at least partially located on the first sub-layer SD2 .
  • the light-emitting device 232 of the pixel 230B is within the orthographic projection on the substrate 210; the transparent connection trace 266 of the second power signal line VDD2 is located on the second transparent wiring layer 272, and the transparent connection trace 266 of the second power signal line VDD2 266 is connected to the metal trace 256 of the second power signal line VDD2 through a via hole.
  • the light-emitting device 232 of the first sub-pixel 230B is not shown in FIG. 11B. Please refer to FIG. 5C.
  • the orthographic projection of the metal trace 256 of the second power signal line VDD2 on the substrate 210 is entirely within the orthographic projection of the light emitting device 232 of the first sub-pixel 230B on the substrate 210 .
  • the orthographic projection of the transparent connection trace 266 of the second power signal line VDD2 on the substrate 210 partially overlaps with the orthographic projection of the light-emitting device 232 of the first sub-pixel 230B on the substrate 210 .
  • the portion of the orthographic projection of the metal trace 256 of the second power signal line VDD2 on the substrate 210 is located within the orthographic projection of the light-emitting device 232 of the first sub-pixel 230B on the substrate 210 .
  • the orthographic projection of the metal trace 256 of the second power signal line VDD2 on the substrate 210 is at least partially located within the orthographic projection of the AND-B of the first sub-pixel 230B on the substrate 210 .
  • the metal trace 256 of the second power signal line VDD2 is connected to the third bridge pattern 530 located under the light emitting device 232 of the first sub-pixel 230B through a via hole, thereby connecting the first The power-like signal is transmitted to the first plate Cst1 of the capacitor Cst and the active layer T5-P of the first light emission control transistor T5 in the first sub-pixel 230B through the third bridge pattern 530.
  • the display panel 200 also includes data lines DT.
  • the display panel 200 further includes: a plurality of data lines DT extending along the column direction Y.
  • the fact that the data line DT extends along the column direction Y means that the main pattern of the data line DT tends to extend along a certain column direction Y.
  • the data line DT pattern may be a straight line pattern or an approximately straight line pattern.
  • the portion of the plurality of data lines DT located in the first display area A1 is on the substrate 210
  • the orthographic projection on the substrate 210 is located outside the orthographic projection of the light-emitting device 232 of any sub-pixel 230 on the substrate 210 .
  • the data line DT does not occupy the space under the light-emitting device 232, thereby increasing the space occupied by the pixel driving circuit 231 under the light-emitting device 232, and preventing the pixel driving circuit 231 under the light-emitting device 232 from being too compact.
  • the portion of at least one data line DT located in the first display area A1 is located in the second transparent wiring layer 272 .
  • the part of the data line DT located in the first display area A1 is provided on the second transparent wiring layer 272.
  • the part of the data line DT located in the first display area A1 will not block the light, thereby improving the efficiency of the display panel 200.
  • the circuit body 2311 of the pixel driving circuit 231 includes a writing transistor T4.
  • the first poles are respectively connected to different data lines DT. 7C does not show the writing transistor T4 of the first sub-pixel 230B, the first electrode of the writing transistor T4 of the second sub-pixel 230G, and the writing transistor T4 of the third sub-pixel 230R. Please refer to FIG. 5D .
  • the data line DT is used to transmit data signals.
  • the first electrode of the writing transistor T4 is electrically connected to the data line DT, so that the data signal can be transmitted to the first electrode of the writing transistor T4.
  • multiple sub-pixels 230 are respectively connected to different data lines DT.
  • the voltages of data signals in different data lines DT may be different, so that the light-emitting devices 232 in different sub-pixels 230 may have Different grayscales.
  • the first reset transistor T11 and the second reset transistor T12 in the plurality of sub-pixels 230 are turned on at the same time, so the pixel driving circuit 231 in the plurality of sub-pixels 230 At the same time it is in the reset phase.
  • the compensation transistor T2, the writing transistor T4 and the third reset transistor T7 are turned on at the same time, so the pixel driving circuit 231 in the multiple sub-pixels 230 is in the data refresh and compensation phase t2 at the same time.
  • the data signal is written
  • the transistor T4 and the compensation transistor T2 are written to the control electrode of the driving transistor T3, so the data signal is written to the pixel driving circuit 231 in a first pixel unit 220 at the same time.
  • the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on at the same time, so the pixel driving circuits 231 in the plurality of sub-pixels 230 are in the light-emitting stage t3 at the same time.
  • multiple sub-pixels 230 emit light at the same time.
  • the portion where at least one data line DT is located in the first display area A1 is a transparent wiring segment 27 .
  • the transparent wiring segment 27 is located in the second transparent wiring layer 272.
  • the second transparent wiring layer 272 also includes a transparent connection pattern 2701, wherein the transparent connection pattern 2701 is generally along the row direction. Extending toward X, one end of the transparent connection pattern 2701 is connected to the transparent wiring segment 27, and the other end is electrically connected to the active layer T4-P of the writing transistor T4.
  • the first source-drain metal layer SD1 further includes a fourth bridge pattern 540 .
  • Transfer patterns are provided in both the first transparent wiring layer 271 and the second source-drain metal layer SD2.
  • One end of the transparent connection pattern 2701 away from the transparent wiring segment 27 is connected to the transfer pattern via hole in the second source-drain metal layer SD2 through a via hole, and the transfer pattern in the second source-drain metal layer SD2 is connected to the first transfer pattern via the via hole.
  • the transfer patterns in the transparent wiring layer 271 are connected via vias, and the transfer patterns in the first transparent wiring layer 271 are connected via vias to the fourth bridge patterns 540 , and the fourth bridge patterns 540 are connected to the active terminal of the write transistor T4
  • the layers T4-P are connected via vias, thereby allowing data signals to be transmitted to the first pole of the write transistor T4.
  • the via hole depth can be reduced. Since the deeper the via, the greater the impedance, in some examples of the present disclosure, the impedance can be reduced.
  • each data line DT located in the first display area A1 is located on the second transparent wiring layer 272 , that is, each data line DT includes a transparent wiring segment 27 .
  • the orthographic projection of the transparent wiring segment 27-B of the data line DT-B electrically connected to the writing transistor T4 in the first sub-pixel 230B on the substrate 210 is located on the side away from the orthographic projection of the circuit body 2311 -G of the second sub-pixel 230G on the substrate 210 .
  • the orthographic projection of the light-emitting device 232 of the second sub-pixel 230G on the substrate 210 and the orthographic projection of the light-emitting device 232 of the third sub-pixel 230R on the substrate 210 are electrically connected to the writing transistor T4 of the second sub-pixel 230G.
  • the orthographic projection of the transparent wiring section 27-G of the data line DT-G on the substrate 210 and the transparent wiring section 27-R of the data line DT-R electrically connected to the writing transistor T4 of the third sub-pixel 230G are on the substrate. between orthographic projections on bottom 210.
  • the transparent wiring segment 27-G electrically connected to the second sub-pixel 230G and the transparent wiring segment 27-R electrically connected to the third sub-pixel 230G are respectively arranged in the column where the second sub-pixel 230G and the third sub-pixel 230G are located. both sides.
  • the transparent trace segments 27 -R, the transparent trace segments 27 -G, and the transparent trace segments 27 -B are sequentially arranged along the first designated direction C1.
  • the transparent trace segments 27-G, the transparent trace segments 27-R, and the transparent trace segments 27-B are sequentially arranged along the first designated direction C1.
  • the third reset transistor T7 , the compensation transistor T2 and the write transistor T4 in the first sub-pixel 230B are sequentially away from the circuit of the second sub-pixel 230G Subject 2311-G. That is, the third reset crystal in the first sub-pixel 230B
  • the transistor T7, the compensation transistor T2 and the writing transistor T4 are sequentially away from the columns where the second sub-pixel 230G and the third sub-pixel 230R are located, so that the transparent wiring segment 27-B electrically connected to the first sub-pixel 230B can be located in the first sub-pixel.
  • 230B is away from the side of the column where the second sub-pixel 230G and the third sub-pixel 230R are located.
  • the third reset transistor T7, the compensation transistor T2 and the write transistor T4 in the second sub-pixel 230G are sequentially arranged along the first setting direction;
  • the third reset transistor T7, the compensation transistor T2 and the writing transistor T4 in the third sub-pixel 230R are sequentially arranged in the opposite direction of the first set direction.
  • the transparent wiring segment 27 is electrically connected to the active layer T4-P of the writing transistor T4.
  • the writing transistor T4 is located on a side of the compensation transistor T2 away from the first subpixel 230B.
  • the write transistor T4 is located on the side of the compensation transistor T2 close to the first sub-pixel 230B. Therefore, the transparent wiring segment 27-G electrically connected to the second sub-pixel 230G and the transparent wiring segment 27-R of the third sub-pixel 230R can be respectively disposed on both sides of the column where the second sub-pixel 230G and the third sub-pixel 230R are located. , and can facilitate the connection between the transparent wiring section 27-R and the writing transistor T4 of the third sub-pixel 230R, and at the same time facilitate the connection between the transparent wiring section 27-G and the writing transistor T4 of the second sub-pixel 230G.
  • the first set direction D is opposite to the first specified direction C1.
  • the transparent wiring segment 27-R and the second sub-pixel 230G electrically connected to the third sub-pixel 230R are electrically connected to each other.
  • the connected transparent wiring segments 27-G and the data lines 27-B electrically connected to the first sub-pixel 230B are sequentially arranged along the first designated direction C1.
  • the first set direction D is the same as the first designated direction C1, the transparent wiring segment 27-G electrically connected to the second sub-pixel 230G, and the transparent wiring segment 27-G electrically connected to the third sub-pixel 230R.
  • R and the data lines 27-B electrically connected to the first sub-pixel 230B are sequentially arranged along the first designated direction C1.
  • the display panel 200 also includes an anode layer AND.
  • the anode layer AND includes a plurality of anodes AND1, such as the anode AND-B of the first sub-pixel 230B and the anode AND-G of the second sub-pixel 230G. and the anode AND-R of the third sub-pixel 230R.
  • the display panel 200 also includes: a second display area A2 .
  • the first display area A1 is provided with the first pixel unit 220 .
  • a plurality of second pixel units 290 are provided in the second display area A2, and the plurality of second pixel units 290 are arranged in multiple rows and multiple columns; the second pixel unit 290 includes a plurality of sub-pixels 291.
  • the plurality of sub-pixels 291 include a first sub-pixel 291B, a second sub-pixel 291G and a third sub-pixel 291R,
  • the second display area A2 is located on at least one side of the first display area A1. In some examples, the second display area A2 may be disposed on one or more sides of the first display area A1. In other examples, the second display area A2 may be arranged around the first display area A1. It should be noted that in Figure 2B, the area framed by the smaller dotted line frame is the first display area A1, and the larger dotted line frame is located outside the smaller dotted line frame. The smaller dotted line frame and the larger dotted line frame The area between the frames is the second display area A2, and the first display area A1 and the second display area A2 together constitute the display area AA.
  • the sub-pixel 291 of the second pixel unit 290 includes a light-emitting device 232 .
  • the area of the light-emitting device 232 of the first sub-pixel 291B of the second pixel unit 290 is larger than that of the second sub-pixel 291G of the second pixel unit 290 .
  • the area of the light-emitting device 232 is larger than the area of the light-emitting device 232 of the third sub-pixel 291R of the second pixel unit 290.
  • the light-emitting device 232 includes an anode AND1.
  • the area of the anode AND1 of the first sub-pixel 291B of the second pixel unit 290 is larger than the area of the anode AND1 of the second sub-pixel 291G of the second pixel unit 290, and is larger than the area of the third electrode AND1 of the second sub-pixel 291G of the second pixel unit 290.
  • the area of the light-emitting device 232 of the sub-pixel 230 in the first display area A1 is 0.4 to 0.6 times the area of the light-emitting device 232 of the sub-pixel 291 of the same color in the second display area A2.
  • the first sub-pixel 291B of the second pixel unit 290 may be a blue sub-pixel
  • the second sub-pixel 291G may be a green sub-pixel
  • the third sub-pixel 291R may be a red sub-pixel. pixels.
  • the first sub-pixel 230B of the first pixel unit 220 is a blue sub-pixel
  • the second sub-pixel 230G is a green sub-pixel
  • the third sub-pixel 230R is a red sub-pixel.
  • the area of the light-emitting device 232 of the first sub-pixel 230B of the first pixel unit 220 is 0.4 to 0.6 times the area of the light-emitting device 232 of the first sub-pixel 291B of the second pixel unit 290, so that it can be avoided
  • the area of the light-emitting device 232 of the first sub-pixel 230B of the first pixel unit 220 is too large (for example, greater than 0.6 times the area of the light-emitting device 232 of the first sub-pixel 291B), resulting in a low light transmittance of the first display area A1 .
  • the area of the light-emitting device 232 of the first sub-pixel 230B of the first pixel unit 220 is too small (for example, less than 0.4 times the area of the light-emitting device 232 of the first sub-pixel 291B), causing the area to be located in the first pixel unit 220
  • the pixel driving circuit 231 under the light-emitting device 232 of the first sub-pixel 230B occupies a small area, making the structure of the pixel driving circuit 231 of the light-emitting device 232 of the first sub-pixel 230B of the first pixel unit 220 too compact. , causing coupling between structures.
  • the area of the light-emitting device 232 of the first sub-pixel 230B of the first pixel unit 220 is It is 0.5 times the area of the light-emitting device 232 of the first sub-pixel 291B of the second pixel unit 290.
  • the area of the light-emitting device 232 of the second sub-pixel 230G of the first pixel unit 220 is 0.4 to 0.6 times the area of the light-emitting device 232 of the second sub-pixel 291G of the second pixel unit 290 . This can avoid The area of the light-emitting device 232 of the second sub-pixel 230G of the first pixel unit 220 is too large (for example, greater than 0.6 times the area of the light-emitting device 232 of the second sub-pixel 291G), resulting in a low light transmittance of the first display area A1 .
  • the area of the light-emitting device 232 of the second sub-pixel 230G of the first pixel unit 220 is too small (for example, less than 0.4 times the area of the light-emitting device 232 of the second sub-pixel 291G), causing the first pixel unit 220 to
  • the circuit body 2311-G of the second sub-pixel 230G under the light-emitting device 232 of the second sub-pixel 230G occupies a smaller area, so that the circuit body 2311-G of the second sub-pixel 230G of the first pixel unit 220
  • the structure is too compact, causing coupling between structures.
  • the area of the light-emitting device 232 of the second sub-pixel 230G of the first pixel unit 220 is 0.5 times the area of the light-emitting device 232 of the second sub-pixel 291G of the second pixel unit 290.
  • the area of the light-emitting device 232 of the third sub-pixel 230R of the first pixel unit 220 is 0.4 to 0.6 times the area of the light-emitting device 232 of the third sub-pixel 291R of the second pixel unit 290 .
  • the area of the light-emitting device 232 of the third sub-pixel 230R of the first pixel unit 220 is too large (for example, greater than 0.6 times the area of the light-emitting device 232 of the third sub-pixel 291R), resulting in the transparency of the first display area A1.
  • the light rate is lower.
  • the area of the light-emitting device 232 of the third sub-pixel 230R of the first pixel unit 220 is too small (for example, less than 0.4 times the area of the light-emitting device 232 of the third sub-pixel 291R), causing the first pixel unit 220 to
  • the circuit body 2311-R of the third sub-pixel 230R under the light-emitting device 232 of the third sub-pixel 230R occupies a small area, making the structure of the circuit body 2311-R of the third sub-pixel 230R too compact, causing the structure to be too compact. coupling occurs between them.
  • the area of the light-emitting device 232 of the third sub-pixel 230R of the first pixel unit 220 is 0.5 times the area of the light-emitting device 232 of the third sub-pixel 291R of the second pixel unit 290.
  • the sub-pixel density of the first display area A1 is equal to the sub-pixel density of the second display area A2. It should be noted that the sub-pixel density of the first display area A1 refers to the number of sub-pixels 230 per unit area in the first display area A1. The sub-pixel density of the second display area A2 refers to the number of sub-pixels 291 per unit area in the second display area A2.
  • the sub-pixel density of the first display area A1 is the same as that of the light-emitting device 232 of the sub-pixel 291 in the second display area A2.
  • the sub-pixel densities of the second display area A2 are equal, therefore, the display difference between the first display area A1 and the second display area A2 can be reduced.
  • the light transmittance of the first display area A1 is greater than the light transmittance of the second display area A2, thereby ensuring that the sensor 300 can sense sufficient light.
  • the structure of the light-emitting device 232 of the sub-pixel 291 is the same as the structure of the light-emitting device 232 of the above-mentioned sub-pixel 230, and will not be described again here. It can be understood that among the cathode CTD1, luminescent layer EL and anode AND1 of a sub-pixel 291, if the area of the cathode CTD1 is the largest, then the area of the light-emitting device 232 of the sub-pixel 291 is the area of the cathode CTD1. If the area of the anode AND1 is the largest, then the area of the light emitting device 232 of the sub-pixel 291 is the area of the anode AND1. If the area of the light-emitting layer EL is the largest, then the area of the light-emitting device 232 of the sub-pixel 291 is the area of the light-emitting layer EL.
  • the display device 100 provided by some embodiments of the present disclosure includes: the display panel 200 provided by any of the above embodiments. Therefore, the display device 100 provided by some embodiments of the present disclosure has all the beneficial effects of the display panel 200 provided by any of the above embodiments, which will not be described again here.

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Abstract

一种显示面板。显示面板包括：衬底和多个第一像素单元。多个第一像素单元位于衬底的一侧，且呈多行多列排布；其中，第一像素单元中包括多个子像素，子像素包括像素驱动电路和发光器件；发光器件位于像素驱动电路远离衬底的一侧，且与像素驱动电路电连接；像素驱动电路包括第一复位晶体管；多个子像素包括第一子像素、第二子像素和第三子像素，且第一子像素的发光器件的面积，大于第二子像素的发光器件的面积，且大于第三子像素的发光器件的面积；第二子像素中的第一复位晶体管和/或第三子像素中的第一复位晶体管在衬底上的正投影，位于第一子像素的发光器件在衬底上的正投影之内。

Description

显示面板及显示装置
本申请要求于2022年04月29日提交的、申请号为202210468937.6的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
目前，OLED(organic light-emitting diode，有机发光二极管)显示装置因其具有自发光、快速响应、宽视角和可制作在柔性衬底上等特点，受到广泛应用，OLED显示装置包括多个子像素，各子像素包括像素驱动电路和发光器件，通过像素驱动电路驱动发光器件发光，从而实现显示。
发明内容
一方面，提供一种显示面板。所述显示面板包括：衬底和多个第一像素单元。所述多个第一像素单元位于所述衬底的一侧，且呈多行多列排布；其中，所述第一像素单元中包括多个子像素，所述子像素包括像素驱动电路和发光器件；所述发光器件位于所述像素驱动电路远离所述衬底的一侧，且与所述像素驱动电路电连接；所述像素驱动电路包括第一复位晶体管。
所述多个子像素包括第一子像素、第二子像素和第三子像素，且所述第一子像素的发光器件的面积，大于所述第二子像素的发光器件的面积，且大于所述第三子像素的发光器件的面积。
所述第二子像素中的第一复位晶体管和/或所述第三子像素中的第一复位晶体管在所述衬底上的正投影，位于所述第一子像素的发光器件在所述衬底上的正投影之内。
在一些实施例中，所述第一子像素的第一复位晶体管、所述第二子像素的第一复位晶体管和所述第三子像素的第一复位晶体管，均位于所述第一子像素的发光器件在所述衬底的正投影之内。
在一些实施例中，所述第一子像素的第一复位晶体管、所述第二子像素的第一复位晶体管和所述第三子像素的第一复位晶体管中的至少两个，为同一晶体管。
在一些实施例中，所述像素驱动电路还包括第二复位晶体管；所述第一子像素的第二复位晶体管、所述第二子像素的第二复位晶体管和所述第三子像素的第二复位晶体管，为同一晶体管；所述第二复位晶体管在所述衬底上的正投影，位于所述第一子像素的发光器件在所述衬底上的正投影之内；所 述第二复位晶体管与任一所述第一复位晶体管串联。
所述显示面板还包括复位信号线和初始化信号线；各个所述第一复位晶体管的控制极和所述第二复位晶体管的控制极均与所述复位信号线电连接；所述第二复位晶体管的第一极与所述初始化信号线电连接，所述第二复位晶体管的第二极与各个所述第一复位晶体管的第一极电连接。
所述像素驱动电路还包括：驱动晶体管，各个所述像素驱动电路的驱动晶体管的控制极与各个所述第一复位晶体管的第二极电连接。
在一些实施例中，所述第二子像素的发光器件和所述第三子像素的发光器件沿列方向间隔设置；所述第一子像素的发光器件，位于所述第二子像素的发光器件和所述第三子像素的发光器件所在列的相邻列；且所述第一子像素的发光器件，跨过所述第二子像素的发光器件和所述第三子像素的发光器件之间的间隙区域。
所述像素驱动电路还包括电路主体；所述第一子像素的电路主体在所述衬底上的正投影位于所述第一子像素的发光器件在所述衬底上的正投影之内，所述第二子像素的电路主体在所述衬底上的正投影位于所述第二子像素的发光器件在所述衬底上的正投影之内、所述第三子像素的电路主体在所述衬底上的正投影位于所述第三子像素的发光器件在所述衬底上的正投影之内。
在一些实施例中，所述第二复位晶体管、所述第三子像素的第一复位晶体管和所述第二子像素的第一复位晶体管，位于所述第一子像素的第一复位晶体管靠近所述第三子像素的电路主体的一侧，且依次远离所述第三子像素的电路主体。
在一些实施例中，所述复位信号线沿行方向延伸，一条所述复位信号线与一行所述第一像素单元中所述第二复位晶体管的控制极以及各个所述第一复位晶体管的控制极电连接，所述初始化信号线沿行方向延伸，一条所述初始化信号线与一行所述第一像素单元中所述第二复位晶体的第一极电连接。
所述第二复位晶体管以及各个所述第一复位晶体管在所述衬底上的正投影，位于与该第二复位晶体管所电连接的初始化信号线在所述衬底上的正投影和所述第三子像素的电路主体在所述衬底上的正投影之间；所述复位信号线在所述衬底上的正投影，位于该条初始化信号线在所述衬底上的正投影和该第三子像素的电路主体在所述衬底上的正投影之间。
在一些实施例中，所述衬底包括第一显示区，所述多个第一像素单元位于所述第一显示区内。
所述显示面板还包括：多条信号线，位于所述衬底和所述发光器件之间；至少一条信号线位于所述第一显示区内的部位包括彼此电连接的金属走线和透明连接走线；至少部分所述金属走线在所述衬底上的正投投影，位于所述发光器件在所述衬底上的正投影之内。
在一些实施例中，所述显示面板包括：第一栅金属层和第一透明走线层，均位于所述衬底和所述发光器件之间，所述第一透明走线层位于所述第一栅金属层背离所述衬底的一侧。
所述至少一条信号线包括复位信号线，所述复位信号线沿行方向延伸，一条所述复位信号线与一行所述第一像素单元中所述第二复位晶体管的控制极以及各个第一复位晶体管的控制极电连接。
所述复位信号线的金属走线位于所述第一栅金属层，所述复位信号线的金属走线在所述衬底上的正投影的至少部分位于所述第一子像素的发光器件在所述衬底上的正投影之内；所述复位信号线的透明连接走线位于所述第一透明走线层；所述复位信号线的透明连接走线在所述衬底上的正投影，位于所述第二子像素的发光器件在所述衬底上的正投影之外，且位于所述第三子像素的发光器件在所述衬底上的正投影之外；所述复位信号线的透明连接走线与所述复位信号线的金属走线通过过孔连接。
在一些实施例中，所述像素驱动电路的电路主体包括写入晶体管、补偿晶体管和第三复位晶体管；所述至少一条信号线还包括扫描信号线，一条所述扫描信号线与一行所述第一像素单元中所有所述子像素的写入晶体管的控制极、补偿晶体管的控制极和第三复位晶体管的控制极电连接。
所述扫描信号线的金属走线位于所述第一栅金属层，所述扫描信号线的金属走线在所述衬底上的正投影的至少部分位于所述发光器件在所述的衬底上的正投影之内；所述扫描信号线的透明连接走线位于所述第一透明走线层，所述扫描信号线的透明连接走线与所述扫描信号线的金属走线通过过孔连接。
在一些实施例中，所述像素驱动电路的电路主体还包括第一发光控制晶体管和第二发光控制晶体管；所述至少一条信号线还包括发光控制信号线，一条所述发光控制信号线与一行所述第一像素单元中所有所述子像素的第一发光控制晶体管的控制极和第二发光控制晶体管的控制极电连接。
所述发光控制信号线的金属走线位于所述第一栅金属层，所述发光控制信号线的金属走线在所述衬底上的正投影的至少部分位于所述发光器件在所述的衬底上的正投影之内；所述发光控制信号线的透明连接走线位于所述第 一透明走线层，所述发光控制信号线的透明连接走线与所述发光控制信号线的金属走线通过过孔连接。
在一些实施例中，所述显示面板包括：第一源漏金属层和第一透明走线层，均位于所述衬底和所述发光器件之间，所述第一透明走线层位于所述第一源漏金属层背离所述衬底的一侧。
所述至少一条信号线还包括：初始化信号线，一条所述初始化信号线与一行所述第一像素单元中所述第二复位晶体的第一极电连接；所述初始化信号线的金属走线位于所述第一源漏金属层，所述初始化信号线的金属走线在所述衬底上的正投影的至少部分位于所述第一子像素的发光器件在所述衬底上的正投影之内；所述初始化信号线的透明连接走线位于所述第一透明走线层；所述初始化信号线的透明连接走线在所述衬底上的正投影，位于所述第二子像素的发光器件在所述衬底上的正投影之外，且位于所述第三子像素的发光器件在所述衬底上的正投影之外；所述初始化信号线的透明连接走线与所述初始化信号线的金属走线通过过孔连接。
在一些实施例中，所述显示面板包括：第二栅金属层、第二源漏金属层和第二透明走线层，位于所述衬底和所述发光器件之间，所述第二源漏金属层位于所述第二栅金属层背离所述衬底的一侧，所述第二透明走线层位于所述第二源漏金属层背离所述第二栅金属层的一侧。所述像素驱动电路的电路主体还包括：电容器，所述电容器的第一极板位于所述第二栅金属层。
所述至少一条信号线还包括第一电源信号线，所述第一电源信号线沿列方向延伸，一条所述第一电源信号线与一列所述第一像素单元中所述第二子像素的电容器的第一极板和所述第三子像素的电容器的第一极板电连接。
所述第一电源信号线的金属走线位于所述第二源漏金属层，所述第一电源信号线的金属走线在所述衬底上的正投影的至少部分位于所述第二子像素的发光器件和所述第三子像素的发光器件在所述的衬底上的正投影之内；所述第一电源信号线的透明连接走线位于所述第二透明走线层，所述第一电源信号线的透明连接走线与所述第一电源信号线的金属走线通过过孔连接。
在一些实施例中，所述至少一条信号线还包括第二电源信号线，所述第二电源信号线沿列方向延伸，一条所述第二电源信号线与一列所述第一像素单元中所述第一子像素的电容器的第一极板电连接。
所述第二电源信号线的金属走线位于所述第二源漏金属层，所述第二电源信号线的金属走线在所述衬底上的正投影至少部分位于所述第一子像素的发光器件在所述的衬底上的正投影之内；所述第二电源信号线的透明连接走 线位于所述第二透明走线层，所述第二电源信号线的透明连接走线与所述第二电源信号线的金属走线通过过孔连接。
在一些实施例中，所述显示面板还包括：多条数据线，所述多条数据线沿列方向延伸，所述多条数据线位于所述第一显示区中的部位在所述衬底上的正投影位于任一所述子像素的发光器件在所述衬底上的正投影之外，至少一条数据线位于所述第一显示区的部位位于所述第二透明走线层。
所述像素驱动电路的电路主体包括：写入晶体管；在一个所述第一像素单元中，所述第一子像素的写入晶体管的第一极、所述第二子像素的写入晶体管的第一极和所述第三子像素的写入晶体管的第一极分别连接于不同的所述数据线。
在一些实施例中，所述至少一条数据线位于所述第一显示区中的部位为透明走线段。
在同一列所述第一像素单元内，所述第一子像素中写入晶体管所电连接的数据线的透明走线段在所述衬底上的正投影，位于该第一子像素的电路主体在所述衬底上的正投影远离所述第二子像素的电路主体在所述衬底上的正投影的一侧；所述第二子像素的发光器件在所述衬底上的正投影和所述第三子像素的发光器件在所述衬底上的正投影，位于所述第二子像素的写入晶体管所电连接的数据线的透明走线段在衬底上的正投影和所述第三子像素的写入晶体管所电连接的数据线的透明走线段在衬底上的正投影之间。
在一些实施例中，所述像素驱动电路的电路主体还包括补偿晶体管和第三复位晶体管。
在一个所述第一像素单元内，所述第一子像素中的写入晶体管、补偿晶体管和第三复位晶体管依次远离所述第二子像素的电路主体；所述第二子像素中的写入晶体管、补偿晶体管和第三复位晶体管沿第一设定方向依次设置；所述第三子像素中的写入晶体管、补偿晶体管和第三复位晶体管沿所述第一设定方向的反方向依次设置。
在一些实施例中，所述发光器件包括阳极、发光层和阴极，所述阳极与所述像素驱动电路电连接，所述发光层位于所述阳极背离所述衬底的一侧，所述阴极位于所述发光层背离所述衬底的一侧。所述第二子像素中的第一复位晶体管和/或所述第三子像素中的第一复位晶体管在所述衬底上的正投影，位于所述第一子像素的阳极在所述衬底上的正投影之内。
在一些实施例中，所述第一子像素为蓝色子像素，所述第二子像素为绿色子像素，所述第三子像素为红色子像素。
在一些实施例中，所述显示面板包括：第一显示区和第二显示区。所述第一显示区设置有所述第一像素单元；所述第二显示区设置有多个第二像素单元，所述多个第二像素单元呈多行多列排布；所述第二像素单元包括多个子像素，所述第一显示区的子像素密度与所述第二显示区的子像素密度相等；所述第一显示区中子像素的发光器件的面积为所述第二显示区中相同颜色的子像素的发光器件的面积的0.4～0.6倍。
又一方面，提供一种显示装置。该显示装置包括：如上述任一实施例所述的显示面板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1A为根据一些实施例的显示装置的结构图；
图1B为根据一些实施例的显示装置的结构图；
图2A为根据一些实施例的显示装置的结构图；
图2B为根据一些实施例的显示面板的结构图；
图3A为根据一些实施例的显示面板的结构图；
图3B为根据一些实施例的显示面板的结构图；
图4A为根据一些实施例的像素驱动单元的结构图；
图4B为根据一些实施例的像素驱动电路的时序图；
图4C为根据一些实施例的像素驱动单元的结构图；
图4D为根据一些实施例的像素驱动单元的结构图；
图4E为根据一些实施例的像素驱动单元的结构图；
图4F为根据一些实施例的像素驱动单元的结构图；
图5A为根据一些实施例的显示面板的结构图；
图5B为根据一些实施例的显示面板的结构图；
图5C为根据一些实施例的显示面板的结构图；
图5D为根据一些实施例的显示面板的结构图；
图6A为根据一些实施例的显示面板的结构图；
图6B为根据一些实施例的显示面板的结构图；
图7A为根据一些实施例的显示面板的结构图；
图7B为根据一些实施例的显示面板的结构图；
图7C为根据一些实施例的显示面板的结构图；
图8A为根据一些实施例的显示面板的结构图；
图8B为根据一些实施例的显示面板的结构图；
图9A为根据一些实施例的显示面板的结构图；
图9B为根据一些实施例的显示面板的结构图；
图9C为根据一些实施例的显示面板的结构图；
图10A为根据一些实施例的显示面板的结构图；
图10B为根据一些实施例的显示面板的结构图；
图11A为根据一些实施例的显示面板的结构图；
图11B为根据一些实施例的显示面板的结构图；
图11C为根据一些实施例的显示面板的结构图；
图11D为根据一些实施例的显示面板的结构图；
图11E为根据一些实施例的显示面板的结构图；
图12A为根据一些实施例的显示面板的结构图；
图12B为根据一些实施例的显示面板的结构图；
图12C为根据一些实施例的显示面板的结构图；
图13A为根据一些实施例的显示面板的结构图；
图13B为根据一些实施例的显示面板的结构图；
图14为根据一些实施例的显示面板的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一些实施例(some embodiments)”、“示例(example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外， 所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”。
本文中“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
在描述一些实施例时，可能使用了‘“某结构”设置于阳极之下’或‘“某结构”位于阳极之下’或‘“某结构”藏于阳极之下’，则表示，某结构在衬底上的正投影位于阳极在衬底上的正投影之内。
在描述一些实施例时，可能使用了“某结构的面积”，则表示，某结构在衬底上的正投影的面积。
如本文所使用的那样，“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相 等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的一些实施例提供了一种显示装置。图1A和图1B为根据一些实施例的显示装置的结构图。请参阅图1A和图1B，显示装置100为具有图像(包括：静态图像或动态图像，其中，动态图像可以是视频)显示功能的产品。例如，显示装置100可以是：手表、显示器，电视机，广告牌，数码相框，具有显示功能的激光打印机，电话，手机，个人数字助理(personal digital assistant，简称PDA)，数码相机，便携式摄录机，取景器，导航仪，车辆，大面积墙壁，家电，信息查询设备(如电子政务、银行、医院、电力等部门的业务查询设备)，监视器等中的任一种。
其中，请参阅图2A，显示装置100中包括显示面板200和传感器300。
本公开的一些实施例提供了一种显示面板200，图2B为根据一些实施例的显示面板的结构图。请参阅图2B，显示面板200包括显示区AA和设置于显示区AA至少一侧的周边区BB。其中，显示区AA用于显示画面。在一些示例中，周边区BB可设置于显示区AA的一侧或多侧。在另一些示例中，周边区BB绕显示区AA设置一周。
其中，显示面板200可以为OLED(organic light-emitting diode，有机发光二极管)显示面板。OLED显示面板具有广视角、高对比度、快响应、低功耗、可折叠、柔性等优势。
请参阅图2B，显示面板200包括衬底210和多个第一像素单元220，多个第一像素单元220设置于衬底210的一侧，且呈多行多列排布。第一像素单元220中包括多个子像素230。子像素230是显示面板200进行画面显示的最小单元，每个子像素230可显示一种单一的颜色，例如红色、绿色或蓝色。 通过调节不同颜色子像素的亮度(灰阶)，进而颜色组合和叠加可以实现多种颜色的显示，从而实现显示面板200的全彩化显示。
在一些实施例中，请参阅图2B，显示区AA中包括第一显示区A1，多个第一像素单元220设置于第一显示区A1。请参阅图2A，显示面板200包括相背设置的背光侧201和显示侧202，其中，显示侧202用于显示画面。传感器300设置于显示面板200的背光侧201。且位于显示面板200的第一显示区A1。
其中，传感器300例如为图像传感器或红外传感器等。该传感器300被配置为接收来自显示面板200的显示侧202的光线，从而可以进行图像拍摄、距离感知、光强感知等操作。这些光线可透过第一显示区A1后照射到传感器300上，从而被传感器300感测到。
通过将传感器300设置于显示面板200的第一显示区A1，且位于所述显示面板的背光侧201，可以避免在显示屏中挖孔，并且提高屏占比，具有较佳的视觉体验。
图3A为根据一些实施例的显示面板在第一显示区A1的结构图。请参阅图3A，一个子像素230包括像素驱动电路231和发光器件232，发光器件232位于像素驱动电路231远离衬底210的一侧，且与像素驱动电路231电连接。其中，像素驱动电路231用于驱动发光器件232发光。
图3B为根据一些实施例的显示面板的结构图，图3B中示出了一个子像素的结构。请参阅图3B，发光器件232包括阳极AND1、发光层EL和阴极CTD1。其中，阳极AND1位于像素驱动电路231远离衬底210的一侧，且与像素驱动电路231电连接。发光层EL位于阳极AND1背离衬底210的一侧，阴极CTD1位于发光层EL背离衬底210的一侧。在一些示例中，发光器件232还包括电子传输层(election transporting layer，简称ETL)、电子注入层(election injection layer，简称EIL)、空穴传输层(hole transporting layer，简称HTL)以及空穴注入层(hole injection layer，简称HIL)中的一层或多层。
在一些示例中，阳极AND1在衬底210上的正投影、发光层EL在衬底210上的正投影和阴极CTD1在衬底210上的正投影至少部分重合。
请参阅图3A，一个第一像素单元220中的多个子像素230包括第一子像素230B、第二子像素230G和第三子像素230R。
在一个第一像素单元220中，第一子像素230B的发光器件232的面积大于第二子像素230G的发光器件232的面积，且大于第三子像素230R的发光器件232的面积。相应的，请参阅图3A，在一个第一像素单元220中，第一 子像素230B的阳极AND-B的面积大于第二子像素230G的阳极AND-G的面积，且大于第三子像素230R的阳极AND-R的面积。相应的，在一个第一像素单元220中，第一子像素230B的发光层EL的面积大于第二子像素230G的发光层EL的面积，且大于第三子像素230R的发光层EL的面积。相应的，在一个第一像素单元220中，第一子像素230B的阴极CTD1的面积大于第二子像素230G的阴极CTD1的面积，且大于第三子像素230R的阴极CTD1的面积。
阳极AND1呈块状，不同子像素230的阳极AND1彼此之间是相互分离的。发光层EL呈块状，不同子像素230的发光层EL彼此之间是相互分离的。
在一些示例中，显示面板200中的多个子像素230的阴极CTD1，彼此之间相互连接，且多个子像素230的阴极CTD1是整层的结构。在该些示例中，一个子像素230的阴极CTD1的面积等于发光层EL的面积或阳极AND1的面积。此外，在该些示例中，发光层EL和阳极AND1中面积较大者的面积为发光器件232的面积。示例性的，若阳极AND1在衬底210上的正投影的面积大于发光层EL在衬底210上的正投影的面积，那么发光器件232的面积则为阳极AND1的面积。示例性的，若发光层EL在衬底210上的正投影的面积大于阳极AND1在衬底210上的正投影的面积，那么发光器件232的面积则为发光层EL的面积。
在另一些示例种，阴极CTD1呈块状，显示面板200中的多个子像素230的阴极CTD1，彼此之间相互分离，此时，阴极CTD1、发光层EL和阳极AND1中面积最大者的面积为发光器件232的面积。示例性的，在一个子像素230的阴极CTD1、发光层EL和阳极AND1三者中，若阴极CTD1的面积最大，那么发光器件232的面积则为阴极CTD1的面积。若阳极AND1的面积最大，那么发光器件232的面积则为阳极AND1的面积。若发光层EL的面积最大，那么发光器件232的面积则为发光层EL的面积。
示例性的，在第一像素单元220内，第一子像素230B为蓝色子像素，第二子像素230G为绿色子像素，第三子像素230R为红色子像素。
发光层EL包括有效发光区域。在一些示例中，在一个第一像素单元220中，第一子像素230B的发光器件232的面积大于第二子像素230G的发光器件232的面积，且大于第三子像素230R的发光器件232的面积。对应的，第一子像素230B的有效发光区域的面积大于第二子像素230G的有效发光区域的面积，且大于第三子像素230R的有效发光区域的面积。其中，发光器件232中的发光层EL包括发光材料，蓝色子像素的发光材料的效率较低，通过 使得蓝色子像素的有效发光面积最大，可以减小因红、绿、蓝子像素发光效率不同而产生的色偏问题。
在一种实现方式中，通过缩小子像素230的发光器件232的面积，并且将像素驱动电路231藏于发光器件232之下，以此可以减小子像素230在显示面板200所占的面积，进而可以增大透光区的面积，提高第一显示区A1的透光率。其中，需要说明的是，发光器件232的面积指的是发光器件232在衬底210上的正投影所覆盖的面积。而像素驱动电路231藏于发光器件232之下指的是，像素驱动电路231位于发光器件232靠近衬底210的一侧，且像素驱动电路231在衬底210上的正投影位于发光器件232在衬底210上的正投影之内。
然而，由于第二子像素230G的发光器件232以及第三子像素230R的发光器件232的面积较小，因此，难以将第二子像素230G的像素驱动电路231-G藏于第二子像素230G的发光器件232之下，且难以将第三子像素230R的像素驱动电路231-R藏于第三子像素230R的发光器件232之下。如果像素驱动电路231暴露在发光器件232之外，会降低第一显示区A1的透光率，并加重衍射，不利于摄像。
基于此，本公开提供了一种像素驱动单元400，请参阅图4A，该像素驱动单元400包括多个像素驱动电路231。
在一些实施例中，本公开中的像素驱动电路的结构包括多种，可以根据实际需要选择设置。例如，像素驱动电路231的结构可以包括“6T1C”、“7T1C”、“6T2C”或“7T2C”等。此处，“T”表示为薄膜晶体管，位于“T”前面的数字表示为薄膜晶体管的数量；“C”表示为存储电容器C，位于“C”前面的数字表示为存储电容器C的数量。以下以7T1C模式的像素驱动电路为例做介绍。
请参阅图4A，一个像素驱动电路231包括驱动晶体管T3和第二复位晶体管T12，第二复位晶体管T12与复位信号端Rst、初始化信号端Vin和驱动晶体管T3的控制极电连接，第二复位晶体管T12被配置为：响应于在复位信号端Rst处接收的复位信号，将在初始化信号端Vin处接收的初始化信号传输至驱动晶体管T3的控制极，以对驱动晶体管T3的控制极进行复位。
示例性的，第二复位晶体管T12的控制极与复位信号端Rst电连接，第一极与初始化信号端Vin电连接，第二极与驱动晶体管T3的控制极电连接。
请参阅图4A，除第二复位晶体管T12和驱动晶体管T3外，像素驱动电路231还包括补偿晶体管T2、写入晶体管T4、第一发光控制晶体管T5、第 二发光控制晶体管T6、第三复位晶体管T7和电容器Cst。
其中，补偿晶体管T2的控制极与扫描信号端Gt电连接，补偿晶体管T2的第一极与驱动晶体管T3的第二极电连接，补偿晶体管T2的第二极与驱动晶体管T3的控制极电连接。
写入晶体管T4的控制极与扫描信号端Gt电连接，写入晶体管T4的第一极与数据信号端Dt电连接，写入晶体管T4的第二极与驱动晶体管T3的第一极电连接。
第一发光控制晶体管T5的控制极与发光控制信号端Em电连接，第一发光控制晶体管T5的第一极与第一类电源信号端Vdd电连接，第一发光控制晶体管T5的第二极与驱动晶体管T3的第一极电连接。
第二发光控制晶体管T6的控制极与发光控制信号端Em电连接，第二发光控制晶体管T6的第一极与驱动晶体管T3的第二极电连接，第二发光控制晶体管T6的第二极与发光器件232的阳极电连接。发光器件232的阴极与第二类电源信号端Vss电连接。其中，在第一类电源信号端Vdd处接收的第一类电源信号的电压大于在第二类电源信号端Vss处接收的第二类电源信号的电压。
第三复位晶体管T7的控制极与扫描信号端Gt电连接，第三复位晶体管T7的第一极与初始化信号端Vin电连接，第三复位晶体管T7的第二极与发光器件232的阳极电连接。
电容器Cst的第一极板与第一类电源信号端Vdd电连接，电容器Cst的第二极板与驱动晶体管T3的控制极电连接。
在一些示例中，第二复位晶体管T12、补偿晶体管T2、驱动晶体管T3、写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和第三复位晶体管T7均可以为P型晶体管也可以为N型晶体管。N型晶体管在栅极接收到高电压信号的情况下导通，而P型晶体管在栅极接收到低电压信号的情况下导通。需要说明的是，上述提到的“高电压信号”和“低电压信号”是通俗说法，一般来说，N型晶体管的导通条件为栅源电压差大于其阈值电压，即N型晶体管的栅极电压大于其源极电压与其阈值电压之和，N型晶体管的阈值电压为正值，则称使得N型晶体管导通的栅极电压信号为高电压信号，P型晶体管的导通条件为栅源电压差的绝对值大于其阈值电压，P型晶体管的阈值电压为负值，即P型晶体管的栅极电压小于其源极电压与其阈值电压之和，则称使得P型晶体管导通的栅极电压信号为低电压信号，“高电压信号”和“低电压信号”中的高低是相对于源极的电压来说的。
在一些示例中，请参阅图4A，第二复位晶体管T12、补偿晶体管T2、驱动晶体管T3、写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和第三复位晶体管T7均可以为P型晶体管均为P型晶体管，此时像素驱动电路231的时序图，如图4B所示。
以下基于像素驱动电路231中的晶体管均为P型晶体管对像素驱动电路231的驱动过程进行介绍。
像素驱动电路231的驱动过程为：一个帧周期包括复位阶段t1、数据刷新及补偿阶段t2和发光阶段t3。
在复位阶段t1，复位信号为低压，此时，第二复位晶体管T12导通，第二复位晶体管T12将初始化信号传输至驱动晶体管T3的控制极，以此对驱动晶体管T3的控制极进行复位，同时使得驱动晶体管T3导通。而补偿晶体管T2、写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6以及第三复位晶体管T7均处于断开的状态，且发光器件232不发光。
在数据刷新及补偿阶段t2，在复位信号端Rst处接收的复位信号为高压，第二复位晶体管T12断开。而在扫描信号端Gt处接收的扫描信号为低压，因此，第三复位晶体管T7在扫描信号的控制下导通，进而将在初始化信号端Vin处接收的初始化信号写入到发光器件232的阳极，以对发光器件232的阳极进行复位。
同时，在扫描信号的控制下，写入晶体管T4和补偿晶体管T2导通，同时驱动晶体管T3维持复位阶段t1的导通状态，因此在数据信号端Dt处接收的数据信号可以依次通过写入晶体管T4、驱动晶体管T3和补偿晶体管T2传输至驱动晶体管T3的控制极，使得驱动晶体管T3的控制极的电压改变，直至驱动晶体管T3的控制极的电压达到驱动晶体管T3的阈值电压与数据信号的电压之和，使得驱动晶体管T3断开。
在数据刷新及补偿阶段t2，可以将驱动晶体管T3的阈值电压写入到驱动晶体管T3的控制极，以此补偿驱动晶体管T3的阈值电压漂移，进而减少对发光器件232的发光强度所产生的影响。在该阶段，第一发光控制晶体管T5和第二发光控制晶体管T6在发光控制信号的控制下处于断开的状态。
在发光阶段t3，第二复位晶体管T12、补偿晶体管T2、写入晶体管T4和第三复位晶体管T7断开。电容器Cst固定驱动晶体管T3的控制极的电压，使驱动晶体管T3的控制极维持在数据刷新及补偿阶段t2的电压。此时，发光控制信号为低压，第一发光控制晶体管T5和第二发光控制晶体管T6在发光控制信号的控制下导通，进而使得在第一类电源信号端Vdd处接收的第一类 电源信号写入到驱动晶体管T3的第一极，从而使得驱动晶体管T3导通，以此在第一类电源信号端与发光器件232之间形成通路，使得发光器件232发光。
本公开的一些实施例所提供的像素驱动单元400中，请参阅图4A，至少两个像素驱动电路231的第二复位晶体管T12为同一晶体管，进而可以减小像素驱动单元400的面积，有利于将像素驱动单元400中的素驱动电路231隐藏在发光器件232之下。
在一些示例中，一个像素驱动单元400中的所有像素驱动电路231的第二复位晶体管T12为同一晶体管。
在一些示例中，在一个像素驱动单元400中，多个像素驱动电路231包括第一像素驱动电路231B、第二像素驱动电路231G和第三像素驱动电路231R。其中，第一像素驱动电路231B的第二复位晶体管T12、第二像素驱动电路231G的第二复位晶体管T12和第三像素驱动电路231R的第二复位晶体管T12为同一晶体管。
其中，第一像素驱动电路231B、第二像素驱动电路231G和第三像素驱动电路231R共用第二复位晶体管T12，一个第二复位晶体管T12可以同时为像素驱动电路231B、231G和231R中的驱动晶体管T3的控制极进行复位。
通过共用第二复位晶体管T12，可以减小一个像素驱动单元400中晶体管的数量，因此，可以减小像素驱动单元400的面积，有利于将像素驱动单元400中的素驱动电路231隐藏在发光器件232之下。
在一些示例中，可参阅图3A，第一子像素230B包括第一像素驱动电路231B和阳极AND-B，此时，第一像素驱动电路231B和阳极AND-B电连接。第二子像素230G包括第二像素驱动电路231G和阳极AND-G，此时，第二像素驱动电路231G和阳极AND-G电连接。第三子像素230R包括第三像素驱动电路231R和阳极AND-R，此时，第三像素驱动电路231R和阳极AND-R电连接。
在一些实施例中，请参阅图4A，像素驱动电路231还包括第一复位晶体管T11；在同一个像素驱动电路231中，第一复位晶体管T11串联于第二复位晶体管T12与驱动晶体管T3的控制极之间。
其中，第一复位晶体管T11的控制极与复位信号端Rst电连接，第一复位晶体管T11与第二复位晶体管T12共同为驱动晶体管T3的控制极进行复位，以此可以起到防漏电的效果。
在一些示例中，请参阅图4C～图4F，在一个像素驱动单元400中，至少 两个像素驱动电路231的第一复位晶体管T11为同一晶体管。
基于以上多个像素驱动电路231包括第一像素驱动电路231B、第二像素驱动电路231G和第三像素驱动电路231R的实施例。在一些实施例中，请参阅图4C～图4F，第一像素驱动电路231B的第一复位晶体管T11-B、第二像素驱动电路231G的第一复位晶体管T11-G和第三像素驱动电路231R的第一复位晶体管T11-R中的至少两个为同一晶体管。
在一些示例中，请参阅图4C，第一像素驱动电路231B的第一复位晶体管T11-B与第二像素驱动电路231G的第一复位晶体管T11-G，为同一晶体管。
在一些示例中，请参阅图4D，第一像素驱动电路231B的第一复位晶体管T11-B与第三像素驱动电路231R的第一复位晶体管T11-R，为同一晶体管。
在一些示例中，请参阅图4E，第二像素驱动电路231G的第一复位晶体管T11-G与第三像素驱动电路231R的第一复位晶体管T11-R，为同一晶体管。
在一些示例中，请参阅图4F，一个像素驱动单元400中，多个像素驱动电路231(即全部的像素驱动电路231)的第一复位晶体管T11为同一晶体管。基于以上多个像素驱动电路231包括第一像素驱动电路231B、第二像素驱动电路231G和第三像素驱动电路231R的实施例，此时，第一像素驱动电路231B的第一复位晶体管T11-B、第二像素驱动电路231G的第一复位晶体管T11-G和第三像素驱动电路231R的第一复位晶体管T11-R为同一晶体管。
通过使得一个像素驱动单元400中多个像素驱动电路231中的至少两个共用第一复位晶体管T11，可以减小一个像素驱动单元400中晶体管的数量，进而减小像素驱动单元400中像素驱动电路231的面积，有利于将像素驱动单元400中的素驱动电路231隐藏在发光器件232之下。
除此之外，在其他的一些实施例中，请参阅图4A，第一像素驱动电路231B的第一复位晶体管T11-B、第二像素驱动电路231G的第一复位晶体管T11-G和第三像素驱动电路231R的第一复位晶体管T11-R均为不同的晶体管。
通过为每个像素驱动电路231设置一第一复位晶体管T11，在不同的像素驱动电路231中，通过不同的第一复位晶体管T11对驱动晶体管T3的控制极进行复位，进而可以保证对驱动晶体管T3的控制极的复位效果。
本公开的一些实施例所提供的显示装置100包括：以上任一实施例所提供的像素驱动单元400。因此本公开的一些实施例所提供的显示装置100具有以上任一实施例所提供的像素驱动单元400的全部有益效果，在此不进行赘述。
本公开的一些实施例还提供了一种显示面板200，请参阅图5A，在显示 面板200中，第二子像素230G中的第一复位晶体管T11-G和/或第三子像素230R中的第一复位晶体管T11-R在衬底210上的正投影，位于第一子像素230B的发光器件232在衬底210上的正投影之内。
其中需要说明的是，在发光器件232的面积为阳极AND1的面积的情况下，发光器件232在衬底210上的正投影则与阳极AND1在衬底210上的正投影重合。在发光器件232的面积为发光层EL的面积的情况下，发光器件232在衬底210上的正投影则与发光层EL在衬底210上的正投影重合。在发光器件232的面积为阴极CTD1的面积的情况下，发光器件232在衬底210上的正投影则与阴极CTD1在衬底210上的正投影重合。
在一些示例中，在一个第一像素单元220中，第一子像素230B的发光器件232的面积最大，而第二子像素230G的发光器件232的面积和第三子像素230R的发光器件232的面积均相对较小，将第二子像素230G中的第一复位晶体管T11-G和/或第三子像素230R中的第一复位晶体管T11-R藏于第一子像素230B的发光器件232之下，不仅可以对将第二子像素230G中的第一复位晶体管T11-G和/或第三子像素230R中的第一复位晶体管T11-R进行遮挡。并且由于第一子像素230B的发光器件232的面积较大，进而不会造成第一子像素230B的发光器件232之下的像素驱动电路231的结构过于紧凑，合理利用第一子像素230B的发光器件232之下的空间。
在一些示例中，可以仅使得第二子像素230G中的第一复位晶体管T11-G在衬底210上的正投影位于第一子像素230B的发光器件232在衬底210上的正投影之内。其中，在一个第一像素单元220内，第二子像素230G的发光器件232的面积较小，通过将第二子像素230G中的第一复位晶体管T11-G设置于第一子像素230B的发光器件232之下，以此可以减小位于第二子像素230G的发光器件232之下的像素驱动电路231中晶体管的数量，进而可以减小位于第二子像素230G的发光器件232之下的像素驱动电路231的面积，有利于第二子像素230G的发光器件232对位于其下的像素驱动电路231进行遮挡。
在另一些示例中，可以仅使得第三子像素230R中的第一复位晶体管T11-R在衬底210上的正投影位于第一子像素230B的发光器件232在衬底210上的正投影之内。通过将第三子像素230R中的第一复位晶体管T11-R设置于第一子像素230B的发光器件232之下，以此可以减小位于第三子像素230R的发光器件232之下的像素驱动电路231中晶体管的数量，进而可以减小位于第三子像素230R的发光器件232之下的像素驱动电路231的面积，有利于第三子像素230R的发光器件232对位于其下的像素驱动电路231进行遮挡。
在另一些实施例中，请参阅图5A，第一子像素230B的第一复位晶体管T11-B、第二子像素230G的第一复位晶体管T11-G和第三子像素230R的第一复位晶体管T11-R，均位于第一子像素230B的发光器件232在衬底210的正投影之内。
其中，第二子像素230G的第一复位晶体管T11-G和第三子像素230R的第一复位晶体管T11-R均设置在第一子像素230B的发光器件232之下，既能够减小第二子像素230G的发光器件232之下的像素驱动电路231的面积，还能够减小第三子像素230R的发光器件232之下的像素驱动电路231的面积，有利于对第二子像素230G中的像素驱动电路231和第三子像素230R中的像素驱动电路231进行遮挡，降低衍射现象。且第一子像素230B的第一复位晶体管T11-B位于设置在第一子像素230B的发光器件232之下，避免第一复位晶体管T11-B占用其他空间，以此提高了透光率。
在一些实施例中，请参阅图4C～图4F，第一子像素230B的第一复位晶体管T11-B、第二子像素230G的第一复位晶体管T11-G和第三子像素230R的第一复位晶体管T11-R中的至少两个，为同一晶体管。
其中，一个第一像素单元220内，至少两个子像素230的第一复位晶体管T11为同一晶体管，可以减小第一像素单元220中第一复位晶体管T11的数量。在将第一子像素230B的第一复位晶体管T11-B、第二子像素230G的第一复位晶体管T11-G以及第三子像素230R的第一复位晶体管T11-R均设置于第一子像素230B的发光器件232之下时，通过减少第一复位晶体管T11的数量，可以减小第一子像素230B的发光器件232之下的像素驱动电路231的面积，进而可以减小第一子像素230B的发光器件232的面积，提高第一显示区A1的透光率。
在一些示例中，阳极AND1的材料包括透明导电氧化物材料和金属材料，其中，透明导电氧化物材料例如为ITO、IZO，金属材料例如为Au、Ag、Ni、Pt。示例性的，阳极层AND可以包括一层透明导电氧化物、一层金属和一层透明导电氧化物这样的叠层复合结构，该种结构可以记作透明导电氧化物/金属/透明导电氧化物，例如，一种阳极层AND的结构为：ITO/Ag/ITO。其中，阳极AND1的透光性较差或不透光。
在一些实施例中，请参阅图5A，第二子像素230G中的第一复位晶体管T11-G和/或第三子像素230R中的第一复位晶体管T11-R在衬底210上的正投影，位于第一子像素230B的阳极AND-B在衬底210上的正投影之内。其中，需要说明的是，此时，发光器件232与阳极AND1的面积可以相等，也 可以不等，其还可以理解为发光器件232在衬底210上的正投影可以与阳极AND1在衬底210上的正投影完全重合或部分重合。
其中，阳极AND1透光性较差或不透光，进而阳极AND1可以对位于阳极AND1之下的像素驱动电路231和信号线等进行遮挡，进而减少像素驱动电路231和信号线外露，从而降低传感器300透过第一显示区A1拍照时的衍射，同时增大第一显示区A1的透光率。
在一些示例中，第一子像素230B中的第一复位晶体管T11-B、第二子像素230G中的第一复位晶体管T11-G、第三子像素230R中的第一复位晶体管T11-R在衬底210上的正投影，均位于第一子像素230B的阳极AND-B在衬底210上的正投影之内。
在一些实施例中，请参阅图5A和图5B，显示面板200还包括复位信号线RST和初始化信号线VIN。
请参阅图5A，像素驱动电路231还包括第二复位晶体管T12，第二复位晶体管T12与任一第一复位晶体管T11串联。结合图5B所示，各个第一复位晶体管T11的控制极和第二复位晶体管T12的控制极均与复位信号线RST电连接；第二复位晶体管T12的第一极与初始化信号线VIN电连接，第二复位晶体管T12的第二极与各个第一复位晶体管T11的第一极电连接。像素驱动电路231还包括：驱动晶体管T3，各个像素驱动电路231的驱动晶体管T3的控制极与各个第一复位晶体管T11的第二极电连接。
复位信号线RST用于传输复位信号，初始化信号线VIN用于传输初始化信号。在第一复位晶体管T11和第二复位晶体管T12均为P型晶体管的情况下，当复位信号为低压信号时，第一复位晶体管T11和第二复位晶体管T12导通，第一复位晶体管T11和第二复位晶体管T12可以将初始化信号传输至驱动晶体管T3的控制极，进而对驱动晶体管T3的控制极进行复位。其中，通过两个晶体管对驱动晶体管T3的控制极进行复位，可以起到防漏电的效果。
在一些实施例中，请参阅图5A，第一子像素230B的第二复位晶体管T12、第二子像素230G的第二复位晶体管T12和第三子像素230R的第二复位晶体管T12，为同一晶体管；第二复位晶体管T12在衬底210上的正投影，位于第一子像素230B的发光器件232在衬底210上的正投影之内。
其中，如图5A所示，第一子像素230B的第二复位晶体管T12、第二子像素230G的第二复位晶体管T12和第三子像素230R的第二复位晶体管T12，为同一晶体管，可以减少第一子像素230B的发光器件232之下的晶体管的数量，以此减小第一子像素230B的发光器件232之下像素驱动电路231的面积， 有利于第一子像素230B的发光器件232将位于其下的像素驱动电路231进行遮挡，避免像素驱动电路231外露，以此减少衍射现象。
同时，在第一子像素230B的发光器件232之下的晶体管的数量较少的情况下，可以减小第一子像素230B的发光器件232的面积，进而可以增大透光率。
在另一些示例中，请参阅图5A，第二复位晶体管T12在衬底210上的正投影，位于第一子像素230B的阳极AND-B在衬底210上的正投影之内。其中，第一子像素230B的阳极AND-B不透光，其对第二复位晶体管T12的遮挡效果较好，从而降低传感器300透过第一显示区A1拍照时的衍射现象。
在一些实施例中，请参阅图5C，第二子像素230G的发光器件232和第三子像素230R的发光器件232沿列方向Y间隔设置。箭头Y所指的方向为列方向Y。第二子像素230G的发光器件232和第三子像素230R的发光器件232沿列方向Y依次设置，因此一列第一像素单元220中的第二子像素230G的发光器件232和第三子像素230R的发光器件232可以排成一列。一列第一像素单元220中的第一子像素230B的发光器件232可以排成一列。请参阅图5B和图5C，第一子像素230B的发光器件232，位于第二子像素230G的发光器件232和第三子像素230R的发光器件232所在列的相邻列；且第一子像素230B的发光器件232，跨过第二子像素230G的发光器件232和第三子像素230R的发光器件232之间的间隙区域。
其中，需要说明的是，请参阅图5B和图5C，箭头X所指的方向为行方向X，在一些示例中，行方向X与列方向Y垂直。一行第一像素单元220中的第三子像素230R的发光器件232可以排成一行。一行第一像素单元220中的第二子像素230G的发光器件232可以排成一行。一行第一像素单元220中的第一子像素230B的发光器件232可以排成一行。而第二子像素230G的发光器件232和第三子像素230R的发光器件232之间的间隙区域指的是，相邻的一行第三子像素230R的发光器件232与一行第二子像素230G的发光器件232之间的间隙区域。
第一子像素230B的发光器件232，跨过第二子像素230G的发光器件232和第三子像素230R的发光器件232之间的间隙区域，还可以理解为，第一子像素230B的发光器件232在行方向X上的投影与第二子像素230G的发光器件232、第三子像素230R的发光器件232均有重叠。
以上一些实施例所公开的子像素230的排列方式可以被称为“REAL像素排列”，通过使用REAL像素排列，在显示面板200的PPI(pixels per inch， 每英寸像素数)较低(例如低于400)的情况下，可以降低颗粒感，提高显示效果。上述显示面板200可以应用于手表设备。
在一些实施例中，请参阅图5A，像素驱动电路231还包括电路主体2311。示例性的，每个子像素230的电路主体2311包括补偿晶体管T2、驱动晶体管T3、写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6、第三复位晶体管T7和电容器Cst。
第一子像素230B的电路主体2311-B在衬底210上的正投影位于第一子像素230B的发光器件232在衬底210上的正投影之内，第二子像素230G的电路主体2311-G在衬底210上的正投影位于第二子像素230G的发光器件232在衬底210上的正投影之内，第三子像素230R的电路主体2311-R在衬底210上的正投影位于第三子像素230R的发光器件232在衬底210上的正投影之内。
在一个子像素230内，通过发光器件232对其所电连接的电路主体2311进行遮挡，以此避免电路主体2311暴露在发光器件232之外，降低衍射现象。同时，还可以提高第一显示区A1的透光率。
在另一些示例中，请参阅图5A，各个子像素230的电路主体2311在衬底210上的正投影位于该子像素230B的阳极AND1在衬底210上的正投影之内。示例性的，第一子像素230B的电路主体2311-B在衬底210上的正投影位于第一子像素230B的阳极AND-B在衬底210上的正投影之内，第二子像素230G的电路主体2311-G在衬底210上的正投影位于第二子像素230G的阳极AND-G在衬底210上的正投影之内，第三子像素230R的电路主体2311-R在衬底210上的正投影位于第三子像素230R的阳极AND-R在衬底210上的正投影之内。其中，子像素230B的阳极AND1不透光，其对各个电路主体2311的遮挡效果较好，从而降低传感器300透过第一显示区A1拍照时的衍射现象。
在一些示例中，请参阅图5A，第二子像素230G指向第三子像素230的方向为第二指定方向C2，箭头C2所指的方向为第二指定方向C2，第二指定方向C2与列方向Y平行。
在一些实施例中，请参阅图5D，在一行第一像素单元220中，第二复位晶体管T12和多个第一复位晶体管T11位于第三子像素230R的电路主体2311-R远离第二子像素230G的发光器件232所在行的一侧，此时，第三子像素230R的电路主体2311-R指向第二复位晶体管T12和多个第一复位晶体管T11的方向为第二指定方向C2。
在一些实施例中，请参阅图5D，第二复位晶体管T12、第三子像素230R的第一复位晶体管T11-R和第二子像素230G的第一复位晶体管T11-G，位于第一子像素230B的第一复位晶体管T11-B靠近第三子像素230R的电路主体2311-R的一侧，且依次远离第三子像素230R的电路主体2311-R。
在一些示例中，在一个第一像素单元220中，第三子像素230R指向第一子像素230B的方向为第一指定方向C1，箭头C1所指的方向为第一指定方向C1，且第一指定方向C1与行方向X平行。
第二复位晶体管T12、第三子像素230R的第一复位晶体管T11-R、第二子像素230G的第一复位晶体管T11-G和第一子像素230B的第一复位晶体管T11-B沿第一指定方向C1依次设置，以此能够方便第三子像素230R的第一复位晶体管T11-R与第三子像素230R的驱动晶体管T3电连接，同时方便第二子像素230G的第一复位晶体管T11-G与第二子像素230G的驱动晶体管T3电连接。
在一些实施例中，请参阅图5B和图5C，复位信号线RST沿行方向X延伸，一条复位信号线RST与一行第一像素单元220中第二复位晶体管T12的控制极以及各个第一复位晶体管T11的控制极电连接。其中，图5B和图5C中未示出第二复位晶体管T12，可参阅图5A。
其中，复位信号线RST的图案可以为一直线图形，也可以为一近似直线图形，上述复位信号线RST“沿行方向X延伸”是指复位信号线RST的主体图案呈沿某行方向X延伸的趋势。
一行第一像素单元220中的第二复位晶体管T12、第一子像素230B的第一复位晶体管T11-B、第二子像素230G的第一复位晶体管T11-G以及第三子像素230R的第一复位晶体管T11-R接收同一复位信号。因此，一行第一像素单元220中的各个子像素230中的驱动晶体管T3的控制极同时进行复位。
请参阅图5B，初始化信号线VIN沿行方向X延伸，一条初始化信号线VIN与一行第一像素单元220中第二复位晶体T12的第一极电连接。其中，图5B中未示出第二复位晶体T12，可参阅图5A。
其中，初始化信号线VIN的图案可以为一直线图形，也可以为一近似直线图形，上述初始化信号线VIN“沿行方向X延伸”是指初始化信号线VIN的主体图案呈沿某行方向X延伸的趋势。
初始化信号线VIN用于传输初始化信号，初始化信号通过第二复位晶体T12传输至各个第一复位晶体管T11，进而传输至各个子像素230的驱动晶体管T3的控制极，对驱动晶体管T3的控制极进行复位。
请参阅图5A，第二复位晶体管T12以及各个第一复位晶体管T11在衬底210上的正投影，位于与该第二复位晶体管T12所电连接的初始化信号线VIN在衬底210上的正投影和第三子像素230R的电路主体2311-R在衬底210上的正投影之间；复位信号线RST在衬底210上的正投影，位于该条初始化信号线VIN在衬底210上的正投影和该第三子像素230R的电路主体2311-G在衬底210上的正投影之间。
为了方便叙述，将第二复位晶体管T12以及各个第一复位晶体管T11定义为第一类复位晶体管。
请参阅图5A，第三子像素230R的电路主体2311-R、第一类复位晶体管和初始化信号线VIN沿第二指定方向C2依次设置。
在一行第一像素单元220中，第二复位晶体管T12以及各个第一复位晶体管T11的控制极位于复位信号线RST上。
以下对结合显示面板200中的多个膜层对第一复位晶体管T11的控制极的位置进行介绍。
在一些示例中，请参阅图5D，显示面板200包括设置于衬底210一侧的有源膜层240和第一栅金属层Gate1，有源膜层240和第一栅金属层Gate1均位于衬底210和发光器件232之间，第一栅金属层Gate1位于有源膜层240远离衬底210的一侧。在一些示例中，有源膜层240和第一栅金属层Gate1之间设置有第一栅绝缘层。
有源膜层240中包括像素驱动电路231中各个晶体管的有源层，其中，晶体管的有源层包括第一极区、第二极区以及连接第一极区和第二极区的沟道区。
示例性的，请参阅图6A，有源膜层240中包括第二复位晶体管T12的有源层T12-P以及各个第一复位晶体管T11的有源层T11-P。
请参阅图6A，第二复位晶体管T12的有源层T12-P沿行方向X延伸，各个第一复位晶体管T11的有源层T11-P均沿列方向Y延伸。第二复位晶体管T12的有源层T12-P远离第三子像素230R的电路主体2311-R的一端与各个第一复位晶体管T11的有源层T11-P远离第一子像素230B的电路主体2311-B的一端连接。
其中，第三子像素230R的第一复位晶体管T11-R的有源层T11-RP、第二子像素230G的第一复位晶体管T11-G的有源层T11-GP和第一子像素230B的第一复位晶体管T11-B的有源层T11-BP沿第一指定方向C1依次设置。
请参阅图6B，第一栅金属层Gate1中包括复位信号线RST。复位信号线 RST位于有源膜层240远离衬底210的一侧。其中，请参阅图5D，复位信号线RST与第二复位晶体管T12的有源层T12-P以及各个第一复位晶体管T11的有源层T11-P交叠的部分复用为第二复位晶体管T12的控制极以及各个第一复位晶体管T11的控制极。
在一些实施例中，请参阅图2B，衬底210包括第一显示区A1，多个第一像素单元220位于第一显示区A1内；显示面板200还包括：多条信号线，位于衬底210和发光器件232之间。其中需要说明的是，衬底210中的第一显示区A1与显示面板200中的第一显示区A1为同一区域。其中，图2B中未示出发光器件232，可参阅图3A、图5A和图5B等。
请参阅图5B，至少一条信号线位于第一显示区A1内的部位包括彼此电连接的金属走线250和透明连接走线260。至少部分金属走线250在衬底210上的正投投影，位于发光器件232在衬底210上的正投影之内。示例性的，请参阅图5C，显示面板200中的多条信号线包括复位信号线RST、扫描信号线GT、发光控制信号线EM、初始化信号线VIN、第一电源信号线VDD1和第二电源信号线VDD2。
在一些示例中，全部金属走线250在衬底210上的正投投影，位于发光器件232在衬底210上的正投影之内。
在另一些示例中，请参阅图5B，部分金属走线250在衬底210上的正投投影，位于发光器件232在衬底210上的正投影之内，其余部分全部金属走线250在衬底210上的正投影，位于发光器件232在衬底210上的正投影之外。
示例性的，请参阅图5A和图5B，金属走线250的端部设置有金属连接部2501。请参阅图5B，透明连接走线260的端部设置有透明连接部2601，金属连接部2501在衬底210上的正投影与透明连接部2601在衬底210上的正投影至少部分重合。其中，在一些示例中，金属连接部2501在衬底210上的正投影至少部分位于发光器件232在衬底210上的正投影之内。在另一些示例中，金属连接部2501在衬底210上的正投影全部位于发光器件232在衬底210上的正投影之外。
一条信号线中的金属走线250可以通过透明连接走线260连接，至少部分透明连接走线260暴露在发光器件232的外部，而透明连接走线260为透明的走线，可透光。因此通过透明连接走线260连接金属走线250，可以提高第一显示区A1的透光率。
在另一些示例中，请参阅图5B，至少部分金属走线250在衬底210上的 正投投影，位于子像素230的阳极AND1在衬底210上的正投影之内。
以下对复位信号线RST、扫描信号线GT、发光控制信号线EM、初始化信号线VIN、第一电源信号线VDD1和第二电源信号线VDD2依次进行介绍。
在一些实施例中，请参阅图7A，显示面板200包括：第一透明走线层271，第一透明走线层271位于衬底210和发光器件232之间，第一透明走线层271位于第一栅金属层Gate1背离衬底210的一侧。
在一些示例中，第一栅金属层Gate1的材料为金属，例如Al、Ag、Cu、Cr等。第一透明走线层271的材料为透明导电氧化物材料，例如为ITO、IZO等。
请参阅图7B，至少一条信号线包括复位信号线RST。复位信号线RST包括金属走线251和透明连接走线261。其中，复位信号线RST的金属走线251位于第一栅金属层Gate1，复位信号线RST的金属走线251在衬底210上的正投影的至少部分位于第一子像素230B的发光器件232在衬底210上的正投影之内。其中，图7B中未示出第一子像素230B的发光器件232，可参阅图5B。
一条复位信号线RST包括多段金属走线251，一段金属走线251的至少部分位于第一子像素230B的发光器件232之下。在一些示例中，一段金属走线251的全部均位于一个第一子像素230B的发光器件232之下。在另一些示例中，一段金属走线251的部分位于一个第一子像素230B的发光器件232之下。
请参阅图6B，复位信号线RST中的金属走线251包括主体走线段2511和连接走线段2512，主体走线段2511沿行方向X延伸，且主体走线段2511在衬底210与各个第一复位晶体管T11的有源层T11-P有交叠，其中，第一复位晶体管T11的控制极位于主体走线段2511上。而连接走线段2512沿列方向Y延伸，与第二复位晶体管T12的有源层T12-P有交叠。连接走线段2512中与第二复位晶体管T12的有源层T12-P重叠的部分为第二复位晶体管T12的控制极，即第二复位晶体管T12的控制极位于连接走线段2512上。其中，图6B中未示出第二复位晶体管T12的有源层T12-P，可参阅图5D和图6A。
请参阅图7B，复位信号线RST的透明连接走线261位于第一透明走线层271，复位信号线RST的透明连接走线261与复位信号线RST的金属走线251通过过孔连接。
其中，复位信号线RST的透明连接走线261在衬底210上的正投影，位于第二子像素230G的发光器件232在衬底210上的正投影之外，且位于第三 子像素230R的发光器件232在衬底210上的正投影之外。因此，复位信号线RST的透明连接走线261不会占用第二子像素230G的发光器件232和第三子像素230R的发光器件232之下的空间，进而增大了第二子像素230G的发光器件232和第三子像素230R的发光器件232之下的像素驱动电路231的面积，避免了第二子像素230G的发光器件232和第三子像素230R的发光器件232之下的像素驱动电路231的结构过于紧凑，而发生耦合。其中，图7B中未示出第三子像素230R的发光器件232，可以参阅5A和图5B。
在另一些示例中，请参阅图7B，复位信号线RST的金属走线251在衬底210上的正投影的至少部分位于第一子像素230B的阳极AND-B在衬底210上的正投影之内。复位信号线RST的透明连接走线261在衬底210上的正投影，位于第二子像素230G的阳极AND-G在衬底210上的正投影之外，且位于第三子像素230R的阳极AND-R在衬底210上的正投影之外。其中，图7B中未示出各个子像素230的阳极AND1，可参阅图5B。
在一些实施例中，请参阅图5D，像素驱动电路231的电路主体2311包括写入晶体管T4、补偿晶体管T2和第三复位晶体管T7。
至少一条信号线还包括扫描信号线GT，一条扫描信号线GT与一行第一像素单元220中所有子像素230的写入晶体管T4的控制极、补偿晶体管T2的控制极和第三复位晶体管T7的控制极电连接。
扫描信号线GT用于传输扫描信号，一行第一像素单元220中所有子像素230接收同一扫描信号。一行第一像素单元220中写入晶体管T4、补偿晶体管T2和第三复位晶体管T7同时开启。
请参阅图7B，扫描信号线GT的金属走线252位于第一栅金属层Gate1，扫描信号线GT的金属走线252在衬底210上的正投影的至少部分位于发光器件232在的衬底210上的正投影之内。扫描信号线GT的透明连接走线262位于第一透明走线层271，扫描信号线GT的透明连接走线262与扫描信号线GT的金属走线252通过过孔连接。
请参阅图7B，扫描信号线GT包括多段金属走线252，一段金属走线252在衬底210上的正投影至少部分位于一个发光器件232在的衬底210上的正投影之内。在一些示例中，每段金属走线252的全部均设置于发光器件232之下。在另一些示例中，每段金属走线252的部分设置于发光器件232之下。
在其他的一些示例中，请参阅图7B，扫描信号线GT的金属走线252在衬底210上的正投影的至少部分位于子像素230的阳极AND1在的衬底210上的正投影之内。
在一些示例中，请参阅图5D，扫描信号线GT中一段金属走线252与一个子像素230中的写入晶体管T4的控制极、补偿晶体管T2的控制极和第三复位晶体管T7的控制极电连接。
在一些示例中，请参阅图6A，有源膜层240包括写入晶体管T4的有源层T4-P、补偿晶体管T2的有源层T2-P和第三复位晶体管T7的有源层T7-P。
请参阅图5D，一段金属走线252与写入晶体管T4的有源层T4-P的交叠部分复用为写入晶体管T4的控制极。一段金属走线252与补偿晶体管T2的有源层T2-P的交叠部分复用为补偿晶体管T2的控制极。一段金属走线252与第三复位晶体管T7的有源层T7-P的交叠部分复用为第三复位晶体管T7的控制极。即一个子像素230中的写入晶体管T4的控制极、补偿晶体管T2的控制极和第三复位晶体管T7的控制极位于一段金属走线252上。
在一些示例中，请参阅图4A和图5D，每个子像素230的补偿晶体管T2包括第一补偿晶体管T21和第二补偿晶体管T22。其中，第一补偿晶体管T21和第二补偿晶体管T22串联。
其中，第一补偿晶体管T21的控制极与扫描信号线GT电连接，第一补偿晶体管T21的第一极与驱动晶体管T3的第二极以及第二发光控制晶体管T6的第一极电连接，第一补偿晶体管T21的第二极与第二补偿晶体管T22的第一极电连接。
第二补偿晶体管T22的控制极与扫描信号线GT电连接，第二补偿晶体管T22的第二极与第一复位晶体管T11的第二极和驱动晶体管T3的控制极电连接。
通过将补偿晶体管T2设置为串联的第一补偿晶体管T21和第二补偿晶体管T22，可以起到防漏电的效果。
基于补偿晶体管T2包括第一补偿晶体管T21和第二补偿晶体管T22示例，请参阅图6B，扫描信号线GT的金属走线252包括主体走线段2521和连接走线段2522。主体走线段2521沿着行方向X延伸，连接走线段2522沿着列方向延伸，且连接走线段2522的一端与主体走线段2521连接。其中，连接走线段2522与补偿晶体管T2的有源层T2-P的交叠部分复用为第二补偿晶体管T22的控制极。主体走线段2521与写入晶体管T4的有源层T4-P、补偿晶体管T2的有源层T2-P以及第三复位晶体管T7的有源层T7-P的交叠复位分别复用为写入晶体管T4的控制极、第一补偿晶体管T21的控制极以及第三复位晶体管T7的控制极。其中，在图6B中未示出各个晶体管的有源层，可参阅图5D和图6A。
在一些示例中，请参阅图7C，一条扫描信号线GT中包括多段金属走线252和多段透明连接走线262。其中，多段金属走线252中包括第一段金属走线252A、第二段金属走线252B和第三段金属走线252C。其中，图7C中未示出金属走线252和多段透明连接走线262，可参阅图7B。
其中，第一段金属走线252A在衬底210上的正投影至少部分位于第一子像素230B的发光器件232在衬底210上的正投影之内。
第二段金属走线252B在衬底210上的正投影至少部分位于第二子像素230G的发光器件232在衬底210上的正投影之内。
第三段金属走线252C在衬底210上的正投影至少部分位于第三子像素230R的发光器件232在衬底210上的正投影之内。
在一些示例中，请参阅图7C，显示面板200还包括第二透明走线层272。第二透明走线层272位于第一透明走线层271背离衬底210的一侧，或朝向衬底210的一侧。
一条扫描信号线GT中的多段透明连接走线262包括第一段透明连接走线262A、第二段透明连接走线262B、第三段透明连接走线262C和第四段透明连接走线262D。其中，第一段透明连接走线262A、第二段透明连接走线262B和第三段透明连接走线262C位于第一透明走线层271。而第四段透明连接走线262D位于第二透明走线层272。
其中，每个第一像素单元220中的第一子像素230B所电连接的第一段金属走线252A和第三子像素230R所电连接的第三段金属走线252C通过第一段透明连接走线262A电连接。
一个第一像素单元220中第一子像素230B所电连接的第一段金属走线252A，与在行方向X上相邻的第一像素单元220中第三子像素230R所电连接的第三段金属走线252C通过第二段透明连接走线262B电连接。
第三段透明连接走线262C的一端与第二段金属走线252B远离第一子像素230B的一端电连接，另一端与第四段透明连接走线262D电连接，而第四段透明连接走线262D远离第三段透明连接走线262C的一端与第二段透明连接走线262B电连接。
在一些实施例中，请参阅图5D，像素驱动电路231的电路主体2311还包括第一发光控制晶体管T5和第二发光控制晶体管T6。至少一条信号线还包括发光控制信号线EM，一条发光控制信号线EM与一行第一像素单元220中所有子像素230的第一发光控制晶体管T5的控制极和第二发光控制晶体管T6的控制极电连接。
发光控制信号线EM用于传输发光控制信号，一行第一像素单元220中所有子像素230接收同一发光控制信号。一行第一像素单元220中第一发光控制晶体管T5和第二发光控制晶体管T6同时开启。
请参阅图7B和图7C，发光控制信号线EM的金属走线253位于第一栅金属层Gate1。发光控制信号线EM的金属走线253在衬底210上的正投影的至少部分位于发光器件232在衬底210上的正投影之内。发光控制信号线EM的透明连接走线263位于第一透明走线层271，发光控制信号线EM的透明连接走线263与发光控制信号线EM的金属走线253通过过孔连接。其中，图7B和图7C中未示出发光器件232，可参阅图5A。
在其他的一些示例中，请参阅图5A，发光控制信号线EM的金属走线253在衬底210上的正投影的至少部分位于子像素230的阳极AND1在衬底210上的正投影之内。
请参阅图7B和图7C，发光控制信号线EM包括多段金属走线253，一段金属走线253在衬底210上的正投影至少部分位于一个发光器件232在的衬底210上的正投影之内。在一些示例中，每段金属走线253的全部均设置于发光器件232之下。在另一些示例中，每段金属走线253的部分设置于发光器件232之下。
在一些示例中，请参阅图5A，发光控制信号线EM中一段金属走线253与一个子像素230中的第一发光控制晶体管T5的控制极和第二发光控制晶体管T6的控制极电连接。
在一些示例中，请参阅图6A，有源膜层240包括第一发光控制晶体管T5的有源层T5-P和第二发光控制晶体管T6的有源层T6-P。
其中，请参阅图5D，一段金属走线253与第一发光控制晶体管T5的有源层T5-P的交叠部分复用为第一发光控制晶体管T5的控制极。一段金属走线253与第二发光控制晶体管T6的有源层T6-P的交叠部分复用为第二发光控制晶体管T6的控制极。即一个子像素230中的第一发光控制晶体管T5的控制极和第二发光控制晶体管T6的控制极位于一段金属走线252上。
在一些示例中，请参阅图6A，有源膜层240还包括驱动晶体管T3的有源层T3-P，请参阅图6B，第一栅金属层Gate1中还包括电容器Cst的第二极板Cst2，请参阅图5D，第二极板Cst2在衬底210上的正投影与驱动晶体管T3的有源层T3-P在衬底210上的正投影部分重叠，其中，第二极板Cst2与驱动晶体管T3的有源层T3-P的交叠部分作为驱动晶体管T3的控制极。
在一些示例中，请参阅图7C，一条发光控制信号线EM中包括多段金属 走线253和多段透明连接走线263。其中，多段金属走线253中包括第四段金属走线253D、第五段金属走线253E和第六段金属走线253F。其中，图7C中未示出发光控制信号线EM、金属走线253和透明连接走线263，可参阅图7B。
其中，第四段金属走线253D在衬底210上的正投影至少部分位于第一子像素230B的发光器件232在衬底210上的正投影之内。
第五段金属走线253E在衬底210上的正投影至少部分位于第二子像素230G的发光器件232在衬底210上的正投影之内。
第六段金属走线253F在衬底210上的正投影至少部分位于第三子像素230R的发光器件232在衬底210上的正投影之内。
请参阅图7B，一条发光控制信号线EM中的多段透明连接走线263包括第五段透明连接走线263E、第六段透明连接走线263F和第七段透明连接走线263G，且均位于第一透明走线层271。
请参阅图7B，一个第一像素单元220中的第一子像素230B所电连接的第四段金属走线253D和第三子像素230R所电连接的第六段金属走线253F通过第五段透明连接走线263E电连接。
一个第一像素单元220中第一子像素230B所电连接的第四段金属走线253D，与在第一指定方向C1上相邻的第一像素单元220中第三子像素230R所电连接的第六段金属走线253F通过第六段透明连接走线263F电连接。
第七段透明连接走线263G的一端与第二子像素230G所电连接的第五段金属走线253E远离第一子像素230B的一端电连接，另一端与第六段透明连接走线263F电连接。
除了第一栅金属层Gate1外，在一些实施例中，请参阅图8A和图8B，显示面板200还包括：第二栅金属层Gate2，第二栅金属层Gate2位于有源膜层240和发光器件232之间。
在一些示例中，第二栅金属层Gate2的材料为金属，例如Al、Ag、Cu、Cr等。
请参阅图8A和图8B，像素驱动电路231的电路主体2311还包括：电容器Cst，电容器Cst的第一极板Cst1位于第二栅金属层Gate2。
在一些示例中，请参阅图8B，第二栅金属层Gate2位于第一栅金属层Gate1远离衬底210的一侧。其中，电容器Cst的第一极板Cst1，第一极板Cst1在衬底210上的正投影与第二极板Cst2在衬底210上的正投影至少部分重叠。
在一些实施例中，请参阅图9A和图9B，显示面板200包括：第一源漏金属层SD1，第一源漏金属层SD1位于衬底210和发光器件232之间，第一源漏金属层SD1位于第二栅金属层Gate1背离衬底210的一侧，第一透明走线层271位于第一源漏金属层SD1背离衬底210的一侧，第一透明走线层271位于第一源漏金属层SD1和发光器件232之间。其中，请参阅图9C，第二栅金属层Gate1与第一源漏金属层SD1之间设置有层间介质层ILD，层间介质层ILD中设置有多个过孔ILDO，其中，层间介质层ILD中多个过孔的位置如图9C所示。
在一些示例中，第一源漏金属层SD1的材料为金属，例如Al、Ag、Cu、Cr等。
请参阅图7B和图7C，至少一条信号线还包括：初始化信号线VIN，一条初始化信号线VIN与一行第一像素单元220中第二复位晶体T12的第一极电连接。其中，初始化信号线VIN的金属走线254位于第一源漏金属层SD1。请参阅图5A，初始化信号线VIN的金属走线254在衬底210上的正投影的至少部分位于第一子像素230B的发光器件232在衬底210上的正投影之内。
在一些示例中，一条初始化信号线VIN中包括多段金属走线254，一段金属走线254与一个第一子像素230B的发光器件232有交叠。
在一些示例中，初始化信号线VIN中的一段金属走线254全部设置于第一子像素230B的发光器件232之下。
在另一些示例中，初始化信号线VIN中一段金属走线254的部分设置于第一子像素230B的发光器件232之下。此时，初始化信号线VIN的透明连接走线264则部分位于第一子像素230B的发光器件232之下。
请参阅图7B，初始化信号线VIN的透明连接走线264位于第一透明走线层271；初始化信号线VIN的透明连接走线264与初始化信号线VIN的金属走线254通过过孔连接。其中，初始化信号线VIN的透明连接走线264在衬底210上的正投影，位于第二子像素230G的发光器件232在衬底210上的正投影之外，且位于第三子像素230R的发光器件232在衬底210上的正投影之外。因此，初始化信号线VIN的透明连接走线264不会占用第二子像素230G的发光器件232和第三子像素230R的发光器件232之下的空间，进而增大了第二子像素230G的发光器件232和第三子像素230R的发光器件232之下的像素驱动电路231的面积，以此避免了第二子像素230G的发光器件232和第三子像素230R的发光器件232之下的像素驱动电路231的结构过于紧凑，而发生耦合。其中，图7B中未示出第二子像素230G的发光器件232和第三子 像素230R的发光器件232，请参阅图5B。
在其他的一些示例中，请参阅图5A，初始化信号线VIN的金属走线254在衬底210上的正投影的至少部分位于第一子像素230B的阳极AND-B在衬底210上的正投影之内。初始化信号线VIN的透明连接走线264在衬底210上的正投影，位于第二子像素230G的阳极AND-G在衬底210上的正投影之外，且位于第三子像素230R的阳极AND-R在衬底210上的正投影之外。
在一些示例中，请参阅图5A和图9A，初始化信号线VIN中的金属走线254包括主体走线段2541和连接走线段2542，其中，主体走线段2541沿行方向X延伸，而连接走线段2542沿列方向Y延伸，主体走线段2541靠近第三子像素230R的一端与连接走线段2542连接。
请参阅图5A，第二复位晶体管T12的有源层T12-P靠近第三子像素230R的一端与连接走线段2542的中部通过过孔连接，而连接走线段2542远离主体走线段2541的一端与第一子像素230B中第三复位晶体管T7的有源层T7-P通过过孔连接。
在一些示例中，请参阅图7B，显示面板200还包括第一透明连线281，第一透明连线281位于第一透明走线层271，第一透明连线281的一端与连接走线段2542远离主体走线段2541的一端电连接，另一端与第三子像素230R中第三复位晶体管T7的有源层T7-P电连接。
在一些示例中，请参阅图7C，显示面板200还包括第二透明连线282和第三透明连线283，其中第二透明连线282位于第一透明走线层271，第三透明连线283位于第二透明走线层272。其中，第二透明连线282的一端与第二子像素230G的第三复位晶体管T7的有源层T7-P电连接，另一端与第三透明连线283电连接，而第三透明连线283远离第二透明连线282的一端与第一透明连线281连接于连接走线段2542的一端过孔连接。
请参阅图7B，显示面板200中还包括第四透明连线284和第五透明连线285，其中，第四透明连线284和第五透明连线285均位于第一透明走线层271。
第五透明连线285的一端与第二子像素230G中第一复位晶体管T11-G的有源层T11-GP电连接，另一端与第二子像素230G中驱动晶体管T3的控制极也就是电容器Cst的第二极板Cst2电连接。
第四透明连线284的一端与第三子像素230R中第一复位晶体管T11-R的有源层T11-RP电连接，另一与第三子像素230R中驱动晶体管T3的控制极也就是电容器Cst的第二极板Cst2电连接。
除初始化信号线VIN中的金属走线254外，第一源漏金属层SD1中还包 括多个桥接图案，桥接图案通过过孔与有源膜层240、第一栅金属层Gate1和第二栅金属层Gate2通过过孔连接。
在一些示例中，请参阅图9A和图9B，多个桥接图案中包括第一桥接图案510，第一桥接图案510的一端与第二发光控制晶体管T6的有源层T6-P通过过孔连接，另一端与第三复位晶体管T7的有源层T7-P通过过孔连接。
在一些示例中，请参阅图9A和图9B，多个桥接图案中包括第二桥接图案520，第二桥接图案520的一端与驱动晶体管T3的控制极即电容器Cst的第二极板Cst2通过过孔连接，另一端与补偿晶体管T2的有源层T2-P通过过孔连接。
在一些示例中，请参阅图9A和图9B，多个桥接图案中包括第三桥接图案530，第三桥接图案530的一端与电容器Cst的第一极板Cst1通过过孔连接，另一端与第一发光控制晶体管T5的有源层T5-P通过过孔连接。
在其他的一些示例中，多个桥接图案在衬底210上的正投影也位于阳极AND1在衬底210上的正投影之内。
在一些实施例中，请参阅图10A和图10B，显示面板200包括：第二源漏金属层SD2，第二源漏金属层SD2位于衬底210和发光器件232之间，且第二源漏金属层SD2位于第二栅金属层Gate2背离衬底210的一侧。
请参阅图11A和图11B，显示面板200还包括：第二透明走线层272，第二透明走线层272均位于衬底210和发光器件232之间，第二透明走线层272位于第二源漏金属层SD2背离第二栅金属层Gate2的一侧。
在一些示例中，第二源漏金属层SD2位于第一源漏金属层SD1背离衬底210的一侧。第二源漏金属层SD2的材料为金属，例如Al、Ag、Cu、Cr等。第二透明走线层272的材料为透明导电氧化物材料，例如为ITO、IZO等。
在显示面板200中还包括第一源漏金属层SD1和第一透明走线层271的情况下，在一些示例中，第一源漏金属层SD1、第二源漏金属层SD2、第一透明走线层271和第二透明走线层272依次设置于第二栅金属层Gate2背离衬底210的一侧。
在另一些示例中，第一源漏金属层SD1、第一透明走线层271、第二源漏金属层SD2和第二透明走线层272依次设置于第二栅金属层Gate2背离衬底210的一侧。其中，请参阅图11C，第一源漏金属层SD1和第一透明走线层271之间设置有钝化层PVX，钝化层PVX中设置有多个过孔PVXO。请参阅图11D，第一透明走线层271和第二源漏金属层SD2之间设置有第一平坦化层PLN1，第一平坦化层PLN1中设置有多个过孔PLNO1。请参阅图11E， 第二源漏金属层SD2和第二透明走线层272之间设置有第二平坦化层PLN2，第二平坦化层PLN2中设置有多个过孔PLNO2。
请参阅图11B，至少一条信号线还包括第一电源信号线VDD1，第一电源信号线VDD1沿列方向Y延伸，一条第一电源信号线VDD1与一列第一像素单元220中第二子像素230G的电容器Cst的第一极板Cst1和第三子像素230R的电容器Cst的第一极板Cst1电连接。
其中，第一电源信号线VDD1沿列方向Y延伸，是指第一电源信号线VDD1的主体图案呈沿某列方向Y延伸的趋势。第一电源信号线VDD1的图案可以为一直线图形，也可以为一近似直线图形。
其中，第一电源信号线VDD1用于传输第一类电源信号。第一电源信号线VDD1与电容器Cst的第一极板Cst1电连接，以此将第一类电源信号传输至第一极板Cst1。
请参阅图11B，第一电源信号线VDD1的金属走线255位于第二源漏金属层SD2，第一电源信号线VDD1的金属走线255在衬底210上的正投影的至少部分位于第二子像素230G的发光器件232和第三子像素230R的发光器件232在的衬底210上的正投影之内。第一电源信号线VDD1的透明连接走线265位于第二透明走线层272，第一电源信号线VDD1的透明连接走线265与第一电源信号线VDD1的金属走线255通过过孔连接。其中，图11B中未示出第二子像素230G的发光器件232和第三子像素230R的发光器件232，可参阅图5C。
在其他的一些示例中，请参阅图11B，第一电源信号线VDD1的金属走线255在衬底210上的正投影的至少部分位于第二子像素230G的阳极AND-G和第三子像素230R的阳极AND-R在的衬底210上的正投影之内。图11B中未示出第二子像素230G的阳极AND-G和第三子像素230R的阳极AND-R，可参阅图5C。
在一些示例中，请参阅图11B，第一电源信号线VDD1中包括多段金属走线255，其中，第一电源信号线VDD1中的多段金属走线255包括第七段金属走线255G和第八段金属走线255H。
在一些示例中，第七段金属走线255G在衬底210上的正投影的全部位于第二子像素230G的发光器件232在衬底210上的正投影之内。第八段金属走线255H在衬底210上的正投影的全部位于第三子像素230R的发光器件232在衬底210上的正投影之内。此时，第七段金属走线255G和第八段金属走线255H之间通过透明连接走线265电连接，透明连接走线265延伸至第三子像 素230R的发光器件232之下以及第二子像素230G的发光器件232之下。
在另一些示例中，第七段金属走线255G在衬底210上的正投影的部分位于第二子像素230G的发光器件232在衬底210上的正投影之内，其余部分位于第二子像素230G的发光器件232在衬底210上的正投影之外。第八段金属走线255H在衬底210上的正投影的部分位于第三子像素230R的发光器件232在衬底210上的正投影之内，其余部分位于第三子像素230R的发光器件232在衬底210上的正投影之外。
在一些示例中，请参阅图11B，第一电源信号线VDD1中包括多段透明连接走线265，多段透明连接走线265中包括第八段透明连接走线265H和第九段透明连接走线265I。
在一个第一像素单元220中，第二子像素230G所电连接的第七段金属走线255G与第三子像素230R所电连接的第八段金属走线255H之间，通过第八段透明连接走线265H电连接。
一个第一像素单元220中第三子像素230R所电连接的第八段金属走线255H与在第二指定方向C2上相邻的第一像素单元220中第二子像素230G所电连接的第七段金属走线255G之间，通过第九段透明连接走线265I电连接。
在一些示例中，请参阅图12A，第一电源信号线VDD1的第七段金属走线255G与位于第二子像素230G的发光器件232之下的第三桥接图案530通过过孔连接，以此将第一类电源信号线通过第三桥接图案530传输至第二子像素230G中电容器Cst的第一极板Cst1和第一发光控制晶体管T5的有源层T5-P。
在一些示例中，请参阅图12B，第一电源信号线VDD1的第八段金属走线255H与位于第三子像素230R的发光器件232之下的第三桥接图案530通过过孔连接，以此将第一类电源信号线通过第三桥接图案530传输至第三子像素230R中电容器Cst的第一极板Cst1和第一发光控制晶体管T5的有源层T5-P。
在一些实施例中，请参阅图11B，至少一条信号线还包括第二电源信号线VDD2，第二电源信号线VDD2沿列方向Y延伸，一条第二电源信号线VDD2与一列第一像素单元220中第一子像素230B的电容器Cst的第一极板Cst1电连接。
其中，第二电源信号线VDD2沿列方向Y延伸，是指第二电源信号线VDD2的主体图案呈沿某列方向Y延伸的趋势。第二电源信号线VDD2图案可以为一直线图形，也可以为一近似直线图形。
其中，第二电源信号线VDD2用于传输第一类电源信号。第二电源信号线VDD2与第一子像素230B的电容器Cst的第一极板Cst1电连接，以此将第一类电源信号传输至第一子像素230B的第一极板Cst1。
请参阅图11B，第二电源信号线VDD2的金属走线256位于第二源漏金属层SD2，第二电源信号线VDD2的金属走线256在衬底210上的正投影至少部分位于第一子像素230B的发光器件232在的衬底210上的正投影之内；第二电源信号线VDD2的透明连接走线266位于第二透明走线层272，第二电源信号线VDD2的透明连接走线266与第二电源信号线VDD2的金属走线256通过过孔连接。其中，图11B中未示出第一子像素230B的发光器件232，可参阅图5C。
在一些示例中，第二电源信号线VDD2的金属走线256在衬底210上的正投影全部位于第一子像素230B的发光器件232在的衬底210上的正投影之内。此时，第二电源信号线VDD2的透明连接走线266在衬底210上的正投影与第一子像素230B的发光器件232在的衬底210上的正投影部分重叠。
在另一些示例中，第二电源信号线VDD2的金属走线256在衬底210上的正投影的部分位于第一子像素230B的发光器件232在的衬底210上的正投影之内。
在其他的一些示例中，第二电源信号线VDD2的金属走线256在衬底210上的正投影至少部分位于第一子像素230B的AND-B在的衬底210上的正投影之内。
在一些示例中，请参阅图12C，第二电源信号线VDD2的金属走线256与位于第一子像素230B的发光器件232之下的第三桥接图案530通过过孔连接，以此将第一类电源信号通过第三桥接图案530传输至第一子像素230B中电容器Cst的第一极板Cst1和第一发光控制晶体管T5的有源层T5-P。
以上对显示面板200中的复位信号线RST、扫描信号线GT、发光控制信号线EM、第一电源信号线VDD1以及第二电源信号线VDD2进行了介绍。除了上述的一些信号线外，显示面板200中还包括数据线DT。在一些实施例中，请参阅图11B，显示面板200还包括：多条数据线DT，多条数据线DT沿列方向Y延伸。
其中，数据线DT沿列方向Y延伸，是指数据线DT的主体图案呈沿某列方向Y延伸的趋势。数据线DT图案可以为一直线图形，也可以为一近似直线图形。
请参阅图11B，多条数据线DT位于第一显示区A1中的部位在衬底210 上的正投影位于任一子像素230的发光器件232在衬底210上的正投影之外。
因此，数据线DT不会占用发光器件232之下的空间，进而可以增大发光器件232之下的像素驱动电路231占用的空间，避免发光器件232之下的像素驱动电路231的结构过于紧凑。
其中，至少一条数据线DT位于第一显示区A1的部位位于第二透明走线层272。其中，数据线DT位于第一显示区A1中的部位设置于第二透明走线层272，数据线DT位于第一显示区A1中的部位不会对光线造成遮挡，进而可以提高显示面板200中第一显示区A1的透光率。
请参阅图7C，像素驱动电路231的电路主体2311包括：写入晶体管T4。在一个第一像素单元220中，第一子像素230B的写入晶体管T4的第一极、第二子像素230G的写入晶体管T4的第一极和第三子像素230R的写入晶体管T4的第一极分别连接于不同的数据线DT。其中，图7C中未示出第一子像素230B的写入晶体管T4、第二子像素230G的写入晶体管T4的第一极和第三子像素230R的写入晶体管T4，可参阅图5D。
数据线DT用于传输数据信号，在每个子像素230中，写入晶体管T4的第一极与数据线DT电连接，以此数据信号可以传输至写入晶体管T4的第一极。在一个第一像素单元220中，多个子像素230分别连接于不同的数据线DT，不同的数据线DT中的数据信号的电压可以不同，进而使得不同的子像素230中的发光器件232可以具有不同的灰阶。
此外，在上述的一些实施例中，在一个第一像素单元220中，多个子像素230中的第一复位晶体管T11和第二复位晶体管T12同时开启，因此多个子像素230中的像素驱动电路231同时处于复位阶段。补偿晶体管T2、写入晶体管T4和第三复位晶体管T7同时开启，因此多个子像素230中的像素驱动电路231同时处于数据刷新及补偿阶段t2，在数据刷新及补偿阶段t2，数据信号经过写入晶体管T4和补偿晶体管T2写入驱动晶体管T3的控制极，因此数据信号同时写入一个第一像素单元220中的像素驱动电路231。第一发光控制晶体管T5和第二发光控制晶体管T6同时开启，因此多个子像素230中的像素驱动电路231同时处于发光阶段t3。综上，一个第一像素单元220中，多个子像素230同时发光。
在一些实施例中，请参阅图7C，至少一条数据线DT位于第一显示区A1中的部位为透明走线段27。
透明走线段27位于第二透明走线层272，除透明走线段27外，第二透明走线层272还包括透明连接图案2701，其中，透明连接图案2701大致沿行方 向X延伸，透明连接图案2701的一端连接于透明走线段27，另一端与写入晶体管T4的有源层T4-P电连接。
在一些示例中，请参阅图9A，第一源漏金属层SD1中还包括第四桥接图案540。第一透明走线层271和第二源漏金属层SD2中均设置有转接图案。透明连接图案2701远离透明走线段27的一端通过过孔与第二源漏金属层SD2中的转接图案过孔连接，而第二源漏金属层SD2中的转接图案通过过孔与第一透明走线层271中的转接图案过孔连接，而第一透明走线层271中的转接图案与第四桥接图案540过孔连接，第四桥接图案540与写入晶体管T4的有源层T4-P通过过孔连接，进而使得数据信号传输至写入晶体管T4的第一极。其中，通过在透明连接图案2701与写入晶体管T4的有源层T4-P设置第四桥接图案540以及多个转接图案，可以减小过孔深度。由于过孔越深，阻抗越大，因此，在本公开的一些示例中，可以降低阻抗。
在一些示例中，每条数据线DT位于第一显示区A1中的部位均位于第二透明走线层272，即每条数据线DT均包括透明走线段27。
请参阅图11B，在同一列第一像素单元220内，第一子像素230B中写入晶体管T4所电连接的数据线DT-B的透明走线段27-B在衬底210上的正投影，位于该第一子像素230B的电路主体2311-B在衬底210上的正投影远离第二子像素230G的电路主体2311-G在衬底210上的正投影的一侧。
第二子像素230G的发光器件232在衬底210上的正投影和第三子像素230R的发光器件232在衬底210上的正投影，位于第二子像素230G的写入晶体管T4所电连接的数据线DT-G的透明走线段27-G在衬底210上的正投影和第三子像素230G的写入晶体管T4所电连接的数据线DT-R的透明走线段27-R在衬底210上的正投影之间。
其中，第二子像素230G所电连接的透明走线段27-G和第三子像素230G所电连接的透明走线段27-R分别设置于第二子像素230G和第三子像素230G所在列的两侧。
在一些示例中，请参阅图11A和图11B，透明走线段27-R、透明走线段27-G和透明走线段27-B沿第一指定方向C1依次设置。
在另一些示例中，透明走线段27-G、透明走线段27-R和透明走线段27-B沿第一指定方向C1依次设置。
在一些实施例中，请参阅图5D，在一个第一像素单元220内，第一子像素230B中的第三复位晶体管T7、补偿晶体管T2和写入晶体管T4依次远离第二子像素230G的电路主体2311-G。即第一子像素230B中的第三复位晶体 管T7、补偿晶体管T2和写入晶体管T4依次远离第二子像素230G和第三子像素230R所在列，进而可以使得第一子像素230B所电连接的透明走线段27-B位于第一子像素230B远离第二子像素230G和第三子像素230R所在列的一侧。
在一些实施例中，请参阅图5D，在一个第一像素单元220内，第二子像素230G中的第三复位晶体管T7、补偿晶体管T2和写入晶体管T4沿第一设定方向依次设置；第三子像素230R中的第三复位晶体管T7、补偿晶体管T2和写入晶体管T4沿第一设定方向的反方向依次设置。
其中，请参阅图11B，并结合图5D，透明走线段27与写入晶体管T4的有源层T4-P电连接。在第二子像素230G和第三子像素230R中的一个子像素230中，写入晶体管T4位于补偿晶体管T2远离第一子像素230B的一侧。在另一个子像素230中，写入晶体管T4位于补偿晶体管T2靠近第一子像素230B的一侧。因此，可以使得第二子像素230G电连接的透明走线段27-G和第三子像素230R的透明走线段27-R分别设置于第二子像素230G和第三子像素230R所在列的两侧，且能够方便透明走线段27-R与第三子像素230R的写入晶体管T4连接，同时方便透明走线段27-G与第二子像素230G的写入晶体管T4连接。
在一些示例中，请参阅图11B，第一设定方向D与第一指定方向C1相反，此时，第三子像素230R所电连接的透明走线段27-R、第二子像素230G所电连接的透明走线段27-G和第一子像素230B所电连接的数据线27-B沿第一指定方向C1依次设置。
在另一些示例中，第一设定方向D与第一指定方向C1相同，第二子像素230G所电连接的透明走线段27-G、第三子像素230R所电连接的透明走线段27-R和第一子像素230B所电连接的数据线27-B沿第一指定方向C1依次设置。
请参阅图13A和图13B，显示面板200中还包括阳极层AND，阳极层AND中包括多个阳极AND1，例如第一子像素230B的阳极AND-B、第二子像素230G的阳极AND-G和第三子像素230R的阳极AND-R。
在一些实施例中，请参阅图2B，除第一显示区A1外，显示面板200还包括：第二显示区A2，第一显示区A1设置有第一像素单元220。第二显示区A2内设置有多个第二像素单元290，多个第二像素单元290呈多行多列排布；第二像素单元290包括多个子像素291。多个子像素291中包括第一子像素291B、第二子像素291G和第三子像素291R，
其中，第二显示区A2位于第一显示区A1的至少一侧。在一些示例中，第二显示区A2可以设置于第一显示区A1的一侧或多侧。在另一些示例中，第二显示区A2可以绕第一显示区A1设置一周。其中需要说明的是，在图2B中，较小的虚线框所框出来的区域为第一显示区A1，而较大的虚线框位于较小虚线框的外部，较小虚线框与较大虚线框之间的区域为第二显示区A2，第一显示区A1和第二显示区A2共同构成了显示区AA。
请参阅图14，第二像素单元290的子像素291包括发光器件232，第二像素单元290的第一子像素291B的发光器件232的面积，大于第二像素单元290的第二子像素291G的发光器件232的面积，且大于第二像素单元290的第三子像素291R的发光器件232的面积。
其中，发光器件232包括阳极AND1。在一些示例中，第二像素单元290的第一子像素291B的阳极AND1的面积，大于第二像素单元290的第二子像素291G的阳极AND1的面积，且大于第二像素单元290的第三子像素291R的阳极AND1的面积。
在一些实施例中，第一显示区A1中子像素230的发光器件232的面积为第二显示区A2中相同颜色的子像素291的发光器件232的面积的0.4～0.6倍。
在一些示例中，在第二显示区A2中，第二像素单元290的第一子像素291B可以为蓝色子像素，第二子像素291G可以为绿色子像素，第三子像素291R可以红色子像素。
通过上文可知，在一些示例中，在第一显示区A1中，第一像素单元220的第一子像素230B为蓝色子像素，第二子像素230G为绿色子像素，第三子像素230R为红色子像素。
在一些示例中，第一像素单元220的第一子像素230B的发光器件232的面积为第二像素单元290的第一子像素291B的发光器件232的面积的0.4～0.6倍，以此可以避免第一像素单元220的第一子像素230B的发光器件232的面积过大(例如大于第一子像素291B的发光器件232的面积的0.6倍)，导致第一显示区A1的透光率较低。同时，还可以避免第一像素单元220的第一子像素230B的发光器件232的面积过小(例如小于第一子像素291B的发光器件232的面积的0.4倍)，导致位于第一像素单元220的第一子像素230B的发光器件232之下的像素驱动电路231所占的面积较小，使得第一像素单元220的第一子像素230B的发光器件232的像素驱动电路231中的结构过于紧凑，造成结构之间发生耦合。
示例性的，第一像素单元220的第一子像素230B的发光器件232的面积 为第二像素单元290的第一子像素291B的发光器件232的面积的0.5倍。
请参阅图14，第一像素单元220的第二子像素230G的发光器件232的面积为第二像素单元290的第二子像素291G的发光器件232的面积的0.4～0.6倍，以此可以避免第一像素单元220的第二子像素230G的发光器件232的面积过大(例如大于第二子像素291G的发光器件232的面积的0.6倍)，导致第一显示区A1的透光率较低。同时，还可以避免第一像素单元220的第二子像素230G的发光器件232的面积过小(例如小于第二子像素291G的发光器件232的面积的0.4倍)，导致第一像素单元220的第二子像素230G的发光器件232之下的第二子像素230G的电路主体2311-G所占的面积较小，使得第一像素单元220的第二子像素230G的电路主体2311-G中的结构过于紧凑，造成结构之间发生耦合。
示例性的，第一像素单元220的第二子像素230G的发光器件232的面积为第二像素单元290的第二子像素291G的发光器件232的面积的0.5倍。
请参阅图14，第一像素单元220的第三子像素230R的发光器件232的面积为第二像素单元290的第三子像素291R的发光器件232的面积的0.4～0.6倍。以此可以避免第一像素单元220的第三子像素230R的发光器件232的面积过大(例如大于第三子像素291R的发光器件232的面积的0.6倍)，导致第一显示区A1的透光率较低。同时，还可以避免第一像素单元220的第三子像素230R的发光器件232的面积过小(例如小于第三子像素291R的发光器件232的面积的0.4倍)，导致第一像素单元220的第三子像素230R的发光器件232之下的第三子像素230R的电路主体2311-R所占的面积较小，使得第三子像素230R的电路主体2311-R中的结构过于紧凑，造成结构之间发生耦合。
示例性的，第一像素单元220的第三子像素230R的发光器件232的面积为第二像素单元290的第三子像素291R的发光器件232的面积的0.5倍。
在一些示例中，第一显示区A1的子像素密度与第二显示区A2的子像素密度相等。其中，需要说明的是，第一显示区A1的子像素密度指的是，在第一显示区A1中，单位面积内子像素230的数量。第二显示区A2的子像素密度指的是，在第二显示区A2内，单位面积内子像素291的数量。
其中，虽然第二显示区A2中子像素291的发光器件232的面积大于第一显示区A1中与其颜色相同的子像素230的发光器件232的面积，但是第一显示区A1的子像素密度与第二显示区A2的子像素密度相等，因此，可以降低第一显示区A1与第二显示区A2之间的显示差异。
此外，第一显示区A1的透光率大于第二显示区A2的透光率，以此保证传感器300可以感测到充足的光线。
其中，子像素291的发光器件232的结构与上述子像素230的发光器件232的结构相同，在此不进行赘述。其中，可以理解的是，在一个子像素291的阴极CTD1、发光层EL和阳极AND1三者中，若阴极CTD1的面积最大，那么子像素291的发光器件232的面积则为阴极CTD1的面积。若阳极AND1的面积最大，那么子像素291的发光器件232的面积则为阳极AND1的面积。若发光层EL的面积最大，那么子像素291的发光器件232的面积则为发光层EL的面积。
本公开的一些实施例所提供的显示装置100包括：以上任一实施例所提供的显示面板200。因此本公开的一些实施例所提供的显示装置100具有以上任一实施例所提供的显示面板200的全部有益效果，在此不进行赘述。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种显示面板，包括：
    衬底；
    多个第一像素单元，位于所述衬底的一侧，且呈多行多列排布；其中，所述第一像素单元中包括多个子像素，所述子像素包括像素驱动电路和发光器件；所述发光器件位于所述像素驱动电路远离所述衬底的一侧，且与所述像素驱动电路电连接；所述像素驱动电路包括第一复位晶体管；
    所述多个子像素包括第一子像素、第二子像素和第三子像素，且所述第一子像素的发光器件的面积，大于所述第二子像素的发光器件的面积，且大于所述第三子像素的发光器件的面积；
    所述第二子像素中的第一复位晶体管和/或所述第三子像素中的第一复位晶体管在所述衬底上的正投影，位于所述第一子像素的发光器件在所述衬底上的正投影之内。
  2. 根据权利要求1所述的显示面板，其中，
    所述第一子像素的第一复位晶体管、所述第二子像素的第一复位晶体管和所述第三子像素的第一复位晶体管，均位于所述第一子像素的发光器件在所述衬底的正投影之内。
  3. 根据权利要求1或2所述的显示面板，其中，
    所述第一子像素的第一复位晶体管、所述第二子像素的第一复位晶体管和所述第三子像素的第一复位晶体管中的至少两个，为同一晶体管。
  4. 根据权利要求1～3中任一项所述的显示面板，其中，
    所述像素驱动电路还包括第二复位晶体管；所述第一子像素的第二复位晶体管、所述第二子像素的第二复位晶体管和所述第三子像素的第二复位晶体管，为同一晶体管；所述第二复位晶体管在所述衬底上的正投影，位于所述第一子像素的发光器件在所述衬底上的正投影之内；所述第二复位晶体管与任一所述第一复位晶体管串联；
    所述显示面板还包括复位信号线和初始化信号线；各个所述第一复位晶体管的控制极和所述第二复位晶体管的控制极均与所述复位信号线电连接；所述第二复位晶体管的第一极与所述初始化信号线电连接，所述第二复位晶体管的第二极与各个所述第一复位晶体管的第一极电连接；
    所述像素驱动电路还包括：驱动晶体管，各个所述像素驱动电路的驱动晶体管的控制极与各个所述第一复位晶体管的第二极电连接。
  5. 根据权利要求4所述的显示面板，其中，
    所述第二子像素的发光器件和所述第三子像素的发光器件沿列方向间隔 设置；所述第一子像素的发光器件，位于所述第二子像素的发光器件和所述第三子像素的发光器件所在列的相邻列；且所述第一子像素的发光器件，跨过所述第二子像素的发光器件和所述第三子像素的发光器件之间的间隙区域；
    所述像素驱动电路还包括电路主体；所述第一子像素的电路主体在所述衬底上的正投影位于所述第一子像素的发光器件在所述衬底上的正投影之内，所述第二子像素的电路主体在所述衬底上的正投影位于所述第二子像素的发光器件在所述衬底上的正投影之内、所述第三子像素的电路主体在所述衬底上的正投影位于所述第三子像素的发光器件在所述衬底上的正投影之内；
    所述第二复位晶体管、所述第三子像素的第一复位晶体管和所述第二子像素的第一复位晶体管，位于所述第一子像素的第一复位晶体管靠近所述第三子像素的电路主体的一侧，且依次远离所述第三子像素的电路主体。
  6. 根据权利要求5所述的显示面板，其中，
    所述复位信号线沿行方向延伸，一条所述复位信号线与一行所述第一像素单元中所述第二复位晶体管的控制极以及各个所述第一复位晶体管的控制极电连接；
    所述初始化信号线沿行方向延伸，一条所述初始化信号线与一行所述第一像素单元中所述第二复位晶体的第一极电连接；
    所述第二复位晶体管以及各个所述第一复位晶体管在所述衬底上的正投影，位于与该第二复位晶体管所电连接的初始化信号线在所述衬底上的正投影和所述第三子像素的电路主体在所述衬底上的正投影之间；所述复位信号线在所述衬底上的正投影，位于该条初始化信号线在所述衬底上的正投影和该第三子像素的电路主体在所述衬底上的正投影之间。
  7. 根据权利要求5或6所述的显示面板，其中，
    所述衬底包括第一显示区，所述多个第一像素单元位于所述第一显示区内；
    所述显示面板还包括：多条信号线，位于所述衬底和所述发光器件之间；
    至少一条信号线位于所述第一显示区内的部位包括彼此电连接的金属走线和透明连接走线；至少部分所述金属走线在所述衬底上的正投投影，位于所述发光器件在所述衬底上的正投影之内。
  8. 根据权利要求7所述的显示面板，包括：
    第一栅金属层和第一透明走线层，均位于所述衬底和所述发光器件之间， 所述第一透明走线层位于所述第一栅金属层背离所述衬底的一侧；
    所述至少一条信号线包括复位信号线，所述复位信号线沿行方向延伸，一条所述复位信号线与一行所述第一像素单元中所述第二复位晶体管的控制极以及各个第一复位晶体管的控制极电连接；
    所述复位信号线的金属走线位于所述第一栅金属层，所述复位信号线的金属走线在所述衬底上的正投影的至少部分位于所述第一子像素的发光器件在所述衬底上的正投影之内；
    所述复位信号线的透明连接走线位于所述第一透明走线层；所述复位信号线的透明连接走线在所述衬底上的正投影，位于所述第二子像素的发光器件在所述衬底上的正投影之外，且位于所述第三子像素的发光器件在所述衬底上的正投影之外；所述复位信号线的透明连接走线与所述复位信号线的金属走线通过过孔连接。
  9. 根据权利要求8所述的显示面板，其中，
    所述像素驱动电路的电路主体包括写入晶体管、补偿晶体管和第三复位晶体管；
    所述至少一条信号线还包括扫描信号线，一条所述扫描信号线与一行所述第一像素单元中所有所述子像素的写入晶体管的控制极、补偿晶体管的控制极和第三复位晶体管的控制极电连接；
    所述扫描信号线的金属走线位于所述第一栅金属层，所述扫描信号线的金属走线在所述衬底上的正投影的至少部分位于所述发光器件在所述的衬底上的正投影之内；
    所述扫描信号线的透明连接走线位于所述第一透明走线层，所述扫描信号线的透明连接走线与所述扫描信号线的金属走线通过过孔连接。
  10. 根据权利要求8或9所述的显示面板，其中，
    所述像素驱动电路的电路主体还包括第一发光控制晶体管和第二发光控制晶体管；
    所述至少一条信号线还包括发光控制信号线，一条所述发光控制信号线与一行所述第一像素单元中所有所述子像素的第一发光控制晶体管的控制极和第二发光控制晶体管的控制极电连接；
    所述发光控制信号线的金属走线位于所述第一栅金属层，所述发光控制信号线的金属走线在所述衬底上的正投影的至少部分位于所述发光器件在所述的衬底上的正投影之内；
    所述发光控制信号线的透明连接走线位于所述第一透明走线层，所述发 光控制信号线的透明连接走线与所述发光控制信号线的金属走线通过过孔连接。
  11. 根据权利要求7～10中任一项所述的显示面板，包括：第一源漏金属层和第一透明走线层，均位于所述衬底和所述发光器件之间，所述第一透明走线层位于所述第一源漏金属层背离所述衬底的一侧；
    所述至少一条信号线还包括：初始化信号线，一条所述初始化信号线与一行所述第一像素单元中所述第二复位晶体的第一极电连接；
    所述初始化信号线的金属走线位于所述第一源漏金属层，所述初始化信号线的金属走线在所述衬底上的正投影的至少部分位于所述第一子像素的发光器件在所述衬底上的正投影之内；
    所述初始化信号线的透明连接走线位于所述第一透明走线层；所述初始化信号线的透明连接走线在所述衬底上的正投影，位于所述第二子像素的发光器件在所述衬底上的正投影之外，且位于所述第三子像素的发光器件在所述衬底上的正投影之外；所述初始化信号线的透明连接走线与所述初始化信号线的金属走线通过过孔连接。
  12. 根据权利要求7～11中任一项所述的显示面板，包括：第二栅金属层、第二源漏金属层和第二透明走线层，位于所述衬底和所述发光器件之间，所述第二源漏金属层位于所述第二栅金属层背离所述衬底的一侧，所述第二透明走线层位于所述第二源漏金属层背离所述第二栅金属层的一侧；
    所述像素驱动电路的电路主体还包括：电容器，所述电容器的第一极板位于所述第二栅金属层；
    所述至少一条信号线还包括第一电源信号线，所述第一电源信号线沿列方向延伸，一条所述第一电源信号线与一列所述第一像素单元中所述第二子像素的电容器的第一极板和所述第三子像素的电容器的第一极板电连接；
    所述第一电源信号线的金属走线位于所述第二源漏金属层，所述第一电源信号线的金属走线在所述衬底上的正投影的至少部分位于所述第二子像素的发光器件和所述第三子像素的发光器件在所述的衬底上的正投影之内；
    所述第一电源信号线的透明连接走线位于所述第二透明走线层，所述第一电源信号线的透明连接走线与所述第一电源信号线的金属走线通过过孔连接。
  13. 根据权利要求12所述的显示面板，其中，
    所述至少一条信号线还包括第二电源信号线，所述第二电源信号线沿列方向延伸，一条所述第二电源信号线与一列所述第一像素单元中所述第一子 像素的电容器的第一极板电连接；
    所述第二电源信号线的金属走线位于所述第二源漏金属层，所述第二电源信号线的金属走线在所述衬底上的正投影至少部分位于所述第一子像素的发光器件在所述的衬底上的正投影之内；
    所述第二电源信号线的透明连接走线位于所述第二透明走线层，所述第二电源信号线的透明连接走线与所述第二电源信号线的金属走线通过过孔连接。
  14. 根据权利要求12或13所述的显示面板，还包括：
    多条数据线，沿列方向延伸，所述多条数据线位于所述第一显示区中的部位在所述衬底上的正投影位于任一所述子像素的发光器件在所述衬底上的正投影之外，至少一条数据线位于所述第一显示区的部位位于所述第二透明走线层；
    所述像素驱动电路的电路主体包括：写入晶体管；在一个所述第一像素单元中，所述第一子像素的写入晶体管的第一极、所述第二子像素的写入晶体管的第一极和所述第三子像素的写入晶体管的第一极分别连接于不同的所述数据线。
  15. 根据权利要求14所述的显示面板，其中，
    所述至少一条数据线位于所述第一显示区中的部位为透明走线段；
    在同一列所述第一像素单元内，所述第一子像素中写入晶体管所电连接的数据线的透明走线段在所述衬底上的正投影，位于该第一子像素的电路主体在所述衬底上的正投影远离所述第二子像素的电路主体在所述衬底上的正投影的一侧；所述第二子像素的发光器件在所述衬底上的正投影和所述第三子像素的发光器件在所述衬底上的正投影，位于所述第二子像素的写入晶体管所电连接的数据线的透明走线段在衬底上的正投影和所述第三子像素的写入晶体管所电连接的数据线的透明走线段在衬底上的正投影之间。
  16. 根据权利要求15所述的显示面板，其中，
    所述像素驱动电路的电路主体还包括补偿晶体管和第三复位晶体管；
    在一个所述第一像素单元内，所述第一子像素中的第三复位晶体管、补偿晶体管和写入晶体管依次远离所述第二子像素的电路主体；所述第二子像素中的第三复位晶体管、补偿晶体管和写入晶体管沿第一设定方向依次设置；所述第三子像素中的第三复位晶体管、补偿晶体管和写入晶体管沿所述第一设定方向的反方向依次设置。
  17. 根据权利要求1～16中任一项所述的显示面板，其中，
    所述发光器件包括阳极、发光层和阴极，所述阳极与所述像素驱动电路电连接，所述发光层位于所述阳极背离所述衬底的一侧，所述阴极位于所述发光层背离所述衬底的一侧；
    所述第二子像素中的第一复位晶体管和/或所述第三子像素中的第一复位晶体管在所述衬底上的正投影，位于所述第一子像素的阳极在所述衬底上的正投影之内。
  18. 根据权利要求1～17中任一项所述的显示面板，其中，
    所述第一子像素为蓝色子像素，所述第二子像素为绿色子像素，所述第三子像素为红色子像素。
  19. 根据权利要求1～18中任一项所述的显示面板，包括：
    第一显示区和第二显示区，所述第一显示区设置有所述第一像素单元；
    所述第二显示区设置有多个第二像素单元，所述多个第二像素单元呈多行多列排布；所述第二像素单元包括多个子像素，所述第一显示区的子像素密度与所述第二显示区的子像素密度相等；
    所述第一显示区中子像素的发光器件的面积为所述第二显示区中相同颜色的子像素的发光器件的面积的0.4～0.6倍。
  20. 一种显示装置，包括：
    权利要求1～19中任一项所述的显示面板。
PCT/CN2023/078983 2022-04-29 2023-03-01 显示面板及显示装置 WO2023207318A1 (zh)

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