WO2023206744A1 - 信号控制电路、信号控制方法和半导体存储器 - Google Patents

信号控制电路、信号控制方法和半导体存储器 Download PDF

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Publication number
WO2023206744A1
WO2023206744A1 PCT/CN2022/098681 CN2022098681W WO2023206744A1 WO 2023206744 A1 WO2023206744 A1 WO 2023206744A1 CN 2022098681 W CN2022098681 W CN 2022098681W WO 2023206744 A1 WO2023206744 A1 WO 2023206744A1
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Prior art keywords
signal
value
output
activation operation
module
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PCT/CN2022/098681
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English (en)
French (fr)
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高恩鹏
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长鑫存储技术有限公司
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Priority to US18/167,819 priority Critical patent/US20230352074A1/en
Publication of WO2023206744A1 publication Critical patent/WO2023206744A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing

Definitions

  • the present disclosure relates to, but is not limited to, a signal control circuit, a signal control method and a semiconductor memory.
  • DRAM Dynamic Random Access Memory
  • DRAM Dynamic Random Access Memory
  • Bit lines there are a large number of word lines in DRAM, and these word lines are arranged adjacently.
  • Row hammer effect Row Hammer
  • the memory cells on the word lines adjacent to the word line may generate data. mistake.
  • the problem caused by the hammer effect is generally solved by performing supplementary refresh operations on the basis of periodic refresh.
  • the above mechanism cannot completely avoid the impact of the row hammer effect, and data errors may still occur due to row hammer attacks.
  • an embodiment of the present disclosure provides a signal control circuit, including:
  • the generation module is used to accumulate the number of execution times of the activation operation. If the accumulated value is greater than or equal to the first preset value, a blocking signal is output;
  • a logic module configured to receive an activation operation signal and the blocking signal. If the blocking signal is received, the output of the activation operation signal is blocked; if the blocking signal is not received, the output of the blocking signal is output. Activate operating signal.
  • the generation module is further configured to receive a periodic refresh signal, a refresh management signal, or an activation operation signal output by the logic module; and, when receiving the activation operation signal, perform the cumulative value Perform an addition operation; when receiving the periodic refresh signal, subtract a second preset value from the accumulated value; when receiving the refresh management signal, subtract a third preset value from the accumulated value .
  • the generation module includes a calculation module, a latch module and a comparison module; wherein the calculation module is used to perform calculation processing on the accumulated value to obtain a first calculation value, a second calculation value and The third operation value; the latch module is used to receive the activation operation signal, the periodic refresh signal or the refresh management signal, and based on the first operation value corresponding to the activation operation signal, the The second operation value corresponding to the periodic refresh signal or the third operation value corresponding to the refresh management signal updates the cumulative value; the latch module is also used to store the updated cumulative value; The comparison module is used to compare the accumulated value with a first preset value, and if the accumulated value is greater than or equal to the first preset value, output the blocking signal.
  • the generation module includes a calculation module, a latch module and a comparison module; wherein the calculation module is used to generate The cumulative value is subjected to calculation processing to obtain a target calculation value; the latch module is used to update the cumulative value using the target calculation value and store the updated cumulative value; the comparison module is used to Comparing the accumulated value with the first preset value, if the accumulated value is greater than or equal to the first preset value, the blocking signal is output.
  • the generation module includes a calculation module, a latch module and a comparison module; wherein the calculation module is used to generate The accumulated value is subjected to corresponding operation processing to obtain the first operation value corresponding to the activation operation signal, the second operation value corresponding to the periodic refresh signal or the third operation value corresponding to the refresh management signal; the lock a storage module, configured to receive the activation operation signal, the periodic refresh signal or the refresh management signal; when receiving the activation operation signal, update the accumulated value using the first operation value; when receiving When the periodic refresh signal is used, the second operation value is used to update the accumulated value; when the refresh management signal is received, the third operation value is used to update the accumulated value; the latch module also uses After storing the updated accumulated value; the comparison module is used to compare the accumulated value with the first preset value, and if the accumulated value is greater than or equal to the first preset value, output the blocking signal .
  • the calculation module includes an addition unit, a first subtraction unit and a second subtraction unit; wherein the addition unit is used to activate the operation signal output by the logic module after the calculation module receives it. In this case, add one to the accumulated value and output a first operation value; the first subtraction unit is used to add the accumulated value to the calculated value when the calculation module receives the periodic refresh signal.
  • the second preset value performs subtraction processing and outputs a second operation value; the second subtraction unit is used to compare the accumulated value and the said refresh management signal when the calculation module receives the refresh management signal.
  • the third preset value is subtracted and a third operation value is output.
  • the latch module includes a first control output unit, a second control output unit, a third control output unit and a latch unit; wherein the first control output unit is configured to When the storage module receives the activation operation signal output by the logic module, the first operation value is determined as the accumulated value; wherein the control end of the first control output unit and the output of the logic module terminal is connected, the input terminal of the first control output unit is connected to the output terminal of the adder unit, the output terminal of the first control output unit is connected to the input terminal of the latch unit; the second control output A unit configured to determine the second operation value as the accumulated value when the latch module receives the periodic refresh signal; wherein the control end of the second control output unit is used to receive For the periodic refresh signal, the input terminal of the second control output unit is connected to the output terminal of the first subtraction unit, and the output terminal of the second control output unit is connected to the input terminal of the latch unit; The third control output unit is configured to determine the third operation value as the accumulated value when the latch module receives the
  • the decoding module is configured to receive a signal to be processed, decode the signal to be processed, and output the corresponding activation operation signal, the periodic refresh signal or the refresh management signal.
  • the logic module includes a NOT gate and an AND gate; wherein, the NOT gate is used to perform a NOT operation on the blocking signal to obtain an inverted blocking signal; and the AND gate is used to An AND operation is performed on the inverted blocking signal and the activation operation signal, and the activation operation signal is blocked or output according to the operation result.
  • the logic module includes an AND gate; the AND gate is used to perform an AND operation on the blocking signal and the activation operation signal, and block or output the activation operation signal according to the operation result.
  • the first preset value is n times the second preset value, n is greater than 1; the third preset value is m times the second preset value, m is greater than or equal to 1.
  • the method further includes: a mode register, configured to receive a mode selection signal; and determine a first operation code, a second operation code and a third operation code according to the mode selection signal; wherein the first operation code The code is used to indicate the multiple relationship between the first preset value and the second preset value, the second operation code is used to indicate the value of the second preset value, and the third operation code is used to indicate The multiple relationship between the third preset value and the second preset value; the generating module is also used to receive the first operation code, the second operation code and the third operation code; and according to the third operation code Two operation codes, determine the second preset value, determine the first preset value according to the first operation code and the second operation code, determine the first preset value according to the third operation code and the second operation code code to determine the third preset value.
  • a mode register configured to receive a mode selection signal; and determine a first operation code, a second operation code and a third operation code according to the mode selection signal; wherein the first operation code The code is used to indicate
  • embodiments of the present disclosure provide a signal control method, which method includes:
  • the cumulative number of execution times of the activation operation and determining the cumulative value include:
  • receiving the activation operation signal includes:
  • blocking the output of the activation operation signal when the accumulated value is greater than or equal to the first preset value includes:
  • performing a logical operation on the blocking signal and the activation operation signal to block the activation operation signal includes:
  • an embodiment of the present disclosure provides a semiconductor memory, which includes the signal control circuit as described in the first aspect.
  • Figure 1 is a schematic structural diagram of a signal control circuit provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of another signal control circuit provided by an embodiment of the present disclosure.
  • Figure 3A is a partial structural schematic diagram of a signal control circuit provided by an embodiment of the present disclosure.
  • Figure 3B is a partial structural schematic diagram of another signal control circuit provided by an embodiment of the present disclosure.
  • Figure 3C is a partial structural schematic diagram of yet another signal control circuit provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic flow chart of a signal control method provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic structural diagram of another signal control circuit provided by an embodiment of the present disclosure.
  • Figure 6 is a partial structural diagram of a decoding and logic module provided by an embodiment of the present disclosure.
  • Figure 7 is a partial structural diagram of a generation module provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic diagram 2 of a partial structure of a generation module provided by an embodiment of the present disclosure.
  • Figure 9 is a schematic diagram 3 of a partial structure of a generation module provided by an embodiment of the present disclosure.
  • Figure 10 is a schematic diagram 4 of a partial structure of a generation module provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a semiconductor memory provided by an embodiment of the present disclosure.
  • first ⁇ second ⁇ third involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understandable that "first ⁇ second ⁇ third” Where permitted, the specific order or sequence may be interchanged so that the embodiments of the disclosure described herein can be practiced in an order other than that illustrated or described herein.
  • DRAM Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • LPDDR Low Power Double Data Rate SDRAM
  • LPDDR5Specification LP5SPEC
  • Refresh management signal (refresh management)
  • Block signal (Block)
  • a Row Hammer attack refers to a certain word line in DRAM being repeatedly activated in a short period of time, which in turn causes data errors in memory cells in adjacent word lines.
  • the impact of the traveling hammer effect on DRAM is becoming more and more serious.
  • a signal control circuit including: a generation module, used to accumulate the number of execution times of the activation operation, and if the accumulated value is greater than or equal to the first preset value, output a blocking signal; a logic module, It is used to receive the activation operation signal and the blocking signal. If the blocking signal is received, the output of the activation operation signal is blocked; if the blocking signal is not received, the activation operation signal is output. In this way, the signal control circuit can accumulate the number of execution times of the activation operation. When the accumulated value is greater than or equal to the first preset value, it blocks the new activation operation signal by blocking the signal to avoid the recurrence of the activation operation and further alleviate the problem. Problems caused by Row Hammer attacks.
  • FIG. 1 shows a schematic structural diagram of a signal control circuit 10 provided by an embodiment of the present disclosure.
  • the signal control circuit 10 may include:
  • the generation module 11 is used to accumulate the number of execution times of the activation operation. If the accumulated value is greater than or equal to the first preset value, output a blocking signal;
  • the logic module 12 is used to receive the activation operation signal and the blocking signal. If the blocking signal is received, the output of the activation operation signal is blocked; if the blocking signal is not received, the activation operation signal is output.
  • the signal control circuit 10 of the embodiment of the present disclosure can be applied in various scenarios.
  • the signal control circuit 10 can be applied to a semiconductor memory to mitigate the impact of Row Hammer attacks. Subsequently, the signal control circuit 10 will be described in detail using DRAM as an application scenario, but this does not constitute a relevant limitation.
  • the activation operation signal is used to indicate activation operation on the corresponding word line in the DRAM.
  • the DRAM may include multiple signal control circuits 10 to handle activation operations of different storage areas respectively.
  • the signal control circuit 10 includes a generation module 11 and a logic module 12.
  • the generation module 11 can count the number of execution times of activation operations in a certain storage area in the DRAM. If the cumulative value is greater than or equal to the first preset value, it means that the The storage area may be subject to a Row Hammer attack, and a blocking signal is output to the logic module 12; at this time, even if the logic module 12 receives a new activation operation signal, it will not output the activation operation signal, thereby preventing the storage area from entering again.
  • the present disclosure divides the memory into several storage areas, monitors the number of activations of each storage area, and can use fewer counters to prevent the occurrence of line hammer attacks.
  • the blocking signal may be a high-level active signal.
  • the logic module 12 may include a NOT gate and an AND gate; wherein, the NOT gate is used to perform a NOT operation on the blocking signal to obtain an inverted blocking signal; and the AND gate is used to perform the inverting blocking signal and activate the The operation signal is ANDed, and the operation signal is blocked or outputted according to the operation result.
  • the blocking signal may be an active low signal.
  • the logic module 12 may only include an AND gate; wherein the AND gate is used to perform an AND operation on the blocking signal and the activation operation signal, and block or output the activation operation signal according to the operation result.
  • the generation module 11 is also used to receive the periodic refresh signal Refresh, the refresh management signal RFM, or the activation operation signal Active-2 output by the logic module; and,
  • the accumulated value is increased by one; when the periodic refresh signal Refresh is received, the accumulated value is subtracted from the second preset value; when the refresh management signal RFM is received, the accumulated value is value minus the third preset value.
  • the traditional periodic refresh signal Refresh is used to periodically refresh memory cells to prevent data loss.
  • LP5Spec also provides refresh management signal RFM to implement supplementary refresh to alleviate problems caused by Row Hammer attacks.
  • the periodic refresh signal Refresh refers to the regular refresh command in DRAM
  • the refresh management signal RFM refers to the additional refresh command generated after detecting that a Row Hammer may occur in the DRAM.
  • This disclosure provides a specific control scheme for the refresh operation: using a rolling accumulation counter (Rolling Accumulated, namely the generation module 11) to accumulate activation operations. Specifically, every time an activation operation signal Active is received, the cumulative value is incremented by one; every time a periodic refresh signal Refresh is received, the cumulative value is subtracted from the second preset value; every time a refresh management signal RFM is received, the cumulative value is subtracted by Go to the third preset. In this way, through the accumulated value, the execution of activation operations and refresh operations can be measured, and in the case of insufficient refresh operations, the refresh management signal RFM is generated to implement additional refresh processing to reduce the risk of line hammer attacks.
  • a rolling accumulation counter Rolling Accumulated, namely the generation module 11
  • both the periodic refresh signal Refresh and the refresh management signal RFM are used to instruct DRAM to perform refresh operations, which can alleviate the problems caused by Row Hammer. Therefore, after receiving the periodic refresh signal Refresh or the refresh management signal RFM, the corresponding storage area will be refreshed to reduce the risk of Row Hammer attacks.
  • the refresh operation will increase power consumption. As long as the refresh operation does not occur, it is not advisable to perform too many refresh operations. Therefore, in most cases, the cumulative value of the generation module 11 is always a positive number.
  • each of the first preset value/the second preset value/the third preset value can have multiple possible values, and the user can choose according to actual usage needs. Cope with different work scenarios.
  • the periodic refresh signal Refresh is performed regularly. If the cumulative value of the rolling accumulation counter is high and the execution time of the next periodic refresh signal Refresh has not yet reached, an additional refresh management signal RFM can be generated to supplement the execution time. Refresh operation. Based on such processing logic, it can be defined that the second preset value is equal to the third preset value. Furthermore, in order to bring better control effect, the second preset value can also be defined to be smaller than the third preset value.
  • the signal control circuit 10 may also include a mode register 14 for receiving a mode selection signal; and determining the first operation code, the second operation code and the third operation code according to the mode selection signal. ;
  • the first operation code is used to indicate the multiple relationship between the first preset value and the second preset value
  • the second operation code is used to indicate the value of the second preset value
  • the third operation code is used to indicate The multiple relationship between the third preset value and the second preset value
  • the generation module is also configured to receive the first operation code, the second operation code and the third operation code; and determine the second preset value according to the second operation code, and determine the first operation code according to the first operation code and the second operation code.
  • the preset value determines the third preset value according to the third operation code and the second operation code.
  • the signal control circuit 10 may also include a decoding module 13 for receiving the signal to be processed, decoding the signal to be processed, and outputting the corresponding activation operation signal Active-1, Periodic refresh signal Refresh or refresh management signal RFM.
  • the activation operation signal Active-1 refers to the signal received by the input terminal of the logic module 12
  • the activation operation signal Active-2 refers to the signal output by the output terminal of the logic module 12 .
  • the signal to be processed is generated by the front-end circuit and sent to the signal control circuit 10 to instruct the semiconductor memory to perform corresponding actions.
  • the generation module 11 may include a calculation module 112, a latch module 111 and a comparison module 113; wherein,
  • the calculation module 112 is used to perform calculation processing on the accumulated value to obtain the first calculation value, the second calculation value and the third calculation value;
  • the latch module 111 is used to receive the activation operation signal Active-2, the periodic refresh signal Refresh or the refresh management signal RFM, and based on the first operation value corresponding to the activation operation signal Active-2 and the second operation value corresponding to the periodic refresh signal Refresh , or refresh the third operation value corresponding to the management signal RFM to update the accumulated value; the latch module 111 is also used to store the updated accumulated value;
  • the comparison module 113 is used to compare the accumulated value with the first preset value. If the accumulated value is greater than or equal to the first preset value, output the blocking signal Block.
  • the input terminal of the calculation module 112 and the input terminal of the comparison module 113 are both connected to the output terminal of the latch module 111, and the output terminal of the calculation module 112 is connected to the input terminal of the latch module 111.
  • FIG. 3A shows a partial structural diagram of a signal control circuit 10 provided by an implementation of the present disclosure.
  • the calculation module 112 may include an addition unit 201, a first subtraction unit 202 and a second subtraction unit 203; wherein,
  • the addition unit 201 is used to add one to the accumulated value and output the first operation value
  • the first subtraction unit 202 is used to subtract the accumulated value and the second preset value, and output the second operation value;
  • the second subtraction unit 203 is used to perform subtraction processing on the accumulated value and the third preset value, and output a third operation value.
  • the latch module 111 may include a first control output unit 204, a second control output unit 205, a third control output unit 206 and a latch unit 207; wherein,
  • the first control output unit 204 is configured to receive the activation operation signal Active-2 and the first operation value output by the logic module 12; and in the case of receiving the activation operation signal Active-2, determine the first operation value as the accumulated value. ;
  • the second control output unit 205 is configured to receive the periodic refresh signal Refresh and the second operation value; and when the periodic refresh signal Refresh is received, determine the second operation value as the accumulated value;
  • the third control output unit 206 is configured to receive the refresh management signal RFM and the third operation value; and when the refresh management signal RFM is received, determine the third operation value as the accumulated value;
  • the output terminal of the latch unit 207 is used to output the accumulated value.
  • the calculation module 112 can simultaneously enable all calculation units (the addition unit 201, the first subtraction unit 202, the second subtraction unit 203) to perform corresponding calculations on the accumulated value, and obtain multiple operation values at the same time; the latch module 111 According to the specific signal received by the generation module 11 (activation operation signal Active-2, refresh management signal RFM or periodic refresh signal Refresh), one of the multiple operation values is selected to form a new cumulative value. In other words, only the latch module 111 needs to perform corresponding actions according to the specific signal received by the generating module 11 . In this way, the circuit complexity can be reduced and the number of signal terminals can be reduced.
  • the generation module 11 includes a calculation module 112, a latch module 111 and a comparison module 113; wherein,
  • the calculation module 112 is used to perform calculation processing on the accumulated value based on the activation operation signal Active-2, the periodic refresh signal Refresh or the refresh management signal RFM, and obtain the target calculation value;
  • the latch module 111 is used to update the cumulative value using the target operation value and store the updated cumulative value
  • the comparison module 113 is used to compare the accumulated value with the first preset value. If the accumulated value is greater than or equal to the first preset value, output the blocking signal Block.
  • the calculation module 112 may include an addition unit 201, a first subtraction unit 202 and a second subtraction unit 203; wherein,
  • the addition unit 201 is used to receive the activation operation signal Active-2 and the accumulated value output by the logic module; when receiving the activation operation signal Active-2, add one to the accumulated value and output the target operation value;
  • the first subtraction unit 202 is configured to receive the periodic refresh signal Refresh and the accumulated value; and when receiving the periodic refresh signal Refresh, perform subtraction processing on the accumulated value and the second preset value, and output the target operation value;
  • the second subtraction unit 203 is configured to receive the refresh management signal RFM and the accumulated value; and when receiving the refresh management signal RFM, perform subtraction processing on the accumulated value and the third preset value, and output the target operation value.
  • the latch module 111 is configured to receive the target operation value and update the accumulated value using the target operation value.
  • the calculation module 112 can correspondingly control the addition unit 201/first subtraction unit 202/th according to the specific signal received by the generation module 11 (activation operation signal Active-2, refresh management signal RFM or periodic refresh signal Refresh).
  • the specific signal received by the generation module 11 activation operation signal Active-2, refresh management signal RFM or periodic refresh signal Refresh.
  • One of the two subtraction units 203 performs a corresponding operation to obtain a target operation value; the latch module 111 uses the target operation value to update the accumulated value.
  • the calculation module 112 needs to perform corresponding actions according to the specific signals received by the generation module 11, and only one calculation unit performs calculation processing at a time, which can improve the working efficiency of the circuit.
  • the generation module 11 includes a calculation module 112, a latch module 111 and a comparison module 113; wherein,
  • the calculation module 112 is configured to perform corresponding calculation processing on the accumulated value based on the activation operation signal Active-2, the periodic refresh signal Refresh or the refresh management signal RFM, and obtain the first operation value corresponding to the activation operation signal Active-2 and the periodic refresh signal.
  • the latch module 111 is used to receive the activation operation signal Active-2, the periodic refresh signal Refresh or the refresh management signal RFM; when receiving the activation operation signal Active-2, update the accumulated value using the first operation value; when receiving the periodic refresh When the Refresh signal is generated, the second operation value is used to update the accumulated value; when the refresh management signal RFM is received, the accumulated value is updated using the third operation value; the latch module 111 is also used to store the updated accumulated value;
  • the comparison module 113 is used to compare the accumulated value with the first preset value. If the accumulated value is greater than or equal to the first preset value, output the blocking signal Block.
  • the calculation module 112 may include an addition unit 201, a first subtraction unit 202 and a second subtraction unit 203; wherein,
  • the addition unit 201 is used to add one to the accumulated value and output the first operation value when the calculation module 112 receives the activation operation signal Active-2 output by the logic module 12;
  • the first subtraction unit 202 is configured to subtract the accumulated value and the second preset value and output the second operation value when the calculation module 112 receives the periodic refresh signal Refresh;
  • the second subtraction unit 203 is configured to subtract the accumulated value and the third preset value and output a third operation value when the calculation module 112 receives the refresh management signal RFM.
  • the latch module 111 may include a first control output unit 204, a second control output unit 205, a third control output unit 206 and a latch unit 207; wherein,
  • the first control output unit 204 is used to determine the first operation value as the accumulated value when the latch module 111 receives the activation operation signal Active-2 output by the logic module 12; wherein, the control of the first control output unit 204 The terminal is connected to the output terminal of the logic module 12, the input terminal of the first control output unit 204 is connected to the output terminal of the adder unit 201, and the output terminal of the first control output unit 204 is connected to the input terminal of the latch unit 207;
  • the second control output unit 205 is used to determine the second operation value as the accumulated value when the latch module 111 receives the periodic refresh signal Refresh; wherein, the control end of the second control output unit 205 is used to receive the periodic refresh signal.
  • Signal Refresh the input terminal of the second control output unit 205 is connected to the output terminal of the first subtraction unit 202, and the output terminal of the second control output unit 205 is connected to the input terminal of the latch unit 207;
  • the third control output unit 206 is used to determine the third operation value as the accumulated value when the latch module 111 receives the refresh management signal RFM; wherein, the control end of the third control output unit 206 is used to receive the refresh management signal.
  • signal RFM the input terminal of the third control output unit 206 is connected to the output terminal of the second subtraction unit 203, and the output terminal of the third control output unit 206 is connected to the input terminal of the latch unit 207;
  • the output terminal of the latch unit 207 is used to output the accumulated value.
  • the latch unit 207 can be an active output, that is, the latch unit 207 continuously outputs the signal received at the input end as an accumulated value; or the latch unit 207 can be a passive output, that is, when After the control end of the latch unit 207 receives the request instruction from other circuit units, the latch unit 207 outputs the signal received at the input end to form an accumulated value.
  • the calculation module 112 needs to activate the corresponding calculation unit (addition signal).
  • the unit 201, the first subtraction unit 202 or the second subtraction unit 203) performs corresponding calculations on the accumulated value to obtain the corresponding operation value;
  • the latch module 111 also calculates the calculation module according to the specific signal received by the generation module 11
  • the operation value output by 112 is determined as the new accumulated value.
  • both the calculation module 112 and the latch module 111 need to perform corresponding actions according to the specific signals received by the generation module 11, which can avoid useless calculation processes and reduce circuit energy consumption.
  • the above three embodiment methods can also be further superimposed and adjusted according to the actual physical devices used.
  • certain calculation units such as the first subtraction unit 202 or the second subtraction unit 203 are always enabled to calculate the accumulated value
  • the generation module 11 receives a certain signal (such as the activation operation signal Active- 2), enable the corresponding calculation unit (such as the addition unit 201) to calculate the accumulated value, and so on.
  • the signal control circuit provided by the embodiment of the present disclosure, when the activation operation is repeatedly performed in a certain storage area and the refresh operation is not performed in time, the new activation operation signal can be blocked to avoid performing the new activation operation again, thereby avoiding Hammer effect.
  • This embodiment provides a signal control circuit, including: a generation module, used to accumulate the number of execution times of the activation operation, and if the accumulated value is greater than or equal to the first preset value, output a blocking signal; a logic module, used to receive the activation Operation signal and blocking signal. If the blocking signal is received, the output of the activation operation signal is blocked; if the blocking signal is not received, the activation operation signal is output.
  • the signal control circuit can accumulate the number of execution times of the activation operation, and when the accumulated value is greater than or equal to the first preset value, block the new activation operation signal by blocking the signal, and avoid the activation operation again before completing the refresh operation. occurs, which can further alleviate the problems caused by Row Hammer attacks.
  • FIG. 4 shows a schematic flowchart of a signal control method provided by an embodiment of the present disclosure. As shown in Figure 4, the method may include:
  • S301 Receive activation operation signal.
  • the signal control method is applied to the aforementioned signal control circuit 10, which can alleviate the problems caused by Row Hammer attacks in dynamic random access memories.
  • the activation operation signal is used to indicate activation operation on the corresponding word line.
  • receiving the activation operation signal may include:
  • the signal to be processed is decoded to obtain the corresponding activation operation signal, periodic refresh signal or refresh management signal.
  • S302 Accumulate the number of execution times of the activation operation and determine the cumulative value.
  • step S301 there is no sequence between step S301 and step S302.
  • step S302 is a continuously executed process, and step S301 occurs during step S302.
  • the cumulative value refers to the actual number of executions of active operations in a certain storage area in DRAM. That is to say, the cumulative value is determined by conducting continuous statistics on the actual execution of the activated operations in the storage area. After receiving the activation operation signal, the activation operation signal needs to be subsequently processed based on the accumulated value collected in real time.
  • accumulating the number of executions of the activation operation and determining the cumulative value may include:
  • the accumulated value still needs to be determined to determine whether to perform the activation operation.
  • the cumulative value is greater than or equal to the first preset value, that is, the actual number of executions of activation operations in a certain storage area exceeds the normal range, indicating that the storage area may be subject to a Row Hammer attack, then new receptions will be blocked.
  • the activation operation signal received prevents the storage area from performing new activation operations and prevents data loss caused by Row Hammer attacks.
  • the cumulative value is less than the first preset value, then the actual number of executions of the activation operation in the storage area is still within the normal range. After receiving the new activation operation signal, the normal activation operation will be performed without affecting the semiconductor memory. normal function.
  • each of the first preset value/second preset value/third preset value can have multiple possible values, and the user can flexibly adjust according to actual usage needs to cope with different working scenarios. .
  • blocking of the activation operation signal can be achieved by blocking the signal.
  • the blocking of the output of the activation operation signal may include:
  • the blocking signal may be an active high signal. Therefore, logical operations are performed on the blocking signal and the activating operation signal to realize blocking the activating operation signal, which may include:
  • phase blocking signal performs an AND operation on the inverted blocking signal and the activation operation signal, and outputs the activation operation signal according to the operation result.
  • the blocking signal may be an active low signal. Therefore, performing logical operations on the blocking signal and the activating operation signal to realize blocking the activating operation signal may include:
  • Embodiments of the present disclosure provide a signal control method, including: receiving an activation operation signal; accumulating the number of executions of the activation operation to determine a cumulative value; and blocking the activation operation signal when the cumulative value is greater than or equal to a first preset value. output; when the accumulated value is less than the first preset value, an activation operation signal is output.
  • the number of execution times of the activation operation is accumulated, and when the accumulated value is greater than or equal to the first preset value, the new activation operation signal is blocked by blocking the signal, and the recurrence of the activation operation is avoided before the refresh operation is completed, which can further Mitigate problems caused by Row Hammer attacks.
  • FIG. 5 shows a schematic structural diagram of yet another signal control circuit 10 provided by an embodiment of the present disclosure.
  • the signal control circuit 10 may include a generation module 11 , a decoding and logic module 41 and a mode register 14 .
  • the generation module 11 is used to accumulate the number of execution times of the activation operation to obtain a cumulative value. Specifically, when the generation module 11 receives the activation operation signal Active-2, it adds one to the accumulated value; when the generation module 11 receives the periodic refresh signal Refresh, it subtracts the second preset value from the accumulated value; when generating When the module 11 receives the refresh management signal RFM, it subtracts the third preset value from the accumulated value. In addition, after the accumulated value is greater than or equal to the first preset value, the generation module 11 outputs the blocking signal Block to the decoding and logic module 41 .
  • the decoding and logic module 41 is mainly used for decoding the signal to be processed; in addition, when the signal to be processed is decoded to obtain the activation operation signal Active-1, if the blocking signal Block is not received, the activation operation The signal Active-1 is output to instruct a certain storage area to perform a normal activation operation; if the blocking signal Block is received, the activation operation signal Active-1 is blocked to prevent a certain storage area from performing an activation operation again. Thereby mitigating the problems caused by Row Hammer attacks.
  • the decoding and logic module 41 can be regarded as the entirety of the decoding module 13 and the logic module 12 in FIG. 2 .
  • the mode register 14 provides the first operation code RAAMult ⁇ 1:0>, the second operation code RAAIMT ⁇ 4:0> and the third operation code RAADec ⁇ 1:0> to the generation module 11.
  • the first operation code RAAMult ⁇ 1:0> and the second operation code RAAIMT ⁇ 4:0> are used to determine the first preset value
  • the second operation code RAAIMT ⁇ 4:0> is used to determine the second preset value.
  • the third opcode RAADec ⁇ 1:0> and the second opcode RAAIMT ⁇ 4:0> are used to determine the third preset value.
  • the decoding and logic module 41 includes an activation instruction decoding unit 411 , a NOT gate 412 and an AND gate 413 .
  • the activation instruction decoding unit 411 is used to receive the signal to be processed, and if the decoding is successful, the activation operation signal Active-1 is obtained; the input terminal of the NOT gate 412 is connected to the blocking signal Block, and the input terminal of the AND gate 413 is connected to the blocking signal Block.
  • the two input terminals are respectively connected to the output terminal of the activation instruction decoding unit 411 and the output terminal of the NOT gate 412.
  • the output of the AND gate 413 is always at a low level, thereby blocking the activation operation signal Active-1; when the blocking signal Block is in a low-level state, The output of the AND gate 413 changes along with the activation operation signal Active-1, so that the activation operation signal Active-1 is output, and the activation operation signal Active-2 is obtained.
  • the decoding and logic module 41 also includes a periodic refresh instruction decoding unit and a refresh management instruction decoding unit.
  • the periodic refresh instruction decoding unit is used to decode the signal to be processed, and obtain the periodic refresh signal Refresh if the decoding is successful; and the refresh management instruction decoding unit is used to decode the signal to be processed, and obtain the periodic refresh signal Refresh. If the decoding is successful, the refresh management signal RFM is obtained.
  • the accumulated value is composed of a set of data Out ⁇ n>, Out ⁇ n-1>...Out ⁇ 0>, expressed as Out ⁇ n: 0>.
  • the generation module 11 may include n+1 generation sub-modules 42, respectively used to determine Out ⁇ n>, Out ⁇ n-1>...Out ⁇ 0>.
  • FIG. 7 a schematic diagram 1 of a partial structure of a generation module 11 provided by an embodiment of the present disclosure is shown. Specifically, FIG. 7 shows a schematic structural diagram of a generation sub-module 42. As shown in FIG. 7 , the generation sub-module 42 may at least include an adder 421 , a flip-flop 422 and a latch sub-module 423 .
  • the input end of the adder 421 is used to receive Out ⁇ n> and carry signal C ⁇ n-1>.
  • the carry signal C ⁇ n-1> is generated by the corresponding generation sub-module of Out ⁇ n-1>. generated by the adder (not shown in the figure); the output terminal of the adder 421 is used to output carry signals C ⁇ n> and Out ⁇ n>.
  • the adder 421 can be implemented by an XOR half adder, that is, if the input terminals of the adder 421 are the same, a low-level signal is output; if the input terminals of the adder 421 are different, a high-level signal is output.
  • the input end of the adder 421 in the generation sub-module corresponding to Out ⁇ 0> can be used to receive the Out ⁇ 0> and the counting trigger signal output by the latch sub-module, and output Out ⁇ 0> and C ⁇ 0 >, and the Out ⁇ 0> output by the adder 421 subsequently enters the flip-flop 422 and the latch sub-module 423.
  • the counting trigger signal can use the activation operation signal Active-2 or a high level signal.
  • the input terminal of the flip-flop 422 is used to receive the Out ⁇ n> output by the adder 421, the control terminal of the flip-flop 422 is used to receive the activation operation signal Active-2, and the output terminal of the flip-flop 422 is used to output ActS ⁇ n>.
  • ActS ⁇ n> refers to the n+1th bit of data in the aforementioned first operation value.
  • n+1 adders 421 and n+1 flip-flops 422 together constitute the adding unit 201 in FIG. 3C.
  • the n+1th bit data in the second operation value can be represented by RfshS ⁇ n>
  • the n+1th bit data in the third operation value can be represented by RfmS ⁇ n>.
  • FIG. 8 shows a partial structural schematic diagram 2 of a generation module 11 provided by an embodiment of the present disclosure.
  • the generation module 11 may also include a first subtractor 43 (equivalent to the first subtraction unit 202 in FIG. 3C ) and a second subtractor 44 (equivalent to the second subtraction unit 203 in FIG. 3C ).
  • the input of the first subtractor 43 is Out ⁇ n:0> and the second preset value (expressed by RAAIMT).
  • RfshS ⁇ n By subtracting Out ⁇ n:0> and the second preset value, RfshS ⁇ n is obtained :0>.
  • the input of the second subtractor 44 is Out ⁇ n:0> and the third preset value (expressed by RAAIMT*RAADec).
  • RfmS ⁇ n By subtracting Out ⁇ n:0> and the third preset value, RfmS ⁇ n is obtained :0>.
  • the n+1th bit of data in RfshS ⁇ n:0> is the aforementioned RfshS ⁇ n>
  • the n+1th bit of data in RfmS ⁇ n:0> is the aforementioned RfmS ⁇ n>.
  • the latch submodule 423 is used to output ActS ⁇ n> to obtain Out ⁇ n> when the activation operation signal Active-2 is received; when the periodic refresh signal Refresh is received, RfshS ⁇ n> Output to get Out ⁇ n>; when the refresh management signal RFM is received, RfmS ⁇ n> is output to get Out ⁇ n>.
  • FIG. 9 a partial structural diagram 3 of a generation module 11 provided by an embodiment of the present disclosure is shown.
  • FIG. 9 is a schematic structural diagram of the latch sub-module 423.
  • the latch sub-module 423 includes a first control output sub-unit 4231, a second control output sub-unit 4232, a third control output sub-unit 4233 and a latch sub-unit 4234.
  • the input terminal of the first control output subunit 4231 receives ActS ⁇ n>, and its control terminal receives the activation operation signal Active-2, and is used to output ActS ⁇ n> to the lock when the activation operation signal Active-2 is received.
  • Storage subunit 4234; the input end of the second control output subunit 4232 receives RfshS ⁇ n>, and its control end receives the periodic refresh signal Refresh, and is used to output RfshS ⁇ n> to Latch subunit 4234; the input end of the third control output subunit 4233 receives RfmS ⁇ n>, and its control end receives the refresh management signal RFM, which is used to output RfmS ⁇ n> when the refresh management signal RFM is received.
  • the latch subunit 4234; the latch subunit 4234 mainly plays the role of signal retention and is used to output the received signal to obtain Out ⁇ n>.
  • n+1 first control output sub-units 4231 together constitute the first control output unit 204 in Figure 3C
  • n+1 second control output sub-units 4232 together constitute the second control output unit 205 in Figure 3C
  • n+1 third control output sub-units 4233 together constitute the third control output unit 206 in Figure 3C
  • n+1 latch sub-units 4234 together constitute the latch unit 207 in Figure 3C.
  • the first control output sub-unit 4231, the second control output sub-unit 4232 and the third control output sub-unit 4233 have the same structure, each consisting of a three-state buffer, and the latch sub-unit 4234 consists of two end-to-end connected The buffer composition.
  • the generation module 11 also includes a comparator 45 (equivalent to the comparison module 113 in Figure 2).
  • the comparator 45 is used to receive the accumulated value Out ⁇ n:0> and the first preset value (using RAAIMT* RAAMult represents), and when the accumulated value Out ⁇ n:0> is greater than or equal to the first preset value, the blocking signal Block is output.
  • Figure 5 and Figure 6 show the working principle block diagram of the entire signal control circuit 10: First, for the generation module 11, when receiving the activation operation signal Active-2, the accumulated value is increased by one, or When the periodic refresh signal Refresh is received, the accumulated value is subtracted from the second preset value (provided by the mode register 14), or when the refresh management signal RFM is received, the accumulated value is subtracted from the second preset value (provided by the mode register 14). Three preset values; during the operation of the signal control circuit 10, if the accumulated value of the generation module 11 reaches the first preset value (provided by the mode register 14), then a blocking signal is output to block the new activation operation signal. .
  • Figures 7 to 10 are schematic structural diagrams of the generation module 11 implemented using devices such as adders, subtractors, and multi-bit latches.
  • the adder will be used to calculate the cumulative number of times the activation operation signal Active-2 is received to determine the first operation value, and the first subtractor 43 will calculate the current cumulative value minus the second preset value in real time to determine For the second operation value, the second subtractor 44 will calculate the current accumulated value minus the third preset value in real time to determine the third operation value.
  • the latch sub-module 423 is used to determine the third operation value according to the received activation operation signal Active-2,
  • the periodic refresh signal Refresh or the refresh management signal RFM latches the first operation value corresponding to the activation operation signal Active-2, the second operation value corresponding to the periodic refresh signal Refresh or the third operation value corresponding to the refresh management signal RFM; comparator 45
  • the current accumulated value and the first preset value will be compared in real time to generate a blocking signal Block.
  • the embodiment of the present disclosure provides a signal control circuit.
  • the specific implementation of the foregoing embodiment is explained in detail through this embodiment. It can be seen that the signal control circuit can accumulate the number of execution times of the activation operation, and when the accumulated value is greater than Or equal to the first preset value, blocking the new activation operation signal by blocking the signal, avoiding the recurrence of the activation operation before completing the refresh operation, can alleviate the problems caused by the Row Hammer attack.
  • Figure 11 shows a schematic structural diagram of a semiconductor memory 50 provided by an embodiment of the present disclosure.
  • the semiconductor memory 50 may include the signal control circuit 10 of any of the foregoing embodiments to alleviate the problems caused by Row Hammer attacks.
  • Embodiments of the present disclosure provide a signal control circuit, a signal control method, and a semiconductor memory.
  • the signal control circuit includes: a generating module configured to accumulate the number of execution times of the activation operation. If the accumulated value is greater than or equal to the first preset value, then Output the blocking signal; the logic module is used to receive the activation operation signal and the blocking signal. If the blocking signal is received, the output of the activation operation signal is blocked; if the blocking signal is not received, the activation operation signal is output. In this way, the signal control circuit can accumulate the number of execution times of the activation operation. When the accumulated value is greater than or equal to the first preset value, it blocks the new activation operation signal by blocking the signal to avoid the recurrence of the activation operation and alleviate the traffic congestion. Problems caused by hammer attacks.

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Abstract

一种信号控制电路（10）、信号控制方法和半导体存储器，该信号控制电路（10）包括：生成模块（11），用于累计激活操作的执行次数，若累计值大于或等于第一预设值，则输出阻断信号；逻辑模块（12），用于接收激活操作信号和阻断信号，若接收到阻断信号，则阻断激活操作信号的输出；若未收到阻断信号，则输出激活操作信号。这样，信号控制电路能够对激活操作的执行次数进行累计，在累计值大于或等于第一预设值时，通过阻断信号阻断新的激活操作信号，避免激活操作的再次发生，能够缓解行锤攻击带来的问题。

Description

信号控制电路、信号控制方法和半导体存储器
相关申请的交叉引用
本公开要求在2022年04月29日提交中国专利局、申请号为202210475197.9、申请名称为“一种信号控制电路、信号控制方法和半导体存储器”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限于一种信号控制电路、信号控制方法和半导体存储器。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成，且不同的存储单元需要经由字线和位线进行选中操作。也就是说，DRAM中存在大量字线，这些字线相邻排列，在某一字线受到行锤效应(Row Hammer)时，与该字线相邻的字线上的存储单元可能会产生数据错误。目前，一般通过在周期刷新的基础上进行补充刷新操作来解决行锤效应带来的问题。但是，以上机制并不能完全避免行锤效应带来的影响，仍然可能由于Row Hammer攻击而出现数据错误。
发明内容
本公开的技术方案是这样实现的：
第一方面，本公开实施例提供了一种信号控制电路，包括：
生成模块，用于累计激活操作的执行次数，若累计值大于或等于第一预设值，则输出阻断信号；
逻辑模块，用于接收激活操作信号和所述阻断信号，若接收到所述阻断信号，则阻断所述激活操作信号的输出；若未收到所述阻断信号，则输出所述激活操作信号。
在一些实施例中，所述生成模块，还用于接收周期刷新信号、刷新管理信号或所述逻辑模块输出的激活操作信号；以及，在接收到所述激活操作信号时，对所述累计值进行加一操作；在接收到所述周期刷新信号时，将所述累计值减去第二预设值；在接收到所述刷新管理信号时，将所述累计值减去第三预设值。
在一些实施例中，所述生成模块包括计算模块、锁存模块和比较模块；其中，所述计算模块，用于对所述累计值进行运算处理，得到第一运算值、第二运算值和第三运算值；所述锁存模块，用于接收所述激活操作信号、所述周期刷新信号或所述刷新管理信号，并基于所述激活操作信号对应的所述第一运算值、所述周期刷新信号对应的所述第二运算值、或所述刷新管理信号对应的所述第三运算值更新所述累计值；所述锁存模块还用于存储更新后的所述累计值； 所述比较模块，用于比较所述累计值和第一预设值，若所述累计值大于或等于第一预设值，则输出所述阻断信号。
在一些实施例中，所述生成模块包括计算模块、锁存模块和比较模块；其中，所述计算模块，用于基于所述激活操作信号、所述周期刷新信号或所述刷新管理信号，对所述累计值进行运算处理，得到目标运算值；所述锁存模块，用于利用所述目标运算值更新所述累计值，并存储更新后的所述累计值；所述比较模块，用于比较所述累计值和第一预设值，若所述累计值大于或等于第一预设值，则输出所述阻断信号。
在一些实施例中，所述生成模块包括计算模块、锁存模块和比较模块；其中，所述计算模块，用于基于所述激活操作信号、所述周期刷新信号或所述刷新管理信号，对所述累计值进行对应的运算处理，得到所述激活操作信号对应的第一运算值、所述周期刷新信号对应的第二运算值或所述刷新管理信号对应的第三运算值；所述锁存模块，用于接收所述激活操作信号、所述周期刷新信号或所述刷新管理信号；在接收到所述激活操作信号时，利用所述第一运算值更新所述累计值；在接收到所述周期刷新信号时，利用所述第二运算值更新所述累计值；在接收到所述刷新管理信号时，利用所述第三运算值更新所述累计值；所述锁存模块还用于存储更新后的所述累计值；所述比较模块，用于比较所述累计值和第一预设值，若所述累计值大于或等于第一预设值，则输出所述阻断信号。
在一些实施例中，所述计算模块包括加法单元、第一减法单元和第二减法单元；其中，所述加法单元，用于在所述计算模块接收到所述逻辑模块输出的激活操作信号的情况下，对所述累计值进行加一处理，输出第一运算值；所述第一减法单元，用于在所述计算模块接收到所述周期刷新信号的情况下，对所述累计值和所述第二预设值进行减法处理，输出第二运算值；所述第二减法单元，用于在所述计算模块接收到所述刷新管理信号的情况下，对所述累计值和所述第三预设值进行减法处理，输出第三运算值。
在一些实施例中，所述锁存模块包括第一控制输出单元、第二控制输出单元、第三控制输出单元和锁存单元；其中，所述第一控制输出单元，用于在所述锁存模块接收到所述逻辑模块输出的激活操作信号的情况下，将所述第一运算值确定为所述累计值；其中，所述第一控制输出单元的控制端与所述逻辑模块的输出端连接，所述第一控制输出单元的输入端与所述加法单元的输出端连接，所述第一控制输出单元的输出端与所述锁存单元的输入端连接；所述第二控制输出单元，用于在所述锁存模块接收到所述周期刷新信号的情况下，将所述第二运算值确定为所述累计值；其中，所述第二控制输出单元的控制端用于接收所述周期刷新信号，所述第二控制输出单元的输入端与所述第一减法单元的输出端连接，所述第二控制输出单元的输出端与所述锁存单元的输入端连接；所述第三控制输出单元，用于在所述锁存模块接收到所述刷新管理信号的情况下，将所述第三运算值确定为所述累计值；其中，所述第三控制输出单元的控制端用于接收所述刷新管理信号，所述第三控制输出单元的输入端与所述第二减法单元的输出端连接，所述第三控制输出单元的输出端与所述锁存单元的输 入端连接；所述锁存单元的输出端用于输出所述累计值。
在一些实施例中，译码模块，用于接收待处理信号，并对所述待处理信号进行译码处理，输出对应的所述激活操作信号、所述周期刷新信号或所述刷新管理信号。
在一些实施例中，所述逻辑模块包括非门和与门；其中，所述非门，用于对所述阻断信号进行非运算，得到反相阻断信号；所述与门，用于对所述反相阻断信号和所述激活操作信号进行与运算，根据运算结果阻断或输出所述激活操作信号。
在一些实施例中，所述逻辑模块包括与门；所述与门，用于对所述阻断信号和所述激活操作信号进行与运算，根据运算结果阻断或输出所述激活操作信号。
在一些实施例中，所述第一预设值是所述第二预设值的n倍，n大于1；所述第三预设值是所述第二预设值的m倍，m大于或等于1。
在一些实施例中，还包括：模式寄存器，用于接收模式选择信号；并根据所述模式选择信号，确定第一操作码、第二操作码和第三操作码；其中，所述第一操作码用于指示第一预设值与所述第二预设值之间的倍数关系，所述第二操作码用于指示所述第二预设值的取值，第三操作码用于指示第三预设值与所述第二预设值之间的倍数关系；所述生成模块，还用于接收所述第一操作码、第二操作码和第三操作码；并根据所述第二操作码，确定所述第二预设值，根据所述第一操作码和所述第二操作码，确定所述第一预设值，根据所述第三操作码和所述第二操作码，确定第三预设值。
第二方面，本公开实施例提供了一种信号控制方法，该方法包括：
接收激活操作信号；
累计激活操作的执行次数，确定累计值；在所述累计值大于或等于第一预设值的情况下，阻断所述激活操作信号的输出；在所述累计值小于第一预设值的情况下，输出所述激活操作信号。
在一些实施例中，所述累计激活操作的执行次数，确定累计值，包括：
接收周期刷新信号、刷新管理信号或者输出后的所述激活操作信号；在接收到输出后的所述激活操作信号时，对所述累计值进行加一操作；在接收到所述周期刷新信号时，将所述累计值减去第二预设值；在接收到所述刷新管理信号时，将所述累计值减去第三预设值。
在一些实施例中，所述接收激活操作信号，包括：
接收待处理信号；对所述待处理信号进行译码处理，得到对应的所述激活操作信号、所述周期刷新信号或所述刷新管理信号。
在一些实施例中，所述在所述累计值大于或等于第一预设值的情况下，阻断所述激活操作信号的输出，包括：
比较所述累计值和所述第一预设值，若所述累计值大于或等于所述第一预设值，则输出阻断信号；对所述阻断信号和所述激活操作信号进行逻辑运算，根据运算结果阻断所述激活操作信号。
在一些实施例中，所述对所述阻断信号和所述激活操作信号进行逻辑运算， 以实现阻断所述激活操作信号，包括：
对所述阻断信号进行非运算，并输出反相阻断信号；对所述反相阻断信号和所述激活操作信号进行与运算，根据运算结果阻断所述激活操作信号；或者对所述反相阻断信号和所述激活操作信号进行与运算，根据运算结果输出所述激活操作信号。
第三方面，本公开实施例提供了一种半导体存储器，该半导体存储器包括如第一方面所述的信号控制电路。
附图说明
图1为本公开实施例提供的一种信号控制电路的组成结构示意图；
图2为本公开实施例提供的另一种信号控制电路的组成结构示意图；
图3A为本公开实施例提供的一种信号控制电路的局部结构示意图；
图3B为本公开实施例提供的另一种信号控制电路的局部结构示意图；
图3C为本公开实施例提供的又一种信号控制电路的局部结构示意图；
图4为本公开实施例提供的一种信号控制方法的流程示意图；
图5为本公开实施例提供的又一种信号控制电路的组成结构示意图；
图6为本公开实施例提供的一种译码及逻辑模块的局部结构示意图；
图7为本公开实施例提供的一种生成模块的局部结构示意图一；
图8为本公开实施例提供的一种生成模块的局部结构示意图二；
图9为本公开实施例提供的一种生成模块的局部结构示意图三；
图10为本公开实施例提供的一种生成模块的局部结构示意图四；
图11为本公开实施例提供的一种半导体存储器的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅仅用于解释相关申请，而非对该申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关申请相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅是用于区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
以下为本公开实施例中涉及到的专业名词解释以及部分名词的对应关系：
动态随机存取存储器(Dynamic Random Access Memory，DRAM)
同步动态随机存取存储器(Synchronous Dynamic Random Access Memory，SDRAM)
低功耗双倍数据速率内存(Low Power Double Data Rate SDRAM，LPDDR)
第5代LPDDR标准(LPDDR5Specification，LP5SPEC)
行锤(Row Hammer)
激活操作信号(Active)
周期刷新信号(Refresh)
刷新管理信号(refresh management)
阻断信号(Block)
模式寄存器(Mode Register，MR)
可以理解，Row Hammer攻击是指DRAM中某一字线在短时间内被反复激活，进而导致相邻字线中的存储单元产生数据错误。目前，随着工艺的演进，行锤效应给DRAM带来的影响愈发严重。
基于此，本公开实施例提供了一种信号控制电路，包括：生成模块，用于累计激活操作的执行次数，若累计值大于或等于第一预设值，则输出阻断信号；逻辑模块，用于接收激活操作信号和阻断信号，若接收到阻断信号，则阻断激活操作信号的输出；若未收到阻断信号，则输出激活操作信号。这样，信号控制电路能够对激活操作的执行次数进行累计，在累计值大于或等于第一预设值时，通过阻断信号阻断新的激活操作信号，避免激活操作的再次发生，能够进一步缓解Row Hammer攻击带来的问题。
下面将结合附图对本公开各实施例进行详细说明。
在本公开的一实施例中，参见图1，其示出了本公开实施例提供的一种信号控制电路10的组成结构示意图。如图1所示，该信号控制电路10可以包括：
生成模块11，用于累计激活操作的执行次数，若累计值大于或等于第一预设值，则输出阻断信号；
逻辑模块12，用于接收激活操作信号和阻断信号，若接收到阻断信号，则阻断激活操作信号的输出；若未收到阻断信号，则输出激活操作信号。
需要说明的是，本公开实施例的信号控制电路10可以应用于多种场景中。示例性的，信号控制电路10可以应用于半导体存储器，以缓解Row Hammer攻击带来的影响。后续以DRAM为应用场景，对信号控制电路10进行具体说明，但这并不构成相关限定。
在这里，激活操作信号用于指示对DRAM中相应的字线进行激活操作。
需要说明的是，DRAM中可以包括多个信号控制电路10，分别针对不同存储区域的激活操作进行处置。具体地，信号控制电路10包括生成模块11和逻辑模块12，生成模块11可以对DRAM中某一存储区域中激活操作的执行次数进行计数，若累计值大于或等于第一预设值，说明该存储区域可能遭受到Row Hammer攻击，则向逻辑模块12输出阻断信号；此时，即使逻辑模块12接收到新的激活操作信号，也不会输出该激活操作信号，从而避免该存储区域中再次执行新的激活操作，只有该存储区域进行刷新操作之后，才能进行正常的激 活操作，避免由于Row Hammer攻击造成的数据错误。相对于监控每条字线的激活次数，本公开将存储器划分成若干存储区域，对每个存储区域的激活次数进行监控，可以用更少的计数器，以预防行锤攻击的发生。
需要说明的是，在一些实施例中，阻断信号可以为高电平有效信号。示例性的，逻辑模块12可以包括非门和与门；其中，非门，用于对阻断信号进行非运算，得到反相阻断信号；与门，用于对反相阻断信号和激活操作信号进行与运算，根据运算结果阻断或输出激活操作信号。
在一些实施例中，阻断信号可以为低电平有效信号。示例性的，逻辑模块12可以仅包括与门；其中，与门用于对阻断信号和激活操作信号进行与运算，根据运算结果阻断或输出激活操作信号。
在一些实施例中，如图2所示，生成模块11，还用于接收周期刷新信号Refresh、刷新管理信号RFM或逻辑模块输出的激活操作信号Active-2；以及，
在接收到激活操作信号Active-2时，对累计值进行加一操作；在接收到周期刷新信号Refresh时，将累计值减去第二预设值；在接收到刷新管理信号RFM时，将累计值减去第三预设值。
需要说明的是，在DRAM中，传统的周期刷新信号Refresh用于对存储单元进行周期性刷新，防止数据丢失。另外，LP5Spec还提供了刷新管理信号RFM来实现补充刷新，以缓解Row Hammer攻击带来的问题。换句话说，周期刷新信号Refresh是指DRAM中的常规刷新命令，刷新管理信号RFM是指在检测到DRAM可能发生Row Hammer后产生的额外的刷新命令。
本公开提供了刷新操作的具体控制方案：利用一个滚动累加计数器(Rolling Accumulated，即生成模块11)对激活操作进行累计。具体地，每接收到一个激活操作信号Active，累计值加一；每接收到一个周期刷新信号Refresh，将累计值减去第二预设值；每接收到一个刷新管理信号RFM，将累计值减去第三预设值。这样，通过累计值，可以衡量激活操作和刷新操作的执行情况，并在刷新操作不足的情况下，产生刷新管理信号RFM以实现额外的刷新处理，以降低遭受行锤攻击的风险。
换句话说，周期刷新信号Refresh和刷新管理信号RFM均用于指示DRAM进行刷新操作，能够缓解Row Hammer带来的问题。因此，在接收到周期刷新信号Refresh或者刷新管理信号RFM后，相应的存储区域会进行刷新操作，以降低遭受Row Hammer攻击的风险。
另外，刷新操作会提高功耗，刷新操作只要保证不发生行锤就好，不宜过多执行刷新操作，因此，在大部分情况下，生成模块11的累计值始终为正数。
还需要说明的是，第一预设值、第二预设值、第三预设值的具体取值不限。另外，在一个信号控制电路中，第一预设值/第二预设值/第三预设值中的每一个均可以具有多个可能的取值，用户可以根据实际使用需求进行选择，以应对不同的工作场景。
需要说明的是，周期刷新信号Refresh是定时进行的，如果滚动累加计数器的累计值较高且未到下一周期刷新信号Refresh的执行时间，则可以另外产生一个刷新管理信号RFM，以补充进行一次刷新操作。基于这样的处理逻辑， 可以定义第二预设值等于第三预设值。进一步地，为了带来更好的控制效果，也可以定义第二预设值小于第三预设值。
在此基础上，如图2所示，信号控制电路10还可以包括模式寄存器14，用于接收模式选择信号；并根据模式选择信号，确定第一操作码、第二操作码和第三操作码；其中，第一操作码用于指示第一预设值与第二预设值之间的倍数关系，第二操作码用于指示第二预设值的取值，第三操作码用于指示第三预设值与第二预设值之间的倍数关系；
生成模块，还用于接收第一操作码、第二操作码和第三操作码；并根据第二操作码，确定第二预设值，根据第一操作码和第二操作码，确定第一预设值，根据第三操作码和第二操作码，确定第三预设值。
在一些实施例中，如图2所示，信号控制电路10还可以包括译码模块13，用于接收待处理信号，并对待处理信号进行译码处理，输出对应的激活操作信号Active-1、周期刷新信号Refresh或刷新管理信号RFM。
在这里，激活操作信号Active-1是指逻辑模块12的输入端接收的信号，激活操作信号Active-2是指逻辑模块12的输出端输出的信号。
需要说明的是，待处理信号是由前置电路生成并向信号控制电路10发送的，用于指示半导体存储器进行相应动作。
在一些实施例中，如图2所示，生成模块11可以包括计算模块112、锁存模块111和比较模块113；其中，
计算模块112，用于对累计值进行运算处理，得到第一运算值、第二运算值和第三运算值；
锁存模块111，用于接收激活操作信号Active-2、周期刷新信号Refresh或刷新管理信号RFM，并基于激活操作信号Active-2对应的第一运算值、周期刷新信号Refresh对应的第二运算值、或刷新管理信号RFM对应的第三运算值更新累计值；锁存模块111还用于存储更新后的累计值；
比较模块113，用于比较累计值和第一预设值，若累计值大于或等于第一预设值，则输出阻断信号Block。
在这里，计算模块112的输入端和比较模块113的输入端均与锁存模块111的输出端连接，且计算模块112的输出端与锁存模块111的输入端连接。
在一些实施例中，参见图3A，其示出了本公开实施提供的一种信号控制电路10的局部结构示意图。如图3A所示，计算模块112可以包括加法单元201、第一减法单元202和第二减法单元203；其中，
加法单元201，用于对累计值进行加一处理，输出第一运算值；
第一减法单元202，用于对累计值和第二预设值进行减法处理，输出第二运算值；
第二减法单元203，用于对累计值和第三预设值进行减法处理，输出第三运算值。
相应地，在一些实施例中，如图3A所示，锁存模块111可以包括第一控制输出单元204、第二控制输出单元205、第三控制输出单元206和锁存单元207；其中，
第一控制输出单元204，用于接收逻辑模块12输出的激活操作信号Active-2和第一运算值；并在接收到激活操作信号Active-2的情况下，将第一运算值确定为累计值；
第二控制输出单元205，用于接收周期刷新信号Refresh和第二运算值；并在接收到周期刷新信号Refresh的情况下，将第二运算值确定为累计值；
第三控制输出单元206，用于接收刷新管理信号RFM和第三运算值；并在接收到刷新管理信号RFM的情况下，将第三运算值确定为累计值；
锁存单元207的输出端用于输出累计值。
也就是说，计算模块112可以同时启用所有的计算单元(加法单元201、第一减法单元202、第二减法单元203)对累计值进行相应的计算，同时得到多个运算值；锁存模块111根据生成模块11所接收到的具体信号(激活操作信号Active-2、刷新管理信号RFM或者周期刷新信号Refresh)，在多个运算值中选择一个以形成新的累计值。换句话说，仅有锁存模块111需要根据生成模块11所接收到的具体信号进行相应的动作。这样，能够降低电路复杂性，减少信号端的数量。
在另一些实施例中，生成模块11包括计算模块112、锁存模块111和比较模块113；其中，
计算模块112，用于基于激活操作信号Active-2、周期刷新信号Refresh或刷新管理信号RFM，对累计值进行运算处理，得到目标运算值；
锁存模块111，用于利用目标运算值更新累计值，并存储更新后的累计值；
比较模块113，用于比较累计值和第一预设值，若累计值大于或等于第一预设值，则输出阻断信号Block。
相应地，参见图3B，其示出了本公开实施提供的另一种信号控制电路10的局部结构示意图。如图3B所示，计算模块112可以包括加法单元201、第一减法单元202和第二减法单元203；其中，
加法单元201，用于接收逻辑模块输出的激活操作信号Active-2和累计值；在接收到激活操作信号Active-2的情况下，对累计值进行加一处理，输出目标运算值；
第一减法单元202，用于接收周期刷新信号Refresh和累计值；并在接收到周期刷新信号Refresh的情况下，对累计值和第二预设值进行减法处理，输出目标运算值；
第二减法单元203，用于接收刷新管理信号RFM和累计值；并在接收到刷新管理信号RFM的情况下，对累计值和第三预设值进行减法处理，输出目标运算值。
相应地，在一些实施例中，如图3B所示，锁存模块111，用于接收目标运算值，并利用目标运算值更新累计值。
也就是说，计算模块112可以根据生成模块11所接收到的具体信号(激活操作信号Active-2、刷新管理信号RFM或者周期刷新信号Refresh)，相应控制加法单元201/第一减法单元202/第二减法单元203中的一个进行相应运算，从而运算得到目标运算值；锁存模块111利用目标运算值更新累计值。这样，仅 有计算模块112需要根据生成模块11所接收到的具体信号进行相应的动作，而且每次仅有一个计算单元进行计算处理，能够提高电路的工作效率。
在又一些实施例中，如图2所示，生成模块11包括计算模块112、锁存模块111和比较模块113；其中，
计算模块112，用于基于激活操作信号Active-2、周期刷新信号Refresh或刷新管理信号RFM，对累计值进行对应的运算处理，得到激活操作信号Active-2对应的第一运算值、周期刷新信号Refresh对应的第二运算值或刷新管理信号RFM对应的第三运算值；
锁存模块111，用于接收激活操作信号Active-2、周期刷新信号Refresh或刷新管理信号RFM；在接收到激活操作信号Active-2时，利用第一运算值更新累计值；在接收到周期刷新信号Refresh时，利用第二运算值更新累计值；在接收到刷新管理信号RFM时，利用第三运算值更新累计值；锁存模块111还用于存储更新后的累计值；
比较模块113，用于比较累计值和第一预设值，若累计值大于或等于第一预设值，则输出阻断信号Block。
相应的，参见图3C，其示出了本公开实施提供的又一种信号控制电路10的局部结构示意图。如图3C所示，计算模块112可以包括加法单元201、第一减法单元202和第二减法单元203；其中，
加法单元201，用于在计算模块112接收到逻辑模块12输出的激活操作信号Active-2的情况下，对累计值进行加一处理，输出第一运算值；
第一减法单元202，用于在计算模块112接收到周期刷新信号Refresh的情况下，对累计值和第二预设值进行减法处理，输出第二运算值；
第二减法单元203，用于在计算模块112接收到刷新管理信号RFM的情况下，对累计值和第三预设值进行减法处理，输出第三运算值。
在一些实施例中，如图3C所示，锁存模块111可以包括第一控制输出单元204、第二控制输出单元205、第三控制输出单元206和锁存单元207；其中，
第一控制输出单元204，用于在锁存模块111接收到逻辑模块12输出的激活操作信号Active-2情况下，将第一运算值确定为累计值；其中，第一控制输出单元204的控制端与逻辑模块12的输出端连接，第一控制输出单元204的输入端与加法单元201的输出端连接，第一控制输出单元204的输出端与锁存单元207的输入端连接；
第二控制输出单元205，用于在锁存模块111接收到周期刷新信号Refresh的情况下，将第二运算值确定为累计值；其中，第二控制输出单元205的控制端用于接收周期刷新信号Refresh，第二控制输出单元205的输入端与第一减法单元202的输出端连接，第二控制输出单元205的输出端与锁存单元207的输入端连接；
第三控制输出单元206，用于在锁存模块111接收到刷新管理信号RFM的情况下，将第三运算值确定为累计值；其中，第三控制输出单元206的控制端用于接收刷新管理信号RFM，第三控制输出单元206的输入端与第二减法单元203的输出端连接，第三控制输出单元206的输出端与锁存单元207的输入端 连接；
锁存单元207的输出端用于输出累计值。
需要说明的是，锁存单元207可以是主动输出的，即锁存单元207持续性的将输入端接收到的信号输出以作为累计值；或者，锁存单元207可以是被动输出的，即在锁存单元207的控制端接收到其他电路单元的请求指令后，锁存单元207将输入端接收到的信号输出以形成累计值。
需要说明的是，在前述内容中，根据生成模块11所接收到的具体信号(激活操作信号Active-2、刷新管理信号RFM或者周期刷新信号Refresh)，计算模块112需要启用相应的计算单元(加法单元201、第一减法单元202或者第二减法单元203)对累计值进行相应的计算，得到相应的运算值；另外，锁存模块111同样根据生成模块11所接收到的具体信号，将计算模块112输出的运算值确定为新的累计值。换句话说，计算模块112和锁存模块111均需要根据生成模块11所接收到的具体信号进行相应的动作，能够避免无用的运算过程，降低电路能耗。
应理解，以上三种实施例方法，也可以根据实际采用的物理器件可以进一步的叠加和调整。例如，在计算模块112中，始终启用某些计算单元(例如第一减法单元202或第二减法单元203)对累计值进行计算，在生成模块11接收到某一信号(例如激活操作信号Active-2)时启用对应的计算单元(例如加法单元201)对累计值进行计算，等等。综上，通过本公开实施例提供的信号控制电路，能够在某一存储区域反复进行激活操作并且没有及时进行刷新操作时，阻断新的激活操作信号，避免再次执行新的激活操作，从而避免行锤效应。
本实施例提供了一种信号控制电路，包括：生成模块，用于累计激活操作的执行次数，若累计值大于或等于第一预设值，则输出阻断信号；逻辑模块，用于接收激活操作信号和阻断信号，若接收到阻断信号，则阻断激活操作信号的输出；若未收到阻断信号，则输出激活操作信号。这样，信号控制电路能够对激活操作的执行次数进行累计，在累计值大于或等于第一预设值时，通过阻断信号阻断新的激活操作信号，在完成刷新操作之前避免激活操作的再次发生，能够进一步缓解Row Hammer攻击带来的问题。
在本公开的一些实施例中，参见图4，其示出了本公开实施例提供的一种信号控制方法的流程示意图。如图4所示，该方法可以包括：
S301：接收激活操作信号。
需要说明的是，信号控制方法应用于前述的信号控制电路10，能够缓解动态随机存取存储器中的Row Hammer攻击带来的问题。
在这里，激活操作信号用于指示对相应的字线进行激活操作。
在一些实施例中，所述接收激活操作信号，可以包括：
接收待处理信号；
对待处理信号进行译码处理，得到对应的激活操作信号、周期刷新信号或刷新管理信号。
S302：累计激活操作的执行次数，确定累计值。
需要说明的是，步骤S301和步骤S302之间无先后顺序。具体来说，步骤 S302是一个持续执行的过程，而步骤S301是在步骤S302的期间发生的。
在这里，累计值是指DRAM中某一存储区域中激活操作的实际执行次数。也就是说，通过对该存储区域中激活操作的实际执行情况进行一个持续性的统计，确定累计值。在接收到激活操作信号后，需要依据实时统计到的累计值对激活操作信号进行后续处理。
在一些实施例中，所述累计激活操作的执行次数，确定累计值，可以包括：
接收周期刷新信号、刷新管理信号或者输出后的激活操作信号；
在接收到输出后的激活操作信号时，对累计值进行加一操作；在接收到周期刷新信号时，将累计值减去第二预设值；在接收到刷新管理信号时，将累计值减去第三预设值。
这样，在接收到激活操作信号后，还需要确定累计值，以确定是否执行激活操作。
S303：在累计值大于或等于第一预设值的情况下，阻断激活操作信号的输出。
S304：在累计值小于第一预设值的情况下，输出激活操作信号。
需要说明的是，如果累计值大于或等于第一预设值，即某一存储区域中激活操作的实际执行次数超出正常范围，说明该存储区域可能遭受到Row Hammer攻击，那么将阻断新接收到的激活操作信号，避免该存储区域执行新的激活操作，防止由于Row Hammer攻击造成的数据丢失。反之，如果累计值小于第一预设值，那么该存储区域中激活操作的实际执行次数仍属于正常范围，在接收到新的激活操作信号后，将进行正常的激活操作，不会影响半导体存储器的正常功能。
在这里，第一预设值/第二预设值/第三预设值中的每一个均可以具有多个可能的取值，用户可以根据实际使用需求进行灵活调整，以应对不同的工作场景。
在一些实施例中，激活操作信号的阻断可以借由阻断信号实现。所述阻断激活操作信号的输出，可以包括：
比较累计值和第一预设值，若累计值大于或等于第一预设值，则输出阻断信号；
对阻断信号和激活操作信号进行逻辑运算，根据运算结果阻断激活操作信号。
在一些实施例中，阻断信号可以为高电平有效信号。因此，对阻断信号和激活操作信号进行逻辑运算，以实现阻断激活操作信号，可以包括：
对阻断信号进行非运算，输出反相阻断信号，并对反相阻断信号和激活操作信号进行与运算，根据运算结果阻断激活操作信号；或者对阻断信号进行非运算，输出反相阻断信号，并对反相阻断信号和激活操作信号进行与运算，根据运算结果输出激活操作信号。
在另一些实施例中，阻断信号可以为低电平有效信号。因此，所述对阻断信号和激活操作信号进行逻辑运算，以实现阻断激活操作信号，可以包括：
对阻断信号和激活操作信号进行与运算，根据运算结果阻断激活操作信号；或者对阻断信号和激活操作信号进行与运算，根据运算结果输出激活操作信号。
本公开实施例提供了一种信号控制方法，包括：接收激活操作信号；累计激活操作的执行次数，确定累计值；在累计值大于或等于第一预设值的情况下，阻断激活操作信号的输出；在累计值小于第一预设值的情况下，输出激活操作信号。这样，对激活操作的执行次数进行累计，在累计值大于或等于第一预设值时，通过阻断信号阻断新的激活操作信号，在完成刷新操作之前避免激活操作的再次发生，能够进一步缓解Row Hammer攻击带来的问题。
在本公开的一些实施例中，参见图5，其示出了本公开实施例提供的又一种信号控制电路10的组成结构示意图。如图5所示，信号控制电路10可以包括生成模块11、译码及逻辑模块41和模式寄存器14。
在这里，生成模块11，用于对激活操作的执行次数进行累计，得到累计值。具体地，在生成模块11接收到激活操作信号Active-2时，对累计值进行加一处理；在生成模块11接收到周期刷新信号Refresh时，将累计值减去第二预设值；在生成模块11接收到刷新管理信号RFM时，将累计值减去第三预设值。另外，在累计值大于或等于第一预设值后，生成模块11向译码及逻辑模块41输出阻断信号Block。
译码及逻辑模块41，主要用于待处理信号的译码处理；另外，在待处理信号译码得到激活操作信号Active-1的情况下，若未接收到阻断信号Block，则对激活操作信号Active-1进行输出，以指示某一存储区域执行正常的激活操作；若接收到阻断信号Block，则对激活操作信号Active-1进行阻断处理，避免某一存储区域再次执行激活操作，从而缓解Row Hammer攻击带来的问题。换句话说，译码及逻辑模块41可以视为图2中译码模块13和逻辑模块12的整体。
模式寄存器14，向生成模块11提供第一操作码RAAMult<1:0>、第二操作码RAAIMT<4:0>和第三操作码RAADec<1:0>。在这里，第一操作码RAAMult<1:0>和第二操作码RAAIMT<4:0>用于确定第一预设值，第二操作码RAAIMT<4:0>用于确定第二预设值，第三操作码RAADec<1:0>和第二操作码RAAIMT<4:0>用于确定第三预设值。具体可参见前述的表1～表4。
参见图6，其示出了本公开实施例提供的一种译码及逻辑模块41的局部结构示意图。如图6所示，译码及逻辑模块41包括激活指令译码单元411、非门412和与门413。在这里，激活指令译码单元411用于接收待处理信号，并在译码成功的情况下，得到激活操作信号Active-1；非门412的输入端与阻断信号Block连接，与门413的两个输入端分别与激活指令译码单元411的输出端和非门412的输出端连接。这样，在阻断信号Block处于高电平状态时，与门413的输出始终为低电平，从而实现对激活操作信号Active-1的阻断；在阻断信号Block处于低电平状态时，与门413的输出随着激活操作信号Active-1进行变化，从而实现将激活操作信号Active-1进行输出，得到激活操作信号Active-2。
另外，译码及逻辑模块41还包括周期刷新指令译码单元和刷新管理指令译码单元。周期刷新指令译码单元，用于对待处理信号进行译码，并在译码成功的情况下，得到周期刷新信号Refresh；以及刷新管理指令译码单元，用于对待处理信号进行译码，并在译码成功的情况下，得到刷新管理信号RFM。
在一些实施例中，累计值是由一组数据Out<n>、Out<n-1>……Out<0>构 成的，表示为Out<n：0>。相应地，生成模块11可以包括n+1个生成子模块42，分别用于确定Out<n>、Out<n-1>……Out<0>。
以下仅以Out<n>为例，对累计值的确定过程进行说明，累计值中其他位的确定过程可进行参照理解，不再一一解释。
参见图7，其示出了本公开实施例提供的一种生成模块11的局部结构示意图一。具体地，图7示出了一个生成子模块42的结构示意图。如图7所示，生成子模块42至少可以包括加法器421、触发器422和锁存子模块423。
如图7所示，加法器421的输入端用于接收Out<n>和进位信号C<n-1>，进位信号C<n-1>是由Out<n-1>对应的生成子模块中的加法器(图中未示出)产生的；加法器421的输出端用于输出进位信号C<n>和Out<n>。在这里，加法器421可以通过异或半加器实现，即若加法器421的输入端相同，则输出低电平信号；如果加法器421的输入端不同，则输出高电平信号。
需要说明的是，Out<0>对应的生成子模块中的加法器421的输入端可以用于接收锁存子模块输出的Out<0>和计数触发信号，输出Out<0>和C<0>，且加法器421输出的Out<0>后续依次进入触发器422和锁存子模块423。在这里，计数触发信号可以采用激活操作信号Active-2或者高电平信号。
触发器422的输入端用于接收加法器421输出的Out<n>，触发器422的控制端用于接收激活操作信号Active-2，触发器422的输出端用于输出ActS<n>。在这里，ActS<n>是指前述的第一运算值中的第n+1位数据。这样，n+1个加法器421和n+1个触发器422共同构成图3C中的加法单元201。
另外，第二运算值中的第n+1位数据可以用RfshS<n>表示，第三运算值中的第n+1位数据可以用RfmS<n>表示。除此之外，参见图8，其示出了本公开实施例提供的一种生成模块11的局部结构示意图二。如图8所示，生成模块11还可以包括第一减法器43(相当于图3C中的第一减法单元202)和第二减法器44(相当于图3C中的第二减法单元203)。其中，第一减法器43的输入是Out<n:0>和第二预设值(用RAAIMT表示)，通过对Out<n:0>和第二预设值进行减法运算，得到RfshS<n：0>。第二减法器44的输入是Out<n:0>和第三预设值(用RAAIMT*RAADec表示)，通过对Out<n:0>和第三预设值进行减法运算，得到RfmS<n：0>。另外，RfshS<n：0>中的第n+1位数据就是前述的RfshS<n>，RfmS<n：0>的第n+1位数据就是前述的RfmS<n>。
锁存子模块423，用于在接收到激活操作信号Active-2的情况下，将ActS<n>输出以得到Out<n>；在接收到周期刷新信号Refresh的情况下，将RfshS<n>输出以得到Out<n>；在接收到刷新管理信号RFM的情况下，将RfmS<n>输出以得到Out<n>。
参见图9，其示出了本公开实施例提供的一种生成模块11的局部结构示意图三。具体地，图9为锁存子模块423的具体结构示意图。如图9所示，锁存子模块423包括第一控制输出子单元4231、第二控制输出子单元4232、第三控制输出子单元4233和锁存子单元4234。
第一控制输出子单元4231的输入端接收ActS<n>，其控制端接收激活操作信号Active-2，用于在接收到激活操作信号Active-2的情况下，将ActS<n>输 出至锁存子单元4234；第二控制输出子单元4232的输入端接收RfshS<n>，其控制端接收周期刷新信号Refresh，用于在接收到周期刷新信号Refresh的情况下，将RfshS<n>输出至锁存子单元4234；第三控制输出子单元4233的输入端接收RfmS<n>，其控制端接收刷新管理信号RFM，用于在接收到刷新管理信号RFM的情况下，将RfmS<n>输出以至锁存子单元4234；锁存子单元4234主要起到信号保持的作用，用于将接收的信号进行输出以得到Out<n>。
在这里，n+1个第一控制输出子单元4231共同构成图3C中的第一控制输出单元204，n+1个第二控制输出子单元4232共同构成图3C中的第二控制输出单元205，n+1个第三控制输出子单元4233共同构成图3C中的第三控制输出单元206，n+1个锁存子单元4234共同构成图3C中的锁存单元207。
示例性的，第一控制输出子单元4231、第二控制输出子单元4232和第三控制输出子单元4233的结构相同，各自由一个三态缓冲器构成，锁存子单元4234由两个首尾连接的缓冲器构成。
这样，通过生成模块11中的n+1个锁存子模块423，可以分别得到Out<n>～Out<0>，从而获得累计值Out<n：0>。
参见图10，其示出了本公开实施例提供的一种生成模块的局部结构示意图四。如图10所示，生成模块11还包括比较器45(相当于图2中的比较模块113)，比较器45用于接收累计值Out<n：0>和第一预设值(用RAAIMT*RAAMult表示)，并在累计值Out<n：0>大于或等于第一预设值时，输出阻断信号Block。
综上所述，图5和图6示出了整个信号控制电路10的工作原理框图：首先，对于生成模块11，在接收到激活操作信号Active-2时，将累计值进行加一处理，或者在接收到周期刷新信号Refresh时，将累计值减去(模式寄存器14提供的)第二预设值，或者在接收到刷新管理信号RFM时，将累计值减去(模式寄存器14提供的)第三预设值；在信号控制电路10的工作过程中，如果生成模块11的累计值达到(模式寄存器14提供的)第一预设值，那么输出阻断信号，以阻断新的激活操作信号。图7～图10是利用加法器、减法器、多位锁存器等器件实现生成模块11的结构示意图。具体地，加法器会用于计算接收到激活操作信号Active-2累计的次数，以确定第一运算值，第一减法器43会实时计算当前的累计值减去第二预设值，以确定第二运算值，第二减法器44会实时计算当前的累计值减去第三预设值，以确定第三运算值，锁存子模块423用于根据接收到的激活操作信号Active-2、周期刷新信号Refresh或刷新管理信号RFM，锁存激活操作信号Active-2对应的第一运算值、周期刷新信号Refresh对应的第二运算值或刷新管理信号RFM对应的第三运算值；比较器45会实时比较当前的累计值和第一预设值，以产生阻断信号Block。
本公开实施例提供了一种信号控制电路，通过本实施例对前述实施例的具体实现进行详细阐述，从中可以看出，信号控制电路能够对激活操作的执行次数进行累计，并在累计值大于或等于第一预设值时，通过阻断信号阻断新的激活操作信号，在完成刷新操作之前避免激活操作的再次发生，能够缓解Row Hammer攻击带来的问题。
在本公开的又一实施例中，参见图11，其示出了本公开实施例提供的一种 半导体存储器50的组成结构示意图。如图11所示，半导体存储器50可以包括前述实施例任一项的信号控制电路10，以缓解Row Hammer攻击带来的问题。
以上，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围。需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种信号控制电路、信号控制方法和半导体存储器，该信号控制电路包括：生成模块，用于累计激活操作的执行次数，若累计值大于或等于第一预设值，则输出阻断信号；逻辑模块，用于接收激活操作信号和阻断信号，若接收到阻断信号，则阻断激活操作信号的输出；若未收到阻断信号，则输出激活操作信号。这样，信号控制电路能够对激活操作的执行次数进行累计，在累计值大于或等于第一预设值时，通过阻断信号阻断新的激活操作信号，避免激活操作的再次发生，能够缓解行锤攻击带来的问题。

Claims (18)

  1. 一种信号控制电路，包括：
    生成模块，用于累计激活操作的执行次数，若累计值大于或等于第一预设值，则输出阻断信号；
    逻辑模块，用于接收激活操作信号和所述阻断信号，若接收到所述阻断信号，则阻断所述激活操作信号的输出；若未收到所述阻断信号，则输出所述激活操作信号。
  2. 根据权利要求1所述的信号控制电路，其中，
    所述生成模块，还用于接收周期刷新信号、刷新管理信号或所述逻辑模块输出的激活操作信号；以及，
    在接收到所述激活操作信号时，对所述累计值进行加一操作；在接收到所述周期刷新信号时，将所述累计值减去第二预设值；在接收到所述刷新管理信号时，将所述累计值减去第三预设值。
  3. 根据权利要求2所述的信号控制电路，其中，所述生成模块包括计算模块、锁存模块和比较模块；其中，
    所述计算模块，用于对所述累计值进行运算处理，得到第一运算值、第二运算值和第三运算值；
    所述锁存模块，用于接收所述激活操作信号、所述周期刷新信号或所述刷新管理信号，并基于所述激活操作信号对应的所述第一运算值、所述周期刷新信号对应的所述第二运算值、或所述刷新管理信号对应的所述第三运算值更新所述累计值；所述锁存模块还用于存储更新后的所述累计值；
    所述比较模块，用于比较所述累计值和第一预设值，若所述累计值大于或等于第一预设值，则输出所述阻断信号。
  4. 根据权利要求2所述的信号控制电路，其中，所述生成模块包括计算模块、锁存模块和比较模块；其中，
    所述计算模块，用于基于所述激活操作信号、所述周期刷新信号或所述刷 新管理信号，对所述累计值进行运算处理，得到目标运算值；
    所述锁存模块，用于利用所述目标运算值更新所述累计值，并存储更新后的所述累计值；
    所述比较模块，用于比较所述累计值和第一预设值，若所述累计值大于或等于第一预设值，则输出所述阻断信号。
  5. 根据权利要求2所述的信号控制电路，其中，所述生成模块包括计算模块、锁存模块和比较模块；其中，
    所述计算模块，用于基于所述激活操作信号、所述周期刷新信号或所述刷新管理信号，对所述累计值进行对应的运算处理，得到所述激活操作信号对应的第一运算值、所述周期刷新信号对应的第二运算值或所述刷新管理信号对应的第三运算值；
    所述锁存模块，用于接收所述激活操作信号、所述周期刷新信号或所述刷新管理信号；在接收到所述激活操作信号时，利用所述第一运算值更新所述累计值；在接收到所述周期刷新信号时，利用所述第二运算值更新所述累计值；在接收到所述刷新管理信号时，利用所述第三运算值更新所述累计值；所述锁存模块还用于存储更新后的所述累计值；
    所述比较模块，用于比较所述累计值和第一预设值，若所述累计值大于或等于第一预设值，则输出所述阻断信号。
  6. 根据权利要求5所述的信号控制电路，其中，所述计算模块包括加法单元、第一减法单元和第二减法单元；其中，
    所述加法单元，用于在所述计算模块接收到所述逻辑模块输出的激活操作信号的情况下，对所述累计值进行加一处理，输出第一运算值；
    所述第一减法单元，用于在所述计算模块接收到所述周期刷新信号的情况下，对所述累计值和所述第二预设值进行减法处理，输出第二运算值；
    所述第二减法单元，用于在所述计算模块接收到所述刷新管理信号的情况下，对所述累计值和所述第三预设值进行减法处理，输出第三运算值。
  7. 根据权利要求6所述的信号控制电路，其中，所述锁存模块包括第一控 制输出单元、第二控制输出单元、第三控制输出单元和锁存单元；其中，
    所述第一控制输出单元，用于在所述锁存模块接收到所述逻辑模块输出的激活操作信号的情况下，将所述第一运算值确定为所述累计值；其中，所述第一控制输出单元的控制端与所述逻辑模块的输出端连接，所述第一控制输出单元的输入端与所述加法单元的输出端连接，所述第一控制输出单元的输出端与所述锁存单元的输入端连接；
    所述第二控制输出单元，用于在所述锁存模块接收到所述周期刷新信号的情况下，将所述第二运算值确定为所述累计值；其中，所述第二控制输出单元的控制端用于接收所述周期刷新信号，所述第二控制输出单元的输入端与所述第一减法单元的输出端连接，所述第二控制输出单元的输出端与所述锁存单元的输入端连接；
    所述第三控制输出单元，用于在所述锁存模块接收到所述刷新管理信号的情况下，将所述第三运算值确定为所述累计值；其中，所述第三控制输出单元的控制端用于接收所述刷新管理信号，所述第三控制输出单元的输入端与所述第二减法单元的输出端连接，所述第三控制输出单元的输出端与所述锁存单元的输入端连接；
    所述锁存单元的输出端用于输出所述累计值。
  8. 根据权利要求2所述的信号控制电路，其中，还包括：
    译码模块，用于接收待处理信号，并对所述待处理信号进行译码处理，输出对应的所述激活操作信号、所述周期刷新信号或所述刷新管理信号。
  9. 根据权利要求1所述的信号控制电路，其中，所述逻辑模块包括非门和与门；其中，
    所述非门，用于对所述阻断信号进行非运算，得到反相阻断信号；
    所述与门，用于对所述反相阻断信号和所述激活操作信号进行与运算，根据运算结果阻断或输出所述激活操作信号。
  10. 根据权利要求1所述的信号控制电路，其中，所述逻辑模块包括与门；所述与门，用于对所述阻断信号和所述激活操作信号进行与运算，根据运算结 果阻断或输出所述激活操作信号。
  11. 根据权利要求2-8任一项所述的信号控制电路，其中，所述第一预设值是所述第二预设值的n倍，n大于1；所述第三预设值是所述第二预设值的m倍，m大于或等于1。
  12. 根据权利要求11所述的信号控制电路，其中，还包括：
    模式寄存器，用于接收模式选择信号；并根据所述模式选择信号，确定第一操作码、第二操作码和第三操作码；其中，所述第一操作码用于指示第一预设值与所述第二预设值之间的倍数关系，所述第二操作码用于指示所述第二预设值的取值，第三操作码用于指示第三预设值与所述第二预设值之间的倍数关系；
    所述生成模块，还用于接收所述第一操作码、第二操作码和第三操作码；并根据所述第二操作码，确定所述第二预设值，根据所述第一操作码和所述第二操作码，确定所述第一预设值，根据所述第三操作码和所述第二操作码，确定第三预设值。
  13. 一种信号控制方法，所述方法包括：
    接收激活操作信号；
    累计激活操作的执行次数，确定累计值；在所述累计值大于或等于第一预设值的情况下，阻断所述激活操作信号的输出；在所述累计值小于第一预设值的情况下，输出所述激活操作信号。
  14. 根据权利要求13所述的信号控制方法，其中，所述累计激活操作的执行次数，确定累计值，包括：
    接收周期刷新信号、刷新管理信号或者输出后的所述激活操作信号；
    在接收到输出后的所述激活操作信号时，对所述累计值进行加一操作；在接收到所述周期刷新信号时，将所述累计值减去第二预设值；在接收到所述刷新管理信号时，将所述累计值减去第三预设值。
  15. 根据权利要求14所述的信号控制方法，其中，所述接收激活操作信号，包括：
    接收待处理信号；
    对所述待处理信号进行译码处理，得到对应的所述激活操作信号、所述周期刷新信号或所述刷新管理信号。
  16. 根据权利要求13所述的信号控制方法，其中，所述在所述累计值大于或等于第一预设值的情况下，阻断所述激活操作信号的输出，包括：
    比较所述累计值和所述第一预设值，若所述累计值大于或等于所述第一预设值，则输出阻断信号；
    对所述阻断信号和所述激活操作信号进行逻辑运算，根据运算结果阻断所述激活操作信号。
  17. 根据权利要求16所述的信号控制方法，其中，所述对所述阻断信号和所述激活操作信号进行逻辑运算，以实现阻断所述激活操作信号，包括：
    对所述阻断信号进行非运算，并输出反相阻断信号；
    对所述反相阻断信号和所述激活操作信号进行与运算，根据运算结果阻断所述激活操作信号；或者对所述反相阻断信号和所述激活操作信号进行与运算，根据运算结果输出所述激活操作信号。
  18. 一种半导体存储器，包括如权利要求1至12任一项所述的信号控制电路。
PCT/CN2022/098681 2022-04-29 2022-06-14 信号控制电路、信号控制方法和半导体存储器 WO2023206744A1 (zh)

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