WO2023202440A1 - 一种适用于多电平通信的io电路及其控制方法 - Google Patents

一种适用于多电平通信的io电路及其控制方法 Download PDF

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Publication number
WO2023202440A1
WO2023202440A1 PCT/CN2023/087778 CN2023087778W WO2023202440A1 WO 2023202440 A1 WO2023202440 A1 WO 2023202440A1 CN 2023087778 W CN2023087778 W CN 2023087778W WO 2023202440 A1 WO2023202440 A1 WO 2023202440A1
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level
circuit
input
input branch
signal
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PCT/CN2023/087778
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English (en)
French (fr)
Inventor
刘帅锋
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合肥市芯海电子科技有限公司
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Publication of WO2023202440A1 publication Critical patent/WO2023202440A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/02—System on chip [SoC] design

Definitions

  • the present application relates to the field of electronic technology, and in particular to an IO circuit suitable for multi-level communication and a control method thereof.
  • the IO (In/Out, input and output) interface is often used to realize the interaction and communication between the internal circuit of the chip and the outside world.
  • the corresponding IO circuit is used to realize digital input, output, pull-up and pull-down, and the output can include push-pull output and switch. There are two situations of leakage output.
  • the IO circuit includes an input branch and an output branch, and its different functions are realized through the configuration of internal logic.
  • the communication of IO interface needs to adapt to different communication level requirements.
  • different IO interfaces in the chip can be connected to different electronic devices (such as other chips or board-level circuits) at the board level.
  • the communication levels of electronic devices may not be the same, so the IO circuit needs to adapt to different communication levels depending on the application.
  • the power supply voltage of the input branch can be switched between VDD1 and VDD2 through the power switching circuit according to the application needs, thereby adapting to different communication levels.
  • each IO circuit requires a power switching circuit, and the power switching circuit has a larger area and will occupy a larger area of the chip.
  • IO circuits are usually equipped with ESD (Electro-Static Discharge, electrostatic resistor) protection circuits.
  • ESD Electro-Static Discharge, electrostatic resistor
  • the ESD protection circuit needs to consider the influence of the power switching circuit. In order to achieve the same ESD capability, it is necessary to increase the area of the ESD discharge device and increase the complexity of the ESD protection circuit design.
  • embodiments of the present application provide an IO circuit suitable for multi-level communication and a control method thereof, which can avoid using a power switching circuit and reduce area occupation.
  • the technical solution is as follows:
  • an IO circuit suitable for multi-level communication includes multiple input branches, and the power supply voltage of each input branch is different;
  • the input branch is configured to convert the level signal connected to the pin into a first level signal when the input branch is selected, wherein the first level signal is consistent with the target communication level. adapted, and the first level signal is used to access the next level circuit.
  • the input branch also includes a control module
  • the control module is configured to receive an enable control signal of the input branch, and is configured to control the input branch to be effective based on the enable control signal of the first level when the input branch is selected; When the input branch is not selected, the enable control signal based on the second level controls the input branch to be invalid.
  • the enable control signal is configured to the first level
  • the enable control signal is configured to the second level.
  • control module includes a first field effect transistor, and the control end of the first field effect transistor is used to access the enable control signal.
  • the input branch includes a level detection module and an input module
  • the level detection module is used to output a detection signal based on the level signal connected to the pin and the set threshold;
  • the input module is used to convert the detection signal into the first level signal.
  • the IO circuit also includes a default state setting module
  • the default state setting module is configured to connect a certain level to the input terminal of the input module when the input branch is invalid.
  • the default state setting module includes a second field effect transistor, the control end of the second field effect transistor is used to receive the enable control signal, or receive a signal opposite to the enable control signal.
  • the input branch further includes a level conversion module
  • the level conversion module is used to convert the first level signal into a second level signal, and the second level signal is adapted to the power supply voltage applicable to the next stage circuit.
  • a control method for an IO circuit suitable for multi-level communication is provided.
  • the IO circuit includes multiple input branches, and the power supply voltage of each input branch is different.
  • the method includes :
  • the target communication level with the external circuit determine the target input branch that is adapted to the target communication level
  • a chip including the above-mentioned IO circuit suitable for multi-level communication.
  • an electronic device including the above-mentioned IO circuit suitable for multi-level communication.
  • the IO circuit may include multiple input branches, each input branch has a certain power supply voltage, and there is no need to switch the power supply. The switching of the power supply is converted into the selection of the input branch. Compared with the power switching circuit, this application The IO circuit provided by you has a simple structure and takes up less chip area.
  • Figure 1 shows a schematic diagram of an IO input circuit provided according to an exemplary embodiment of the present application
  • Figure 2 shows a schematic diagram of an input branch provided according to an exemplary embodiment of the present application
  • FIG. 3 shows a schematic diagram of a control module provided according to an exemplary embodiment of the present application
  • Figure 4 shows a schematic diagram of an input branch provided according to an exemplary embodiment of the present application
  • Figure 5 shows a schematic diagram of an IO input circuit provided according to an exemplary embodiment of the present application
  • Figure 6 shows a schematic diagram of an IO input circuit provided according to an exemplary embodiment of the present application
  • Figure 7 shows a schematic diagram of default state setting provided according to an exemplary embodiment of the present application.
  • Figure 8 shows a schematic diagram of a default state setting module provided according to an exemplary embodiment of the present application.
  • Figure 9 shows a schematic diagram of an IO input circuit provided according to an exemplary embodiment of the present application.
  • Figure 10 shows a schematic diagram of an input branch provided according to an exemplary embodiment of the present application.
  • Figure 11 shows a schematic diagram of an IO circuit provided according to an exemplary embodiment of the present application.
  • Figure 12 shows a flow chart of a control method provided according to an exemplary embodiment of the present application
  • FIG. 13 shows a structural block diagram of an exemplary electronic device that can be used to implement embodiments of the present application.
  • the term “include” and its variations are open-ended, ie, “including but not limited to.”
  • the term “based on” means “based at least in part on.”
  • the term “one embodiment” means “at least one embodiment”; the term “another embodiment” means “at least one additional embodiment”; and the term “some embodiments” means “at least some embodiments”.
  • Relevant definitions of other terms will be given in the description below. It should be noted that concepts such as “first” and “second” mentioned in this application are only used to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units. Or interdependence.
  • the embodiment of the present application provides an IO circuit suitable for multi-level communication.
  • the IO circuit can be integrated in a chip or board-level circuit, or provided in an electronic device.
  • the IO circuit can communicate with external circuits based on the target communication level, including input branches and output branches, and access or output signals through pins.
  • the embodiments of this application mainly focus on improving the input branch, and the output branch can adopt the existing structure to achieve corresponding functions.
  • the embodiments of this application do not limit the output branch, nor are they introduced in detail in the embodiments of this application.
  • the IO circuit may include multiple input branches, each input branch has a different power supply voltage, and each input branch is connected in parallel.
  • the power supply voltage VDD1 of one input branch may be 3.3V
  • the power supply voltage VDD2 of the other input branch may be 1.8V, or other voltage values. This embodiment does not limit the number of input branches and the specific power supply voltage value.
  • An input branch can be configured to convert the level signal connected to the pin into a first level signal when the input branch is selected.
  • the level signal connected to the pin may be an analog signal, and the first level signal may be a digital signal.
  • the first level signal is adapted to the target communication level, and is used to access the next level circuit.
  • Phase matching may refer to high and low level logic matching. For example, if the level signal connected to the pin is 1.8V, it can be judged as high level in a circuit with a power supply voltage of 1.8V, but it may be judged as a low level in a circuit with a power supply voltage of 3.3V.
  • the connected 1.8V needs to be used as a high level in the correct circuit logic, then in a circuit with a power supply voltage of 1.8V, the high and low level logic will match, and the circuit can run correctly, that is, it is compatible; but in the power supply In a circuit with a voltage of 3.3V, the high and low level logic does not match, and the circuit may perform incorrect actions, that is, it is not suitable.
  • the input end of the input branch is connected to a pin for receiving a level signal input from an external circuit; the output end is connected to the next-level circuit to connect the output level signal to the internal circuit.
  • the power supply voltage applicable to the external circuit can be determined, that is, the target communication level is determined, and a target input branch that matches the target communication level is determined through internal logic.
  • the target input branch can be selected.
  • the 01 signal can be used to indicate whether the input branch is selected. For example, when there are two input branches, "01" indicates that the second input branch is selected, and "10" indicates that the first input branch is selected. .
  • the target input branch can be configured to be valid, and the input branch (ie, the target input branch) can operate normally and convert the level signal input by the external circuit into the first level signal.
  • the input branch can be configured to be valid or invalid.
  • the input branch when the input branch is not selected, the input branch is configured to be invalid.
  • the input branch when the input branch is invalid, the The input branch does not process the level signal input from the external circuit and outputs an invalid signal. On this basis, the power consumption of unselected input branches can be reduced.
  • the first level signal output by the target input branch can be connected to the next-level circuit through multiplex selection, which is not limited in this embodiment.
  • the above-mentioned 01 signal can be connected to a multiplexer, and the first level signal output by the target input branch can be selected through the multiplexer.
  • the second input branch can be selected.
  • the signal of the first input branch can be selected based on the signal "10".
  • the input branch may also include a control module.
  • This control module can be used to control whether the input branch is valid.
  • the control module may be configured to receive an enable control signal of the input branch, and be configured to control the input branch to be effective based on the first level when the input branch is selected; and to control the input branch to be effective based on the second level when the input branch is not selected.
  • the flat control input branch is invalid.
  • the above-mentioned enable control signal may be configured to the first level.
  • the above-mentioned enable control signal may be configured to the second level.
  • one input branch corresponds to an enable control signal.
  • the enable control signal for the input branch can be configured as the first level; if they do not match, the enable control signal for the input branch can be configured as the second level.
  • the first level may be a high level
  • the second level may be a low level, which is opposite to the first level.
  • the first level may be low level and the second level may be high level. This embodiment does not limit the specific enable control signal.
  • the enable control signal of the first level can be connected to the target input branch, thereby configuring the target input branch to be effective; the enable control signal of the second level can be connected to the remaining input branches, so that the target input branch can be configured to be valid. Configure the remaining input legs as inactive.
  • control module can be set at the ground end of the input branch to control whether the input branch is grounded.
  • control module can also be set at the end of the input branch connected to the power supply to control whether the power supply voltage is connected to the input branch. This embodiment does not limit the specific location of the control module.
  • control module may include a first field effect transistor, and the control end of the first field effect transistor is used to access the enable control signal.
  • the control module installed at the ground terminal and the first field effect transistor as an NMOS (N-Metal-Oxide-Semiconductor, N-type metal-oxide-semiconductor) tube.
  • NMOS N-Metal-Oxide-Semiconductor, N-type metal-oxide-semiconductor
  • the control terminal (i.e. gate) of the first field effect transistor can be used to access the enable control signal
  • the source can be used to ground
  • the drain can be used to connect to the input branch. Ground connection.
  • the first level at this time may be high level.
  • the first field effect tube When the control terminal of the first field effect transistor is connected to a high level, the first field effect tube is turned on, and the input branch can be grounded to form a path, which can work normally; when the control terminal of the first field effect tube is connected to a low level, The first field effect transistor is turned off, and the input branch is not connected to ground. in a high resistance state.
  • the first field effect transistor may also be a PMOS (P-Metal-Oxide-Semiconductor, P-type metal-oxide-semiconductor) tube.
  • PMOS P-Metal-Oxide-Semiconductor, P-type metal-oxide-semiconductor
  • the first level may be a low level
  • the input end of the first field effect transistor may be used to connect to the ground end of the input branch, and the output end may be used to ground.
  • the input branch may include a level detection module and an input module, and the output end of the level detection module is connected to the input end of the input module.
  • the level detection module can be used to output detection signals based on the level signal connected to the pin and the set threshold.
  • the input module can be used to convert the detection signal into a first level signal.
  • the input end of the level detection module can be connected to a pin, and the output end can be connected to the input end of the input module; the input end of the input module can be connected to the output end of the level detection module, and the output
  • the terminal can be connected to the next-level circuit to convert the detection signal into a first-level signal and connect to the internal circuit.
  • the level signal input by the external circuit can be compared with the set threshold to determine whether it is higher or lower than the set threshold, and detect whether the level signal is high level or low level
  • the set threshold can be related to the power supply voltage of the input branch.
  • the set threshold can be half of the power supply voltage. Assuming that the power supply voltage is 3V, the set threshold can be 1.5V. If the input level signal is 1.3V, which is lower than the set threshold, it is a low level, then the detection signal can be a low level; if the input level signal is 2.5V, which is higher than the set threshold, it is a high level. , then the detection signal can be high level.
  • This embodiment does not limit the specific set threshold.
  • the level detection module can be composed of a pair of PMOS tubes and NMOS tubes connected in parallel, where the gate of the PMOS tube is connected to the pin, and the source The electrode is connected to the drain of the NMOS tube, the drain is used to receive the power supply voltage, the gate of the NMOS tube is connected to the pin, the drain is connected to the source of the NMOS tube, and the source is used to ground.
  • PMOS tubes and NMOS tubes can be used to implement the inverting function, that is, when the pin is connected to a high level, the level detection module can output a low level, and when the pin is connected to a low level, the level detection module The module can output high level.
  • the input module can be used to implement the inverting function.
  • it can be composed of an inverter to convert the high level output by the level detection module into a low level, and convert the low level output by the level detection module. is high level.
  • the buffering function can be realized based on the level detection module and the input module.
  • the first level signal output by the input branch can be the corresponding high level.
  • the first level signal output by the input branch may be a corresponding low level.
  • This embodiment does not limit the specific circuit structures of the level detection module and the input module.
  • the IO circuit shown in Figure 6 can be formed.
  • the specific implementation principle of this IO circuit has been introduced above and will not be repeated here.
  • the level signal connected to the internal circuit may be high level or It is a low level and is in an unstable state, which may cause leakage problems. Therefore, referring to the IO circuit diagram shown in Figure 7, the IO circuit can also include a default state setting module.
  • the default state setting module is configured to connect a certain level to the input terminal of the input module when the input branch is invalid.
  • the input terminal of the input module can also be connected to a certain level, so that the input module can output a certain level signal to avoid an unstable state and solve the leakage problem.
  • the default state setting module includes a second field effect transistor, and the control end of the second field effect transistor is used to receive the above-mentioned enable control signal, or to access a signal opposite to the above-mentioned enable control signal.
  • the enable control signal connected to the second field effect transistor may be the same as or opposite to the enable control signal connected to the above-mentioned access control module, and is related to the type of the second field effect transistor. For example, when the input branch is high-level enabled, if the second field effect transistor is a PMOS tube and is low-level enabled, the control end of the second field effect transistor can be used to receive and enable the input circuit.
  • the control signal is the same signal; if the second field effect transistor is an NMOS tube and is enabled at a high level, the control end of the second field effect transistor can be used to access a signal opposite to the enable control signal of the input circuit. The same applies when the input branch is enabled at a low level and will not be described again.
  • the second field effect transistor is a PMOS transistor
  • the source is connected to the input terminal of the input module
  • the drain is used to receive the power supply voltage.
  • the second field effect transistor is turned on to connect the power supply voltage to the input module.
  • the determination level of the access input module can also be other values, and this embodiment does not limit the specific value of the determination level.
  • the IO circuit shown in Figure 9 can be formed.
  • the specific implementation principle of this IO circuit has been introduced above and will not be repeated here.
  • the input branch may also include a level conversion module.
  • the level conversion module is used to convert the first level signal into the second level signal.
  • the second level signal is adapted to the power supply voltage applicable to the next-level circuit, so that it can be processed by the next-level circuit.
  • Both the first level signal and the second level signal are digital signals.
  • the input terminal of the level conversion module can be used to receive a first level signal, and the output terminal can be used to output a second level signal.
  • the level conversion module can adopt an existing circuit structure, as long as it can realize level conversion. This embodiment does not limit the specific circuit structure of the level conversion module.
  • the power supply voltage of the input branch is 3V
  • the corresponding voltage can be 3V
  • the corresponding voltage can be 0.1V.
  • the power supply voltage of the next-level circuit is 1.5V
  • the level conversion module can convert 3.3V to 1.5V
  • the second level signal can be used as high level in the next level circuit
  • the level conversion module can convert 0.1V to 0.05V, and the obtained second level signal can be used in the next level circuit.
  • level circuit can be used as low level.
  • Figure 11 shows a specific IO circuit schematic diagram, including an output branch and multiple parallel input branches.
  • the output branch includes output control and pull-up and pull-down control logic modules, field effect transistors for driving, pull-up resistors and pull-down resistors, which are used to connect the signals output by the internal circuit to the pins and transmit them to the external circuit.
  • the output control logic module is used to control the output enable, as well as the output mode (push-pull output or open-drain output), output current size, etc. This embodiment does not limit the circuit structure and implementation of the output branch.
  • the IO circuit can include multiple input branches. Each input branch has a certain power supply voltage. There is no need to switch the power supply. The switching of the power supply is converted into the selection of the input branch. Compared with the power switching circuit, the IO circuit provided by this application has a simple structure and occupies less chip area.
  • the input branches used by different power supply voltages are the same, so the devices in the input branches need to adapt to most power supply voltages, and there may be mismatches that affect the circuit. performance.
  • the circuit structure of each input branch can be the same, and the device size can be different according to the requirements of different power domains. Matching the corresponding power supply voltage can improve the performance of the IO circuit.
  • the embodiment of the present application provides a control method suitable for the above IO circuit.
  • the specific implementation method has been introduced above, and will not be described again in this embodiment. Referring to the control method flow chart shown in Figure 12, the method includes:
  • Step 1201 Based on the target communication level with the external circuit, determine the target input branch that is adapted to the target communication level;
  • Step 1202 based on the target input branch, convert the level signal connected to the pin into a first level signal
  • Step 1203 Connect the first level signal to the next level circuit.
  • the first level signal is adapted to the target communication level.
  • the input branch further includes a control module, the control module is configured to receive an enable control signal of the input branch, and the method further includes:
  • the enable control signal based on the first level controls the input branch to be effective; when the input branch is not selected, based on the second level The enable control signal controls the input branch to be inactive.
  • the method also includes:
  • the enable control signal is configured to the second level.
  • control module includes a first field effect transistor, and the control end of the first field effect transistor is used to access the enable control signal.
  • the input branch includes a level detection module and an input module, and converting a level signal connected to a pin into a first level signal includes:
  • a detection signal is output based on the level signal connected to the pin and the set threshold;
  • the detection signal is converted into the first level signal through the input module.
  • the IO circuit also includes a default state setting module, and the method further includes:
  • the default state setting module is controlled to connect a certain level to the input terminal of the input module.
  • the default state setting module includes a second field effect transistor, the control end of the second field effect transistor is used to receive the enable control signal, or receive a signal opposite to the enable control signal.
  • the input branch further includes a level conversion module, and the method further includes:
  • the first level signal is converted into a second level signal through the level conversion module, and the second level signal is adapted to the power supply voltage applicable to the next stage circuit.
  • the IO circuit can include multiple input branches. Each input branch has a certain power supply voltage. There is no need to switch the power supply. The switching of the power supply is converted into the selection of the input branch. Compared with the power switching circuit, the IO circuit provided by this application has a simple structure and occupies less chip area.
  • the input branches used by different power supply voltages are the same, so the devices in the input branches need to adapt to most power supply voltages, and there may be mismatches that affect the circuit. performance.
  • the circuit structure of each input branch can be the same, and the device size can be different according to the requirements of different power domains. Matching the corresponding power supply voltage can improve the performance of the IO circuit.
  • Exemplary embodiments of the present application also provide a chip, including the IO circuit suitable for multi-level communication provided by the embodiments of the present application.
  • Exemplary embodiments of the present application also provide an electronic device, including: the IO circuit suitable for multi-level communication provided by the embodiment of the present application; at least one processor; and a memory communicatively connected to the at least one processor.
  • the memory stores computer programs executable by at least one processor.
  • Electronic equipment is intended to mean various forms of digital electronic computing equipment, such as data center servers, notebook computers, clients, laptops, desktop computers, workstations, personal digital assistants, blade servers, mainframe computers, and others suitable computer.
  • Electronic devices may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices, and other similar computing devices.
  • the components shown herein, their connections and relationships, and their functions are examples only and are not intended to limit the implementation of the present application as described and/or claimed herein.
  • the electronic device 1300 includes a computing unit 1301 that can perform calculations according to a computer program stored in a read-only memory (ROM) 1302 or loaded from a storage unit 1308 into a random access memory (RAM) 1303 . Perform various appropriate actions and processing.
  • ROM read-only memory
  • RAM random access memory
  • various programs and data required for the operation of the device 1300 can also be stored.
  • the computing unit 1301, ROM 1302 and RAM 1303 are connected to each other via a bus 1304.
  • An input/output (I/O) interface 1305 is also connected to bus 1304.
  • the input unit 1306 may be any type of device capable of inputting information to the electronic device 1300.
  • the input unit 1306 may receive input numeric or character information and generate key signal input related to user settings and/or function control of the electronic device.
  • Output unit 1307 may be any type of device capable of presenting information, and may include, but is not limited to, a display, speakers, video/audio output terminal, vibrator, and/or printer.
  • the storage unit 1304 may include, but is not limited to, magnetic disks and optical disks.
  • the communication unit 1309 allows the electronic device 1300 to exchange information/data with other devices through a computer network such as the Internet and/or various telecommunications networks, and may include, but is not limited to, a modem, a network card, an infrared communication device, a wireless communication transceiver and/or a chip Groups such as Bluetooth devices, WiFi devices, WiMax devices, cellular communications devices and/or the like.
  • Computing unit 1301 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of the computing unit 1301 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processing processor (DSP), and any appropriate processor, controller, microcontroller, etc. Part or all of the computer program may be loaded and/or installed onto the electronic device 1300 via the ROM 1302 and/or the communication unit 1309 .
  • CPU central processing unit
  • GPU graphics processing unit
  • AI dedicated artificial intelligence
  • DSP digital signal processing processor
  • Part or all of the computer program may be loaded and/or installed onto the electronic device 1300 via the ROM 1302 and/or the communication unit 1309 .
  • Program code may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that the program codes, when executed by the processor or controller, cause the functions specified in the flowcharts and/or block diagrams/ The operation is implemented.
  • the program code can be completed Execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.
  • a machine-readable medium may be a tangible medium that may contain or store a program for use by or in connection with an instruction execution system, apparatus, or device.
  • the machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium.
  • Machine-readable media may include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any suitable combination of the foregoing.
  • machine-readable storage media would include one or more wire-based electrical connections, laptop disks, hard drives, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above.
  • RAM random access memory
  • ROM read only memory
  • EPROM or flash memory erasable programmable read only memory
  • CD-ROM portable compact disk read-only memory
  • magnetic storage device or any suitable combination of the above.
  • machine-readable medium and “computer-readable medium” refer to any computer program product, apparatus, and/or means for providing machine instructions and/or data to a programmable processor (eg, magnetic disk, optical disk, memory, programmable logic device (PLD)), including machine-readable media that receive machine instructions as machine-readable signals.
  • machine-readable signal refers to any signal used to provide machine instructions and/or data to a programmable processor.
  • the systems and techniques described herein may be implemented on a computer having a display device (eg, a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user ); and a keyboard and pointing device (eg, a mouse or a trackball) through which a user can provide input to the computer.
  • a display device eg, a CRT (cathode ray tube) or LCD (liquid crystal display) monitor
  • a keyboard and pointing device eg, a mouse or a trackball
  • Other kinds of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and may be provided in any form, including Acoustic input, voice input or tactile input) to receive input from the user.
  • the systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., A user's computer having a graphical user interface or web browser through which the user can interact with implementations of the systems and technologies described herein), or including such backend components, middleware components, or any combination of front-end components in a computing system.
  • the components of the system may be interconnected by any form or medium of digital data communication (eg, a communications network). Examples of communication networks include: local area network (LAN), wide area network (WAN), and the Internet.
  • Computer systems may include clients and servers.
  • Clients and servers are generally remote from each other and typically interact over a communications network.
  • the relationship of client and server is created by computer programs running on corresponding computers and having a client-server relationship with each other.

Abstract

本申请提供一种适用于多电平通信的IO电路及其控制方法，属于电子技术领域。所述IO电路包括多个输入支路，每个输入支路的电源电压不同；所述输入支路，被配置为当所述输入支路被选中时，将引脚接入的电平信号转换为第一电平信号，其中，所述第一电平信号与目标通信电平相适配，且所述第一电平信号用于接入下一级电路。采用本申请，可以减少IO电路的面积。

Description

一种适用于多电平通信的IO电路及其控制方法
本申请要求于2022年04月22日提交国家知识产权局、申请号为202210429317.1、申请名称为“一种适用于多电平通信的IO电路及其控制方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子技术领域，尤其涉及一种适用于多电平通信的IO电路及其控制方法。
背景技术
IO(In/Out，输入输出)接口常用于实现芯片内部电路与外界的交互及通信，相应的IO电路用于实现数字输入、输出、上拉和下拉，其中输出又可以包括推挽输出和开漏输出两种情况。IO电路包括输入支路和输出支路，其不同功能通过内部逻辑的配置实现。
IO接口的通信需要适应不同的通信电平的要求，比如通用MCU在某些应用中，其芯片中不同的IO接口在板级可以连接不同的电子装置(如其他芯片或板级电路)，这些电子设备的通信电平可能并不相同，因此IO电路需要根据应用适应不同的通信电平。以通信电平为VDD1和VDD2为例，输入支路的电源电压可以根据应用需要，通过电源切换电路在VDD1和VDD2之间进行切换，进而适应不同的通信电平。
如果芯片中存在多个IO电路需要适应不同的通信电平，则每个IO电路都需要一个电源切换电路，而电源切换电路的面积较大，将占用芯片较大的面积。
并且，IO电路通常还会设置ESD(Electro-Static Discharge，静电阻抗器)保护电路。ESD保护电路需要考虑电源切换电路的影响，为达到同等的ESD能力需要增大ESD泄放器件的面积，增加ESD保护电路设计的复杂度。
发明内容
为了解决现有技术的问题，本申请实施例提供了一种适用于多电平通信的IO电路及其控制方法，可以避免采用电源切换电路，减小面积占用。技术方案如下：
根据本申请的一方面，提供了一种适用于多电平通信的IO电路，所述IO电路包括多个输入支路，每个输入支路的电源电压不同；
所述输入支路，被配置为当所述输入支路被选中时，将引脚接入的电平信号转换为第一电平信号，其中，所述第一电平信号与目标通信电平相适配，且所述第一电平信号用于接入下一级电路。
可选的，所述输入支路还包括控制模块；
所述控制模块用于接收所述输入支路的使能控制信号，被配置为当所述输入支路被选中时，基于第一电平的使能控制信号控制所述输入支路有效；当所述输入支路未被选中时，基于第二电平的使能控制信号控制所述输入支路无效。
可选的，当所述输入支路对应的电源电压与所述目标通信电平相适配时，使能控制信号被配置为所述第一电平；
当所述输入支路对应的电源电压与所述目标通信电平不适配时，使能控制信号被配置为所述第二电平。
可选的，所述控制模块包括第一场效应管，所述第一场效应管的控制端用于接入所述使能控制信号。
可选的，所述输入支路包括电平检测模块和输入模块；
所述电平检测模块，用于基于所述引脚接入的电平信号和设定阈值，输出检测信号；
所述输入模块，用于将所述检测信号转换为所述第一电平信号。
可选的，所述IO电路还包括默认状态设定模块；
所述默认状态设定模块，被配置为当所述输入支路无效时，将一确定电平接入所述输入模块的输入端。
可选的，所述默认状态设定模块包括第二场效应管，所述第二场效应管的控制端用于接收所述使能控制信号，或接收与所述使能控制信号相反的信号。
可选的，当所述输入支路对应的电源电压与所述下一级电路所适用的电源电压不一致时，所述输入支路还包括电平转换模块；
所述电平转换模块，用于将所述第一电平信号转换为第二电平信号，所述第二电平信号与所述下一级电路所适用的电源电压相适配。
根据本申请的另一方面，提供了一种适用于多电平通信的IO电路的控制方法，所述IO电路包括多个输入支路，每个输入支路的电源电压不同，所述方法包括：
根据与外部电路的目标通信电平，确定与所述目标通信电平相适配的目标输入支路；
基于所述目标输入支路，将引脚接入的电平信号转换为第一电平信号，其中，所述第一电平信号与所述目标通信电平相适配；
将所述第一电平信号接入下一级电路。
根据本申请的另一方面，提供了一种芯片，包括上述适用于多电平通信的IO电路。
根据本申请的另一方面，提供了一种电子设备，包括上述适用于多电平通信的IO电路。
本申请中，IO电路可以包括多个输入支路，每个输入支路具有确定的电源电压，无需进行电源的切换，将对电源的切换转换为对输入支路的选择。相比于电源切换电路，本申 请提供的IO电路结构简单，占用芯片的面积减少。
附图说明
在下面结合附图对于示例性实施例的描述中，本申请的更多细节、特征和优点被公开，在附图中：
图1示出了根据本申请示例性实施例提供的IO输入电路示意图；
图2示出了根据本申请示例性实施例提供的输入支路示意图；
图3示出了根据本申请示例性实施例提供的控制模块示意图；
图4示出了根据本申请示例性实施例提供的输入支路示意图；
图5示出了根据本申请示例性实施例提供的IO输入电路示意图；
图6示出了根据本申请示例性实施例提供的IO输入电路示意图；
图7示出了根据本申请示例性实施例提供的默认状态设定示意图；
图8示出了根据本申请示例性实施例提供的默认状态设定模块示意图；
图9示出了根据本申请示例性实施例提供的IO输入电路示意图；
图10示出了根据本申请示例性实施例提供的输入支路示意图；
图11示出了根据本申请示例性实施例提供的IO电路示意图；
图12示出了根据本申请示例性实施例提供的控制方法流程图；
图13示出了能够用于实现本申请的实施例的示例性电子设备的结构框图。
具体实施方式
下面将参照附图更详细地描述本申请的实施例。虽然附图中显示了本申请的某些实施例，然而应当理解的是，本申请可以通过各种形式来实现，而且不应该被解释为限于这里阐述的实施例，相反提供这些实施例是为了更加透彻和完整地理解本申请。应当理解的是，本申请的附图及实施例仅用于示例性作用，并非用于限制本申请的保护范围。
本文使用的术语“包括”及其变形是开放性包括，即“包括但不限于”。术语“基于”是“至少部分地基于”。术语“一个实施例”表示“至少一个实施例”；术语“另一实施例”表示“至少一个另外的实施例”；术语“一些实施例”表示“至少一些实施例”。其他术语的相关定义将在下文描述中给出。需要注意，本申请中提及的“第一”、“第二”等概念仅用于对不同的装置、模块或单元进行区分，并非用于限定这些装置、模块或单元所执行的功能的顺序或者相互依存关系。
需要注意，本申请中提及的“一个”、“多个”的修饰是示意性而非限制性的，本领域技术人员应当理解，除非在上下文另有明确指出，否则应该理解为“一个或多个”。
本申请实施方式中的多个装置之间所交互的消息或者信息的名称仅用于说明性的目的，而并不是用于对这些消息或信息的范围进行限制。
本申请实施例提供了一种适用于多电平通信的IO电路，该IO电路可以集成在芯片或板级电路中，或者设置在电子设备中。该IO电路可以基于目标通信电平与外部电路通信，包括输入支路和输出支路，通过引脚接入或输出信号。本申请实施例主要针对输入支路进行改进，输出支路可以采用现有的结构以实现相应功能，本申请实施例对输出支路不作限定，也不在本申请实施例中详细介绍。
参照图1所示的IO电路示意图，该IO电路可以包括多个输入支路，每个输入支路的电源电压不同，每个输入支路之间并联。例如，一个输入支路的电源电压VDD1可以是3.3V，另一输入支路的电源电压VDD2可以是1.8V，还可以是其他电压值。本实施例对输入支路的数量以及具体的电源电压值不作限定。
下面将基于一个输入支路进行介绍，其他输入支路同理。
一个输入支路，可以被配置为当输入支路被选中时，将引脚接入的电平信号转换为第一电平信号。
其中，引脚接入的电平信号可以是模拟信号，上述第一电平信号可以是数字信号。
第一电平信号与目标通信电平相适配，且该第一电平信号用于接入下一级电路。相适配可以是指高低电平逻辑匹配。例如，设引脚接入的电平信号为1.8V，在电源电压为1.8V的电路中可以被判定为高电平，但是在电源电压为3.3V的电路中可能被判定为低电平，若在正确的电路逻辑中需要将接入的1.8V作为高电平，则在电源电压为1.8V的电路中高低电平逻辑匹配，电路可以正确运行，也即是相适配；但在电源电压为3.3V的电路中高低电平逻辑不匹配，电路可能执行错误动作，也即是不适配。
在一种可能的实施方式中，输入支路的输入端与引脚连接，用于接收外部电路输入的电平信号；输出端与下一级电路连接，将输出的电平信号接入内部电路。
当IO电路与外部电路连接时，可以确定外部电路所适用的电源电压，也即是确定目标通信电平，并通过内部逻辑确定与目标通信电平相适配的一个目标输入支路。进而，可以选中该目标输入支路。示例性的，可以通过01信号指示输入支路是否被选中，例如，当存在2个输入支路时，“01”表示选中第二个输入支路，“10”表示选中第一个输入支路。
当输入支路被选中时，可以将该目标输入支路配置为有效，该输入支路(即目标输入支路)可以正常工作，将外部电路输入的电平信号转换为第一电平信号。
当输入支路未被选中时，该输入支路可以被配置为有效，也可以被配置为无效。
优选的，当输入支路未被选中时，将该输入支路配置为无效。当输入支路无效时，该 输入支路不对外部电路输入的电平信号进行处理，输出无效信号。在此基础上，可以降低未被选中的输入支路的功耗。
由于存在多个输入支路，可以通过多路选择将目标输入支路输出的第一电平信号接入下一级电路，本实施例对此不作限定。示例性的，可以将上述01信号接入多路选择器，通过多路选择器将目标输入支路输出的第一电平信号选出，例如，基于信号“01”可以将第二个输入支路的信号选出，基于信号“10”可以将第一个输入支路的信号选出。
可选的，参照图2所示的输入支路示意图，输入支路还可以包括控制模块。该控制模块可以用于控制输入支路是否有效。
控制模块可以用于接收输入支路的使能控制信号，被配置为当输入支路被选中时，基于第一电平控制输入支路有效；当输入支路未被选中时，基于第二电平控制输入支路无效。
当输入支路对应的电源电压与目标通信电平相适配时，上述使能控制信号可以被配置为第一电平。当输入支路对应的电源电压与目标通信电平不适配时，上述使能控制信号可以被配置为第二电平。
其中，一个输入支路与一个使能控制信号相对应。
在芯片应用中，根据实际场景确定每个输入支路的电源电压是否与目标通信电平相适配。如果相适配，则可以将对该输入支路的使能控制信号配置为第一电平；如果不适配，则可以将对该输入支路的使能控制信号配置为第二电平。示例性的，第一电平可以是高电平，第二电平与第一电平相反，可以是低电平。当然，也可以是第一电平为低电平、第二电平为高电平，本实施例对具体的使能控制信号不作限定。
进而，可以将第一电平的使能控制信号接入目标输入支路，以此将目标输入支路配置为有效；将第二电平的使能控制信号接入其余输入支路，以此将其余输入支路配置为无效。
可选的，控制模块可以设置在输入支路的接地端，以控制输入支路是否接地。或者，控制模块还可以设置在输入支路接电源的一端，以控制是否将电源电压接入输入支路。本实施例对控制模块具体的设置位置不作限定。
可选的，控制模块可以包括第一场效应管，第一场效应管的控制端用于接入使能控制信号。
示例性的，以控制模块设置在接地端、第一场效应管为NMOS(N-Metal-Oxide-Semiconductor，N型金属-氧化物-半导体)管为例。参照图3所示的控制模块示意图，第一场效应管的控制端(即栅极)可以用于接入使能控制信号，源极可以用于接地，漏极可以用于与输入支路的接地端连接。此时的第一电平可以是高电平。当第一场效应管的控制端接入高电平时，第一场效应管导通，输入支路可以接地形成通路，可以正常工作；当第一场效应管的控制端接入低电平时，第一场效应管关断，输入支路未接地， 处于高阻态。
当然，第一场效应管还可以是PMOS(P-Metal-Oxide-Semiconductor，P型金属-氧化物-半导体)管，本实施例对第一场效应管的具体类型不作限定。此时，第一电平可以是低电平，第一场效应管的输入端可以用于与输入支路的接地端连接，输出端可以用于接地。
可选的，参照图4所示的输入支路示意图，输入支路可以包括电平检测模块和输入模块，电平检测模块的输出端与输入模块的输入端连接。
电平检测模块，可以用于基于引脚接入的电平信号和设定阈值，输出检测信号。
输入模块，可以用于将检测信号转换为第一电平信号。
在一种可能的实施方式中，电平检测模块的输入端可以与引脚连接，输出端可以与输入模块的输入端连接；输入模块的输入端可以与电平检测模块的输出端连接，输出端可以与下一级电路连接，用于将检测信号转换为第一电平信号，接入内部电路。
在电平检测模块和输入模块构成的输入支路中，可以将外部电路输入的电平信号与设定阈值进行比较，判断是否高于或是否低于设定阈值，检测该电平信号为高电平或低电平，该设定阈值可以与输入支路的电源电压相关。例如，设定阈值可以是电源电压的二分之一，设电源电压为3V，则设定阈值可以是1.5V。如果输入的电平信号为1.3V，低于设定阈值，属于低电平，则检测信号可以为低电平；如果输入的电平信号为2.5V，高于设定阈值，属于高电平，则检测信号可以为高电平。本实施例对具体的设定阈值不作限定。
在一种具体的实施方式中，参照图5所示的输入支路示意图，电平检测模块可以由一对并联的PMOS管和NMOS管构成，其中，PMOS管的栅极与引脚连接，源极与NMOS管的漏极连接，漏极用于接收电源电压，NMOS管的栅极与引脚连接，漏极与NMOS管的源极连接，源极用于接地。此时，PMOS管和NMOS管可以用于实现反相功能，也即是当引脚接入高电平时，电平检测模块可以输出低电平，当引脚接入低电平时，电平检测模块可以输出高电平。相对应的，输入模块可以用于实现反相功能，例如可以由一个反相器构成，将电平检测模块输出的高电平转换为低电平，将电平检测模块输出的低电平转换为高电平。由此可以基于电平检测模块和输入模块实现缓冲的功能，当引脚接入高电平时，输入支路输出的第一电平信号可以是相应的高电平，当引脚接入低电平时，输入支路输出的第一电平信号可以是相应的低电平。
本实施例对电平检测模块和输入模块的具体电路结构不作限定。
示例性的，当图3所示的控制模块与图5所示的电平检测模块、输入模块相结合时，可以构成如图6所示的IO电路。该IO电路的具体实现原理在上文已经介绍，此处不再赘述。
可选的，当输入支路处于高阻态时，接入内部电路的电平信号可能是高电平，也可能 是低电平，处于不稳定的状态，可能造成漏电问题，因此，参照图7所示的IO电路示意图，IO电路还可以包括默认状态设定模块。
默认状态设定模块，被配置为当输入支路无效时，将一确定电平接入输入模块的输入端。当输入支路处于高阻态时，输入模块的输入端也可以接入一确定电平，使得输入模块可以输出确定的电平信号，避免不稳定的状态，可以解决漏电问题。
可选的，默认状态设定模块包括第二场效应管，第二场效应管的控制端用于接收上述使能控制信号，或接入与上述使能控制信号相反的信号。
当输入支路有效时，第二场效应管可以关断，不影响检测信号接入输入模块；当输入支路无效时，第二场效应管可以导通，将一确定电平接入输入模块。因此，第二场效应管接入的使能控制信号可能与上述接入控制模块的使能控制信号相同或相反，与第二场效应管的类型相关。例如，当输入支路为高电平使能时，若第二场效应管为PMOS管，为低电平使能，则第二场效应管的控制端可以用于接收与输入电路的使能控制信号相同的信号；若第二场效应管为NMOS管，为高电平使能，则第二场效应管的控制端可以用于接入与输入电路的使能控制信号相反的信号。当输入支路为低电平使能时同理，不再赘述。
在一种具体的实施方式中，参照图8所示的默认状态设定模块示意图，第二场效应管为PMOS管，源极与输入模块的输入端连接，漏极用于接收电源电压。当输入支路被配置为无效时，第二场效应管导通，将电源电压接入输入模块。
当然，接入输入模块的确定电平还可以是其他的取值，本实施例对该确定电平的具体取值不作限定。
示例性的，当图6所示的IO电路与图8所示的默认状态设定模块相结合时，可以构成如图9所示的IO电路。该IO电路的具体实现原理在上文已经介绍，此处不再赘述。
可选的，当输入支路对应的电源电压与下一级电路所适用的电源电压不一致时，输入支路还可以包括电平转换模块。
电平转换模块，用于将第一电平信号转换为第二电平信号。
其中，第二电平信号与下一级电路所适用的电源电压相适配，以便下一级电路进行处理。第一电平信号和第二电平信号均为数字信号。
参照图10所示的输入支路示意图，电平转换模块的输入端可以用于接收第一电平信号，输出端可以用于输出第二电平信号。电平转换模块可以采用现有的电路结构，能够实现电平转换即可，本实施例对电平转换模块的具体电路结构不作限定。
示例性的，设输入支路的电源电压为3V，若第一电平信号为高电平，则相应的电压可以为3V；若第一电平信号为低电平，则相应的电压可以为0.1V。当下一级电路的电源电压为1.5V时，则在第一电平信号为高电平时，电平转换模块可以将3.3V转换为1.5V，得到 的第二电平信号在下一级电路中可以作为高电平；在第一电平信号为低电平时，电平转换模块可以将0.1V转换为0.05V，得到的第二电平信号在下一级电路中可以作为低电平。
图11示出了一种具体的IO电路示意图，包括输出支路和多个并联的输入支路。其中多个并联的输入支路的实现原理在上文已经介绍，此处不再赘述。输出支路包括输出控制和上下拉控制逻辑模块、用于驱动的场效应管、上拉电阻和下拉电阻，用于将内部电路输出的信号接入引脚，传输至外部电路。输出控制逻辑模块用于控制输出的使能，以及输出方式(推挽输出或开漏输出)、输出电流大小等。本实施例对输出支路的电路结构及其实现方式不作限定。
本申请实施例至少可以获得如下有益效果：
(1)IO电路可以包括多个输入支路，每个输入支路具有确定的电源电压，无需进行电源的切换，将对电源的切换转换为对输入支路的选择。相比于电源切换电路，本申请提供的IO电路结构简单，占用芯片的面积减少。
(2)在IO电路面积减少的基础上，相应的ESD保护电路设计复杂度降低，性能提高，进而可以提高芯片的鲁棒性。
(3)现有的切换电源的方案中，不同的电源电压所使用的输入支路是相同的，因此输入支路中的器件需要适应大多数的电源电压，可能存在不匹配的情况，影响电路性能。本申请提供的IO电路中，每个输入支路的电路结构可以是一样的，器件尺寸可以根据不同电源域的要求有所差异，与对应的电源电压相匹配，可以提高IO电路性能。
本申请实施例提供了一种适用于上文IO电路的控制方法，具体的实现方式在上文中已经介绍，本实施例不再赘述。参照图12所示的控制方法流程图，该方法包括：
步骤1201，根据与外部电路的目标通信电平，确定与目标通信电平相适配的目标输入支路；
步骤1202，基于目标输入支路，将引脚接入的电平信号转换为第一电平信号；
步骤1203，将第一电平信号接入下一级电路。
其中，第一电平信号与目标通信电平相适配。
可选的，所述输入支路还包括控制模块，所述控制模块用于接收所述输入支路的使能控制信号，所述方法还包括：
通过所述控制模块，当所述输入支路被选中时，基于第一电平的使能控制信号控制所述输入支路有效；当所述输入支路未被选中时，基于第二电平的使能控制信号控制所述输入支路无效。
可选的，所述方法还包括：
当所述输入支路对应的电源电压与所述目标通信电平相适配时，将使能控制信号配置为所述第一电平；
当所述输入支路对应的电源电压与所述目标通信电平不适配时，将使能控制信号配置为所述第二电平。
可选的，所述控制模块包括第一场效应管，所述第一场效应管的控制端用于接入所述使能控制信号。
可选的，所述输入支路包括电平检测模块和输入模块，所述将引脚接入的电平信号转换为第一电平信号，包括：
通过所述电平检测模块，基于所述引脚接入的电平信号和设定阈值，输出检测信号；
通过所述输入模块，将所述检测信号转换为所述第一电平信号。
可选的，所述IO电路还包括默认状态设定模块，所述方法还包括：
当所述输入支路无效时，控制所述默认状态设定模块将一确定电平接入所述输入模块的输入端。
可选的，所述默认状态设定模块包括第二场效应管，所述第二场效应管的控制端用于接收所述使能控制信号，或接收与所述使能控制信号相反的信号。
可选的，当所述输入支路对应的电源电压与所述下一级电路所适用的电源电压不一致时，所述输入支路还包括电平转换模块，所述方法还包括：
通过所述电平转换模块，将所述第一电平信号转换为第二电平信号，所述第二电平信号与所述下一级电路所适用的电源电压相适配。
本申请实施例至少可以获得如下有益效果：
(1)IO电路可以包括多个输入支路，每个输入支路具有确定的电源电压，无需进行电源的切换，将对电源的切换转换为对输入支路的选择。相比于电源切换电路，本申请提供的IO电路结构简单，占用芯片的面积减少。
(2)在IO电路面积减少的基础上，相应的ESD保护电路设计复杂度降低，性能提高，进而可以提高芯片的鲁棒性。
(3)现有的切换电源的方案中，不同的电源电压所使用的输入支路是相同的，因此输入支路中的器件需要适应大多数的电源电压，可能存在不匹配的情况，影响电路性能。本申请提供的IO电路中，每个输入支路的电路结构可以是一样的，器件尺寸可以根据不同电源域的要求有所差异，与对应的电源电压相匹配，可以提高IO电路性能。
本申请示例性实施例还提供一种芯片，包括本申请实施例提供的适用于多电平通信的IO电路。
本申请示例性实施例还提供一种电子设备，包括：本申请实施例提供的适用于多电平通信的IO电路；至少一个处理器；以及与至少一个处理器通信连接的存储器。存储器存储有能够被至少一个处理器执行的计算机程序。
参考图13，现将描述可以作为本申请的电子设备1300的结构框图，其是可以应用于本申请的各方面的硬件设备的示例。电子设备旨在表示各种形式的数字电子的计算机设备，诸如，数据中心服务器、笔记本电脑、客户机、膝上型计算机、台式计算机、工作站、个人数字助理、刀片式服务器、大型计算机、和其它适合的计算机。电子设备还可以表示各种形式的移动装置，诸如，个人数字处理、蜂窝电话、智能电话、可穿戴设备和其它类似的计算装置。本文所示的部件、它们的连接和关系、以及它们的功能仅仅作为示例，并且不意在限制本文中描述的和/或者要求的本申请的实现。
如图13所示，电子设备1300包括计算单元1301，其可以根据存储在只读存储器(ROM)1302中的计算机程序或者从存储单元1308加载到随机访问存储器(RAM)1303中的计算机程序，来执行各种适当的动作和处理。在RAM 1303中，还可存储设备1300操作所需的各种程序和数据。计算单元1301、ROM 1302以及RAM 1303通过总线1304彼此相连。输入/输出(I/O)接口1305也连接至总线1304。
电子设备1300中的多个部件连接至I/O接口1305，包括：输入单元1306、输出单元1307、存储单元1308以及通信单元1309。输入单元1306可以是能向电子设备1300输入信息的任何类型的设备，输入单元1306可以接收输入的数字或字符信息，以及产生与电子设备的用户设置和/或功能控制有关的键信号输入。输出单元1307可以是能呈现信息的任何类型的设备，并且可以包括但不限于显示器、扬声器、视频/音频输出终端、振动器和/或打印机。存储单元1304可以包括但不限于磁盘、光盘。通信单元1309允许电子设备1300通过诸如因特网的计算机网络和/或各种电信网络与其他设备交换信息/数据，并且可以包括但不限于调制解调器、网卡、红外通信设备、无线通信收发机和/或芯片组，例如蓝牙设备、WiFi设备、WiMax设备、蜂窝通信设备和/或类似物。
计算单元1301可以是各种具有处理和计算能力的通用和/或专用处理组件。计算单元1301的一些示例包括但不限于中央处理单元(CPU)、图形处理单元(GPU)、各种专用的人工智能(AI)计算芯片、各种运行机器学习模型算法的计算单元、数字信号处理器(DSP)、以及任何适当的处理器、控制器、微控制器等。计算机程序的部分或者全部可以经由ROM1302和/或通信单元1309而被载入和/或安装到电子设备1300上。
程序代码可以采用一个或多个编程语言的任何组合来编写。这些程序代码可以提供给通用计算机、专用计算机或其他可编程数据处理装置的处理器或控制器，使得程序代码当由处理器或控制器执行时使流程图和/或框图中所规定的功能/操作被实施。程序代码可以完 全在机器上执行、部分地在机器上执行，作为独立软件包部分地在机器上执行且部分地在远程机器上执行或完全在远程机器或服务器上执行。
在本申请的上下文中，机器可读介质可以是有形的介质，其可以包含或存储以供指令执行系统、装置或设备使用或与指令执行系统、装置或设备结合地使用的程序。机器可读介质可以是机器可读信号介质或机器可读储存介质。机器可读介质可以包括但不限于电子的、磁性的、光学的、电磁的、红外的、或半导体系统、装置或设备，或者上述内容的任何合适组合。机器可读存储介质的更具体示例会包括基于一个或多个线的电气连接、便携式计算机盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦除可编程只读存储器(EPROM或快闪存储器)、光纤、便捷式紧凑盘只读存储器(CD-ROM)、光学储存设备、磁储存设备、或上述内容的任何合适组合。
如本申请使用的，术语“机器可读介质”和“计算机可读介质”指的是用于将机器指令和/或数据提供给可编程处理器的任何计算机程序产品、设备、和/或装置(例如，磁盘、光盘、存储器、可编程逻辑装置(PLD))，包括，接收作为机器可读信号的机器指令的机器可读介质。术语“机器可读信号”指的是用于将机器指令和/或数据提供给可编程处理器的任何信号。
为了提供与用户的交互，可以在计算机上实施此处描述的系统和技术，该计算机具有：用于向用户显示信息的显示装置(例如，CRT(阴极射线管)或者LCD(液晶显示器)监视器)；以及键盘和指向装置(例如，鼠标或者轨迹球)，用户可以通过该键盘和该指向装置来将输入提供给计算机。其它种类的装置还可以用于提供与用户的交互；例如，提供给用户的反馈可以是任何形式的传感反馈(例如，视觉反馈、听觉反馈、或者触觉反馈)；并且可以用任何形式(包括声输入、语音输入或者、触觉输入)来接收来自用户的输入。
可以将此处描述的系统和技术实施在包括后台部件的计算系统(例如，作为数据服务器)、或者包括中间件部件的计算系统(例如，应用服务器)、或者包括前端部件的计算系统(例如，具有图形用户界面或者网络浏览器的用户计算机，用户可以通过该图形用户界面或者该网络浏览器来与此处描述的系统和技术的实施方式交互)、或者包括这种后台部件、中间件部件、或者前端部件的任何组合的计算系统中。可以通过任何形式或者介质的数字数据通信(例如，通信网络)来将系统的部件相互连接。通信网络的示例包括：局域网(LAN)、广域网(WAN)和互联网。
计算机系统可以包括客户端和服务器。客户端和服务器一般远离彼此并且通常通过通信网络进行交互。通过在相应的计算机上运行并且彼此具有客户端-服务器关系的计算机程序来产生客户端和服务器的关系。
以上对本申请所提供一种适用于多电平通信的IO电路及其控制方法进行了详细介绍， 本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (11)

  1. 一种适用于多电平通信的IO电路，所述IO电路包括多个输入支路，每个输入支路的电源电压不同；
    所述输入支路，被配置为当所述输入支路被选中时，将引脚接入的电平信号转换为第一电平信号，其中，所述第一电平信号与目标通信电平相适配，且所述第一电平信号用于接入下一级电路。
  2. 根据权利要求1所述的IO电路，其中，所述输入支路还包括控制模块；
    所述控制模块用于接收所述输入支路的使能控制信号，被配置为当所述输入支路被选中时，基于第一电平的使能控制信号控制所述输入支路有效；当所述输入支路未被选中时，基于第二电平的使能控制信号控制所述输入支路无效。
  3. 根据权利要求2所述的IO电路，其中，当所述输入支路对应的电源电压与所述目标通信电平相适配时，使能控制信号被配置为所述第一电平；
    当所述输入支路对应的电源电压与所述目标通信电平不适配时，使能控制信号被配置为所述第二电平。
  4. 根据权利要求2所述的IO电路，其中，所述控制模块包括第一场效应管，所述第一场效应管的控制端用于接入所述使能控制信号。
  5. 根据权利要求2所述的IO电路，其中，所述输入支路包括电平检测模块和输入模块；
    所述电平检测模块，用于基于所述引脚接入的电平信号和设定阈值，输出检测信号；
    所述输入模块，用于将所述检测信号转换为所述第一电平信号。
  6. 根据权利要求5所述的IO电路，其中，所述IO电路还包括默认状态设定模块；
    所述默认状态设定模块，被配置为当所述输入支路无效时，将一确定电平接入所述输入模块的输入端。
  7. 根据权利要求6所述的IO电路，其中，所述默认状态设定模块包括第二场效应管，所述第二场效应管的控制端用于接收所述使能控制信号，或接收与所述使能控制信号相反的信号。
  8. 根据权利要求1所述的IO电路，其中，当所述输入支路对应的电源电压与所述下一级电路所适用的电源电压不一致时，所述输入支路还包括电平转换模块；
    所述电平转换模块，用于将所述第一电平信号转换为第二电平信号，所述第二电平信号与所述下一级电路所适用的电源电压相适配。
  9. 一种适用于多电平通信的IO电路的控制方法，所述IO电路包括多个输入支路，每个输入支路的电源电压不同，所述方法包括：
    根据与外部电路的目标通信电平，确定与所述目标通信电平相适配的目标输入支路；
    基于所述目标输入支路，将引脚接入的电平信号转换为第一电平信号，其中，所述第一电平信号与所述目标通信电平相适配；
    将所述第一电平信号接入下一级电路。
  10. 一种芯片，包括如权利要求1-8中任一项所述的适用于多电平通信的IO电路。
  11. 一种电子设备，包括如权利要求1-8中任一项所述的适用于多电平通信的IO电路。
PCT/CN2023/087778 2022-04-22 2023-04-12 一种适用于多电平通信的io电路及其控制方法 WO2023202440A1 (zh)

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