WO2023201824A1 - 单端转差分麦克风电路 - Google Patents

单端转差分麦克风电路 Download PDF

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Publication number
WO2023201824A1
WO2023201824A1 PCT/CN2022/093937 CN2022093937W WO2023201824A1 WO 2023201824 A1 WO2023201824 A1 WO 2023201824A1 CN 2022093937 W CN2022093937 W CN 2022093937W WO 2023201824 A1 WO2023201824 A1 WO 2023201824A1
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Prior art keywords
capacitor
terminal
positive
negative
signal
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Ceased
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PCT/CN2022/093937
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English (en)
French (fr)
Inventor
韩冬
蔡东记
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AAC Technologies Holdings Shenzhen Co Ltd
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AAC Acoustic Technologies Shenzhen Co Ltd
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Priority to JP2022579859A priority Critical patent/JP7586943B2/ja
Priority to US17/918,894 priority patent/US12289082B2/en
Publication of WO2023201824A1 publication Critical patent/WO2023201824A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/181—Low-frequency amplifiers, e.g. audio preamplifiers
    • H03F3/183—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; ELECTRIC HEARING AIDS; PUBLIC ADDRESS SYSTEMS
    • H04R19/00—Electrostatic transducers
    • H04R19/04—Microphones
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/181—Low-frequency amplifiers, e.g. audio preamplifiers
    • H03F3/183—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
    • H03F3/187—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/38—DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers
    • H03F3/387—DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45237—Complementary long tailed pairs having parallel inputs and being supplied in series
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45636—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by using feedback means
    • H03F3/45641—Measuring at the loading circuit of the differential amplifier
    • H03F3/45645—Controlling the input circuit of the differential amplifier
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; ELECTRIC HEARING AIDS; PUBLIC ADDRESS SYSTEMS
    • H04R3/00—Circuits for transducers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/03—Indexing scheme relating to amplifiers the amplifier being designed for audio applications
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45526—Indexing scheme relating to differential amplifiers the FBC comprising a resistor-capacitor combination and being coupled between the LC and the IC
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; ELECTRIC HEARING AIDS; PUBLIC ADDRESS SYSTEMS
    • H04R2201/00—Details of transducers, loudspeakers or microphones covered by H04R1/00 but not provided for in any of its subgroups
    • H04R2201/003—Mems transducers or their use

Definitions

  • the present invention relates to the field of electroacoustic conversion, and in particular, to a single-ended to differential microphone circuit.
  • MEMS Microelectro Mechanical Systems
  • MEMS microphones are microphones manufactured based on MEMS sensor technology. They have improved noise cancellation performance, good radio frequency performance and electromagnetic interference suppression capabilities. They are widely used in smartphones, wire-controlled headphones, tablets and notebooks and other electronic products.
  • the single-ended signal output by the MEMS microphone is usually converted into a differential signal for transmission.
  • the output terminal of the MEMS microphone is directly connected to the positive input terminal of the fully differential amplifier Amp, and the compensation capacitor CDMY is connected to the negative input terminal of the fully differential amplifier Amp.
  • the substrate of the sensor will produce a large parasitic capacitance to the ground, causing the amplitude of the signal output by the substrate to be smaller than the amplitude of the signal output by the signal terminal of the sensor.
  • the signal output by the substrate It is transmitted to the negative input terminal of the fully differential amplifier Amp, and the signal terminal of the sensor is transmitted to the positive input terminal of the fully differential amplifier Amp.
  • the purpose of the present invention is to provide a single-ended to differential microphone circuit that can use a current common amplifier with a small input common-mode voltage range and low noise to realize single-ended conversion of signals to differential, which is beneficial to improving the signal-to-noise ratio of the circuit.
  • the present invention provides a single-ended to differential microphone circuit, including a power supply end for inputting a first bias voltage, a microphone capacitor, a coupling capacitor, a first primary amplifier, a second primary amplifier, and a signal processing module. , current sharing amplifier, positive terminal feedback resistor, positive terminal feedback capacitor, negative terminal feedback resistor and negative terminal feedback capacitor; wherein, the microphone capacitor is equivalently formed when the microphone is connected to the single-ended to differential microphone circuit;
  • the power supply terminal is connected to the bias voltage input terminal of the microphone capacitor, and the output terminal of the microphone capacitor is connected to the input terminal of the first primary amplifier;
  • the positive electrode of the coupling capacitor is grounded or connected to the bias voltage input terminal.
  • the microphone circuit also includes a series connection between the power supply terminal and the bias voltage input terminal. a first bias resistor between the bias voltage input terminals, and the negative electrode of the coupling capacitor is connected to the input terminal of the second primary amplifier;
  • the output end of the first primary amplifier and the output end of the second primary amplifier are respectively connected to the positive input end and the negative input end of the signal processing module, and the positive output end and negative output end of the signal processing module are respectively connected to the
  • the positive input terminal and the negative input terminal of the current common amplifier are connected to adjust the output signals of the first primary amplifier and the second primary amplifier into target differential signals with equal amplitude and opposite phase through the signal processing module, and Output the target differential signal to the current sharing amplifier;
  • the positive terminal feedback resistor and the positive terminal feedback capacitor are both connected in parallel between the positive input terminal and the negative output terminal of the current sharing amplifier, and the negative terminal feedback resistor and the negative terminal feedback capacitor are both connected in parallel to the Current is shared between the negative input and positive output of the amplifier.
  • the signal processing module includes a signal multiplier, which is specifically used for:
  • the difference signal is output from the positive output terminal of the signal processing module, and the difference inverted signal is output from the negative output terminal of the signal processing module.
  • the signal multiplier includes four switched capacitors, each of the switched capacitors includes two first switches, two second switches and a capacitor, and the four switched capacitors are a first switched capacitor, a third switched capacitor respectively.
  • the positive electrode of the capacitor of the first switched capacitor is connected to the positive input terminal of the signal processing module through a first switch, and is connected to the positive input terminal of the signal processing module through a second switch.
  • the negative electrode of the capacitor is connected to the negative input end of the signal processing module through another first switch, and is connected to the input common mode voltage through another second switch;
  • the positive electrode of the capacitor of the second switched capacitor is connected to the positive input terminal of the signal processing module through a first switch, and is connected to the input common mode voltage through a second switch.
  • the negative electrode is connected to the negative input terminal of the signal processing module through another first switch, and is connected to the negative output terminal of the signal processing module through another second switch;
  • the positive electrode of the capacitor of the third switched capacitor is connected to the positive output terminal of the signal processing module through one of the first switches, and is connected to the positive input terminal of the signal processing module through one of the second switches.
  • the negative electrode of the capacitor is connected to the input common mode voltage through another first switch, and is connected to the negative input terminal of the signal processing module through another second switch;
  • the positive electrode of the capacitor of the fourth switched capacitor is connected to the input common mode voltage through a first switch, and is connected to the positive input terminal of the signal processing module through a second switch.
  • the negative electrode is connected to the negative output terminal of the signal processing module through another first switch, and is connected to the negative input terminal of the signal processing module through another second switch;
  • All the first switches and the second switches are controlled by the set clock signal.
  • the clock signal When the clock signal is in the first phase, all the first switches are closed and all the second switches are open; when the clock signal is in the first phase, all the first switches are closed and all the second switches are open;
  • the clock signal When the clock signal is a second phase opposite to the first phase, all the first switches are turned off and all the second switches are turned on.
  • the single-ended to differential microphone circuit also includes a first chopper switch and a second chopper switch;
  • the first chopper switch is connected in series between the output terminal of the microphone and the input terminal of the first primary amplifier through an input terminal and an output terminal, and the first chopper switch passes through another input terminal and another An output terminal is connected in series between the negative electrode of the coupling capacitor and the input terminal of the second primary amplifier;
  • the second chopper switch is connected in series between the output terminal of the first primary amplifier and the positive input terminal of the signal processing module through an input terminal and an output terminal.
  • the second chopper switch passes through another input terminal.
  • the terminal and the other output terminal are connected in series between the output terminal of the second primary amplifier and the negative input terminal of the signal processing module.
  • the current sharing amplifier includes a bias current source, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor;
  • the source of the first PMOS transistor and the source of the second PMOS transistor are both connected to the output end of the bias current source, and the gate of the first PMOS transistor is connected to the gate of the first NMOS transistor.
  • the drains of the first PMOS transistor, the drain of the first NMOS transistor and the gate of the third NMOS transistor are connected and serve together as the positive input end of the current sharing amplifier. The current shares the negative output terminal of the amplifier;
  • the gate of the second PMOS transistor is connected to the gate of the second NMOS transistor and together serve as the negative input terminal of the current sharing amplifier, and the drain of the second PMOS transistor is connected to the gate of the second NMOS transistor.
  • the drain and the gate of the fourth NMOS transistor are connected and together serve as the positive output terminal of the current sharing amplifier;
  • the source of the first NMOS transistor is connected to the drain of the third NMOS transistor, the source of the second NMOS transistor, and the drain of the fourth NMOS transistor;
  • the source of the third NMOS transistor and the source of the fourth NMOS transistor are both grounded.
  • the single-ended to differential microphone circuit also includes a second bias resistor and a third bias resistor;
  • One end of the second bias resistor is connected to the input end of the first primary amplifier, and the other end of the second bias resistor is used to input a second bias voltage; one end of the third bias resistor is connected to the input end of the first primary amplifier. The input end of the second primary amplifier is connected, and the other end of the third bias resistor is used to input the second bias voltage.
  • the first bias voltage is greater than the second bias voltage.
  • the resistance value of the first bias resistor ranges from 100G ⁇ to 200G ⁇ .
  • the positive terminal feedback resistor and the negative terminal feedback resistor have the same resistance value, and the positive terminal feedback capacitor and the negative terminal feedback capacitor have the same capacitance value.
  • the microphone circuit of the present invention includes a power supply terminal for inputting a first bias voltage, a microphone capacitor, a coupling capacitor, a first primary amplifier, a second primary amplifier, a signal processing module, and a current sharing amplifier.
  • positive terminal feedback resistor, positive terminal feedback capacitor, negative terminal feedback resistor, negative terminal feedback capacitor, first output terminal and second output terminal; the microphone and the coupling capacitor are respectively connected to the input terminal of the first primary amplifier is connected to the input end of the second primary amplifier, and the output end of the first primary amplifier and the output end of the second primary amplifier are respectively connected to the positive input end and the negative input end of the signal processing module.
  • the signal processing module The positive output terminal and the negative output terminal are respectively connected to the positive input terminal and the negative input terminal of the current sharing amplifier to adjust the output signals of the first primary amplifier and the second primary amplifier through the signal processing module.
  • the target differential signal is a target differential signal with equal amplitude and opposite phase, and the target differential signal is output to the current common amplifier, so that a differential signal with equal amplitude and opposite phase can be output through the action of the signal processing module, so that the input common
  • a current sharing amplifier with a smaller mold voltage range and smaller noise is used to realize the output of differential signals, which is beneficial to improving the signal-to-noise ratio of the circuit.
  • Figure 1 is a circuit diagram of a single-ended to differential microphone circuit in the prior art
  • Figure 2 is a circuit diagram of a single-ended to differential microphone circuit provided by an embodiment of the present invention.
  • Figure 3 is a circuit diagram of a signal multiplier provided by an embodiment of the present invention.
  • Figure 4a is an equivalent circuit diagram of the signal multiplier shown in Figure 3 when the clock signal is in the first phase
  • Figure 4b is an equivalent circuit diagram of the signal multiplier shown in Figure 3 when the clock signal is in the second phase
  • Figure 5 is another circuit diagram of a single-ended to differential microphone circuit provided by an embodiment of the present invention.
  • FIG. 6 is a circuit diagram of a current sharing amplifier provided by an embodiment of the present invention.
  • the microphone circuit includes a power supply terminal V HCM for inputting a first bias voltage, a microphone capacitor CMEMS , a coupling capacitor C AC , a first primary amplifier Amp1, The second primary amplifier Amp2, the signal processing module 10, the current common amplifier CR-Amp, the positive terminal feedback resistor R FB1 , the positive terminal feedback capacitor C FB1 , the negative terminal feedback resistor R FB2 and the negative terminal feedback capacitor C FB2 .
  • the microphone capacitor C MEMS is equivalently formed when the microphone is connected to the single-ended to differential microphone circuit.
  • the power supply terminal V HCM is connected to the bias voltage input terminal of the microphone capacitor C MEMS , thereby providing a first bias voltage for the microphone capacitor C MEMS .
  • the first bias voltage is a high voltage bias voltage, for example It may be 13.8V, and the output end of the microphone capacitor C MEMS is connected to the input end of the first primary amplifier Amp1.
  • the anode of the coupling capacitor C AC is connected to ground, and the cathode of the coupling capacitor C AC is connected to the input end of the second primary amplifier Amp2.
  • the output terminal of the first primary amplifier Amp1 is connected to the positive input terminal VI + of the signal processing module 10, and the output terminal of the second primary amplifier Amp2 is connected to the negative input terminal VI- of the signal processing module 10.
  • the signal The positive output terminal V O+ of the processing module 10 is connected to the positive input terminal of the current sharing amplifier CR-Amp, and the negative output terminal V O- of the signal processing module 10 is connected to the negative input terminal of the current sharing amplifier CR-Amp. connected to adjust the output signals of the first primary amplifier Amp1 and the second primary amplifier Amp2 into a target differential signal with equal amplitude and opposite phase through the signal processing module 10, and output the target differential signal to The currents share the amplifier CR-Amp.
  • the positive terminal feedback resistor R FB1 and the positive terminal feedback capacitor C FB1 are both connected in parallel between the positive input terminal and the negative output terminal V OUTN of the current common amplifier CR-Amp, and the negative terminal feedback resistor R FB2 and The negative terminal feedback capacitor C FB2 is connected in parallel between the negative input terminal of the current sharing amplifier CR-Amp and the positive output terminal V OUTP .
  • the positive terminal feedback resistor R FB1 and the negative terminal feedback resistor R FB2 may have the same resistance value, and the positive terminal feedback capacitor C FB1 and the negative terminal feedback capacitor C FB2 may have the same capacitance value.
  • the current common amplifier CR-Amp is a fully differential amplifier with dual-end input and double-end output.
  • the single-ended conversion of the signal to differential is achieved through the function of the current common amplifier CR-Amp.
  • the output signals of the first primary amplifier Amp1 and the second primary amplifier Amp2 are adjusted to target differential signals with equal amplitude and opposite phase, thereby allowing the input to the fully differential amplifier in the subsequent circuit
  • the differential signals have equal amplitude and opposite phase, which can make the input common mode voltage range smaller.
  • the fully differential amplifier in the subsequent circuit can be implemented by using the current sharing amplifier CR-Amp with a small input common mode voltage range, and the current sharing amplifier Compared with fully differential amplifiers with a large input common-mode voltage range, CR-Amp has smaller noise, which can reduce the impact of the current common amplifier CR-Amp's own noise on the entire circuit, which is beneficial to improving the signal-to-noise of the microphone circuit. Compare.
  • the signal processing module 10 of the present invention includes a signal multiplier, which is specifically used to subtract the output signal of the second primary amplifier Amp2 from the output signal of the first primary amplifier Amp1 to obtain a difference. signal; then perform inversion processing on the difference signal to obtain a difference inversion signal, the difference signal and the difference inversion signal constitute the target differential signal; and also used to convert the difference signal
  • the signal is output from the positive output terminal of the signal processing module 10
  • the difference inverted signal is output from the negative output terminal of the signal processing module 10 .
  • the signal multiplier can be used to adjust the output signals of the first primary amplifier Amp1 and the second primary amplifier Amp2 into a target differential signal with equal amplitude and opposite phase, and the two signals of the target differential signal
  • the amplitude difference is doubled compared to the amplitude difference before adjustment, which is beneficial to reducing the impact of the current sharing amplifier in the subsequent circuit on the signal-to-noise ratio of the entire circuit.
  • the signal multiplier includes four switched capacitors, each of the switched capacitors includes two first switches S1, two second switches S2 and a capacitor.
  • the four switched capacitors are the first switched capacitor 101, the second switched capacitor 102, the third switched capacitor 103 and the fourth switched capacitor 104;
  • the positive electrode of the capacitor C1 of the first switched capacitor 101 is connected to the positive input terminal VI+ of the signal processing module 10 through a first switch S1, and is connected to the positive input terminal VI + of the signal processing module 10 through a second switch S2.
  • the positive output terminal V O+ of the signal processing module 10 and the negative electrode of the capacitor C1 are connected to the negative input terminal VI- of the signal processing module 10 through another first switch S1, and through another first switch S1
  • the second switch S2 is connected to the input common mode voltage V CM .
  • the positive electrode of the capacitor C2 of the second switched capacitor 102 is connected to the positive input terminal VI + of the signal processing module 10 through a first switch S1, and is connected to the input through a second switch S2.
  • Common mode voltage V CM the negative electrode of the capacitor C2 is connected to the negative input terminal V I- of the signal processing module 10 through another first switch S1, and is connected to the negative input terminal V I- through another second switch S2.
  • the positive electrode of the capacitor C3 of the third switched capacitor 103 is connected to the positive output terminal V O+ of the signal processing module 10 through a first switch S1, and is connected to the positive output terminal V O+ of the signal processing module 10 through a second switch S2.
  • the positive input terminal V I+ of the signal processing module 10 the negative electrode of the capacitor C3 is connected to the input common mode voltage V CM through another first switch S1, and is connected to the input common mode voltage V CM through another second switch S2.
  • the negative input terminal V I- of the signal processing module 10 is connected to the positive output terminal V O+ of the signal processing module 10 through a first switch S1, and is connected to the positive output terminal V O+ of the signal processing module 10 through a second switch S2.
  • the positive electrode of the capacitor C4 of the fourth switched capacitor 104 is connected to the input common mode voltage V CM through a first switch S1, and is connected to the signal processing module 10 through a second switch S2.
  • the positive input terminal V I+ , the negative electrode of the capacitor C4 is connected to the negative output terminal V O- of the signal processing module 10 through another first switch S1 , and is connected to the negative output terminal V O- through another second switch S2
  • All the first switches S1 and the second switches S2 are controlled by the set clock signal.
  • the clock signal is the first phase S01
  • all the first switches S1 are closed, and all the second switches S2 is disconnected.
  • the clock signal is the second phase S02 which is opposite to the first phase S01
  • all the first switches S1 are open and all the second switches S2 are closed.
  • Figure 4a is an equivalent circuit diagram of the signal multiplier shown in Figure 3 when the clock signal is the first phase S01
  • Figure 4b is an equivalent circuit diagram of the signal multiplier shown in Figure 3 when the clock signal is the first phase S01.
  • the capacitor C1 and the capacitor C2 are connected in parallel between the positive input terminal V I+ and the negative input terminal V I- of the signal processing module 10 , and the capacitor C3 and the capacitor C4 are connected in series between the positive output terminal V of the signal processing module 10
  • the voltage difference between the capacitor C1 and the capacitor C2 is the voltage difference between the positive input terminal V I+ and the negative input terminal V I- , that is, the first primary amplifier Amp1 and the second The difference signal of the output signal of the primary amplifier Amp2; and in the second phase S02, the capacitor C1 and the capacitor C2 are connected in series between the positive output terminal V O+ and the negative output terminal V O- of the signal processing module 10, so that the capacitor C1
  • the voltage difference between the two ends of the capacitor C2 during the first phase S01 and the voltage difference between the two ends of the capacitor C2 during the first phase S01 are superimposed between the positive output terminal V O+ and the negative output terminal V O- .
  • the working principle of capacitor C3 and capacitor C4 is similar to the working principle of capacitor C1 and capacitor C2.
  • the control clock phases of the two are inverse to each other, and the phase complementary clock control of capacitor C1, capacitor C2, capacitor C3 and capacitor C4 is , so that the positive and negative output terminals of the signal processing module 10 can obtain continuous difference multiplication signals.
  • the microphone circuit further includes a first chopper switch 11 and a second chopper switch 12 .
  • the first chopper switch 11 is connected in series between the output terminal of the microphone capacitor C MEMS and the input terminal of the first primary amplifier Amp1 through an input terminal and an output terminal.
  • the first chopper switch 11 is connected through an input terminal and an output terminal.
  • the other input terminal and the other output terminal are connected in series between the negative electrode of the coupling capacitor C AC and the input terminal of the second primary amplifier Amp2.
  • the second chopper switch 12 is connected in series between the output terminal of the first primary amplifier Amp1 and the positive input terminal VI + of the signal processing module 10 through an input terminal and an output terminal.
  • the switch 12 is connected in series between the output terminal of the second primary amplifier Amp2 and the negative input terminal VI- of the signal processing module 10 through another input terminal and another output terminal.
  • the low-frequency noise of the first primary amplifier Amp1 and the second primary amplifier Amp2 can be eliminated.
  • the positive electrode of the coupling capacitor C AC can also be connected to the bias voltage input end of the microphone capacitor C MEMS .
  • the microphone circuit also It includes a first bias resistor R B1 connected in series between the power supply terminal V HCM and the bias voltage input terminal.
  • the first bias resistor R B1 is a large resistance resistor, and its resistance range may be, for example, 100G ⁇ to 200G ⁇ .
  • the microphone circuit also includes a second bias resistor RB2 and a third bias resistor RB3 .
  • One end of the second bias resistor R B2 is connected to the input end of the first primary amplifier Amp1, and the other end of the second bias resistor R B2 is used to input the second bias voltage V B ;
  • One end of the third bias resistor RB3 is connected to the input end of the second primary amplifier Amp2, and the other end of the third bias resistor RB3 is used to input the second bias voltage V B .
  • the first bias voltage is greater than the second bias voltage V B
  • the second bias voltage V B is a low voltage bias voltage, such as 0.8V.
  • the second bias resistor RB2 and the third bias resistor RB3 have the same resistance value.
  • the first bias resistor RB1 , the second bias resistor RB2 , and the third bias resistor RB3 may have the same or different resistance values, for example, they may all be 200 G ⁇ .
  • the sound signal is input from the microphone capacitor C MEMS , it is converted into an alternating current signal through the microphone capacitor C MEMS . Due to the high impedance of the first bias resistor R B1 , the alternating current signal can be passed through the first chopper.
  • the wave switch 11 is then simultaneously input to the first primary amplifier Amp1 and the second primary amplifier Amp2, and the alternating current signals input to the first primary amplifier Amp1 and the second primary amplifier Amp2 have opposite phases.
  • the low-frequency noise of the first primary amplifier Amp1 and the second primary amplifier Amp2 can be eliminated, and then the signal processing module 10 is used to process the second chopper switch 12
  • the signal after adjustment is adjusted to obtain a target differential signal with equal amplitude and opposite phase, and the amplitude of the target differential signal can also be amplified compared to before adjustment, which is beneficial to reducing the signal noise of the current sharing amplifier to the entire circuit.
  • the influence of signal-to-noise ratio is beneficial to improving the signal-to-noise ratio.
  • the capacitance values of the positive and negative terminal feedback capacitors in the prior art need to be set to the same capacitance value as the microphone capacitor C MEMS , and the capacitance value of the microphone capacitor C MEMS is usually small, so the positive , the capacitance value of the negative terminal feedback capacitor is also a small capacitance value, which will reduce the signal-to-noise ratio of the entire circuit.
  • the capacitance values of the positive and negative terminal feedback capacitors can be set It is twice the capacitance value of the microphone capacitor C MEMS .
  • the capacitance value of the positive and negative terminal feedback capacitors can be increased, thereby filtering out more noise of the current sharing amplifier itself and improving the entire microphone capacitor circuit. signal-to-noise ratio.
  • the current sharing amplifier CR-Amp includes a bias current source IB, a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3 and the fourth NMOS transistor N4.
  • the source of the first PMOS transistor P1 and the source of the second PMOS transistor P2 are both connected to the output end of the bias current source IB, and the gate of the first PMOS transistor P1 is connected to the first
  • the gate of the NMOS transistor N1 is connected and serves together as the positive input terminal V INP of the current sharing amplifier CR-Amp.
  • the drain of the first PMOS transistor P1 is connected with the drain of the first NMOS transistor N1 and the The gates of the third NMOS transistor N3 are connected and together serve as the negative output terminal V OUTN of the current sharing amplifier CR-Amp.
  • the gate of the second PMOS transistor P2 is connected to the gate of the second NMOS transistor N2 and together serve as the negative input terminal of the current sharing amplifier CR-Amp.
  • the drain of the second PMOS transistor P2 is connected to the gate of the second NMOS transistor N2.
  • the drain of the second NMOS transistor N2 and the gate of the fourth NMOS transistor N4 are connected and together serve as the positive output terminal of the current sharing amplifier CR-Amp.
  • the source of the first NMOS transistor N1 is connected to the drain of the third NMOS transistor N3, the source of the second NMOS transistor N2, and the drain of the fourth NMOS transistor N4.
  • the source of the third NMOS transistor N3 and the source of the fourth NMOS transistor N4 are both grounded.
  • the transconductance of the first PMOS transistor P1 as the input transistor and the first NMOS transistor N1 are added together and then converted into a voltage at the negative output terminal after passing through the third NMOS transistor N3 as the load.
  • V OUTN output the transconductance of the second PMOS transistor P2 as the input transistor and the second NMOS transistor N2 are added together and then converted into a voltage through the fourth NMOS transistor N4 as the load and output at the positive output terminal V OUTP , thus in the same Under bias current, the transconductance doubles, which is beneficial to reducing the noise of the current sharing amplifier CR-Amp.

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Abstract

一种单端转差分麦克风电路，包括用于输入第一偏置电压的供电端（V HCM）、麦克风电容（C MEMS）、耦合电容（C AC）、第一初级放大器（Amp1）、第二初级放大器（Amp2）、信号处理模块（10）、电流共用放大器（CR-Amp）、正端反馈电阻（R FB1）、正端反馈电容（C FB1）、负端反馈电阻（R FB2）以及负端反馈电容（C FB2），其中麦克风电容（C MEMS）连接第一初级放大器（Amp1）的输入端，耦合电容（C AC）连接第二初级放大器（Amp2）的输入端，信号处理模块（10）用于将第一初级放大器（Amp1）和第二初级放大器（Amp2）的输出信号调整为振幅相等且相位相反的目标差分信号，并将目标差分信号输出给电流共用放大器（CR-Amp），单端转差分麦克风电路利用输入共模电压范围小且噪声小的电流共用放大器（CR-Amp）实现信号的单端转差分，有利于提高电路的信噪比。

Description

单端转差分麦克风电路 技术领域
本发明涉及电声转换领域，尤其涉及一种单端转差分麦克风电路。
 背景技术
MEMS（微型机电系统，Microelectro Mechanical Systems）麦克风是基于MEMS传感器技术制造的麦克风，具有改进的噪声消除性能、良好的射频性能及电磁干扰抑制能力，被广泛应用于智能手机、线控耳机、平板以及笔记本等各类电子产品中。为了减少外界的电磁干扰、提高信号传输质量，相关技术中通常将MEMS麦克风输出的单端信号转为差分信号进行传输。
 技术问题
如图1所示，传统的单端转差分麦克风电路中， MEMS麦克风的输出端直接连接至全差分放大器Amp的正输入端，补偿电容CDMY连接至全差分放大器Amp负输入端，然而，受MEMS麦克风自身结构的限制，其传感器的衬底会对地产生较大的寄生电容，导致衬底输出的信号的振幅小于传感器的信号端输出的信号的振幅，在等效电路中衬底输出的信号传输给全差分放大器Amp的负输入端，传感器的信号端传输给全差分放大器Amp的正输入端，因此全差分放大器的正负输入端的信号振幅存在差异，相位相反，为非理想差分信号，导致正负输入端的共模电压会有较大的振幅，这就要求全差分放大器Amp必须为输入共模电压范围大的放大器，才能确保全差分放大器Amp能够正常工作，然而，此类全差分放大器的噪声通常也较大，不利于提高电路的信噪比。
 技术解决方案
本发明的目的在于提供一种单端转差分麦克风电路，可以利用输入共模电压范围小且噪声小的电流共用放大器实现信号的单端转差分，有利于提高电路的信噪比。
为了达到上述目的，本发明提供了一种单端转差分麦克风电路，包括用于输入第一偏置电压的供电端、麦克风电容、耦合电容、第一初级放大器、第二初级放大器、信号处理模块、电流共用放大器、正端反馈电阻、正端反馈电容、负端反馈电阻以及负端反馈电容；其中，所述麦克风电容为麦克风连接至所述单端转差分麦克风电路中等效形成；
所述供电端与所述麦克风电容的偏置电压输入端连接，所述麦克风电容的输出端与所述第一初级放大器的输入端连接；
所述耦合电容的正极接地或与所述偏置电压输入端连接，其中当所述耦合电容的正极与所述偏置电压输入端连接时，所述麦克风电路还包括串联在所述供电端和所述偏置电压输入端之间的第一偏置电阻，所述耦合电容的负极与所述第二初级放大器的输入端连接；
所述第一初级放大器的输出端和第二初级放大器的输出端分别与所信号处理模块的正输入端和负输入端连接，所述信号处理模块的正输出端和负输出端分别与所述电流共用放大器的正输入端和负输入端连接，以通过所述信号处理模块将所述第一初级放大器和所述第二初级放大器的输出信号调整为振幅相等且相位相反的目标差分信号，并将所述目标差分信号输出给所述电流共用放大器；
所述正端反馈电阻和所述正端反馈电容均并联于所述电流共用放大器的正输入端和负输出端之间，所述负端反馈电阻和所述负端反馈电容均并联于所述电流共用放大器的负输入端和正输出端之间。
进一步地，所述信号处理模块包括信号倍增器，所述信号倍增器具体用于：
将所述第一初级放大器的输出信号减去所述第二初级放大器的输出信号，得到差值信号；
将所述差值信号进行反相处理从而得到差值反相信号，所述差值信号和所述差值反相信号构成所述目标差分信号；
将所述差值信号从所述信号处理模块的正输出端输出，将所述差值反相信号从所述信号处理模块的负输出端进行输出。
进一步地，所述信号倍增器包括四个开关电容，每个所述开关电容包括两个第一开关、两个第二开关以及一个电容器，所述四个开关电容分别为第一开关电容、第二开关电容、第三开关电容以及第四开关电容；
其中，所述第一开关电容的所述电容器的正极通过一个所述第一开关连接至所述信号处理模块的正输入端，并通过一个所述第二开关连接至所述信号处理模块的正输出端，所述电容器的负极通过另一个所述第一开关连接至所述信号处理模块的负输入端，并通过另一个所述第二开关连接输入共模电压；
所述第二开关电容的所述电容器的正极通过一个所述第一开关连接至所述信号处理模块的正输入端，并通过一个所述第二开关连接所述输入共模电压，所述电容器的负极通过另一个所述第一开关连接至所述信号处理模块的负输入端，并通过另一个所述第二开关连接至所述信号处理模块的负输出端；
所述第三开关电容的所述电容器的正极通过一个所述第一开关连接至所述信号处理模块的正输出端，并通过一个所述第二开关连接至所述信号处理模块的正输入端，所述电容器的负极通过另一个所述第一开关连接所述输入共模电压，并通过另一个所述第二开关连接至所述信号处理模块的负输入端；
所述第四开关电容的所述电容器的正极通过一个所述第一开关连接所述输入共模电压，并通过一个所述第二开关连接至所述信号处理模块的正输入端，所述电容器的负极通过另一个所述第一开关连接至所述信号处理模块的负输出端，并通过另一个所述第二开关连接至所述信号处理模块的负输入端；
所有所述第一开关和所述第二开关受控于设定的时钟信号，当所述时钟信号为第一相位时，所有所述第一开关闭合，所有所述第二开关断开；当所述时钟信号为与所述第一相位相反的第二相位时，所有所述第一开关断开，所有所述第二开关闭合。
进一步地，所述单端转差分麦克风电路还包括第一斩波开关和第二斩波开关；
所述第一斩波开关通过一输入端和一输出端串联于所述麦克风的输出端和所述第一初级放大器的输入端之间，所述第一斩波开关通过另一输入端和另一输出端串联于所述耦合电容的负极和所述第二初级放大器的输入端之间；
所述第二斩波开关通过一输入端和一输出端串联于所述第一初级放大器的输出端和所述信号处理模块的正输入端之间，所述第二斩波开关通过另一输入端和另一输出端串联于所述第二初级放大器的输出端和所述信号处理模块的负输入端之间。
进一步地，所述电流共用放大器包括偏置电流源、第一PMOS管、第二PMOS管、第一NMOS管、第二NMOS管、第三NMOS管以及第四NMOS管；
所述第一PMOS管的源极和所述第二PMOS管的源极均与所述偏置电流源的输出端连接，所述第一PMOS管的栅极与所述第一NMOS管的栅极相连接并共同作为所述电流共用放大器的正输入端，所述第一PMOS管的漏极与所述第一NMOS管的漏极、所述第三NMOS管的栅极相连接并共同作为所述电流共用放大器的负输出端；
所述第二PMOS管的栅极与所述第二NMOS管的栅极相连接并共同作为所述电流共用放大器的负输入端，所述第二PMOS管的漏极与所述第二NMOS管的漏极、所述第四NMOS管的栅极相连接并共同作为所述电流共用放大器的正输出端；
所述第一NMOS管的源极与所述第三NMOS管的漏极、所述第二NMOS管的源极、所述第四NMOS管的漏极相连接；
所述第三NMOS管的源极和所述第四NMOS管的源极均接地。
进一步地，所述单端转差分麦克风电路还包括第二偏置电阻和第三偏置电阻；
所述第二偏置电阻的一端与所述第一初级放大器的输入端连接，所述第二偏置电阻的另一端用于输入第二偏置电压；所述第三偏置电阻的一端与所述第二初级放大器的输入端连接，所述第三偏置电阻的另一端用于输入所述第二偏置电压。
进一步地，所述第一偏置电压大于所述第二偏置电压。
进一步地，所述第一偏置电阻的阻值范围为100GΩ至200GΩ。
进一步地，所述正端反馈电阻和所述负端反馈电阻的阻值相同，所述正端反馈电容和所述负端反馈电容的电容值相同。
 有益效果
与相关技术相比，本发明的麦克风电路中，其包括用于输入第一偏置电压的供电端、麦克风电容、耦合电容、第一初级放大器、第二初级放大器、信号处理模块、电流共用放大器、正端反馈电阻、正端反馈电容、负端反馈电阻、负端反馈电容、第一输出端以及第二输出端；所述麦克风和所述耦合电容分别与所述第一初级放大器的输入端和所述第二初级放大器的输入端连接，所述第一初级放大器的输出端和第二初级放大器的输出端分别与所信号处理模块的正输入端和负输入端连接，所述信号处理模块的正输出端和负输出端分别与所述电流共用放大器的正输入端和负输入端连接，以通过所述信号处理模块将所述第一初级放大器和所述第二初级放大器的输出信号调整为振幅相等且相位相反的目标差分信号，并将所述目标差分信号输出给所述电流共用放大器，由此通过信号处理模块的作用可以输出振幅相等且相位相反的差分信号，从而可以利用输入共模电压范围较小且噪声较小的电流共用放大器来实现差分信号的输出，有利于提高电路的信噪比。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图，其中：
图1为现有技术一种单端转差分麦克风电路的电路图；
图2为本发明实施例提供的单端转差分麦克风电路的一电路图；
图3为本发明实施例提供的信号倍增器的电路图；
图4a为图3所示的信号倍增器在时钟信号为第一相位时的等效电路图；
图4b为图3所示的信号倍增器在时钟信号为第二相位时的等效电路图；
图5为本发明实施例提供的单端转差分麦克风电路的另一电路图；
图6为本发明实施例提供的电流共用放大器的电路图。
 本发明的最佳实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
请参阅图2，本发明的单端转差分麦克风电路中，该麦克风电路包括用于输入第一偏置电压的供电端V HCM、麦克风电容C MEMS、耦合电容C AC、第一初级放大器Amp1、第二初级放大器Amp2、信号处理模块10、电流共用放大器CR-Amp、正端反馈电阻R FB1、正端反馈电容C FB1、负端反馈电阻R FB2以及负端反馈电容C FB2。其中，所述麦克风电容C MEMS为麦克风连接至所述单端转差分麦克风电路中等效形成。
所述供电端V HCM与所述麦克风电容C MEMS的偏置电压输入端连接，从而为所述麦克风电容C MEMS提供第一偏置电压，该第一偏置电压为高电压偏置电压，例如可以是13.8V，所述麦克风电容C MEMS的输出端与所述第一初级放大器Amp1的输入端连接。
所述耦合电容C AC的正极接地，所述耦合电容C AC的负极与所述第二初级放大器Amp2的输入端连接。
所述第一初级放大器Amp1的输出端与所信号处理模块10的正输入端V I+连接，第二初级放大器Amp2的输出端与所信号处理模块10的负输入端V I-连接，所述信号处理模块10的正输出端V O+与所述电流共用放大器CR-Amp的正输入端连接，所述信号处理模块10的负输出端V O-与所述电流共用放大器CR-Amp的负输入端连接，以通过所述信号处理模块10将所述第一初级放大器Amp1和所述第二初级放大器Amp2的输出信号调整为振幅相等且相位相反的目标差分信号，并将所述目标差分信号输出给所述电流共用放大器CR-Amp。
所述正端反馈电阻R FB1和所述正端反馈电容C FB1均并联于所述电流共用放大器CR-Amp的正输入端和负输出端V OUTN之间，所述负端反馈电阻R FB2和所述负端反馈电容C FB2均并联于所述电流共用放大器CR-Amp的负输入端和正输出端V OUTP之间。其中，所述正端反馈电阻R FB1和所述负端反馈电阻R FB2的阻值可以相同，所述正端反馈电容C FB1和所述负端反馈电容C FB2的电容值可以相同。
因此，本实施例的单端转差分麦克风电路中，电流共用放大器CR-Amp为一个双端输入双端输出的全差分放大器，通过电流共用放大器CR-Amp的作用实现信号的单端转差分。其中，通过信号处理模块10的作用，将第一初级放大器Amp1和第二初级放大器Amp2的输出信号调整为振幅相等且相位相反的目标差分信号，由此可以使得输入至后续电路中的全差分放大器的差分信号振幅相等且相位相反，从而可以使得输入共模电压范围变小，因此后续电路中的全差分放大器能够采用输入共模电压范围小的电流共用放大器CR-Amp来实现，而电流共用放大器CR-Amp相比于输入共模电压范围大的全差分放大器，具有更小的噪声，从而可以减小电流共用放大器CR-Amp自身的噪声对整个电路的影响，有利于提高麦克风电路的信噪比。
进一步地，本发明的信号处理模块10包括信号倍增器，所述信号倍增器具体用于将所述第一初级放大器Amp1的输出信号减去所述第二初级放大器Amp2的输出信号，得到差值信号；然后将所述差值信号进行反相处理从而得到差值反相信号，所述差值信号和所述差值反相信号构成所述目标差分信号；还用于将所述差值信号从所述信号处理模块10的正输出端输出，将所述差值反相信号从所述信号处理模块10的负输出端进行输出。
由此，通过所述信号倍增器可以实现将所述第一初级放大器Amp1和所述第二初级放大器Amp2的输出信号调整为振幅相等且相位相反的目标差分信号，并且目标差分信号的两路信号的振幅差相比于调整前的振幅差扩大了一倍，有利于减小后续电路中的电流共用放大器对整个电路的信噪比的影响。
更具体地，参阅图3，本发明的实施例中，所述信号倍增器包括四个开关电容，每个所述开关电容包括两个第一开关S1、两个第二开关S2以及一个电容器，所述四个开关电容分别为第一开关电容101、第二开关电容102、第三开关电容103以及第四开关电容104；
其中，所述第一开关电容101的所述电容器C1的正极通过一个所述第一开关S1连接至所述信号处理模块10的正输入端V I+，并通过一个所述第二开关S2连接至所述信号处理模块10的正输出端V O+，所述电容器C1的负极通过另一个所述第一开关S1连接至所述信号处理模块10的负输入端V I-，并通过另一个所述第二开关S2连接输入共模电压V CM。
所述第二开关电容102的所述电容器C2的正极通过一个所述第一开关S1连接至所述信号处理模块10的正输入端V I+，并通过一个所述第二开关S2连接所述输入共模电压V CM，所述电容器C2的负极通过另一个所述第一开关S1连接至所述信号处理模块10的负输入端V I-，并通过另一个所述第二开关S2连接至所述信号处理模块10的负输出端V O-。
所述第三开关电容103的所述电容器C3的正极通过一个所述第一开关S1连接至所述信号处理模块10的正输出端V O+，并通过一个所述第二开关S2连接至所述信号处理模块10的正输入端V I+，所述电容器C3的负极通过另一个所述第一开关S1连接所述输入共模电压V CM，并通过另一个所述第二开关S2连接至所述信号处理模块10的负输入端V I-。
所述第四开关电容104的所述电容器C4的正极通过一个所述第一开关S1连接所述输入共模电压V CM，并通过一个所述第二开关S2连接至所述信号处理模块10的正输入端V I+，所述电容器C4的负极通过另一个所述第一开关S1连接至所述信号处理模块10的负输出端V O-，并通过另一个所述第二开关S2连接至所述信号处理模块10的负输入端V I-。
所有所述第一开关S1和所述第二开关S2受控于设定的时钟信号，当所述时钟信号为第一相位S01时，所有所述第一开关S1闭合，所有所述第二开关S2断开。当所述时钟信号为与所述第一相位S01相反的第二相位S02时，所有所述第一开关S1断开，所有所述第二开关S2闭合。
如图4a和图4b所示，图4a为图3所示的信号倍增器在时钟信号为第一相位S01时的等效电路图，图4b为图3所示的信号倍增器在时钟信号为第二相位S02时的等效电路图。在第一相位S01时，电容器C1和电容器C2并联在信号处理模块10的正输入端V I+和负输入端V I-之间，电容器C3和电容器C4串联在信号处理模块10的正输出端V O+和负输出端V O-之间，此时电容器C1和电容器C2两端的电压差即为正输入端V I+和负输入端V I-的电压差，也即第一初级放大器Amp1和第二初级放大器Amp2的输出信号的差值信号；而在第二相位S02时，电容器C1和电容器C2串联在信号处理模块10的正输出端V O+和负输出端V O-之间，从而将电容器C1在第一相位S01时两端的电压差和电容器C2在第一相位S01时两端的电压差叠加在正输出端V O+和负输出端V O-之间。由此，正输出端V O+的信号变为电容器C1两端的电压差加上输入共模电压V CM，即V O+=V CM+V I+-V I-；负输出端V O-的信号变为输入共模电压V CM减去电容器C2两端的电压差，即V O-=V CM-（V I+-V I-）。因此，正输出端V O+的信号和负输出端V O-的信号构成目标差分信号并传输给电流共用放大器CR-Amp的正负输入端，并且，V O+- V O-=( V CM+V I+-V I-)-( V CM-（V I+-V I-）) =2(V I+-V I-)，即目标差分信号的正负振幅差变为第一初级放大器Amp1和第二初级放大器Amp2的输出信号的振幅差的两倍，从而实现振幅的差值倍增。
其中，电容器C3和电容器C4的工作原理与电容器C1和电容器C2的工作原理相类似，两者控制时钟相位互为反相，通过电容器C1、电容器C2、电容器C3和电容器C4在相位互补的时钟控制下，使得信号处理模块10的正负输出端可得到持续的差值倍增信号。
参阅图5，本发明的实施例中，所述麦克风电路还包括第一斩波开关11和第二斩波开关12。
所述第一斩波开关11通过一输入端和一输出端串联于所述麦克风电容C MEMS的输出端和所述第一初级放大器Amp1的输入端之间，所述第一斩波开关11通过另一输入端和另一输出端串联于所述耦合电容C AC的负极和所述第二初级放大器Amp2的输入端之间。
所述第二斩波开关12通过一输入端和一输出端串联于所述第一初级放大器Amp1的输出端和所述信号处理模块10的正输入端V I+之间，所述第二斩波开关12通过另一输入端和另一输出端串联于所述第二初级放大器Amp2的输出端和所述信号处理模块10的负输入端V I-之间。
通过第一斩波开关11和第二斩波开关12对信号进行Chopping处理，可以消除第一初级放大器Amp1和第二初级放大器Amp2的低频噪声。
继续参阅图5，本实施例中，与图2所示实施例不同的是，耦合电容C AC的正极还可以连接至所述麦克风电容C MEMS的偏置电压输入端，此时，麦克风电路还包括串联在所述供电端V HCM和所述偏置电压输入端之间的第一偏置电阻R B1。其中，第一偏置电阻R B1为大阻值电阻，其阻值范围比如可以是100GΩ至200GΩ。
进一步地，麦克风电路还包括第二偏置电阻R B2和第三偏置电阻R B3。
所述第二偏置电阻R B2的一端与所述第一初级放大器Amp1的输入端连接，所述第二偏置电阻R B2的另一端用于输入第二偏置电压V B；所述第三偏置电阻R B3的一端与所述第二初级放大器Amp2的输入端连接，所述第三偏置电阻R B3的另一端用于输入所述第二偏置电压V B。第一偏置电压大于第二偏置电压V B，第二偏置电压V B为低电压偏置电压，如为0.8V。
其中，所述第二偏置电阻R B2和第三偏置电阻R B3的阻值相同。所述第一偏置电阻R B1与所述第二偏置电阻R B2、第三偏置电阻R B3的阻值可以相同也可以不相同，例如可以都为200GΩ。
如图5所示，声音信号从麦克风电容C MEMS输入后，经麦克风电容C MEMS转变为交流电信号，而由于第一偏置电阻R B1的高阻抗作用，可以使得交流电信号经过第一斩波开关11后同时输入至第一初级放大器Amp1和第二初级放大器Amp2，且输入至第一初级放大器Amp1和第二初级放大器Amp2的交流电信号相位相反。经过第一斩波开关11和第二斩波开关12的Chopping处理，可以消除第一初级放大器Amp1和第二初级放大器Amp2的低频噪声，然后利用信号处理模块10对经过第二斩波开关12处理后的信号进行调整，以获得振幅相等且相位相反的目标差分信号，并且还可以使目标差分信号的振幅相比于调整前有所扩增，从而有利于降低电流共用放大器对整个电路的信噪比的影响，有利于提高信噪比。
此外，当闭环增益为1时，现有技术的正、负端反馈电容的电容值需要设置为与麦克风电容C MEMS的电容值相同，而麦克风电容C MEMS的电容值通常都较小，从而正、负端反馈电容的电容值也是较小的电容值，会降低整个电路的信噪比，而本实施例中，通过将耦合电容C AC连接至所述麦克风电容C MEMS的偏置电压输入端，并且在供电端V HCM和所述麦克风电容C MEMS的偏置电压输入端之间串联第一偏置电阻R B1，从而当闭环增益为1时，正、负端反馈电容的电容值可设置为麦克风电容C MEMS的电容值的两倍，相比于现有方式，可以增大正、负端反馈电容的电容值，从而能够更多地滤除电流共用放大器自身的噪声，提高整个麦克风电容电路的信噪比。
参阅图6，本发明的实施例中，电流共用放大器CR-Amp包括偏置电流源IB、第一PMOS管P1、第二PMOS管P2、第一NMOS管N1、第二NMOS管N2、第三NMOS管N3以及第四NMOS管N4。
所述第一PMOS管P1的源极和所述第二PMOS管P2的源极均与所述偏置电流源IB的输出端连接，所述第一PMOS管P1的栅极与所述第一NMOS管N1的栅极相连接并共同作为所述电流共用放大器CR-Amp的正输入端V INP，所述第一PMOS管P1的漏极与所述第一NMOS管N1的漏极、所述第三NMOS管N3的栅极相连接并共同作为所述电流共用放大器CR-Amp的负输出端V OUTN。
所述第二PMOS管P2的栅极与所述第二NMOS管N2的栅极相连接并共同作为所述电流共用放大器CR-Amp的负输入端，所述第二PMOS管P2的漏极与所述第二NMOS管N2的漏极、所述第四NMOS管N4的栅极相连接并共同作为所述电流共用放大器CR-Amp的正输出端。
所述第一NMOS管N1的源极与所述第三NMOS管N3的漏极、所述第二NMOS管N2的源极、所述第四NMOS管N4的漏极相连接。
所述第三NMOS管N3的源极和所述第四NMOS管N4的源极均接地。
由此，对于上述电流共用放大器CR-Amp，作为输入管的第一PMOS管P1和第一NMOS管N1的跨导相加后经过作为负载的第三NMOS管N3后转变为电压在负输出端V OUTN输出，作为输入管的第二PMOS管P2和第二NMOS管N2的跨导相加后经过作为负载的第四NMOS管N4后转变为电压在正输出端V OUTP输出，从而在同样的偏置电流下，跨导增大一倍，有利于减小电流共用放大器CR-Amp的噪声。
以上所述的仅是本发明的实施方式，在此应当指出，对于本领域的普通技术人员来说，在不脱离本发明创造构思的前提下，还可以做出改进，但这些均属于本发明的保护范围。

Claims (9)

  1. 一种单端转差分麦克风电路，其特征在于，包括用于输入第一偏置电压的供电端、麦克风电容、耦合电容、第一初级放大器、第二初级放大器、信号处理模块、电流共用放大器、正端反馈电阻、正端反馈电容、负端反馈电阻以及负端反馈电容；其中，所述麦克风电容为麦克风连接至所述单端转差分麦克风电路中等效形成；
    所述供电端与所述麦克风电容的偏置电压输入端连接，所述麦克风电容的输出端与所述第一初级放大器的输入端连接；
    所述耦合电容的正极接地或与所述偏置电压输入端连接，其中当所述耦合电容的正极与所述偏置电压输入端连接时，所述单端转差分麦克风电路还包括串联在所述供电端和所述偏置电压输入端之间的第一偏置电阻，所述耦合电容的负极与所述第二初级放大器的输入端连接；
    所述第一初级放大器的输出端和第二初级放大器的输出端分别与所信号处理模块的正输入端和负输入端连接，所述信号处理模块的正输出端和负输出端分别与所述电流共用放大器的正输入端和负输入端连接，以通过所述信号处理模块将所述第一初级放大器和所述第二初级放大器的输出信号调整为振幅相等且相位相反的目标差分信号，并将所述目标差分信号输出给所述电流共用放大器；
    所述正端反馈电阻和所述正端反馈电容均并联于所述电流共用放大器的正输入端和负输出端之间，所述负端反馈电阻和所述负端反馈电容均并联于所述电流共用放大器的负输入端和正输出端之间。
  2. 根据权利要求1所述的单端转差分麦克风电路，其特征在于，所述信号处理模块包括信号倍增器，所述信号倍增器用于：
    将所述第一初级放大器的输出信号减去所述第二初级放大器的输出信号，得到差值信号；
    将所述差值信号进行反相处理从而得到差值反相信号，所述差值信号和所述差值反相信号构成所述目标差分信号；
    将所述差值信号从所述信号处理模块的正输出端输出，将所述差值反相信号从所述信号处理模块的负输出端进行输出。
  3. 根据权利要求2所述的单端转差分麦克风电路，其特征在于，所述信号倍增器包括四个开关电容，每个所述开关电容包括两个第一开关、两个第二开关以及一个电容器，所述四个开关电容分别为第一开关电容、第二开关电容、第三开关电容以及第四开关电容；
    其中，所述第一开关电容的所述电容器的正极通过一个所述第一开关连接至所述信号处理模块的正输入端，并通过一个所述第二开关连接至所述信号处理模块的正输出端，所述电容器的负极通过另一个所述第一开关连接至所述信号处理模块的负输入端，并通过另一个所述第二开关连接输入共模电压；
    所述第二开关电容的所述电容器的正极通过一个所述第一开关连接至所述信号处理模块的正输入端，并通过一个所述第二开关连接所述输入共模电压，所述电容器的负极通过另一个所述第一开关连接至所述信号处理模块的负输入端，并通过另一个所述第二开关连接至所述信号处理模块的负输出端；
    所述第三开关电容的所述电容器的正极通过一个所述第一开关连接至所述信号处理模块的正输出端，并通过一个所述第二开关连接至所述信号处理模块的正输入端，所述电容器的负极通过另一个所述第一开关连接所述输入共模电压，并通过另一个所述第二开关连接至所述信号处理模块的负输入端；
    所述第四开关电容的所述电容器的正极通过一个所述第一开关连接所述输入共模电压，并通过一个所述第二开关连接至所述信号处理模块的正输入端，所述电容器的负极通过另一个所述第一开关连接至所述信号处理模块的负输出端，并通过另一个所述第二开关连接至所述信号处理模块的负输入端；
    所有所述第一开关和所述第二开关受控于设定的时钟信号：当所述时钟信号为第一相位时，所有所述第一开关闭合，所有所述第二开关断开；当所述时钟信号为与所述第一相位相反的第二相位时，所有所述第一开关断开，所有所述第二开关闭合。
  4. 根据权利要求1所述的单端转差分麦克风电路，其特征在于，所述单端转差分麦克风电路还包括第一斩波开关和第二斩波开关；
    所述第一斩波开关通过一输入端和一输出端串联于所述麦克风的输出端和所述第一初级放大器的输入端之间，所述第一斩波开关通过另一输入端和另一输出端串联于所述耦合电容的负极和所述第二初级放大器的输入端之间；
    所述第二斩波开关通过一输入端和一输出端串联于所述第一初级放大器的输出端和所述信号处理模块的正输入端之间，所述第二斩波开关通过另一输入端和另一输出端串联于所述第二初级放大器的输出端和所述信号处理模块的负输入端之间。
  5. 根据权利要求1所述的单端转差分麦克风电路，其特征在于，所述电流共用放大器包括偏置电流源、第一PMOS管、第二PMOS管、第一NMOS管、第二NMOS管、第三NMOS管以及第四NMOS管；
    所述第一PMOS管的源极和所述第二PMOS管的源极均与所述偏置电流源的输出端连接，所述第一PMOS管的栅极与所述第一NMOS管的栅极相连接并共同作为所述电流共用放大器的正输入端，所述第一PMOS管的漏极与所述第一NMOS管的漏极、所述第三NMOS管的栅极相连接并共同作为所述电流共用放大器的负输出端；
    所述第二PMOS管的栅极与所述第二NMOS管的栅极相连接并共同作为所述电流共用放大器的负输入端，所述第二PMOS管的漏极与所述第二NMOS管的漏极、所述第四NMOS管的栅极相连接并共同作为所述电流共用放大器的正输出端；
    所述第一NMOS管的源极与所述第三NMOS管的漏极、所述第二NMOS管的源极、所述第四NMOS管的漏极相连接；
    所述第三NMOS管的源极和所述第四NMOS管的源极均接地。
  6. 根据权利要求1所述的单端转差分麦克风电路，其特征在于，所述单端转差分麦克风电路还包括第二偏置电阻和第三偏置电阻；
    所述第二偏置电阻的一端与所述第一初级放大器的输入端连接，所述第二偏置电阻的另一端用于输入第二偏置电压；所述第三偏置电阻的一端与所述第二初级放大器的输入端连接，所述第三偏置电阻的另一端用于输入所述第二偏置电压。
  7. 根据权利要求6所述的单端转差分麦克风电路，其特征在于，所述第一偏置电压大于所述第二偏置电压。
  8. 根据权利要求7所述的单端转差分麦克风电路，其特征在于，所述第一偏置电阻的阻值范围为100GΩ至200GΩ。
  9. 根据权利要求1所述的单端转差分麦克风电路，其特征在于，所述正端反馈电阻和所述负端反馈电阻的阻值相同，所述正端反馈电容和所述负端反馈电容的电容值相同。
PCT/CN2022/093937 2022-04-19 2022-05-19 单端转差分麦克风电路 Ceased WO2023201824A1 (zh)

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