WO2023199808A1 - Dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur Download PDF

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Publication number
WO2023199808A1
WO2023199808A1 PCT/JP2023/014042 JP2023014042W WO2023199808A1 WO 2023199808 A1 WO2023199808 A1 WO 2023199808A1 JP 2023014042 W JP2023014042 W JP 2023014042W WO 2023199808 A1 WO2023199808 A1 WO 2023199808A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
semiconductor element
signal terminal
power terminals
sealing resin
Prior art date
Application number
PCT/JP2023/014042
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English (en)
Japanese (ja)
Inventor
沢水 神田
Original Assignee
ローム株式会社
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Publication date
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Publication of WO2023199808A1 publication Critical patent/WO2023199808A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Definitions

  • the present disclosure relates to a semiconductor device.
  • Patent Document 1 discloses an example of a semiconductor device equipped with two power semiconductor elements (for example, IGBT).
  • the semiconductor device is used in a power conversion device such as an inverter.
  • the semiconductor device is surface mounted on a wiring board.
  • the semiconductor device disclosed in Patent Document 1 includes a plurality of power supply terminals and a plurality of control terminals.
  • a plurality of power supply terminals and a plurality of control terminals protrude outside from a housing that covers the two power semiconductor elements.
  • a portion protruding outward from the housing is bent into a gull wing shape to enable surface mounting.
  • the mutual spacing between the plurality of power supply terminals is further reduced. Thereby, there is a concern that the dielectric strength voltage of the semiconductor device may be reduced due to each portion of the plurality of power supply terminals protruding from the housing to the outside.
  • An object of the present disclosure is to provide a semiconductor device that is improved over conventional ones.
  • a semiconductor device provided by the present disclosure includes: a first semiconductor element, a second semiconductor element, a plurality of power terminals each electrically connected to at least one of the first semiconductor element and the second semiconductor element;
  • the semiconductor device includes a first signal terminal electrically connected to one semiconductor element, a second signal terminal electrically connected to the second semiconductor element, and a sealing resin covering the first semiconductor element and the second semiconductor element.
  • the sealing resin has a bottom surface facing in the first direction.
  • the plurality of power terminals, the first signal terminal, and the second signal terminal are exposed from the bottom surface. When viewed in the first direction, the entirety of each of the plurality of power terminals and the entirety of each of the first signal terminal and the second signal terminal are surrounded by the outer edge of the sealing resin.
  • FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present disclosure.
  • FIG. 2 is a bottom view of the semiconductor device shown in FIG. 1.
  • FIG. 3 is a bottom view corresponding to FIG. 2, through which the sealing resin is seen.
  • FIG. 4 is a left side view of the semiconductor device shown in FIG.
  • FIG. 5 is a right side view of the semiconductor device shown in FIG. 1.
  • FIG. 6 is a cross-sectional view taken along line VI-VI in FIG.
  • FIG. 7 is a cross-sectional view taken along line VII-VII in FIG.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG.
  • FIG. 9 is a partially enlarged view of FIG. 6.
  • FIG. 6 is a cross-sectional view taken along line VI-VI in FIG.
  • FIG. 7 is a cross-sectional view taken along line VII-VII in FIG.
  • FIG. 8 is a cross-sectional view taken along line VIII-V
  • FIG. 10 is a plan view of a modification of the semiconductor device shown in FIG.
  • FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 10.
  • FIG. 12 is a plan view of a semiconductor device according to a second embodiment of the present disclosure.
  • FIG. 13 is a bottom view of the semiconductor device shown in FIG. 12.
  • FIG. 14 is a left side view of the semiconductor device shown in FIG. 12.
  • FIG. 15 is a right side view of the semiconductor device shown in FIG. 12.
  • FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 13.
  • FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 13.
  • FIG. 18 is a plan view of a modification of the semiconductor device shown in FIG. 12.
  • FIG. 12 is a plan view of a semiconductor device according to a second embodiment of the present disclosure.
  • FIG. 13 is a bottom view of the semiconductor device shown in FIG. 12.
  • FIG. 19 is a sectional view taken along line XIX-XIX in FIG. 18.
  • FIG. 20 is a plan view of a semiconductor device according to a third embodiment of the present disclosure.
  • 21 is a bottom view of the semiconductor device shown in FIG. 20.
  • FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 21.
  • FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 21.
  • FIG. 24 is a plan view of a semiconductor device according to a fourth embodiment of the present disclosure.
  • FIG. 25 is a bottom view of the semiconductor device shown in FIG. 24.
  • FIG. 26 is a bottom view corresponding to FIG. 25, in which the sealing resin is seen through.
  • FIG. 27 is a right side view of the semiconductor device shown in FIG. 24.
  • FIG. 28 is a plan view of a semiconductor device according to a fifth embodiment of the present disclosure.
  • FIG. 29 is a bottom view of the semiconductor device shown in FIG. 28.
  • FIG. 30 is a bottom view corresponding to FIG. 29, in which the sealing resin is seen through.
  • FIG. 31 is a front view of the semiconductor device shown in FIG. 28.
  • FIG. 32 is a cross-sectional view taken along the line XXXII-XXXII in FIG. 29.
  • a semiconductor device A10 according to a first embodiment of the present disclosure will be described based on FIGS. 1 to 9.
  • the semiconductor device A10 is used in electronic equipment including a power conversion circuit such as an inverter.
  • the semiconductor device A10 includes a support member 10, two semiconductor elements 20, a plurality of power terminals 30, a plurality of first signal terminals 31, a plurality of second signal terminals 32, two conductive members 40, and two gate wires 41, 2.
  • the detection wire 42 and the sealing resin 50 are provided.
  • FIG. 3 for convenience of understanding, the sealing resin 50 is shown.
  • the outline of the transparent sealing resin 50 is shown by an imaginary line (two-dot chain line).
  • first direction z the normal direction of the bottom surface 52 of the sealing resin 50, which will be described later, will be referred to as a "first direction z.”
  • second direction x One direction perpendicular to the first direction z
  • third direction y A direction perpendicular to the first direction z and the second direction x is referred to as a "third direction y.”
  • the semiconductor device A10 converts the DC power supply voltage applied to the first input terminal 30A and the second input terminal 30B (see FIG. 2) among the plurality of power terminals 30 into AC power using the two semiconductor elements 20.
  • the converted AC power is input to a power supply target such as a motor from an output terminal 30C (see FIG. 2) among the plurality of power terminals 30.
  • the semiconductor device A10 is surface mounted on a wiring board.
  • the sealing resin 50 covers the two semiconductor elements 20, as shown in FIGS. 2, 6, and 7. Furthermore, the sealing resin 50 covers the support member 10 excluding the heat dissipation layer 16, the two conductive members 40, the two gate wires 41, and the two detection wires 42.
  • the sealing resin 50 has electrical insulation properties.
  • the sealing resin 50 is made of a material containing, for example, a black epoxy resin. As shown in FIGS. 1 and 2, the sealing resin 50 has a top surface 51, a bottom surface 52, two first side surfaces 53, and two second side surfaces 54.
  • top surface 51 and the bottom surface 52 face oppositely to each other in the first direction z.
  • Top surface 51 has a periphery 511 that defines top surface 51 .
  • the peripheral edge 511 is surrounded by the outer edge 501 of the sealing resin 50 and is located away from the outer edge 501 when viewed in the first direction z.
  • the outer edge 501 corresponds to the outline of the sealing resin 50 when viewed in the first direction z.
  • each of the two first side surfaces 53 face opposite to each other in the second direction x. As shown in FIG. 5, each of the two first side surfaces 53 is connected to the top surface 51 and the bottom surface 52. Each of the two first side surfaces 53 includes a region connected to the bottom surface 52 and facing in the second direction x, and a region connected to the top surface 51 and inclined with respect to the top surface 51.
  • the two second side surfaces 54 face oppositely to each other in the third direction y.
  • Each of the two second side surfaces 54 is connected to the top surface 51 and the bottom surface 52.
  • Each of the two second side surfaces 54 includes a region connected to the bottom surface 52 and facing in the third direction y, and a region connected to the top surface 51 and inclined with respect to the top surface 51.
  • the support member 10 mounts two semiconductor elements 20, as shown in FIGS. 3 and 8. As shown in FIGS. 1 and 3, the support member 10 includes an insulating layer 11, a first conductive layer 12, a second conductive layer 13, a third conductive layer 14, a plurality of pad layers 15, and a heat dissipation layer 16.
  • the insulating layer 11 is located between the first conductive layer 12 and the second conductive layer 13 and the heat dissipation layer 16 in the first direction z.
  • the material for the insulating layer 11 is preferably one with relatively high thermal conductivity. Therefore, the insulating layer 11 is made of a material containing aluminum nitride (AlN) in its composition, for example.
  • AlN aluminum nitride
  • the first conductive layer 12, the second conductive layer 13, the third conductive layer 14, and the plurality of pad layers 15 are connected to the heat dissipation layer 16 with respect to the insulating layer 11 in the first direction z. located on the opposite side.
  • the first conductive layer 12 and the second conductive layer 13 are located between the two semiconductor elements 20 and the insulating layer 11 in the first direction z.
  • Each of the first conductive layer 12 , the second conductive layer 13 , the third conductive layer 14 , and the plurality of pad layers 15 is electrically connected to at least one of the two semiconductor elements 20 .
  • the compositions of the first conductive layer 12, the second conductive layer 13, the third conductive layer 14, and the plurality of pad layers 15 include copper (Cu).
  • the first conductive layer 12 is located on one side in the third direction y.
  • the second conductive layer 13 is located next to the first conductive layer 12 in the third direction y.
  • the third conductive layer 14 is sandwiched between the first conductive layer 12 and the second conductive layer 13 in the third direction y.
  • the plurality of pad layers 15 are located on the opposite side of the third conductive layer 14 with respect to the first conductive layer 12 and the second conductive layer 13 in the second direction x.
  • the plurality of pad layers 15 are arranged along the third direction y.
  • the heat dissipation layer 16 is located on the opposite side of the first conductive layer 12 and the second conductive layer 13 with respect to the insulating layer 11 in the first direction z.
  • the heat dissipation layer 16 is exposed from the top surface 51 of the sealing resin 50.
  • the composition of the heat dissipation layer 16 includes copper.
  • the heat dissipation layer 16 completely overlaps each of the two semiconductor elements 20. As shown in FIG.
  • the two semiconductor elements 20 are located between the bottom surface 52 of the sealing resin 50 and the support member 10 in the first direction z. As shown in FIGS. 3 and 8, the two semiconductor elements 20 are individually conductively bonded to the first conductive layer 12 and the second conductive layer 13 of the support member 10 via a bonding layer 29. Bonding layer 29 is, for example, solder. In addition, the bonding layer 29 may be a sintered metal containing silver (Ag) or the like.
  • the two semiconductor elements 20 are n-channel type MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) with a vertical structure.
  • the two semiconductor elements 20 include compound semiconductor substrates.
  • the main material of the compound semiconductor substrate is silicon carbide (SiC).
  • silicon (Si) may be used as the main material of the compound semiconductor substrate.
  • the two semiconductor elements 20 may be other switching elements such as IGBTs (Insulated Gate Bipolar Transistors).
  • IGBTs Insulated Gate Bipolar Transistors
  • each of the two semiconductor elements 20 has a first electrode 21, a second electrode 22, and a gate electrode 23.
  • the first electrode 21 is provided facing either the first conductive layer 12 or the second conductive layer 13 of the support member 10 .
  • a current corresponding to the power before being converted by the semiconductor element 20 flows through the first electrode 21 . That is, the first electrode 21 corresponds to a drain electrode.
  • the second electrode 22 is provided on the opposite side to the first electrode 21 in the first direction z. A current corresponding to the power converted by the semiconductor element 20 flows through the second electrode 22 . That is, the second electrode 22 corresponds to a source electrode.
  • the gate electrode 23 is provided on the opposite side to the first electrode 21 in the first direction z, and is located away from the second electrode 22.
  • a gate voltage for driving the semiconductor element 20 is applied to the gate electrode 23 .
  • the area of the gate electrode 23 is smaller than the area of the second electrode 22 when viewed in the first direction z.
  • the two semiconductor elements 20 include a first semiconductor element 20A and a second semiconductor element 20B.
  • the first electrode 21 of the first semiconductor element 20A is conductively bonded to the first conductive layer 12 of the support member 10 via the bonding layer 29. Thereby, the first semiconductor element 20A is electrically connected to the first conductive layer 12.
  • the first electrode 21 of the second semiconductor element 20B is conductively bonded to the second conductive layer 13 via the bonding layer 29. Thereby, the second semiconductor element 20B is electrically connected to the second conductive layer 13.
  • the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 are connected to the bottom surface 52 of the sealing resin 50 and the support member 10 in the first direction z. located between.
  • at least one of the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 connect two semiconductor elements 20 in the second direction x. They are located opposite each other as a reference.
  • the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 are exposed from the bottom surface 52.
  • each of the plurality of power terminals 30, the whole of each of the plurality of first signal terminals 31, and the whole of each of the plurality of second signal terminals 32. is surrounded by an outer edge 501 of the sealing resin 50.
  • each of the plurality of power terminals 30, each of the plurality of first signal terminals 31, and each of the plurality of second signal terminals 32 are separated from the support member 10. It's sticking out.
  • the compositions of the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 include copper.
  • the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 are metal leads.
  • the plurality of power terminals 30 include a first input terminal 30A, a second input terminal 30B, and an output terminal 30C.
  • the first input terminal 30A, the second input terminal 30B, and the output terminal 30C are connected to the plurality of first signal terminals 31 and the plurality of second signal terminals with reference to the two semiconductor elements 20 in the second direction x. It is located on the opposite side from the terminal 32.
  • the second input terminal 30B is located between the first input terminal 30A and the output terminal 30C in the third direction y.
  • the first input terminal 30A is electrically conductively bonded to the first conductive layer 12 of the support member 10. Thereby, the first input terminal 30A is electrically connected to the first semiconductor element 20A.
  • the second input terminal 30B is electrically conductively bonded to the third conductive layer 14 of the support member 10.
  • the output terminal 30C is conductively bonded to the second conductive layer 13 of the support member 10. Thereby, the output terminal 30C is electrically connected to the second semiconductor element 20B.
  • the first input terminal 30A corresponds to the positive electrode (P terminal)
  • the second input terminal 30B corresponds to the negative electrode (N terminal).
  • the plurality of first signal terminals 31 include a first gate terminal 31A, a first detection terminal 31B, and a second detection terminal 31C.
  • Each of the plurality of first signal terminals 31 is electrically connected to the first semiconductor element 20A.
  • the first gate terminal 31A is located closest to the plurality of second signal terminals 32.
  • the first detection terminal 31B is located between the first gate terminal 31A and the second detection terminal 31C in the third direction y.
  • the first gate terminal 31A and the first detection terminal 31B are individually conductively bonded to any two of the plurality of pad layers 15 of the support member 10.
  • the second detection terminal 31C is conductively bonded to the first conductive layer 12 of the support member 10.
  • a gate voltage for driving the first semiconductor element 20A is applied to the first gate terminal 31A.
  • a voltage equal to the potential applied to the second electrode 22 of the first semiconductor element 20A is applied to the first detection terminal 31B.
  • a voltage equal to the potential applied to the first electrode 21 of the first semiconductor element 20A is applied to the second detection terminal 31C.
  • the plurality of second signal terminals 32 include a second gate terminal 32A, a third detection terminal 32B, and a fourth detection terminal 32C.
  • Each of the plurality of second signal terminals 32 is electrically connected to the second semiconductor element 20B.
  • the second gate terminal 32A among the plurality of second signal terminals 32 is located closest to the plurality of first signal terminals 31.
  • the third detection terminal 32B is located between the second gate terminal 32A and the fourth detection terminal 32C in the third direction y.
  • the second gate terminal 32A and the third detection terminal 32B are individually conductively bonded to any two of the plurality of pad layers 15 of the support member 10.
  • the fourth detection terminal 32C is electrically conductively bonded to the first conductive layer 12 of the support member 10.
  • a gate voltage for driving the second semiconductor element 20B is applied to the second gate terminal 32A.
  • a voltage equal to the potential applied to the second electrode 22 of the second semiconductor element 20B is applied to the third detection terminal 32B.
  • a voltage equal to the potential applied to the first electrode 21 of the second semiconductor element 20B is applied to the fourth detection terminal 32C.
  • each of the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 includes a mounting surface 33, an end surface 34, a joint portion 35, a mounting portion 36 and an intermediate portion 37.
  • the mounting surface 33 is exposed from the bottom surface 52 of the sealing resin 50.
  • the mounting surface 33 is flush with the bottom surface 52.
  • the end surface 34 faces the opposite side to the side where the two semiconductor elements 20 are located in the second direction x.
  • the end surface 34 of each of the plurality of power terminals 30 is exposed from one of the two first side surfaces 53 of the sealing resin 50.
  • the plurality of first signal terminals 31 and the end surface 34 of each of the plurality of first signal terminals 31 are exposed from the other first side surface 53 of the two first side surfaces 53.
  • FIG. 3 As shown in FIG. 3, FIG. 6, and FIG. Conductively bonded.
  • the joint portion 35 is sandwiched between the sealing resin 50 and the support member 10.
  • the mounting portion 36 is separated from the joining portion 35 in the first direction z.
  • the mounting portion 36 is exposed from the bottom surface 52 of the sealing resin 50.
  • the intermediate portion 37 connects the joint portion 35 and the mounting portion 36.
  • the mounting portion 36 is located on the opposite side of the joint portion 35 with respect to the intermediate portion 37 in the second direction x.
  • the mounting section 36 includes a mounting surface 33 and an end surface 34.
  • the intermediate portion 37 is inclined with respect to the mounting portion 36 such that the farther from the mounting portion 36 in the first direction z, the closer it approaches the joint portion 35 in the second direction x. .
  • the two conductive members 40 are individually conductively bonded to the two semiconductor elements 20 and the second conductive layer 13 and the third conductive layer 14 of the support member 10.
  • the two conductive members 40 include a first member 40A and a second member 40B.
  • Each of the first member 40A and the second member 40B consists of a plurality of wires.
  • the composition of the plurality of wires includes aluminum (Al).
  • the composition of the plurality of wires may include copper.
  • each of the first member 40A and the second member 40B may be a metal clip instead of the plurality of wires.
  • the first member 40A is conductively bonded to the second electrode 22 of the first semiconductor element 20A and the second conductive layer 13 of the support member 10.
  • the first semiconductor element 20A is electrically connected to the second semiconductor element 20B and the output terminal 30C of the plurality of power terminals 30.
  • the second member 40B is conductively bonded to the second electrode 22 of the second semiconductor element 20B and the third conductive layer 14 of the support member 10.
  • the second semiconductor element 20B is electrically connected to the second input terminal 30B of the plurality of power terminals 30.
  • the first input terminal 30A of the plurality of power terminals 30 is electrically connected to the first semiconductor element 20A.
  • the output terminal 30C is electrically connected to the second semiconductor element 20B. Therefore, each of the plurality of power terminals 30 is electrically connected to at least one of the two semiconductor elements 20.
  • one of the two gate wires 41 has the gate electrode 23 of the first semiconductor element 20A and the first gate terminal 31A of the plurality of pad layers 15 of the support member 10 conductive. It is conductively bonded to the bonded pad layer 15. Thereby, the first gate terminal 31A is electrically connected to the gate electrode 23 of the first semiconductor element 20A.
  • the other gate wire 41 of the two gate wires 41 is connected to the gate electrode 23 of the second semiconductor element 20B and the pad layer 15 to which the second gate terminal 32A among the plurality of pad layers 15 of the support member 10 is conductively bonded. conductively bonded to the Thereby, the second gate terminal 32A is electrically connected to the gate electrode 23 of the second semiconductor element 20B.
  • the composition of the two gate wires 41 includes gold (Au).
  • one of the two detection wires 42 is connected to the second electrode 22 of the first semiconductor element 20A and the first detection terminal 31B among the plurality of pad layers 15 of the support member 10. It is conductively bonded to the pad layer 15 which is conductively bonded. Thereby, the first detection terminal 31B is electrically connected to the second electrode 22 of the first semiconductor element 20A.
  • the other detection wire 42 of the two detection wires 42 is a pad layer 15 to which the second electrode 22 of the second semiconductor element 20B and the third detection terminal 32B among the plurality of pad layers 15 of the support member 10 are electrically bonded. and are electrically conductively bonded to each other. Thereby, the third detection terminal 32B is electrically connected to the second electrode 22 of the second semiconductor element 20B.
  • the composition of the two sensing wires 42 includes aluminum.
  • the configurations of the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 are different from the configuration of the semiconductor device A10.
  • the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 are connected to the periphery 511 of the top surface 51 of the sealing resin 50.
  • the end surfaces 34 of each of the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 are covered with a sealing resin 50. Therefore, in the semiconductor device A11, only the mounting surfaces 33 of each of the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 are exposed from the sealing resin 50.
  • the semiconductor device A10 includes a plurality of power terminals 30, a first signal terminal 31, a second signal terminal 32, and a sealing resin 50.
  • the sealing resin 50 has a bottom surface 52 facing in the first direction z.
  • a plurality of power terminals 30, a first signal terminal 31, and a second signal terminal 32 are exposed from the bottom surface 52.
  • the entirety of each of the plurality of power terminals 30 and the entirety of each of the first signal terminal 31 and the second signal terminal 32 are surrounded by the outer edge 501 of the sealing resin 50.
  • the semiconductor device A10 further includes a support member 10 on which a first semiconductor element 20A and a second semiconductor element 20B are mounted.
  • the support member 10 is exposed from the top surface 51 of the sealing resin 50.
  • the first semiconductor element 20A, the second semiconductor element 20B, the plurality of power terminals 30, the first signal terminal 31, and the second signal terminal 32 are located between the bottom surface 52 of the sealing resin 50 and the support member 10 in the first direction z. Located in With this configuration, in the semiconductor device A10, heat can be dissipated from the side opposite to the side where the wiring board on which the semiconductor device A10 is mounted is located in the first direction z.
  • the support member 10 has the heat dissipation layer 16 exposed from the top surface 51.
  • Each of the plurality of power terminals 30 has an end surface 34 facing the opposite side to the side where the first semiconductor element 20A and the second semiconductor element 20B are located in the second direction x.
  • the end surface 34 is exposed from the sealing resin 50.
  • Each of the plurality of power terminals 30 has a joint portion 35, a mounting portion 36, and an intermediate portion 37.
  • the joint portion 35 is joined to the support member 10.
  • the mounting portion 36 is separated from the joint portion 35 in the first direction z and is exposed from the bottom surface 52 of the sealing resin 50.
  • the intermediate portion 37 connects the joint portion 35 and the mounting portion 36.
  • the joint portion 35 is sandwiched between the sealing resin 50 and the support member 10.
  • FIGS. 12 to 17 A semiconductor device A20 according to a second embodiment of the present disclosure will be described based on FIGS. 12 to 17.
  • elements that are the same as or similar to those of the semiconductor device A10 described above are denoted by the same reference numerals, and redundant explanation will be omitted.
  • the configurations of the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 are different from the configuration of the semiconductor device A10.
  • the mounting portion 36 has an intermediate portion 37 in the second direction x. It is located on the same side as the joint portion 35 as a reference.
  • the joint portion 35 is sandwiched between the sealing resin 50 and the support member 10.
  • the mounting portion 36 is attached to the joint portion 35 when viewed in the first direction z. overlapping. As a result, a part of the sealing resin 50 is sandwiched between the mounting section 36 and the joining section 35.
  • the intermediate portion 37 of each of the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 includes an end surface 34.
  • the end surface 34 of each of the plurality of power terminals 30 is exposed from one of the two first side surfaces 53 of the sealing resin 50.
  • the plurality of first signal terminals 31 and the end surface 34 of each of the plurality of first signal terminals 31 are exposed from the other first side surface 53 of the two first side surfaces 53.
  • the configurations of the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 are different from the configuration of the semiconductor device A20.
  • the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 are located near the periphery 511 of the top surface 51 of the sealing resin 50. away from As shown in FIG. 19, the end surfaces 34 of each of the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 are covered with a sealing resin 50. Therefore, in the semiconductor device A21, only the mounting surfaces 33 of each of the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 are exposed from the sealing resin 50.
  • the semiconductor device A20 includes a plurality of power terminals 30, a first signal terminal 31, a second signal terminal 32, and a sealing resin 50.
  • the sealing resin 50 has a bottom surface 52 facing in the first direction z.
  • a plurality of power terminals 30, a first signal terminal 31, and a second signal terminal 32 are exposed from the bottom surface 52.
  • the entirety of each of the plurality of power terminals 30 and the entirety of each of the first signal terminal 31 and the second signal terminal 32 are surrounded by the outer edge 501 of the sealing resin 50. Therefore, according to this configuration, even in the semiconductor device A20, it is possible to reduce the size of the semiconductor device A20 while suppressing a decrease in the dielectric strength voltage of the semiconductor device A20.
  • the semiconductor device A20 has the same configuration as the semiconductor device A10, and thus has the same effects as the semiconductor device A10.
  • the mounting portion 36 is located on the same side as the bonding portion 35 with respect to the intermediate portion 37 in the second direction x.
  • each intermediate portion 37 of the plurality of power terminals 30 includes an end surface 34.
  • the dimension of the end surface 34 exposed from the sealing resin 50 in the first direction z becomes larger. Therefore, when mounting the semiconductor device A20 on a wiring board, the volume of the solder fillet formed along the end surface 34 in the first direction z can be further expanded. This makes it possible to further increase the bonding strength of the semiconductor device A20 to the wiring board and to improve the heat dissipation of the semiconductor device A20.
  • the plurality of power terminals 30, first signal terminals 31, and second signal terminals 32 are separated from the periphery 511 of the top surface 51 of the sealing resin 50 when viewed in the first direction z.
  • each end surface 34 of the plurality of power terminals 30 is covered with the sealing resin 50, so that the area covered by the sealing resin 50 in each of the plurality of sealing resins 50 is further increased. Therefore, it becomes possible to more effectively suppress a decrease in the dielectric strength voltage of the semiconductor device A21.
  • FIGS. 20 to 23 A semiconductor device A30 according to a third embodiment of the present disclosure will be described based on FIGS. 20 to 23.
  • elements that are the same as or similar to those of the semiconductor device A10 described above are denoted by the same reference numerals, and redundant explanation will be omitted.
  • the configurations of the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 are different from the configuration of the semiconductor device A10.
  • each of the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 has a rectangular parallelepiped shape extending in the first direction z.
  • the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 are metal blocks. Therefore, each of these does not have a joint portion 35, a mounting portion 36, and an intermediate portion 37.
  • the entirety of each of the plurality of power terminals 30, the entirety of each of the plurality of first signal terminals 31, and the whole of each of the plurality of second signal terminals 32. overlaps the insulating layer 11 of the support member 10. Furthermore, as shown in FIG. 21, when viewed in the first direction z, the entirety of each of the plurality of power terminals 30, the whole of each of the plurality of first signal terminals 31, and the whole of each of the plurality of second signal terminals 32, It overlaps with the first conductive layer 12, second conductive layer 13, third conductive layer 14, and multiple pad layers 15 of the support member 10.
  • the end surfaces 34 of each of the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 are covered with a sealing resin 50. Therefore, in the semiconductor device A30, only the mounting surfaces 33 of each of the plurality of power terminals 30, the plurality of first signal terminals 31, and the plurality of second signal terminals 32 are exposed from the sealing resin 50.
  • the semiconductor device A30 includes a plurality of power terminals 30, a first signal terminal 31, a second signal terminal 32, and a sealing resin 50.
  • the sealing resin 50 has a bottom surface 52 facing in the first direction z.
  • the plurality of power terminals 30, the first signal terminal 31, and the second signal terminal 32 are exposed from the bottom surface 52.
  • the entirety of each of the plurality of power terminals 30 and the entirety of each of the first signal terminal 31 and the second signal terminal 32 are surrounded by the outer edge 501 of the sealing resin 50. Therefore, according to this configuration, even in the semiconductor device A30, it is possible to reduce the size of the semiconductor device A30 while suppressing a decrease in the withstand voltage of the semiconductor device A30.
  • the semiconductor device A30 has the same configuration as the semiconductor device A10, and thus has the same effects as the semiconductor device A10.
  • each of the plurality of power terminals 30 and the entirety of each of the first signal terminal 31 and the second signal terminal 32 overlap with the support member 10 when viewed in the first direction z.
  • each of the plurality of power terminals 30, first signal terminals 31, and second signal terminals 32 does not protrude from the support member 10 when viewed in the first direction z. Therefore, it is possible to further reduce the dimensions of the semiconductor device A30 in the direction perpendicular to the first direction z.
  • the sealing resin 50 since the end surface 34 of each of the plurality of power terminals 30 is covered with the sealing resin 50, the area covered by the sealing resin 50 in each of the plurality of sealing resins 50 is further increased. Therefore, it becomes possible to more effectively suppress a decrease in the dielectric strength voltage of the semiconductor device A30.
  • FIGS. 24 to 27 A semiconductor device A40 according to a fourth embodiment of the present disclosure will be described based on FIGS. 24 to 27.
  • elements that are the same as or similar to those of the semiconductor device A10 described above are denoted by the same reference numerals, and redundant explanation will be omitted.
  • FIG. 26 for convenience of understanding, the sealing resin 50 is shown.
  • the outline of the transparent sealing resin 50 is shown with imaginary lines.
  • the configuration of the plurality of power terminals 30 is different from the configuration of the semiconductor device A10.
  • the output terminal 30C among the plurality of power terminals 30 is connected to the first input terminal 30A and the second It is located on the opposite side to the input terminal 30B.
  • a first gate terminal 31A of the plurality of first signal terminals 31 is located on one side of the output terminal 30C in the third direction y.
  • the second gate terminal 32A of the plurality of second signal terminals 32 is located on the other side of the output terminal 30C in the third direction y.
  • the end surfaces 34 of each of the plurality of first signal terminals 31 and the plurality of second signal terminals 32 are exposed.
  • the end surface 34 of the output terminal 30C is exposed.
  • the semiconductor device A40 includes a plurality of power terminals 30, a first signal terminal 31, a second signal terminal 32, and a sealing resin 50.
  • the sealing resin 50 has a bottom surface 52 facing in the first direction z.
  • a plurality of power terminals 30, a first signal terminal 31, and a second signal terminal 32 are exposed from the bottom surface 52.
  • the entirety of each of the plurality of power terminals 30 and the entirety of each of the first signal terminal 31 and the second signal terminal 32 are surrounded by the outer edge 501 of the sealing resin 50. Therefore, according to this configuration, even in the semiconductor device A40, it is possible to reduce the size of the semiconductor device A40 while suppressing a decrease in the dielectric strength voltage of the semiconductor device A40. Further, the semiconductor device A40 has the same configuration as the semiconductor device A10, and thus has the same effects as the semiconductor device A10.
  • the output terminal 30C among the plurality of power terminals 30 is connected to the first input terminal 30A and the first input terminal 30C of the plurality of power terminals 30 with respect to the first semiconductor element 20A and the second semiconductor element 20B in the second direction x. It is located on the opposite side to the second input terminal 30B.
  • FIGS. 28 to 32 A semiconductor device A50 according to a fifth embodiment of the present disclosure will be described based on FIGS. 28 to 32.
  • elements that are the same as or similar to those of the semiconductor device A10 described above are denoted by the same reference numerals, and redundant explanation will be omitted.
  • FIG. 30 for convenience of understanding, the sealing resin 50 is shown.
  • the outline of the transparent sealing resin 50 is shown with imaginary lines.
  • the configurations of the plurality of first signal terminals 31 and the plurality of second signal terminals 32 are different from the configuration of the semiconductor device A10.
  • the second detection terminal 31C among the plurality of first signal terminals 31 and the fourth detection terminal 32C among the plurality of second signal terminals 32 are connected to each other in the third direction y. They are located on opposite sides with respect to the semiconductor element 20.
  • the second detection terminal 31C is located between the first input terminal 30A of the plurality of power terminals 30 and the first detection terminal 31B of the plurality of first signal terminals 31 in the second direction x.
  • the fourth detection terminal 32C is located between the output terminal 30C of the plurality of power terminals 30 and the third detection terminal 32B of the second signal terminal 32 in the second direction x.
  • the distance between the first gate terminal 31A of the first signal terminal 31 and the second gate terminal 32A of the second signal terminal 32 is longer than the distance in the semiconductor device A10.
  • the end surfaces 34 of each of the second detection terminal 31C and the fourth detection terminal 32C are individually exposed from the two second side surfaces 54 of the sealing resin 50.
  • the semiconductor device A50 includes a plurality of power terminals 30, a first signal terminal 31, a second signal terminal 32, and a sealing resin 50.
  • the sealing resin 50 has a bottom surface 52 facing in the first direction z.
  • a plurality of power terminals 30, a first signal terminal 31, and a second signal terminal 32 are exposed from the bottom surface 52.
  • the entirety of each of the plurality of power terminals 30 and the entirety of each of the first signal terminal 31 and the second signal terminal 32 are surrounded by the outer edge 501 of the sealing resin 50. Therefore, according to this configuration, even in the semiconductor device A50, it is possible to reduce the size of the semiconductor device A50 while suppressing a decrease in the dielectric strength voltage of the semiconductor device A50.
  • the semiconductor device A50 has the same configuration as the semiconductor device A10, and thus has the same effects as the semiconductor device A10.
  • the distance between the first gate terminal 31A as the first signal terminal 31 and the second gate terminal 32A as the second signal terminal 32 is longer than the distance in the semiconductor device A10. There is. By adopting this configuration, it is possible to reduce noise acting on the first gate terminal 31A and the second gate terminal 32A.
  • At least one of the plurality of power terminals, the first signal terminal, and the second signal terminal connect the first semiconductor element and the second semiconductor element in a second direction perpendicular to the first direction.
  • the semiconductor devices according to supplementary note 1 which are located on opposite sides of each other as a reference.
  • Appendix 3. further comprising a support member on which the first semiconductor element and the second semiconductor element are mounted,
  • the semiconductor device according to appendix 2 wherein the first semiconductor element and the second semiconductor element are located between the bottom surface and the support member in the first direction.
  • Appendix 4 The semiconductor device according to appendix 3, wherein the plurality of power terminals, the first signal terminal, and the second signal terminal are located between the bottom surface and the support member in the first direction.
  • the sealing resin has a top surface facing opposite to the bottom surface in the first direction,
  • the semiconductor device according to appendix 4 wherein the support member is exposed from the top surface.
  • Appendix 6. The semiconductor device according to appendix 5, wherein the plurality of power terminals are joined to the support member.
  • Appendix 7. The semiconductor device according to appendix 6, wherein the first signal terminal and the second signal terminal are joined to the support member.
  • the support member includes an insulating layer, and a first conductive layer and a second conductive layer located between the first semiconductor element, the second semiconductor element, and the insulating layer in the first direction, the first semiconductor element is conductively bonded to the first conductive layer,
  • Appendix 9 The semiconductor device according to appendix 8, wherein any one of the plurality of power terminals is conductively bonded to either the first conductive layer or the second conductive layer.
  • the support member has a heat dissipation layer located on the opposite side of the first conductive layer and the second conductive layer with respect to the insulating layer,
  • Appendix 11 Each of the plurality of power terminals has an end face facing opposite to the side where the first semiconductor element and the second semiconductor element are located in the second direction, 11.
  • Each of the plurality of power terminals includes a joint portion joined to the support member, a mounting portion that is separated from the joint portion in the first direction and exposed from the bottom surface, and the joint portion and the mounting portion.
  • the mounting section is located on the opposite side of the joint section with respect to the intermediate section in the second direction, The semiconductor device according to appendix 12, wherein the mounting portion includes the end surface.
  • Appendix 14 The mounting portion is located on the same side as the joint portion with respect to the intermediate portion in the second direction, The semiconductor device according to appendix 12, wherein the intermediate portion includes the end surface.
  • Appendix 15. 11 The semiconductor device according to any one of appendices 6 to 10, wherein the plurality of power terminals, the first signal terminal, and the second signal terminal are separated from a periphery of the top surface when viewed in the first direction.
  • Appendix 16 Supplementary Notes 7 to 10, wherein the entirety of each of the plurality of power terminals and the entirety of each of the first signal terminal and the second signal terminal overlap with the support member when viewed in the first direction.
  • Each of the plurality of power terminals has a mounting surface exposed from the bottom surface, 11.
  • A10, A20, A30, A40, A50 Semiconductor device 10: Support member 11: Insulating layer 12: First conductive layer 13: Second conductive layer 14: Third conductive layer 15: Pad layer 16: Heat dissipation layer 20: Semiconductor element 20A: First semiconductor element 20B: Second semiconductor element 21: First electrode 22: Second electrode 23: Gate electrode 29: Bonding layer 30: Power terminal 30A: First input terminal 30B: Second input terminal 30C: Output terminal 31: First signal terminal 31A: First gate terminal 31B: First detection terminal 31C: Second detection terminal 32: Second signal terminal 32A: Second gate terminal 32B: Third detection terminal 32C: Fourth detection terminal 33: Mounting surface 34: End surface 35: Joint portion 36: Mounting portion 37: Intermediate portion 40: Conductive member 40A: First member 40B: Second member 41: Gate wire 42: Detection wire 50: Sealing resin 501: Outer edge 51: Top Surface 511: Periphery 52: Bottom surface 53: First side surface 54: Second side surface z: First direction x

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

Un dispositif à semi-conducteur selon la présente invention comprend : un premier élément semi-conducteur ; un second élément semi-conducteur ; une pluralité de bornes d'alimentation, dont chacune est électriquement connectée au premier élément semi-conducteur et/ou au second élément semi-conducteur ; une première borne de signal qui est électriquement connectée au premier élément semi-conducteur ; une seconde borne de signal qui est électriquement connectée au second élément semi-conducteur ; et une résine d'étanchéité qui recouvre le premier élément semi-conducteur et le second élément semi-conducteur. La résine d'étanchéité a une surface inférieure qui fait face dans une première direction. La pluralité de bornes d'alimentation, la première borne de signal et la seconde borne de signal sont exposées à partir de la surface inférieure. Dans une vue dans la première direction, la totalité de chacune de la pluralité de bornes d'alimentation, la totalité de la première borne de signal et la totalité de la seconde borne de signal sont entourées par le bord externe de la résine d'étanchéité.
PCT/JP2023/014042 2022-04-12 2023-04-05 Dispositif à semi-conducteur WO2023199808A1 (fr)

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JP2022065748 2022-04-12
JP2022-065748 2022-04-12

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11312775A (ja) * 1998-04-28 1999-11-09 Ars Seimitsu Kk 半導体パッケージの製造方法、及びこれにより製造される半導体パッケージ
JP2000091493A (ja) * 1998-09-16 2000-03-31 Mitsui High Tec Inc 表面実装型半導体装置
JP2011223016A (ja) * 2005-11-18 2011-11-04 Fairchild Semiconductor Corp リードフレーム及びクリップを使用する半導体ダイ・パッケージ、並びに製造方法
JP2020009979A (ja) * 2018-07-12 2020-01-16 株式会社 日立パワーデバイス 半導体装置および半導体装置の製造方法
JP2021034657A (ja) * 2019-08-28 2021-03-01 富士電機株式会社 半導体装置及び半導体装置の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11312775A (ja) * 1998-04-28 1999-11-09 Ars Seimitsu Kk 半導体パッケージの製造方法、及びこれにより製造される半導体パッケージ
JP2000091493A (ja) * 1998-09-16 2000-03-31 Mitsui High Tec Inc 表面実装型半導体装置
JP2011223016A (ja) * 2005-11-18 2011-11-04 Fairchild Semiconductor Corp リードフレーム及びクリップを使用する半導体ダイ・パッケージ、並びに製造方法
JP2020009979A (ja) * 2018-07-12 2020-01-16 株式会社 日立パワーデバイス 半導体装置および半導体装置の製造方法
JP2021034657A (ja) * 2019-08-28 2021-03-01 富士電機株式会社 半導体装置及び半導体装置の製造方法

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