WO2023193340A1 - 半导体存储器、刷新方法和电子设备 - Google Patents

半导体存储器、刷新方法和电子设备 Download PDF

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Publication number
WO2023193340A1
WO2023193340A1 PCT/CN2022/098668 CN2022098668W WO2023193340A1 WO 2023193340 A1 WO2023193340 A1 WO 2023193340A1 CN 2022098668 W CN2022098668 W CN 2022098668W WO 2023193340 A1 WO2023193340 A1 WO 2023193340A1
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Prior art keywords
storage
row
flag bit
rows
refresh
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PCT/CN2022/098668
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English (en)
French (fr)
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卢欢
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长鑫存储技术有限公司
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Priority to US17/953,405 priority Critical patent/US20230017826A1/en
Publication of WO2023193340A1 publication Critical patent/WO2023193340A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/402—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40622—Partial refresh of memory arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 

Definitions

  • the present disclosure relates to the technical field of semiconductor memory, and in particular, to a semiconductor memory, a refresh method and an electronic device.
  • DRAM Dynamic Random Access Memory
  • DRAM Dynamic Random Access Memory
  • Bit lines there are a large number of word lines in DRAM, and these word lines are arranged adjacently.
  • Row Hammer hammer attack
  • the memory cells on the word lines adjacent to the word line may generate data. mistake.
  • the refresh object is randomly determined, and the mitigation effect of the Row Hammer attack is not obvious, while causing high power consumption. .
  • the present disclosure provides a semiconductor memory, a refreshing method and an electronic device.
  • the first flag bit can mark the hammering row of a row hammering event, thereby improving the processing effect of the row hammering event.
  • an embodiment of the present disclosure provides a semiconductor memory.
  • the semiconductor memory includes a main storage area and a mark storage area.
  • a plurality of storage rows are set in the main storage area.
  • a plurality of third storage lines are set in the mark storage area.
  • Each storage row has a corresponding relationship with one of the first flag bits, and the first flag bit is used to indicate whether the storage row is a hammer row of a row hammer event.
  • the part of the storage row extending to the mark storage area is used to form a first flag bit corresponding to the storage row; wherein the first flag bit occupies one storage unit.
  • the semiconductor memory is configured to adjust the first flag bit of the storage row to the first state when detecting that the number of consecutive accesses of the storage row within unit time exceeds a preset threshold; or , after performing a refresh operation on adjacent storage rows of the storage row, adjust the first flag bit of the storage row to the second state, and re-accumulate the consecutive accesses of the storage row within the unit time. frequency.
  • multiple storage lines are divided into several storage groups, and the mark storage area is also provided with several second flag bits; each storage group has one second flag bit. corresponding relationship, and the second flag bit is at least used to indicate whether at least one storage unit in the storage group has a specific status, and the specific status includes being occupied.
  • each storage group includes a storage line, and the part of the storage line extending to the mark storage area is used to form a second flag bit corresponding to the storage group; or each storage group
  • Each of the storage groups includes a plurality of storage rows, and a portion of one of the storage rows extending to the mark storage area is used to form a second flag bit corresponding to the storage group.
  • the semiconductor memory is further configured to adjust the second flag bit of the storage group to which the storage unit belongs to the third state after receiving a memory allocation instruction for the storage unit; or, after receiving After receiving the memory release instruction for the storage group, adjust the second flag bit of the storage group to the fourth state; or, after performing a refresh operation on the storage group, adjust the second flag bit of the storage group to the fourth state.
  • the flag bit is adjusted to the fourth state; wherein, the memory allocation instruction is a word line activation instruction or constructed using the first reserved code in the memory controller, and the memory release instruction is constructed using the first reserved code in the memory controller.
  • the second reserved code is constructed.
  • embodiments of the present disclosure provide a refresh method, applied to a semiconductor memory including multiple storage rows and multiple first flag bits.
  • One of the first flag bits is used to indicate whether one of the storage rows is Hammering rows of row hammering events, the method includes:
  • determining whether to refresh adjacent storage rows of the target storage row based on the reading result includes:
  • refresh processing is performed on at least one of the adjacent storage rows; when the first flag is in the second state, refresh processing is not performed on the adjacent storage rows. ; and perform one of the following steps: end the execution of the hammer refresh instruction, or determine a new target storage row and return to the step of reading the first flag bit of the target storage row.
  • the method further includes:
  • the first flag bit of the storage row is adjusted to the first state; after refreshing processing is performed on at least one of the adjacent storage rows , adjust the first flag bit of the storage row to the second state, and re-accumulate the number of consecutive accesses of the storage row within the unit time.
  • the semiconductor memory further includes a second flag bit, a plurality of the storage rows are divided into several storage groups, and one of the second flag bits is at least used to indicate at least one of the storage groups. Whether a storage unit is in a specific state, the specific state includes being occupied; before performing refresh processing on at least one of the adjacent storage rows, the method further includes:
  • the adjacent storage row is not refreshed; and one of the following steps is performed: ending the execution of the hammer refresh instruction, or determining the new phase. adjacent storage row and returns to the step of reading the second flag bit of the storage group to which the adjacent storage row belongs.
  • the method further includes:
  • the line activation instruction may be constructed using the first reserved code in the memory controller; the memory release instruction may be constructed using the second reserved code in the memory controller.
  • embodiments of the present disclosure provide a refresh method, applied to a semiconductor memory including multiple storage rows and multiple first flag bits.
  • One of the first flag bits is used to indicate whether one of the storage rows is Hammering rows of row hammering events, the method includes:
  • a storage row to be refreshed is determined, and a refresh process is performed on the storage row to be refreshed.
  • determining candidate storage rows among multiple storage rows according to the reading results includes: determining the storage row with the first flag bit in the first state as the hammer storage row; The hammered storage line is directly determined to be the candidate storage line;
  • determining the storage row to be refreshed based on the candidate storage row includes: randomly selecting the candidate storage row, and determining adjacent storage rows of the selected storage row as the storage row to be refreshed.
  • determining candidate storage rows among multiple storage rows according to the reading results includes: determining the storage row with the first flag bit in the first state as the hammer storage row; The adjacent storage rows of the hammered storage row are determined as the candidate storage rows;
  • determining the storage row to be refreshed based on the candidate storage row includes: randomly selecting among the candidate storage rows to obtain the storage row to be refreshed.
  • the semiconductor memory further includes a second flag bit, a plurality of the storage rows are divided into several storage groups, and one of the second flag bits is at least used to indicate at least one of the storage groups.
  • the semiconductor memory further includes a second flag bit, a plurality of the storage rows are divided into several storage groups, and one of the second flag bits is at least used to indicate at least one of the storage groups. Whether a storage unit is in a specific state, including being occupied;
  • Determining the storage row to be refreshed based on the candidate storage row includes:
  • an embodiment of the present disclosure provides an electronic device, which includes the semiconductor memory as described in the first aspect.
  • Embodiments of the present disclosure provide a semiconductor memory, a refresh method and an electronic device.
  • the semiconductor memory includes a main storage area and a mark storage area. Multiple storage lines are set in the main storage area, and multiple first flag bits are set in the mark storage area. ; Wherein, each storage row has a corresponding relationship with a first flag bit, and the first flag bit is used to indicate whether the storage row is a hammer row of a row hammer event. In this way, since a mark storage area is added to the semiconductor memory, the hammering row of the row hammering event can be marked through the first flag bit, and the target of the row hammering attack can be clarified, which can improve the handling effect of the row hammering event and save power consumption. .
  • Figure 1 is a timing diagram of a refresh operation
  • Figure 2 is a schematic structural diagram of a semiconductor memory provided by an embodiment of the present disclosure
  • Figure 3 is a schematic diagram 1 of the specific structure of a semiconductor memory provided by an embodiment of the present disclosure
  • Figure 4 is a schematic structural diagram of another semiconductor memory provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic diagram 2 of the specific structure of a semiconductor memory provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic diagram 3 of the specific structure of a semiconductor memory provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic flowchart 1 of a refreshing method provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic flowchart 2 of a refreshing method provided by an embodiment of the present disclosure.
  • Figure 9 is a schematic flowchart 3 of a refreshing method provided by an embodiment of the present disclosure.
  • Figure 10 is a schematic flowchart 4 of a refreshing method provided by an embodiment of the present disclosure.
  • Figure 11 is a schematic flow chart 5 of a refreshing method provided by an embodiment of the present disclosure.
  • Figure 12A is a schematic flow chart 6 of a refreshing method provided by an embodiment of the present disclosure.
  • Figure 12B is a schematic flow chart 7 of a refresh method provided by an embodiment of the present disclosure.
  • Figure 12C is a schematic flowchart 8 of a refreshing method provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic flowchart 1 of another refresh method provided by an embodiment of the present disclosure.
  • Figure 14 is a schematic flowchart 2 of another refresh method provided by an embodiment of the present disclosure.
  • Figure 15 is a schematic flowchart 3 of another refresh method provided by an embodiment of the present disclosure.
  • Figure 16 is a schematic flowchart 4 of another refresh method provided by an embodiment of the present disclosure.
  • Figure 17 is a schematic flow chart 5 of another refresh method provided by an embodiment of the present disclosure.
  • Figure 18 is a schematic flow chart 6 of another refresh method provided by an embodiment of the present disclosure.
  • Figure 19 is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure.
  • first ⁇ second ⁇ third involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understandable that "first ⁇ second ⁇ third” Where permitted, the specific order or sequence may be interchanged so that the embodiments of the disclosure described herein can be practiced in an order other than that illustrated or described herein.
  • FIG. 1 a timing diagram of a refresh operation is shown. As shown in Figure 1, after the memory receives the command REFpb, it selects 8 rows of word lines through the address selection signal CBR (this number needs to be determined according to the specific refresh mechanism of the memory), and turns on the selected 8 rows of word lines through the row activation signal.
  • embodiments of the present disclosure provide a semiconductor memory. Since a mark storage area is added to the semiconductor memory, the hammering row of the row hammering event can be marked through the first flag bit, and the attack target of the row hammering can be clarified. Improve the handling effect of row hammer events and save power consumption.
  • FIG. 2 shows a schematic structural diagram of a semiconductor memory 10 provided by an embodiment of the present disclosure.
  • the semiconductor memory 10 includes a main storage area 11 and a mark storage area 12.
  • a plurality of storage rows are provided in the main storage area 11 (for example, the storage row 111-1, the storage row 111-2... in FIG. 1).
  • multiple first flag bits are set in the mark storage area 12 (for example, the first flag bit 121-1, the first flag bit 121-2... in Figure 1); wherein, each storage line has a first flag bit There is a corresponding relationship, and the first flag bit is used to indicate whether the storage row is a hammer row of a row hammer event.
  • the semiconductor memory 10 may be a volatile memory, such as a dynamic random access memory (Dynamic Random Access Memory, DRAM).
  • DRAM Dynamic Random Access Memory
  • a mark storage area 12 is added to the semiconductor memory 10 to record whether each storage line in the main storage area 11 is a hammering line in a row hammering event, which can accurately locate the row.
  • the attack target of hammering events improves the handling effect of hammering events.
  • the part of the storage row extending to the mark storage area is used to form the first flag bit corresponding to the storage row; wherein the first flag bit occupies one storage unit.
  • FIG. 3 shows a schematic structural diagram of another semiconductor memory provided by an embodiment of the present disclosure.
  • the semiconductor memory includes multiple different memory arrays (Banks), and a part of each memory array belongs to the main storage area (for example, main storage area 0, main storage area 1...main storage area n in Figure 3) , another part of each storage array belongs to the mark storage area (for example, mark storage area 0, mark storage area 1...mark storage area n in Figure 2).
  • each storage row (or word line) is represented by Row
  • each storage column is represented by Col (or bit line)
  • the subscript of the storage row or storage column represents the number.
  • each number is only used to identify each storage row or storage column and does not constitute any position limitation.
  • each intersection formed by a storage row and a storage column can be regarded as having a storage unit.
  • the storage row Row j and the bit line Col m form the first flag bit of the storage row Row j
  • the storage row Row j+1 and the bit line Col m form the first flag bit of the storage row Row j+1 ... ...Others can be understood by reference.
  • the first flag bit in the mark storage area shares the same storage row with the main storage area.
  • the main storage area and the mark storage area may be two relatively independent areas.
  • the mark bit in the mark storage area Does not share the same storage row as the main storage area.
  • the mark storage area 12 can be arranged outside the main storage area 11.
  • the bit line Col m is located on the side of the bit line Col i away from the bit line Col i+n , or the bit line Col m is located on The side of the bit line Col i+n away from the bit line Col i ; for another example, the mark storage area 12 can be disposed between the interior of the main storage area 11.
  • the bit line Col m is located on the bit line Col. between i and bit line Col i+n .
  • a storage array can set 1024 bit lines belonging to the main storage area and 1 bit line belonging to the mark storage area. That is to say, the ratio of bit lines in the main storage area 11 and the mark storage area 12 is 1024:1, and the area ratio of the mark storage area 12 is less than 0.1%, so the impact of setting the mark storage area 12 on the chip area is very small.
  • the semiconductor memory 10 is configured to adjust the first flag bit of the storage row to the first state when detecting that the number of consecutive accesses of the storage row within unit time exceeds a preset threshold; or, when the After the adjacent storage row of the storage row performs a refresh operation, the first flag bit of the storage row is adjusted to the second state, and the number of consecutive accesses of the storage row within the unit time is re-accumulated.
  • multiple storage lines are divided into several storage groups (such as storage group 112-1, storage group 112-2 in Figure 4), and the mark storage area 12 is also provided with several storage groups.
  • second flag bits for example, second flag bit 122-1, second flag bit 122-2 in Figure 3
  • each storage group has a corresponding relationship with a second flag bit, and the second flag bit is at least used for Indicates whether at least one storage unit in the storage group has a specific status, including occupied.
  • each storage group includes 2 storage rows, but it may be more or less in actual application scenarios.
  • the second flag bit is used to record the status information of the storage group.
  • the specific status includes at least being occupied, and may also include being damaged, locked, released, etc.
  • the occupied storage unit may have different definitions. For example, occupied means that the storage unit is allocated to the user and has not yet stored valid data, or occupied means that valid data is stored in the storage unit.
  • each storage row has a second flag bit, in a row hammering event, it can be accurately known whether the victim row is occupied; when each storage group containing multiple storage rows corresponds to a second flag bit, flag bit, you can only know that the victim row may be occupied. If the victim row is occupied, the victim row needs to be refreshed to prevent data loss; if the victim row is not occupied, there is no need to refresh the victim row to save power consumption; when the victim row may be occupied, it is also necessary to refresh the victim row. The victim row is refreshed.
  • the first flag bit can be adjacent to the second flag bit, or the mark storage area 12 can be divided into two completely independent areas, one area is used to form the first flag bit, and the other area is used to form the second flag bit. Bit.
  • each storage group includes a storage row, and the portion of the storage row extending to the mark storage area is used to form the second flag bit corresponding to the storage group.
  • the storage unit formed by the storage row Row j and the bit lines Col i ⁇ Col i+n forms a storage group.
  • the storage row Row j and the bit line Col m+1 forms the second flag bit of the storage group;
  • the storage unit formed by the storage row Row j+1 and the bit lines Col i ⁇ Col i+n forms another storage group, and the storage row Row j+1 and the bit line Col m+1 forms the second flag bit of this storage group, others can be understood by reference.
  • each storage group includes a plurality of storage rows, and one of the storage rows extends to a portion of the mark storage area for forming a second flag bit corresponding to the storage group.
  • the storage units formed by the storage rows Row j ⁇ Row j+a and the bit lines Col i ⁇ Col i+n form a storage group.
  • the storage row Row j and the bit line Col m+1 form the second flag bit of the memory group;
  • the memory cells formed by the memory rows Row j+a+1 to Row j+2a+1 and the bit lines Col i to Col i+n form another A storage group, storage row Row j+a+1 and bit line Col m+1 form the second flag bit of the storage group.
  • the storage rows Row j+a+2 ⁇ Row j+2a+1 and the bit line Col m+1 will also form corresponding storage cells. This part of the storage cells can be assigned in the main storage area.
  • the second flag bit in the mark storage area and the main storage area will also share the same storage row.
  • the second mark bit in the mark storage area is not the same as the main storage area. Storage areas share the same storage row.
  • the bit line Col m and the bit line Col m+1 in the mark storage area can be set on an outer side of the main storage area; alternatively, the bit line Col m and the bit line Col m+1 can be set on opposite sides of the main storage area respectively.
  • the first flag bit and the second flag bit can not only play a role of identification, but also play a role in protecting the storage group, that is, the storage array is damaged.
  • the mark storage area will be damaged first instead of the main storage area, thereby ensuring the effectiveness of the basic function; alternatively, the bit line Col m and the bit line Col m+1 can be set inside the main storage area.
  • the storage array is affected by When the main storage area is damaged, priority will be given to damaging the main storage area rather than the mark storage area.
  • the main storage area is generally provided with a redundant area for damage replacement to prevent the main storage area from being unable to work; in some embodiments, the redundant area can also be used for replacement. Mark the storage area to ensure the effectiveness of the marking function.
  • each second flag bit includes at least two identifiers, and different identifiers are used to indicate different specific states; wherein, each identifier occupies one storage unit. That is, a second flag can occupy more memory cells, depending on the type of specific state.
  • the number of bit lines in the mark storage area 12 ⁇ the number of storage lines in each storage group ⁇ the number of identifiers, and the number of identifiers is equal to the number of storage lines in each storage group and the second flag The sum of the number of specific states represented by a bit.
  • each storage group includes one storage row, at least three bit lines may exist in the mark storage area 12, so that the portion of each storage line extending to the mark storage area may form a first flag bit and a second flag.
  • each storage group includes two storage rows, there are at least two bit lines in the tag storage area 12 such that each storage row in each storage group extends to the tag
  • the part of the storage area 12 may form a first flag bit with the first bit line, and the part of at least two storage rows in each storage group extending to the mark storage area 12 may form a second flag bit with the second bit line.
  • at least two identifiers are at least two identifiers.
  • the state of the second flag bit can be defined using existing instructions/operations in the DRAM.
  • the semiconductor memory 10 is also configured to adjust the second flag bit of the storage group to which the storage unit belongs to the third state after receiving a memory allocation instruction for the storage unit, where the memory allocation instruction may be a word line Activate the instruction Active; or, after performing a refresh operation on the storage group, adjust the second flag bit of the storage group to the fourth state.
  • the semiconductor memory 10 activates the designated storage row and adjusts the second flag bit corresponding to the storage row to the third state.
  • the semiconductor memory 10 performs a refresh operation on a certain storage group and adjusts the second flag bit of the storage group to the fourth state. In this way, there is no need to define additional status control instructions for the second flag bit, thereby saving signaling resources.
  • the state of the second flag bit may be constructed based on the memory application/memory release function in DRAM.
  • the semiconductor memory 10 is also configured to adjust the second flag bit of the storage group to which the storage unit belongs to the third state after receiving a memory allocation instruction for the storage unit, wherein the memory allocation instruction is controlled by memory control. It is constructed from the first reserved code in the device; or, after receiving the memory release instruction for the storage group, adjust the second flag bit of the storage group to the fourth state; wherein, the memory release instruction uses the memory control Constructed from the second reserved code in the processor.
  • Mode Register mode Register
  • operation codes Opand, OP
  • RFU Reserved For Use
  • part of the memory can be applied for through the memory allocation instruction Allocate, and based on the memory allocation instruction Allocate, the second flag bit of the storage group corresponding to the applied memory area is adjusted to the third state; accordingly, it is possible to Part of the memory is released through the memory release instruction Release, and the second flag bit of the storage group corresponding to the released memory area is adjusted to the fourth state based on the memory release instruction Release. In this way, it is helpful to adjust the status of the standard bit more accurately and ensure the accurate execution of the refresh operation.
  • the semiconductor memory 10 is also configured to adjust the second flag bit of the storage group to which the storage unit belongs to the third state after receiving a memory allocation instruction for the storage unit, wherein the memory allocation instruction is The word line activation instruction Active; or, after receiving the memory release instruction for the storage group, adjust the second flag bit of the storage group to the fourth state; wherein the memory release instruction utilizes the second preset in the memory controller. Obtained by leaving code structure. In this way, after activation and before release, the corresponding second flag bit is always in the third state and is not affected by the refresh operation. This can reduce the adjustment frequency of the second flag bit corresponding to the storage group and reduce power consumption.
  • the first state means that the data 1 is stored in the first flag bit
  • the second state means that the data 0 is stored in the first flag bit; or, the first state means that the data is stored in the first flag bit.
  • the second state means that the data 1 is stored in the first flag bit.
  • the third state means that the data 1 is stored in the second flag bit (or the corresponding identifier in the second flag bit), and the fourth state means that the data 1 is stored in the second flag bit (or the corresponding identifier in the second flag bit).
  • the embodiments of the present disclosure provide a new type of storage structure.
  • a new mark storage area is added to the semiconductor memory.
  • the hammering row of the row hammering event can be marked through the first flag bit, and the hammering row of the row hammering event can be marked through the second flag bit. It is clear whether the adjacent storage row of the hammer row is occupied, and then determines whether to refresh the adjacent storage row, which improves the processing effect of the row hammer event and saves power consumption.
  • FIG. 7 shows a schematic flowchart of a refresh method provided by an embodiment of the present disclosure. As shown in Figure 7, the method may include:
  • the refresh method provided by the embodiment of the present disclosure is applied to a semiconductor memory including multiple storage rows and multiple first flag bits.
  • a first flag bit has an associated relationship with a storage row, and a first flag bit is used to indicate whether a storage row is a hammer row of a row hammer event, please refer to the aforementioned Figure 2 or Figure 3 for details.
  • random is a macro concept, which also includes some pseudo-random mechanisms.
  • the target storage row is recorded as the i-th row
  • the adjacent storage row can be a random row among the (i+a)-th storage row ⁇ (i-a)-th storage row; or the adjacent storage row can be the (-th) storage row i+a) storage row ⁇ all rows in the (i-a)th storage row, a and i are positive integers. Generally speaking, i is less than or equal to 3.
  • embodiments of the present disclosure provide a low-power row hammer refresh method. After receiving the hammer refresh command, whether the target storage row is subject to row hammering can be understood through the first flag bit of the target storage row, and then Determining whether to refresh the adjacent storage rows of the target storage row can improve the handling effect of row hammer events and reduce power consumption.
  • step S22 if the first flag is in the first state, then step S231 is performed; if the first flag is in the second state, then step S2321 is performed.
  • S231 Refresh at least one adjacent storage row.
  • step S2322 may also be performed.
  • the first flag bit is in the first state, it means that the hammering row in the target storage row hammering event requires refreshing of adjacent storage rows. If the first flag bit is in the second state, it means that the target storage row has not suffered row hammering, and there is no need to refresh adjacent storage rows, thereby saving power consumption. Further, without performing refresh processing on adjacent storage groups, there may be at least two different processing mechanisms: (1) waiting, see step S2321; (2) skipping, see step S2322.
  • determining a new target storage line it may be randomly determined again among multiple storage lines, or the next storage line or the previous storage line of the original target storage line may be used as the new target storage line.
  • the method further includes: after detecting that the number of consecutive accesses of the storage row in unit time exceeds a preset threshold, adjusting the first flag bit of the storage row to the first state; After the adjacent storage row is refreshed, the first flag bit of the storage row is adjusted to the second state, and the number of consecutive accesses of the storage row within unit time is re-accumulated.
  • the semiconductor memory also includes a second flag bit.
  • Multiple storage rows are divided into several storage groups, and a second flag located in a storage group has a corresponding relationship.
  • a second flag bit is at least used to indicate whether at least one storage unit in a storage group is in a specific state, and the specific state includes being occupied.
  • the method further includes:
  • step S24 if the second flag bit is in the third state, then step S241 is executed; if the second flag bit is in the fourth state, then step S2321 is executed.
  • step S241 Refresh the adjacent storage rows; it can be understood that step S241 can also be adjusted to refresh at least one adjacent storage row.
  • the adjacent storage rows that are actually refreshed can be determined in a random manner, that is, no need Refresh operations are performed on all defined adjacent storage rows (adjacent rows of the target storage row).
  • step S242 may also be performed.
  • step S242 Do not refresh the adjacent storage rows, determine the new adjacent storage rows, and return to step S24.
  • the second flag bit is in the third state, it means that the adjacent storage line may be occupied, and the adjacent storage line needs to be refreshed; if the second flag bit is in the fourth state, it means that the adjacent storage line must be occupied. If it is not occupied, there is no need to perform refresh processing on adjacent memory rows, saving power consumption. Further, in the case where adjacent storage rows are not refreshed, there may be at least two different processing mechanisms: (1) waiting: see step S2321; (2) skipping: see step S242.
  • the adjacent storage rows refer to all the rows in the (a+i)th storage row to the (a-i)th storage row, then only the (a+i)th storage row to the (a-i)th storage row correspond to each other
  • the "wait” or "skip” mechanism will only be executed when the second flag bits are all in the fourth state; at the same time, for the "skip” mechanism, a new target storage row needs to be determined among the remaining storage rows. , and use the adjacent storage rows of the new target storage row as the new adjacent storage rows.
  • the adjacent storage row refers to a random row among the (a+i)th storage row to the (a-i)th storage row
  • the second flag bit of the randomly determined storage row is in the fourth state, execute "wait” or "Skip” mechanism; at the same time, for the "skip mechanism”
  • new adjacent storage rows can be randomly determined among the (a+i)th storage row to (a-i)th storage row (of the original target storage row) .
  • the second flag bits of the (a+i)th to (a-i)th storage rows (of the original target storage row) are all in the fourth state, a new target storage row needs to be determined and the new The adjacent storage rows of the target storage row are used as new adjacent storage rows.
  • each hammer refresh instruction may not necessarily generate a refresh operation; for the "skip” mechanism, each hammer refresh instruction will definitely generate a refresh operation.
  • the following special situation may exist in the semiconductor memory: only storage row 0 is the hammer row in the row hammer event, but all adjacent rows of storage row 0 are not occupied. At this time, the semiconductor memory does not actually need to be The refreshed "adjacent memory rows", for the "skip” mechanism, will cause the semiconductor memory to be unable to end the hammer refresh instruction, or it is determined that the adjacent memory rows of several consecutive target memory rows do not need to be refreshed. , causing the execution time of the hammer refresh command to be too long.
  • an auxiliary termination mechanism can also be set up: within a certain period of time after receiving the hammer refresh command, even if the refresh process is not executed, the hammer refresh command is deemed to have ended. .
  • the method further includes: after receiving the memory allocation instruction, adjusting the second flag bit of the storage group corresponding to the memory allocation instruction to the third state; after performing refresh processing on the storage group, changing the storage group The second flag bit is adjusted to the fourth state.
  • the memory allocation instruction may refer to the word line activation instruction Active.
  • the refresh process may be executed according to the aforementioned hammer refresh instruction, or may be executed according to other instructions (such as periodic refresh instructions).
  • the method further includes: after receiving the memory allocation instruction, adjusting the second flag bit of the storage group corresponding to the memory allocation instruction to the third state; after receiving the memory release instruction, releasing the memory The second flag bit of the storage group corresponding to the instruction is adjusted to the fourth state.
  • the memory allocation instruction is an Allocate instruction constructed through the first reservation code
  • the memory release instruction is a Release instruction constructed through the second reservation code.
  • the method further includes: after receiving a memory allocation instruction for the storage unit, adjusting the second flag bit of the storage group to which the storage unit belongs to the third state; or, after refreshing the storage group After processing, the second flag bit of the storage group is adjusted to the fourth state.
  • the memory allocation instruction may refer to the word line activation instruction Active.
  • the embodiment of the present disclosure provides a new hammer refresh method.
  • the attack object can be accurately located, and the attack object has never been accessed (that is, not occupied) in a storage array (Bank).
  • the storage row is not refreshed, thereby improving the handling effect of row hammer events and reducing refresh power consumption.
  • the refresh method provided by the embodiment of the present disclosure can also be combined with the function of applying for/releasing memory in DRAM, so as to perform the refresh operation with higher accuracy.
  • the method may include:
  • S312 Determine whether the number of consecutive accesses of storage row Row i per unit time is greater than the preset threshold.
  • step S313 is executed.
  • the number of accesses of the storage row Row i in unit time is accumulated to determine whether the storage row Row i is a storage row in the row hammer event.
  • the storage row Row i refers to any storage row in Figure 3
  • the flag bit Row i Col m refers to the first flag bit formed by the storage row Row i and the bit line Col m .
  • the method also includes:
  • a target storage row is randomly selected in the storage array as the refresh object, and the selected refresh object is recorded as the storage row Row i .
  • step S321 and step S311 have no specific execution order.
  • step S322 if the judgment result is no, step S323 is executed; if the judgment result is yes, step S3241 is executed.
  • S3241 Refresh the storage rows Row i+1 and Row i-1 , and adjust the first flag bit Row i Col m corresponding to the storage row Row i to the second state.
  • step S3242 may also be performed.
  • S3242 Randomly select one storage row from storage rows Row i+a to storage row Row ia for refresh, and adjust the first flag bit Row i Col m corresponding to storage row Row i to the second state.
  • step S322 if the judgment result is no, this hammer refresh instruction can also be regarded as ending, and step S325 is directly executed. In this way, the refresh operation may not be performed for the received refresh command.
  • the embodiments of the present disclosure provide a hammer refresh working method, which is applied to a semiconductor memory provided with a mark storage area.
  • the hammer row in the row hammer event can be accurately located through the first flag bit, improving the efficiency of hammer refresh. Improve the processing effect of hammering events and reduce power consumption.
  • the second flag bit it can be clarified whether the adjacent memory rows of the hammer row are occupied, and then decide whether to refresh the adjacent memory rows to save power consumption.
  • FIG. 13 shows a schematic flowchart of a refresh method provided by an embodiment of the present disclosure. As shown in Figure 13, the method may include:
  • a first flag bit has a corresponding relationship with a storage row, and a first flag bit is used It is used to indicate whether a storage row is a hammer row of a row hammer event, as shown in the aforementioned Figure 2 or Figure 3.
  • embodiments of the present disclosure provide a low-power row hammer refresh method. After receiving the hammer refresh command, the victim rows of the row hammer event can be screened out according to the first flag bit of the storage row, and then the refresh is performed. processing, which can improve the processing effect of row hammer events and reduce power consumption.
  • a candidate storage row refers to a hammered row in a row hammering event. Therefore, refreshing an object requires selecting among adjacent storage rows of a candidate storage row.
  • step S42 may specifically include:
  • S421 Determine the storage line whose first flag bit is in the first state as the hammering storage line, and directly determine the hammering storage line as the candidate storage line.
  • Step S43 may specifically include:
  • S431 Randomly select candidate storage rows, and determine adjacent storage rows of the selected storage row as storage rows to be refreshed.
  • the candidate storage row refers to the victim row in a row hammering event. Therefore, the refresh object can directly select among the candidate storage rows.
  • step S42 may specifically include:
  • S422 Determine the storage line whose first flag bit is in the first state as the hammering storage line, and determine the adjacent storage lines of the hammering storage line as the candidate storage line.
  • Step S43 may specifically include:
  • S432 Randomly select among the candidate storage rows to obtain the storage row to be refreshed.
  • the storage rows can be filtered through the first flag bit, thereby narrowing the scope of effective refresh objects and improving the handling effect of row hammering events.
  • the semiconductor memory also includes a second flag bit.
  • Multiple storage rows are divided into several storage groups, and a second flag bit has a corresponding relationship with a storage group.
  • a second flag bit The bit is at least used to indicate whether at least one storage unit in a storage group is in a specific state, and the specific state includes being occupied.
  • the method may further include:
  • step S45 if the second flag bit is in the third state, then step S44 is executed; if the second flag bit is in the fourth state, then step S461 is executed.
  • step S462 may also be selected.
  • step S462 The storage row to be refreshed is not refreshed, a new storage row to be refreshed is determined, and step S45 is returned to execution.
  • the second flag is in the third state, it means that the storage line to be refreshed may be occupied, and the storage line to be refreshed needs to be refreshed; if the second flag is in the fourth state, it means that the storage line to be refreshed must not be occupied. There is no need to refresh the memory row to be refreshed, saving power consumption. Similarly, without performing refresh processing on the storage row to be refreshed, there can be at least two different processing mechanisms: (1) waiting: see step S461; (2) skipping: see step S462.
  • the new storage row to be refreshed can be randomly selected from the remaining candidate storage rows; if the candidate storage row is The hammering row in the row hammering event, and the adjacent storage rows refer to all the rows in the (a+i)th storage row to (a-i)th storage row.
  • the new ones to be refreshed The storage row can be the adjacent storage row of the remaining candidate storage rows randomly selected; if the candidate storage row is the hammering row in the row hammering event, and the adjacent storage row refers to the (a+i)th storage row ⁇ (th) A random row in the a-i) storage row.
  • the new storage row to be refreshed can be randomly selected again from the (a+i)th storage row to the (a-i)th storage row; if The second flag bits of all the storage rows in the (a+i)th storage row to (a-i)th storage row are in the fourth state, then the new storage row to be refreshed can be randomly selected adjacent to the remaining candidate storage rows. Store row.
  • step S43 may specifically include:
  • S4331 Read the second flag bit of the storage group to which the candidate storage line belongs.
  • S4333 Randomly select among the secondary candidate storage rows to obtain the storage row to be refreshed.
  • the second flag bit is used to further narrow the range of candidate storage rows. That is, the secondary candidate storage rows refer to the "victim rows of the row hammer event" and the "occupied" storage rows. Therefore, the random selection of the secondary candidate rows is directly performed. Just select a row to refresh.
  • the embodiments of the present disclosure provide a hammer refresh working method, which is applied to a semiconductor memory provided with a mark storage area.
  • the hammer row in the row hammer event can be accurately located through the first flag bit, improving the efficiency of hammer refresh.
  • the processing effect of row hammering events is improved and power consumption is reduced; at the same time, through the second flag bit, it can be clarified whether the adjacent storage rows of the hammering row are occupied, and then it is decided whether to refresh the adjacent storage rows to save power consumption.
  • FIG. 19 shows a schematic structural diagram of an electronic device 50 provided by an embodiment of the present disclosure.
  • the electronic device 50 may include the aforementioned semiconductor memory 10 .
  • the semiconductor memory 10 may be a DRAM chip.
  • the embodiment of the present disclosure provides an electronic device 50, which includes a semiconductor memory 10, and the semiconductor memory 10 has a new mark storage area.
  • the first flag bit can accurately locate the hammering row in the row hammering event, improving the row hammering. processing effect of hit events and reduce power consumption.
  • Embodiments of the present disclosure provide a semiconductor memory, a refresh method and an electronic device.
  • the semiconductor memory includes a main storage area and a mark storage area. Multiple storage lines are set in the main storage area, and multiple first flag bits are set in the mark storage area. ; Wherein, each storage row has a corresponding relationship with a first flag bit, and the first flag bit is used to indicate whether the storage row is a hammer row of a row hammer event. In this way, since a mark storage area is added to the semiconductor memory, the hammering row of the row hammering event can be marked through the first flag bit, and the target of the row hammering attack can be clarified, which can improve the handling effect of the row hammering event and save power consumption. .

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Abstract

一种半导体存储器（10）、刷新方法和电子设备（50），半导体存储器（10）包括主存储区域（11）和标记存储区域（12），主存储区域（11）中设置多个存储行（111-1，111-2），标记存储区域（12）中设置多个第一标志位（121-1，121-2）；其中，每一存储行（111-1，111-2）与一个第一标志位（121-1，121-2）具有对应关系，且第一标志位（121-1，121-2）用于指示存储行（111-1，111-2）是否为行锤击事件的锤击行。

Description

半导体存储器、刷新方法和电子设备
相关的交叉引用
本公开基于申请号为202210370026.X、申请日为2022年04月08日、发明名称为“半导体存储器、刷新方法和电子设备”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体存储器技术领域，尤其涉及一种半导体存储器、刷新方法和电子设备。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成，且不同的存储单元需要经由字线和位线进行选中操作。也就是说，DRAM中存在大量字线，这些字线相邻排列，在某一字线受到锤式攻击(Row Hammer)时，与该字线相邻的字线上的存储单元可能会产生数据错误。为了解决这一问题，在检测到Row Hammer攻击后，需要对字线进行加刷处理，此时刷新对象是随机确定的，对Row Hammer攻击的缓解效果并不明显，同时造成较高的功耗。
发明内容
本公开提供了一种半导体存储器、刷新方法和电子设备，通过第一标志位可以标记行锤击事件的锤击行，提高行锤击事件的处置效果。
本公开的技术方案是这样实现的：
第一方面，本公开实施例提供了一种半导体存储器，所述半导体存储器包括主存储区域和标记存储区域，所述主存储区域中设置多个存储行，所述标记存储区域中设置多个第一标志位；其中，
每一所述存储行与一个所述第一标志位具有对应关系，且所述第一标志位用于指示所述存储行是否为行锤击事件的锤击行。
在一些实施例中，所述存储行延伸到所述标记存储区域的部分用于形成所述存储行对应的第一标志位；其中，所述第一标志位占用一个存储单元。
在一些实施例中，所述半导体存储器，用于在监测到存储行在单位时间内的连续被访问次数超过预设阈值时，将所述存储行的第一标志位调整为第一状态；或者，在对所述存储行的相邻存储行进行刷新操作后，将所述存储行的第一标志位调整为第二状态，并重新累计所述存储行在所述单位时间内的连续被访问次数。
在一些实施例中，多个所述存储行被分为若干个存储组，所述标记存储区域还设置有若干个第二标志位；每一所述存储组与一个所述第二标志位具有对应关系，且所述第二标志位至少用于指示所述存储组中至少一个存储单元是否具有特定状态，所述特定状态包括被占用。
在一些实施例中，每一所述存储组均包括一个存储行，且所述存储行延伸到所述标记存储区域的部分用于形成所述存储组对应的第二标志位；或者每一所述存储组均包括多个存储行，且其中一个所述存储行延伸到所述标记存储区域的部分用于形成所述存储组对应的第二标志位。
在一些实施例中，所述半导体存储器，还用于在接收到针对存储单元的内存分配指令后，将所述存储单元所属的存储组的第二标志位调整为第三状态；或者，在接收到针对于所述存储组的内存释放指令后，将所述存储组的第二标志位调整为第四状态；或者，在对所述存储组进行刷新操作后，将所述存储组的第二标志位调整为所述第四状态；其中，所述内存分配指令是字线激活指令或者利用内存控制器中的第一预留码构造得到的，所述内存释放指令是利用内存控制器中的第二预留码构造得到的。
第二方面，本公开实施例提供了一种刷新方法，应用于包括多个存储行和多个第一标志位的半导体存储器，一个所述第一标志位用于指示一个所述存储行是否为行锤击事件的锤击行，所述方法 包括：
在接收到锤击刷新指令后，在多个所述存储行中随机确定目标存储行；
对所述目标存储行的第一标志位进行读取，得到读取结果；
根据所述读取结果，确定是否对所述目标存储行的相邻存储行进行刷新处理。
在一些实施例中，所述根据所述读取结果，确定是否对所述目标存储行的相邻存储行进行刷新处理，包括：
在所述第一标志位处于第一状态时，对至少一条所述相邻存储行进行刷新处理；在所述第一标志位处于第二状态时，对所述相邻存储行不进行刷新处理；以及执行下述步骤之一：结束所述锤击刷新指令的执行，或者，确定新的目标存储行并返回执行所述对所述目标存储行的第一标志位进行读取的步骤。
在一些实施例中，所述方法还包括：
在监测到存储行在单位时间内的连续被访问次数超过预设阈值后，将所述存储行的第一标志位调整为第一状态；在对至少一条所述相邻存储行进行刷新处理后，将所述存储行的第一标志位调整为第二状态，并重新累计所述存储行在单位时间内的连续被访问次数。
在一些实施例中，所述半导体存储器还包括第二标志位，多个所述存储行被分为若干个存储组，且一个所述第二标志位至少用于指示一个所述存储组中至少一个存储单元是否处于特定状态，所述特定状态包括被占用；在对至少一条所述相邻存储行进行刷新处理之前，所述方法还包括：
对所述相邻存储行所属的存储组的第二标志位进行读取；
若所述第二标志位处于第三状态，对所述相邻存储行进行刷新处理；
若所述第二标志位处于第四状态，对所述相邻存储行不进行刷新处理；以及执行下述步骤之一：结束所述锤击刷新指令的执行，或者，确定新的所述相邻存储行并返回执行对所述相邻存储行所属的存储组的第二标志位进行读取的步骤。
在一些实施例中，所述方法还包括：
在接收到内存分配指令后，将所述内存分配指令对应的存储组的第二标志位调整为第三状态；在接收到内存释放指令后，将所述内存释放指令对应的存储组的第二标志位调整为第四状态；或者，在对所述存储组进行刷新处理后，将所述存储组的所述第二标志位调整为所述第四状态；其中，所述内存分配指令是字线激活指令或者利用内存控制器中的第一预留码构造得到的；所述内存释放指令是利用内存控制器中的第二预留码构造得到的。
第三方面，本公开实施例提供了一种刷新方法，应用于包括多个存储行和多个第一标志位的半导体存储器，一个所述第一标志位用于指示一个所述存储行是否为行锤击事件的锤击行，所述方法包括：
在接收到锤击刷新指令后，对多个所述存储行的第一标志位进行读取，得到读取结果；
根据读取结果，在多个所述存储行中确定候选存储行；
根据所述候选存储行，确定待刷新存储行，并对所述待刷新存储行进行刷新处理。
在一些实施例中，所述根据读取结果，在多个所述存储行中确定候选存储行，包括：将第一标志位处于第一状态的存储行确定为锤击存储行；将所述锤击存储行直接确定为所述候选存储行；
相应地，所述根据所述候选存储行，确定待刷新存储行，包括：对所述候选存储行进行随机选择，将选择到的存储行的相邻存储行确定为所述待刷新存储行。
在一些实施例中，所述根据读取结果，在多个所述存储行中确定候选存储行，包括：将第一标志位处于第一状态的存储行确定为锤击存储行；将所述锤击存储行的相邻存储行确定为所述候选存储行；
相应地，所述根据所述候选存储行，确定待刷新存储行，包括：在所述候选存储行中进行随机选择，得到所述待刷新存储行。
在一些实施例中，所述半导体存储器还包括第二标志位，多个所述存储行被分为若干个存储组，且一个所述第二标志位至少用于指示一个所述存储组中至少一个存储单元是否处于特定状态，所述特定状态包括被占用；在确定所述待刷新存储行之后，包括：
对所述待刷新存储行所属的存储组的第二标志位进行读取；若所述第二标志位处于第三状态，则执行所述对所述待刷新存储行进行刷新处理的步骤；若所述第二标志位处于第四状态，则对所述待刷新存储行不进行刷新处理；以及执行下述步骤之一：结束所述锤击刷新指令的执行，或者，确定新的所述待刷新存储行并返回执行所述对所述待刷新存储行所属的存储组的第二标志位进行读取，确定待刷新存储行的步骤。
在一些实施例中，所述半导体存储器还包括第二标志位，多个所述存储行被分为若干个存储组，且一个所述第二标志位至少用于指示一个所述存储组中至少一个存储单元是否处于特定状态，所述特定状态包括被占用；
所述根据所述候选存储行，确定待刷新存储行，包括：
对所述候选存储行所属的存储组的第二标志位进行读取；在所述第二标志位处于第三状态的情况下，将所述候选存储行确定为二次候选存储行；在所述二次候选存储行中进行随机选择，得到所述待刷新存储行。
第四方面，本公开实施例提供了一种电子设备，该电子设备包括如第一方面所述的半导体存储器。
本公开实施例提供了一种半导体存储器、刷新方法和电子设备，该半导体存储器包括主存储区域和标记存储区域，主存储区域中设置多个存储行，标记存储区域中设置多个第一标志位；其中，每一存储行与一个第一标志位具有对应关系，且第一标志位用于指示存储行是否为行锤击事件的锤击行。这样，由于半导体存储器中新增了标记存储区域，通过第一标志位可以标记行锤击事件的锤击行，明确行锤击的攻击对象，能够提高行锤击事件的处置效果且节省功耗。
附图说明
图1为一种刷新操作的时序示意图；
图2为本公开实施例提供的一种半导体存储器的结构示意图；
图3为本公开实施例提供的一种半导体存储器的具体结构示意图一；
图4为本公开实施例提供的另一种半导体存储器的结构示意图；
图5为本公开实施例提供的一种半导体存储器的具体结构示意图二；
图6为本公开实施例提供的一种半导体存储器的具体结构示意图三；
图7为本公开实施例提供的一种刷新方法的流程示意图一；
图8为本公开实施例提供的一种刷新方法的流程示意图二；
图9为本公开实施例提供的一种刷新方法的流程示意图三；
图10为本公开实施例提供的一种刷新方法的流程示意图四；
图11为本公开实施例提供的一种刷新方法的流程示意图五；
图12A为本公开实施例提供的一种刷新方法的流程示意图六；
图12B为本公开实施例提供的一种刷新方法的流程示意图七；
图12C为本公开实施例提供的一种刷新方法的流程示意图八；
图13为本公开实施例提供的另一种刷新方法的流程示意图一；
图14为本公开实施例提供的另一种刷新方法的流程示意图二；
图15为本公开实施例提供的另一种刷新方法的流程示意图三；
图16为本公开实施例提供的另一种刷新方法的流程示意图四；
图17为本公开实施例提供的另一种刷新方法的流程示意图五；
图18为本公开实施例提供的另一种刷新方法的流程示意图六；
图19为本公开实施例提供的一种电子设备的组成结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅仅用于解释相关申请，而非对该申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关申请相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅是用于区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
目前，对于挥发性存储器而言，由于存储单元越来越密集，存储行之间的距离越来越小，导致相邻存储行之间的电容耦合增大。此时，如果重复激活某一存储行(称为锤击行)，可能导致相邻的存储行(也称为受害行)受到电磁干扰，从而受害行上的存储单元在下一次刷新之前丢失数据。以上情况被称为行锤击Row Hammer。行锤击可以在不访问目标内存区域的前提下使其产生数据错误，所以需要定期对锤击行附近的存储行进行刷新，防止数据错误。
具体地，在检测到某一区域遭受行锤击时，需要对该区域内的随机一条字线进行刷新。参见图1，其示出了一种刷新操作的时序示意图。如图1所示，在存储器接收到命令REFpb后，通过地址选择信号CBR选择8行字线(该数量需要依据存储器的具体刷新机制确定)，通过行激活信号开启被选择的8行字线，然后通过刷新信号REF对处于开启状态的字线进行刷新，从而完成一次周期刷新操作；在接收到行锤击命令(图中未示出)后，通过锤击刷新信号RHR来随机选择1行字线，通过行激活信号开启被选择字线，同时通过锤击刷新信号RHR对处于开启状态的字线进行刷新，从而完成一次针对行锤击的加刷操作。也就是说，在遭受行锤击时，半导体存储器无法准确定位攻击对象，处置效果较差且功耗较高。
基于此，本公开实施例提供了一种半导体存储器，由于半导体存储器中新增了标记存储区域，通过第一标志位可以标记行锤击事件的锤击行，明确行锤击的攻击对象，能够提高行锤击事件的处置效果且节省功耗。
下面将结合附图对本公开各实施例进行详细说明。
在本公开的一实施例中，参见图2，其示出了本公开实施例提供的一种半导体存储器10的结构示意图。如图2所示，半导体存储器10包括主存储区域11和标记存储区域12，主存储区域11中设置多个存储行(例如图1中的存储行111-1、存储行111-2……)，标记存储区域12中设置多个第一标志位(例如图1中的第一标志位121-1、第一标志位121-2……)；其中，每一存储行与一个第一标志位具有对应关系，且第一标志位用于指示存储行是否为行锤击事件的锤击行。
需要说明的是，半导体存储器10可以是挥发性存储器，例如动态随机存取存储器(Dynamic Random Access Memory，DRAM)。
在本公开实施例中，在半导体存储器10中，新增了标记存储区域12，用于对主存储区域11中各存储行是否为行锤击事件中的锤击行进行记录，能够准确定位行锤击事件的攻击对象，提高行锤击事件的处置效果。
在一些实施例中，存储行延伸到标记存储区域的部分用于形成存储行对应的第一标志位；其中，第一标志位占用一个存储单元。
示例性的，参见图3，其示出了本公开实施例提供的另一种半导体存储器的结构示意图。在图3中，半导体存储器包括多个不同的存储阵列(Bank)，每个存储阵列的一部分属于主存储区域(例如图3中的主存储区域0、主存储区域1……主存储区域n)，每个存储阵列的另一部分属于标记存储区域(例如图2中的标记存储区域0、标记存储区域1……标记存储区域n)。在图2中，每一个存储行(或称为字线)用Row表示，每一个存储列用Col(或称为位线)表示，存储行或者存储列的下标代表编号。在本公开实施例中，各编号仅用于标识各个存储行或者存储列，而不构成任何位置限定。另外，每个存储行和存储列构成的交叉点可视为存在一个存储单元。
如图3所示，存储行Row j与位线Col m形成存储行Row j的第一标志位，存储行Row j+1与位线Col m形成存储行Row j+1的第一标志位……其他可参照理解。这样，标记存储区域中的第一标志位与主存储区域共用了同一存储行，在其他实施例中，主存储区域和标记存储区域可以是两个相对独立的区域，标记存储区域中的标记位并不与主存储区域共用同一存储行。
需要说明的是，如图2或者图3所示，主存储区域11和标记存储区域12之间并无特定的位置关系。例如，标记存储区域12可以设置在主存储区域11的外侧，以存储行Row j为例，位线Col m位于位线Col i远离位线Col i+n的一侧，或者位线Col m位于位线Col i+n远离位线Col i的一侧；再例如，标记存储区域12可以设置在主存储区域11的内部之间，以存储行Row j为例，位线Col m位于位线Col i和位线Col i+n之间。
还需要说明的是，一个存储阵列可以设置1024条属于主存储区域的位线，设置1条属于标记存储区域的位线。也就是说，主存储区域11与标记存储区域12中的位线比例为1024:1，标记存储区域12的面积占比小于0.1％，所以设置标记存储区域12对于芯片面积的影响非常小。
在一些实施例中，半导体存储器10，用于在监测到存储行在单位时间内的连续被访问次数超过预设阈值时，将存储行的第一标志位调整为第一状态；或者，在对存储行的相邻存储行进行刷新操作后，将存储行的第一标志位调整为第二状态，并重新累计存储行在单位时间内的连续被访问次数。
如图4所示，在一些实施例中，多个存储行被分为若干个存储组(例如图4中的存储组112-1、存储组112-2)，标记存储区域12还设置有若干个第二标志位(例如图3中的第二标志位122-1、第二标志位122-2)；每一存储组与一个第二标志位具有对应关系，且第二标志位至少用于指示存储组中至少一个存储单元是否具有特定状态，特定状态包括被占用。
需要说明的是，存储组中包括的存储行数量需要根据实际应用场景进行确定，每一存储组中存储行的数量理论上是相同的，特殊情况下也可以不同。应理解，在图4中，每一存储组包括2个存储行，但实际应用场景中可以更多或更少。第二标志位用于记录存储组的状态信息。
在这里，特定状态至少包括被占用，还可以包括被损坏、被锁定、被释放等等。进一步地，在不同的应用场景中，存储单元的被占用可以具有不同的定义。例如，被占用是指该存储单元被分配给用户使用而尚未存储有效数据，或者被占用是指存储单元中存储有效数据。
可以理解的是，当每一存储行具有一第二标志位时，在行锤击事件中，就可以准确知晓受害行是否被占用；当包含多条存储行的每一存储组对应一第二标志位时，只能知道受害行可能被占用。如果受害行被占用，则需要对受害行进行刷新处理，防止数据丢失；如果受害行未被占用，则无需对受害行进行刷新处理，节省功耗；当受害行可能被占用时，也需要对受害行进行刷新处理。
应理解，第一标志位的位置和第二标志位的位置之间并无限制关系。例如，第一标志位可以与第二标志位相邻，或者，标记存储区域12可以划分为两个完全独立的区域，一个区域用于形成第一标志位，另一个区域用于形成第二标志位。
在一些实施例中，每一存储组均包括一个存储行，且存储行延伸到标记存储区域的部分用于形成存储组对应的第二标志位。
假设第二标志位占一个存储单元，以图5为例进行具体说明：存储行Row j与位线Col i～Col i+n所形成的存储单元构成一个存储组，存储行Row j与位线Col m+1形成该存储组的第二标志位；存储行Row j+1与位线Col i～Col i+n所形成的存储单元构成另一个存储组，存储行Row j+1与位线Col m+1形成该存储组的第二标志位，其他可参照理解。
在另一些实施例中，每一存储组均包括多个存储行，且其中一个存储行延伸到标记存储区域的部分用于形成存储组对应的第二标志位。
假设第二标志位占一个存储单元，以图6为例进行具体说明存储行Row j～Row j+a与位线Col i～Col i+n所形成的存储单元构成一个存储组，存储行Row j与位线Col m+1形成该存储组的第二标志位；存储行Row j+a+1～Row j+2a+1与位线Col i～Col i+n所形成的存储单元构成另一个存储组，存储行Row j+a+1与位线Col m+1形成该存储组的第二标志位，其他可参照理解。
另外，在图6中，为了避免存储空间的浪费，存储行Row j+a+2～Row j+2a+1与位线Col m+1也会形成相应的存储单元，这部分存储单元可以归属于主存储区域。
这样，如图5或者图6所示，标记存储区域中的第二标志位与主存储区域同样会共用同一存储行，在其他实施例中，标记存储区域中的第二标记位并不与主存储区域共用同一存储行。
需要说明的是，如图5或者图6所示，标记存储区域中的位线Col m和位线Col m+1可以设置在主存储区域中的一个外侧；或者，位线Col m和位线Col m+1可以分别设置在主存储区域中的相对两侧，此时第一标志位和第二标志位不仅能够起到标识作用，还可以起到保护存储组的作用，即存储阵列受损时会优先损坏标记存储区域而非是主存储区域，从而保证基础功能的有效性；或者，位线Col m和位线Col m+1可以设置在主存储区域中的内部，此时存储阵列受损时会优先损坏主存储区域而非是标记存储区域，但是主存储区域一般设置有冗余区域进行损坏替换，避免主存储区域无法工作；在一些实施例中，冗余区域也可以用于替换标记存储区域，保证标记功能的有效性。
需要说明的是，在特定状态包括至少两个的情况下，每一个第二标志位包括至少两个标识符，且不同的标识符用于指示不同的特定状态；其中，每一标识符占用一个存储单元。也就是说，一个第二标志位可以占据更多的存储单元，具体取决于特定状态的种类。
可以理解的是，标记存储区域12中位线的条数×每一存储组中存储行的条数≥标识符的数量，标识符的数量等于每一存储组中存储行的数量与第二标志位表征的特定状态的数量的和。具体地，在每个存储组包括一个存储行的情况下，标记存储区域12中可以存在至少三条位线，从而每一存储行延伸到标记存储区域的部分可以形成第一标志位和第二标志位中的至少两个标识符；或者，在每个存储组包括两条存储行的情况下，标记存储区域12存在至少两条位线，从而每一存储组中的每一存储行延伸到标记存储区域12的部分可以与第一条位线形成第一标志位，每一存储组中的至少两个存储行延伸到标记存储区域12的部分可以与第二条位线形成第二标志位中的至少两个标识符。
在一些实施例中，第二标志位的状态可以利用DRAM中已有的指令/操作进行定义。示例性的， 半导体存储器10，还用于在接收到针对存储单元的内存分配指令后，将存储单元所属的存储组的第二标志位调整为第三状态，其中，内存分配指令可以是字线激活指令Active；或者，在对存储组进行刷新操作后，将存储组的第二标志位调整为第四状态。
这样，在接收到字线激活指令Active之后，半导体存储器10激活指定存储行，并将该存储行所对应的第二标志位调整为第三状态。另外，在接收到刷新指令之后，半导体存储器10在对某个存储组进行刷新操作后，将该存储组的第二标志位调整为第四状态。如此，无需为第二标志位定义额外的状态控制指令，节省信令资源。
在另一些实施例中，第二标志位的状态可以基于DRAM中的内存申请/内存释放的功能进行构造。示例性的，半导体存储器10，还用于在接收到针对存储单元的内存分配指令后，将存储单元所属的存储组的第二标志位调整为第三状态，其中，内存分配指令是利用内存控制器中的第一预留码构造得到的；或者，在接收到针对于存储组的内存释放指令后，将存储组的第二标志位调整为第四状态；其中，内存释放指令是利用内存控制器中的第二预留码构造得到的。
应理解，半导体存储器10中存在一些模式寄存器(Mode Register)，每一模式寄存器中的操作码(Operand，OP)用于提供不同的控制功能，一些通用的操作码由行业标准进行规定，同时模式寄存器中还存在一些未经启用的预留码(Reserved For Use，RFU)。此时，可以通过这些预留码构造全新的Allocate指令作为内存分配指令，构造全新的Release指令作为内存释放指令。
这样，在半导体存储器的工作过程中，可以通过内存分配指令Allocate申请部分内存，并基于内存分配指令Allocate将被申请内存区域对应的存储组的第二标志位调整为第三状态；相应地，可以通过内存释放指令Release释放部分内存，以及基于内存释放指令Release将被释放内存区域对应的存储组的第二标志位调整为第四状态。如此，有利于更加精确的调整标准位的状态，保证刷新操作的准确执行。
在又一些实施例中，半导体存储器10，还用于在接收到针对存储单元的内存分配指令后，将存储单元所属的存储组的第二标志位调整为第三状态，其中，内存分配指令是字线激活指令Active；或者，在接收到针对于存储组的内存释放指令后，将存储组的第二标志位调整为第四状态；其中，内存释放指令是利用内存控制器中的第二预留码构造得到的。如此，在激活后与被释放之前，相应的第二标志位始终为第三状态，不受刷新操作的影响，能降低存储组对应的第二标志位的调整频率，降低功耗。
在前述说明中，第一状态是指第一标志位中存储有数据1，第二状态是指第一标志位中存储有数据0；或者，第一状态是指第一标志位中存储有数据0，第二状态是指第一标志位中存储有数据1。
第三状态是指第二标志位(或第二标志位中的相应标识符)中存储有数据1，第四状态是指第二标志位(或第二标志位中的相应标识符)中存储有数据0；或者，第三状态是指第二标志位(或第二标志位中的相应标识符)中存储有数据0，第四状态是指第二标志位(或第二标志位中的相应标识符)中存储有数据1。
综上所述，本公开实施例提供了一种新型存储结构，在半导体存储器中新增了标记存储区域，通过第一标志位可以标记行锤击事件的锤击行，通过第二标志位可以明确锤击行的相邻存储行是否被占用，进而决定是否对相邻存储行进行刷新，提高行锤击事件的处置效果且节省功耗。
在本公开的另一实施例中，参见图7，其示出了本公开实施例提供的一种刷新方法的流程示意图。如图7所示，该方法可以包括：
S21：在接收到锤击刷新指令后，在多个存储行中随机确定目标存储行。
S22：对目标存储行的第一标志位进行读取，得到读取结果。
S23：根据读取结果，确定是否对目标存储行的相邻存储行进行刷新处理。
需要说明的是，本公开实施例提供的刷新方法应用于包括多个存储行和多个第一标志位的半导体存储器，一个第一标志位和一个存储行具有关联关系，一个第一标志位用于指示一个存储行是否为行锤击事件的锤击行，具体可参见前述的图2或者图3。
特别地，在本公开实施例中，“随机”是一种宏观的概念，其中也包括一些伪随机机制。
在这里，将目标存储行记为第i行，那么相邻存储行可以是第(i+a)存储行～第(i-a)存储行中的随机一行；或者，相邻存储行可以是第(i+a)存储行～第(i-a)存储行中的所有行，a和i均为正整数，一般来说，i小于或等于3。
这样，本公开实施例提供了一种低功耗的行锤击刷新方法，在接收到锤击刷新指令后，通过目标存储行的第一标志位可以了解目标存储行是否遭受行锤击，进而决定是否刷新目标存储行的相邻存储行，能够提高行锤击事件的处置效果且减小功耗。
在一些实施例中，如图8所示，对于步骤S22，如果第一标志位处于第一状态，那么执行步骤S231；如果第一标志位处于第二状态，那么执行步骤S2321。
S231：对至少一条相邻存储行进行刷新处理。
S2321：对相邻存储行不进行刷新处理，结束锤击刷新指令的执行。
在另一些实施例中，如图9所示，对于步骤S22，如果第一标志位处于第二状态，也可以执行步骤S2322。
S2322：对相邻存储行不进行刷新处理，确定新的目标存储行，并返回执行步骤S22。
也就是说，如果第一标志位处于第一状态，说明目标存储行为行锤击事件中的锤击行，需要对相邻存储行进行刷新。如果第一标志位处于第二状态，说明目标存储行没有遭受行锤击，不需要对相邻存储行进行刷新，节省功耗。进一步地，在不对相邻存储组执行刷新处理的情况下，可以具有至少两种不同的处理机制：(1)等待，参见步骤S2321；(2)跳过，参见步骤S2322。
需要说明的是，在确定新的目标存储行时，可以在多个存储行中再次进行随机确定，也可以将原目标存储行的下一存储行或者上一存储行作为新的目标存储行。
在一些实施例中，该方法还包括：在监测到存储行在单位时间内的连续被访问次数超过预设阈值后，将存储行的第一标志位调整为第一状态；在对至少一条相邻存储行进行刷新处理后，将存储行的第一标志位调整为第二状态，并重新累计存储行在单位时间内的连续被访问次数。
在一些实施例中，如前述的图4～图6所示，半导体存储器还包括第二标志位，多个存储行被分为若干个存储组，且一个第二标志位于一个存储组具有对应关系，一个第二标志位至少用于指示一个存储组中至少一个存储单元是否处于特定状态，特定状态包括被占用。
因此，如图10所示，在目标存储行的第一标志位处于第一状态的情况下，该方法还包括：
S24：对相邻存储行所属的存储组的第二标志位进行读取。
在这里，对于步骤S24，如果第二标志位处于第三状态，那么执行步骤S241；如果第二标志位处于第四状态，那么执行步骤S2321。
S241：对相邻存储行进行刷新处理；可以理解的是，步骤S241也可以调整为对至少一相邻存储行进行刷新处理，实际进行刷新的相邻存储行可以通过随机的方式确定，即无需对定义的所有相邻存储行(目标存储行的相邻a行)都进行刷新操作。
S2321：对相邻存储行不进行刷新处理，结束锤击刷新指令的执行。
在另一些实施例中，如图11所示，对于步骤S24，如果第二标志位处于第四状态，也可以执行步骤S242。
S242：对相邻存储行不进行刷新处理，确定新的相邻存储行，并返回执行步骤S24。
需要说明的是，如果第二标志位处于第三状态，说明相邻存储行可能被占用，需要对相邻存储行执行刷新处理；如果第二标志位处于第四状态，说明相邻存储行必定未被占用，无需对相邻存储行执行刷新处理，节省功耗。进一步地，在不对相邻存储行进行刷新处理的情况下，可以具有至少两种不同的处理机制：(1)等待：参见步骤S2321；(2)跳过：参见步骤S242。
在这里，如果相邻存储行是指第(a+i)存储行～第(a-i)存储行中的所有行，那么只有在第(a+i)存储行～第(a-i)存储行各自对应的第二标志位均处于第四状态的情况下，才会执行“等待”或者“跳过”机制；同时，对于“跳过”机制而言，需要在其余存储行中确定新的目标存储行，并将新的目标存储行的相邻存储行作为新的相邻存储行。
如果相邻存储行是指第(a+i)存储行～第(a-i)存储行中的随机一行，那么如果随机确定的存储行的第二标志位处于第四状态，则执行“等待”或者“跳过”机制；同时，对于“跳过机制”而言，可以在(原目标存储行的)第(a+i)存储行～第(a-i)存储行中随机确定新的相邻存储行。特别地，如果(原目标存储行的)第(a+i)存储行～第(a-i)存储行的第二标志位均处于第四状态，则需要确定新的目标存储行，并将新的目标存储行的相邻存储行作为新的相邻存储行。
也就是说，对于“等待”机制，每一个锤击刷新指令不一定会产生刷新操作；对于“跳过”机制，每一个锤击刷新指令必定会产生刷新操作。另外，半导体存储器中可能存在以下特殊情况：仅有存储行0是行锤击事件中的锤击行，但是存储行0的所有相邻行均未被占用，此时半导体存储器其实不存在需要被刷新的“相邻存储行”，对于“跳过”机制而言，会导致半导体存储器无法结束该锤击刷新指令，或者说确定得到的连续几个目标存储行的相邻存储行都不需要刷新，导致锤击刷新命令的执行时间过长。因此，对于采用“跳过”机制的半导体存储器而言，还可以设置一个辅助终止机制：在接收到锤击刷新指令后的一定时间内，即使未执行刷新处理，也视为锤击刷新指令结束。
在一些实施例中，该方法还包括：在接收到内存分配指令后，将内存分配指令对应的存储组的 第二标志位调整为第三状态；在对存储组进行刷新处理后，将存储组的第二标志位调整为第四状态。此时，内存分配指令可以是指字线激活指令Active。
需要说明的是，刷新处理可以是根据前述的锤击刷新指令执行的，也可以是根据其他指令(例如周期刷新指令)执行的。
在另一些实施例中，该方法还包括：在接收到内存分配指令后，将内存分配指令对应的存储组的第二标志位调整为第三状态；在接收到内存释放指令后，将内存释放指令对应的存储组的第二标志位调整为第四状态。此时，内存分配指令是通过第一预留码构造得到的Allocate指令，内存释放指令是通过第二预留码构造得到的Release指令。
在又一些实施例中，该方法还包括：在接收到针对存储单元的内存分配指令后，将存储单元所属的存储组的第二标志位调整为第三状态；或者，在对存储组进行刷新处理后，将存储组的第二标志位调整为第四状态。此时，内存分配指令可以是指字线激活指令Active。
这样，本公开实施例提供了一种新的锤击刷新方法，在锤击刷新过程中，可以准确定位攻击对象，而且对于一个存储阵列(Bank)中从未访问过(即未被占用)的存储行不进行刷新，从而提高行锤击事件的处置效果且降低刷新功耗。另外，本公开实施例提供的刷新方法还可以选择与DRAM中的申请/释放内存的功能相结合，从而以更高的准确度进行刷新操作。
基于前述的思想，针对前述的图3，假设第一状态是第一标志位存储有数据1，第二状态是第一标志位存储有写入数据0，以下提供刷新方法的两种具体实施方式。
在第一种具体实施方式中，如图3和图12A所示，该方法可以包括：
S311：访问存储行Row i。
S312：判断单位时间内存储行Row i的连续被访问次数是否大于预设阈值。
在这里，对于步骤S312，如果判断结果为是，则执行步骤S313。
需要说明的是，在半导体存储器的上电初始化时，向主存储区域和标记存储区域均写入数据0。此时，主存储区域中所有的存储单元还未被写入数据，且所有的存储行未遭受行锤击，因此标记存储区域中所有的第一标记位均为第二状态。
在半导体存储器的工作过程中，累计存储行Row i在单位时间内的被访问次数，以确定存储行Row i是否为行锤击事件中的存储行。在这里，存储行Row i是指图3中的任意一个存储行，标志位Row iCol m是指存储行Row i与位线Col m所形成的第一标志位。
示例性的，在接收到针对存储行Row i的字线激活指令Active时，视为“访问存储行Row i”。
S313：将存储行Row i对应的第一标志位Row iCol m调整为第一状态。
需要说明的是，通过向标志位Row iCol m写入数据1，将第一标志位Row iCol m调整为第一状态。
如图3和图12B所示，该方法还包括：
S321：对存储行Row i进行Row Hammer刷新。
需要说明的是，在确定发生行锤击事件时，在存储阵列中随机选择一个目标存储行作为刷新对象，在此将被选择的刷新对象记为存储行Row i。
应理解，步骤S321和步骤S311并无特定的执行顺序。
S322：判断存储行Row i对应的第一标志位Row iCol m是否处于第一状态。
在这里，对于步骤S322，如果判断结果为否，则执行步骤S323；如果判断结果为是，则执行步骤S3241。
S323：确定新的存储行Row i，并返回执行步骤S322。
需要说明的是，如果第一标志位Row iCol m存储有数据0，则确定新的存储行Row i，直至某一存储行的第一标志位存储有数据1。
S3241：对存储行Row i+1和Row i-1进行刷新，将存储行Row i对应的第一标志位Row iCol m调整为第二状态。
需要说明的是，在对相邻存储行Row i+1和Row i-1进行刷新后，向第一标志位Row iCol m写入数据0。
S325：等待下一次锤击刷新指令。
在另一种具体的实施例中，如图12C所示，对于步骤S322，如果判断结果为是，还可以执行步骤S3242。
S3242：在存储行Row i+a到存储行Row i-a中随机选择1个存储行进行刷新，将存储行Row i对应的第一标志位Row iCol m调整为第二状态。
如此，可以大幅降低锤击刷新的功耗。
在又一种具体的实施例中，对于步骤S322，如果判断结果为否，也可以视为结束本次锤击刷新指令，直接执行步骤S325。这样，对于接收到的刷新指令，可能不会执行刷新操作。
综上所述，本公开实施例提供了一种锤击刷新的工作方法，应用于设置有标记存储区域的半导体存储器，通过第一标志位可以准确定位行锤击事件中的锤击行，提高行锤击事件的处置效果并降低功耗。除此之外，通过第二标志位，可以明确锤击行的相邻存储行是否被占用，进而决定是否对相邻存储行进行刷新，节省功耗。
在本公开的又一实施例中，参见图13，其示出了本公开实施例提供的一种刷新方法的流程示意图。如图13所示，该方法可以包括：
S41：在接收到锤击刷新指令后，对多个存储行的第一标志位进行读取，得到读取结果。
S42：根据读取结果，在多个存储行中确定候选存储行。
S43：根据候选存储行，确定待刷新存储行。
S44：对待刷新存储行进行刷新处理。
需要说明的是，本公开实施例提供的刷新方法应用于包括多个存储行和多个第一标志位的半导体存储器，一个第一标志位与一个存储行具有对应关系，一个第一标志位用于指示一个存储行是否为行锤击事件的锤击行，具体如前述的图2或者图3所示。
需要说明的是，待刷新存储行的数量不限，可以是一条，也可以是多条。在这里，相邻存储行的含义参见前述说明，其数量可以为一条，也可以为多条。
这样，本公开实施例提供了一种低功耗的行锤击刷新方法，在接收到锤击刷新指令后，可以根据存储行的第一标志位筛选出行锤击事件的受害行，进而执行刷新处理，能够提高行锤击事件的处置效果并减少功耗。
在一些实施例中，候选存储行指的是行锤击事件中的锤击行。因此，刷新对象需要在候选存储行的相邻存储行中进行选择。
相应地，如图14所示，步骤S42具体可以包括：
S421：将第一标志位处于第一状态的存储行确定为锤击存储行，将锤击存储行直接确定为候选存储行。
步骤S43具体可以包括：
S431：对候选存储行进行随机选择，将选择到的存储行的相邻存储行确定为待刷新存储行。
在另一些实施例中，候选存储行指的是行锤击事件中的受害行。因此，刷新对象可以直接在候选存储行中进行选择。
相应地，如图15所示，步骤S42具体可以包括：
S422：将第一标志位处于第一状态的存储行确定为锤击存储行，将锤击存储行的相邻存储行确定为候选存储行。
步骤S43具体可以包括：
S432：在候选存储行中进行随机选择，得到待刷新存储行。
这样，通过第一标志位，可以对存储行进行筛选，从而缩小有效刷新对象的范围，提高行锤击事件的处置效果。
如前述的图4～图6所示，半导体存储器还包括第二标志位，多个存储行被分为若干个存储组，且一个第二标志位与一个存储组具有对应关系，一个第二标志位至少用于指示一个存储组中至少一个存储单元是否处于特定状态，特定状态包括被占用。
因此，在一些实施例中，如图16所示，在步骤S43之后，该方法还可以包括：
S45：对待刷新存储行所属的存储组的第二标志位进行读取。
在这里，对于步骤S45，如果第二标志位处于第三状态，那么执行步骤S44；如果第二标志位处于第四状态，那么执行步骤S461。
S44：对待刷新存储行进行刷新处理。
S461：对待刷新存储行不进行刷新处理，结束锤击刷新指令的执行。
在另一些实施例中，如图17所示，对于步骤S45，如果第二标志位处于第四状态，也可以选择执行步骤S462。
S462：对待刷新存储行不进行刷新处理，确定新的待刷新存储行，并返回执行步骤S45。
这样，如果第二标志位处于第三状态，说明待刷新存储行可能被占用，需要对待刷新存储行进行刷新处理；如果第二标志位处于第四状态，说明待刷新存储行必定未被占用，无需对待刷新存储行进行刷新处理，节省功耗。类似地，在不对待刷新存储行执行刷新处理的情况下，可以具有至少 两种不同的处理机制：(1)等待：参见步骤S461；(2)跳过：参见步骤S462。
在这里，如果候选存储行是行锤击事件中的受害行，对于“跳过”机制而言，新的待刷新存储行可以是在其余候选存储行进行随机选择确定的；如果候选存储行是行锤击事件中的锤击行，且相邻存储行是指第(a+i)存储行～第(a-i)存储行中的所有行，对于“跳过”机制而言，新的待刷新存储行可以是随机选择的其余候选存储行的相邻存储行；如果候选存储行是行锤击事件中的锤击行，且相邻存储行是指第(a+i)存储行～第(a-i)存储行中的随机一行，对于“跳过”机制而言，新的待刷新存储行可以是在第(a+i)存储行～第(a-i)存储行进行再次随机选择确定的；如果第(a+i)存储行～第(a-i)存储行中所有的存储行的第二标志位均处于第四状态，则新的待刷新存储行可以是随机选择的其余候选存储行的相邻存储行。
需要说明的是，如果候选存储行是行锤击事件的受害行，也可以根据第二标志位对候选存储行进行二次筛选，确定出被占用的受害行，再进行刷新操作。相应地，在一些实施例中，如图18所示，步骤S43具体可以包括：
S4331：对候选存储行所属的存储组的第二标志位进行读取。
S4332：在第二标志位处于第三状态的情况下，将候选存储行确定为二次候选存储行。
S4333：在二次候选存储行中进行随机选择，得到待刷新存储行。
这样，利用第二标志位进一步缩小候选存储行的范围，即二次候选存储行是指“行锤击事件的受害行”且“被占用”的存储行，因此直接对二次候选行中随机选择的一行进行刷新即可。
综上所述，本公开实施例提供了一种锤击刷新的工作方法，应用于设置有标记存储区域的半导体存储器，通过第一标志位可以准确定位行锤击事件中的锤击行，提高行锤击事件的处置效果并降低功耗；同时通过第二标志位，可以明确锤击行的相邻存储行是否被占用，进而决定是否对相邻存储行进行刷新，节省功耗。
在本公开的再一实施例中，参见图19，其示出了本公开实施例提供的一种电子设备50的结构示意图。如图19所示，电子设备50可以包括前述的半导体存储器10。
在本公开实施例中，半导体存储器10可以为DRAM芯片。
本公开实施例提供了一种电子设备50，其中包含半导体存储器10，且半导体存储器10新增了标记存储区域，通过第一标志位可以准确定位行锤击事件中的锤击行，提高行锤击事件的处置效果并降低功耗。
以上，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围。
需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。
本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种半导体存储器、刷新方法和电子设备，该半导体存储器包括主存储区域和标记存储区域，主存储区域中设置多个存储行，标记存储区域中设置多个第一标志位；其中，每一存储行与一个第一标志位具有对应关系，且第一标志位用于指示存储行是否为行锤击事件的锤击行。这样，由于半导体存储器中新增了标记存储区域，通过第一标志位可以标记行锤击事件的锤击行，明确行锤击的攻击对象，能够提高行锤击事件的处置效果且节省功耗。

Claims (17)

  1. 一种半导体存储器，所述半导体存储器包括主存储区域和标记存储区域，所述主存储区域中设置多个存储行，所述标记存储区域中设置多个第一标志位；其中，
    每一所述存储行与一个所述第一标志位具有对应关系，且所述第一标志位用于指示所述存储行是否为行锤击事件的锤击行。
  2. 根据权利要求1所述的半导体存储器，其中，
    所述存储行延伸到所述标记存储区域的部分用于形成所述存储行对应的第一标志位；
    其中，所述第一标志位占用一个存储单元。
  3. 根据权利要求1所述的半导体存储器，其中，
    所述半导体存储器，用于在监测到存储行在单位时间内的连续被访问次数超过预设阈值时，将所述存储行的第一标志位调整为第一状态；或者，
    在对所述存储行的相邻存储行进行刷新操作后，将所述存储行的第一标志位调整为第二状态，并重新累计所述存储行在所述单位时间内的连续被访问次数。
  4. 根据权利要求1所述的半导体存储器，其中，多个所述存储行被分为若干个存储组，所述标记存储区域还设置有若干个第二标志位；
    每一所述存储组与一个所述第二标志位具有对应关系，且所述第二标志位至少用于指示所述存储组中至少一个存储单元是否具有特定状态，所述特定状态包括被占用。
  5. 根据权利要求4所述的半导体存储器，其中，
    每一所述存储组均包括一个存储行，且所述存储行延伸到所述标记存储区域的部分用于形成所述存储组对应的第二标志位；或者
    每一所述存储组均包括多个存储行，且其中一个所述存储行延伸到所述标记存储区域的部分用于形成所述存储组对应的第二标志位。
  6. 根据权利要求4所述的半导体存储器，其中，
    所述半导体存储器，还用于在接收到针对存储单元的内存分配指令后，将所述存储单元所属的存储组的第二标志位调整为第三状态；或者，
    在接收到针对于所述存储组的内存释放指令后，将所述存储组的第二标志位调整为第四状态；或者，
    在对所述存储组进行刷新操作后，将所述存储组的第二标志位调整为所述第四状态；
    其中，所述内存分配指令是字线激活指令或者利用内存控制器中的第一预留码构造得到的，所述内存释放指令是利用内存控制器中的第二预留码构造得到的。
  7. 一种刷新方法，应用于包括多个存储行和多个第一标志位的半导体存储器，一个所述第一标志位用于指示一个所述存储行是否为行锤击事件的锤击行，所述方法包括：
    在接收到锤击刷新指令后，在多个所述存储行中随机确定目标存储行；
    对所述目标存储行的第一标志位进行读取，得到读取结果；
    根据所述读取结果，确定是否对所述目标存储行的相邻存储行进行刷新处理。
  8. 根据权利要求7所述的刷新方法，其中，所述根据所述读取结果，确定是否对所述目标存储行的相邻存储行进行刷新处理，包括：
    在所述第一标志位处于第一状态时，对至少一条所述相邻存储行进行刷新处理；
    在所述第一标志位处于第二状态时，对所述相邻存储行不进行刷新处理；以及执行下述步骤之一：结束所述锤击刷新指令的执行，或者，确定新的目标存储行并返回执行所述对所述目标存储行的第一标志位进行读取的步骤。
  9. 根据权利要求8所述的刷新方法，其中，所述方法还包括：
    在监测到存储行在单位时间内的连续被访问次数超过预设阈值后，将所述存储行的第一标志位调整为第一状态；
    在对至少一条所述相邻存储行进行刷新处理后，将所述存储行的第一标志位调整为第二状态，并重新累计所述存储行在单位时间内的连续被访问次数。
  10. 根据权利要求9所述的刷新方法，其中，所述半导体存储器还包括第二标志位，多个所述存储行被分为若干个存储组，且一个所述第二标志位至少用于指示一个所述存储组中至少一个存储单元是否处于特定状态，所述特定状态包括被占用；在对至少一条所述相邻存储行进行刷新处理之前，所述方法还包括：
    对所述相邻存储行所属的存储组的第二标志位进行读取；
    若所述第二标志位处于第三状态，对所述相邻存储行进行刷新处理；
    若所述第二标志位处于第四状态，对所述相邻存储行不进行刷新处理；以及执行下述步骤之一：结束所述锤击刷新指令的执行，或者，确定新的所述相邻存储行并返回执行对所述相邻存储行所属的存储组的第二标志位进行读取的步骤。
  11. 根据权利要求10所述的刷新方法，其中，所述方法还包括：
    在接收到内存分配指令后，将所述内存分配指令对应的存储组的第二标志位调整为第三状态；
    在接收到内存释放指令后，将所述内存释放指令对应的存储组的第二标志位调整为第四状态；或者，在对所述存储组进行刷新处理后，将所述存储组的所述第二标志位调整为所述第四状态；
    其中，所述内存分配指令是字线激活指令或者利用内存控制器中的第一预留码构造得到的；所述内存释放指令是利用内存控制器中的第二预留码构造得到的。
  12. 一种刷新方法，应用于包括多个存储行和多个第一标志位的半导体存储器，一个所述第一标志位用于指示一个所述存储行是否为行锤击事件的锤击行，所述方法包括：
    在接收到锤击刷新指令后，对多个所述存储行的第一标志位进行读取，得到读取结果；
    根据读取结果，在多个所述存储行中确定候选存储行；
    根据所述候选存储行，确定待刷新存储行，并对所述待刷新存储行进行刷新处理。
  13. 根据权利要求12所述的刷新方法，其中，所述根据读取结果，在多个所述存储行中确定候选存储行，包括：
    将第一标志位处于第一状态的存储行确定为锤击存储行；
    将所述锤击存储行直接确定为所述候选存储行；
    相应地，所述根据所述候选存储行，确定待刷新存储行，包括：
    对所述候选存储行进行随机选择，将选择到的存储行的相邻存储行确定为所述待刷新存储行。
  14. 根据权利要求12所述的刷新方法，其中，所述根据读取结果，在多个所述存储行中确定候选存储行，包括：
    将第一标志位处于第一状态的存储行确定为锤击存储行；
    将所述锤击存储行的相邻存储行确定为所述候选存储行；
    相应地，所述根据所述候选存储行，确定待刷新存储行，包括：
    在所述候选存储行中进行随机选择，得到所述待刷新存储行。
  15. 根据权利要求13或者14所述的刷新方法，其中，所述半导体存储器还包括第二标志位，多个所述存储行被分为若干个存储组，且一个所述第二标志位至少用于指示一个所述存储组中至少一个存储单元是否处于特定状态，所述特定状态包括被占用；在确定所述待刷新存储行之后，包括：
    对所述待刷新存储行所属的存储组的第二标志位进行读取；
    若所述第二标志位处于第三状态，则执行所述对所述待刷新存储行进行刷新处理的步骤；
    若所述第二标志位处于第四状态，则对所述待刷新存储行不进行刷新处理；以及执行下述步骤之一：结束所述锤击刷新指令的执行，或者，确定新的所述待刷新存储行并返回执行所述对所述待刷新存储行所属的存储组的第二标志位进行读取，确定待刷新存储行的步骤。
  16. 根据权利要求14所述的刷新方法，其中，所述半导体存储器还包括第二标志位，多个所述存储行被分为若干个存储组，且一个所述第二标志位至少用于指示一个所述存储组中至少一个存储单元是否处于特定状态，所述特定状态包括被占用；
    所述根据所述候选存储行，确定待刷新存储行，包括：
    对所述候选存储行所属的存储组的第二标志位进行读取；
    在所述第二标志位处于第三状态的情况下，将所述候选存储行确定为二次候选存储行；
    在所述二次候选存储行中进行随机选择，得到所述待刷新存储行。
  17. 一种电子设备，所述电子设备至少包括权利要求1-6任一项所述的半导体存储器。
PCT/CN2022/098668 2022-04-08 2022-06-14 半导体存储器、刷新方法和电子设备 WO2023193340A1 (zh)

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