WO2023193143A1

WO2023193143A1 - Method for manufacturing electronic device and electronic device

Info

Publication number: WO2023193143A1
Application number: PCT/CN2022/085348
Authority: WO
Inventors: 金兰; 刘铁军; 朱靖华
Original assignee: 华为技术有限公司
Priority date: 2022-04-06
Filing date: 2022-04-06
Publication date: 2023-10-12

Abstract

The present disclosure relates to a method for manufacturing an electronic device, and an electronic device. The electronic device comprises a substrate. The method comprises: forming a pseudo gate on a substrate, a top surface of the pseudo gate comprising a first region, and a second region different from the first region, the first region comprising silicon nitride, and the second region comprising silicon oxide. The method further comprises: nitriding the second region of the pseudo gate without nitriding the first region of the pseudo gate, so as to form a silicon oxynitride protective layer only on the second region. According to the described method, it is possible to prevent a horn-shaped protrusion from being formed during the manufacture of an electronic device, thereby ensuring the yield of the electronic device.

Description

Method of manufacturing electronic device and electronic device

Technical field

The present disclosure relates to the field of integrated circuits, and more specifically to a method of manufacturing an electronic device and an electronic device.

Background technique

With the rapid development of integrated circuits, integrated circuits have been able to manufacture a large number of devices on a single silicon chip. In this context, the performance of traditional integrated circuits can no longer meet today's needs. In addition, in order to enable silicon chips to meet a variety of different usage scenarios, their sizes are getting smaller and smaller. As a result, the complexity and circuit density (that is, the number of devices that can be assembled into a given chip area) on existing silicon chips are increasing.

Although existing silicon chips have undergone significant improvements, such device designs still have many limitations. For example, some designs are often difficult to manufacture and often require complex manufacturing processes and structures. At the same time, the yield of this device also needs to be improved. As can be seen from the above, there is still a desire to improve the technology for manufacturing semiconductor electronic devices.

Contents of the invention

In view of the above problems, in order to improve the performance and yield of electronic devices, embodiments of the present disclosure provide a method of manufacturing an electronic device and a corresponding electronic device.

In a first aspect of the present disclosure, a method of manufacturing an electronic device is provided. The electronic device includes a substrate, the method includes: forming a dummy gate on the substrate, wherein the dummy gate has a first region and a second region different from the first region on a top surface, and wherein the first region Containing silicon nitride, the second region contains silicon oxide; and nitriding the second region of the dummy gate without nitriding the first region of the dummy gate, thereby forming nitrogen only above the second region Silicon oxide protective layer.

According to the method of the present disclosure, only the second region having silicon oxide is nitrided, thereby forming a silicon oxynitride protective layer only over the second region. Such a silicon nitride oxide protective layer can avoid the problem of bumps in existing designs, thereby improving the yield of electronic devices.

In an implementation manner of the first aspect, the method further includes: after forming the silicon oxynitride protective layer, etching the substrate to form a source and drain growth region. Using this method, selective nitridation can be performed before forming the source and drain growth regions and epitaxial growth, thereby expanding its applicable scenarios.

In an implementation of the first aspect, the method further includes: after forming the dummy gate and before forming the silicon oxynitride protective layer, performing a first etching on the substrate to form a pre-source and drain growth region ; and after forming the silicon oxynitride protective layer, perform a second etching on the pre-source and drain growth regions to form the final source and drain growth regions. In this way, selective nitridation can be performed after forming the pre-source and drain growth regions and before forming the final source and drain growth regions, thereby expanding its applicable scenarios.

In an implementation manner of the first aspect, the method further includes: after forming the dummy gate and before forming the silicon oxynitride protective layer, etching the substrate to form a source and drain growth region. Using this method, selective nitridation can be performed after forming the final source and drain growth regions, thereby expanding its applicable scenarios.

In an implementation manner of the first aspect, the method further includes: filling the source and drain growth regions to grow the epitaxial portion. In this way, an epitaxial part that meets the device design requirements can be obtained.

In an implementation of the first aspect, the method further includes: before nitriding or filling, pre-cleaning the substrate and the dummy gate to remove the intrinsic oxide layer on the surface of the substrate and the dummy gate. . In this way, the impact of oxygen in the environment on subsequent processes can be reduced or even avoided.

In an implementation of the first aspect, the nitridation is performed using a nitrogen plasma. In this way, a silicon oxynitride protective layer that meets the design requirements can be obtained.

In an implementation of the first aspect, nitriding is performed under the following parameters: a temperature of 200°C to 600°C, a pressure of 0 to 20 Torr, and an ambient gas of one or more of N ₂ , Ar, and He. kind. In this way, by performing nitridation under appropriate temperature, pressure and other environments, the quality of the finished electronic device can meet the desired requirements.

In an implementation of the first aspect, the nitriding is performed under continuous or pulsed power. Using this method, nitriding can be achieved in a variety of environments, thereby making the implementation of the present disclosure flexible in usage scenarios.

In an implementation manner of the first aspect, forming the dummy gate includes: forming an active region and a shallow channel isolation region on the substrate; and sequentially forming multiple layers above the active region and the shallow channel isolation region. structure, a multi-layer structure including a silicon oxide layer on top; etching the multi-layer structure on the first part of the active region and the shallow trench isolation region, and retaining the features of the active region that are different from the first part a multilayer structure on the second portion, thereby forming surface silicon nitride on the side of the shallow trench isolation region, the first portion, the silicon oxide layer and the multilayer structure; and removing the shallow trench isolation region, the The first portion and surface silicon nitride are formed over the silicon oxide layer to form the dummy gate. In this way, dummy gates can be formed on the substrate for subsequent processing.

In an implementation of the first aspect, the first region includes silicon nitride on the sides of the multilayer structure, and wherein the second region includes a silicon oxide layer. In this way, by nitriding only the areas containing silicon oxide, it is possible to avoid the formation of horn-shaped bumps by forming a protective layer.

In an implementation of the first aspect, the multi-layer structure further includes a gate oxide layer, a silicon layer and a silicon nitride layer in a stacked structure located below the silicon oxide layer, and wherein the silicon nitride layer serves as the silicon layer barrier during etching. In this way, the main part of the multilayer structure can be left unaffected in the nitrided device.

In a second aspect of the present disclosure, an electronic device is provided. The electronic device is manufactured using a method according to the first aspect of the present disclosure.

It should be understood that what is described in this summary is not intended to identify key or important features of the implementations of the disclosure, nor to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the description below.

Description of the drawings

The above and other features, advantages and aspects of various implementations of the present disclosure will become more apparent with reference to the following detailed description taken in conjunction with the accompanying drawings. In the drawings, the same or similar reference numbers represent the same or similar elements, where:

1A to 1B illustrate a method of manufacturing an electronic device in the prior art;

2A-2D illustrate steps of a method for forming a dummy gate according to an exemplary implementation of the present disclosure;

3A to 3D illustrate various steps of a method for manufacturing an electronic device according to an exemplary implementation of the present disclosure;

4A to 4D illustrate various steps of a method for manufacturing an electronic device according to another exemplary implementation of the present disclosure; and

5A-5D illustrate various steps of a method for manufacturing an electronic device according to yet another exemplary implementation of the present disclosure.

Detailed ways

Implementations of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain implementations of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure may be implemented in various forms and should not be construed as limited to the implementations set forth herein, but rather these implementations are provided for A more thorough and complete understanding of this disclosure. It should be understood that the drawings and implementations of the present disclosure are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

In describing implementations of the present disclosure, the term "including" and similar expressions should be understood as an open-ended inclusion, ie, "including but not limited to." The term "based on" should be understood to mean "based at least in part on." The term "one implementation" or "the implementation" shall be understood to mean "at least one implementation". The terms "first," "second," etc. may refer to different or the same object. The term "and/or" means at least one of the two items associated with it. For example, "A and/or B" means A, B, or A and B. Other explicit and implicit definitions may be included below.

It should be understood that for the technical solutions provided by the implementation of this disclosure, in the following introduction of specific implementations, some overlapping points may not be described again, but it should be considered that these specific implementations have mutual references and can be combined with each other.

1A to 1B illustrate a method of manufacturing an electronic device 1' in the prior art. 1A, in the existing process of preparing an electronic device 1', it is common to form a multi-layer structure composed of a silicon layer 14', a silicon nitride layer 15' and a silicon oxide layer 16' above the substrate 10'. The way. However, for this structure, in the process of forming the source and drain growth regions 120', it is necessary to strictly control the etching ratio of silicon nitride and silicon oxide, otherwise it will be easy to form on the shoulders of the upper end of the silicon layer 14' as shown in the figure. 1B shows the horn-shaped protrusion 25'. In addition, during the pre-cleaning process before growing the epitaxial portion 130' in the source and drain growth regions 120', if the etching ratio is inappropriate, the above-mentioned bumps 25' will also be easily formed. However, the etching ratio of silicon nitride to silicon oxide is actually difficult to accurately control, so the protrusion 25' in the existing solution is unavoidable. During chemical mechanical polishing, the horn-shaped protrusions 25' will affect the performance of the electronic device 1'. Therefore, as mentioned above, it is always difficult to improve the yield of the final electronic device 1'. How to effectively eliminate this protrusion 25' in the existing solution to ensure the yield is a challenge faced in this field.

At least to solve the above problems, embodiments of the present disclosure disclose a method of manufacturing an electronic device 1 and a corresponding device. Some illustrative embodiments of the present disclosure are described in detail below with reference to FIGS. 2A to 5D .

In a first aspect of the present disclosure, a method of manufacturing an electronic device 1 is provided. The electronic device 1 includes a substrate 10 , and the method includes: forming a dummy gate 20 on the substrate 10 . The dummy gate 20 can be formed by various methods. The embodiments of the present disclosure do not limit this.

2A-2D illustrate steps of a method for forming a dummy gate according to an exemplary implementation of the present disclosure. As shown in FIG. 2A , an active region 11 and a shallow channel isolation region 12 are first formed on the substrate 10 . Subsequently, as shown in FIG. 2B , a multilayer structure 17 is formed over the active region 11 and the shallow trench isolation region 12 . In a specific embodiment, the multi-layer structure 17 may include a gate oxide layer 13, a silicon layer 14, a silicon nitride layer 15 and a silicon oxide layer 16 in a stacked structure from bottom to top. As shown in FIG. 2B , the silicon oxide layer 16 is located at the top of the multi-layer structure 17 , and in the multi-layer structure 17 , the silicon nitride layer 15 can be used as a barrier layer for the silicon layer 14 during etching. The multi-layer structure 17 is then etched. As shown in FIG. 2C , the etching does not occur on the entire multi-layer structure 17 , but only on the first portion 111 located in the active region 11 and the shallow channel isolation region. The portion of the multi-layer structure 17 on the active area 11 is etched, and the portion of the multi-layer structure 17 on the second portion 112 of the active area 11 that is different from the first portion 111 is retained. After such etching, the surface silicon nitride 180 shown in FIG. 2C can be formed. The surface silicon nitride 180 can be formed on the etched area. Such areas include horizontal surfaces, such as shallow trench isolation areas 12, The first portion 111 of the active area 11 and the silicon oxide layer 16 . In addition, the surface silicon nitride 180 may also be formed on a vertical surface, such as the side 170 of the multilayer structure 17, to form sidewalls. Subsequently, as shown in FIG. 2D , the shallow channel isolation region 12 , the first portion 111 of the active region 11 and the surface silicon nitride formed above the silicon oxide layer 16 are removed to finally obtain the dummy gate 20 . As shown, the thickness of surface silicon nitride 180 on side 170 of multilayer structure 17 is increased compared to FIGS. 2D and 2C .

Continuing reference will now be made to FIGS. 3A to 5D , which illustrate different implementations of the method of manufacturing the electronic device 1 according to the present disclosure.

Embodiment 1

3A to 3D illustrate various steps of a method of manufacturing the electronic device 1 according to an exemplary embodiment of the present disclosure. The dummy gate 20 in FIG. 3A may be formed by the method described above in conjunction with FIGS. 2A to 2D . 3A and 2D , the top surface of the dummy gate 20 can be divided into a first area 210 and a second area 220 different from the first area 210 , where the first area 210 includes a second area on the side 170 of the multi-layer structure 17 Surface silicon nitride 180 , while second region 220 includes silicon oxide layer 16 on dummy gate 20 .

As shown in FIG. 3B , the dummy gate 20 is nitrided. During this process, only the second region 220 is nitrided without the first region 210 , so that the silicon oxynitride protective layer 230 is only formed over the second region 220 . In some embodiments, in order to ensure the effective implementation of the process, the influence of oxygen atoms in the environment needs to be eliminated. To this end, a pre-cleaning operation may be performed before nitriding to remove the intrinsic oxide layer formed by oxygen atoms. According to the embodiment here, on the top of the silicon layer 14, since the second region 220 for protecting silicon oxide has been nitrided into the silicon oxynitride protective layer 230, during the pre-cleaning process, the silicon oxynitride protective layer 230 will not Etched away. In this way, the horn-shaped protrusion 25' in the existing solution can be effectively prevented from being formed on the shoulder of the upper end of the silicon layer 14.

Continuing to refer to FIG. 3C , as shown in the figure, after the silicon oxynitride protective layer 230 is formed, the substrate 10 can be etched to form the source and drain growth regions 120 . The etching here can be dry etching, wet etching, or a combination of the two.

As shown in FIG. 3D , the source and drain growth regions 120 formed in FIG. 3C are filled, so that the epitaxial portion 130 is grown in the source and drain growth regions 120 . In some embodiments, the above filling can be achieved by silicon germanium. In some embodiments, the substrate 10 and the dummy gate 20 may also be pre-cleaned before filling to remove the intrinsic oxide layer on the surfaces of the substrate 10 and the dummy gate 20 . In this way, the performance of the formed electronic device 1 can be ensured.

Embodiment 2

4A to 4D illustrate various steps of a method of manufacturing the electronic device 1 according to another exemplary embodiment of the present disclosure. The dummy gate 20 in FIG. 4A may be formed by the method described above in conjunction with FIGS. 2A to 2D . 4A and 2D , the top surface of the dummy gate 20 can be divided into a first area 210 and a second area 220 different from the first area 210 , where the first area 210 includes an area on the side 170 of the multi-layer structure 17 Surface silicon nitride 180 , while second region 220 includes silicon oxide layer 16 on dummy gate 20 .

As shown in FIG. 4A , the substrate 10 is etched to form a pre-source and drain growth region 110 . The etching here can be dry etching, wet etching, or a combination of the two.

Subsequently, as shown in FIG. 4B , the dummy gate 20 is nitrided. During this process, only the second region 220 of the dummy gate 20 is nitrided without the first region 210 of the dummy gate 20 , so that the silicon oxynitride protective layer 230 is only formed over the second region 220 . In some embodiments, in order to ensure the effective implementation of the process, the influence of oxygen atoms in the environment needs to be eliminated. To this end, a pre-cleaning operation may be performed before nitriding to remove the intrinsic oxide layer formed by oxygen atoms. According to the embodiment here, on the top of the silicon layer 14, since the second region 220 for protecting silicon oxide has been nitrided into the silicon oxynitride protective layer 230, during the pre-cleaning process, the silicon oxynitride protective layer 230 will not Etched away. In this way, the horn-shaped protrusion 25' in the existing solution can be effectively prevented from being formed on the shoulder of the upper end of the silicon layer 14.

Continuing to refer to FIG. 4C , as shown in the figure, after the silicon oxynitride protective layer 230 is formed, the pre-source and drain growth regions 110 on the substrate 10 are further etched to form the final source and drain growth regions 120 . The etching here can be dry etching, wet etching, or a combination of the two.

As shown in FIG. 4D , the source and drain growth regions 120 formed in FIG. 4C are filled, so that the epitaxial portion 130 is grown in the source and drain growth regions 120 . In some embodiments, the above filling can be achieved by silicon germanium. In some embodiments, the substrate 10 and the dummy gate 20 may also be pre-cleaned before filling to remove the intrinsic oxide layer on the surfaces of the substrate 10 and the dummy gate 20 . In this way, the performance of the formed electronic device 1 can be ensured.

Embodiment 3

5A to 5D illustrate various steps of a method of manufacturing the electronic device 1 according to yet another exemplary embodiment of the present disclosure. The dummy gate 20 in FIG. 5A may be formed by the method described above in conjunction with FIGS. 2A to 2D . 5A and 2D , the top surface of the dummy gate 20 can be divided into a first area 210 and a second area 220 different from the first area 210 , where the first area 210 includes an area on the side 170 of the multi-layer structure 17 Surface silicon nitride 180 , while second region 220 includes silicon oxide layer 16 on dummy gate 20 .

As shown in FIG. 5A , the substrate 10 is etched to form a source and drain growth region 120 in a final shape. The etching here can be dry etching, wet etching, or a combination of the two.

Subsequently, as shown in FIG. 5B , the dummy gate 20 is nitrided. During this process, only the second region 220 is nitrided without the first region 210 , so that the silicon oxynitride protective layer 230 is only formed over the second region 220 . As shown in Figure 5B, due to the presence of oxygen atoms in the environment, an intrinsic oxide layer 122 may be formed on the surface. Although the intrinsic oxide layer 122 is only shown on the surface of the source and drain growth regions 120 of the substrate 10 in FIG. 5B , it should be understood that the intrinsic oxide layer 122 can be located on any exposed surface of the substrate 10 and the dummy gate 20 s surface.

Continuing to refer to FIG. 5C , as shown in the figure, in some embodiments, in order to ensure the effective implementation of the process, the influence of oxygen atoms in the environment needs to be eliminated. To this end, the substrate 10 and the dummy gate 20 can be processed before nitriding. A pre-cleaning operation is performed to remove these intrinsic oxide layers 122 . .

Subsequently, as shown in FIG. 5D , the source and drain growth regions 120 formed in FIG. 5C are filled, thereby growing the epitaxial portion 130 located in the source and drain growth regions 120 . In some embodiments, the above filling can be achieved by silicon germanium.

According to the embodiment here, on the top of the silicon layer 14, since the second region 220 for protecting silicon oxide has been nitrided into the silicon oxynitride protective layer 230, during the pre-cleaning process, the silicon oxynitride protective layer 230 will not Etched away. In this way, the horn-shaped protrusion 25' in the existing solution can be effectively prevented from being formed on the shoulder of the upper end of the silicon layer 14.

Some possible implementations of the present disclosure are described above in conjunction with the accompanying drawings. However, it should be understood that these embodiments are only illustrative and not restrictive. Some optional methods according to embodiments of the present disclosure are introduced below.

In any of the embodiments described above, nitriding may be performed using a nitrogen plasma. In this way, good nitriding results can be ensured in a reliable way.

In any of the embodiments described above, nitriding can be performed within the following parameters: temperature from 200°C to 600°C and pressure from 0 to 20 Torr. It should be understood that the temperature and pressure values listed here are merely illustrative and not limiting. Based on other reaction environments and process requirements, different temperature and pressure ranges can be set, and specific values are not limited by the embodiments of the present disclosure.

In any of the embodiments described above, nitriding may occur in a certain ambient gas. In further embodiments, such ambient gas may include pure Ar ₂ , pure He, or pure N ₂ . In other embodiments, the ambient gas can also be any combination of the above gases.

In any of the embodiments described above, nitriding can be performed under continuous power. In other embodiments, nitriding can also be performed under pulsed power. Such power can be selected from the range of 0 to 5000kW. It should be noted that the power values listed here are only illustrative and not restrictive. In this way, nitriding can be performed in more scenarios, thereby expanding the applicable scope of the embodiments of the present disclosure.

In addition, although in the illustrated embodiment, the cross-section of the source and drain growth regions 120 is generally diamond-shaped, it should be understood that this is only schematic. In other embodiments, the cross-section of the source and drain growth regions 120 may also be other polygons, such as quadrilateral, pentagon, etc. In more embodiments, the cross-section of the source-drain growth region 120 may also have a certain arc, such as a U-shape, an ellipse, a circle, etc. The specific cross-sectional form of the source and drain growth regions 120 is not limited by the embodiments of the present disclosure.

In a second aspect of the present disclosure, an electronic device 1 is provided. The electronic device 1 is manufactured using the method according to the first aspect of the present disclosure. In some embodiments, the electronic device 1 may be used as a logic chip, for example. It should be understood that this is merely illustrative and not restrictive. Electronic devices according to embodiments of the present disclosure may implement other functions, such as with logic chip-based memory.

Through the implementation of the present disclosure, in the nitriding process of manufacturing electronic devices, only the area containing silicon oxide is nitrided, and the area without silicon oxide is not nitrided, so that a relatively hard layer can be formed on the local area. Silicon oxynitride. Through this selective nitridation, the silicon oxynitride can be left unaffected during pre-cleaning, thereby effectively preventing the formation of horn bulges in the prior art. This effect can bring significant results, such as reducing the differences between different device sizes during chemical mechanical polishing, thus ensuring the yield of electronic devices. In addition, selective nitriding can occur at various times, ensuring that the implementation of the present disclosure has flexible application scenarios. For example, the selective nitrogen can be implemented before forming the source and drain growth regions and epitaxial growth, or after forming the pre-source and drain growth regions and before forming the final source and drain growth regions, or after forming the final source and drain growth regions. change.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Claims

A method of manufacturing an electronic device, the electronic device including a substrate, the method comprising:

A dummy gate is formed on the substrate, wherein the dummy gate has a first region and a second region different from the first region on a top surface, and wherein the first region contains silicon nitride, The second region contains silicon oxide; and

The second region of the dummy gate is nitrided without nitriding the first region of the dummy gate, thereby forming a silicon oxynitride protective layer only over the second region.
The method of claim 1, further comprising:

After forming the silicon oxynitride protective layer, the substrate is etched to form source and drain growth regions.
The method according to any one of claims 1 to 2, further comprising:

After forming the dummy gate and before forming the silicon oxynitride protective layer, performing a first etching on the substrate to form a pre-source and drain growth region; and

After forming the silicon oxynitride protective layer, a second etching is performed on the pre-source and drain growth regions to form final source and drain growth regions.
The method according to any one of claims 1 to 3, further comprising:

After forming the dummy gate and before forming the silicon oxynitride protective layer, the substrate is etched to form source and drain growth regions.
The method according to any one of claims 2 to 4, further comprising:

The source and drain growth regions are filled to grow the epitaxial portion.
The method of claim 5, further comprising:

Before the nitriding or the filling, the substrate and the dummy gate are pre-cleaned to remove the intrinsic oxide layer on the surface of the substrate and the dummy gate.
The method of any one of claims 1 to 6, wherein the nitriding is performed using nitrogen plasma.
The method according to any one of claims 1 to 7, wherein the nitriding is carried out in the following parameters: a temperature of 200°C to 600°C, a pressure of 0 to 20 Torr, and ambient gases of N 2 , Ar and One or more of He.
The method according to any one of claims 1 to 8, wherein said nitriding is carried out under continuous or pulsed power.
The method of any one of claims 1 to 9, wherein forming the dummy gate includes:

forming an active region and a shallow channel isolation region on the substrate;

A multi-layer structure is sequentially formed above the active area and the shallow trench isolation area, and the multi-layer structure includes a silicon oxide layer on top;

Etch the first portion of the active region and the multi-layer structure on the shallow trench isolation region, and retain the layer on a second portion of the active region that is different from the first portion. A multilayer structure to form surface silicon nitride on the shallow trench isolation region, the first portion, the silicon oxide layer, and sides of the multilayer structure; and

Surface silicon nitride formed over the shallow trench isolation region, the first portion, and the silicon oxide layer is removed to form the dummy gate.
10. The method of claim 10, wherein the first region includes silicon nitride on the side of the multilayer structure, and wherein the second region includes the silicon oxide layer.
The method according to claim 10 or 11, wherein the multi-layer structure further includes a gate oxide layer, a silicon layer and a silicon nitride layer in a stacked structure below the silicon oxide layer, and wherein the silicon nitride This layer serves as a barrier layer for the silicon layer during etching.
An electronic device manufactured using the method according to any one of claims 1 to 12.