WO2023189164A1 - 半導体装置及び電力変換装置 - Google Patents

半導体装置及び電力変換装置 Download PDF

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WO2023189164A1
WO2023189164A1 PCT/JP2023/007772 JP2023007772W WO2023189164A1 WO 2023189164 A1 WO2023189164 A1 WO 2023189164A1 JP 2023007772 W JP2023007772 W JP 2023007772W WO 2023189164 A1 WO2023189164 A1 WO 2023189164A1
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Prior art keywords
semiconductor device
electrode
insulating film
semiconductor substrate
sic semiconductor
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French (fr)
Japanese (ja)
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和成 中田
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2024511538A priority Critical patent/JP7785159B2/ja
Priority to US18/832,489 priority patent/US20250113533A1/en
Priority to CN202380029068.XA priority patent/CN118901141A/zh
Publication of WO2023189164A1 publication Critical patent/WO2023189164A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide

Definitions

  • the present disclosure relates to a semiconductor device and a power conversion device.
  • Silicon carbide has superior voltage resistance, low resistance, and heat resistance compared to silicon (Si).
  • Power semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) made of SiC have been proposed to increase voltage resistance, reduce loss, and use semiconductor devices in high-temperature environments. There is.
  • SiC semiconductor devices smaller and more efficient semiconductor devices are being developed by taking advantage of the high dielectric breakdown electric field of SiC.
  • an increase in the number of wires to ensure current capacity increases the number of locations where stress is applied during assembly, and stress increases due to a rise in temperature during operation due to an increase in current density during energization. .
  • electrodes such as gate electrodes of the semiconductor device are damaged, resulting in a problem that the reliability of the semiconductor device is impaired.
  • the present disclosure has been made in view of the above problems, and aims to provide a technique that can improve the reliability of a semiconductor device.
  • a semiconductor device includes a semiconductor substrate, an electrode at least partially protruding upward from a reference surface of the semiconductor substrate, and an insulating film covering the reference surface of the semiconductor substrate and the electrode,
  • the insulating film has a first upper surface that corresponds to the reference surface of the semiconductor substrate and the at least a portion of the electrode that protrudes from the reference surface, and a protrusion that protrudes from the first upper surface.
  • a distance between the reference surface of the semiconductor substrate and a connecting portion connecting the first upper surface of the insulating film and the surface of the protrusion is a distance between the reference surface of the semiconductor substrate and the first upper surface of the electrode. 2 and the upper surface.
  • the distance between the reference surface of the semiconductor substrate and the connection portion is greater than or equal to the distance between the reference surface of the semiconductor substrate and the second upper surface of the electrode. According to such a configuration, the reliability of the semiconductor device can be improved.
  • FIG. 1 is a top view showing the overall configuration of a SiC semiconductor device according to Embodiment 1.
  • FIG. 1 is a cross-sectional view showing the configuration of a SiC semiconductor device according to Embodiment 1.
  • FIG. 3 is a flowchart showing a manufacturing process of the SiC semiconductor device according to the first embodiment.
  • FIG. 3 is a cross-sectional view showing the manufacturing process of the SiC semiconductor device according to the first embodiment.
  • FIG. 3 is a cross-sectional view showing the manufacturing process of the SiC semiconductor device according to the first embodiment.
  • FIG. 3 is a cross-sectional view showing the manufacturing process of the SiC semiconductor device according to the first embodiment.
  • FIG. 3 is a cross-sectional view showing the manufacturing process of the SiC semiconductor device according to the first embodiment.
  • FIG. 3 is a cross-sectional view showing the manufacturing process of the SiC semiconductor device according to the first embodiment.
  • FIG. 3 is a cross-sectional view showing the manufacturing process of the SiC semiconductor device according to the first embodiment.
  • FIG. 3 is a cross-sectional view showing the manufacturing process of the SiC semiconductor device according to the first embodiment.
  • FIG. 3 is a cross-sectional view showing the manufacturing process of the SiC semiconductor device according to the first embodiment.
  • FIG. 3 is a cross-sectional view showing the manufacturing process of the SiC semiconductor device according to the first embodiment.
  • FIG. 3 is a cross-sectional view showing the manufacturing process of the SiC semiconductor device according to the first embodiment.
  • 1 is a cross-sectional view showing the configuration of a SiC semiconductor device according to Embodiment 1.
  • FIG. 1 is a cross-sectional view showing a SEM image of the configuration of a SiC semiconductor device according to Embodiment 1.
  • FIG. 2 is a cross-sectional view showing a mounting example of the SiC semiconductor device according to the first embodiment. It is a figure showing the result of a test.
  • FIG. 2 is a cross-sectional view showing the configuration of a SiC semiconductor device according to a second embodiment.
  • 7 is a flowchart showing a manufacturing process of a SiC semiconductor device according to a second embodiment.
  • FIG. 3 is a cross-sectional view showing a manufacturing process of a SiC semiconductor device according to a second embodiment.
  • FIG. 3 is a cross-sectional view showing a manufacturing process of a SiC semiconductor device according to a second embodiment.
  • FIG. 3 is a cross-sectional view showing a manufacturing process of a SiC semiconductor device according to a second embodiment.
  • FIG. 3 is a cross-sectional view showing a manufacturing process of a SiC semiconductor device according to a second embodiment.
  • FIG. 3 is a cross-sectional view showing a manufacturing process of a SiC semiconductor device according to a second embodiment.
  • FIG. 3 is a cross-sectional view showing a manufacturing process of a SiC semiconductor device according to a second embodiment.
  • FIG. 3 is a cross-sectional view showing a manufacturing process of a SiC semiconductor device according to a second embodiment.
  • FIG. 3 is a cross-sectional view showing a manufacturing process of a SiC semiconductor device according to a second embodiment.
  • FIG. 3 is a cross-sectional view showing a manufacturing process of a SiC semiconductor device according to a second embodiment.
  • FIG. 3 is a cross-sectional view showing a manufacturing process of a SiC semiconductor device according to a second embodiment.
  • FIG. 3 is a cross-sectional view showing a manufacturing process of a SiC semiconductor device according to a second embodiment.
  • FIG. 3 is a cross-sectional view showing a manufacturing process of a SiC semiconductor device according to a second embodiment.
  • FIG. 3 is a cross-sectional view showing a manufacturing process of a SiC semiconductor device according to a second embodiment.
  • FIG. 3 is a cross-sectional view showing a manufacturing process of a SiC semiconductor device according to a second embodiment.
  • FIG. 3 is a cross-sectional view showing a manufacturing process of a SiC semiconductor device according to a second embodiment.
  • FIG. 3 is a cross-sectional view showing a manufacturing process of a SiC semiconductor device according to a second embodiment.
  • FIG. 3 is a cross-sectional view showing a manufacturing process of a SiC semiconductor device according to a second embodiment.
  • FIG. 3 is a cross-sectional view showing a manufacturing process of a SiC semiconductor device according to a second embodiment.
  • FIG. 2 is a cross-sectional view showing the configuration of a SiC semiconductor device according to a second embodiment. It is a figure showing the result of a test.
  • FIG. 3 is a cross-sectional view showing the configuration of a SiC semiconductor device according to a third embodiment.
  • FIG. 3 is a cross-sectional view showing the configuration of a SiC semiconductor device according to a third embodiment.
  • FIG. 3 is a cross-sectional view showing the configuration of a SiC semiconductor device according to a third embodiment.
  • FIG. 3 is a block diagram showing the configuration of a power conversion system to which a power conversion device according to a fourth embodiment is applied.
  • the semiconductor device according to the first embodiment will be described as an SiC semiconductor device containing silicon carbide (SiC), which is a wide bandgap semiconductor.
  • the material of the semiconductor device according to the first embodiment may be ordinary silicon (Si) or a wide bandgap semiconductor other than silicon carbide (SiC).
  • Examples of wide bandgap semiconductors other than silicon carbide (SiC) include gallium nitride (GaN) and diamond.
  • the material of the semiconductor device is a wide bandgap semiconductor, it becomes possible to achieve high breakdown voltage, low loss, and use in a high-temperature environment.
  • SiC has a higher dielectric breakdown electric field than Si, so the breakdown voltage layer (for example, a drift layer) to achieve the same breakdown voltage can be made thinner, and the amount of impurity doping in the breakdown voltage layer can be increased. It is possible to reduce on-resistance, etc.
  • FIG. 1 is a top view showing the overall configuration of the SiC semiconductor device according to the first embodiment
  • FIG. 2 is a top view showing the configuration of the SiC semiconductor device according to the first embodiment taken along line AA' in FIG. FIG.
  • the SiC semiconductor device has the configuration shown in FIG. 2 surrounded by the insulating protective film provided in the outer peripheral insulating region 10 of FIG. Equipped with.
  • the configuration of FIG. 2 includes a SiC substrate 1 which is an n-type semiconductor substrate, an n-type drift layer 2, a p-type base region 3, an n-type source region 4, a gate insulating film 5, and an electrode. It includes a certain gate electrode 6, an interlayer insulating film 7 which is an insulating film, a source electrode 8, and a drain electrode 9.
  • the gate connection portion 11 in FIG. 1 is electrically connected to the gate electrode 6 in FIG. 2. Note that the above n-type and p-type may be replaced with p-type and n-type, respectively.
  • the SiC semiconductor device according to the first embodiment is a MOSFET with a planar gate structure
  • FIG. 2 shows the main cell structure of the SiC semiconductor device.
  • the cell structure shown in FIG. 1 is repeatedly provided in the planar direction of the SiC substrate 1.
  • the SiC semiconductor device of the present disclosure may be a MOSFET with a trench gate structure, an IGBT, an RC-IGBT (Reverse Conducting-IGBT), an SBD (Schottky Barrier Diode), or a PND (PN junction diode). It may be.
  • An example in which the SiC semiconductor device of the present disclosure is a MOSFET with a trench gate structure will be described in Embodiment 2.
  • FIG. 3 is a flowchart showing the manufacturing process of the SiC semiconductor device according to the first embodiment, and the SiC semiconductor device is manufactured in this order.
  • a drift layer 2 containing SiC is formed as an epitaxial film on the first main surface (hereinafter referred to as the surface) of the SiC substrate 1.
  • step S2 of forming the base region as shown in FIG. 5, after forming a mask (not shown) made of resist etc. on the n-type drift layer 2, p-type impurities are selectively added.
  • Base region 3 is selectively formed on top of drift layer 2 by ion implantation.
  • p-type impurities include boron (B) and aluminum (Al).
  • a source region 4 is selectively formed on top of the base region 3 by implantation.
  • n-type impurities include phosphorus (P) and nitrogen (N).
  • the SiC substrate 1 is heat-treated at a high temperature using a heat treatment apparatus (not shown). As a result, p-type and n-type ions implanted into base region 3 and source region 4 are electrically activated.
  • step S4 of forming a gate insulating film as shown in FIG. It is formed by a deposition method such as
  • a gate electrode 6 is formed on the gate insulating film 5.
  • the gate electrode 6 may be formed by depositing polycrystalline Si or poly-Si using chemical vapor deposition or the like, or if higher-speed operation of the SiC semiconductor device is desired, a tungsten film or a tungsten film may be formed. It may be formed by depositing a silicide ( WSix ) film.
  • the gate insulating film 5 and gate electrode 6 are patterned using photolithography and dry etching or wet etching.
  • a pair of base regions 3 and a pair of source regions 4 are located below both ends of the gate electrode 6, and a portion of the drift layer 2 located between the pair of base regions 3 is located below the center of the gate electrode 6.
  • the gate electrode 6 is patterned to do so.
  • the interlayer insulating film 7 is patterned using photolithography and dry etching or wet etching to expose a part of the source region 4.
  • the source electrode 8 is formed on the source region 4 and the interlayer insulating film 7.
  • the source electrode 8 is formed, for example, by appropriately forming a barrier metal made of titanium or a titanium compound of titanium nitride (TiN) on a film of aluminum, an aluminum alloy made of aluminum and silicon, or nickel.
  • the source electrode 8 is then patterned using photolithography and dry etching or wet etching.
  • an insulating protective film is formed in the outer peripheral insulating region 10 of FIG. 1.
  • the material of the insulating protective film is, for example, polyimide resin or silicone resin.
  • photolithography technology to form the insulating protective film, and etching technology may also be used in combination.
  • the method for forming the insulating protective film is not limited to this, and for example, screen printing technology or drawing coating technology may be used.
  • the second main surface (hereinafter referred to as the back surface) of the SiC substrate 1 is machined using a grinding wheel to thin the SiC substrate 1. Then, the SiC substrate 1 is thinned as shown in FIG.
  • a drain electrode 9 is formed on the back side of the SiC substrate 1.
  • the drain electrode 9 is formed by forming a nickel film with a thickness of, for example, about 600 nm using a sputtering method or the like as appropriate.
  • the drain electrode 9 may be formed of a laminated film of a nickel film and a protective film by forming a protective film on the surface of nickel from a metal with poor reactivity such as gold or silver.
  • FIG. 12 is a cross-sectional view showing the gate electrode 6 and surrounding components in the configuration of FIG. 2, and FIG. 13 is a cross-sectional view showing an image of the configuration of FIG. 12 taken with a scanning electron microscope (SEM). It is a diagram. In FIG. 12, the upper surface of SiC substrate 1 is shown as reference surface 1a.
  • the entire gate electrode 6 is disposed above the reference surface 1a of the SiC substrate 1, and the interlayer insulating film 7 covers the reference surface 1a of the SiC substrate 1 and the gate electrode 6.
  • the interlayer insulating film 7 has a first upper surface 7a and a protrusion 7b protruding from the first upper surface 7a, and the first upper surface 7a and the protrusion 7b are connected to the reference surface 1a of the SiC substrate 1, They respectively correspond to the gate electrodes 6 protruding from the reference surface 1a.
  • FIG. 12 shows a connecting portion 7c that connects the first upper surface 7a of the interlayer insulating film 7 and the surface of the protruding portion 7b, and shows the distance h1 between the reference surface 1a of the SiC substrate 1 and the connecting portion 7c. has been done. Further, FIG. 12 shows a distance h2 between the reference surface 1a of the SiC substrate 1 and the second upper surface 6a of the gate electrode 6.
  • the distance h1 is greater than or equal to the distance h2. In other words, the ratio of the distance h1 to the distance h2 (h1/h2) is 1 or more.
  • FIG. 14 is a cross-sectional view showing an example of mounting the SiC semiconductor device according to the first embodiment.
  • the SiC semiconductor device of FIG. 2 is shown as a SiC semiconductor device 12.
  • the back side of the SiC semiconductor device 12 is connected to a lead frame 14a via a solder 13
  • the front side of the SiC semiconductor device 12 is connected to a lead frame 14b via a wire 15.
  • the SiC semiconductor device 12 and its surrounding area are covered with a molding resin 16.
  • FIG. 15 is a diagram showing the results of the assembly test.
  • the horizontal axis indicates the ratio of the distance h1 to the distance h2 (h1/h2), and the vertical axis indicates the non-defective rate of SiC semiconductor devices determined to be non-defective in the assembly test.
  • the ratio (h1/h2) is 1 or more, the yield rate of SiC semiconductor devices after assembly can be increased.
  • the distance h1 is greater than or equal to the distance h2, and the ratio (h1/h2) is greater than or equal to 1, so that it is possible to increase the non-defective product rate of the SiC semiconductor device. This can improve reliability.
  • the electrode covered by the interlayer insulating film 7 is the gate electrode 6, but the electrode is not limited to this.
  • the electrode covered by the interlayer insulating film 7 may be a dummy electrode used as a dummy for the gate electrode 6. This also applies to the second embodiment described below.
  • the SiC semiconductor device according to the first embodiment is a semiconductor device with a planar gate structure, but the SiC semiconductor device according to the second embodiment is a semiconductor device with a trench gate structure.
  • the top view showing the overall configuration of the SiC semiconductor device according to the second embodiment is the same as the top view (FIG. 1) showing the overall configuration of the SiC semiconductor device according to the first embodiment.
  • FIG. 16 is a cross-sectional view showing the configuration of the SiC semiconductor device according to the second embodiment along line A-A' in FIG. 1.
  • the configuration of FIG. 16 includes a SiC substrate 1 which is an n-type semiconductor substrate, an n-type drift layer 2, a p-type base region 3, an n-type source region 4, a gate insulating film 5, and an electrode. It includes a certain gate electrode 6, an interlayer insulating film 7 which is an insulating film, a source electrode 8, a drain electrode 9, and a p-type bottom base region 17.
  • the gate connection portion 11 in FIG. 1 is electrically connected to the gate electrode 6 in FIG. 16.
  • the above n-type and p-type may be replaced with p-type and n-type, respectively.
  • the number of trench gate structures is not limited to this. In the overall configuration of an actual SiC semiconductor device, an arbitrary number of trench gate structures shown in FIG. 16 are repeatedly provided in the planar direction of the SiC substrate 1.
  • FIG. 17 is a flowchart showing the manufacturing process of the SiC semiconductor device according to the second embodiment, and the SiC semiconductor device is manufactured in this order.
  • a drift layer 2 containing SiC is formed as an epitaxial film on the surface of the SiC substrate 1.
  • step S12 of forming the base region as shown in FIG. 19, after forming a mask (not shown) made of resist or the like on the n-type drift layer 2, p-type impurities are selectively added.
  • Base region 3 is selectively formed on top of drift layer 2 by ion implantation.
  • the p-type impurity include boron (B) and aluminum (Al).
  • n-type impurities are selectively ionized.
  • a source region 4 is selectively formed on top of the base region 3 by implantation. Examples of n-type impurities include phosphorus (P) and nitrogen (N).
  • the SiC substrate 1 is heat-treated at a high temperature using a heat treatment apparatus (not shown). As a result, p-type and n-type ions implanted into base region 3 and source region 4 are electrically activated.
  • a mask (not shown) made of resist or the like is formed to open a part of the source region 4, and then dry etching using plasma or the like is performed as shown in FIG. A trench is formed.
  • an oxide film made of, for example, TEOS is formed on the surfaces of the base region 3 and source region 4 in FIG. Dry etching may be performed using the oxide film as a mask. In this case, deeper trenches can be formed.
  • p-type impurities such as boron (B) and aluminum (Al) are ion-implanted into the bottom of the trench.
  • a region 17 is formed. Note that if the electric field does not need to be relaxed, the bottom base region 17 may not be formed.
  • the drift layer 2 is oxidized using a thermal oxidation method in order to remove plasma damage from the drift layer 2 when forming the trench.
  • a thermal oxidation method in order to remove plasma damage, it is desirable that the amount of oxidation be large, but if the amount of oxidation is large, the impurity layer formed in the drift layer 2 will be reduced.
  • the thermal oxide film is 20 to 80 nm, more preferably 30 to 70 nm, plasma damage can be sufficiently removed from the drift layer 2 without substantially reducing the impurity layer. This was confirmed by measuring the leakage current between the electrode 6 and the source electrode 8.
  • the gate insulating film 5 is formed in the trench by a thermal oxidation method or a deposition method such as chemical vapor deposition.
  • the thickness of the gate insulating film 5 on the side surface of the trench is preferably greater than or equal to the thickness of the gate insulating film 5 on the bottom surface of the trench, and is preferably 10% or more of the thickness of the gate insulating film 5 on the bottom surface of the trench. It is more preferable that there be.
  • a gate electrode 6 is formed, a portion of which is provided within the trench.
  • the gate electrode 6 may be formed by depositing polycrystalline Si or poly-Si using chemical vapor deposition or the like, or if higher-speed operation of the SiC semiconductor device is desired, a tungsten film or a tungsten film may be formed. It may be formed by depositing a silicide ( WSix ) film.
  • the gate electrode 6 is patterned using photolithography and dry etching or wet etching. It is desirable to use isotropic etching for patterning the gate electrode 6. For example, if dry etching is used, etching with plasma containing SF 6 is used, or if wet etching is performed, etching is performed with a mixed acid containing hydrofluoric acid and nitric acid. Etching is preferred.
  • the gate electrode 6 is provided in a first electrode portion 6b protruding from the reference surface, which is the upper surface of the SiC substrate, and in a trench provided in the reference surface of the SiC substrate 1. and a second electrode portion 6c.
  • the width of the first electrode portion 6b is larger than the width of the second electrode portion 6c, and the gate electrode 6 has a T-shape as a whole. According to such a configuration, the contact area between the gate electrode 6, the drift layer 2, the base region 3, and the source region 4 can be increased.
  • an oxide layer (not shown) is formed on the surface of the gate electrode 6 by a thermal oxidation method.
  • the oxidation temperature at this time is preferably, for example, 850 to 1050°C, more preferably about 900 to 1000°C.
  • interlayer insulating film 7 is formed using, for example, a vapor phase epitaxy (CVD) method.
  • CVD vapor phase epitaxy
  • interlayer insulating film 7 is patterned using photolithography and dry etching or wet etching to expose parts of base region 3 and source region 4.
  • the source electrode 8 is formed on the base region 3, source region 4, and interlayer insulating film 7, as shown in FIG.
  • the source electrode 8 is formed, for example, by appropriately forming a barrier metal made of titanium or a titanium compound of titanium nitride (TiN) on a film of aluminum, an aluminum alloy made of aluminum and silicon, or nickel.
  • the source electrode 8 is then patterned using photolithography and dry etching or wet etching.
  • an insulating protective film is formed in the outer peripheral insulating region 10 of FIG. 1.
  • the material of the insulating protective film is, for example, polyimide resin or silicone resin.
  • photolithography technology to form the insulating protective film, and etching technology may also be used in combination.
  • the method for forming the insulating protective film is not limited to this, and for example, screen printing technology or drawing coating technology may be used.
  • the back surface of the SiC substrate 1 is machined using a grinding wheel to reduce the thickness of the SiC substrate 1, as shown in FIG. Dilute 1.
  • the drain electrode 9 is formed on the back side of the SiC substrate 1.
  • the SiC semiconductor device shown in FIG. 16 is completed.
  • the drain electrode 9 is formed by forming a nickel film with a thickness of, for example, about 600 nm using a sputtering method or the like as appropriate.
  • the drain electrode 9 may be formed of a laminated film of a nickel film and a protective film by forming a protective film on the surface of nickel from a metal with poor reactivity such as gold or silver.
  • the interlayer insulating film 7 is a TEOS film or an SOG (Spin-On-Glass) film into which impurities such as B (boron) and P (phosphorous) are introduced.
  • the interlayer insulating film 7 is a TEOS film
  • heat treatment is performed at 700 to 900°C after the formation of the TEOS film
  • the interlayer insulating film 7 is an SOG film
  • heat treatment is performed at 400 to 500°C after the formation of the SOG film. Perform heat treatment.
  • the corner portion marked with a broken line circle of the protruding portion 7b protruding from the first upper surface 7a of the interlayer insulating film 7 as shown in FIG. can be rounded more than the corners in FIG.
  • a source electrode forming step of step S18 a source electrode 8 is formed on the base region 3, source region 4, and interlayer insulating film 7, as shown in FIG.
  • a SiC semiconductor device as shown in FIG. 32 is completed through a process of thinning the SiC substrate in step S19 and a process of forming a drain electrode in step S20.
  • FIG. 33 is a cross-sectional view showing the gate electrode 6 and its surrounding components in the configuration of FIG. 32.
  • the upper surface of SiC substrate 1 is shown as reference surface 1a.
  • the first electrode portion 6b of the gate electrode 6 protrudes from the reference surface 1a of the SiC substrate 1, and the interlayer insulating film 7 covers the reference surface 1a of the SiC substrate 1 and the gate electrode 6.
  • the interlayer insulating film 7 has a first upper surface 7a and a protrusion 7b protruding from the first upper surface 7a, and the first upper surface 7a and the protrusion 7b are connected to the reference surface 1a of the SiC substrate 1, They respectively correspond to the gate electrodes 6 protruding from the reference surface 1a.
  • FIG. 33 shows a connecting portion 7c that connects the first upper surface 7a of the interlayer insulating film 7 and the surface of the protrusion 7b, and shows the distance h1 between the reference surface 1a of the SiC substrate 1 and the connecting portion 7c. has been done. Further, FIG. 33 shows the distance h2 between the reference surface 1a of the SiC substrate 1 and the second upper surface 6a of the first electrode portion 6b.
  • the distance h1 is greater than or equal to the distance h2
  • the ratio of the distance h1 to the distance h2 (h1/h2) is greater than or equal to 1.
  • the second embodiment similarly to the first embodiment, it is possible to increase the non-defective product rate of the SiC semiconductor device after assembly, and in turn, it is possible to increase the reliability of the SiC semiconductor device. This is the same for both the configuration in FIG. 16 and the configuration in FIG. 32.
  • FIG. 33 shows an angle ⁇ 1 between the reference surface 1a of the SiC substrate 1 and the second side surface 7e of the lower portion 7d below the first upper surface 7a of the interlayer insulating film 7.
  • Angle ⁇ 1 in the example of FIG. 33 is an angle between the reference surface 1a of the SiC substrate 1 and the second side surface 7e at a position half the thickness of the lower portion 7d.
  • FIG. 33 shows an angle ⁇ 2 between the reference surface 1a of the SiC substrate 1 and the first side surface 7f of the protrusion 7b of the interlayer insulating film 7.
  • the first side surface 7f of the protrusion 7b is, for example, a surface other than the upper surface of the protrusion 7b.
  • the angle ⁇ 2 in the example of FIG. 33 is the angle between the reference surface 1a of the SiC substrate 1 and the first side surface 7f at a position half the thickness of the protrusion 7b.
  • the angle ⁇ 1 is greater than or equal to the angle ⁇ 2
  • the ratio of the angle ⁇ 1 to the angle ⁇ 2 ( ⁇ 1/ ⁇ 2) is greater than or equal to 1.
  • FIG. 34 shows the yield rate of SiC semiconductor devices after conducting a 10,000-cycle switching test to evaluate accelerated deterioration in a configuration where the ratio of distance h1 to distance h2 (h1/h2) is 1. This is a graph. In this test, the rated current was doubled. The horizontal axis indicates the ratio of the angle ⁇ 1 to the angle ⁇ 2 ( ⁇ 1/ ⁇ 2), and the vertical axis indicates the non-defective rate of SiC semiconductor devices determined to be non-defective in the switching test. As shown in FIG. 34, it was confirmed that when the ratio ( ⁇ 1/ ⁇ 2) was 1 or more, the reliability of the SiC semiconductor device could be improved.
  • the ratio ( ⁇ 1/ ⁇ 2) is 1 or more is substantially the same as that the corners of the protrusion 7b are rounded. Therefore, when the ratio of the angle ⁇ 1 to the angle ⁇ 2 ( ⁇ 1/ ⁇ 2) is 1 or more, the upper surface of the source electrode 8 can be flattened, and the bonding strength between the wire 15 and the source electrode 8 after wiring is increased. can be increased. Note that the configuration in which the ratio ( ⁇ 1/ ⁇ 2) is 1 or more is applicable not only to the trench gate structure according to the second embodiment but also to the planar gate structure according to the first embodiment.
  • Embodiment 3 the same components as in Embodiment 1 or Embodiment 2 are given the same reference numerals, and detailed description thereof will be omitted.
  • the top view showing the overall configuration of the SiC semiconductor device according to the third embodiment is similar to the top view (FIG. 1) showing the overall configuration of the SiC semiconductor device according to the first embodiment or the second embodiment.
  • FIG. 35 is a cross-sectional view showing the configuration of the SiC semiconductor device according to the third embodiment along line A-A' in FIG.
  • the configuration of FIG. 35 includes a SiC substrate 1 which is an n-type semiconductor substrate, an n-type drift layer 2, a p-type base region 3, an n-type source region 4, a gate insulating film 5, and an electrode. It includes a certain gate electrode 6, an interlayer insulating film 7 which is an insulating film, a source electrode 8, and a drain electrode 9.
  • the gate connection portion 11 in FIG. 1 is electrically connected to the gate electrode 6 in FIG. 35. Note that the above n-type and p-type may be replaced with p-type and n-type, respectively.
  • FIG. 36 is an enlarged view showing the mutual positional relationship of the gate insulating film 5, gate electrode 6, and interlayer insulating film 7 of FIG. 35.
  • FIG. 37 is an enlarged view showing the mutual positional relationship between the end of the gate electrode 6 and the interlayer insulating film 7 in FIG. 36.
  • the outer edge of the protruding portion 7b of the interlayer insulating film 7 has a curved portion 7g in cross-sectional view.
  • a connecting portion 7i between the straight portion 7h and the curved portion 7g in a cross-sectional view of the upper surface of the protruding portion 7b is located directly above the end of the gate electrode 6 or directly above the end.
  • the outer edge of the protruding portion 7b has a radius of curvature R, and the distance between the center point of the arc having the radius of curvature R and the end of the gate electrode 6 in the left-right direction of the paper in FIG. 37 is d. Sometimes d is greater than or equal to 0.
  • the SiC semiconductor device according to the third embodiment is a MOSFET with a planar gate structure, it may be a MOSFET with a trench gate structure, an IGBT, or an RC-IGBT (Reverse Conducting-IGBT). It may be an SBD (Schottky Barrier Diode) or a PND (PN junction diode).
  • SBD Schottky Barrier Diode
  • PND PN junction diode
  • the manufacturing process of the SiC semiconductor device according to the third embodiment is similar to the manufacturing process shown in the flowchart of FIG. 3, and the SiC semiconductor device is manufactured in this order. From step S1 to step S5, the same manufacturing process as in the first embodiment is performed as shown in FIGS. 4 to 7.
  • a film made of TEOS (Tetra EthOxy Silane) or SOG (Spin-On-Glass) film is is formed as the interlayer insulating film 7.
  • the boron concentration contained in the interlayer insulating film 7 is set to 3 wt% or less.
  • the connecting portion 7i between the straight part 7h and the curved part 7g of the interlayer insulating film 7 can be It can be located directly above the edge of the gate electrode 6 on the outside.
  • the interlayer insulating film 7 is patterned using photolithography and dry etching or wet etching to expose a part of the source region 4.
  • step S7 to step S9 the same manufacturing process as in the first embodiment is performed as shown in FIGS. 10 to 11, and the semiconductor device shown in FIG. 35 is completed.
  • the connecting portion 7i between the straight portion 7h and the curved portion 7g in the cross-sectional view of the upper surface of the protruding portion 7b of the interlayer insulating film 7 is located directly above the end of the gate electrode 6, or at the end thereof. It is located directly above the outside.
  • Embodiment 4 is an example in which the SiC semiconductor device according to any one of Embodiments 1 to 3 described above is applied to a power conversion device.
  • the power conversion device according to the fourth embodiment is not limited to a specific power conversion device, a case where the power conversion device according to the fourth embodiment is applied to a three-phase inverter will be described below. .
  • FIG. 38 is a block diagram schematically showing the configuration of a power conversion system to which the power conversion device 200 according to the fourth embodiment is applied.
  • This power conversion system includes a power supply 100, a power conversion device 200, and a load 300.
  • the power supply 100 is a DC power supply and supplies DC power to the power conversion device 200.
  • the power source 100 can be configured with various power sources, for example, it may be configured with a DC system, a solar battery, a storage battery, or a rectifier circuit or an AC/DC converter connected to an AC system. good.
  • the power supply 100 may be configured by a DC/DC converter that converts DC power output from a DC system into predetermined power.
  • the power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300.
  • Power converter 200 converts DC power supplied from power supply 100 into AC power and supplies it to load 300.
  • Power conversion device 200 includes a main conversion circuit 201 and a control circuit 203.
  • the main conversion circuit 201 converts input DC power into AC power and outputs the AC power.
  • Control circuit 203 outputs a control signal for controlling main conversion circuit 201 to main conversion circuit 201 .
  • the load 300 is a three-phase electric motor driven by AC power supplied from the power conversion device 200.
  • the load 300 is not limited to a specific use, but is a motor installed in various electrical devices, and is used, for example, as a motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioner.
  • the main conversion circuit 201 includes a switching element and a free wheel diode (not shown). By switching the switching element, the main conversion circuit 201 converts the DC power supplied from the power supply 100 into AC power, and supplies it to the load 300.
  • the main conversion circuit 201 according to the fourth embodiment is a two-level three-phase full bridge circuit, and includes six switching elements and each switching element. The device can be configured with six freewheeling diodes connected in antiparallel to the element.
  • At least one of the switching element and the freewheeling diode of the main conversion circuit 201 is applied with the SiC semiconductor device 12 according to any one of the above-described embodiments 1 to 3 and variations thereof.
  • the six switching elements are connected in series every two switching elements to constitute upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit.
  • the output terminals of the upper and lower arms, that is, the three output terminals of the main conversion circuit 201, are connected to the load 300.
  • the main conversion circuit 201 includes a drive circuit (not shown) that drives each switching element.
  • the drive circuit generates a drive signal for driving the switching element of the main conversion circuit 201 and supplies it to the control electrode of the switching element of the main conversion circuit 201.
  • the drive circuit applies a drive signal that turns the switching element on and a drive signal that turns the switching element off to the control electrode of each switching element, in accordance with a control signal from a control circuit 203 that will be described later. Output.
  • the drive signal When keeping the switching element in the on state, the drive signal is a voltage signal (on signal) that is greater than or equal to the threshold voltage of the switching element, and when the switching element is kept in the off state, the drive signal is a voltage signal that is less than or equal to the threshold voltage of the switching element. signal (off signal).
  • the control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, the control circuit 203 calculates the time (on time) during which each switching element of the main conversion circuit 201 should be in the on state, based on the power to be supplied to the load 300. For example, the control circuit 203 can control the main conversion circuit 201 by pulse width modulation (PWM) control that modulates the on-time of the switching element according to the voltage to be output.
  • PWM pulse width modulation
  • the control circuit 203 controls the main control circuit so that at each point in time, an on signal is output to a switching element that should be in an on state, and an off signal is output to a switching element that should be in an off state.
  • a control command (control signal) is output to the drive circuit included in the conversion circuit 201.
  • the drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.
  • the method for manufacturing the power conversion device 200 includes the following steps.
  • SiC semiconductor device 12 is manufactured by the manufacturing method described in the above-described first to third embodiments or variations thereof.
  • a main conversion circuit 201 having this SiC semiconductor device 12 is formed.
  • a control circuit 203 is also formed. In this way, a power conversion device 200 is formed.
  • the main conversion circuit 201 is formed, for example, as shown in FIG. 14b.
  • the SiC semiconductor device 12 according to any one of the first to third embodiments is used as at least one of the semiconductor devices constituting the main conversion circuit 201.
  • This makes it possible to suppress unexpected adverse effects caused by stress during assembly of the SiC semiconductor device 12, and to suppress defects caused by stress from peripheral members during switching operations.
  • This increases the reliability of the main conversion circuit 201. Therefore, the reliability of power conversion device 200 can be improved.
  • the fourth embodiment describes an example in which the SiC semiconductor device 12 is applied to a two-level three-phase inverter
  • the fourth embodiment is not limited to this, and can be applied to various power conversion devices. can do.
  • the power conversion device is a two-level power conversion device, but it may be a multi-level power conversion device such as a three-level power conversion device.
  • the above power conversion device may be applied to a single-phase inverter.
  • the power conversion device is not limited to the case where the above-mentioned load is an electric motor. It can be used as any power supply device, and furthermore, it can be used as a power conditioner for a solar power generation system, a power storage system, or the like.

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0629487A (ja) * 1992-03-25 1994-02-04 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JP2010171057A (ja) * 2009-01-20 2010-08-05 Denso Corp 半導体装置およびその製造方法
WO2016114057A1 (ja) * 2015-01-16 2016-07-21 富士電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
WO2019171678A1 (ja) * 2018-03-07 2019-09-12 三菱電機株式会社 炭化珪素半導体装置、電力変換装置および炭化珪素半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0629487A (ja) * 1992-03-25 1994-02-04 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JP2010171057A (ja) * 2009-01-20 2010-08-05 Denso Corp 半導体装置およびその製造方法
WO2016114057A1 (ja) * 2015-01-16 2016-07-21 富士電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
WO2019171678A1 (ja) * 2018-03-07 2019-09-12 三菱電機株式会社 炭化珪素半導体装置、電力変換装置および炭化珪素半導体装置の製造方法

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