WO2023188391A1 - 量子デバイス及び量子デバイスの製造方法 - Google Patents

量子デバイス及び量子デバイスの製造方法 Download PDF

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WO2023188391A1
WO2023188391A1 PCT/JP2022/016879 JP2022016879W WO2023188391A1 WO 2023188391 A1 WO2023188391 A1 WO 2023188391A1 JP 2022016879 W JP2022016879 W JP 2022016879W WO 2023188391 A1 WO2023188391 A1 WO 2023188391A1
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substrate
quantum bit
quantum
substrates
base material
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French (fr)
Japanese (ja)
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岳明 島内
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Fujitsu Ltd
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Fujitsu Ltd
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Priority to EP22935529.2A priority Critical patent/EP4503904A4/en
Priority to JP2024511130A priority patent/JP7819759B2/ja
Priority to PCT/JP2022/016879 priority patent/WO2023188391A1/ja
Publication of WO2023188391A1 publication Critical patent/WO2023188391A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N69/00—Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/40—Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Definitions

  • the present disclosure relates to a quantum device and a method for manufacturing a quantum device.
  • An object of the present disclosure is to provide a quantum device and a method for manufacturing a quantum device that can stabilize the capacitance between qubits.
  • the first substrate includes a first substrate and a plurality of second substrates placed on the first substrate, and the first substrate includes a first substrate having a first surface. a plurality of first pads provided on the first surface, and wiring connecting two first pads of the plurality of first pads, each of the plurality of second substrates includes a second base material having a second surface facing the first surface, a second pad provided on the second surface facing the first pad, and a quantum substrate connected to the second pad. a quantum bit included in one second substrate of the plurality of second substrates, and a quantum bit included in another second substrate of the plurality of second substrates. are capacitively coupled to each other via the wiring, and has an alignment mechanism that restrains each of the plurality of second substrates within a predetermined region within a plane parallel to the first surface of the first substrate. provided.
  • the capacitance between quantum bits can be stabilized.
  • FIG. 1 is a top view showing a quantum device according to a first embodiment.
  • FIG. 2 is a cross-sectional view showing the quantum device according to the first embodiment.
  • FIG. 3 is a bottom view showing the quantum bit substrate included in the quantum device according to the first embodiment.
  • FIG. 4 is a schematic diagram showing the arrangement relationship between four quantum bit substrates in the quantum device according to the first embodiment.
  • FIG. 5 is a cross-sectional view showing the coupling relationship between two quantum bit substrates in the quantum device according to the first embodiment.
  • FIG. 6 is a schematic diagram showing the coupling relationship between two quantum bit substrates in the quantum device according to the first embodiment.
  • FIG. 7 is a partial equivalent circuit diagram of the quantum device according to the first embodiment.
  • FIG. 8 is a cross-sectional view (part 1) showing a method for manufacturing a quantum bit substrate.
  • FIG. 9 is a cross-sectional view (Part 2) showing a method for manufacturing a quantum bit substrate.
  • FIG. 10 is a cross-sectional view (part 3) showing a method for manufacturing a quantum bit substrate.
  • FIG. 11 is a cross-sectional view (Part 4) showing a method for manufacturing a quantum bit substrate.
  • FIG. 12 is a cross-sectional view (Part 5) showing a method for manufacturing a quantum bit substrate.
  • FIG. 13 is a cross-sectional view (part 6) showing a method for manufacturing a quantum bit substrate.
  • FIG. 14 is a cross-sectional view (No. 7) showing a method for manufacturing a quantum bit substrate.
  • FIG. 15 is a cross-sectional view (Part 8) showing a method for manufacturing a quantum bit substrate.
  • FIG. 16 is a cross-sectional view (Part 9) showing a method for manufacturing a quantum bit substrate.
  • FIG. 17 is a cross-sectional view (No. 10) showing a method for manufacturing a quantum bit substrate.
  • FIG. 18 is a cross-sectional view (No. 11) showing a method for manufacturing a quantum bit substrate.
  • FIG. 19 is a cross-sectional view (No. 12) showing a method for manufacturing a quantum bit substrate.
  • FIG. 20 is a cross-sectional view (No. 13) showing a method for manufacturing a quantum bit substrate.
  • FIG. 21 is a cross-sectional view (No. 14) showing a method for manufacturing a quantum bit substrate.
  • FIG. 22 is a cross-sectional view (No. 15) showing a method for manufacturing a quantum bit substrate.
  • FIG. 23 is a cross-sectional view (No. 16) showing a method for manufacturing a quantum bit substrate.
  • FIG. 24 is a cross-sectional view (No. 17) showing a method for manufacturing a quantum bit substrate.
  • FIG. 25 is a cross-sectional view (No. 18) showing a method for manufacturing a quantum bit substrate.
  • FIG. 26 is a cross-sectional view (No. 19) showing a method for manufacturing a quantum bit substrate.
  • FIG. 27 is a cross-sectional view (No. 20) showing a method for manufacturing a quantum bit substrate.
  • FIG. 28 is a cross-sectional view (No.
  • FIG. 29 is a cross-sectional view (part 1) showing a method for manufacturing a carrier substrate.
  • FIG. 30 is a cross-sectional view (Part 2) showing the method for manufacturing the carrier substrate.
  • FIG. 31 is a cross-sectional view (part 3) showing the method for manufacturing the carrier substrate.
  • FIG. 32 is a cross-sectional view (No. 4) showing the method for manufacturing the carrier substrate.
  • FIG. 33 is a cross-sectional view (No. 5) showing the method for manufacturing the carrier substrate.
  • FIG. 34 is a cross-sectional view (part 6) showing the method for manufacturing the carrier substrate.
  • FIG. 35 is a cross-sectional view (No. 7) showing the method for manufacturing the carrier substrate.
  • FIG. 36 is a cross-sectional view (No. 8) showing the method for manufacturing the carrier substrate.
  • FIG. 37 is a cross-sectional view (Part 9) showing the method for manufacturing the carrier substrate.
  • FIG. 38 is a cross-sectional view (No. 10) showing the method for manufacturing the carrier substrate.
  • FIG. 39 is a schematic diagram showing another example of the arrangement of the first spacers.
  • FIG. 40 is a cross-sectional view showing the coupling relationship between two quantum bit substrates in the quantum device according to the second embodiment.
  • FIG. 1 is a top view showing a quantum device according to a first embodiment.
  • FIG. 2 is a cross-sectional view showing the quantum device according to the first embodiment.
  • FIG. 3 is a bottom view showing the quantum bit substrate included in the quantum device according to the first embodiment.
  • FIG. 4 is a schematic diagram showing the arrangement relationship between four quantum bit substrates in the quantum device according to the first embodiment.
  • FIG. 5 is a cross-sectional view showing the coupling relationship between two quantum bit substrates in the quantum device according to the first embodiment.
  • FIG. 6 is a schematic diagram showing the coupling relationship between two quantum bit substrates in the quantum device according to the first embodiment.
  • FIG. 7 is a partial equivalent circuit diagram of the quantum device according to the first embodiment.
  • FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG.
  • FIG. 5 corresponds to a cross-sectional view taken along line VV in FIG. 4.
  • the quantum device 1 includes a carrier substrate 10, a quantum bit substrate 20A, a quantum bit substrate 20B, a quantum bit substrate 20C, and a quantum bit substrate 20D.
  • the carrier substrate 10 is an example of a first substrate
  • the quantum bit substrates 20A to 20D are examples of second substrates.
  • the number of quantum bit substrates is not limited as long as it is two or more.
  • the carrier substrate 10 includes a base material 11 and a convex portion 13 provided on the upper surface of the base material 11.
  • the base material 11 and the convex portion 13 are made of silicon, for example. Although details will be described later, the base material 11 and the convex portions 13 are formed by forming four cavities 12 in a silicon substrate.
  • the convex portions 13 are provided at a plurality of locations on the upper surface of the base material 11, and the convex portions 13 provided at the multiple locations together constitute a frame.
  • the height of the convex portion 13 is, for example, about 2 ⁇ m to 4 ⁇ m.
  • the upper surface of the base material 11 is an example of the first surface.
  • the convex portion 13 is part of the alignment mechanism.
  • the quantum bit substrates 20A to 20D have the same configuration. In the following description of the quantum bit substrates 20A to 20D, only the quantum bit substrate 20A will be described as a representative.
  • the quantum bit substrate 20A includes a base material 21 and a plurality of first spacers 22 provided on the lower surface of the base material 21. As shown in FIG. 3, some of the plurality of first spacers 22 are provided in a rectangular frame shape, and a part of the outer surface of the first spacer 22 contacts a part of the inner surface of the convex part 13. (See Figure 5). As shown in FIG. 3, some of the plurality of first spacers 22 are provided, for example, in a cross shape inside the first spacer 22 provided in the shape of a rectangular frame. The lower surface of the first spacer 22 is in contact with the upper surface of the base material 11 of the carrier substrate 10 .
  • the first spacer 22 is, for example, an Al layer.
  • the height of the first spacer 22 is, for example, 4 ⁇ m to 6 ⁇ m, which is greater than the height of the convex portion 13.
  • the lower surface of the base material 21 is an example of the second surface.
  • the first spacer 22 is part of the alignment mechanism.
  • the quantum bit substrate 20A includes a quantum bit (Qubit) 23, a resonator 24, a filter 25, a pad 33, a control port 61, a readout port 62, and a ground port, as shown in FIGS. 63.
  • Quantbit quantum bit
  • the quantum bit 23 is an element that forms a coherent two-level system using superconductivity, and includes a transmon quantum bit circuit in which a superconducting Josephson element 231 and a capacitor 232 are connected in parallel.
  • the superconducting Josephson element 231 consists of a pair of superconductors that exhibit superconductivity at a temperature below a predetermined critical temperature, and an extremely thin insulator with a thickness of several nanometers sandwiched between the pair of superconductors. It is composed of:
  • the superconductor may be, for example, aluminum, and the insulator may be, for example, aluminum oxide.
  • a plurality of quantum bits 23 are connected to other adjacent quantum bits 23 via inter-bit wiring 27.
  • a capacitor 28 is provided on the path of the inter-bit wiring 27.
  • each of the quantum bits 23 creates a quantum entangled state with other adjacent quantum bits 23 and performs quantum operations.
  • the spacing between the quantum bits 23 is, for example, about 2 mm.
  • a superconducting inductor 236 is connected between the quantum bit 23 and ground.
  • FIG. 7 shows only the surrounding configuration of one quantum bit 23.
  • the resonator 24 reads out a bit signal indicating the state of the quantum bit 23 by interacting with the quantum bit 23.
  • Resonator 24 is connected to quantum bit 23 via capacitor 233.
  • the resonator 24 includes a resonant circuit in which a superconducting inductor 241 and a capacitor 242 are connected in parallel.
  • the filter 25 is connected to the resonator 24 via a capacitor 243.
  • the filter 25 includes a circuit in which a superconducting inductor 251 and a capacitor 252 are connected in parallel.
  • the pad 33 is connected to either of the quantum bits 23 and is used for coupling with the quantum bit 23 provided on the quantum bit substrate 20B or 20C.
  • the pad 33 has a square planar shape with a side length of about 200 ⁇ m, for example.
  • Pad 33 is an example of a second pad.
  • the distance between the pad 33 and the first spacer 22 is, for example, about 100 ⁇ m to 200 ⁇ m. This is to suppress coupling between the pad 33 and the first spacer 22.
  • each filter 25 For example, four sets of resonators 24 and quantum bits 23 are connected to each filter 25.
  • the quantum bit 23, the resonator 24, the filter 25, and the pad 33 are provided on the lower surface of the base material 21.
  • the control port 61, the read port 62, and the ground port 63 are access ports for accessing the quantum operation circuit including the quantum bit 23, the resonator 24, and the filter 25 from the outside.
  • the control port 61, readout port 62, and ground port 63 are provided on the upper surface of the base material 21.
  • the control port 61 is connected to the quantum bit 23 via a capacitor 234. Control port 61 is used to control quantum bit 23 from the outside.
  • a superconducting inductor 235 is connected between the wiring between the control port 61 and the capacitor 234 and the ground.
  • the readout port 62 is connected to the filter 25 via a through silicon via (TSV) 72 provided on the base material 21 and a capacitor 253.
  • TSV through silicon via
  • the read port 62 is used to take out the bit signal read by the resonator 24 to the outside.
  • the ground port 63 is connected to the quantum bit 23, the resonator 24, and the filter 25 via the TSV 73.
  • the ground port 63 is used to apply a ground potential to the quantum bit 23, resonator 24, and filter 25 from the outside.
  • through holes 21A and 21B are formed in the base material 21.
  • a pad 33, a quantum bit 23, a superconductor layer 32, and a superconductor layer 38 are provided on the lower surface of the base material 21. Pad 33 and quantum bit 23 are connected to each other.
  • the superconductor layer 32 constitutes a resonator 24 and a filter 25, and is connected to the quantum bit 23.
  • Superconductor layer 32 is adjacent to through hole 21A.
  • Superconductor layer 38 is adjacent to through hole 21B.
  • the pad 33, the superconductor layer 32, and the superconductor layer 38 are, for example, TiN layers.
  • the thickness of the pad 33, the superconductor layer 32, and the superconductor layer 38 is, for example, about 100 nm.
  • a superconductor layer 34, a superconductor layer 35, and a superconductor layer 36 are provided on the upper surface of the base material 21.
  • the superconductor layer 34 overlaps the quantum bit 23 in plan view.
  • the superconductor layer 35 is adjacent to the through hole 21A and is included in the TSV 72.
  • the superconductor layer 36 is adjacent to the through hole 21B and is included in the TSV 73.
  • the superconductor layer 34, the superconductor layer 35, and the superconductor layer 36 are, for example, TiN layers.
  • the thicknesses of the superconductor layer 34, the superconductor layer 35, and the superconductor layer 36 are, for example, about 100 nm.
  • a superconductor layer 41 is provided on the superconductor layer 34, a superconductor layer 42 is provided inside the through hole 21A, and a superconductor layer 43 is provided inside the through hole 21B.
  • Superconductor layer 42 contacts superconductor layers 32 and 35.
  • Superconductor layer 43 contacts superconductor layers 36 and 38.
  • the superconductor layer 42 constitutes the TSV 72, and the superconductor layer 43 constitutes the TSV 73.
  • the superconductor layers 41, 42, and 43 are, for example, Al layers.
  • the thickness of the superconductor layers 41, 42, and 43 is, for example, about 300 nm.
  • Superconductor layer 41 is included in control port 61
  • superconductor layer 42 is included in readout port 62
  • superconductor layer 43 is included in ground port 63 .
  • through holes 11A are formed in the base material 11 of the carrier substrate 10 so as to correspond to the pads 33.
  • the through hole 11A has a circular planar shape with a diameter of about 150 ⁇ m, for example.
  • a coupler pad 14 is provided on the upper surface of the base material 11 around the through hole 11A.
  • the outer edge of the coupler pad 14 has a circular planar shape with a diameter of about 180 ⁇ m, for example.
  • Coupler pad 14 is an example of a first pad.
  • a superconductor layer connected to the coupler pad 14 is provided inside the through hole 11A.
  • Wiring 15 is provided on the lower surface of the base material 11. The wiring 15 is connected to the superconductor layer inside the two through holes 11A.
  • two coupler pads 14 are connected to each other via wiring 15.
  • Two coupler pads 14 connected via wiring 15 correspond to different quantum bit substrates.
  • one coupler pad 14 corresponds to quantum bit substrate 20A
  • the other coupler pad 14 corresponds to quantum bit substrate 20B.
  • the coupler pad 14 faces the pad 33 with a gap between the coupler pad 14 and the pad 33.
  • Pad 33 and coupler pad 14 can function as two electrodes included in one capacitor.
  • the pad 33 has a rectangular shape, and the coupler pad 14 has an annular shape.
  • the coupler pad 14 may be circular.
  • the outer edge of the coupler pad 14 is inside the outer edge of the pad 33.
  • a control probe 51, a readout probe 52, and a ground probe 53 are pressed against the upper surface of the quantum bit substrate 20A.
  • the control probe 51 is pressed against the control port 61
  • the read probe 52 is pressed against the read port 62
  • the ground probe 53 is pressed against the ground port 63.
  • FIGS. 29 to 38 are cross-sectional views showing a method for manufacturing the carrier substrate 10.
  • the quantum device 1 will be described upside down from the quantum device 1.
  • a base material 21 is prepared.
  • a silicon substrate can be used as the base material 21.
  • the thickness of the base material 21 is, for example, about 300 ⁇ m.
  • a superconductor layer for example a TiN layer 31X
  • the TiN layer 31X can be formed by, for example, a sputtering method, a plasma chemical vapor deposition (CVD) method, an ion plating method, or the like.
  • the thickness of the TiN layer 31X is, for example, about 100 nm.
  • a resist mask 111 is formed on the surfaces of the two TiN layers 31X using photolithography.
  • the resist mask 111 covers the portion of the TiN layer 31X where the pad 33, superconductor layer 32, superconductor layer 34, superconductor layer 35, superconductor layer 36, or superconductor layer 38 is to be formed.
  • the TiN layer 31X is etched using a resist mask 111. Then, as shown in FIG. 12, the resist mask 111 is removed. In this way, pad 33, superconductor layer 32, superconductor layer 34, superconductor layer 35, superconductor layer 36, and superconductor layer 38 are formed.
  • a resist mask 112 is formed on the upper surface of the base material 21 using photolithography technology.
  • the resist mask 112 exposes the portion where the quantum bit 23 is to be formed.
  • a film 23X constituting the quantum bit 23 is formed.
  • the film 23X can be formed, for example, by a vapor deposition method.
  • the resist mask 112 is removed together with the film 23X formed thereon. In other words, perform liftoff. As a result, a quantum bit 23 is formed.
  • a protective layer 39 is formed on the upper and lower surfaces of the base material 21.
  • a SiO 2 layer is formed.
  • the protective layer 39 can be formed, for example, by a CVD method.
  • a resist mask 113 is formed on the protective layer 39 on the upper surface of the base material 21 using photolithography technology. A resist mask 113 covers the quantum bit 23 from above the protective layer 39 .
  • the protective layer 39 is etched using the resist mask 113.
  • the resist mask 113 is removed.
  • resist masks 114 are formed on the upper and lower surfaces of the base material 21 using photolithography technology.
  • the resist mask 114 exposes a portion where the through hole 21A will be formed and a portion where the through hole 21B will be formed.
  • Deep reactive ion etching (Deep-RIE) is performed on the base material 21 using a resist mask 114.
  • Et-RIE deep reactive ion etching
  • through holes 21A and 21B are formed in the base material 21.
  • the resist mask 114 is removed.
  • resist masks 115 are formed on the upper and lower surfaces of the base material 21 using photolithography.
  • the resist mask 115 exposes the portion where the superconductor layer 41, 42 or 43 will be formed.
  • an Al layer 42X is formed as a superconductor layer.
  • the Al layer 42X can be formed by, for example, a vapor deposition method.
  • the thickness of the Al layer 42X is, for example, about 300 nm.
  • the resist mask 115 is removed together with the Al layer 42X formed thereon. In other words, perform liftoff.
  • superconductor layers 41, 42 and 43 are formed.
  • Superconductor layer 41 is included in control port 61
  • superconductor layer 42 is included in readout port 62
  • superconductor layer 43 is included in ground port 63 .
  • the superconductor layer 42 constitutes the TSV 72
  • the superconductor layer 43 constitutes the TSV 73.
  • a resist mask 116 is formed on the upper surface of the base material 21 using photolithography technology.
  • the resist mask 116 exposes the portion where the first spacer 22 will be formed.
  • an Al layer 22X is formed as a film constituting the first spacer 22.
  • the Al layer 22X can be formed, for example, by a vapor deposition method.
  • the thickness of the Al layer 22X is, for example, about 4 ⁇ m to 6 ⁇ m.
  • the resist mask 116 is removed together with the Al layer 22X formed thereon. In other words, perform liftoff. As a result, first spacers 22 are formed.
  • the quantum bit substrate 20A can be manufactured.
  • Qubit substrates 20B, 20C and 20D can also be manufactured in the same direction.
  • a base material 11 is prepared.
  • a silicon substrate can be used as the base material 11.
  • the thickness of the base material 11 is, for example, about 300 ⁇ m.
  • a resist mask 121 is formed on the upper surface of the base material 11 using photolithography technology.
  • the resist mask 121 covers the portion where the convex portion 13 is to be formed.
  • the cavity 12 is formed by etching the base material 11 using the resist mask 121.
  • the depth of the cavity 12 is, for example, about 2 ⁇ m to 4 ⁇ m.
  • a convex portion 13 having a height of about 2 ⁇ m to 4 ⁇ m is formed around the cavity 12.
  • the resist mask 121 is removed.
  • resist masks 122 are formed on the upper and lower surfaces of the base material 11 using photolithography technology.
  • the resist mask 122 exposes a portion where the through hole 11A is to be formed.
  • resist masks 123 are formed on the upper and lower surfaces of the base material 11 using photolithography.
  • the resist mask 123 exposes the coupler pad 14, the wiring 15, and a portion where a superconductor layer connecting these is to be formed.
  • an Al layer 15X is formed as a superconductor layer.
  • the Al layer 15X can be formed, for example, by a vapor deposition method.
  • the resist mask 123 is removed together with the Al layer 15X formed thereon. In other words, perform liftoff. As a result, coupler pad 14, wiring 15, and a superconductor layer connecting these are formed.
  • the carrier substrate 10 can be manufactured.
  • the upper surface of the carrier substrate 10 and the lower surface of the quantum bit substrate 20A are opposed to each other.
  • the first spacer 22 is positioned within the cavity 12. That is, the first spacer 22 is located within the region surrounded by the convex portion 13.
  • the quantum bit substrate 20A is placed on the carrier substrate 10 while a part of the outer surface of the first spacer 22 is brought into contact with a part of the inner surface of the convex portion 13.
  • the lower surface of the first spacer 22 comes into contact with the upper surface of the base material 11.
  • the control probe 51 is pressed against the control port 61
  • the read probe 52 is pressed against the read port 62
  • the ground probe 53 is pressed against the ground port 63.
  • the quantum bit substrate 20A and the carrier substrate 10 can be aligned.
  • the alignment of the quantum bit substrates 20B, 20C, and 20D and the carrier substrate 10 can also be performed in a similar manner.
  • the relative positional relationship in the thickness direction between the quantum bit substrate 20A and the carrier substrate 10 is maintained. In other words, the distance between pad 33 and coupler pad 14 is kept constant. Further, since a part of the outer surface of the first spacer 22 contacts a part of the inner surface of the convex part 13, the relative position of the quantum bit substrate 20A with respect to the carrier substrate 10 in a plane parallel to the upper surface of the base material 11 is position is restricted. That is, the convex portion 13 and the first spacer 22 restrain the quantum bit substrate 20A within a predetermined region within a plane parallel to the upper surface of the base material 11.
  • the area where the pad 33 and the coupler pad 14 overlap in plan view is kept constant. Therefore, fluctuations in capacitance between pad 33 and coupler pad 14 are suppressed. That is, the capacitance between pad 33 and coupler pad 14 is stabilized. Similarly, for the other quantum bit substrates 20B, 20C, and 20D, the capacitance between the pad 33 and the coupler pad 14 is stabilized.
  • two coupler pads 14 are connected via wiring 15 on the carrier substrate 10. Therefore, the quantum bit 23 included in the quantum bit substrate 20A and the quantum bit 23 included in the quantum bit substrate 20B are capacitively coupled to each other via the wiring 15. Similarly, the quantum bit 23 included in the quantum bit substrate 20B and the quantum bit 23 included in the quantum bit substrate 20C are capacitively coupled to each other via the wiring 15. The quantum bit 23 included in the quantum bit substrate 20C and the quantum bit 23 included in the quantum bit substrate 20D are capacitively coupled to each other via the wiring 15. The quantum bit 23 included in the quantum bit substrate 20D and the quantum bit 23 included in the quantum bit substrate 20A are capacitively coupled to each other via the wiring 15.
  • the first embodiment it is possible to stabilize the capacitance between quantum bits, and it is possible to increase the number of bits while obtaining stable capacitance.
  • the quantum bit substrate 20A, 20B, 20C, or 20D can be easily removed from the carrier substrate 10. Therefore, even if a malfunction or the like occurs in any of the quantum bit substrates 20A, 20B, 20C, or 20D, the quantum bit substrate can be easily replaced (repaired).
  • the ground layer of the quantum bit substrate 20A and the ground layer of the carrier substrate 10 can be electrically connected via the first spacer 22.
  • the quantum bit substrate 20A does not need to be completely restrained in a plane parallel to the upper surface of the base material 11 due to the contact between the convex portion 13 and the first spacer 22.
  • the distance between the outer edges of the pads 33 and the distance between the outer edges of the coupler pads 14 is larger than the amount by which the qubit substrate 20A can move. It is preferable that the difference is large. With such a configuration, even if the quantum bit substrate 20A moves within the plane, the area where the pad 33 and the coupler pad 14 overlap in plan view is kept constant, and stable capacitance can be obtained. .
  • a part of the first spacer 22 is located between the pad 33 and the outer edge of the base material 21 in plan view (see FIG. 3), but FIG. As shown in FIG. 2, the first spacer 22 may not be located between the pad 33 and the outer edge of the base material 21.
  • the material of the first spacer 22 is not limited to Al, but may be Cu, Au, or the like.
  • FIG. 40 is a cross-sectional view showing the coupling relationship between two quantum bit substrates in the quantum device according to the second embodiment.
  • the convex portion 13 is formed higher than the first spacer 22 in the first embodiment.
  • the carrier substrate 10 has second spacers 16 at a plurality of locations inside the cavity 12 . That is, the second spacer 16 is provided on the upper surface of the base material 11.
  • the height of the second spacer 16 is approximately the same as the height of the first spacer 22 in the first embodiment, and is, for example, 4 ⁇ m to 6 ⁇ m.
  • the second spacer 16 is continuous with the convex portion 13 .
  • the second spacer 16 is made of silicon, for example, and is formed integrally with the base material 11 and the convex portion 13. The second spacer 16 is part of the alignment mechanism.
  • the quantum bit substrate 20A does not have the first spacer 22, and a portion of the outer surface of the base material 21 of the quantum bit substrate 20A contacts a portion of the inner surface of the convex portion 13. .
  • the upper surface of the second spacer 16 is in contact with the lower surface of the base material 21 of the quantum bit substrate 20A.
  • the upper surface of the carrier substrate 10 and the lower surface of the quantum bit substrate 20A are opposed to each other.
  • the quantum bit substrate 20A is placed on the carrier substrate 10 while a part of the outer surface of the base material 21 is brought into contact with a part of the inner surface of the convex part 13.
  • the upper surface of the second spacer 16 comes into contact with the lower surface of the base material 21.
  • the control probe 51 is pressed against the control port 61
  • the read probe 52 is pressed against the read port 62
  • the ground probe 53 is pressed against the ground port 63.
  • the second spacer 16 is provided on the upper surface of the base material 11, the relative positional relationship in the thickness direction between the quantum bit substrate 20A and the carrier substrate 10 is maintained. In other words, the distance between pad 33 and coupler pad 14 is kept constant. Further, since a part of the outer surface of the base material 21 contacts a part of the inner surface of the convex part 13, the relative position of the quantum bit substrate 20A with respect to the carrier substrate 10 in a plane parallel to the upper surface of the base material 11 is The position is constrained. Therefore, the area where the pad 33 and the coupler pad 14 overlap in plan view is kept constant. Therefore, fluctuations in capacitance between pad 33 and coupler pad 14 are suppressed. That is, the capacitance between pad 33 and coupler pad 14 is stabilized. Similarly, for the other quantum bit substrates 20B, 20C, and 20D, the capacitance between the pad 33 and the coupler pad 14 is stabilized.
  • the second embodiment it is possible to stabilize the capacitance between quantum bits, and it is possible to increase the number of bits while obtaining stable capacitance.
  • the quantum bit substrate 20A, 20B, 20C, or 20D can be easily removed from the carrier substrate 10, and the quantum bit substrate 20A, 20B, 20C, or 20D can be easily replaced (repaired). be able to.
  • the first spacer 22 since the first spacer 22 is not required, contamination and damage caused by the formation of the first spacer 22 can be prevented, and better characteristics can be obtained.
  • the quantum bit substrate 20A does not need to be completely restrained in a plane parallel to the upper surface of the base material 11 due to the contact between the convex portion 13 and the base material 21.
  • the distance between the outer edges of the pads 33 and the distance between the outer edges of the coupler pads 14 is larger than the amount by which the qubit substrate 20A can move. It is preferable that the difference is large. With such a configuration, even if the quantum bit substrate 20A moves within the plane, the area where the pad 33 and the coupler pad 14 overlap in plan view is kept constant, and stable capacitance can be obtained. .
  • Quantum device 10 Carrier substrate 11: Base material 12: Cavity 13: Convex portion 14: Coupler pad 15: Wiring 16: Second spacer 20A, 20B, 20C, 20D: Quantum bit substrate 21: Base material 21A, 21B: Through hole 22: First spacer 23: Qubit 24: Resonator 25: Filter 33: Pad 51: Control probe 52: Read probe 53: Ground probe 61: Control port 62: Read port 63: Ground port

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WO2025134388A1 (en) * 2023-12-22 2025-06-26 Riken Fabrication method for electric circuit device, and qubit device
EP4590108A1 (en) * 2024-01-18 2025-07-23 Fujitsu Limited Method for manufacturing qubit device
WO2025211421A1 (ja) * 2024-04-03 2025-10-09 京セラ株式会社 構造体、量子プロセッサ、量子コンピュータ、及び構造体の製造方法
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WO2025134388A1 (en) * 2023-12-22 2025-06-26 Riken Fabrication method for electric circuit device, and qubit device
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WO2025211421A1 (ja) * 2024-04-03 2025-10-09 京セラ株式会社 構造体、量子プロセッサ、量子コンピュータ、及び構造体の製造方法
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EP4712751A1 (en) 2024-09-10 2026-03-18 Fujitsu Limited Qubit device and method of manufacturing qubit device

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