Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P10/00—Bonding of wafers, substrates or parts of devices
  • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
  • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
  • C23C16/32—Carbides
  • C23C16/325—Silicon carbide
• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B28/00—Production of homogeneous polycrystalline material with defined structure
  • C30B28/12—Production of homogeneous polycrystalline material with defined structure directly from the gas state
  • C30B28/14—Production of homogeneous polycrystalline material with defined structure directly from the gas state by chemical reaction of reactive gases
• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
  • C30B29/10—Inorganic compounds or compositions
  • C30B29/36—Carbides
• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
  • C30B33/06—Joining of crystals
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
  • H10P90/19—Preparing inhomogeneous wafers
  • H10P90/1904—Preparing vertically inhomogeneous wafers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
  • H10D62/8303—Diamond
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
  • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
  • H10D62/8325—Silicon carbide

Definitions

• the present invention relates to the field of semiconductor materials for microelectronic components. It relates in particular to a composite structure comprising a thin monocrystalline layer placed on a support substrate made of polycrystalline silicon carbide.
• the thin monocrystalline layer is preferably made of silicon carbide, and the composite structure is aimed at power electronics applications.
• SiC is increasingly used for the manufacture of innovative power devices, to meet the needs of growing areas of electronics, such as electric vehicles.
• power devices and power integrated systems based on monocrystalline silicon carbide can handle much higher power density compared to their traditional silicon counterparts, and do so with smaller active area dimensions.
• a well-known thin layer transfer solution is the Smart Cut TM process, based on an implantation of light ions and on an assembly, by direct bonding, between a monocrystalline donor substrate and a support substrate, at an interface of collage.
• p-SiC substrates capable of forming support substrates, are currently available on the market.
• their mechanical, electrical, or even thermal characteristics are not necessarily optimal for obtaining, from a thin layer transfer process, a high quality composite structure, aimed at power applications.
• the thin monocrystalline layer can thus be doped, depending on the needs of the application: for example, to present N-type doping and a resistivity less than or equal to 30mohm.cm, 10mohm.cm, or even less than 1mohm.cm. But it is also required to ensure good electrical conductivity in the supporting substrate of the composite structure. For this, it is usual to strongly dope (in particular, type N) the poly-crystalline substrate, to achieve a resistivity lower than 30 mohm.cm. In addition, the assembly interface of the composite structure must be designed so as not (or very little) to increase the vertical electrical resistance.
• a thin layer transfer process based on direct bonding by molecular adhesion, is very dependent on the surface quality of the assembled substrates.
• a roughness less than or equal to 1nm RMS root mean square roughness
• a very low surface defectivity particles, holes, etc. or other reliefs likely to generate bonding defects
• the curvature corresponds to the arrow or “warp” according to Anglo-Saxon terminology, which is equivalent to the algebraic difference of the deviations of the substrate in relation to a reference plane.
• a reduced curvature is required on the one hand, so that these support substrates are compatible with direct assembly of good quality and high bonding energy, and on the other hand so that they are not likely to cause damage in the thin monocrystalline layer during or after the transfer process, due to significant mechanical constraints.
• Low curvature is also important to ensure the performance of manufacturing steps (e.g., photolithography) of components on/in the thin layer of the composite structure.
• the radius of curvature (proportional to the inverse of the "warp") of the p-SiC support substrates is typically aimed at greater than approximately 25m, i.e. a curvature ("warp") less than or equal to 100 micrometers (the micrometers will be noted “ microns” in the remainder of the text, for simplification) for a substrate of 150mm in diameter for example.
• the support substrate guarantees good thermal conductivity, to effectively evacuate heat, particularly generated by power components.
• Document US10934634 proposes a p-SiC substrate for which the rate of change in grain size between the two faces of the substrate is less than 0.43%, which gives it a radius of curvature greater than 142m.
• at least one face of said substrate has an arithmetic average roughness of less than 1 nm.
• the present invention proposes a composite structure comprising a thin layer of monocrystalline material, in particular c-SiC, placed on a p-SiC support substrate. It also relates to a method of manufacturing such a composite structure.
• the invention relates to a composite structure for the manufacture of microelectronic components comprising a thin monocrystalline layer, placed on a support substrate made of polycrystalline silicon carbide, said support substrate having a preferential crystalline orientation according to which:
• a texture coefficient C 422 is less than 30%, in particular less than 20%, and
• a texture coefficient C 220 is greater than 60% or the sum of the texture coefficients C 111 +C 222 +C 511 is greater than 70%, in particular greater than 80%.
• the present invention also relates to a method of manufacturing a composite structure comprising a thin monocrystalline layer placed on a support substrate made of polycrystalline silicon carbide, the manufacturing method comprising the following steps:
• a texture coefficient C 422 is less than 30%, in particular less than 20%, and
• a texture coefficient C 220 is greater than 60% or the sum of the texture coefficients C 111 +C 222 +C 511 is greater than 70%, in particular greater than 80%,
• Figures 3a, 3b, 3c present micrographs (SEM) of support substrates, produced under different conditions and presenting different preferential crystalline orientations or textures, used to manufacture composite structures conforming to the present invention
• Figures 5a, 5b, 5c, 5c', 5c'' and 5d show steps of the manufacturing process according to the invention
• the present invention relates to a composite structure 100 particularly suitable for the manufacture of microelectronic components comprising a thin monocrystalline layer 10, in particular of silicon carbide, diamond, silicon, II-VI or III-V semiconductor compounds (for example example AlN, GaN, etc.), or else in gallium oxide (Ga2O3), placed on a support substrate 20 in polycrystalline silicon carbide ( ).
• a thin monocrystalline layer 10 in particular of silicon carbide, diamond, silicon, II-VI or III-V semiconductor compounds (for example example AlN, GaN, etc.), or else in gallium oxide (Ga2O3), placed on a support substrate 20 in polycrystalline silicon carbide ( ).
• the composite structure 100 is preferably in the form of a circular wafer (“wafer” according to Anglo-Saxon terminology) with a diameter of 100mm, 150mm, 200mm, or even more. It could nevertheless be presented in any other form allowing its subsequent processing for the manufacture of components.
• the thickness of the composite structure 100 extends along the z axis in the figures.
• the thin layer 10 of the composite structure 100 has a thickness typically between a few tens of nm and a few hundred nm, for example, between 50nm and 800nm.
• epitaxy steps can be implemented on said thin layer 10, so as to thicken it (homoepitaxy) or to grow other materials (heteroepitaxy), for the needs of electronic components to be used. make.
• the thin layer 10 has an electrical resistivity adapted to the application and the targeted components.
• its resistivity is usually less than 30mOhm.cm, 10mOhm.cm, or even 1mOhm.cm, with N type doping (nitrogen doping).
• N type doping nitrogen doping
• its resistivity could be greater than 100Ohm.cm, or even 10kOhm.cm, without specific doping or with an addition, for example of vanadium.
• the lateral dimensions in the main plane (x,y) of the support substrate 20 are the same as those of the composite structure 100.
• the thin layer 10 may have a slightly smaller lateral dimension, due to the transfer process: in fact, a peripheral crown of the support substrate 20 is usually devoid of thin layer 10 because the fall of edge or chamfer of the substrate 20 prevent the assembly and effective transfer of said layer 10.
• the support substrate 20 has a thickness typically between several hundred microns and approximately 50 microns, for example between 800 microns and 50 microns, in particular between 500 microns and 60 microns, or between 350 microns and 100 microns. .
• the support substrate 20 When good vertical electrical conductivity is required (power applications), the support substrate 20 has an electrical resistivity less than 30mOhm.cm, 15mOhm.cm, or even less than 10mOhm.cm.
• the type of doping of the support substrate 20 is usually chosen identical, i.e. typical doping with nitrogen.
• the nitrogen concentration (which can be measured by secondary ion mass spectroscopy) is generally greater than 5E19 atoms/cm 3 , preferably greater than or equal to 1E20 atoms/cm 3 , or even greater or equal to 1.5E20 atoms/cm 3 .
• the production of the support substrate 20 in p-SiC takes place from very pure precursors (for example methyltrichlorosilane) and/or with the addition of impurities such as vanadium.
• the preferential crystal orientation is characterized here with particular proportions of different texture coefficients.
• a texture coefficient can be expressed as a percentage and quantifies the average preferential orientation of the crystallites of the support substrate 20 relative to the normal to the surface of said substrate 20.
• the texture coefficients can be measured using the method described by G. Harris (“X. Quantitative measurement of preferred orientation in rolled uranium bars”, Philosophical Magazine Series 7, 43:336, 113-123, 1952). In practice, they are measured from diffraction peaks collected by an X-ray diffractometer, by the ⁇ -2 ⁇ method over an angle range from 10° to 135° (2 ⁇ scale). On this range, the ten diffraction peaks appearing in the table (presented in ) and classified according to increasing Miller indices (hkl), can be taken into account in a SiC substrate of polytype 3C.
• a texture coefficient C hkl is calculated from the intensity of the peak I hkl , proportional to the area under the peak of the sample, and the theoretical intensity I 0 hkl of a powder which can be obtained at based on theoretical percentages published by the ICDD (International Center for Diffraction Data).
• a texture coefficient C hkl is expressed as follows:
• C hkl (I hkl / I 0 hkl )/ (1/N x ⁇ (I hkl / I 0 hkl )), with N the number of peaks taken into account.
• the preferential crystal orientation of the support substrate 20 is characterized by a texture coefficient C 422 less than 30% and a texture coefficient C 220 greater than 60%.
• the preferential crystalline orientation of the support substrate 20 is characterized by a texture coefficient C 422 less than 30% and the fact that the sum of the texture coefficients C 111 +C 222 +C 511 is greater than 70% .
• the texture coefficient C 422 is less than 20%, less than 15%, or even less than 10%.
• the sum of the texture coefficients C 111 +C 222 +C 511 is greater than 80%.
• Figures 3a, 3b and 3c present three examples of textures of support substrates 20 for a composite structure 100 according to the invention.
• the images are obtained by scanning electron microscopy (SEM) by backscattered electrons (EBSD), in the transverse plane (y,z), that is to say in a cross section (in cross-section) of the support substrate 20.
• SEM scanning electron microscopy
• EBSD backscattered electrons
• a right of Figures 3a and 3b a texture triangle includes, for information purposes, certain facets identified by different white symbols; said symbols are also reported on certain textures of the SEM images, for illustration.
• the percentages of the main texture coefficients of interest are indicated to the right of the SEM images in three figures 3a, 3b and 3c.
• the radius of curvature of the support substrate 20 is greater than 25m, advantageously greater than or equal to 50m.
• a support substrate 20 of 150mm in diameter has a curvature (or “warp”) less than or equal to 100 microns, or even 50 microns
• a support substrate 20 of 200mm in diameter has a curvature (or “warp”) of ") less than or equal to 150 microns, or even 70 microns.
• the range of radius of curvature of the support substrate 20 makes the latter perfectly compatible with the specifications of a composite structure 100 provided with a thin monocrystalline layer 10, with the manufacturing process of such a structure 100 and with the subsequent development of microelectronic components on and/or in the thin layer 10. Note that the curvature of the composite structure 100 remains close to the curvature of the support substrate 20.
• the composite structure 100 comprises a continuous or discontinuous intermediate layer 30, disposed between the thin layer 10 and the support substrate 20 and composed of at least one metallic or semiconductor material ( ).
• the intermediate layer 30 may be formed on the side of the thin layer 10, on the side of the support substrate 20 or on both sides, prior to the assembly along a bonding interface 40.
• the intermediate layer 30 may for example be composed of silicon, silicon carbide, tungsten and/or titanium. Its thickness is typically between a few nm and a few hundred nm, preferably between 2nm and 50nm.
• the present invention also relates to a method of manufacturing the composite structure 100.
• the method comprises a first step a) of providing a support substrate 20 made of polycrystalline silicon carbide having a preferential crystalline orientation according to which:
• a texture coefficient C 422 is less than 30%, in particular less than 20%, 15%, or even less than 10%, and
• a texture coefficient C 220 is greater than 60% or the sum of the texture coefficients C 111 +C 222 +C 511 is greater than 70%, in particular greater than 80%.
• the support substrate 20 has nitrogen doping making it possible to achieve an electrical resistivity of less than 30mOhm.cm, 15mOhm.cm, or even less than 10mOhm.cm.
• the radius of curvature of the support substrate 20 is greater than 25m, advantageously greater than or equal to 50m.
• Step a) implements a chemical vapor deposition (CVD) technique.
• This technique involves a gas mixture comprising at least one silicon precursor gas (such as a silane or a chlorosilane) and/or at least one carbon precursor gas (such as an alkane or an alkene), and/or at least one precursor gas of silicon and carbon (such as methyltrichlorosilane, abbreviated MTCS), and, if necessary, at least one doping gas comprising nitrogen (for example NH 3 , N 2 H 4 , N 2 ).
• Said doping gas can also be a carbon and/or silicon precursor (for example an amine such as H 2 NCH 3 ).
• These gases can be diluted in a carrier gas, which can be a reducing gas such as hydrogen and/or an inert gas such as argon.
• This gas mixture is admitted into a reactor located at high temperature where the precursor gases are decomposed and react on the surface of a seed, preferably fine-grained and purified isostatic graphite, to form the 3C-SiC polytype whose properties of mechanical and thermal resistance, thermal expansion coefficient and purity are perfectly compatible with the specifications of the composite structure 100.
• the 3C-SiC polytype moreover, can be doped with nitrogen up to very high levels, typically 10 20 atoms/cm 3 , and thus present a resistivity less than 30mOhm.cm, without degradation of the quality of the substrate which would be detrimental to the quality of the composite structure and subsequently to the performance of the microelectronic components.
• it is a material capable of withstanding the high temperature processes that the support substrate 20 will have to undergo during the manufacture of the composite structure 100 and the components.
• the reactor temperature during CVD deposition of SiC must be between approximately 1000°C and approximately 1600°C, preferably between approximately 1100°C and approximately 1400°C. In this temperature range, deposition rates can vary over fairly wide ranges, from micron/h to more than 100 microns/h.
• the total pressure in the reactor does not exceed 350 mbar, or even 300 mbar.
• the graphite seeds coated with a thick layer of SiC deposit are machined, then oxidized in air typically at 900°C to eliminate any graphite residue. Note that the removal of graphite seeds could also be carried out by purely mechanical machining techniques or even essentially by burning/oxidation.
• a disk of raw p-SiC is recovered for each face of a seed.
• the raw p-SiC disk presents a curvature due to the relaxation of the stresses of the deposited layer. This curvature can be measured using a white light confocal sensor which scans a surface of the p-SiC disk.
• the raw p-SiC disk then undergoes thinning by coarse and then fine grinding, and surface preparations by polishing to arrive at the p-SiC support substrate 20 having the key characteristics stated previously, during the description of the composite structure 100.
• the rectification step aims in particular to eliminate sufficient thickness from the side of the face of the disc which was in contact with the graphite. This removes the initial growth zone of the crystals, which generates strong stresses.
• the curvature of the raw p-SiC disk remains within a reasonable range to allow the development of a support substrate 20 with low curvature, from a raw disk of economically viable thickness.
• the curvature (“warp”) of a raw p-SiC disk with a diameter of 150mm and a thickness of less than 900 microns is aimed at less than or equal to 250 microns. It is thus possible after grinding and polishing to obtain a support substrate 20 with a thickness typically less than 500 microns and a curvature (“warp”) less than 100 microns, or even less than 50 microns, or even less than 30 microns.
• Samples 2, 3 and 4 are representative of the support substrates 20 for a composite structure 100 according to the present invention; their textures are illustrated respectively in Figures 3c, 3a and 3b.
• Samples 1 and 5 do not make it possible to achieve the required specifications (resistivity, curvature) for the manufacture of a high quality composite structure 100 and therefore do not fall within the present invention.
• the textures of these samples are not favorable to low curvature and the size of the grains at surface 20a, larger and heterogeneous than for samples 2, 3 and 4, complicates the surface preparation and obtaining the surface finish required for direct assembly.
• the face 20a of the support substrate 20 ( ) intended to receive the thin layer 10 preferably has a roughness less than or equal to 1nm RMS (measured by atomic force microscopy on scans of 20 microns x 20 microns), still preferably less than or equal to 0.5nm RMS.
• the face of the support substrate 20 intended to form the rear face of the composite structure 100 may have a greater surface roughness, for example of the order of 10nm RMS.
• Step a) of the process may optionally include a heat treatment applied to the support substrate 20, at a temperature greater than or equal to 1500°C, typically between 1500°C and 2000°C, so as to stabilize its poly-crystalline structure. Indeed, these temperature ranges are likely to be applied later in the process for the manufacture of the composite structure 100.
• the manufacturing process according to the invention then comprises a step b) of supplying a donor substrate 1 in a monocrystalline material from which the thin layer 10 will be derived ( ).
• the single-crystal material can be silicon carbide of polytype 4H, 6H or 3C, diamond, silicon, II-IV or III-V semiconductor compounds (in particular GaN) , etc.
• the donor substrate 1 is preferably in the form of a wafer with a diameter of 100mm, 150mm, 200mm or even more (identical to or very close to that of the support substrate 20) and a thickness typically between 300 microns and 800 microns. It has a front face 1a and a rear face 1b.
• the surface roughness of the front face 1a is advantageously chosen less than 1nm RMS, or even less than 0.5nm RMS, measured by atomic force microscopy (AFM) on a 20 micron x 20 micron scan.
• the type of doping and the resistivity of the donor substrate 1 are defined according to the needs of the components which will be produced on and/or in the thin layer 10 of the composite structure 100.
• the method comprises a step c) of transferring a thin layer 10 from the donor substrate 1 onto the support substrate 20.
• a layer transfer mechanical thinning , chemical or mechano-chemical, separation at the level of a porous layer present in the donor substrate 1
• step c) of the process involves implantation of light species and assembly by direct bonding, according to the principle of the Smart Cut TM process.
• a first phase c1) corresponds to the introduction of light species into the donor substrate 1 to form a buried fragile plane 11 delimiting, with a front face 1a of the donor substrate 1, the thin layer 10 to be transferred ( ). Note that even if the thin layer 10 to be transferred is illustrated as a continuous layer, it could also consist of discontinuous blocks, for example prepared on the surface of the donor substrate 1.
• the light species are preferably hydrogen, helium or a co-implantation of these two species, and are implanted at a determined depth in the donor substrate 1, consistent with the thickness of the thin layer 10 targeted. These light species will form, around the determined depth, microcavities distributed in a thin layer parallel to the free surface 1a of the donor substrate 1, i.e. parallel to the plane (x,y) in the figures. We call this thin layer the fragile buried plane 11, for the sake of simplification.
• the implantation energy of the light species is chosen so as to reach the determined depth.
• hydrogen ions will be implanted at an energy between 10 keV and 250 keV, and at a dose between 5 E 16/cm 2 and 1 E 17/cm 2 , to delimit a thin layer 10 having a thickness of l order of 100nm to 1500nm.
• a protective layer may be deposited on the front face 1a of the donor substrate 1, prior to the ion implantation step. This protective layer can be composed of a material such as silicon oxide or silicon nitride for example. It is removed before the next phase.
• Transfer step c) then comprises a second phase c2) of assembling the donor substrate 1, on the side of its front face 1a, on the support substrate 20, on the side of its first face 20a, by bonding by molecular adhesion, along a bonding interface 40 ( ).
• an intermediate layer 30 can be formed on the front face 1a of the donor substrate 1, before or after the introduction of the light species of phase c1), and in any case, before the assembly phase.
• This intermediate layer 30 may be made of a semiconductor material, for example silicon or silicon carbide, or of a metallic material such as tungsten, titanium, etc.
• the thickness of the intermediate layer 30 is advantageously limited, typically between a few nanometers and a few tens of nanometers.
• the implantation energy (and potentially the dose) of the light species will be adjusted when crossing this additional layer.
• care will be taken to form this layer by applying a thermal budget lower than the bubbling thermal budget, said bubbling thermal budget corresponding to the appearance of blisters on the surface of the donor substrate 1 due to growth and excessive pressurization of the microcavities in the buried fragile plane 11.
• an intermediate layer 30 can also be deposited on the face to be assembled of the support substrate 20, prior to the assembly phase; it can be chosen of the same nature or of a different nature from the intermediate layer mentioned for the donor substrate 1.
• An intermediate layer 30 can optionally be deposited on one and the other of the two substrates 1,10 to be assembled.
• the objective of the intermediate layer(s) is essentially to promote the bonding energy (particularly in the temperature range below 1100°C), due to the formation of covalent bonds at higher low temperatures than in the case of two SiC surfaces assembled directly; another advantage of this (these) intermediate layer(s) can be to improve the vertical electrical conduction of the bonding interface 40.
• the intermediate layer(s) 30 is(are) intended to be buried in the glued assembly 50 after assembly ( Figures 5c', 5c''), and ultimately, in the composite structure 100. Even if the intermediate layer 30 is continuous during its formation on one and/or the other of the substrates 1,20, it can, during subsequent heat treatments, become segmented and present a discontinuous character . This is essentially the case when the initial thickness of said layer is very low, typically less than 10nm.
• phase c2) of assembly and as is well known in itself, direct bonding by molecular adhesion does not require an adhesive material, because bonds are established at the atomic scale between the assembled surfaces. .
• the assembly phase c2) may comprise, prior to bringing the faces 1a, 20a to be assembled into contact, conventional sequences of chemical cleaning (for example, RCA cleaning), surface activation (for example, by oxygen or nitrogen plasma) or other surface preparations (such as cleaning by brushing (“scrubbing”)), likely to promote the quality of the bonding interface 40 (low defectivity, high adhesion energy).
• chemical cleaning for example, RCA cleaning
• surface activation for example, by oxygen or nitrogen plasma
• other surface preparations such as cleaning by brushing (“scrubbing”)
• a third phase c3) comprises the separation along the buried fragile plane 11, which leads to the transfer of the thin layer 10 onto the support substrate 20 ( ).
• the separation along the buried fragile plane 11 is usually carried out by the application of a heat treatment at a temperature between 800°C and 1200°C.
• a heat treatment induces the development of cavities and microcracks in the buried fragile plane 11, and their putting under pressure by the light species present in gaseous form, until the propagation of a fracture along said fragile plane 11.
• a mechanical stress can be applied to the glued assembly and in particular at the level of the buried fragile plane 11, so as to propagate or help to mechanically propagate the fracture leading to separation.
• the composite structure 100 comprising the support substrate 20 and the transferred thin layer 10
• the remainder 1' of the donor substrate we obtain on the one hand the composite structure 100 comprising the support substrate 20 and the transferred thin layer 10, and on the other hand, the remainder 1' of the donor substrate.
• the level and type of doping of the thin layer 10 are defined by the choice of the properties of the donor substrate 1 or can be adjusted subsequently via known techniques for doping semiconductor layers.
• the free surface 10a of the thin layer 10 is usually rough after separation: for example, it has a roughness of between 5nm and 100nm RMS.
• Cleaning and/or smoothing phases can be applied to restore a good surface condition (typically, a roughness less than a few angstroms RMS).
• these phases may include a mechanical-chemical smoothing treatment of the free surface of the thin layer 20.
• a removal of between 50nm and 300nm makes it possible to effectively restore the surface state of said layer 10.
• They may also include at minus a heat treatment at a temperature between 1200°C and 1800°C. Such a heat treatment is applied to evacuate the residual light species from the thin layer 10 and to promote the rearrangement of the crystal lattice of the thin layer 10.
• the heat treatment can also include or correspond to an epitaxy on the thin layer 10, in order to increase the thickness of the latter (for example, homoepitaxy of c-SiC on a thin layer 10 in c-SiC, heteroepitaxy of GaN on a thin layer 10 in c -SiC, or other).
• transfer step c) may include a step of reconditioning the remainder 1' of the donor substrate with a view to reuse as donor substrate 1 for a new composite structure 100.
• Mechanical and/or chemical treatments similar to those applied to the composite structure 100, can be implemented at the front face 1'a of the remaining substrate 1'.
• the composite structure 100 obtained is extremely robust to heat treatments at very high temperatures which may be applied to improve the quality of the thin layer 10 or to manufacture components on and/or in said layer 10.
• the support substrate 20 in the structure composite 100 is stable and does not see its curvature increase in a prohibitive manner during the high temperature heat treatments applied to the composite structure 100 for its manufacture and subsequently.
• the composite structure 100 according to the invention is particularly suitable for the development of one (or more) high-voltage microelectronic component(s), such as for example Schottky diodes, MOSFET transistors, etc. It responds more generally to power microelectronic applications, by allowing excellent vertical electrical conduction, good thermal conductivity and by providing a thin layer of high quality c-SiC.
• high-voltage microelectronic component(s) such as for example Schottky diodes, MOSFET transistors, etc. It responds more generally to power microelectronic applications, by allowing excellent vertical electrical conduction, good thermal conductivity and by providing a thin layer of high quality c-SiC.
• the composite structure 100 can also respond to radio frequency applications, with a resistive support substrate 20 whose physical and potentially thermal characteristics are perfectly suited to the manufacture of RF electronic components.

Landscapes

• Chemical & Material Sciences (AREA)
• Engineering & Computer Science (AREA)
• Materials Engineering (AREA)
• Metallurgy (AREA)
• Organic Chemistry (AREA)
• Crystallography & Structural Chemistry (AREA)
• Inorganic Chemistry (AREA)
• Chemical Kinetics & Catalysis (AREA)
• General Chemical & Material Sciences (AREA)
• Mechanical Engineering (AREA)
• Crystals, And After-Treatments Of Crystals (AREA)
• Laminated Bodies (AREA)
• Recrystallisation Techniques (AREA)

Priority Applications (4)

Applications Claiming Priority (2)

Publications (1)

Family

ID=82196623

Family Applications (1)

Country Status (7)

Cited By (2)

Families Citing this family (5)

Citations (1)

• 2022
  • 2022-03-30 FR FR2202859A patent/FR3134234B1/fr active Active
• 2023
  • 2023-03-06 TW TW112108051A patent/TW202343780A/zh unknown
  • 2023-03-10 KR KR1020247029841A patent/KR20240165938A/ko active Pending
  • 2023-03-10 EP EP23709735.7A patent/EP4500575A1/fr active Pending
  • 2023-03-10 JP JP2024552761A patent/JP2025510560A/ja active Pending
  • 2023-03-10 CN CN202380026936.9A patent/CN118922912A/zh active Pending
  • 2023-03-10 WO PCT/EP2023/056240 patent/WO2023186498A1/fr not_active Ceased

Patent Citations (1)

Non-Patent Citations (2)

Also Published As

Similar Documents

Legal Events