WO2023185712A1 - 半导体器件及相关电路、芯片、电子设备、制备方法 - Google Patents

半导体器件及相关电路、芯片、电子设备、制备方法 Download PDF

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Publication number
WO2023185712A1
WO2023185712A1 PCT/CN2023/084016 CN2023084016W WO2023185712A1 WO 2023185712 A1 WO2023185712 A1 WO 2023185712A1 CN 2023084016 W CN2023084016 W CN 2023084016W WO 2023185712 A1 WO2023185712 A1 WO 2023185712A1
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region
semiconductor layer
igbt
layer
diode
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PCT/CN2023/084016
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English (en)
French (fr)
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杨文韬
赵倩
王梁浩
戴楼成
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华为数字能源技术有限公司
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Publication of WO2023185712A1 publication Critical patent/WO2023185712A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a power semiconductor device and related circuits, chips, electronic equipment and preparation methods.
  • Insulated gate bipolar field effect transistor (insulated gate bipolar transistor, IGBT) is composed of bipolar junction transistor (BJT) and insulated gate field effect transistor (metal-oxide-semiconductor field-effect transistor, MOSFET) Composite fully controlled voltage-driven power semiconductor device.
  • IGBT bipolar junction transistor
  • MOSFET insulated gate field effect transistor
  • IGBT and diodes such as freewheeling diode (FWD) can be integrated on a chip.
  • the structure formed is called reverse conduction IGBT (RC-IGBT).
  • RC-IGBT reverse conduction IGBT
  • Figure 1A the top view of the integrated front and rear chips and the cross-sectional view of the RC-IGBT chip shown in Figure 1B.
  • the RC-IGBT chip shown in Figure 1A and Figure 1B integrates the functions of IGBT and FWD in a single chip. , converting 2 chips into 1 chip, the total area of the chip can be reduced by about 20%, the total cost of the chip can be reduced by about 15%, and the power density of the device can be increased by 20% under the same package size.
  • the IGBT area and FWD area can assist each other in dissipating heat, and the thermal resistance can be reduced by about 30%, enhancing the thermal performance of the system.
  • the RC-IGBT chip shown in Figure 1B has a large number of holes injected into the contact area in the FWD area, causing the FWD anode to inject too many carriers, causing the FWD reverse reaction. The recovery loss is higher.
  • Embodiments of the present invention provide a power semiconductor device and related circuits, chips, electronic equipment, and preparation methods to reduce the reverse recovery loss of diodes.
  • embodiments of the present application provide a semiconductor device, including:
  • a first semiconductor layer of a first conductivity type including opposing first and second surfaces, and an IGBT region for forming an insulated gate bipolar transistor IGBT and a diode region for forming a diode;
  • a second semiconductor layer of the second conductivity type is disposed on the first surface of the first semiconductor layer, and the thickness of the second semiconductor layer located on the IGBT region is greater than that of the second semiconductor layer located on the diode region.
  • the surface of the second semiconductor layer located on the IGBT region facing away from the first semiconductor layer is provided with an emission region of the first conductivity type
  • a collector layer and an electrode layer are provided on the second surface of the first semiconductor layer, and the collector layer and the electrode layer are respectively arranged opposite to the IGBT region and the diode region.
  • the above-mentioned semiconductor device optimizes the front-side structure of the diode area, and reduces the carrier concentration in the diode area by reducing the thickness of the semiconductor layer serving as the anode area or cathode area in this area, thereby reducing the front-side carrier injection efficiency when the diode is turned on. , reduce the amount of reverse recovery charge when the diode is turned off, reduce the reverse recovery loss Err, and ultimately improve the RC-IGBT switching efficiency.
  • the first conductivity type is N-type and the second conductivity type is P-type.
  • the injection concentration of holes in the anode of the diode is reduced, thereby reducing the reverse reaction when the diode is turned off. Restore the amount of charge, reduce the reverse recovery loss Err, and ultimately improve the switching efficiency of RC-IGBT.
  • the first conductivity type is P-type and the second conductivity type is N-type.
  • the injection concentration of electrons in the cathode of the diode is reduced, thereby reducing reverse recovery when the diode is turned off.
  • the amount of charge reduces the reverse recovery loss Err of the diode.
  • front side in the embodiment of this application refers to the side of the diode close to the emitter electrode.
  • the front-side structure of the diode is its anode region; conversely, when the second semiconductor layer is N-type, the front-side structure of the diode is its cathode region.
  • the thickness of the second semiconductor layer located on the IGBT area is 0.5-3 microns, and the thickness of the second semiconductor layer located on the diode area is 0.5-2.5 microns.
  • a ratio of the thickness of the second semiconductor layer located on the diode region to the thickness of the second semiconductor layer located on the IGBT region is 0.2-0.8.
  • the second semiconductor layer located on the IGBT region includes a contact region of a second conductivity type
  • the semiconductor device includes a plurality of emitter regions arranged at intervals, and the contact region is provided on the opposite side. Between two adjacent emission regions, the impurity concentration of the second conductivity type in the contact region is greater than the impurity concentration of the second conductivity type in the second semiconductor layer.
  • the above-mentioned semiconductor device further optimizes the front-side structure of the diode area.
  • the carrier concentration in the diode area is further reduced, thereby reducing the front-side carrier injection efficiency when the diode is turned on, and further reducing the diode turn-on state.
  • the amount of reverse recovery charge during interruption is reduced, the reverse recovery loss Err is reduced, and ultimately the switching efficiency of RC-IGBT is improved.
  • the second semiconductor layer located on the diode region does not include a contact region of the second conductivity type.
  • the difference between the thickness of the second semiconductor layer located on the IGBT region and the thickness of the second semiconductor layer located on the diode region is not less than the thickness of the contact region.
  • the semiconductor device further includes:
  • a first insulating layer is disposed between each gate electrode and the first semiconductor layer.
  • one end of the gate electrode is substantially flush with a surface of the emission region facing away from the first semiconductor layer.
  • the semiconductor device further includes:
  • a second insulating layer is disposed between each first electrode and the first semiconductor layer and the first semiconductor layer respectively.
  • one end of the first electrode is substantially flush with the second semiconductor layer located on the diode region.
  • a carrier storage CS layer of the first conductivity type is further included between the IGBT region and the second semiconductor layer or between the first semiconductor layer and the second semiconductor layer.
  • the first semiconductor layer includes pillars of the first conductivity type and pillars of the second conductivity type alternately arranged along a first direction, and the first direction is substantially perpendicular to the thickness direction, so the cylinder of the first conductivity type and The pillars of the second conductive type all extend along the thickness direction.
  • embodiments of the present application further provide a power conversion circuit, which at least includes the semiconductor device described in the first aspect or any implementation of the first aspect.
  • the power conversion circuit is a circuit used to realize functions such as frequency conversion, voltage conversion, phase change, rectification, inversion, and switching of voltage/current. It can be an inverter circuit, a rectifier circuit, a transformer circuit, etc.
  • embodiments of the present application also provide a reverse conduction insulated gate bipolar transistor RC-IGBT chip, which at least includes the semiconductor device described in the first aspect or any implementation of the first aspect.
  • embodiments of the present application further provide an electronic device, which at least includes the semiconductor device described in the first aspect or any one of the first aspects; or at least includes the third aspect or any one of the first aspects.
  • an electronic device which at least includes the semiconductor device described in the first aspect or any one of the first aspects; or at least includes the third aspect or any one of the first aspects.
  • embodiments of the present application also provide a method for manufacturing a semiconductor device, including:
  • first conductivity type substrate including opposing first and second surfaces, an IGBT region for forming an insulated gate bipolar transistor IGBT and a diode region for forming a diode;
  • Impurity ions of a second conductivity type are injected into the first surface of the substrate to form a semiconductor layer of the second conductivity type; an emission region and a contact of the IGBT are formed in the semiconductor layer disposed on the IGBT region. district;
  • the semiconductor layer disposed on the diode region is etched, and the thickness of the etched semiconductor layer disposed on the diode region is smaller than the etched thickness of the semiconductor layer disposed on the IGBT region. Thickness after etching.
  • the above preparation method optimizes the front-side structure of the diode region and reduces the carrier concentration in the diode region by reducing the thickness of the semiconductor layer serving as the anode region or cathode region in this region, thereby reducing the front-side carrier injection efficiency when the diode is turned on. Reduce the amount of reverse recovery charge when the diode is turned off, reduce the reverse recovery loss Err, and ultimately improve the switching efficiency of RC-IGBT.
  • the etched thickness of the second semiconductor layer disposed on the IGBT region is 0.5-3 microns
  • the etched thickness of the second semiconductor layer disposed on the diode region is The thickness after etching is 0.5-2.5 microns.
  • the thickness of the etched second semiconductor layer disposed on the diode region is equal to the etched thickness of the second semiconductor layer disposed on the IGBT region.
  • the ratio is 0.2-0.8.
  • forming the emitter region and contact region of the IGBT in the semiconductor layer provided on the IGBT region includes:
  • Impurity ions of the second conductivity type are implanted into the emission region exposed by the first groove to form a contact region.
  • forming the emitter region and contact region of the IGBT in the semiconductor layer provided on the IGBT region includes:
  • etching the semiconductor layer provided on the diode region includes:
  • the photoresist layer is partially exposed through a photomask to form a mask.
  • the mask is used to protect the emission area, the contact area and the insulating dielectric layer provided on the IGBT area;
  • the method further includes:
  • a collector layer and an electrode layer of the diode are formed on the second surface of the substrate.
  • the method further includes:
  • a CS layer is formed between the substrate and the semiconductor layer; or, a CS layer is formed between the substrate and the semiconductor layer located in the IGBT region.
  • the method further includes: forming pillars of the first conductivity type and pillars of the second conductivity type alternately arranged along a first direction in the substrate, the first direction being the same as The thickness direction is substantially vertical, and both the first conductive type pillar and the second conductive type pillar extend along the thickness direction.
  • the method further includes:
  • the method also includes:
  • the first electrode, the second insulating layer and the insulating dielectric layer located on the diode area are etched. After etching, one end of the first electrode and one end of the second insulating layer are in contact with each other.
  • the semiconductor layer of the diode area is flush.
  • Figure 1A is a schematic top view of an integrated front and rear chip in the prior art
  • Figure 1B is a schematic cross-sectional view of an RC-IGBT chip in the prior art
  • Figure 2A is an example diagram of an equivalent circuit of an RC-IGBT provided by an embodiment of the present application
  • Figure 2B is an example diagram of the working state of an RC-IGBT provided by the embodiment of the present application.
  • 3A-3C are schematic cross-sectional views of some trench RC-IGBTs provided by embodiments of the present application.
  • Figures 4 to 7 are schematic cross-sectional views of other trench RC-IGBTs provided by embodiments of the present application.
  • Figure 8 is a schematic cross-sectional view of a planar gate RC-IGBT provided by an embodiment of the present application.
  • Figure 9 is a schematic distribution diagram of ohmic contact holes of an RC-IGBT provided by an embodiment of the present application.
  • Figure 10 is a schematic cross-sectional view of the FWD region of the RC-IGBT in the prior art and the FWD region of the RC-IGBT provided by the embodiment of the present application;
  • Figure 11 is the hole concentration distribution of the drift layer when FWD is turned on between the existing RC-IGBT and the RC-IGBT provided by this application.
  • Figure 12 is a schematic illustration of the reverse recovery charge quantity Qrr when the FWD is turned off between the existing RC-IGBT and the RC-IGBT provided by this application;
  • Figure 13 is a schematic flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present application.
  • FIGS. 14A-14J are schematic cross-sectional views of a device formed by a preparation process of a semiconductor device provided by an embodiment of the present application.
  • 15A-15G are schematic cross-sectional views of a device formed by another preparation process of a semiconductor device provided by an embodiment of the present application.
  • 16A-16C are schematic cross-sectional views of devices formed by yet another semiconductor device preparation process provided by embodiments of the present application.
  • N (Negative) type that is, electronic type, a semiconductor that mainly conducts electrons is called N-type semiconductor.
  • Doping donor impurities into intrinsic semiconductors results in N-type semiconductors.
  • N type can be divided into N+ type (more electron type) and N- type (less electron type).
  • the impurity concentration of N+ type semiconductor is greater than the impurity concentration of N- type semiconductor. It should be understood that N+ type (more electron type) and N- type (less electron type) are relative terms.
  • P (Positive) type that is, hole type, a semiconductor that mainly conducts holes is called a P-type semiconductor.
  • Doping acceptor impurities into intrinsic semiconductors results in P-type semiconductors.
  • P type can be divided into P+ type (more hole type) and P- type (less hole type).
  • the impurity concentration of P+ type semiconductor is greater than that of P- type semiconductor.
  • IGBT Insulated gate bipolar transistor
  • IGBT is a composite fully controlled voltage-driven power semiconductor device composed of a bipolar junction transistor (BJT) and an insulated gate field effect transistor (metal-oxide-semiconductor field-effect transistor, MOSFET). IGBT is suitable for use in converter systems with DC voltages of 600V and above, such as AC motors, frequency converters, switching power supplies, lighting circuits, traction drives and other fields.
  • BJT bipolar junction transistor
  • MOSFET insulated gate field effect transistor
  • FWD is a diode that performs freewheeling when the IGBT is turned off in an inductive load switching circuit.
  • FRD is a diode with fast reverse recovery speed.
  • Reverse conduction IGBT Reverse conduction IGBT, RC-IGBT.
  • RC-IGBT is an IGBT structure with an integrated diode.
  • the diode can freewheel when the IGBT is turned off.
  • the development of IGBT has gone through different stages.
  • the first generation IGBT is punch through IGBT (PT-IGBT), which adopts a planar gate structure, a thick P-type substrate with a high doping concentration, and has epitaxial growth
  • PT-IGBT punch through IGBT
  • the electric field has a trapezoidal distribution during reverse blocking, but the device voltage level is not high and the forward conduction voltage drop has negative temperature characteristics, which is not conducive to parallel applications.
  • the second generation is non punch through IGBT (non punch through, NPT-IGBT), which is characterized by a trench gate structure and adopts A lightly doped N-type substrate is used as the drift layer, and the back collector layer is formed by P-type impurity injection.
  • NPT-IGBT non punch through
  • the electric field is distributed in a triangle, and the device voltage level is greatly improved, but the thickness of the substrate is also increasing.
  • the conduction voltage drop and switching losses are both large.
  • the third generation is field stop IGBT (Field stop IGBT, FS-IGBT), which adds an N-type field stop layer based on the second generation structure.
  • IGBT Field stop IGBT, FS-IGBT
  • the electric field is distributed in a trapezoidal manner, thereby ensuring sufficient device resistance. While reducing the substrate thickness, the conduction voltage drop and switching loss are greatly reduced, and the trade-off relationship between the conduction voltage drop Vcesat and the turn-off loss Eoff is improved.
  • the fourth generation is the refined FS-IGBT, which further reduces the substrate thickness by reducing the cell size, optimizing the backside buffer distribution (for example, using hydrogen injection to form a deep buffer, etc.), and achieves higher power density and better performance.
  • FIG. 2A it is the equivalent circuit of RC-IGBT.
  • the integrated FWD of RC-IGBT is connected in anti-parallel with the integrated IGBT, which plays a freewheeling role when the IGBT is turned off.
  • the IGBT area and FWD area of the RC-IGBT device switch alternately. Therefore, to reduce the switching loss of the RC-IGBT device, it is necessary to simultaneously optimize the switching losses Eon and Eoff of the integrated IGBT, as well as the integrated FWD switch. Reverse recovery loss Err during interruption.
  • injection enhancement technology is generally used to increase the carrier concentration in the front near-emission region; to reduce FWD reverse recovery losses, it is necessary to reduce front anode carrier injection. This leads to the need to solve the contradictory relationship between IGBT and FWD carrier distribution when designing RC-IGBT.
  • the structure of the FWD region of the RC-IGBT in the prior art does not include the injection of the emitter region, the etching of the contact region, the implantation of the P-type semiconductor layer, and the implantation of the P contact region are all the same as the IGBT region. This results in a very high hole injection efficiency in the anode region of FWD.
  • the excess carriers that need to be extracted during reverse recovery that is, the reverse recovery charge quantity Qrr when the diode is turned off, are excessive, eventually leading to the reverse recovery loss Err. It is very high and affects the switching efficiency of RC-IGBT.
  • embodiments of the present application provide an RC-IGBT that optimizes the front structure of the FWD region and reduces the injection concentration of holes in the anode of the FWD by reducing the thickness of the P-type semiconductor layer in this region, thereby reducing
  • the front carrier injection efficiency when the diode is turned on reduces the amount of reverse recovery charge when the diode is turned off, reduces the reverse recovery loss Err of the diode, and ultimately improves the switching efficiency of RC-IGBT.
  • the RC-IGBT with an N-type drift layer is used as an example to illustrate.
  • the anode of the FWD is an N-type semiconductor layer, and the cathode of the FWD is reduced by reducing the thickness of the N-type semiconductor layer.
  • the injection concentration of medium electrons can reduce the reverse recovery loss Err.
  • the RC-IGBT involved in the embodiment of the present application is introduced below.
  • the RC-IGBT can also be called a semiconductor device or a power semiconductor device, etc.
  • the RC-IGBT can be a PT-IGBT, NPT-IGBT, or FS-IGBT structure.
  • PT-IGBT is of planar gate type
  • NPT-IGBT and FS-IGBT are of trench type.
  • FIGS 3A-3C and 4-8 are schematic cross-sectional views of some RC-IGBTs provided in embodiments of the present application.
  • the RC-IGBTs shown in Figures 3A-3C and 4-7 belong to trenches.
  • Type, the RC-IGBT shown in Figure 8 belongs to the planar gate type.
  • the RC-IGBT may include: a stacked first semiconductor layer 11 of the first conductivity type, a carrier store (CS) layer 12 of the first conductivity type, a second semiconductor layer 13 of the second conductivity type, and a stacked first semiconductor layer 11 of the first conductivity type.
  • CS carrier store
  • the first conductivity type is N-type
  • the second conductivity type is N-type.
  • the type is P type.
  • the electrode layer 21 belongs to the cathode of the diode. It can be understood that the first conductive type The conductivity type may also be P type and the second conductivity type may be N type. In this case, the electrode layer 21 belongs to the anode of the diode. in:
  • RC-IGBT can be divided into IGBT area and diode area.
  • the diode area is also called FWD area. It should be understood that the diode can also be other types of diodes.
  • the IGBT area forms the IGBT device
  • the FWD area forms the FWD.
  • the emitter electrode of IGBT is shared with the anode electrode of FWD
  • the Pbody layer of IGBT is shared with the P region of FWD
  • the N-type drift layer of IGBT is shared with the N region of FWD.
  • the N-type first semiconductor layer 11 is also called an N-type drift layer or an N-type drift layer.
  • the N-type drift layer includes opposing first and second surfaces.
  • the P-type second semiconductor layer 13 is disposed on the first surface of the N-type first semiconductor layer 11.
  • This second semiconductor layer is also called the Pbody layer. It is disposed on the first surface of the N-type drift layer and can pass through It is formed by injecting P-type impurity ions or growing P-type semiconductor on the N-type drift layer.
  • the P-type second semiconductor layer located in the IGBT region provides a channel when the IGBT is operating, so it can also be called a P-type channel layer;
  • the P-type second semiconductor layer located in the FWD region is the P region of FWD, also It is called P zone or anode zone.
  • the thickness d1 of the second semiconductor layer 13 located in the IGBT region is greater than the thickness d2 of the second semiconductor layer 13 located in the FWD region, so as to reduce the carrier concentration in the second semiconductor layer 13 in the FWD region, thereby reducing the time when the diode is turned on.
  • the front-side carrier injection efficiency reduces the amount of reverse recovery charge when the diode is turned off, reduces the reverse recovery loss Err, and ultimately improves the switching efficiency of RC-IGBT.
  • the thickness of the second semiconductor layer 13 located on the IGBT region is 0.5-3 microns, and the thickness of the second semiconductor layer 13 located on the diode region is 0.5-2.5 microns.
  • the ratio of the thickness of the second semiconductor layer 13 located on the diode region to the thickness of the second semiconductor layer 13 located on the IGBT region is 0.1-0.9, or 0.2-0.8, optionally, 0.5 or 0.6.
  • a plurality of spaced-apart emission regions 131 are provided on the surface of the second semiconductor layer 13 away from the first semiconductor layer 11 .
  • the emitter region 131 only exists in the IGBT region, and the N-type emitter region 131 can be obtained by implanting N-type impurity ions into the second semiconductor layer 13 located on both sides of the gate electrode 151 .
  • the surface of the second semiconductor layer 13 facing away from the first semiconductor layer 11 may include a plurality of contact regions 132 , and the contact regions 132 may be located between two adjacent emitter regions 131 for the second semiconductor layer 13 and the emitter electrode 14 Ohmic contact. It can be understood that the concentration of impurity ions in the contact region 132 is generally higher than that of the second semiconductor layer 13 .
  • the emission region 131 may be higher than the contact region 132 in the thickness direction.
  • the end of the emission region 131 adjacent to the emitter electrode 14 may also be substantially flush with the end of the emission region 131 adjacent to the emitter electrode 14 .
  • substantially flush means that there is little difference in average height in the thickness direction, for example, the difference is less than 1 nm.
  • the contact region 132 only exists in the IGBT region.
  • the contact region 132 can be formed by implanting only in the IGBT region during preparation.
  • the difference between the thickness of the second semiconductor layer 13 located in the IGBT region and the thickness of the second semiconductor layer 13 located in the FWD region is not less than the thickness of the contact region 132 .
  • P-type impurity ions can be implanted into part of the P-type second semiconductor layer 13 in both the IGBT region and the FWD region to form the contact region 132, and then, while the emitter region 131 is protected by a mask, the third P-type second semiconductor layer 13 in the FWD region is protected.
  • the second semiconductor layer 13 and the contact region 132 are etched so that the contact region 132 located in the FWD region is completely etched to reduce the concentration of carriers in the anode region in the FWD region, thereby reducing the amount of reverse recovery charge and reducing the reverse direction. Recovery loss Err.
  • Figure 9 takes the chip composed of RC-IGBT as shown in Figure 3A as including two RC-IGBTs, and each RC-IGBT includes 4 IGBTs and 1 FWD as an example, showing the second semiconductor Schematic diagram of the distribution of ohmic contact holes in layer 13.
  • the ohmic contact hole located in the IGBT area is formed by the contact area 132; the contact area located in the IGBT area It is formed by the second semiconductor layer 13 and the first electrode 152 in this area.
  • the width of the ohmic contact hole located in the IGBT area is narrower and located between the gate electrodes 151; the width of the ohmic contact hole located in the FWD area is wider, and its width is the width of the FWD area.
  • the thickness d3 of the contact region 132 located in the FWD region may be smaller than the thickness d4 of the contact region 132 located in the IGBT region, In order to reduce the concentration of carriers in the contact area 132 of the FWD region, thereby reducing the amount of reverse recovery charge when the diode is turned off, reducing its reverse recovery loss Err, and ultimately improving the switching efficiency of the RC-IGBT.
  • a carrier store can also be included between the N-type first semiconductor layer 11 and the P-type second semiconductor layer 13. , CS) layer 12.
  • the CS layer 12 exists in both the IGBT region and the FWD region.
  • the CS layer 12 may be implanted with impurity ions of the same conductivity type as the drift layer.
  • the N-type CS layer 12 can form a hole barrier to prevent holes from being extracted by the emitter when the IGBT is turned on, improving the efficiency of the end near the emitter.
  • the injection efficiency of the drift layer thereby increasing the conductance modulation during turn-on, can reduce the saturation voltage.
  • the CS layer 12 only exists in the IGBT region, and the first semiconductor layer 11 located in the FWD region is in direct contact with the second semiconductor layer 13. It should be understood that the CS layer 12 is not a necessary layer structure of the RC-IGBT, and in some embodiments, the RC-IGBT may not include the CS layer.
  • the trench RC-IGBT shown in FIGS. 4 to 7 also includes: a plurality of gate electrodes 151 , a first insulating layer 16 , an insulating dielectric layer 18 and an emitter electrode 14 .
  • a plurality of gate electrodes 151 penetrate the second semiconductor layer 13 and the CS layer 12, and one end of the gate electrode 151 is inserted into the first semiconductor layer 11 (drift layer).
  • Each gate electrode 151 is in contact with the second semiconductor layer 13,
  • the first insulating layer 16 is included between the CS layer 12 and the first semiconductor layer 11 .
  • the other end of the gate electrode 151 is covered by an insulating dielectric layer 18.
  • the RC-IGBT also includes an emitter electrode 14.
  • the emitter electrode 14 contacts each emitter region 151 and each contact region 152.
  • the insulating dielectric layer 18 is used to isolate the gate electrode. electrode 151 and the emitter electrode 14 .
  • the insulating dielectric layer 18 may also cover or partially cover the emission region 131, as shown in FIG. 3C.
  • the emitter region 131 and the emitter electrode 14 can be electrically connected on the side of the device.
  • the trench RC-IGBT also includes at least a first electrode 152 and a second insulating layer 17 .
  • each first electrode 152 penetrates the second semiconductor layer 13 and the CS layer 12, one end of the first electrode 152 is inserted into the first semiconductor layer 11 (drift layer), and each first electrode 152 is connected to the second semiconductor layer 13, A second insulating layer 17 is included between the CS layer 12 and the first semiconductor layer 11 .
  • the gate electrode 151 and the first electrode 152 can be formed through the same process.
  • the one located in the IGBT region is called the gate electrode 151
  • the one located in the FWD region is called the first electrode 152.
  • the first electrode 152 located in the FWD region is also etched, so that the other end of the first electrode 152 is flush with the second semiconductor layer 13 located in the FWD region.
  • the first electrode 152 located in the FWD region may not be etched, which is not limited here.
  • the first electrode 152 located in the FWD region is electrically connected to the emitter electrode 14 and can function as an anode electrode.
  • the FWD region may not include the first electrode 152 and the second insulating layer 17 .
  • the RC-IGBT further includes: a buffer layer 19 (also called a field stop layer), a collector layer 20 and an electrode layer 21 disposed on the second surface of the first semiconductor layer 11 .
  • a buffer layer 19 also called a field stop layer
  • the buffer layer 19 and the first semiconductor layer 11 are of the same conductivity type, and the impurity ion concentration of the buffer layer 19 is greater than that of the first semiconductor layer. Therefore, for the N-type first semiconductor,
  • the buffer layer 19 is also called an N+ type buffer layer or an N+ type field stop layer.
  • the buffer layer 19 is not a necessary layer structure, and the collector layer 20 and the electrode layer 21 are both used to provide ohmic contact.
  • the first semiconductor layer 11 of the first conductivity type is provided with N-type pillars 111 and P arranged alternately along the first direction.
  • Type pillars 112, N-type pillars 111 and P-type pillars 112 all extend along the thickness direction of the first semiconductor layer 11 to form a superjunction drift region structure.
  • the N-type cylinder 111 and the P-type cylinder 112 deplete each other, which is equivalent to reducing the effective doping concentration of the drift region, thereby improving the withstand voltage level of the device.
  • the first direction is perpendicular or substantially perpendicular to the thickness direction of the device. It should be understood that the substantially vertical angle may be about 90°, for example, the angle range is 85°-105°, or 80°-110°, etc.
  • the first semiconductor layer 11 of the device includes grooves arranged at intervals, and the P-type second semiconductor layer 13 is provided in the grooves.
  • the P-type second semiconductor layer 13 located in the grooves The second semiconductor layer 13 is called a P-well region, and an N+-type emitter region 131 and a P+-type contact region 132 are provided in the P-well region of the IGBT region.
  • the gate electrode 151 is spaced apart on the first surface of the first semiconductor layer 11 , and the first insulating layer 16 is included between the gate electrode 151 and the first semiconductor layer 11 .
  • the thickness d1 of the second semiconductor layer 13 located in the IGBT region is greater than the thickness d2 of the second semiconductor layer 13 located in the FWD region, and the second semiconductor layer 13 located in the FWD region does not include the contact region 132 to reduce the third semiconductor layer 13 in the FWD region.
  • the carrier concentration in the second semiconductor layer 13 reduces the front carrier injection efficiency when the diode is turned on, reduces the amount of reverse recovery charge when the FWD is turned off, reduces its reverse recovery loss Err, and ultimately improves the switching performance of the RC-IGBT. efficiency.
  • the position of the second semiconductor layer 13 adjacent to the gate electrode can form a conduction emission. region and the channel of the first semiconductor layer (ie, the drift layer).
  • Figure 10 takes N-channel RC-IGBT as an example, and compares the cross-sectional schematic diagram of the FWD region of the RC-IGBT in the prior art and the FWD region of an RC-IGBT provided in the embodiment of the present application.
  • the collector electrode located in the FWD region is also called the cathode electrode, and the emitter electrode located in the FWD region is also called the anode.
  • the thickness d1 of the P-type semiconductor layer in the FWD region in the prior art is equal to the IGBT region and is larger than the thickness d1 of the present application.
  • the example provides the thickness d2 of the P-type semiconductor layer in the FWD region of the RC-IGBT.
  • the etching depth t1 of the P-type semiconductor layer in the prior art is smaller than the etching depth t2 of the P-type semiconductor layer in the embodiment of the present application
  • the etching of the P-type semiconductor layer may be the etching of the entire FWD region to reduce the carrier concentration in the P-type semiconductor layer in the FWD region, thereby reducing the reverse recovery charge when the diode is turned off. quantity Qrr, reduce its reverse recovery loss Err, and ultimately improve the switching efficiency of RC-IGBT.
  • Figure 11 shows a schematic diagram of the hole concentration distribution of the drift layer when FWD is turned on between the existing RC-IGBT and the RC-IGBT provided by this application. It can be seen that the hole concentration of the drift layer of the RC-IGBT provided by this application when FWD is turned on is smaller than that of the drift layer of the existing RC-IGBT.
  • Figure 12 shows a schematic illustration of the reverse recovery charge quantity Qrr when FWD is turned off between the existing RC-IGBT and the RC-IGBT provided by this application. It can be seen that the RC-IGBT provided by this application has a smaller reverse recovery charge quantity Qrr when FWD is turned off than the existing RC-IGBT.
  • the preparation method may include, but is not limited to, some or all of the following steps:
  • Substrate 10 includes opposing first and second surfaces.
  • the substrate 10 may be divided into a region for forming an IGBT and a region for forming a diode, which are respectively referred to as the IGBT region and the diode region.
  • the substrate 10 corresponds to the first semiconductor layer 11 in the above-mentioned RC-IGBT, and after preparation is completed, it is the drift layer of the device.
  • N-type pillars and P-type pillars arranged alternately along the first direction may be formed in the substrate 10 to form a superjunction drift region structure.
  • the first direction is perpendicular or substantially perpendicular to the thickness direction of the device, and both the N-type pillar and the P-type pillar extend along the thickness direction.
  • S02 Form the gate electrode 151 and the first insulating layer 16 of the IGBT.
  • the first insulating layer is used to isolate the gate electrode from the substrate 10 located in the IGBT region.
  • the substrate 10 when preparing a trench RC-IGBT, the substrate 10 can be etched through a photolithography process to form a plurality of grooves, which are used to expose the substrate 10; furthermore, within the grooves
  • the first insulating material and the first metal are deposited in sequence.
  • the first metal located in the IGBT region is called the gate electrode 151
  • the first insulating material located between the gate electrode 151 and the substrate 10 is the first insulating layer 16
  • the first metal located in the diode region is called the first insulating layer 16.
  • An electrode 152, and the first insulating material located between the first electrode 152 and the substrate 10 is the second insulating layer 17.
  • first electrode 152 and the second insulating layer 17 are not necessary structures of the RC-IGBT. In other embodiments, the first electrode 152 and the second insulating layer 17 may not be formed.
  • a first insulating material and a first metal may be deposited sequentially on the first surface of the substrate 10 to form a first insulating material layer and a first metal layer sequentially stacked on the second semiconductor layer. , and then pattern the first insulating material layer and the first metal layer through a photolithography process to obtain a gate electrode, a first insulating layer, a first electrode and a second insulating layer.
  • the first metal layer located in the IGBT region is called the gate electrode
  • the first insulating material located between the gate electrode and the substrate 10 is the first insulating layer
  • the first metal layer located in the diode region is called the gate electrode.
  • the first electrode and the first insulating material layer located between the first electrode and the substrate 10 are respectively the second insulating layer.
  • S03 Form the second semiconductor layer 13 of the second conductivity type on the first surface of the substrate 10.
  • impurity ions of the first conductivity type and impurity ions of the second conductivity type can be injected into the first surface of the substrate 10 on both sides of the gate electrode 151 ,
  • the implantation depth of impurity ions of the first conductivity type is greater than that of the impurity ions of the second conductivity type, so that the area in the substrate 10 where the impurity ions of the first conductivity type is implanted is the CS layer, and the second conductivity type is implanted in the substrate 10
  • the region of impurity ions is the second semiconductor layer 13 .
  • the CS layer 12 is not a necessary layer structure of the RC-IGBT, and in other embodiments, the CS layer 12 may not be formed.
  • impurity ions of the first conductivity type may be implanted only into the substrate 10 located in the IGBT region, that is, the CS layer 12 is formed only in the IGBT region.
  • impurity ions of the second conductivity type can be implanted into multiple regions of the first surface of the substrate 10 to form a plurality of well regions of the second conductivity type, and the plurality of second conductivity type well regions are formed.
  • the well region of the two conductivity types is the second semiconductor layer.
  • the CS layer 12 and the second semiconductor layer 13 may be sequentially deposited and grown on the first surface of the substrate 10 , and then the trench-type gate electrode 151 and the first electrode 152 may be formed.
  • S04 Inject impurity ions of the first conductivity type into the second semiconductor layer 13 located on both sides of the gate electrode 151 to form the emission region 131.
  • impurity ions of the first conductivity type may be implanted only into the surface of the second semiconductor layer 13 located in the IGBT region to form the emission region 131 .
  • the thickness of the emission region 131 is smaller than the thickness of the second semiconductor layer 13 .
  • S05 Form an insulating dielectric layer 18 covering the emitter region 131, the gate electrode 151 and the second semiconductor layer 13.
  • the insulating dielectric layer 18 can be used to isolate the gate electrode 151 and the emitter electrode 14. As shown in Figure 14D.
  • S06 Etch the insulating dielectric layer 18 located in the IGBT area to form at least one first groove.
  • the groove penetrates the insulating dielectric layer 18 and exposes a portion of the emission region 131 . As shown in Figure 14D and Figure 14E.
  • a first photoresist layer covering the insulating dielectric layer 18 may be formed first, and the first photoresist layer may be partially exposed through a photomask to form a first mask.
  • the first mask is used to protect the insulating dielectric layer 18 .
  • the insulating dielectric layer 18 in the exposed area of the first mask is etched to a first depth to form a first groove.
  • S07 Inject impurity ions of the second conductivity type into the emitter region 131 exposed in the first groove to form a contact region 132.
  • impurity ions of the second conductivity type may be implanted into the surface of the second semiconductor layer 13 exposed by the first groove in the IGBT region to form a contact region 132 .
  • the contact area 132 is only located in the IGBT area.
  • S08 Etch the second semiconductor layer 13 located in the diode region. As shown in Figure 14G and Figure 14H.
  • a second photoresist layer covering the contact area 132 and the insulating dielectric layer may be formed first, and the second photoresist layer is partially exposed through a photomask to form a second mask.
  • the second mask is used to protect the emission region 131, the contact region 132, the insulating dielectric layer 18, etc. located in the IGBT region.
  • the insulating dielectric layer 18 and the second semiconductor layer 13 in the diode region exposed by the second mask are etched to reduce the thickness of the second semiconductor layer 13 in the diode region.
  • the diode region includes the first electrode 152 and the second insulating layer 17, the first electrode 152 and the second insulating layer 17 can also be etched.
  • the etched first electrode is adjacent to the emitter electrode 14.
  • One end of the second insulating layer 17 and one end adjacent to the emitter electrode 14 are substantially flush with or higher than the etched semiconductor layer located in the diode region.
  • the insulating dielectric layer 18 located on the surface of the emitter region 131 can also be etched away, so that the emitter region 131 contacts the emitter electrode 14 to achieve electrical connection between the two.
  • the emitter region 131 and the emitter electrode 14 are separated by the insulating dielectric layer 18, the emitter region 131 and the emitter electrode 14 can be electrically connected on the side of the device.
  • S10 Form the electrode layer 21, the collector layer 20 and the collector electrode 22 of the diode on the second surface of the substrate 10 in sequence. As shown in Figure 14J.
  • impurity ions of the first conductive type may be implanted on the second surface of the substrate 10 to form the buffer layer 19 .
  • Impurity ions of the second conductivity type may also be implanted in the IGBT region to form the collector layer 20; impurity ions of the first conductivity type may be implanted in the diode region to form the electrode layer 21.
  • the impurity ion concentration of the buffer layer 19 is greater than that of the substrate 10 .
  • the implantation depth of the impurity ions forming the buffer layer 19 is greater than the implantation depth forming the collector layer 20 and the electrode layer 21 to form a structure as shown in FIG. 14J. Furthermore, a metal layer covering the electrode layer 21 and the collector layer 20 is formed to obtain the collector electrode 22 .
  • buffer layer 19 may also be included, for example, growing the buffer layer, the second electrode layer and the collector layer on the surface of the substrate 10 .
  • the buffer layer 19 is not a necessary layer structure of the RC-IGBT, and in other embodiments, the buffer layer 19 may not be included.
  • the insulating dielectric layer 18 and part of the emitter region 131 located in the IGBT region can be etched to form at least one second groove that penetrates
  • the insulating dielectric layer 18 and the emission region 131 are used to expose the second semiconductor layer 13, resulting in a semiconductor structure as shown in FIG. 15A.
  • impurity ions of the second conductivity type are implanted into the second semiconductor layer 13 exposed in the second groove to form a contact region 132, such as As shown in Figure 15B and Figure 15C.
  • the above-mentioned S08 is performed in sequence, as shown in Figure 15D, to obtain the semiconductor structure shown in Figure 15E, in which the etching depth L1 of the second groove located on the IGBT region is smaller than the etching depth L1 of the layer structure located on the diode region.
  • the etching depth L2 since the etched insulating dielectric layer 18 has the same thickness, the etching depth of the emitter region 131 located on the IGBT region is smaller than the etching depth of the second semiconductor layer 13 located on the diode region, and thus also reduces the etching depth L2.
  • the thickness of the second semiconductor layer 13 on the diode region further reduces the carrier concentration in the diode region, thereby reducing the front carrier injection efficiency when the diode is turned on, reducing the amount of reverse recovery charge when the diode is turned off, and reducing its reverse charge.
  • the recovery loss Err ultimately improves the switching efficiency of RC-IGBT.
  • executing the above S09 can obtain the structure shown in Figure 15F, and then executing S10 can obtain the structure shown in Figure 15G.
  • the mask and process for preparing IGBTs can be used as much as possible.
  • contact areas can also be formed in the diode area. While etching is performed in step S08, the contact area of the diode area is also partially etched or completely etched.
  • the structure shown in FIG. 16A is formed through the process of forming IGBT in the prior art. Further, the insulating dielectric layer 18, the emitter region 131, the contact region 132, the second semiconductor layer 13, and the third semiconductor layer located in the diode region can be formed. An electrode 152 and the second insulating layer 17 are etched to form a structure as shown in FIG. 16B , and then the diode electrode layer 21 , the collector layer 20 and the collector electrode 22 are sequentially formed on the second surface of the substrate 10 , as shown in Figure 16C.
  • first conductivity type is N type and the second conductivity type is P type.
  • the electrode layer is the cathode region of the diode; alternatively, the first conductivity type can also be P type and the second conductivity type is N. Type, at this time the electrode layer is the anode region of the diode.
  • each of the above-mentioned layer structures can be achieved by combining a photolithography process and a thin film preparation process, and is not limited here. It is not limited to the schematic preparation flow diagrams shown in FIGS. 14A to 14E , and may also include other structures and preparation methods, to which the embodiments of the present application are not limited.
  • RC-IGBT is used in energy conversion and transmission circuits, such as voltage/current frequency conversion, voltage conversion, phase change, rectification, inverter, switching, etc.
  • the above-mentioned RC-IGBT devices can be packaged into power modules, such as IGBT discrete devices, IGBT modules and intelligent power modules (intelligent power module, IPM), etc.
  • the IGBT discrete device can be the above-mentioned RC-IGBT chip; the IGBT module is obtained by assembling one or more RC-IGBT chips to a DBC substrate with insulation and then packaging; IPM is a combination of the RC-IGBT device and the driving circuit, overvoltage and It is a "combination" device that integrates peripheral circuits such as over-current protection circuit, temperature monitoring and over-temperature protection circuit.
  • RC-IGBT can be used in power conversion circuits that realize functions such as frequency conversion, voltage conversion, phase conversion, rectification, inverter, and switching to adjust voltage/current, such as inverter circuit (inverter circuit), rectifier circuit (rectifier), and voltage transformer.
  • inverter circuit inverter circuit
  • rectifier circuit rectifier circuit
  • the inverter circuit is a circuit that converts DC power into fixed-frequency and constant-voltage or frequency-modulated and voltage-regulated alternating current. It usually includes an inverter bridge, logic control, filter circuit, etc. Among them, the inverter bridge uses the above-mentioned IGBT device as a switching device.
  • the inverter circuit using the semiconductor device provided by this application as a switching device can be applied to scenarios where the power supply is a DC power supply and needs to supply power to an AC load. For example, when the battery in an electric vehicle supplies power to an AC motor, the electric energy needs to be transferred through the inverter circuit. Conversion; as another example, solar cells need to undergo power conversion through an inverter circuit before being integrated into the AC power grid.
  • the rectifier circuit is a circuit that converts AC power into DC power. It usually consists of a main circuit, a filter and a transformer.
  • the main circuit can be composed of a rectifier diode and the IGBT device provided by this application; the filter is connected between the main circuit and the load to filter out the AC component in the pulsating DC voltage; whether the transformer is set depends on the specific situation. Transformers are used to match the AC input voltage to the DC output voltage and to electrically isolate the AC grid from the rectifier circuit.
  • a rectifier circuit using the semiconductor device provided by this application as a switching device can be applied to scenarios where alternating current needs to be converted into direct current. For example, when an electric vehicle charges its battery, it can use a charging pile or charger that includes a rectifier circuit to convert alternating current into direct current at the rated voltage required by the electric vehicle.
  • Transformer circuit which can be a boost converter (Boost Converter) or a buck converter circuit (Buck Converter). in:
  • a boost converter also known as a Boost converter, is a DC-DC converter that can increase the voltage. Its output (load) voltage will be higher than the input (power supply) voltage.
  • a boost converter mainly includes a switching power supply of at least one diode, at least one transistor and at least one energy storage element (inductor). Among them, the transistor can use the IGBT device provided by this application.
  • a step-down conversion circuit also known as a Buck converter, is a DC-DC converter that can reduce the voltage. Its output (load) voltage will be lower than the input (power supply) voltage, but its output current will be greater than the input current.
  • Buck converter mainly includes at least one diode, at least one transistor, and at least one energy storage component (capacitor, inductor or both).
  • capacitor-based filters can be added to the output and input ends to reduce voltage ripples.
  • the transistor can use the IGBT device provided by this application.
  • Boost converter is added to the photovoltaic inverter to adjust the voltage input to the inverter circuit, thereby allowing the power generated by the solar cells to be integrated into the AC grid.
  • the semiconductor device provided in this application can also be used as a switching device in other circuits that require power semiconductor devices, such as DC boost circuits, DC buck circuits, etc., which are not limited here.
  • the above-mentioned RC-IGBT or circuits or devices composed of the above-mentioned RC-IGBT can further be applied to vehicles such as electric vehicles and subway vehicles, home appliances such as inverter air conditioners and inverter refrigerators, and photovoltaic equipment.

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Abstract

本发明实施例提供一种功率半导体器件及相关电路、芯片、电子设备、制备方法，该半导体器件优化了二极管区域的正面结构，通过降低该区域内作为阳极区或阴极区的半导体层的厚度来降低二极管区域的载流子浓度，从而减少反向恢复电荷量，降低二极管的反向恢复损耗Err，最终提高RC-IGBT的开关效率。

Description

半导体器件及相关电路、芯片、电子设备、制备方法
本申请要求于2022年03月30日提交中国专利局、申请号为202210327363.0、申请名称为“半导体器件及相关电路、芯片、电子设备、制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体技术领域，尤其涉及一种功率半导体器件及相关电路、芯片、电子设备、制备方法。
背景技术
绝缘栅双极型场效应管(insulated gate bipolar transistor，IGBT)是由双极型晶体管(bipolar junction transistor，BJT)和绝缘栅型场效应管(metal-oxide-semiconductor field-effect transistor，MOSFET)组成的复合全控型电压驱动式功率半导体器件。
为了提高IGBT的功率密度，可以将IGBT与二极管，如，续流二极管(freewheeling diode，FWD)集成在一颗芯片上，形成的结构被称为逆导型IGBT(reverse conduction IGBT，RC-IGBT)。如图1A所示的集成前后芯片的俯视示意图和图1B所示的RC-IGBT芯片的剖面示意图，图1A和图1B所示的RC-IGBT芯片以单芯片形式将IGBT与FWD的功能相集成，将2个芯片变为1颗芯片，从而芯片的总面积可缩小20％左右，芯片的总成本可以下降大约15％，同时在相同封装尺寸下器件的功率密度可以提升20％。并且，在RC-IGBT工作过程中，IGBT区域和FWD区域可以相互辅助散热，热阻可以降低大约30％，增强系统的热性能。
然而，以上述N沟道型IGBT为例，上述图1B所示的RC-IGBT芯片在FWD区域中的接触区注入了大量的空穴，导致FWD阳极注入过多的载流子，导致FWD反向恢复损耗较高。
发明内容
本发明实施例提供一种功率半导体器件及相关电路、芯片、电子设备、制备方法，以降低二极管的反向恢复损耗。
第一方面，本申请实施例提供了一种半导体器件，包括：
第一导电类型的第一半导体层，所述第一半导体层包括相对的第一表面和第二表面，及用于形成绝缘栅双极型晶体管IGBT的IGBT区域和用于形成二极管的二极管区域；
设置于所述第一半导体层的第一表面上的第二导电类型的第二半导体层，位于所述IGBT区域上的所述第二半导体层的厚度大于位于所述二极管区域上的所述第二半导体层的厚度；
位于所述IGBT区域上的所述第二半导体层背离所述第一半导体层的表面设有第一导电类型的发射区；以及，
设置于所述第一半导体层的第二表面上的集电极层和电极层，所述集电极层和所述电极层分别相对所述IGBT的区域和所述二极管区域设置。
上述半导体器件，优化了二极管区域的正面结构，通过降低该区域内作为阳极区或阴极区的半导体层的厚度来降低二极管区域的载流子浓度，从而降低二极管导通时正面载流子注入效率，减少二极管关断时的反向恢复电荷量，降低反向恢复损耗Err，最终提高RC-IGBT 的开关效率。
例如，第一导电类型为N型，第二导电类型为P型，通过降低该区域内P型第二半导体层的厚度来降低二极管的阳极中空穴的注入浓度，从而减少二极管关断时的反向恢复电荷量，降低反向恢复损耗Err，最终提高RC-IGBT的开关效率。
又例如，第一导电类型为P型，第二导电类型为N型，通过降低N型第二半导体层的厚度来降低二极管的阴极中电子的注入浓度，从而减少二极管关断时的反向恢复电荷量，降低二极管的反向恢复损耗Err。
应理解，本申请实施例中的“正面”是指，二极管中接近发射极电极的一侧。第二半导体层为P型时，二极管的正面结构即为其阳极区；反之，第二半导体层为N型时，二极管的正面结构即为其阴极区。
在一种可能的实现中，位于所述IGBT区域上的所述第二半导体层的厚度为0.5-3微米，位于所述二极管区域上的所述第二半导体层的厚度为0.5-2.5微米。
在一种可能的实现中，位于所述二极管区域上的所述第二半导体层的厚度与位于所述IGBT区域上的所述第二半导体层的厚度的比值为0.2-0.8。
在一种可能的实现中，位于所述IGBT区域上的所述第二半导体层包括第二导电类型的接触区，所述半导体器件包括间隔设置的多个发射区，所述接触区设于相邻的两个发射区之间，所述接触区的第二导电类型的杂质浓度大于所述第二半导体层的第二导电类型的杂质浓度。
上述半导体器件，进一步优化了二极管区域的正面结构，通过去除二极管区域的接触区，进一步降低二极管区域中的载流子浓度，从而降低二极管导通时正面载流子注入效率，进一步地降低二极管关断时反向恢复电荷量，降低反向恢复损耗Err，最终提高RC-IGBT的开关效率。
在一种可能的实现中，位于二极管区域上的所述第二半导体层不包括第二导电类型的接触区。
在一种可能的实现中，位于所述IGBT区域上的所述第二半导体层的厚度与位于所述二极管区域上的所述第二半导体层的厚度之差不小于所述接触区的厚度。
在一种可能的实现中，该半导体器件还包括：
贯穿所述第二半导体层且接触位于所述IGBT区域的所述第一半导体层的至少一个栅极电极；
设置于每个所述栅极电极分别与所述第一半导体层和所述第一半导体层之间的第一绝缘层。
可选地，所述栅极电极的一端与所述发射区背离所述第一半导体层的表面大致齐平。
在一种可能的实现中，该半导体器件还包括：
贯穿所述第二导电层且接触位于所述二极管区域的所述第一半导体层的至少一个第一电极；
设置于每个所述第一电极分别与所述第一半导体层和所第一半导体层之间的第二绝缘层。
可选地，所述第一电极的一端与位于所述二极管区域上的所述第二半导体层大致齐平。
在一种可能的实现中，所述IGBT区域和所述第二半导体层之间或所述第一半导体层和所述第二半导体层之间还包括：第一导电类型的载流子存储CS层。
在一种可能的实现中，所述第一半导体层包括沿第一方向相间排列的第一导电类型的柱体和第二导电类型的柱体，所述第一方向与厚度方向大致垂直，所述第一导电类型的柱体和 所述第二导电类型的柱体均沿厚度方向延伸。
第二方面，本申请实施例还提供了一种功率转换电路，至少包括如第一方面或第一方面任一种实现所述的半导体器件。
其中，电源转换电路是用于实现调节电压/电流的变频、变压、变相、整流、逆变、开关等功能的电路。可以是逆变电路(inverter circuit)、整流电路(rectifier)、变压电路等。
第三方面，本申请实施例还提供了一种逆导型绝缘栅双极型晶体管RC-IGBT芯片，至少包括如第一方面或第一方面任一种实现所述的半导体器件。
第四方面，本申请实施例还提供了一种电子设备，至少包括如第一方面或第一方面任一种实现所述的半导体器件；或至少包含如第三方面或第一方面任一种实现所述的RC-IGBT芯片。
第五方面，本申请实施例还提供了一种半导体器件的制备方法，包括：
提供第一导电类型的衬底，所述衬底包括相对的第一表面和第二表面，用于形成绝缘栅双极型晶体管IGBT的IGBT区域和用于形成二极管的二极管区域；
形成通过第一绝缘层与位于所述IGBT区域的所述衬底接触的至少一个栅极电极；
对所述衬底的第一表面注入第二导电类型的杂质离子，形成第二导电类型的半导体层；在设于所述IGBT区域上的所述半导体层中形成所述IGBT的发射区和接触区；
对设于所述二极管区域上的所述半导体层进行刻蚀，设于所述二极管区域上的所述半导体层被刻蚀后的厚度小于设于所述IGBT区域上的所述半导体层被刻蚀后的厚度。
上述制备方法优化了二极管区域的正面结构，通过降低该区域内作为阳极区或阴极区的半导体层的厚度来降低二极管区域的载流子浓度，从而降低二极管导通时正面载流子注入效率，减少二极管关断时的反向恢复电荷量，降低反向恢复损耗Err，最终提高RC-IGBT的开关效率。
在一种可能的实现中，设于所述IGBT区域上的所述第二半导体层被刻蚀后的厚度为0.5-3微米，设于所述二极管区域上的所述第二半导体层被刻蚀后的厚度为0.5-2.5微米。
在一种可能的实现中，设于所述二极管区域上的所述第二半导体层被刻蚀后的厚度与设于所述IGBT区域上的所述第二半导体层被刻蚀后的厚度的比值为0.2-0.8。
在一种可能的实现中，所述在设于所述IGBT区域上的所述半导体层中形成所述IGBT的发射区和接触区，包括：
对位于所述栅极电极两侧的所述半导体层注入第一导电类型的杂质离子，形成发射区；
形成覆盖所述发射区、所述栅极电极和所述半导体层的绝缘介质层；
对设于所述IGBT区域上的所述绝缘介质层进行刻蚀，形成至少一个第一凹槽，所述第一凹槽贯穿所述绝缘介质层并显露所述发射区；
对所述第一凹槽显露的所述发射区注入第二导电类型的杂质离子，形成接触区。
在一种可能的实现中，所述在设于所述IGBT区域上的所述半导体层中形成所述IGBT的发射区和接触区，包括：
对所述栅极电极两侧的所述半导体层注入第一导电类型的杂质离子，形成发射区；
形成覆盖所述发射区、所述栅极电极和所述半导体层的绝缘介质层；
对设于所述IGBT区域上的所述绝缘介质层和部分的所述发射区进行刻蚀，形成至少一个第二凹槽，所述第二凹槽贯穿所述绝缘介质层和所述发射区并用于显露所述半导体层，设于所述IGBT区域上的所述发射区的刻蚀深度小于设于所述二极管区域上的所述半导体层的刻蚀深度；
对所述第二凹槽显露的所述半导体层注入第二导电类型的杂质离子，形成接触区；
在一种可能的实现中，对设于所述二极管区域上的所述半导体层进行刻蚀，包括：
形成覆盖所述接触区、所述绝缘介质层和所述半导体层的光刻胶层；
通过光罩部分曝光所述光刻胶层，形成掩膜，所述掩膜用于保护设于所述IGBT区域上的所述发射区、所述接触区和所述绝缘介质层；
对所述第二掩膜暴露的所述绝缘介质层刻蚀和所述半导体层进行刻蚀。
在一种可能的实现中，所述方法还包括：
形成覆盖所述半导体层、所述绝缘介质层和所述接触区的发射极电极；
在所述衬底的第二表面形成集电极层和所述二极管的电极层。
在一种可能的实现中，所述方法还包括：
在所述衬底与所述半导体层之间形成CS层；或，在位于所述IGBT区域的衬底与所述半导体层之间形成CS层。
在一种可能的实现中，所述方法还包括：在所述衬底内形成沿第一方向相间排列的第一导电类型的柱体和第二导电类型的柱体，所述第一方向与厚度方向大致垂直，所述第一导电类型的柱体和所述第二导电类型的柱体均沿厚度方向延伸。
在一种可能的实现中，所述方法还包括：
形成通过第二绝缘层与所述二极管区域的所述衬底的接触的至少一个第一电极；
形成通过第二绝缘层与位于所述二极管区域的所述衬底接触的至少一个第一电极；
所述方法还包括：
对位于所述二极管区域上的所述第一电极、所述第二绝缘层和所述绝缘介质层进行刻蚀，刻蚀后第一电极的一端、所述第二绝缘层的一端均与位于所述二极管区域的所述半导体层齐平。
附图说明
下面将对实施例描述中所需要使用的附图作简单地介绍。
图1A是现有技术中的一种集成前后芯片的俯视示意图；
图1B是现有技术中的一种RC-IGBT芯片的剖面示意图；
图2A是本申请实施例提供的一种RC-IGBT的等效电路的示例图；
图2B是本申请实施例提供的一种RC-IGBT的工作状态的示例图；
图3A-图3C是本申请实施例提供的一些沟槽型RC-IGBT的剖面示意图；
图4-图7是本申请实施例提供的另一些沟槽型RC-IGBT的剖面示意图；
图8是本申请实施例提供的一种平面栅型RC-IGBT的剖面示意图；
图9是本申请实施例提供的一种RC-IGBT的欧姆接触孔的分布示意图；
图10是现有技术中RC-IGBT的FWD区域与本申请实施例提供的一种RC-IGBT的FWD区域的剖面示意图；
图11是现有RC-IGBT与本申请提供的RC-IGBT在FWD导通时的漂移层空穴浓度分布 示意图；
图12是现有RC-IGBT与本申请提供的RC-IGBT在FWD关断时反向恢复电荷量Qrr的示意性说明图；
图13是本申请实施例提供的一种半导体器件的制备方法的流程示意图；
图14A-图14J是本申请实施例提供的一种半导体器件的制备流程形成的器件的剖面示意图；
图15A-图15G是本申请实施例提供的另一种半导体器件的制备流程形成的器件的剖面示意图；
图16A-图16C是本申请实施例提供的又一种半导体器件的制备流程形成的器件的剖面示意图。
具体实施方式
首先对本申请实施例涉及的部分关键术语进行说明。
(1)、N型半导体。
N(Negative)型，即电子型，以电子导电为主的半导体称之为N型半导体。在本征半导体中掺入施主杂质就得到N型半导体，例如，在纯硅掺入微量5价元素(磷或砷等)，磷与周围4价硅原子组成共价结合会多出一个自由电子。其中，N型又可以分为N+型(多电子型)和N-型(少电子型)，N+型半导体的杂质浓度大于N-型半导体的杂质浓度。应理解，N+型(多电子型)和N-型(少电子型)是相对来说的。
(2)、P型半导体。
P(Positive)型，即空穴型，以空穴导电为主的半导体称之为P型半导体。在本征半导体中掺入受主杂质，就得到P型半导体。例如，在纯硅掺入微量3价元素(硼或铟等)，硼与周围4价硅原子组成共价结合会缺少一个电子，形成一个空穴。其中，P型又可以分为P+型(多空穴型)和P-型(少空穴型)，P+型半导体的杂质浓度大于P-型半导体的杂质浓度。
(3)、绝缘栅双极型晶体管(insulated gate bipolar transistor，IGBT)。
IGBT是由双极型晶体管(bipolar junction transistor，BJT)和绝缘栅型场效应管(metal-oxide-semiconductor field-effect transistor，MOSFET)组成的复合全控型电压驱动式功率半导体器件。IGBT适合应用于直流电压为600V及以上的变流系统如交流电机、变频器、开关电源、照明电路、牵引传动等领域。
(4)、续流二极管(freewheeling diode，FWD)、快恢复二极管(fast recovery diode，FRD)。
FWD是在感性负载开关电路中，IGBT关断时进行续流的二极管。FRD是具有快反向恢复速度的二极管。
(5)逆导型IGBT(reverse conduction IGBT,RC-IGBT)。
RC-IGBT是集成了二极管的IGBT结构，二极管可在IGBT关断时进行续流。
(6)IGBT的类型和参数。
IGBT的发展经历了不同的阶段，第一代IGBT为穿通型IGBT(punch through IGBT，PT-IGBT)，其采用平面栅结构，采用厚的P型衬底且掺杂浓度很高，具有外延生长的N型缓冲区和漂移区，反向阻断时电场呈梯形分布，但是器件耐压等级不高且正向导通压降具有负温度特性，不利于并联应用。
第二代为非穿通型IGBT(non punch through，NPT-IGBT)，其特点是沟槽栅结构，采用 轻掺杂的N型衬底做漂移层，背面集电极层采用P型杂质注入形成，反向阻断时电场呈三角形分布，器件耐压等级大幅度提高，但是衬底厚度也不断增大，导通压降和开关损耗都很大。
第三代为场截止型IGBT(Field stop IGBT，FS-IGBT)，其是在第二代结构基础上增加N型场截止层，反向阻断时电场呈梯形分布，从而在保证足够器件耐压的同时减薄衬底厚度，使得导通压降和开关损耗都大幅降低，并且改善了导通压降Vcesat与关断损耗Eoff之间的折中关系。
第四代为精细化的FS-IGBT，其通过缩小元胞尺寸、优化背面缓冲区分布(例如采用氢注入形成深缓冲区等)，进一步减薄衬底厚度，获得了更高的功率密度、更好的导通压降Vcesat与关断损耗Eoff之间的折中关系。
如图2A所示，为RC-IGBT的等效电路,RC-IGBT的集成FWD与集成IGBT反向并联，在IGBT关断时起续流作用。在实际工作时如图2B所示，RC-IGBT器件的IGBT区域和FWD区域交替开关，因此要降低RC-IGBT器件的开关损耗就需要同时优化集成IGBT的开关损耗Eon、Eoff，以及集成FWD关断时的反向恢复损耗Err。然而，要降低IGBT开关损耗，一般采用注入增强技术，提高正面近发射区的载流子浓度；而要降低FWD反向恢复损耗，就要降低正面阳极载流子注入。这就导致RC-IGBT在设计时需要解决IGBT与FWD载流子分布之间的矛盾关系。这需要设计一种RC-IGBT可以在不增加IGBT开关损耗的情况下降低FWD反向恢复损耗。设计的同时还要尽量减少RC-IGBT的制备成本，如减少制备工序等。
由于现有技术中的RC-IGBT的FWD区域的结构除未进行发射区的注入，接触区的刻蚀、P型半导体层的注入、P接触区的注入等都同IGBT区域一样。这导致了FWD的阳极区空穴注入效率很高，在反向恢复时需要抽取的过剩载流子，即二极管关断时的反向恢复电荷量Qrr，过多，最终导致反向恢复损耗Err很高，影响到了RC-IGBT的开关效率。
为了解决上述问题，本申请实施例提供了一种RC-IGBT，其优化了FWD区域的正面结构，通过降低该区域内P型半导体层的厚度来降低FWD的阳极中空穴的注入浓度，从而降低二极管导通时正面载流子注入效率，减少二极管关断时反向恢复电荷量，降低二极管的反向恢复损耗Err，最终提高RC-IGBT的开关效率。
应理解，上述以N型漂移层的RC-IGBT为例来说明，对于P型漂移层的IGBT，其FWD的阳极为N型半导体层，其通过降低N型半导体层的厚度来降低FWD的阴极中电子的注入浓度，来降低反向恢复损耗Err。
下面对本申请实施例涉及的RC-IGBT进行介绍，该RC-IGBT还可以称为半导体器件或功率半导体器件等，RC-IGBT可以是PT-IGBT、NPT-IGBT、FS-IGBT结构。其中，PT-IGBT属于平面栅型；NPT-IGBT、FS-IGBT均属于沟槽型。
如图3A-图3C、图4-图8所示，为本申请实施例提供的一些RC-IGBT的剖面示意图，图3A-图3C、图4-图7所示的RC-IGBT属于沟槽型，图8所示的RC-IGBT属于平面栅型。RC-IGBT可以包括：层叠设置的第一导电类型的第一半导体层11、第一导电类型的载流子存储(carrier store，CS)层12、第二导电类型的第二半导体层13、第一导电类型的发射区131、第二导电类型的接触区132、发射极电极14、栅极电极151、第一电极152、第一绝缘层16、第二绝缘层17、绝缘介质层18、缓冲层19、第二导电类型的集电极层20、第一导电类型的电极层21、集电极电极22等中的部分或全部结构，本申请实施例以第一导电类型为N型，第二导电类型为P型为例来说明，此时电极层21属于二极管的阴极。可以理解，第一导电类 型也可以为P型、第二导电类型为N型，此时，电极层21属于二极管的阳极。其中：
RC-IGBT可以划分为IGBT区域和二极管区域，以二极管为FWD为例，二极管区域也成称为FWD区域，应理解，二极管还可以是其他类型的二极管。其中，IGBT区域形成IGBT器件，FWD区域形成FWD。以N沟道IGBT为例，IGBT的发射极电极与FWD的阳极电极共用，IGBT的Pbody层与FWD的P区共用，IGBT的N型漂移层与FWD的N区共用。
N型第一半导体层11也称为N型漂移层、N-型漂移层。N型漂移层包括相对的第一表面和第二表面。
设置于N型第一半导体层11的第一表面上的P型第二半导体层13，该第二半导体层也称为Pbody层，其设置于N型漂移层的第一表面上，其可以通过注入在N型漂移层上注入P型杂质离子或生长P型半导体形成。应理解，位于IGBT区域的P型第二半导体层在IGBT工作时，提供沟道，因此也可以称为P型沟道层；位于FWD区域的P型第二半导体层为FWD的P区，也称为P区或阳极区。
其中，位于IGBT区域的第二半导体层13的厚度d1大于位于FWD区域的第二半导体层13的厚度d2，以降低FWD区域的第二半导体层13中载流子浓度，从而降低二极管导通时正面载流子注入效率，减少二极管关断时的反向恢复电荷量，降低反向恢复损耗Err，最终提高RC-IGBT的开关效率。
例如，位于IGBT区域上的所述第二半导体层13的厚度为0.5-3微米，位于二极管区域的第二半导体层13的厚度为0.5-2.5微米。
又例如，位于二极管区域上的第二半导体层13的厚度与位于述IGBT区域上的第二半导体层13的厚度的比值为0.1-0.9，或者0.2-0.8，可选地，为0.5、0.6。
在第二半导体层13背离第一半导体层11的表面设有多个间隔设置的发射区131。其中，发射区131仅存在于IGBT区域，N型发射区131可以通过对位于栅极电极151两侧的第二半导体层13进行N型杂质离子注入得到。第二半导体层13背离第一半导体层11的表面包括可以包括多个接触区132，接触区132可以位于相邻的两个发射区131之间，用于第二半导体层13与发射极电极14欧姆接触。可以理解，接触区132的杂质离子的浓度一般高于第二半导体层13。
如图3A所示，发射区131可以在厚度方向高于接触区132。
如图3B和图3C所示，发射区131邻近发射极电极14的一端也可以与发射区131邻近发射极电极14的一端大致齐平。其中，大致齐平是指在厚度方向上的平均高度差别不大，例如相差小于1nm。
如图3A-图3C、图5-图7所示的RC-IGBT，接触区132仅仅存在于IGBT区域，例如，制备时可以仅在IGBT区域注入，形成接触区132。
可选地，位于IGBT区域的第二半导体层13的厚度与位于FWD区域上的第二半导体层13的厚度之差不小于接触区132的厚度。其中，制备时可以对IGBT区域和FWD区域的部分P型第二半导体层13均注入P型杂质离子形成接触区132，进而，在掩膜对发射区131进行保护下，对位于FWD区域的第二半导体层13和接触区132进行刻蚀，以使位于FWD区域的接触区132被完全刻蚀，以减少FWD区域中阳极区载流子的浓度，从而减少反向恢复电荷量，降低反向恢复损耗Err。
如图9所示，图9以如图3A所示的RC-IGBT组成的芯片包括两个RC-IGBT，每个RC-IGBT包括4个IGBT和1个FWD为例，示出了第二半导体层13的欧姆接触孔的分布示意图。其中，位于IGBT区域的欧姆接触孔是由接触区132形成；位于IGBT区域的接触区 则由该区域内的第二半导体层13和第一电极152形成。可以看出，位于IGBT区域的欧姆接触孔宽度更窄，位于栅极电极151之间；位于FWD区域的欧姆接触孔宽度较宽，其宽度即为FWD区域的宽度。
如图4所示，在FWD区域的P型第二半导体层13可以包括接触区132时，此时，位于FWD区域的接触区132的厚度d3可以小于位于IGBT区域的接触区132的厚度d4，以降低FWD区域的接触区132中载流子的浓度，从而减少二极管关断时的反向恢复电荷量，降低其反向恢复损耗Err，最终提高RC-IGBT的开关效率。
可选地，如图3A-图3C，图4-图5所示的RC-IGBT，N型第一半导体层11与P型第二半导体层13之间还可以包括载流子存储(carrier store，CS)层12。CS层12既存在于IGBT区域，也存在与FWD区域。对于N型第一半导体层11来说，CS层12可以注入与漂移层相同导电类型的杂质离子。对于N型第一半导体层11(N型漂移层)来说，N型的CS层12可以形成空穴势垒，以在IGBT导通时阻挡空穴被发射极抽走，提高靠近发射极一端的漂移层的注入效率，从而增加导通期间的电导调制，可降低饱和电压。
如图6和图7所示的RC-IGBT，在一些实施例中，CS层12仅存在于IGBT区域，位于FWD区域的第一半导体层11与第二半导体层13直接接触。应理解，CS层12不是RC-IGBT必须的层结构，在一些实施例中，RC-IGBT可以不包括CS层。
如图3A-图3C，图4-图7所示的沟槽型RC-IGBT还包括：多个栅极电极151、第一绝缘层16、绝缘介质层18和发射极电极14。其中，多个栅极电极151贯穿第二半导体层13和CS层12，栅极电极151的一端插入到第一半导体层11(漂移层)，每个栅极电极151与第二半导体层13、CS层12和第一半导体层11之间均包括第一绝缘层16。栅极电极151的另一端被绝缘介质层18覆盖，RC-IGBT还包括发射极电极14，发射极电极14接触每个发射区151和每个接触区152，绝缘介质层18用于隔离栅极电极151和该发射极电极14。
应理解，绝缘介质层18也可以覆盖或部分覆盖发射区131，如图3C所示。当发射区131与发射极电极14之间被绝缘介质层18隔离时，可以在器件的侧面电连接发射区131和发射极电极14。
可选地，如图3A-图3C，图4-图6所示的沟槽型RC-IGBT还包括至少一个第一电极152、第二绝缘层17。其中，每个第一电极152贯穿第二半导体层13和CS层12，第一电极152的一端插入到第一半导体层11(漂移层)，每个第一电极152与第二半导体层13、CS层12和第一半导体层11之间均包括第二绝缘层17。
可选地，栅极电极151和第一电极152可以通过同一道工序生成，位于IGBT区域的称为栅极电极151，而位于FWD区域的则称为第一电极152。在第二半导体层13被刻蚀时，位于FWD区域的第一电极152也被刻蚀，使得第一电极152的另一端与位于FWD区域的第二半导体层13齐平。需要说明的是，位于FWD区域的第一电极152也可以不被刻蚀，此处不作限定。
应理解，对于P沟道IGBT来说，位于FWD区域的第一电极152与发射极电极14电连接，可以起到阳极电极的作用。
如图7所示的沟槽型RC-IGBT，在一些实施例中，FWD区域可以不包括第一电极152和第二绝缘层17。
在一些实施例中，RC-IGBT还包括：设置于第一半导体层11的第二表面的缓冲层19(也称为场截止层)、集电极层20、电极层21。一般地，缓冲层19与第一半导体层11是同一种导电类型，缓冲层19的杂质离子浓度大于第一半导体层，因此，对于N型第一半导体来说， 缓冲层19也被称为N+型缓冲层、N+型场截止层。
其中，缓冲层19不是必须的层结构，集电极层20、电极层21均用于提供欧姆接触。
如图5-图7所示的沟槽型RC-IGBT，在一些实施例中，第一导电类型的第一半导体层11内设有沿着第一方向相间排列的N型柱体111和P型柱体112，N型柱体111和P型柱体112均沿着第一半导体层11的厚度方向延伸，以形成超结漂移区结构。该结构的器件在工作时，通过N型柱体111与P型柱体112相互耗尽，等效于降低了漂移区的有效掺杂浓度，从而提高器件的耐压水平。其中，第一方向与器件的厚度方向垂直或大致垂直。应理解，大致垂直可以是角度成90°左右，例如，角度范围为85°-105°，或80°-110°等。
如图8所示的平面栅型RC-IGBT，该器件的第一半导体层11包括间隔设置的凹槽，P型第二半导体层13设置于该凹槽内，位于凹槽内的P型第二半导体层13称为P阱区，位于IGBT区域的P阱区内设置N+型发射区131和P+型接触区132。栅极电极151间隔设置于第一半导体层11的第一表面，栅极电极151和第一半导体层11之间包括第一绝缘层16。
其中，位于IGBT区域的第二半导体层13的厚度d1大于位于FWD区域的第二半导体层13的厚度d2，且位于FWD区域的第二半导体层13不包括接触区132，以降低FWD区域的第二半导体层13中载流子浓度，从而降低二极管导通时正面载流子注入效率，减少FWD关断时的反向恢复电荷量，降低其反向恢复损耗Err，最终提高RC-IGBT的开关效率。
对于N型第一半导体层的RC-IGBT，在栅极电极和发射极电极之间上施加电压VGS大于临界值VGES时，第二半导体层13邻接栅极电极的位置可以形成导通发射区和第一半导体层(即漂移层)的沟道。
图10以N沟道RC-IGBT为例，对比了现有技术中RC-IGBT的FWD区域与本申请实施例提供的一种RC-IGBT的FWD区域的剖面示意图。位于FWD区域的集电极电极也称为阴极电极，位于FWD区域的发射极电极也称为阳极，现有技术中的FWD区域内的P型半导体层的厚度d1与IGBT区域相等，大于本申请实施例提供的RC-IGBT的FWD区域内的P型半导体层的厚度d2。这可以通过在制备过程中，在刻蚀形成P+接触区时，现有技术中对P型半导体层的刻蚀深度t1小于本申请实施例中对该P型半导体层的刻蚀深度t2，且本申请实施例中对该P型半导体层的刻蚀可以是对整个FWD区域的刻蚀，以降低FWD区域的P型半导体层中载流子浓度，从而减少二极管关断时的反向恢复电荷量Qrr，降低其反向恢复损耗Err，最终提高RC-IGBT的开关效率。
图11示出了现有RC-IGBT与本申请提供的RC-IGBT在FWD导通时的漂移层空穴浓度分布示意图。可见，本申请提供的RC-IGBT在FWD导通时的漂移层空穴浓度均小于现有RC-IGBT的漂移层。
图12示出了现有RC-IGBT与本申请提供的RC-IGBT在FWD关断时反向恢复电荷量Qrr的示意性说明图。可见，本申请提供的RC-IGBT在FWD关断时反向恢复电荷量Qrr小于现有RC-IGBT。
下面介绍上述图3A-图3C，图4-图8所示的RC-IGBT的制备方法，如图13所示的RC-IGBT的制备方法的流程示意图和图14A-图14H所示的，该制备方法可以包括但不限于如下部分或全部步骤：
S01：提供第一导电类型的半导体衬底10。衬底10包括相对的第一表面和第二表面。衬底10可以划分为用于形成IGBT的区域和用于形成二极管的区域，分别称为IGBT区域和二极管区域。
应理解，衬底10对应于上述RC-IGBT中的第一半导体层11，制备完成后，为器件的漂移层。
在一些实施例中，可以在衬底10内形成沿着第一方向相间排列的N型柱体和P型柱体，以形成超结漂移区结构。其中，第一方向与器件的厚度方向垂直或大致垂直，N型柱体和P型柱体均沿着厚度方向延伸。
S02：形成IGBT的栅极电极151和第一绝缘层16。其中，第一绝缘层用于隔离栅极电极和位于IGBT区域的衬底10。
如图14A所示，在制备沟槽型RC-IGBT时，可以通过光刻工艺刻蚀衬底10，形成多个凹槽，该凹槽用于显露衬底10；进而，在该凹槽内依次沉积第一绝缘材料和第一金属。其中，位于IGBT区域的第一金属称为栅极电极151，位于栅极电极151与衬底10之间的第一绝缘材料即为第一绝缘层16；位于二极管区域的第一金属称为第一电极152，位于第一电极152与衬底10之间的第一绝缘材料即为第二绝缘层17。
应理解，第一电极152和第二绝缘层17不是RC-IGBT必须的结构，在另一些实施例中，也可以不形成第一电极152、第二绝缘层17。
在制备平面栅型RC-IGBT时，可以在衬底10的第一表面依次沉积第一绝缘材料和第一金属，形成依次层叠与第二半导体层上的第一绝缘材料层和第一金属层，再通过光刻工艺图案化第一绝缘材料层和第一金属层，得到栅极电极、第一绝缘层、第一电极和第二绝缘层。应理解，位于IGBT区域的第一金属层称为栅极电极，位于栅极电极分别与衬底10之间的第一绝缘材料即为第一绝缘层；位于二极管区域的第一金属层称为第一电极，位于第一电极分别与衬底10之间的第一绝缘材料层即为第二绝缘层。
S03：在衬底10的第一表面形成第二导电类型的第二半导体层13。
如图14B所示，在制备沟槽型RC-IGBT时，可以在衬底10的第一表面位于栅极电极151的两侧注入第一导电类型的杂质离子和第二导电类型的杂质离子，其中，第一导电类型的杂质离子的注入深度大于第二导电类型的杂质离子，从而衬底10中注入第一导电类型的杂质离子的区域即为CS层，衬底10中注入第二导电类型的杂质离子的区域即为第二半导体层13。
可以理解，CS层12不是RC-IGBT必须的层结构，在另一些实施例中，可以不形成CS层12。
在一些实施例中，可以仅对位于IGBT区域的衬底10注入第一导电类型的杂质离子，即仅在IGBT区域形成CS层12。
应理解，在制备平面栅型RC-IGBT时，可以在衬底10的第一表面的多个区域注入第二导电类型的杂质离子，形成多个第二导电类型的阱区，该多个第二导电类型的阱区即为第二半导体层。
在另一些实施例中，也可以先在衬底10的第一表面依次沉积生长CS层12和第二半导体层13，再形成沟槽型的栅极电极151和第一电极152。
S04：对位于栅极电极151两侧的第二半导体层13注入第一导电类型的杂质离子，形成发射区131。
如图14C所示，可以仅对位于IGBT区域的第二半导体层13的表面注入第一导电类型的杂质离子，形成发射区131。发射区131的厚度小于第二半导体层13的厚度。
S05：形成覆盖发射区131、栅极电极151和第二半导体层13的绝缘介质层18，该绝缘介质层18可以用于隔离栅极电极151与发射极电极14。如图14D所示。
S06：对位于IGBT区域的绝缘介质层18进行刻蚀，形成至少一个第一凹槽，该第一凹 槽贯穿绝缘介质层18并显露部分的发射区131。如图14D和图14E所示。
具体地，可以先形成覆盖绝缘介质层18的第一光刻胶层，通过光罩部分曝光第一光刻胶层，以形成第一掩膜。该第一掩膜用于保护绝缘介质层18。进一步地，对第一掩膜暴露区域的绝缘介质层18进行第一深度的刻蚀，形成第一凹槽。
S07：对第一凹槽显露的发射区131注入第二导电类型的杂质离子，形成接触区132。
如图14F所示，在一些实施例中可以对位于IGBT区域的第一凹槽显露的第二半导体层13的表面注入第二导电类型的杂质离子，形成接触区132。此时，接触区132仅仅位于IGBT区域。
S08：对位于二极管区域的第二半导体层13进行刻蚀。如图14G和图14H所示。
具体地，可以先形成覆盖接触区132和绝缘介质层的第二光刻胶层，通过光罩部分曝光第二光刻胶层，以形成第二掩膜。该第二掩膜用于保护位于IGBT区域的发射区131、接触区132和绝缘介质层18等。进一步地，对第二掩膜暴露的位于二极管区域的绝缘介质层18和第二半导体层13进行刻蚀，以降低二极管区域的第二半导体层13的厚度。应理解，当二极管区域包括第一电极152和第二绝缘层17时，还可以对该第一电极152和第二绝缘层17进行刻蚀，刻蚀后的第一电极邻近发射极电极14的一端、第二绝缘层17邻近发射极电极14的一端均与刻蚀后的位于述二极管区域的半导体层大致齐平或高于刻蚀后的位于述二极管区域的半导体层。
S09：形成覆盖接触区132、绝缘介质层18和第二半导体层13的发射极电极14。如图14I所示。
在一些实施例中，位于发射区131表面上的绝缘介质层18也可以被刻蚀掉，以使发射区131与发射极电极14接触，实现两者的电连接。
当发射区131与发射极电极14之间被绝缘介质层18隔离时，可以在器件的侧面电连接发射区131和发射极电极14。
S10：在衬底10的第二表面依次形成二极管的电极层21、集电极层20和集电极电极22。如图14J所示。
在一些实施例中，可以在衬底10的第二表面注入第一导电类型的杂质离子，形成缓冲层19。还可以在IGBT区域的注入第二导电类型的杂质离子，形成集电极层20；在二极管区域注入第一导电类型的杂质离子，形成电极层21。其中，一般地，缓冲层19的杂质离子浓度大于衬底10。
形成缓冲层19的杂质离子的注入深度均大于形成集电极层20和电极层21的注入深度，以形成如图14J所示的结构。进一步地，形成覆盖电极层21和集电极层20的金属层，得到集电极电极22。
应理解，还可以包括其他制备缓冲层19、电极层21和集电极层20的方式，例如，在衬底10的表面生长缓冲层、第二电极层、集电极层。
还应理解，缓冲层19不是RC-IGBT必须的层结构，在另一些实施例中，也可以不包括缓冲层19。
在另一种半导体器件的制备方法中，上述步骤S05之后，可以对位于IGBT区域的绝缘介质层18和部分的发射区131进行刻蚀，形成至少一个第二凹槽，该第二凹槽贯穿绝缘介质层18和发射区131并用于显露第二半导体层13，得到如图15A所示的半导体结构。进一步地，对第二凹槽显露的第二半导体层13注入第二导电类型的杂质离子，形成接触区132，如 图15B和图15C所示。更进一步地，依次执行上述S08，如图15D，得到如图15E所示的半导体结构，其中，位于IGBT区域上的第二凹槽的刻蚀深度L1小于对位于二极管区域上的层结构的刻蚀深度L2，由于刻蚀的绝缘介质层18厚度相同，那么位于IGBT区域上的发射区131的刻蚀深度小于设于二极管区域上的第二半导体层13的刻蚀深度，进而，也降低了二极管区域上的第二半导体层13的厚度，进而降低二极管区域的载流子浓度，从而降低二极管导通时正面载流子注入效率，减少二极管关断时的反向恢复电荷量，降低其反向恢复损耗Err，最终提高RC-IGBT的开关效率。
进一步地，执行上述S09可以得到如图15F所示的结构，再执行S10可以得到如图15G所示的结构。
各个步骤的具体实现可以参见上述图13所示的实施例中相关描述，这里不再赘述。
在另一种半导体器件的制备方法中，为了减少光罩制备和工艺的改进，可以尽量使用制备IGBT的光罩和工艺。
例如，在二极管区域也可以形成接触区。在步骤S08进行刻蚀的同时，对二极管区域的接触区也进行部分刻蚀或完全刻蚀。
又例如，通过现有技术中形成IGBT的工艺形成如图16A所示的结构，进一步地，可以对位于二极管区域的绝缘介质层18、发射区131、接触区132、第二半导体层13、第一电极152和第二绝缘层17进行刻蚀，以形成如图16B所示的结构，进而，在衬底10的第二表面依次形成二极管的电极层21、集电极层20和集电极电极22，如图16C所示。
各个步骤的具体实现可以参见上述图13所示的实施例中相关描述，这里不再赘述。
需要说明的是，上述第一导电类型为N型，第二导电类型为P型，此时电极层为二极管的阴极区；或者，第一导电类型也可以为P型、第二导电类型为N型，此时电极层为二极管的阳极区。
还需要说明的是，上述各个层结构的制备可以结合光刻工艺、薄膜制备工艺来实现，这里不作限定。不限于上述图14A-图14E所示的制备流程示意图，还可以包括其他结构和制备方法，对此，本申请实施例不作限定。
RC-IGBT作为一种开关器件，用于能源转换和传输电路，如电压/电流的变频、变压、变相、整流、逆变、开关等。在应用过程中，上述RC-IGBT器件可以被封装为功率模块，如IGBT分立器件、IGBT模块和智能功率模块(intelligent power module，IPM)等。其中，IGBT分立器件可以是上述RC-IGBT芯片；IGBT模块是将一个或多个RC-IGBT芯片以绝缘组装到DBC基板后封装得到的；IPM是将RC-IGBT器件与驱动电路、过压和过流保护电路、温度监视和超温保护电路等外围电路集成得到的“组合”型器件。
RC-IGBT可以被应用于是实现调节电压/电流的变频、变压、变相、整流、逆变、开关等功能的电源转换电路，如逆变电路(inverter circuit)、整流电路(rectifier)、变压电路中，下面对各个电路和其应用场景进行分别描述。
(1)、逆变电路是将直流电能转变成定频定压或调频调压交流电的电路，通常包括逆变桥、逻辑控制、滤波电路等。其中，逆变桥以上述IGBT器件作为开关器件。采用本申请提供的半导体器件作为开关器件的逆变电路可以应用于电源为直流电源，需要向交流负载供电的场景，例如，电动汽车中的蓄电池为交流电机供电时，需要经过逆变电路进行电能转换；又例如，太阳能电池并入交流电网之前需要经过逆变电路进行电能转换。
(2)、整流电路是将交流电能转换为直流电能的电路，通常由主电路、滤波器和变压器组成。其中，主电路可以采用整流二极管和本申请提供的IGBT器件组成；滤波器连接于主电路与负载之间，用于滤除脉动直流电压中的交流成分；变压器设置与否视具体情况而定，变压器用于实现交流输入电压与直流输出电压间的匹配以及交流电网与整流电路之间的电隔离。采用本申请提供的半导体器件作为开关器件的整流电路可以应用于需要将交流电转换为直流电的场景。例如，电动汽车在给蓄电池充电时，可以采用通过包括整流电路的充电桩或者充电器将交流电转换为电动汽车需要的额定电压的直流电。
(3)、变压电路，可以是升压变换器(Boost Converter)或降压变换电路(Buck Converter)。其中：
升压变换器又称为Boost变换器，是可以提升电压的直流-直流转换器，其输出(负载)电压会比输入(电源)电压高。Boost变换器主要包括至少一个二极管、至少一晶体管及至少一个储能元件(电感器)的开关电源。其中，晶体管可以采用本申请提供的IGBT器件。
降压变换电路又称为Buck变换器，是可以降低电压的直流-直流转换器，其输出(负载)电压会比输入(电源)电压低，但其输出电流会大于输入电流。Buck变换器主要包括至少一个二极管、至少一晶体管、至少一个储能元件(电容器、电感器或是二者都有)。可选地，还可以在输出端及输入端加上以电容器为主的滤波器以降低电压涟波。其中，晶体管可以采用本申请提供的IGBT器件。
例如，由于时间或天气的变化，太阳能电池板电压不断变化。为保证太阳能电池板都输出额定功率，会在光伏逆变器中增加Boost变换器，以调节输入到逆变电路的电压，进而，使得太阳能电池发出的电能并入交流电网。
不限于上述电路，本申请提供的半导体器件作为开关器件作还可以应用于需要功率半导体器件的其他电路，如直流升压电路、直流降压电路等，这里不作限定。
上述RC-IGBT或者由上述RC-IGBT组成的电路或器件进一步地可以应用于电动汽车、地铁车辆等车辆，也可以应用于变频空调、变频冰箱等家电设备，还可以应用于光伏设备等。
本发明实施例中所使用的技术术语仅用于说明特定实施例而并不旨在限定本发明。在本文中，单数形式“一”、“该”及“所述”用于同时包括复数形式，除非上下文中明确另行说明。进一步地，在说明书中所使用的用于“包括”和/或“包含”是指存在所述特征、整体、步骤、操作、元件和/或构件，但是并不排除存在或增加一个或多个其它特征、整体、步骤、操作、元件和/或构件。
在所附权利要求中对应结构、材料、动作以及所有装置或者步骤以及功能元件的等同形式(如果存在的话)旨在包括结合其他明确要求的元件用于执行该功能的任何结构、材料或动作。本发明的描述出于实施例和描述的目的被给出，但并不旨在是穷举的或者将被发明限制在所公开的形式。

Claims (25)

  1. 一种半导体器件，其特征在于，包括：
    第一导电类型的第一半导体层，所述第一半导体层包括相对的第一表面和第二表面，及用于形成绝缘栅双极型晶体管IGBT的IGBT区域和用于形成二极管的二极管区域；
    设置于所述第一半导体层的第一表面上的第二导电类型的第二半导体层，位于所述IGBT区域上的所述第二半导体层的厚度大于位于所述二极管区域上的所述第二半导体层的厚度；
    位于所述IGBT区域上的所述第二半导体层背离所述第一半导体层的表面设有第一导电类型的发射区；以及，
    设置于所述第一半导体层的第二表面上的集电极层和电极层，所述集电极层和所述电极层分别相对所述IGBT的区域和所述二极管区域设置。
  2. 根据权利要求1所述的半导体器件，其特征在于，位于所述IGBT区域上的所述第二半导体层的厚度为0.5-3微米，位于所述二极管区域上的所述第二半导体层的厚度为0.5-2.5微米。
  3. 根据权利要求1所述的半导体器件，其特征在于，位于所述二极管区域上的所述第二半导体层的厚度与位于所述IGBT区域上的所述第二半导体层的厚度的比值为0.2-0.8。
  4. 根据权利要求1-3任一项所述的半导体器件，其特征在于，位于所述IGBT区域上的所述第二半导体层包括第二导电类型的接触区，所述半导体器件包括间隔设置的多个所述发射区，所述接触区设于相邻的两个发射区之间，所述接触区的第二导电类型的杂质浓度大于所述第二半导体层的第二导电类型的杂质浓度。
  5. 根据权利要求1-4任一项所述的半导体器件，其特征在于，位于二极管区域上的所述第二半导体层不包括第二导电类型的接触区。
  6. 根据权利要求1-5任一项所述的半导体器件，其特征在于，位于所述IGBT区域上的所述第二半导体层的厚度与位于所述二极管区域上的所述第二半导体层的厚度之差不小于所述接触区的厚度。
  7. 根据权利要求1-6任一项所述的半导体器件，其特征在于，还包括：
    贯穿所述第二半导体层且接触位于所述IGBT区域的所述第一半导体层的至少一个栅极电极；
    设置于每个所述栅极电极分别与所述第一半导体层和所述第一半导体层之间的第一绝缘层。
  8. 根据权利要求7所述的半导体器件，其特征在于，所述栅极电极的一端与所述发射区背离所述第一半导体层的表面大致齐平。
  9. 根据权利要求1-8任一项所述的半导体器件，其特征在于，还包括：
    贯穿所述第二导电层且接触位于所述二极管区域的所述第一半导体层的至少一个第一电极；
    设置于每个所述第一电极分别与所述第一半导体层和所第一半导体层之间的第二绝缘层。
  10. 根据权利要求9所述的半导体器件，其特征在于，所述第一电极的一端与位于所述二极管区域上的所述第二半导体层大致齐平。
  11. 根据权利要求1-10任一项所述的半导体器件，其特征在于，所述IGBT区域和所述第二半导体层之间或所述第一半导体层和所述第二半导体层之间还包括：第一导电类型的载流子存储CS层。
  12. 根据权利要求1-11任一项所述的半导体器件，其特征在于，所述第一半导体层包括沿第一方向相间排列的第一导电类型的柱体和第二导电类型的柱体，所述第一方向与厚度方向大致垂直，所述第一导电类型的柱体和所述第二导电类型的柱体均沿厚度方向延伸。
  13. 一种功率转换电路，其特征在于，至少包括一个如权利要求1-12任一项所述的半导体器件。
  14. 一种逆导型绝缘栅双极型晶体管RC-IGBT芯片，其特征在于，至少包括一个如权利要求1-12任一项所述的半导体器件。
  15. 一种电子设备，其特征在于，至少包括如权利要求1-9任一项所述的半导体器件或包含如权利要求1-12任一项所述的RC-IGBT芯片。
  16. 一种半导体器件的制备方法，其特征在于，包括：
    提供第一导电类型的衬底，所述衬底包括相对的第一表面和第二表面，用于形成绝缘栅双极型晶体管IGBT的IGBT区域和用于形成二极管的二极管区域；
    形成通过第一绝缘层与位于所述IGBT区域的所述衬底接触的至少一个栅极电极；
    对所述衬底的第一表面注入第二导电类型的杂质离子，形成第二导电类型的半导体层；在设于所述IGBT区域上的所述半导体层中形成所述IGBT的发射区和接触区；
    对设于所述二极管区域上的所述半导体层进行刻蚀，设于所述二极管区域上的所述半导体层被刻蚀后的厚度小于设于所述IGBT区域上的所述半导体层被刻蚀后的厚度。
  17. 根据权利要求16所述的方法，其特征在于，设于所述IGBT区域上的所述第二半导体层被刻蚀后的厚度为0.5-3微米，设于所述二极管区域上的所述第二半导体层被刻蚀后的厚度为0.5-2.5微米。
  18. 根据权利要求17所述的方法，其特征在于，设于所述二极管区域上的所述第二半导体层被刻蚀后的厚度与设于所述IGBT区域上的所述第二半导体层被刻蚀后的厚度的比值为0.2-0.8。
  19. 根据权利要求16-18任一项所述的方法，其特征在于，所述在设于所述IGBT区域上的所述半导体层中形成所述IGBT的发射区和接触区，包括：
    对位于所述栅极电极两侧的所述半导体层注入第一导电类型的杂质离子，形成发射区；
    形成覆盖所述发射区、所述栅极电极和所述半导体层的绝缘介质层；
    对设于所述IGBT区域上的所述绝缘介质层进行刻蚀，形成至少一个第一凹槽，所述第一凹槽贯穿所述绝缘介质层并显露部分的所述发射区；
    对所述第一凹槽显露的所述发射区注入第二导电类型的杂质离子，形成接触区。
  20. 根据权利要求16-18任一项所述的方法，其特征在于，所述在设于所述IGBT区域上的所述半导体层中形成所述IGBT的发射区和接触区，包括：
    对所述栅极电极两侧的所述半导体层注入第一导电类型的杂质离子，形成发射区；
    形成覆盖所述发射区、所述栅极电极和所述半导体层的绝缘介质层；
    对设于所述IGBT区域上的所述绝缘介质层和部分的所述发射区进行刻蚀，形成至少一个第二凹槽，所述第二凹槽贯穿所述绝缘介质层和所述发射区并用于显露所述半导体层，设于所述IGBT区域上的所述发射区的刻蚀深度小于设于所述二极管区域上的所述半导体层的刻蚀深度；
    对所述第二凹槽显露的所述半导体层注入第二导电类型的杂质离子，形成接触区。
  21. 根据权利要求19或20所述的方法，其特征在于，对设于所述二极管区域上的所述半导体层进行刻蚀，包括：
    形成覆盖所述接触区、所述绝缘介质层和所述半导体层的光刻胶层；
    通过光罩部分曝光所述光刻胶层，形成掩膜，所述掩膜用于保护设于所述IGBT区域上的所述发射区、所述接触区和所述绝缘介质层；
    对所述第二掩膜暴露的所述绝缘介质层刻蚀和所述半导体层进行刻蚀。
  22. 根据权利要求16-21任一项所述的方法，其特征在于，还包括：
    形成覆盖所述半导体层、所述绝缘介质层和所述接触区的发射极电极；
    在所述衬底的第二表面形成集电极层和所述二极管的电极层。
  23. 根据权利要求16-22任一项所述的方法，其特征在于，还包括：
    在所述衬底与所述半导体层之间形成CS层；或，在位于所述IGBT区域的衬底与所述半导体层之间形成CS层。
  24. 根据权利要求16-23任一项所述的方法，其特征在于，还包括：在所述衬底内形成沿第一方向相间排列的第一导电类型的柱体和第二导电类型的柱体，所述第一方向与厚度方向大致垂直，所述第一导电类型的柱体和所述第二导电类型的柱体均沿厚度方向延伸。
  25. 根据权利要求16-24任一项所述的方法，其特征在于，还包括：
    形成通过第二绝缘层与所述二极管区域的所述衬底的接触的至少一个第一电极；
    形成通过第二绝缘层与位于所述二极管区域的所述衬底接触的至少一个第一电极；
    所述方法还包括：
    对位于所述二极管区域上的所述第一电极、所述第二绝缘层和所述绝缘介质层进行刻蚀，刻蚀后第一电极的一端、所述第二绝缘层的一端均与位于所述二极管区域的所述半导体层大致齐平。
PCT/CN2023/084016 2022-03-30 2023-03-27 半导体器件及相关电路、芯片、电子设备、制备方法 WO2023185712A1 (zh)

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