WO2023185192A1 - 一种模拟数字转换器和提高模拟数字转换器的带宽方法 - Google Patents

一种模拟数字转换器和提高模拟数字转换器的带宽方法 Download PDF

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WO2023185192A1
WO2023185192A1 PCT/CN2023/070648 CN2023070648W WO2023185192A1 WO 2023185192 A1 WO2023185192 A1 WO 2023185192A1 CN 2023070648 W CN2023070648 W CN 2023070648W WO 2023185192 A1 WO2023185192 A1 WO 2023185192A1
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signal
analog
circuit
input terminal
coupled
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PCT/CN2023/070648
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English (en)
French (fr)
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扶仲毅
李定
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华为技术有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • H03M1/54—Input signal sampled and held with linear return to datum

Definitions

  • the present invention relates to the technical field of signal processing, and in particular to an analog-to-digital converter, a method for improving the bandwidth of the analog-to-digital converter, and electronic equipment.
  • An analog-to-digital converter is a converter that converts analog signals into digital signals.
  • Successive approximation register (SAR) ADCs are ADCs for medium to high-resolution applications with sampling rates below 5Msps (millions of samples per second). In each conversion process, by traversing all quantized values and converting them into analog values, the input signal is compared with them one by one, and finally the digital signal to be output is obtained.
  • SAR ADC has the characteristics of low power consumption and small size, it is widely used in various electronic devices.
  • the single-channel bandwidth of the existing SAR ADC which is half of the Nyquist sampling rate, can no longer meet the large-bandwidth/multi-mode direct acquisition requirements of existing wireless communications and optical communications. Therefore, how to improve the single-channel bandwidth of the SAR ADC? Channel bandwidth is an issue that needs to be solved urgently.
  • embodiments of the present application provide an analog-to-digital converter, a method for improving the bandwidth of the analog-to-digital converter, and electronic equipment.
  • the SAR logic circuit Stop working, after the dynamic amplifier obtains the residual voltage, it converts the input residual voltage into a timing signal with time, and then converts the time information into a digital signal through a time-to-digital converter to obtain LSB information, achieving more accurate results at the same time.
  • High resolution means increasing the conversion speed of SAR ADC, thereby increasing the single-channel bandwidth of SAR ADC.
  • embodiments of the present application provide an analog-to-digital converter, including: an analog signal input terminal, a capacitor array, a comparator circuit, a dynamic amplifier, and a time-to-digital converter; the capacitor array is coupled to the analog signal input between the terminal and the first output terminal of the comparator circuit; the input terminal of the comparator circuit is coupled to the analog signal input terminal, and the first output terminal of the comparator circuit is connected to the control terminal of the capacitor array.
  • the second output end of the comparator circuit is coupled with the control end of the dynamic amplifier, the comparator circuit is used to generate a comparison signal according to the analog signal received by the analog signal input end, and passes the first
  • the output terminal is output to the capacitor array and is used to generate a first control signal according to the analog signal and output it to the dynamic amplifier through the second output terminal.
  • the first control signal is used to enable the The dynamic amplifier operates, the comparison signal is used to generate a first part of the digital signal; the input terminal of the dynamic amplifier is coupled to the analog signal input terminal, and the output terminal of the dynamic amplifier is coupled to the input terminal of the time-to-digital converter ;
  • the output end of the time-to-digital converter is used to output the second part of the digital signal.
  • a dynamic amplifier and time-to-digital converter are added to the SAR ADC.
  • the first input terminal of the dynamic amplifier is coupled to the capacitor array, the second input terminal of the dynamic amplifier is coupled to the comparator, and the output terminal of the dynamic amplifier is coupled to the time-to-digital converter.
  • the dynamic amplifier receives the control signal sent by the comparator, converts the input analog electrical signal into a timing signal with time, and then converts the timing signal into a digital signal through a time-to-digital converter to achieve At the same time, a higher resolution is obtained, that is, the conversion speed of the SAR ADC is increased, thereby increasing the single-channel bandwidth of the SAR ADC.
  • the method further includes: a successive approximation register type SAR logic circuit, wherein the input terminal of the SAR logic circuit is coupled to the first output terminal of the comparator circuit, and the first output terminal of the SAR logic circuit The terminal is coupled to the control terminal of the capacitor array, the second output terminal of the SAR logic circuit is used to output the second control signal, and the second output terminal of the SAR logic circuit is used to output the first part of the digital signal, so The second control signal is used to enable the capacitor array to operate.
  • a successive approximation register type SAR logic circuit wherein the input terminal of the SAR logic circuit is coupled to the first output terminal of the comparator circuit, and the first output terminal of the SAR logic circuit The terminal is coupled to the control terminal of the capacitor array, the second output terminal of the SAR logic circuit is used to output the second control signal, and the second output terminal of the SAR logic circuit is used to output the first part of the digital signal, so The second control signal is used to enable the capacitor array to operate.
  • the comparator circuit is used to determine whether the difference between the analog signals received at the analog signal input terminal is less than a set threshold, and whether the difference between the analog signals is less than a set threshold. threshold, the first control signal is generated.
  • the comparator circuit includes a clock signal input terminal, a comparator, a delay circuit and a flip-flop; the first input terminal of the comparator is coupled to the analog signal input terminal, and the comparator The second input terminal is coupled to the clock signal input terminal, and the output terminal of the comparator is coupled to the output terminal of the SAR logic circuit and the first input terminal of the flip-flop respectively, and the comparator is used according to the The clock signal input by the clock signal input terminal and the analog signal received by the analog signal input terminal generate the comparison signal; the delay circuit is coupled between the clock signal input terminal and the second input terminal of the flip-flop. time; the input terminal of the flip-flop is coupled to the control terminal of the dynamic amplifier, and the input terminal of the flip-flop is used to output the first control signal.
  • the comparator includes a first MOS transistor M1, a second MOS transistor M2, a first inverter, a second inverter and an OR logic device.
  • the source of the first MOS transistor M1 The source of the second MOS transistor M2 is coupled to the first power input terminal.
  • the drain of the first MOS transistor M1 and the drain of the second MOS transistor M2 are respectively connected to the ground.
  • the first MOS transistor The gate of M1 and the gate of the second MOS transistor M2 are respectively coupled to the analog signal input terminal; the input terminal of the first inverter is coupled to the first power input terminal and the first MOS Between the source of the transistor M1, the input end of the second inverter is coupled between the first power input end and the source of the second MOS transistor M2, and the output of the first inverter terminal and the output terminal of the second inverter are coupled with the input terminal of the OR logic device, and the output terminal of the OR logic device is used to output the comparison signal.
  • the comparator further includes a third MOS transistor M7, a fourth MOS transistor M8, a fifth MOS transistor M9 and a sixth MOS transistor M10; the source of the third MOS transistor M7 is coupled to the between the first power input terminal and the first inverter, the source of the fourth MOS transistor M8 is coupled between the first power input terminal and the second inverter; The source of the fifth MOS transistor M9 is coupled to the drain of the first MOS transistor M1 and the drain of the second MOS transistor M2.
  • the drain of the fifth MOS transistor M9 is grounded; the sixth MOS transistor M10 Coupled between the source of the first MOS transistor M1 and the source of the second MOS transistor M2; the gate of the third MOS transistor M7, the gate of the fourth MOS transistor M8, the The gate of the fifth MOS transistor M9 and the gate of the sixth MOS transistor M10 are respectively coupled to the clock signal input terminal.
  • the delay circuit is configured to generate a second clock signal according to the clock signal received by the clock signal input terminal, and the second clock signal is a clock signal delay device received by the clock signal input terminal. time clock signal.
  • the flip-flop is used to generate the first control signal according to the comparison signal and the second clock signal.
  • the dynamic amplifier includes a first switching circuit, a second switching circuit, a first MOS transistor, a second MOS transistor and a current source; one end of the first switching circuit and the first switching circuit One end of the first switching circuit is coupled to the second power input terminal respectively, the other end of the first switching circuit is coupled to the source of the first MOS tube, and the other end of the second switching circuit is coupled to the source of the second MOS tube; so The drain of the first MOS transistor and the drain of the second MOS transistor are respectively coupled to one end of the current source, and the other end of the current source is grounded; the gate of the first MOS transistor and the gate of the second MOS transistor are coupled to one end of the current source. The gates of the two MOS transistors are respectively coupled to the analog signal input terminals.
  • the dynamic amplifier further includes a first capacitor and a second capacitor; one end of the first capacitor is coupled between the first switch circuit and the first MOS transistor, and the first capacitor has The other end is grounded; one end of the second capacitor is coupled between the second switch circuit and the second MOS transistor, and the other end of the second capacitor is grounded.
  • the dynamic amplifier is configured to disconnect the first switch circuit and the second switch circuit according to the first control signal sent by the comparator circuit.
  • embodiments of the present application provide a method for converting an analog signal to a digital signal, including: a comparator circuit generates a first control signal according to the first analog signal and outputs it to a dynamic amplifier; the dynamic amplifier receives the After receiving the first control signal, the first analog signal is converted into a second analog signal, and the second analog signal carries time information; after the time-to-digital converter receives the second analog signal, the second analog signal is converted into a second analog signal. Convert analog signals into digital signals.
  • the method further includes: the comparator circuit receiving a clock signal; the comparator circuit generating a first control signal according to the first analog signal and outputting it to a dynamic amplifier, specifically including: the comparing The processor circuit generates the first control signal based on the clock signal and the first analog signal.
  • the method further includes: the comparator circuit generates a comparison signal according to the first analog signal and the clock signal, and outputs it to a successive approximation register type SAR logic circuit; the SAR logic circuit After receiving the comparison signal, a digital signal is generated according to the comparison signal.
  • embodiments of the present application provide an electronic device, including: an analog circuit for generating an analog signal; a clock circuit for generating a clock signal; and at least one analog-to-digital converter as may be implemented in the first aspect, It is used to receive the analog signal and the clock signal, and convert the analog signal into a digital signal; a digital circuit is used to receive the digital signal and process it.
  • Figure 1 is a schematic structural diagram of an existing SAR ADC
  • FIG. 2 is a schematic structural diagram of a SAR ADC provided in the embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a SAR ADC provided in the embodiment of the present application.
  • Figure 4 is a schematic structural diagram of a comparator circuit provided in an embodiment of the present application.
  • Figure 5 is a schematic structural diagram of a comparator provided in an embodiment of the present application.
  • Figure 6 is a simulation diagram between the discharge time of capacitor C and the voltage difference before and after discharge;
  • Figure 7 is a schematic diagram comparing the performance of the two existing SAR ADCs and the SAR ADC protected by this application;
  • Figure 8 is a schematic flow chart of a method for improving the bandwidth of a SAR ADC provided in the embodiment of the present application.
  • FIG. 9 is a schematic diagram of the frame of an electronic device provided in an embodiment of the present application.
  • a and/or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. these three situations.
  • the symbol "/" in this article indicates that the associated object is or, for example, A/B means A or B.
  • first, second, etc. in the description and claims herein are used to distinguish different objects, rather than to describe a specific order of objects.
  • first response message and the second response message are used to distinguish different response messages, but are not used to describe a specific sequence of response messages.
  • multiple refers to two or more, for example, multiple processing units refers to two or more processing units, etc.; multiple Component refers to two or more components, etc.
  • FIG. 1 is a schematic structural diagram of an existing SAR ADC.
  • the SAR ADC mainly includes a capacitor array, a comparator and a SAR logic circuit.
  • the capacitor array samples the input analog signal V IN , and outputs the analog input voltage V IN and the analog output voltage V OUT after completing the sampling.
  • the analog input voltage V OUTN and the analog output voltage V OUTP are respectively input to the positive input terminal and the negative input terminal of the comparator.
  • the comparator compares the input analog input voltage V OUTN and the analog output voltage V OUTP and generates a comparison signal V comp .
  • the comparator If the analog input voltage V OUTN is greater than the analog output voltage V OUTP , the comparator outputs the comparison signal V comp to a logic high level or "1"; if the analog input voltage V OUTN is less than the analog output voltage V OUTP , the comparator outputs the comparison signal Vcomp is logic low or "0".
  • the clock signal clk serves as an enable signal and controls the output update of the comparator and SAR logic circuit.
  • MSB most significant bit
  • the comparator compares the input analog input voltage V OUTN and the analog output voltage V OUTP , and outputs a comparison signal V comp .
  • the SAR logic circuit completes one setting according to the comparison signal V comp and then moves to the second high position and prepares for the next comparison. And so on, until the clock signal clk is at the least significant bit (LSB), the conversion is completed. After the entire sequential comparison process is completed, the SAR ADC completes an analog to digital conversion and outputs the digital code corresponding to the analog quantity.
  • Multi-bit synchronous comparison technology In SAR ADC, 2 N comparators are set up. During the comparison process of the SAR ADC, multiple comparators perform comparisons simultaneously. In this solution, the sampling rate of the SAR ADC reaches N bit/cycle, which can reduce the number of SAR conversions and improve the single-channel bandwidth of the SAR ADC. However, 2 N comparators are installed in the SAR ADC, which adds 2 N -1 comparators, causing the SAR ADC to consume relatively large power.
  • phase jump technology In order to achieve N bit accuracy, traditional SAR ADC needs to go through N conversion phases. In order to improve the comparison time of SAR ADC, other conditions can be judged to skip multiple phases and directly obtain the final quantification result. This technology is collectively called phase jump technology. Taking the metastable state judgment technology as an example, in a certain comparison of the SAR ADC, after the comparator enters the metastable state, it can be considered that the input residual voltage has converged to a small range, the quantified result has been obtained, and the remaining voltage can be skipped. phase.
  • the metastable state refers to a state in which the voltages at the two input terminals of the comparator are very close, causing the comparator to take a long time to output a comparison signal.
  • the SAR ADC includes a capacitor array 210 , a comparator circuit 220 , a SAR logic circuit 230 , a dynamic amplifier 240 and a time-to-digital converter 250 .
  • the newly added dynamic amplifier 240 is connected to the two input terminals of the comparator circuit 220 and is connected in parallel with the comparator circuit 220 .
  • the comparator circuit 220 determines whether the clock signal clk is in the MSB phase, that is, whether the SAR ADC is in the MSB phase.
  • the comparator circuit 220 compares the residual voltages received at the two input terminals and outputs a comparison signal V comp .
  • the SAR logic circuit 230 completes one setting according to the comparison signal V comp and then moves to the next highest level, generates a control signal and sends it to the capacitor array 210 to prepare for the next comparison.
  • the SAR logic circuit 230 also converts the comparison signal V comp into a digital signal, and outputs a digital code corresponding to the analog quantity.
  • the comparator circuit 220 detects that the difference between the residual voltages of the two input terminals is relatively small, and determines that the metastable state is entered.
  • the comparator circuit 220 controls the SAR logic circuit 230 to stop working.
  • the comparator circuit 220 sends a control signal to the dynamic amplifier 240 to allow the dynamic amplifier 240 to operate.
  • the dynamic amplifier 240 converts the input residual voltage into a timing signal with time, and then inputs the signal into the time-to-digital converter 250 .
  • the time-to-digital converter 250 measures the time interval between the two timing signals, converts the time information corresponding to the time interval into a digital signal, obtains the LSB information, and outputs the digital code corresponding to the analog quantity.
  • the SAR logic circuit stops working.
  • the dynamic amplifier After the dynamic amplifier obtains the residual voltage, it converts the input residual voltage into a timing signal with time, and then passes the time-to-digital converter Convert the timing signal into a digital signal to obtain LSB information, thereby achieving higher resolution at the same time, that is, increasing the conversion speed of the SAR ADC, thereby increasing the single-channel bandwidth of the SAR ADC.
  • FIG 3 is a schematic structural diagram of a SAR ADC provided in the embodiment of the present application.
  • the SAR ADC includes a capacitor array 210, a comparator circuit 220, a SAR logic circuit 230, a dynamic amplifier 240 and a time-to-digital converter 250.
  • the capacitor array 210 samples and holds the analog signal to obtain two voltage signals, namely the first voltage signal V 1 and the second voltage signal V 2 , and then the first voltage signal V 1 and the second voltage signal V 2 are respectively input to Two input terminals of comparator circuit 220.
  • the capacitor array 210 provided by this application includes two input paths, and the input circuit inputs a voltage signal to the input end of the comparator circuit 220 .
  • Four capacitors C are connected in parallel between the input path and the negative reference voltage V refn circuit or the positive reference voltage V refp circuit.
  • a switch circuit S is electrically connected between each capacitor C and the negative reference voltage V refn circuit or the positive reference voltage V refp circuit.
  • the SAR logic circuit 230 generates a control signal according to the comparison signal V comp output by the comparator circuit 220, and sends the control signal to the capacitor array 210 to control each switch circuit and select the input circuit to be electrically connected to the negative reference voltage V refn circuit. Or the input circuit is electrically connected to the positive reference voltage V refp circuit.
  • the working process of the capacitor array 210 can be divided into three stages, namely the sampling stage, the holding stage and the charge redistribution stage.
  • the specific implementation process is as follows:
  • the capacitor array 210 can control the switch circuit S 11 and the switch circuit S 21 to close, and the first voltage signal V 1 and the second voltage signal V 2 are directly input to the two input terminals of the comparator circuit 220 .
  • the SAR logic circuit 230 can control the switch circuit S 22 -S 25 to close.
  • the capacitor array 210 can control the switch circuit S 11 and the switch circuit S 21 to close, and the first voltage signal V 1 and the second voltage signal V 2 are directly input to the two input terminals of the comparator circuit 220 .
  • the SAR logic circuit 230 can control the switch circuits S 12 -S 15 to open, and the input circuit 1 is disconnected from the reference voltage V ref circuit, that is, the capacitors C 11 -C 14 on the input circuit 1 are connected to the ground GND; the SAR logic circuit 230
  • the switch circuits S 22 -S 25 can be controlled to be closed, and the input circuit 2 is electrically connected to the negative reference voltage V refn circuit, that is, the other end of the capacitor C 21 -C 24 on the input circuit 2 is electrically connected to the negative reference voltage V refn circuit.
  • the SAR logic circuit 230 If the comparison signal V cmp1 ⁇ 0, indicating that the first voltage signal V 1 is less than the second voltage signal V 2 , the SAR logic circuit 230 sends a low level or "0" to each switch circuit. At this time, the SAR logic circuit 230 can control the switch circuits S 12 -S 15 to close, and the input circuit 1 is electrically connected to the positive reference voltage V refp circuit, that is, the other end of the capacitor C 11 -C 14 on the input circuit 1 is connected to the positive reference voltage.
  • the V refp circuit is electrically connected; the SAR logic circuit 230 can control the switch circuits S 22 -S 25 to be disconnected, and the input circuit 2 is disconnected from the reference voltage V ref circuit, that is, the capacitors C 21 -C 24 on the input circuit 1 are connected to the ground GND.
  • the charges will be redistributed again, and the comparison signal V cmp2 output by the comparator circuit 220 is increased or decreased by 1/2 of the reference voltage V ref on the comparison signal V cmp1 of the first comparison, that is, Increase or multiply the reference voltage V ref by the proportion of the capacitance value participating in the quantization to the total capacitance.
  • the SAR logic circuit 230 sends a high level or “1” to each switch circuit.
  • the SAR logic circuit 230 can control the switch circuits S 13 -S 15 to open, and the input circuit 1 is disconnected from the reference voltage V ref circuit, that is, the capacitors C 12 -C 14 on the input circuit 1 are connected to the ground GND; the SAR logic circuit 230
  • the switch circuits S 23 -S 25 can be controlled to be closed, and the input circuit 2 is electrically connected to the negative reference voltage V refn circuit, that is, the other end of the capacitor C 22 -C 24 on the input circuit 2 is electrically connected to the negative reference voltage V refn circuit.
  • the SAR logic circuit 230 If the comparison signal V cmp2 ⁇ 0, indicating that the first voltage signal V 1 is less than the second voltage signal V 2 , the SAR logic circuit 230 sends a low level or "0" to each switch circuit. At this time, the SAR logic circuit 230 can control the switch circuits S 13 -S 15 to close, and the input circuit 1 is electrically connected to the positive reference voltage V refp circuit, that is, the other end of the capacitor C 12 -C 14 on the input circuit 1 is connected to the positive reference voltage.
  • the V refp circuit is electrically connected; the SAR logic circuit 230 can control the switch circuits S 23 -S 25 to be disconnected, and the input circuit 2 is disconnected from the reference voltage V ref circuit, that is, the capacitors C 22 -C 24 on the input circuit 1 are connected to the ground GND.
  • the comparator circuit 220 After receiving the clock signal clk, the comparator circuit 220 can determine whether it is in the MSB stage based on the timing of the comparator circuit 220 . When the comparator circuit 220 determines that the clock signal clk is in the MSB stage, it compares the received first voltage signal V 1 and the second voltage signal V 2 and outputs a comparison signal V comp .
  • this application provides a comparator circuit 220 , which includes a comparator 221 , a delay module 222 and a flip-flop 223 .
  • the input terminal 1 and the input terminal 2 of the comparator 221 are electrically connected to the two output terminals of the capacitor array 210 respectively
  • an input terminal 3 of the comparator 221 is electrically connected to an external clock circuit
  • the output terminal 4 of the comparator 221 is electrically connected to
  • the SAR logic circuit 230 is electrically connected to an input terminal 7 of the flip-flop 223 .
  • the comparator 221 compares the first voltage to the received first voltage signal V 1 and the second voltage signal V 2 , and outputs a comparison signal V comp .
  • the comparison signal V comp output by the comparator 221 is a logic high level or “1”.
  • the comparison signal V comp output by the comparator 221 is a logic low level or "0”.
  • the comparator 221 When the first voltage signal V 1 and the second voltage signal V 2 are very close, that is, the relationship between the first voltage signal V 1 and the second voltage signal V 2 is V 1 -V 2 ⁇ 0, the comparator 221 When comparing the first voltage signal V 1 and the second voltage signal V 2 , the time required will be longer than in other cases.
  • the comparator 221 If the comparator 221 cannot provide a judgment result within a specified time, the comparator 221 enters a "metastable" state. In addition, after entering the metastable state, the comparator circuit 220 locks the first voltage signal V 1 and the second voltage signal V 2 to achieve fixed high-bit information, so as to provide a stable electrical signal for the dynamic amplifier 240 .
  • the source of the MOS transistor M1 and the source of the MOS transistor M2 are respectively connected to the power supply, and the drain of the MOS transistor M1 and the drain of the MOS transistor M2 are respectively connected to the power supply.
  • the source of the MOS transistor M9 is connected, and the drain of the MOS transistor M9 is grounded; the gates of the transistor M1 and the transistor M2 are electrically connected to the two output terminals of the capacitor array 210, respectively, for receiving the first voltage signal V 1 and the second voltage. Signal V 2 .
  • the input terminal of the first inverter is coupled between the power supply and the source of the MOS transistor M1
  • the input terminal of the second inverter is coupled between the power supply and the source of the MOS transistor M2.
  • the output terminal of the first inverter and the output terminal of the second inverter are coupled to the input terminal of the OR logic device, and the output terminal of the OR logic device is used to output the comparison signal.
  • the source of MOS tube M7 is coupled between the power supply and the first inverter; the source of MOS tube M8 is coupled between the power supply and the second inverter; the source of MOS tube M10 is coupled between the source and the source of MOS tube M1 Between the sources of the MOS transistor M2; the gates of the MOS transistor M7, the gate of the MOS transistor M8, the gates of the MOS transistor M9 and the gates of the MOS transistor M10 are respectively connected to external clock circuits. When the difference between the first voltage signal V 1 and the second voltage signal V 2 received by the comparator 221 is greater than the set threshold, one of the electrical signal Von and the electrical signal Vop input to the OR logic device is high level.
  • the comparison signal output by the logic device is high level or "1"; when the difference between the first voltage signal V 1 and the second voltage signal V 2 received by the comparator 221 is not greater than the set threshold , that is, the two voltage signals are relatively close, the electrical signal Von and the electrical signal Vop input to the OR logic device are both low level or "0", or the comparison signal output by the logic device is low level or "0".
  • the delay module 222 is generally composed of one or more inverters, its input terminal 5 is electrically connected to an external clock circuit, and its output terminal 6 is electrically connected to the input terminal 8 of the flip-flop 223 for delaying the clock signal clk. Set the time and then input it into trigger 223.
  • Flip-flop 223 is an electronic component that can store the state of a circuit.
  • the circuit structure of the flip-flop 223 is generally composed of logic gates and is used to process the interaction between input and output signals and clock frequency.
  • the comparison signal V comp and the clock signal clk delayed by the set time are compared on the rising edge, Determine whether the comparison signal V comp output by the comparator 221 is valid at the trigger moment.
  • the flip-flop 223 When the output signal is valid at the trigger moment, it indicates that the comparator 221 has not entered the metastable state, and the flip-flop 223 outputs a high level; when the output signal is invalid at the trigger moment, it indicates that the comparator 221 has entered the metastable state, and the flip-flop 223 outputs a low level.
  • the signal output from the output terminal 9 of the flip-flop 223, that is, the control signal, is input to the dynamic amplifier 240.
  • the comparison signal V comp input by the comparator 221 into the SAR logic circuit 230 can cause the SAR logic circuit 230 to stop working.
  • the SAR logic circuit 230 stops working after the comparator 221 enters the metastable state, which can reduce the number of phases of conversion, which is equivalent to increasing the conversion speed of the SAR logic circuit 230.
  • the flip-flop 223 sends a control signal to the dynamic amplifier 240 to de-reset the dynamic amplifier 240 .
  • the SAR ADC 200 During the time period when the comparator circuit 220 enters the metastable state, the SAR ADC 200 has no digital signal output. In order to improve the digital signal output of the SAR ADC 200, the SAR ADC 200 quantifies the input voltage in the time domain when the comparator circuit 220 enters the metastable state, obtains LSB information, improves the sampling speed of the SAR ADC 200, and achieves improved SAR ADC 200 single channel bandwidth.
  • the SAR logic circuit 230 is used to receive the clock signal clk input from the external clock circuit and the comparison signal V comp input from the comparator 220, generate a control signal, and input the control signal into the capacitor array 210 to control each switch in the capacitor array 210.
  • the circuit is turned on or off to control the capacitor array 210 to enter the sampling phase, the holding phase and the charge redistribution phase.
  • the SAR logic circuit 230 can also convert the comparison signal V comp into a digital signal, and output the digital code corresponding to the comparison signal, thereby converting the analog signal into Digital signal. Since the SAR logic circuit 230 used in this application is a conventional SAR logic circuit, it will not be described in detail here.
  • the dynamic amplifier 240 After receiving the control signal, the dynamic amplifier 240 receives the first voltage signal V 1 and the second voltage signal V 2 output by the capacitor array 210 , and converts the first voltage signal V 1 and the second voltage signal V 2 into time-related signals. After the timing signal is input to the time-to-digital converter 250.
  • this application provides a dynamic amplifier 240, which includes two metal-oxide-semiconductor field-effect transistors (MOSFETs) (Mos1, Mos2), two capacitors (C sp , C sm ) and two switching circuits (S sp , S sm ).
  • MOSFETs metal-oxide-semiconductor field-effect transistors
  • C sp capacitors
  • C sm capacitors
  • S sp switching circuits
  • the gate of the transistor Mos1 is connected to the input circuit 1, the source of the transistor Mos1 is electrically connected between the switching circuit S sp and the capacitor C sp , and the drain of the transistor Mos1 is connected to the ground GND.
  • the gate of the transistor Mos2 is connected to the input circuit 2, the source of the transistor Mos2 is electrically connected between the switch circuit S sm and the capacitor C sm , and the drain of the transistor Mos2 is connected to the ground GND.
  • the dynamic amplifier 240 controls the switch circuit S sp and the switch circuit S sm to open or close, and allows the first voltage signal V 1 and the second voltage signal V 2 to pass into the capacitor C sp and the capacitor C sm respectively. gate, allowing the dynamic amplifier 240 to realize the reset stage, the amplification stage and the sampling stage in sequence. Specifically:
  • the switch circuit S sp and the switch circuit S sm are closed, the transistor Mos1 is not connected to the first voltage signal V 1 , and the gate of the transistor Mos2 is not connected to the second voltage signal V 2 .
  • the two ends of the capacitor C sp and the capacitor C sm are reset to the set voltage level, which are recorded as the set voltage V sp and the set voltage V sm respectively.
  • the dynamic amplifier 240 can disconnect the switch circuit S sp and the switch circuit S sm , the transistor Mos1 passes the first voltage signal V 1 , and the gate of the transistor Mos2 passes the second voltage signal V 2 .
  • Current source Is provides current for the amplification stage.
  • the current source may be coupled to the capacitor C sp through the transistor Mos1, and the current source may be coupled to the capacitor C sm through the transistor Mos2.
  • the capacitor C sp and the capacitor C sm are discharged, and the voltage levels of the set voltage V sp and the set voltage V sm decrease.
  • the amplification stage ends.
  • the dynamic amplifier 240 obtains the voltages after the capacitor C sp and the capacitor C sm are discharged, which are recorded as the sampling voltage ⁇ V sp and the sampling voltage ⁇ V sm respectively.
  • the dynamic amplifier 240 determines the change edge between the time when the capacitor C sp is discharged and the voltage difference before and after the capacitor C sp is discharged, based on the voltage difference before and after the capacitor C sp and the capacitor C sm are discharged, and the time when the capacitor C sp and the capacitor C sm are discharged.
  • the dynamic amplifier 240 sends the timing signal Sp and the timing signal Sm to the time-to-digital converter 250.
  • Figure 6 is a simulation diagram between the discharge time of capacitor C and the voltage difference before and after discharge.
  • the dynamic amplifier 240 sends the RST signal to the switch circuit S sp and the switch circuit S sm , the switch circuit S sp and the switch circuit S sm are closed, and the dynamic amplifier 240 is in the reset stage.
  • the dynamic amplifier 240 sends the conv signal to the switch circuit S sp and the switch circuit S sm , the switch circuit S sp and the switch circuit S sm are disconnected, and the dynamic amplifier 240 is in the amplification stage.
  • the time-to-digital converter 250 can measure the time interval between the timing signal Sp and the timing signal Sm , and then convert the time information corresponding to the time interval. Convert it into a digital signal and obtain the LSB information.
  • a dynamic amplifier and a time-to-digital converter are added.
  • the dynamic amplifier converts the input residual voltage into a timing signal with time, and then the time-to-digital converter converts the The timing signal is converted into a digital signal to obtain LSB information, thereby obtaining higher resolution at the same time, that is, increasing the sampling speed of the SAR ADC and increasing the single-channel bandwidth of the SAR ADC.
  • the structures of the capacitor array 210, the comparator circuit 220 and the dynamic amplifier 240 are not limited to the one shown in Figure 3, and can be other structures. This application is only used as an example.
  • the number of the capacitor array 210, the comparator circuit 220, the dynamic amplifier 240 and the time-to-digital converter 250 in this application is not limited to the one in Figure 3, but can also be any number, and this application is not limited here.
  • N is a positive integer greater than 2.
  • Each capacitor array 210, comparator circuit 220, dynamic amplifier 240 and time-to-digital converter 250 may be connected according to the connection relationship shown in Figure 3.
  • the output end of each comparator circuit 220 is connected to the SAR logic circuit 230.
  • the SAR logic circuit 230 can be electrically connected to each capacitor array 210 to control each capacitor array 210.
  • the number of capacitor arrays 210 is one, and the number of comparator circuits 220, dynamic amplifiers 240, and time-to-digital converters 250 are all N, and N is a positive integer greater than 2.
  • the two input terminals of each comparator circuit 220 are connected in parallel to the two output terminals of the capacitor array 210 , and the output terminal of each comparator circuit 220 is connected to the SAR logic circuit 230 .
  • Each comparator circuit 220, dynamic amplifier 240 and time-to-digital converter 250 may be connected according to the connection relationship as shown in Figure 3.
  • Figure 7 is a schematic diagram showing the performance comparison between the two existing SAR ADCs and the SAR ADC protected by this application.
  • Figure 7 shows the resolution number and conversion times of three SAR ADCs under the same accuracy conditions.
  • Figure 7(a) shows the existing SAR ADC.
  • Figure 7(b) shows the existing SAR ADC.
  • the comparator does not detect the metastable state.
  • the metastable state is detected;
  • Figure 7(b) shows the SAR ADC protected by this application.
  • the comparator detects the metastable state, and the dynamic amplifier and time-to-digital converter quantize the time domain.
  • the SAR ADC protected by this application reduces the number of phase conversions of the SAR logic circuit 230 and can increase the conversion speed; compared with the SAR ADC shown in Figure 7(b), Getting higher resolution in the same time can increase conversion speed.
  • Table 1 shows the performance simulation results of three SAR ADCs. According to the results presented in Table 1, it can be seen that under the same number of effective bits, the maximum sampling rate of the SAR ADC protected by this application is nearly doubled.
  • FIG. 8 is a schematic flowchart of a method for improving the bandwidth of a SAR ADC provided in an embodiment of the present application. As shown in Figure 8, the specific process of implementing this method is as follows:
  • step S801 the comparator circuit generates a control signal according to the first analog signal and outputs it to the dynamic amplifier.
  • the capacitor array in the SAR ADC samples and holds the analog signal to obtain two voltage signals, which are the first output electrical signal and the second output electrical signal, and then the first output electrical signal and the second output electrical signal are respectively Inputs to the two inputs of the comparator circuit.
  • the capacitor array in the SAR ADC samples and holds the analog signal to obtain two voltage signals, which are the first output electrical signal and the second output electrical signal, and then the first output electrical signal and the second output electrical signal are respectively Inputs to the two inputs of the comparator circuit.
  • the comparator circuit in the SAR ADC determines whether it is in the MSB stage based on the timing of the internal clock signal clk. When the comparator circuit is determined to be in the MSB stage, it compares the received first output electrical signal and the second output electrical signal, and outputs a comparison signal.
  • the comparison signal output by the comparator circuit When the first output electrical signal is greater than the second output electrical signal, the comparison signal output by the comparator circuit is a logic high level or "1". When the first output electrical signal is smaller than the second output electrical signal, the comparison signal output by the comparator circuit is a logic low level or "0". When the first output electrical signal is equal to or approximately equal to the second output electrical signal, the comparator circuit compares the first output electrical signal with the second output electrical signal for a relatively long time. If the comparator circuit cannot give a judgment result within the specified time, the comparator enters a "metastable" state.
  • the comparator circuit After entering the metastable state, the comparator circuit locks the first output electrical signal and the second output electrical signal to provide a stable electrical signal for the dynamic amplifier.
  • the comparator circuit sends a comparison signal to the SAR logic circuit to stop the SAR logic circuit, which can reduce the number of phase transitions of the SAR logic circuit. Subsequently, the comparator circuit sends a reset signal to the dynamic amplifier to de-reset the dynamic amplifier.
  • a comparison signal to the SAR logic circuit to stop the SAR logic circuit, which can reduce the number of phase transitions of the SAR logic circuit.
  • the comparator circuit sends a reset signal to the dynamic amplifier to de-reset the dynamic amplifier.
  • Step S802 After receiving the control signal, the dynamic amplifier converts the first analog signal into a second analog signal.
  • This step is performed by the dynamic amplifier in the SAR ADC.
  • the dynamic amplifier After receiving the reset signal, the dynamic amplifier receives the first input electrical signal and the second input electrical signal output from the capacitor array, converts the first input electrical signal and the second input electrical signal into a timing signal with time, and then inputs it to in hour-to-digital converter.
  • the dynamic amplifier receives the first input electrical signal and the second input electrical signal output from the capacitor array, converts the first input electrical signal and the second input electrical signal into a timing signal with time, and then inputs it to in hour-to-digital converter.
  • Step S803 After receiving the second analog signal, the time-to-digital converter converts the second analog signal into a digital signal.
  • This step is performed by the hour-to-digital converter in the SAR ADC.
  • the time-to-digital converter can measure the time interval between the timing signals, and then convert the time information corresponding to the time interval into a digital signal to obtain the LSB information.
  • the dynamic amplifier is allowed to convert the first input electrical signal and the second input electrical signal into a timing signal with time, and then the time information is converted through a time-to-digital converter into a digital signal, obtain LSB information, and achieve higher resolution at the same time, that is, increase the sampling speed of the SAR ADC, and increase the single-channel bandwidth of the SAR ADC.
  • FIG. 9 is a schematic diagram of the frame of an electronic device provided in an embodiment of the present application.
  • the electronic device 900 includes an analog circuit 910, a clock circuit 920, a digital circuit 930 and at least one SAR ADC 200 recorded in Figures 2 to 8 and the above corresponding protection scheme.
  • the analog circuit 910 is used to generate analog signals and provide input electrical signals for the capacitor array 210 in the SAR ADC 200.
  • the analog circuit 910 may be an analog sensor, as well as a component or device including an analog sensor.
  • the clock circuit 920 is used to generate a clock signal and provide the clock signal clk for the comparator circuit 220 and the SAR logic circuit in the SAR ADC 200.
  • the clock circuit 920 may be an oscillator, etc., or a component including an oscillator.
  • the digital circuit 930 is used to process the digital signal output by the SAR ADC 200.
  • the digital circuit 930 can be various processors, transceivers, memories, etc.
  • the electronic device 900 includes the SAR ADC 200 recorded in Figures 2 to 8 and the above corresponding protection scheme, the electronic device 900 has all or at least some of the advantages of the SAR ADC 200.
  • power-consuming equipment can be set-top boxes, entertainment units, navigation equipment, communication equipment, fixed location data units, mobile location data units, global positioning system (GPS) equipment, mobile phones, cellular phones, smart phones, session Session initialization protocol (SIP) phone, tablet, phablet, server, computer, laptop, mobile computing device, wearable computing device (e.g., smart watch, health or fitness tracker, glasses, etc.), desktop computer , personal digital assistant (PDA), monitor, computer monitor, television, tuner, radio, satellite radio, music player, digital music player, portable music player, digital video player, video player , digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones and multi-rotor aircraft.
  • PDA personal digital assistant

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Abstract

本申请提供了一种模拟数字转换器、提高模拟数字转换器的带宽方法和电子设备，涉及信号处理技术领域。其中，在SAR ADC中新增动态放大器和时数转换器。动态放大器的第一输入端与电容阵列耦合，动态放大器的第二输入端与比较器耦合，动态放大器的输出端与时数转换器耦合。当比较器进入亚稳态后，动态放大器接收到比较器发送的控制信号，将输入的模拟电信号转换成带有时间的时序信号，然后通过时数转换器将时序信号转换成数字信号，实现在相同时间下，得到更高的分辨率，也即提高SAR ADC的转换速度，从而实现提高SAR ADC的单通道带宽。

Description

一种模拟数字转换器和提高模拟数字转换器的带宽方法
本申请要求于2022年03月31日提交中国国家知识产权局、申请号为202210333217.9、申请名称为“一种模拟数字转换器和提高模拟数字转换器的带宽方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及信号处理技术领域，尤其涉及一种模拟数字转换器、提高模拟数字转换器的带宽方法和电子设备。
背景技术
模拟数字转换器(analog-to-digital converter，ADC)是一种将模拟信号转换成数字信号的转换器。逐次逼近寄存器(successive approximation register，SAR)ADC是采样速率低于5Msps(每秒百万次采样)的中等至高分辨率应用的ADC。在每一次转换过程中，通过遍历所有的量化值并将其转化为模拟值，将输入信号与其逐一比较，最终得到要输出的数字信号。由于SAR ADC具有低功耗、小尺寸等特点，被广泛应用在各种电子设备中。但是，现有的SAR ADC的单通道带宽，也即奈奎斯特采样率的一半，已不能满足现有无线通信和光通信的大带宽/多模式的直采需求，所以如何提高SAR ADC的单通道带宽是目前亟需解决的问题。
发明内容
为了解决上述的问题，本申请的实施例中提供了一种模拟数字转换器、提高模拟数字转换器的带宽方法和电子设备，该模拟数字转换器在比较器进入亚稳态后，SAR逻辑电路停止工作，动态放大器获取残余电压后，将输入的残余电压转换成带有时间的时序信号，然后通过时数转换器将时间信息转换成数字信号，得到LSB信息，实现在相同时间下，得到更高的分辨率，也即提高SAR ADC的转换速度，从而实现提高SAR ADC的单通道带宽。
为此，本申请的实施例中采用如下技术方案：
第一方面，本申请实施例提供了一种模拟数字转换器，包括：模拟信号输入端、电容阵列、比较器电路、动态放大器和时数转换器；所述电容阵列耦合于所述模拟信号输入端和所述比较器电路的第一输出端之间；所述比较器电路的输入端与所述模拟信号输入端耦合，所述比较器电路的第一输出端与所述电容阵列的控制端耦合，所述比较器电路的第二输出端与所述动态放大器的控制端耦合，所述比较器电路用于根据所述模拟信号输入端接收的模拟信号产生比较信号，并通过所述第一输出端输出至所述电容阵列，以及用于根据所述模拟信号产生第一控制信号，并通过所述第二输出端输出至所述动态放大器，所述第一控制信号用于使能所述动态放大器工作，所述比较信号用于产生第一部分数字信号；所述动态放大器的输入端耦合于所述模拟信号输入端，所述动态放大器的输出端耦合于所述时数转换器的输入端；所述时数转换器的输出端用于输出第二部分数字信号。
在该实施方式中，在SAR ADC中新增动态放大器和时数转换器。动态放大器的第一输入端与电容阵列耦合，动态放大器的第二输入端与比较器耦合，动态放大器的输出端与时数转换器耦合。当比较器进入亚稳态后，动态放大器接收到比较器发送的控制信号，将输入的模 拟电信号转换成带有时间的时序信号，然后通过时数转换器将时序信号转换成数字信号，实现在相同时间下，得到更高的分辨率，也即提高SAR ADC的转换速度，从而实现提高SAR ADC的单通道带宽。
在一种实施方式中，还包括：逐次逼近寄存器型SAR逻辑电路，其中，所述SAR逻辑电路的输入端与所述比较器电路的第一输出端耦合，所述SAR逻辑电路的第一输出端与所述电容阵列的控制端耦合，所述SAR逻辑电路的第二输出端用于输出第二控制信号，所述SAR逻辑电路的第二输出端用于输出所述第一部分数字信号，所述第二控制信号用于使能所述电容阵列工作。
在一种实施方式中，所述比较器电路用于根据所述模拟信号输入端接收的模拟信号之间的差值是否小于设定阈值，以及在所述模拟信号之间的差值小于设定阈值时，产生所述第一控制信号。
在一种实施方式中，所述比较器电路包括时钟信号输入端、比较器、延时电路和触发器；所述比较器的第一输入端与所述模拟信号输入端耦合，所述比较器的第二输入端与所述时钟信号输入端耦合，所述比较器的输出端分别与所述SAR逻辑电路的输出端和所述触发器的第一输入端耦合，所述比较器用于根据所述时钟信号输入端输入的时钟信号和所述模拟信号输入端接收的模拟信号产生所述比较信号；所述延时电路耦合于所述时钟信号输入端和所述触发器的第二输入端之间；所述触发器的输入端耦合于所述动态放大器的控制端，所述触发器的输入端用于输出所述第一控制信号。
在一种实施方式中，所述比较器包括第一MOS管M1、第二MOS管M2、第一反相器、第二反相器和或逻辑器件，所述第一MOS管M1的源极和所述第二MOS管M2的源极分别与第一电源输入端耦合，所述第一MOS管M1的漏极和所述第二MOS管M2的漏极分别接地，所述第一MOS管M1的栅极和所述第二MOS管M2的栅极分别与所述模拟信号输入端耦合；所述第一反相器的输入端耦合于所述第一电源输入端与所述第一MOS管M1的源极之间，所述第二反相器的输入端耦合于所述第一电源输入端与所述第二MOS管M2的源极之间，所述第一反相器的输出端和所述第二反相器的输出端与所述或逻辑器件的输入端耦合，所述或逻辑器件的输出端用于输出所述比较信号。
在一种实施方式中，所述比较器还包括第三MOS管M7、第四MOS管M8、第五MOS管M9和第六MOS管M10；所述第三MOS管M7的源极耦合于所述第一电源输入端与所述第一反相器之间，所述第四MOS管M8的源极耦合于所述第一电源输入端与所述第二反相器之间；所述第五MOS管M9的源极与所述第一MOS管M1的漏极和所述第二MOS管M2的漏极耦合，所述第五MOS管M9的漏极接地；所述第六MOS管M10耦合于所述第一MOS管M1的源极和所述第二MOS管M2的源极之间；所述第三MOS管M7的栅极、所述第四MOS管M8的栅极、所述第五MOS管M9的栅极和所述第六MOS管M10的栅极分别与所述时钟信号输入端耦合。
在一种实施方式中，所述延时电路用于根据所述时钟信号输入端接收的时钟信号产生第二时钟信号，所述第二时钟信号为所述时钟信号输入端接收的时钟信号延迟设定时间的时钟信号。
在一种实施方式中，所述触发器用于根据所述比较信号和所述第二时钟信号产生所述第一控制信号。
在一种实施方式中，所述动态放大器包括第一开关电路、第二开关电路、第一MOS管、第二MOS管和电流源；所述第一开关电路的一端和所述第一开关电路的一端分别与第二电源输入端耦合，所述第一开关电路的另一端与第一MOS管的源极耦合，所述第二开关电路的另 一端与第二MOS管的源极耦合；所述第一MOS管的漏极和所述第二MOS管的漏极分别与所述电流源的一端耦合，所述电流源的另一端接地；所述第一MOS管的栅极和所述第二MOS管的栅极分别与所述模拟信号输入端耦合。
在一种实施方式中，所述动态放大器还包括第一电容和第二电容；所述第一电容的一端耦合于所述第一开关电路与第一MOS管之间，所述第一电容的另一端接地；所述第二电容的一端耦合于所述第二开关电路与第二MOS管之间，所述第二电容的另一端接地。
在一种实施方式中，所述动态放大器用于根据所述比较器电路发送的所述第一控制信号，让所述第一开关电路和所述第二开关电路断开。
第二方面，本申请实施例提供了一种模拟信号转数字信号的方法，包括：比较器电路根据第一模拟信号产生第一控制信号，并输出至动态放大器；所述动态放大器接收到所述第一控制信号后，将所述第一模拟信号转换成第二模拟信号，所述第二模拟信号携带有时间信息；时数转换器接收到所述第二模拟信号后，将所述第二模拟信号转换成数字信号。
在一种实施方式中，所述方法还包括：所述比较器电路接收时钟信号；所述比较器电路根据第一模拟信号产生第一控制信号，并输出至动态放大器，具体包括：所述比较器电路根据所述时钟信号和所述第一模拟信号产生所述第一控制信号。
在一种实施方式中，所述方法还包括：所述比较器电路根据所述第一模拟信号和所述时钟信号产生比较信号，并输出至逐次逼近寄存器型SAR逻辑电路；所述SAR逻辑电路接收到所述比较信号后，根据所述比较信号产生数字信号。
第三方面，本申请实施例提供了一种电子设备，包括：模拟电路，用于产生模拟信号；时钟电路，用于产生时钟信号；至少一个如第一方面各个可能实现的模拟数字转换器，用于接收所述模拟信号和所述时钟信号，将所述模拟信号转换成数字信号；数字电路，用于接收所述数字信号，进行处理。
附图说明
下面对实施例或现有技术描述中所需使用的附图作简单地介绍。
图1为现有的一种SAR ADC的结构示意图；
图2为本申请实施例中提供的一种SAR ADC的结构示意图；
图3为本申请实施例中提供的一种SAR ADC的具体结构示意图；
图4为本申请实施例中提供的一种比较器电路的结构示意图；
图5为本申请实施例中提供的一种比较器的结构示意图；
图6为电容C的放电时间与放电前后的电压差之间的仿真图；
图7为现有两种SAR ADC与本申请保护的SAR ADC各项性能对比示意图；
图8为本申请实施例中提供的一种提高SAR ADC的带宽方法的流程示意图；
图9为本申请实施例中提供的一种电子设备的框架示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。
本文中术语“和/或”，是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。本文中符号“/”表示关联对象是或者的关系，例如A/B表示A或者B。
本文中的说明书和权利要求书中的术语“第一”和“第二”等是用于区别不同的对象， 而不是用于描述对象的特定顺序。例如，第一响应消息和第二响应消息等是用于区别不同的响应消息，而不是用于描述响应消息的特定顺序。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
在本申请实施例的描述中，除非另有说明，“多个”的含义是指两个或者两个以上，例如，多个处理单元是指两个或者两个以上的处理单元等；多个元件是指两个或者两个以上的元件等。
图1为现有的一种SAR ADC的结构示意图。如图1所示，该SAR ADC主要包括电容阵列、比较器和SAR逻辑电路。
在实际应用过程中，电容阵列对输入的模拟信号V IN进行采样，并在完成采样后输出模拟输入电压V IN和模拟输出电压V OUT。模拟输入电压V OUTN和模拟输出电压V OUTP分别输入到比较器的正极输入端和负极输入端。比较器对输入的模拟输入电压V OUTN和模拟输出电压V OUTP进行比较，并生成一个比较信号V comp。如果模拟输入电压V OUTN大于模拟输出电压V OUTP，则比较器输出比较信号V comp为逻辑高电平或“1”；如果模拟输入电压V OUTN小于模拟输出电压V OUTP，则比较器输出比较信号V comp为逻辑低电平或“0”。
时钟信号clk作为使能信号，是控制比较器和SAR逻辑电路的输出更新。当时钟信号clk处于最高有效位(most significant bit，MSB)阶段时，比较器对输入的模拟输入电压V OUTN和模拟输出电压V OUTP进行比较，并输出比较信号V comp。SAR逻辑电路根据比较信号V comp完成一次置位后移至次高位，并准备进行下一次比较。以此类推，一直持续到时钟信号clk处于最低有效位(least significant bit，LSB)，完成转换。整个逐次比较过程结束后，SAR ADC完成了一次模拟量到数字量的转换，并输出该模拟量对应的数字码。
为了提高SAR ADC的单通道带宽，现有技术中提出了以下几种解决方案，具体为：
1、多比特同步比较技术。在SAR ADC中，设置2 N个比较器。SAR ADC在执行比较的过程中，由多个比较器同时进行比较。该方案中，SAR ADC的采样率达到N bit/cycle，可以减少SAR转换次数，实现提高SAR ADC的单通道带宽。但是，SAR ADC中设置2 N个比较器，增加了2 N-1个比较器，使得SAR ADC的耗电量比较大。
2、loop-unroll技术。在SAR ADC中，设置N个比较器。SAR ADC在执行比较的过程中，每个bit都使用一个比较器。比较器完成一次比较后，当前比较器不复位，直接开启下一个比较器，此过程可以节省等待比较器复位的时间，实现提高SAR ADC的单通道带宽。但是，随着技术的发展和生产工艺的提高，比较器复位的时间越来越短，所以采用该方案来提高SAR ADC的单通道带宽的效果并不明显。
3、相(phase)跳转技术。传统的SAR ADC为了实现N bit精度，需要经过N次转换phase。为了提高SAR ADC的比较时间，可以通过对其它条件进行判断，实现跳过多个phase，直接得到最终的量化结果，这种技术统称为phase跳转技术。以亚稳态判断技术为例，SAR ADC在某次比较中，比较器进入亚稳态后，可以认为输入的残余电压已经收敛到很小的范围内，已经得到量化结果，可以跳过剩余的phase。但是，如果亚稳态不出现或亚稳态判断错误时，则无法提高SAR ADC的比较时间，从而不能实现提高SAR ADC的单通道带宽。其中，亚稳态是指比较器两个输入端的电压非常接近，导致比较器需要很长的时间才能输出比较信号的状态。
为了解决现有SAR ADC中存在的问题，本申请实施例提供了一种新的SAR ADC。如图2 所示，该SAR ADC包括电容阵列210、比较器电路220、SAR逻辑电路230、动态放大器240和时数转换器250。新增的动态放大器240连接在比较器电路220的两个输入端上，且与比较器电路220并联。比较器电路220判断时钟信号clk是否处在MSB阶段，也即判断SAR ADC是否处在MSB阶段。当SAR ADC处在MSB阶段时，比较器电路220对两个输入端接收到残余电压进行比较，输出比较信号V comp。SAR逻辑电路230根据比较信号V comp完成一次置位后移至次高位，生成控制信号并发送给电容阵列210，准备进行下一次比较。SAR逻辑电路230还将比较信号V comp换成数字信号，并输出该模拟量对应的数字码。比较器电路220检测到两个输入端的残余电压之间差值比较小时，确定进入亚稳态。比较器电路220控制SAR逻辑电路230停止工作。比较器电路220向动态放大器240发送控制信号，让动态放大器240工作。
动态放大器240将输入的残余电压转换为带有时间的时序信号后，输入到时数转换器250中。时数转换器250接收到两个时序信号后，测量两个时序信号之间的时间间隔，并将时间间隔对应的时间信息转换成数字信号，得到LSB信息，输出该模拟量对应的数字码。本申请设计的SAR ADC中，在比较器进入亚稳态后，SAR逻辑电路停止工作，动态放大器获取残余电压后，将输入的残余电压转换成带有时间的时序信号，然后通过时数转换器将时序信号转换成数字信号，得到LSB信息，实现在相同时间下，得到更高的分辨率，也即提高SAR ADC的转换速度，从而实现提高SAR ADC的单通道带宽。
图3为本申请实施例中提供的一种SAR ADC的具体结构示意图。如图3所示，该SAR ADC包括电容阵列210、比较器电路220、SAR逻辑电路230、动态放大器240和时数转换器250。
电容阵列210对模拟信号进行采样保持，得到两个电压信号，分别为第一电压信号V 1和第二电压信号V 2，然后将第一电压信号V 1和第二电压信号V 2分别输入到比较器电路220的两个输入端。
如图3所示，本申请提供的一种电容阵列210，其包括两条输入通路，输入电路向比较器电路220的输入端输入电压信号。输入通路与负基准电压V refn电路或正基准电压V refp电路之间并联四个电容C。每个电容C与负基准电压V refn电路或正基准电压V refp电路之间电连接一个开关电路S。SAR逻辑电路230根据比较器电路220输出的比较信号V comp，生成控制信号，并将控制信号发送至电容阵列210中，实现控制各个开关电路，选择输入电路与负基准电压V refn电路电连接，或者输入电路与正基准电压V refp电路电连接。
电容阵列210的工作过程可以分为三个阶段，分别为采样阶段、保持阶段和电荷重分配阶段。具体实现过程如下：
1、采样阶段。电容阵列210可以控制开关电路S 11和开关电路S 21闭合，第一电压信号V 1和第二电压信号V 2直接输入到比较器电路220的两个输入端。在输入电路1中，SAR逻辑电路230可以控制开关电路S 12-S 15闭合，输入电路1与负基准电压V refn电路电连接。电容C 11-C 14所在的电路连通后，储存的电荷为Q 1＝C 1总×(V 1-V refn),C 1总＝C 11+C 12+C 13+C 14。在输入电路2中，SAR逻辑电路230可以控制开关电路S 22-S 25闭合，输入电路2与正基准电压V refp电路电连接，电容C 21-C 24所在的电路连通后，储存的电荷为Q 2＝C 2总×(V 2-V refp),C 2总＝C 21+C 22+C 23+C 24。
2、保持阶段。电容阵列210可以控制开关电路S 11和开关电路S 21闭合，第一电压信号V 1和第二电压信号V 2直接输入到比较器电路220的两个输入端。在输入电路1中，SAR逻辑电路230可以控制开关电路S 12-S 15断开，电容C 11-C 14储存的电荷为Q 1＝C 1总×V 1,C 1总＝C 11+C 12+C 13+C 14。在输入电路2中，SAR逻辑电路230可以控制开关电路S 22-S 25断开，电容C 21-C 24储存的电荷为Q 2＝C 1总×V 2,C 2总＝C 21+C 22+C 23+C 24。
3、电荷重分配阶段。电容阵列210可以在完成“采样阶段”和“保持阶段”后，根据比较 器电路220的比较信号V cmp＝V 1-V 2，对比较信号进行量化。具体为：在第一次比较过程中，如果比较信号V cmp1＞0，表明第一电压信号V 1大于第二电压信号V 2，则SAR逻辑电路230向各个开关电路发送高电平或“1”。此时，SAR逻辑电路230可以控制开关电路S 12-S 15断开，输入电路1与基准电压V ref电路断开，也即输入电路1上电容C 11-C 14接地GND；SAR逻辑电路230可以控制开关电路S 22-S 25闭合，输入电路2与负基准电压V refn电路电连接，也即输入电路2上电容C 21-C 24的另一端与负基准电压V refn电路电连接。如果比较信号V cmp1＜0，表明第一电压信号V 1小于第二电压信号V 2，则SAR逻辑电路230向各个开关电路发送低电平或“0”。此时，SAR逻辑电路230可以控制开关电路S 12-S 15闭合，输入电路1与正基准电压V refp电路电连接，也即输入电路1上电容C 11-C 14的另一端与正基准电压V refp电路电连接；SAR逻辑电路230可以控制开关电路S 22-S 25断开，输入电路2与基准电压V ref电路断开，也即输入电路1上电容C 21-C 24接地GND。
在完成第一次比较后，电荷会再次重新分配，比较器电路220输出的比较信号V cmp2是在第一次比较的比较信号V cmp1上增加或减小1/2个基准电压V ref，即增加或者基准电压V ref乘以该次参与量化的电容值占总电容比例大小。
第二次比较过程中，如果比较信号V cmp2＞0，表明第一电压信号V 1大于第二电压信号V 2，则SAR逻辑电路230向各个开关电路发送高电平或“1”。此时，SAR逻辑电路230可以控制开关电路S 13-S 15断开，输入电路1与基准电压V ref电路断开，也即输入电路1上电容C 12-C 14接地GND；SAR逻辑电路230可以控制开关电路S 23-S 25闭合，输入电路2与负基准电压V refn电路电连接，也即输入电路2上电容C 22-C 24的另一端与负基准电压V refn电路电连接。如果比较信号V cmp2＜0，表明第一电压信号V 1小于第二电压信号V 2，则SAR逻辑电路230向各个开关电路发送低电平或“0”。此时，SAR逻辑电路230可以控制开关电路S 13-S 15闭合，输入电路1与正基准电压V refp电路电连接，也即输入电路1上电容C 12-C 14的另一端与正基准电压V refp电路电连接；SAR逻辑电路230可以控制开关电路S 23-S 25断开，输入电路2与基准电压V ref电路断开，也即输入电路1上电容C 22-C 24接地GND。
在完成第二次比较后，电荷会再次重新分配，比较器电路220输出的比较信号V cmp3是在第二次比较的比较信号V cmp2上增加或减小1/4个基准电压V ref，依次类推，最后完成该级信号的量化。
比较器电路220在接收到时钟信号clk后，可以通过比较器电路220的时序的快慢来判断是否处在MSB阶段。比较器电路220确定时钟信号clk处在MSB阶段时，会对接收到的第一电压信号V 1和第二电压信号V 2进行比较，并输出比较信号V comp。
如图4所示，本申请提供了一种比较器电路220，该比较器电路220包括比较器221、延时模块222和触发器223。其中，比较器221的输入端1和输入端2分别与电容阵列210的两个输出端电连接，比较器221的一个输入端3与外接的时钟电路电连接，比较器221的输出端4与SAR逻辑电路230和触发器223的一个输入端7电连接。当外接的时钟电路输入的时钟信号处在MSB阶段，比较器221会对第一电压会对接收到的第一电压信号V 1和第二电压信号V 2进行比较，并输出比较信号V comp。
通常情况下，当第一电压信号V 1和第二电压信号V 2之间的关系为V 1-V 2＞0，比较器221输出的比较信号V comp为逻辑高电平或“1”。当第一电压信号V 1和第二电压信号V 2之间的关系为V 1-V 2＜0，比较器221输出的比较信号V comp为逻辑低电平或“0”。当第一电压信号V 1与第二电压信号V 2之间非常接近，也即第一电压信号V 1和第二电压信号V 2之间的关系为V 1-V 2≈0，比较器221比较第一电压信号V 1和第二电压信号V 2时，所需要的时间会比其他情况要长。如果比较器221在规定的时间内不能给出判断结果，则比较器221进入“亚稳态”状态。另外，比较 器电路220在进入亚稳态后，锁定第一电压信号V 1和第二电压信号V 2，实现固定高比特位信息，以便为动态放大器240提供稳定的电信号。
示例性地，如图5所示，该比较器221中，MOS管M1的源极和MOS管M2的源极分别与供电电源连接，MOS管M1的漏极和MOS管M2的漏极分别与MOS管M9的源极连接，MOS管M9的漏极接地；晶体管M1和晶体管M2的栅极分别与电容阵列210的两个输出端电连接，用于接收第一电压信号V 1和第二电压信号V 2。第一反相器的输入端耦合于供电电源与MOS管M1的源极之间，第二反相器的输入端耦合于供电电源与MOS管M2的源极之间。第一反相器的输出端和第二反相器的输出端与或逻辑器件的输入端耦合，或逻辑器件的输出端用于输出所述比较信号。MOS管M7的源极耦合于供电电源与第一反相器之间，MOS管M8的源极耦合于供电电源与第二反相器之间；MOS管M10耦合于MOS管M1的源极和MOS管M2的源极之间；MOS管M7的栅极、MOS管M8的栅极、MOS管M9的栅极和MOS管M10的栅极分别与外接的时钟电路连接。比较器221接收到的第一电压信号V 1和第二电压信号V 2之间差值大于设定阈值时，输入到或逻辑器件中的电信号Von和电信号Vop中有一个为高电平或“1”，或逻辑器件输出的比较信号为高电平或“1”；比较器221接收到的第一电压信号V 1和第二电压信号V 2之间差值不大于设定阈值时，也即两个电压信号比较接近，输入到或逻辑器件中的电信号Von和电信号Vop均为低电平或“0”，或逻辑器件输出的比较信号为低电平或“0”。
延时模块222一般是由一个或多个反相器组成，其输入端5与外接的时钟电路电连接，输出端6与触发器223的输入端8电连接，用于将时钟信号clk延迟设定时间，然后输入到触发器223中。
触发器223是一种可以存储电路状态的电子元件。触发器223的电路结构一般是由逻辑门组合而成，用于处理输入、输出信号和时钟频率之间的相互影响。本申请中，触发器223输入端7和输入端8接收到比较信号V comp和延迟设定时间的时钟信号clk后，将比较信号V comp和延迟设定时间的时钟信号clk进行上升沿比较，判断比较器221输出的比较信号V comp在触发时刻是否有效。当触发时刻输出信号有效值，表明比较器221未进入亚稳态，触发器223输出高电平；当触发时刻输出信号无效，表明比较器221进入亚稳态，触发器223输出低电平。触发器223输出端9输出的信号，也即控制信号，输入到动态放大器240中。
当比较器221处于亚稳态时，比较器221输入到SAR逻辑电路230中的比较信号V comp可以让SAR逻辑电路230停止工作。SAR逻辑电路230在比较器221进入亚稳态后停止工作，可以减少转换的phase次数，等效理解为提高了SAR逻辑电路230的转换速度。触发器223向动态放大器240发送控制信号可以让动态放大器240解复位。
在比较器电路220进入亚稳态的时间段中，SAR ADC 200没有数字信号输出。为了提高SAR ADC 200的数字信号输出，SAR ADC 200对比较器电路220进入亚稳态的时间段的输入电压在时域上进行量化，获取LSB信息，提高SAR ADC 200的采样速度，实现提高SAR ADC 200的单通道带宽。
SAR逻辑电路230用于接收外接的时钟电路输入的时钟信号clk和比较器220输入的比较信号V comp，产生控制信号，并将控制信号输入到电容阵列210中，控制电容阵列210中的各个开关电路导通或断开，实现控制电容阵列210进入采样阶段、保持阶段和电荷重分配阶段。本申请中，SAR逻辑电路230在接收到比较器220输入的比较信号V comp后，还可以将比较信号V comp转换成数字信号，并输出该比较信号对应的数字码，实现将模拟信号转成数字信号。由于本申请采用的SAR逻辑电路230是常规的SAR逻辑电路，在此就不再详细说明了。
动态放大器240在接收到控制信号后，接收电容阵列210输出的第一电压信号V 1和第二电 压信号V 2，将第一电压信号V 1和第二电压信号V 2转换成带有时间的时序信号后，输入到时数转换器250中。
如图3所示，本申请提供的一种动态放大器240，其包括两个金属-氧化物半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor，MOSFET)(Mos1,Mos2)、两个电容(C sp，C sm)和两个开关电路(S sp，S sm)。开关电路S sp与开关电路S sm之间串联。开关电路S sp的另一端与电容C sp电连接后，接地GND。开关电路S sm的另一端与电容C sm电连接后，接地GND。晶体管Mos1的栅极连接在输入电路1上，晶体管Mos1的源极电连接在开关电路S sp与电容C sp之间，晶体管Mos1的漏极接地GND。晶体管Mos2的栅极连接在输入电路2上，晶体管Mos2的源极电连接在开关电路S sm与电容C sm之间，晶体管Mos2的漏极接地GND。
动态放大器240在接收到控制信号后，控制开关电路S sp与开关电路S sm断开或闭合，以及让第一电压信号V 1和第二电压信号V 2分别通入电容C sp和电容C sm的栅极，让动态放大器240依次实现重置阶段、放大阶段和取样阶段。具体为：
在重置阶段，开关电路S sp与开关电路S sm闭合，晶体管Mos1未通入第一电压信号V 1，晶体管Mos2栅极未通入和第二电压信号V 2。电容C sp和电容C sm两端被重置为设定电压电平，分别记为设定电压V sp和设定电压V sm。
在放大阶段，动态放大器240可以让开关电路S sp与开关电路S sm断开，晶体管Mos1通入第一电压信号V 1，晶体管Mos2栅极通入第二电压信号V 2。电流源Is为放大阶段提供电流。电流源可以通过晶体管Mos1耦合至电容C sp，电流源可以通过晶体管Mos2耦合至电容C sm。电容C sp和电容C sm放电，设定电压V sp和设定电压V sm的电压电平下降。当设定电压V sp和设定电压V sm的共模电压达到设定共模电压差时，放大阶段结束。
在放大阶段结束后，进入取样阶段。动态放大器240获取电容C sp和电容C sm放电后的电压，分别记为取样电压△V sp和取样电压△V sm。动态放大器240根据电容C sp和电容C sm放电前后的电压差、电容C sp和电容C sm放电的时间，确定电容C sp放电的时间与电容C sp放电前后的电压差之间的变化沿，也即时序信号S p，以及电容C sm放电的时间与电容C sm放电前后的电压差之间的变化沿，也即时序信号S m。随后，动态放大器240将时序信号S p和时序信号S m发送时数转换器250。
图6为电容C的放电时间与放电前后的电压差之间的仿真图。如图6所示，当动态放大器240向开关电路S sp和开关电路S sm发送RST信号时，开关电路S sp和开关电路S sm闭合，动态放大器240处在重置阶段。当动态放大器240向开关电路S sp和开关电路S sm发送conv信号时，开关电路S sp和开关电路S sm断开，动态放大器240处在放大阶段。此时，电容C放电的时间与电容C放电前后的电压差之间呈线性关系。
时数转换器250在接收到动态放大器240发送的时序信号S p和时序信号S m后，可以测量时序信号S p与时序信号S m之间的时间间隔，然后将该时间间隔对应的时间信息转换成数字信号，得到LSB信息。
本申请保护的SAR ADC中，新增动态放大器和时数转换器，当比较器进入亚稳态后，动态放大器将输入的残余电压转换成带有时间的时序信号，然后通过时数转换器将时序信号转换成数字信号，得到LSB信息，实现在相同时间下，得到更高的分辨率，也即提高SAR ADC的采样速度，实现提高SAR ADC的单通道带宽。
需要说明的是，本申请保护的SAR ADC中，电容阵列210、比较器电路220和动态放大器240的结构不仅限于图3所示的一种，可以为其它结构，本申请在此仅作为示例。本申请中的电容阵列210、比较器电路220、动态放大器240和时数转换器250的数量也不仅限图3中的一个， 还可以任意数量，本申请在此也不作限定。
一个示例中，当电容阵列210、比较器电路220、动态放大器240和时数转换器250的数量均为N个，N为大于2的正整数。每一个电容阵列210、比较器电路220、动态放大器240和时数转换器250可以按照如图3所示的连接关系进行连接。每个比较器电路220的输出端均连接到SAR逻辑电路230上，SAR逻辑电路230可以与每个电容阵列210电连接，实现对每个电容阵列210的控制。
一个示例中，电容阵列210数量为一个，比较器电路220、动态放大器240和时数转换器250的数量均为N个，N为大于2的正整数。每一个比较器电路220的两个输入端并联在电容阵列210的两个输出端，每一个比较器电路220的输出端均连接到SAR逻辑电路230上。每一个比较器电路220、动态放大器240和时数转换器250可以按照如图3所示的连接关系进行连接。
图7为现有两种SAR ADC与本申请保护的SAR ADC各项性能对比示意图。图7所示，为三种SAR ADC在相同精度条件下，分辨率数和转换次数。其中，图7(a)为现有的SAR ADC，该SAR ADC工作过程中，比较器没有检测亚稳态；图7(b)为现有的SAR ADC，该SAR ADC工作过程中，比较器检测了亚稳态；图7(b)为本申请保护的SAR ADC，该SAR ADC工作过程中，比较器检测亚稳态，动态放大器和时数转换器对时域进行量化。
本申请保护的SAR ADC，相比较图7(a)所示的SAR ADC，减少了SAR逻辑电路230转换phase的次数，可以提高转换速度；相比较图7(b)所示的SAR ADC，实现在相同时间内得到更高的分辨率，可以提高转换速度。
表一为三种SAR ADC各项性能仿真结果。根据表一呈现的结果可以看出，在相同有效比特数下，本申请保护的SAR ADC的最高采样速率提高了将近一倍。
表一三种SAR ADC各项性能仿真结果
Figure PCTCN2023070648-appb-000001
图8为本申请实施例中提供的一种提高SAR ADC的带宽方法的流程示意图。如图8所示，该方法实现具体过程如下：
步骤S801，比较器电路根据第一模拟信号产生控制信号，并输出至动态放大器。
在此之前，SAR ADC中电容阵列对模拟信号进行采样保持，得到两个电压信号，分别为第一输出电信号和第二输出电信号，然后将第一输出电信号和第二输出电信号分别输入到比较器电路的两个输入端。具体实现过程可以参考图3和图3对应的描述内容，在此不再详细说 明了。
SAR ADC中的比较器电路根据内部的时钟信号clk的时序的快慢来判断是否处在MSB阶段。比较器电路确定处在MSB阶段时，会对接收到的第一输出电信号和第二输出电信号进行比较，并输出比较信号。
当第一输出电信号大于第二输出电信号时，比较器电路输出的比较信号为逻辑高电平或“1”。当第一输出电信号小于第二输出电信号时，比较器电路输出的比较信号为逻辑低电平或“0”。当第一输出电信号等于或近似等于第二输出电信号时，比较器电路比较第一输出电信号与第二输出电信号的时间比较长。如果比较器电路在规定的时间内不能给出判断结果，则比较器进入“亚稳态”状态。
比较器电路在进入亚稳态后，锁定第一输出电信号和第二输出电信号，以便为动态放大器提供稳定的电信号。比较器电路向SAR逻辑电路发送比较信号，让SAR逻辑电路停止工作，可以减少SAR逻辑电路转换phase的次数。随后，比较器电路再向动态放大器发送复位信号，让动态放大器解复位。具体实现过程可以参考图4-图5和图4-图5对应的描述内容，在此不再详细说明了。
步骤S802，动态放大器接收到控制信号后，将第一模拟信号转换成第二模拟信号。
该步骤是由SAR ADC中的动态放大器执行。动态放大器在接收到复位信号后，接收电容阵列输出的第一输入电信号和第二输入电信号，将第一输入电信号和第二输入电信号转换成带有时间的时序信号后，输入到时数转换器中。具体实现过程可以参考图3和图3对应的描述内容，在此不再详细说明了。
步骤S803，时数转换器接收到第二模拟信号后，将第二模拟信号转换成数字信号。
该步骤是由SAR ADC中的时数转换器执行。时数转换器在接收到动态放大器发送的时序信号后，可以测量时序信号之间的时间间隔，然后将该时间间隔对应的时间信息转换成数字信号，得到LSB信息。
本申请保护的方法中，在比较器进入亚稳态后，让动态放大器将第一输入电信号和第二输入电信号转换成带有时间的时序信号，然后通过时数转换器将时间信息转换成数字信号，得到LSB信息，实现在相同时间下，得到更高的分辨率，也即提高SAR ADC的采样速度，实现提高SAR ADC的单通道带宽。
图9为本申请实施例中提供的一种电子设备的框架示意图。如图9所示，该电子设备900包括模拟电路910、时钟电路920、数字电路930和至少一个图2-图8和上述对应保护方案中记载的SAR ADC 200。
模拟电路910用于产生模拟信号，为SAR ADC 200中的电容阵列210提供输入电信号。其中，模拟电路910可以为模拟传感器，以及包括有模拟传感器的组件或设备。
时钟电路920用于产生时钟信号，为SAR ADC 200中的比较器电路220和SAR逻辑电路提供时钟信号clk。其中，时钟电路920可以为振荡器等，以及包括有振荡器的组件。
数字电路930用于对SAR ADC 200输出的数字信号进行处理。其中，数字电路930可以为各种处理器、收发器、存储器等等。
由于电子设备900包括有如图2-图8和上述对应保护方案中记载的SAR ADC 200，因此该电子设备900具有该SAR ADC 200的所有或至少部分优点。其中，用电设备可以为机顶盒、娱乐单元、导航设备、通信设备、固定位置数据单元、移动位置数据单元、全球定位系统(global positioning system，GPS)设备、移动电话、蜂窝电话、智能电话、会话发起协议(session  initialization protocol，SIP)电话、平板电脑、平板手机、服务器、计算机、便携式计算机、移动计算设备、可穿戴计算设备(例如，智能手表、健康或健身跟踪器、眼镜等)、台式计算机、个人数字助理(personal digital assistant，PDA)、显示器、计算机显示器、电视机、调谐器、收音机、卫星广播、音乐播放器、数字音乐播放器、便携式音乐播放器、数字视频播放器、视频播放器、数字视频光盘(digital video disc，DVD)播放器、便携式数字视频播放器、汽车、车辆组件、航空电子系统、无人机和多旋翼飞行器。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以适合的方式结合。
最后说明的是：以上实施例仅用以说明本申请的技术方案，而对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例中所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或替换，并不使相应技术方案的本质脱离本申请各实施例中技术方案的精神和范围。

Claims (15)

  1. 一种模拟数字转换器，其特征在于，包括：模拟信号输入端、电容阵列、比较器电路、动态放大器和时数转换器；
    所述电容阵列耦合于所述模拟信号输入端和所述比较器电路的第一输出端之间；
    所述比较器电路的输入端与所述模拟信号输入端耦合，所述比较器电路的第一输出端与所述电容阵列的控制端耦合，所述比较器电路的第二输出端与所述动态放大器的控制端耦合，所述比较器电路用于根据所述模拟信号输入端接收的模拟信号产生比较信号，并通过所述第一输出端输出至所述电容阵列，以及用于根据所述模拟信号产生第一控制信号，并通过所述第二输出端输出至所述动态放大器，所述第一控制信号用于使能所述动态放大器工作，所述比较信号用于产生第一部分数字信号；
    所述动态放大器的输入端耦合于所述模拟信号输入端，所述动态放大器的输出端耦合于所述时数转换器的输入端；
    所述时数转换器的输出端用于输出第二部分数字信号。
  2. 根据权利要求1所述的模拟数字转换器，其特征在于，还包括：逐次逼近寄存器型SAR逻辑电路，其中，所述SAR逻辑电路的输入端与所述比较器电路的第一输出端耦合，所述SAR逻辑电路的第一输出端与所述电容阵列的控制端耦合，所述SAR逻辑电路的第二输出端用于输出第二控制信号，所述SAR逻辑电路的第二输出端用于输出所述第一部分数字信号，所述第二控制信号用于使能所述电容阵列工作。
  3. 根据权利要求1或2所述的模拟数字转换器，其特征在于，所述比较器电路用于根据所述模拟信号输入端接收的模拟信号之间的差值是否小于设定阈值，以及在所述模拟信号之间的差值小于设定阈值时，产生所述第一控制信号。
  4. 根据权利要求1-3任意一项所述的模拟数字转换器，其特征在于，所述比较器电路包括时钟信号输入端、比较器、延时电路和触发器；
    所述比较器的第一输入端与所述模拟信号输入端耦合，所述比较器的第二输入端与所述时钟信号输入端耦合，所述比较器的输出端分别与所述SAR逻辑电路的输出端和所述触发器的第一输入端耦合，所述比较器用于根据所述时钟信号输入端输入的时钟信号和所述模拟信号输入端接收的模拟信号产生所述比较信号；
    所述延时电路耦合于所述时钟信号输入端和所述触发器的第二输入端之间；
    所述触发器的输入端耦合于所述动态放大器的控制端，所述触发器的输入端用于输出所述第一控制信号。
  5. 根据权利要求4所述的模拟数字转换器，其特征在于，所述比较器包括第一MOS管M1、第二MOS管M2、第一反相器、第二反相器和或逻辑器件，
    所述第一MOS管M1的源极和所述第二MOS管M2的源极分别与第一电源输入端耦合，所述第一MOS管M1的漏极和所述第二MOS管M2的漏极分别接地，所述第一MOS管M1的栅极和所述第二MOS管M2的栅极分别与所述模拟信号输入端耦合；
    所述第一反相器的输入端耦合于所述第一电源输入端与所述第一MOS管M1的源极之间，所述第二反相器的输入端耦合于所述第一电源输入端与所述第二MOS管M2的源极之间，所述第一反相器的输出端和所述第二反相器的输出端与所述或逻辑器件的输入端耦合，所述或逻辑器件的输出端用于输出所述比较信号。
  6. 根据权利要求5所述的模拟数字转换器，其特征在于，所述比较器还包括第三MOS管M7、第四MOS管M8、第五MOS管M9和第六MOS管M10；
    所述第三MOS管M7的源极耦合于所述第一电源输入端与所述第一反相器之间，所述第四MOS管M8的源极耦合于所述第一电源输入端与所述第二反相器之间；
    所述第五MOS管M9的源极与所述第一MOS管M1的漏极和所述第二MOS管M2的漏极耦合，所述第五MOS管M9的漏极接地；所述第六MOS管M10耦合于所述第一MOS管M1的源极和所述第二MOS管M2的源极之间；
    所述第三MOS管M7的栅极、所述第四MOS管M8的栅极、所述第五MOS管M9的栅极和所述第六MOS管M10的栅极分别与所述时钟信号输入端耦合。
  7. 根据权利要求4-6任意一项所述的模拟数字转换器，其特征在于，所述延时电路用于根据所述时钟信号输入端接收的时钟信号产生第二时钟信号，所述第二时钟信号为所述时钟信号输入端接收的时钟信号延迟设定时间的时钟信号。
  8. 根据权利要求4-7任意一项所述的模拟数字转换器，其特征在于，所述触发器用于根据所述比较信号和所述第二时钟信号产生所述第一控制信号。
  9. 根据权利要求1-8任意一项所述的模拟数字转换器，其特征在于，所述动态放大器包括第一开关电路、第二开关电路、第一MOS管、第二MOS管和电流源；
    所述第一开关电路的一端和所述第一开关电路的一端分别与第二电源输入端耦合，所述第一开关电路的另一端与第一MOS管的源极耦合，所述第二开关电路的另一端与第二MOS管的源极耦合；
    所述第一MOS管的漏极和所述第二MOS管的漏极分别与所述电流源的一端耦合，所述电流源的另一端接地；所述第一MOS管的栅极和所述第二MOS管的栅极分别与所述模拟信号输入端耦合。
  10. 根据权利要求9所述的模拟数字转换器，其特征在于，所述动态放大器还包括第一电容和第二电容；
    所述第一电容的一端耦合于所述第一开关电路与第一MOS管之间，所述第一电容的另一端接地；所述第二电容的一端耦合于所述第二开关电路与第二MOS管之间，所述第二电容的另一端接地。
  11. 根据权利要求9或10所述的模拟数字转换器，其特征在于，所述动态放大器用于根据所述比较器电路发送的所述第一控制信号，让所述第一开关电路和所述第二开关电路断开。
  12. 一种模拟信号转数字信号的方法，其特征在于，包括：
    比较器电路根据第一模拟信号产生第一控制信号，并输出至动态放大器；
    所述动态放大器接收到所述第一控制信号后，将所述第一模拟信号转换成第二模拟信号，所述第二模拟信号携带有时间信息；
    时数转换器接收到所述第二模拟信号后，将所述第二模拟信号转换成数字信号。
  13. 根据权利要求12所述的方法，其特征在于，所述方法还包括：
    所述比较器电路接收时钟信号；
    所述比较器电路根据第一模拟信号产生第一控制信号，并输出至动态放大器，具体包括：
    所述比较器电路根据所述时钟信号和所述第一模拟信号产生所述第一控制信号。
  14. 根据权利要求13所述的方法，其特征在于，所述方法还包括：
    所述比较器电路根据所述第一模拟信号和所述时钟信号产生比较信号，并输出至逐次逼近寄存器型SAR逻辑电路；
    所述SAR逻辑电路接收到所述比较信号后，根据所述比较信号产生数字信号。
  15. 一种电子设备，其特征在于，包括：
    模拟电路，用于产生模拟信号；
    时钟电路，用于产生时钟信号；
    至少一个如权利要求1-11所述的模拟数字转换器，用于接收所述模拟信号和所述时钟信号，将所述模拟信号转换成数字信号；
    数字电路，用于接收所述数字信号，进行处理。
PCT/CN2023/070648 2022-03-31 2023-01-05 一种模拟数字转换器和提高模拟数字转换器的带宽方法 WO2023185192A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060176197A1 (en) * 2005-02-07 2006-08-10 Mcneill John A Calibratable analog-to-digital converter system
CN107070455A (zh) * 2015-12-04 2017-08-18 台湾积体电路制造股份有限公司 混合逐次逼近型寄存器模数转换器及执行模数转换的方法
CN109861691A (zh) * 2019-01-02 2019-06-07 西安电子科技大学 基于延迟锁相环的两步式混合结构sar tdc的模数转换器电路
CN214756299U (zh) * 2021-04-21 2021-11-16 江苏信息职业技术学院 一种12位差分sar adc

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060176197A1 (en) * 2005-02-07 2006-08-10 Mcneill John A Calibratable analog-to-digital converter system
CN107070455A (zh) * 2015-12-04 2017-08-18 台湾积体电路制造股份有限公司 混合逐次逼近型寄存器模数转换器及执行模数转换的方法
CN109861691A (zh) * 2019-01-02 2019-06-07 西安电子科技大学 基于延迟锁相环的两步式混合结构sar tdc的模数转换器电路
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