WO2023173614A1 - 硅通孔测试结构以及硅通孔短路测试方法 - Google Patents

硅通孔测试结构以及硅通孔短路测试方法 Download PDF

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Publication number
WO2023173614A1
WO2023173614A1 PCT/CN2022/099939 CN2022099939W WO2023173614A1 WO 2023173614 A1 WO2023173614 A1 WO 2023173614A1 CN 2022099939 W CN2022099939 W CN 2022099939W WO 2023173614 A1 WO2023173614 A1 WO 2023173614A1
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silicon via
group
voltage
via group
groups
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PCT/CN2022/099939
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English (en)
French (fr)
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张家瑞
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长鑫存储技术有限公司
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Priority to US18/168,085 priority Critical patent/US20230290690A1/en
Publication of WO2023173614A1 publication Critical patent/WO2023173614A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

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  • the present disclosure relates to the technical field of integrated circuits, and specifically to a through silicon via test structure and a through silicon via short circuit test method.
  • TSV Through Silicon Via
  • the purpose of the present disclosure is to provide a through silicon via testing structure and a through silicon via short circuit testing method to overcome, at least to a certain extent, the problem of being unable to test through silicon via short circuits due to limitations and defects in related technologies.
  • a through-silicon via test structure including: a plurality of through-silicon via groups, the through-silicon via group including a plurality of electrically connected through-silicon vias; and a plurality of the through-silicon vias.
  • a power supply circuit connected to the group, the power circuit being used to provide a first voltage or a second voltage to each of the through silicon via groups, the first voltage and the second voltage being different; a control circuit connected to the power supply circuit, and provides a first control signal and a second control signal to the power circuit, the power circuit outputs the first voltage to at least one through silicon via group according to the first control signal, the power circuit according to the The second control signal outputs the second voltage to at least one through silicon via group; a readout circuit, electrically connected to the plurality of through silicon via groups, is configured to provide the first control signal in the control circuit and After receiving the second control signal, electrical signals on a plurality of through silicon via groups are read.
  • the power supply circuit includes a plurality of sub-power supply circuits, each of the sub-power supply circuits is connected to one of the through silicon via groups, and the sub-power supply circuit is configured to connect to the through silicon via group.
  • the through silicon via group provides the first voltage or the second voltage.
  • control circuit provides the first control signal or the second control signal to the sub-power supply circuit respectively, and the first control signal is configured to control the sub-power supply circuit.
  • the power circuit outputs a first voltage
  • the second control signal is configured to control the sub-power circuit to output a second voltage.
  • the sub-power supply circuit includes a pull-up module and a pull-down module, the pull-up module outputs the first voltage according to the first control signal, and the pull-down module outputs the first voltage according to the first control signal.
  • the second control signal outputs the second voltage.
  • the pull-up module includes a first transistor, a first electrode of the first transistor receives the first voltage, and a gate of the first transistor receives the first voltage.
  • control signal the second electrode of the first transistor is connected to the through silicon via group;
  • the pull-down module includes a second transistor and a third transistor, the first electrode of the second transistor is connected to the through silicon via group, the second pole of the second transistor is connected to the first pole of the third transistor, the gate of the second transistor receives the second control signal; the second pole of the third transistor receives the A second voltage, the gate of the third transistor receives a bias voltage.
  • the first voltage is greater than the second voltage, and the second voltage is less than or equal to zero potential.
  • the readout circuit includes a shift register, a plurality of input terminals of the shift register are respectively connected to one of the through silicon via groups, and a control terminal of the shift register is connected to A first read control signal, the first read control signal is used to control the shift register to sequentially read the electrical signals on the through silicon via group.
  • the readout circuit includes a plurality of switch units, a first end of each switch unit is connected to one of the through silicon via groups, and a second end outputs the through silicon via.
  • the control end is connected to a second read control signal, and a plurality of the second read control signals turn on the plurality of switch units in sequence to read the electrical signals on the through silicon via group.
  • a through silicon via short circuit testing method including: determining a first through silicon via group and at least one adjacent through silicon via group among multiple through silicon via groups. A second through silicon via group; providing a first voltage to the first through silicon via group, and providing a second voltage to the second through silicon via group; sequentially reading the first through silicon via group and the an electrical signal on the second through silicon via group; determining whether there is a short circuit between the first through silicon via group and the second through silicon via group based on the electrical signal.
  • the first voltage is greater than the second voltage, and the second voltage is less than or equal to zero potential.
  • the step of determining whether there is a short circuit between the first through silicon via group and the second through silicon via group based on the electrical signal further includes: determining whether the second through silicon via group is short-circuited. Whether the electrical signal of the through silicon via group includes an electrical signal of logic level 1, and whether there is a gap between the first through silicon via group and the second through silicon via group based on the electrical signal of the second through silicon via group.
  • the electrical signal of the second through silicon via group includes an electrical signal of logic level 1, there is a short circuit between the first through silicon via group and the second through silicon via group; if the second through silicon via group The electrical signal of the via group does not include an electrical signal of logic level 1, and the first through silicon via group and the second through silicon via group are not short-circuited.
  • the determination of whether the electrical signal of the second through silicon via group includes an electrical signal of logic level 1 is determined based on the electrical signal of the second through silicon via group.
  • the step of determining whether there is a short circuit between the first through silicon via group and the second through silicon via group includes: determining that the electrical signal is the second through silicon via group with logic level 1, thereby determining that the electrical signal is connected to the first through silicon via group. The position of the second through silicon via group where the hole group is short-circuited.
  • a first through silicon via group and at least a second through silicon via group adjacent to the first through silicon via group are determined among the plurality of through silicon via groups.
  • the method includes: dividing multiple through-silicon via groups into multiple test groups, each of the test groups including at least two adjacent through-silicon via groups; setting one through-silicon via group in each of the test groups to In the first through silicon via group, the other through silicon via groups in the test group are all set as the second through silicon via group, and each of the second through silicon via group is connected to the third through silicon via group.
  • a TSV group is adjacent.
  • providing a first voltage to the first through silicon via group and providing a second voltage to the second through silicon via group includes: testing a plurality of the test groups.
  • the first through silicon via group provides the first voltage
  • the second through silicon via group in a plurality of test groups is provided with the second voltage at the same time.
  • the sequentially reading the electrical signals on the first through silicon via group and the second through silicon via group includes: reading the first through silicon via group in each test group. An electrical signal on a through silicon via group and the second through silicon via group.
  • Embodiments of the present disclosure provide different first voltages and second voltages to adjacent through silicon via groups and perform readout detection on the through silicon via groups, thereby quickly and effectively detecting through silicon via groups with short circuit problems. Even TSV groups with open circuit issues were detected.
  • FIG. 1 is a schematic structural diagram of a through silicon via test structure in an exemplary embodiment of the present disclosure.
  • Figure 2 is a schematic diagram of a power supply circuit in one embodiment of the present disclosure.
  • Figure 3 is a schematic diagram of a sub-power supply circuit according to an embodiment of the present disclosure.
  • 4A and 4B are schematic diagrams of readout circuits in embodiments of the present disclosure.
  • FIG. 5 is a flow chart of a through silicon via short circuit testing method in an exemplary embodiment of the present disclosure.
  • 6A and 6B are schematic top views of through silicon via groups in embodiments of the present disclosure.
  • Figure 7 is a schematic diagram of short circuit detection of a through silicon via group in an embodiment of the present disclosure.
  • FIG. 8 is a flowchart of step S54 in one embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of the connection relationship of the readout circuit in another embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments.
  • the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous specific details are provided to provide a thorough understanding of embodiments of the disclosure.
  • those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details described, or other methods, components, devices, steps, etc. may be adopted.
  • well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the disclosure.
  • FIG. 1 is a schematic structural diagram of a through silicon via test structure in an exemplary embodiment of the present disclosure.
  • the through silicon via test structure 100 may include:
  • the power circuit 1 is used to provide a first voltage V1 or a second voltage V2 to each through silicon via group A.
  • the first voltage V1 Different from the second voltage V2;
  • the control circuit 2 is connected to the power circuit 1 and provides the first control signal CON1 and the second control signal CON1 to the power circuit 1, so that the power circuit 1 outputs a first voltage to at least one through silicon via group A according to the first control signal CON1.
  • V1 output the second voltage V2 to at least one through silicon via group A according to the second control signal CON2;
  • the readout circuit 3 is electrically connected to the plurality of through silicon via groups A, and is configured to read the electrical signals on the plurality of through silicon via groups A after the control circuit 2 provides the first control signal CON1 and the second control signal CON2.
  • the through silicon via group A includes a plurality of electrically connected through silicon vias TSV.
  • the through silicon vias TSV are arranged in multiple chip layers (Die1 ⁇ Die4), and the control circuit 2 is arranged on the outermost layer. In the chip layer (Die0).
  • the through silicon via TSVs in each through silicon via group A are aligned, and multiple chip layers are vertically bonded through multiple through silicon via groups A to form a highly integrated stacked package.
  • the stacking form implemented by the through silicon via group A may also be, for example, wafer-to-wafer, chip-to-wafer, or chip-to-chip, and the bonding method may include, for example, direct Cu-Cu bonding. , bonding, direct fusion, welding, etc., this disclosure does not place special restrictions on this.
  • Through silicon via group A can be used to transmit signals between chips of different layers.
  • the number of through silicon via TSVs in each through silicon via group A is not exactly the same. What is shown in Figure 1 is only an example. In actual applications, the number of through silicon via TSVs in different through silicon via groups A may be more than or equal to one.
  • the power circuit 1 and the readout circuit 3 are electrically connected to the through silicon via group A, either by directly connecting the through silicon via TSV located on the outermost side of the stacked chip, or by connecting each through silicon via through preset and produced leads. Any conductive part in group A.
  • the diameter of the through silicon via is usually 1um to 50um, the depth is usually 10um to 150um, and the aspect ratio is 3 to 5 or even higher.
  • process defects such as slurry residue, particle contamination, copper particles, stress caused by cracking, and edge fragments may occasionally exist, which in turn may cause problems between adjacent through-silicon vias. short circuit.
  • Figure 2 is a schematic diagram of a power supply circuit in one embodiment of the present disclosure.
  • the power circuit 1 includes a plurality of sub-power circuits 11, each sub-power circuit 11 is connected to a through silicon via group A, and the sub-power circuit 11 is configured to provide silicon
  • the via group A provides the first voltage V1 or the second voltage V2.
  • the control circuit 2 provides the first control signal CON1 or the second control signal CON2 to the sub-power circuit 11 respectively.
  • the first control signal CON1 is configured to control the sub-power circuit 11 to output the first voltage V1
  • the second control signal CON2 is configured to control the sub-power circuit 11 to output the first voltage V1. It is configured to control the sub-power supply circuit 11 to output the second voltage V2.
  • Figure 3 is a schematic diagram of a sub-power supply circuit according to an embodiment of the present disclosure.
  • the sub-power circuit 11 includes a pull-up module 111 and a pull-down module 112.
  • the pull-up module 111 is configured to output the first voltage V1 according to the first control signal CON1
  • the pull-down module 112 is Configured to output the second voltage V2 according to the second control signal CON2.
  • the pull-up module 111 includes a first transistor M1 , a first electrode of the first transistor M1 receives the first voltage V1 , and a gate of the first transistor M1 receives the first control signal CON1 .
  • the second electrode of M1 is connected to the through silicon via group A;
  • the pull-down module 112 includes a second transistor M2 and a third transistor M3.
  • the first electrode of the second transistor M2 is connected to the through silicon via group A, and the second electrode of the second transistor M2 is connected to the through silicon via group A.
  • the first electrode of the third transistor M3 and the gate of the second transistor M2 receive the second control signal CON2; the second electrode of the third transistor M3 receives the second voltage V2, and the gate of the third transistor M3 receives the bias voltage Vref.
  • the first voltage V1 is greater than the second voltage V2, and the second voltage V2 is less than or equal to zero potential.
  • the first voltage V1 is, for example, the power supply voltage Vcc
  • the second voltage V2 is, for example, GND.
  • the second voltage V2 may also be a negative voltage, as long as it can be clearly distinguished from the first voltage V1.
  • the bias voltage Vref can be used to control the rate at which the sub-power circuit 11 outputs the second voltage V2, and to improve the pull-down capability of the pull-down module 112.
  • each through silicon via group A can be set to the first voltage V1 or the second voltage V2, thereby forming a variety of voltage distribution forms, and measuring each through silicon via in a variety of scenarios.
  • V1 or the second voltage V2 For the short circuit situation between groups, please refer to the following embodiment shown in Figure 5 for detailed methods.
  • 4A and 4B are schematic diagrams of readout circuits in embodiments of the present disclosure.
  • the readout circuit 3 includes a shift register 31. Multiple input terminals of the shift register 31 are respectively connected to a through silicon via group A, and the control terminal is connected to the first read control signal. RCN1, the first read control signal RCN1 is used to control the shift register to sequentially read the electrical signals on the through silicon via group.
  • the first read control signal RCN1 may come from the control circuit 2 .
  • the readout circuit 3 includes a plurality of switch units 32 , the first end of each switch unit 32 is connected to a through silicon via group A, and the second end outputs the through silicon via group A.
  • the second read control signal RCN2i may come from the control circuit 2.
  • the control circuit 2 can execute the through silicon via short circuit test method provided by the embodiment of the present disclosure, control the voltage state of each through silicon via group A, obtain the read data on the through silicon via group A, and determine multiple through silicon via groups A. Is there a short circuit between them?
  • FIG. 5 is a flow chart of a through silicon via short circuit testing method in an exemplary embodiment of the present disclosure.
  • method 500 may include:
  • Step S51 determine a first through silicon via group and at least one second through silicon via group adjacent to the first through silicon via group among the plurality of through silicon via groups;
  • Step S52 providing a first voltage to the first through silicon via group and a second voltage to the second through silicon via group;
  • Step S53 sequentially read the electrical signals on the first through silicon via group and the second through silicon via group;
  • Step S54 Determine whether there is a short circuit between the first through silicon via group and the second through silicon via group based on the electrical signal.
  • step S51 may include: dividing the plurality of through silicon via groups into multiple test groups, each test group including at least two adjacent through silicon via groups, and the through silicon vias in each test group The number of groups is not exactly the same; one TSV group in each test group is set as the first TSV group, and the other TSV groups in the test group are set as the second TSV group. The two TSV groups are adjacent to the first TSV group.
  • step S52 may include: providing a first voltage to the first through silicon via group in the plurality of test groups, and simultaneously providing a second voltage to the second through silicon via group in the plurality of test groups.
  • Step S53 may include: reading electrical signals on the first through silicon via group and the second through silicon via group in each test group; determining test data corresponding to each test group according to the logic level of each electrical signal. .
  • 6A and 6B are schematic top views of through silicon via groups in embodiments of the present disclosure.
  • each through silicon via group A is arranged in an array in a top view parallel to the chip.
  • each test group 600 has one first TSV group 61 , three second TSV groups 62 , and The two TSV groups 62 are adjacent to the first TSV group 61 .
  • a test data group is formed according to the test group.
  • 8 through silicon via groups are a test group 601, and each test group 601 has 1 first through silicon via group 61 and 7 second through silicon via groups 62.
  • the second through silicon via groups 62 are adjacent to the first through silicon via group 61 , and the seven second through silicon via groups 62 surround the first through silicon via group 61 .
  • a test data group is formed according to the test group.
  • different test groups may have the same TSV group, that is, one TSV group may become a member of different test groups to change Comprehensive measurement of short circuit paths between every two adjacent TSV groups.
  • Figure 7 is a schematic diagram of short circuit detection of a through silicon via group in an embodiment of the present disclosure.
  • the first control signal CON1 is input to the sub-power circuit 11 connected to the first TSV group 61
  • the second control signal CON2 is input to the sub-power circuit 11 connected to the second TSV group 62 , so that the first TSV group 61
  • the first voltage V1 is connected
  • the second through silicon via group 62 is connected to the second voltage V2.
  • a second TSV located on the left side of the first TSV group 61 Taking hole group 62 as an example, after the first through silicon via group 61 is charged to a high voltage (first voltage), before reading, the first through silicon via group 61 communicates with the low voltage second through silicon via through a short circuit path.
  • the group 62 is turned on, causing the voltage of the second through silicon via group 62 to rise.
  • the electrical signal of the first through silicon via group 61 and the electrical signal of the second through silicon via group 62 on the left are both electrical signals of logic level 1. Therefore, whether there is a short circuit between the first through silicon via group 61 and its adjacent second through silicon via group 62 can be determined based on the electrical signal in step S54.
  • the first voltage V1 in order to increase the leakage speed between the first through silicon via group 61 and the second through silicon via group 62 and enhance the short circuit effect, the first voltage V1 can be increased, that is, “strong 1”.
  • Methods for increasing the first voltage V1 include, for example, increasing the power supply voltage through a charge pump, or connecting the pull-up units of each sub-power circuit 11 to a higher power supply voltage, which is not particularly limited in this disclosure.
  • the specific value of the first voltage V1 can be set according to the overall requirements of the integrated circuit, and should be as high as possible while meeting the safety requirements, so as to create a larger voltage between the first through silicon via group 61 and the second through silicon via group 62.
  • the potential difference increases the leakage speed between the first through silicon via group 61 and the second through silicon via group 62, enhances the short circuit effect, and improves detection efficiency.
  • Step S53 and step S54 will be described taking the embodiment shown in FIG. 6A and FIG. 6B as an example.
  • the read data of a test group should have 1 bit of data as 1 and other bits of data as 0.
  • the read data of a test group there may be multiple data being 1 or all data being 0. In short, it is completely different from the normal situation.
  • the test group it can be determined by judging the readout data of a test group whether the test group is a preset normal condition corresponding to the position of the first through silicon via group. Furthermore, when the readout data of the test group is not equal to the normal condition, When the data is obtained, it is determined that there is a short circuit path between the first through silicon via group 61 and the second through silicon via group 62 in the test group.
  • the reading sequence can be set to first read the first through silicon via group 61 and then read the three second through silicon via groups 62 , then the data corresponding to the test group should be equal to 0001 (binary ). If the final data corresponding to the test group is not 0001, it can be determined that there is a short circuit path between the first through silicon via group 61 and the second through silicon via group 62 in the test group.
  • the read data should be 0010. If the read data is erroneous data such as 0011, 1010, 0110, etc., it can be judged that there is a short circuit path in the test group. Even when the read data is abnormal data such as 1110 and 0111, it is determined that there is more than one short-circuit path in the test group.
  • Comparing the read data with the preset data can more accurately determine the number and location of short-circuit paths in a test group, and then locate the faulty TSV group.
  • a more convenient method can also be used to determine whether there is a short-circuit path in a test group.
  • FIG. 8 is a flowchart of step S54 in one embodiment of the present disclosure.
  • step S54 further includes:
  • Step S541 determine whether the electrical signal of the second TSV group includes an electrical signal of logic level 1, and determine whether there is an electrical signal between the first TSV group and the second TSV group based on the electrical signal of the second TSV group. short circuit;
  • Step S542 if the electrical signal of the second through silicon via group includes an electrical signal of logic level 1, determine that there is a short circuit between the first through silicon via group and the second through silicon via group;
  • Step S543 If the electrical signal of the second TSV group does not include an electrical signal of logic level 1, it is determined that the first TSV group and the second TSV group are not short-circuited.
  • the embodiment shown in Figure 8 is a specific example of logical judgment.
  • the first voltage V1 is high, if the first through silicon via group 61 and its adjacent second through silicon via group 62 are short-circuited, the voltage after the short circuit is logic level 1.
  • the third through silicon via group 61 is measured. Whether there is a logic level 1 in the two silicon through hole groups 62 can more accurately detect whether there is a short circuit phenomenon.
  • a second through silicon via group whose electrical signal is a logic level 1 may also be determined in step S541, thereby determining a second through silicon via group that is short-circuited with the first through silicon via group. Location of TSV groups.
  • the data corresponding to the multiple second through silicon via groups 62 should be equal to 0. If there is a value equal to If the data bit is 1, then it can be determined according to the corresponding relationship between the data bit and the second through silicon via group 62 which second through silicon via group 62 or which second through silicon via group 62 and first through silicon via group 61 are short circuited. .
  • two of the plurality of second TSV groups 62 are short-circuited, and one of the second TSV groups 62 is short-circuited to the first TSV group 61 , but not the two second TSV groups 62 are short-circuited.
  • the two TSV groups 62 are all short-circuited with the first TSV group 61 .
  • transposition measurement can be performed on a test group.
  • a test group includes four TSV groups a, b, c, and d.
  • TSV group a is set to the first TSV group 61
  • TSV group b is set to
  • c, and d are set as the second through silicon via group 62
  • the first set of data is measured.
  • the through silicon via group c that is diagonal to the through silicon via group a is set as the first through silicon via group 61
  • the through silicon via groups a, b, and d are set as the second through silicon via group 61.
  • Hole group 62, the second set of data was measured.
  • the specific short-circuit path can be determined based on the first set of values, the second set of values and the reading order of each through silicon via group.
  • test strategy for a test group can also be adjusted according to the adjacent conditions of each through silicon via group. Those skilled in the art can set it by themselves according to the actual situation. By measuring a test group using multiple methods, the location of the short-circuit path can be accurately and comprehensively located, thereby providing technical support for subsequent repairs or alternative solutions.
  • the testing principle of the embodiment shown in Figure 6B is the same.
  • the embodiment shown in FIG. 6B can read the data of 8 second through silicon via groups 62 at one time, which can greatly improve the testing efficiency compared with the embodiment shown in FIG. 6A .
  • the test solution corresponding to the embodiment shown in Figure 6B will also be more complex.
  • test group After measuring the short circuit within a test group, you can also change the test group for testing, or test multiple test groups at the same time to improve testing efficiency. In some embodiments, different test groups may also share the same TSV group to avoid missing short circuits between TSV groups of different test groups.
  • the multiple through silicon via groups are arranged in an array in the embodiment of the present disclosure, in other scenarios, the multiple through silicon via groups may also appear irregularly according to the actual conditions of the circuit and chip (such as the distribution of free areas). Arrangement. At this time, the division of test groups can be determined based on the distance between each through silicon via group (for example, two through silicon via groups whose distance is less than the preset value are determined as adjacent through silicon via groups). Each test group The number of TSV groups in is not necessarily the same, and different test groups may also include the same TSV group, and this disclosure does not place special restrictions on this.
  • FIG. 9 is a schematic diagram of the connection relationship of the readout circuit in another embodiment of the present disclosure.
  • the readout circuit 3 can be connected to the other end of the TSV group that is not connected to the power circuit 1 , furthermore, the readout circuit 3 can determine whether the first voltage V1 is transmitted from one end of the first through silicon via group to the other end while reading the voltage at the end of the first through silicon via group, and then determine whether the first through silicon via Whether there is a circuit break in the group. Finally, the judgment results of open circuits and short circuits are combined to further locate which TSV groups have short circuits. By setting different TSV groups as the first TSV group in turn, the short circuit and open circuit test of all TSV groups can be completed.
  • the embodiments of the present disclosure use a simple circuit to apply a first voltage or a second voltage to adjacent through silicon via groups to create a voltage difference, thereby causing a short circuit phenomenon, and finally locate the short circuit position based on the read data.
  • a simple circuit to apply a first voltage or a second voltage to adjacent through silicon via groups to create a voltage difference, thereby causing a short circuit phenomenon, and finally locate the short circuit position based on the read data.
  • Embodiments of the present disclosure provide different first voltages and second voltages to adjacent through silicon via groups and perform readout detection on the through silicon via groups, thereby quickly and effectively detecting through silicon via groups with short circuit problems. Even TSV groups with open circuit issues were detected.

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Abstract

一种硅通孔测试结构以及硅通孔短路测试方法。硅通孔测试结构（100）包括：多个硅通孔组（A），硅通孔组（A）包括多个电连接的硅通孔（TSV）；与多个硅通孔组（A）连接的电源电路（1），电源电路（1）用于向每个硅通孔组（A）提供第一电压（V1）或第二电压（V2），第一电压（V1）和第二电压（V2）不同；控制电路（2），连接电源电路（1），并向电源电路（1）提供第一控制信号（CON1）和第二控制信号（CON2），电源电路（1）根据第一控制信号（CON1）对至少一个硅通孔组（A）输出第一电压（V1），电源电路（1）根据第二控制信号（CON2）对至少一个硅通孔组（A）输出第二电压（V2）；读出电路（3），电连接多个硅通孔组（A），被配置为在控制电路（2）提供第一控制信号（CON1）和第二控制信号（CON2）后，读取多个硅通孔组（A）上的电信号。可以检测到出现短路的硅通孔组，提高集成电路的产品良率。

Description

硅通孔测试结构以及硅通孔短路测试方法
交叉引用
本公开要求于2022年03月14日提交的申请号为202210247673.1、名称为“硅通孔测试结构以及硅通孔短路测试方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及集成电路技术领域，具体而言，涉及一种硅通孔测试结构以及硅通孔短路测试方法。
背景技术
硅通孔(Through Silicon Via，TSV)技术是三维集成电路中堆叠芯片实现互连的一种新的技术解决方案。TSV能够使芯片在三维方向堆叠的密度最大、芯片之间的互连线最短、外形尺寸最小，并且大大改善芯片速度和低功耗的性能，成为目前电子封装技术中最引人注目的一种技术。TSV作为多个裸片(Die)之间的信号传输通道，其可靠性直接影响整个芯片的良品率。因此，TSV的检测是集成电路检测中重要的一环。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种硅通孔测试结构以及硅通孔短路测试方法，用于至少在一定程度上克服由于相关技术的限制和缺陷而导致的无法测试硅通孔短路的问题。
根据本公开的第一方面，提供一种硅通孔测试结构，包括：多个硅通孔组，所述硅通孔组包括多个电连接的硅通孔；与多个所述硅通孔组连接的电源电路，所述电源电路用于向每个所述硅通孔组提供第一电压或第二电压，所述第一电压和所述第二电压不同；控制电路，连接所述电源电路，并向所述电源电路提供第一控制信号和第二控制信号，所述电源电路根据所述第一控制信号对至少一个硅通孔组输出所述第一电压，所述电源电路根据所述第二控制信号对至少一个硅通孔组输出所述第二电压；读出电路，电连接所述多个硅通孔组，被配置为在所述控制电路提供所述第一控制信号和所述第二控制信号后，读取多个所述硅通孔组上的电信号。
在本公开的一个示例性实施例中，所述电源电路包括多个子电源电路，每一所述子电源电路分别对应连接一个所述硅通孔组，所述子电源电路被配置为向所述硅通孔组提供所述第一电压或所述第二电压。
在本公开的一个示例性实施例中，所述控制电路分别向所述子电源电路提供所述第一 控制信号或所述第二控制信号，所述第一控制信号被配置为控制所述子电源电路输出第一电压，所述第二控制信号被配置为控制所述子电源电路输出第二电压。
在本公开的一个示例性实施例中，所述子电源电路包括上拉模块和下拉模块，所述上拉模块根据所述第一控制信号输出所述第一电压，所述下拉模块根据所述第二控制信号输出所述第二电压。
在本公开的一个示例性实施例中，所述上拉模块包括第一晶体管，所述第一晶体管的第一极接收所述第一电压，所述第一晶体管的栅极接收所述第一控制信号，所述第一晶体管的第二极连接所述硅通孔组；所述下拉模块包括第二晶体管和第三晶体管，所述第二晶体管的第一极连接所述所述硅通孔组，所述第二晶体管的第二极连接所述第三晶体管的第一极，所述第二晶体管的栅极接收所述第二控制信号；所述第三晶体管的第二极接收所述第二电压，所述第三晶体管的栅极接收偏置电压。
在本公开的一个示例性实施例中，所述第一电压大于所述第二电压，所述第二电压小于等于零电位。
在本公开的一个示例性实施例中，所述读出电路包括移位寄存器，所述移位寄存器的多个输入端分别连接一个所述硅通孔组，所述移位寄存器的控制端连接第一读取控制信号，所述第一读取控制信号用于控制所述移位寄存器依次读取所述硅通孔组上的电信号。
在本公开的一个示例性实施例中，所述读出电路包括多个开关单元，每个所述开关单元的第一端连接一个所述硅通孔组，第二端输出所述硅通孔组上的电信号，控制端连接一个第二读取控制信号，多个所述第二读取控制信号依次分别打开所述多个开关单元，读出所述硅通孔组上的电信号。
根据本公开的第二方面，提供一种硅通孔短路测试方法，包括：在多个硅通孔组中确定一个第一硅通孔组和与所述第一硅通孔组相邻的至少一个第二硅通孔组；向所述第一硅通孔组提供第一电压，向所述第二硅通孔组提供第二电压；依次读取所述第一硅通孔组和所述第二硅通孔组上的电信号；根据所述电信号判断所述第一硅通孔组和所述第二硅通孔组之间是否短路。
在本公开的一个示例性实施例中，所述第一电压大于所述第二电压，所述第二电压小于等于零电位。
在本公开的一个示例性实施例中，所述根据所述电信号判断所述第一硅通孔组和所述第二硅通孔组之间是否短路的步骤还包括：判断所述第二硅通孔组的电信号是否包括逻辑电平1的电信号，根据所述第二硅通孔组的电信号判断所述第一硅通孔组和所述第二硅通孔组之间是否短路；如果所述第二硅通孔组的电信号包括逻辑电平1的电信号，所述第一硅通孔组和所述第二硅通孔组之间短路；如果所述第二硅通孔组的电信号不包括逻辑电平1的电信号，所述第一硅通孔组和所述第二硅通孔组未发生短路。
在本公开的一个示例性实施例中，所述判断所述第二硅通孔组的电信号是否包括逻辑电平1的电信号，根据所述第二硅通孔组的电信号判断所述第一硅通孔组和所述第二硅通 孔组之间是否短路的步骤包括：确定电信号为逻辑电平1的所述第二硅通孔组，从而确定与所述第一硅通孔组短路的所述第二硅通孔组的位置。
在本公开的一个示例性实施例中，所述在多个硅通孔组中确定一个第一硅通孔组和与所述第一硅通孔组相邻的至少一个第二硅通孔组包括：将多个硅通孔组分为多个测试组，每个所述测试组包括至少两个相邻的硅通孔组；将每个所述测试组中的一个硅通孔组设置为所述第一硅通孔组，将所述测试组中的其他所述硅通孔组均设置为所述第二硅通孔组，每个所述第二硅通孔组均与所述第一硅通孔组相邻。
在本公开的一个示例性实施例中，所述向所述第一硅通孔组提供第一电压，向所述第二硅通孔组提供第二电压包括：对多个所述测试组中的所述第一硅通孔组提供所述第一电压，同时对多个所述测试组中的所述第二硅通孔组提供所述第二电压。
在本公开的一个示例性实施例中，所述依次读取所述第一硅通孔组和所述第二硅通孔组上的电信号包括：读取每个测试组中的所述第一硅通孔组和所述第二硅通孔组上的电信号。
本公开实施例通过对相邻的硅通孔组提供不同的第一电压和第二电压，并对硅通孔组进行读出检测，可以快速有效地检测出存在短路问题的硅通孔组，甚至检测到存在断路问题的硅通孔组。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开示例性实施例中硅通孔测试结构的结构示意图。
图2是本公开一个实施例中电源电路的示意图。
图3是本公开一个实施例中子电源电路的示意图。
图4A和图4B是本公开实施例中读出电路的示意图。
图5是本公开示例性实施例中的硅通孔短路测试方法的流程图。
图6A和图6B是本公开实施例中硅通孔组的俯视示意图。
图7是本公开实施例中硅通孔组短路检测的原理图。
图8是本公开一个实施例中步骤S54的流程图。
图9是本公开另一个实施例中读出电路的连接关系示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
下面结合附图对本公开示例实施方式进行详细说明。
图1是本公开示例性实施例中硅通孔测试结构的结构示意图。
参考图1，硅通孔测试结构100可以包括：
多个硅通孔组A以及与多个硅通孔组A连接的电源电路1，电源电路1用于向每个硅通孔组A提供第一电压V1或第二电压V2，第一电压V1和第二电压V2不同；
控制电路2，连接电源电路1，并向电源电路1提供第一控制信号CON1和第二控制信号CON1，以使电源电路1根据第一控制信号CON1对至少一个硅通孔组A输出第一电压V1，根据第二控制信号CON2对至少一个硅通孔组A输出第二电压V2；
读出电路3，电连接多个硅通孔组A，被配置为在控制电路2提供第一控制信号CON1和第二控制信号CON2后，读取多个硅通孔组A上的电信号。
在图1所示实施例中，硅通孔组A包括多个电连接的硅通孔TSV，硅通孔TSV分设在多个芯片层(Die1～Die4)中，控制电路2设置在最外侧的芯片层(Die0)中。每个硅通孔组A中的硅通孔TSV对齐，多个芯片层通过多个硅通孔组A的垂直键合以形成高集成度的堆叠封装。在本公开的其他实施例中，由硅通孔组A实现的堆叠形式还例如可以为晶圆到晶圆、芯片到晶圆或芯片到芯片，键合方式例如可以包括直接Cu-Cu键合、粘接、直接熔合、焊接等等，本公开对此不作特殊限制。
硅通孔组A可以用于在不同层的芯片之间传输信号，根据信号起始位置的不同，每个硅通孔组A中的硅通孔TSV数量不完全相同。图1所示仅为示例，在实际应用中，不同的硅通孔组A中的硅通孔TSV的数量可以为多于等于一个。
电源电路1和读出电路3与硅通孔组A电连接的方式，既可以为直接连接位于堆叠芯片最外侧的硅通孔TSV，也可以为通过预先设置和制作的引线连接各硅通孔组A中的任意导电部分。
硅通孔的直径通常在1um到50um、深度通常在10um到150um，纵宽比在3到5甚至更高，一粒芯片上通常存在大约在几百甚至上千的硅通孔，即封装好后通常存在几百甚至上千的硅通孔组。在硅通孔的钻孔、填充、键合过程中，偶尔会存在研磨浆残留、微粒污染、铜微粒、开裂引起的应力、边缘碎片等工艺缺陷，进而导致相邻的硅通孔之间发生短路。
图2是本公开一个实施例中电源电路的示意图。
参考图2，在本公开的一个示例性实施例中，电源电路1包括多个子电源电路11，每一子电源电路11分别对应连接一个硅通孔组A，子电源电路11被配置为向硅通孔组A提供第一电压V1或第二电压V2。对应地，控制电路2分别向子电源电路11提供第一控制信号CON1或第二控制信号CON2，第一控制信号CON1被配置为控制子电源电路11输出第一电压V1，第二控制信号CON2被配置为控制子电源电路11输出第二电压V2。
图3是本公开一个实施例中子电源电路的示意图。
参考图3，在本公开的一个实施例中，子电源电路11包括上拉模块111和下拉模块112，上拉模块111被配置为根据第一控制信号CON1输出第一电压V1，下拉模块112被配置为根据第二控制信号CON2输出第二电压V2。
在图3所示实施例中，上拉模块111包括第一晶体管M1，第一晶体管M1的第一极接收第一电压V1，第一晶体管M1的栅极接收第一控制信号CON1，第一晶体管M1的第二极连接硅通孔组A；下拉模块112包括第二晶体管M2和第三晶体管M3，第二晶体管M2的第一极连接硅通孔组A，第二晶体管M2的第二极连接第三晶体管M3的第一极，第二晶体管M2的栅极接收第二控制信号CON2；第三晶体管M3的第二极接收第二电压V2，第三晶体管M3的栅极接收偏置电压Vref。
在本公开的一个示例性实施例中，第一电压V1大于第二电压V2，且第二电压V2小于等于零电位。在图3所示实施例中，第一电压V1例如为电源电压Vcc，第二电压V2例如为GND。在其他实施例中，第二电压V2也可以为负电压，只要能够被识别出与第一电压V1的明显区别即可。
偏置电压Vref可以用于控制子电源电路11输出第二电压V2的速率，以及提高下拉模块112的下拉能力。
通过图3所示实施例的电路，每个硅通孔组A均可以被设置为第一电压V1或第二电压V2，进而构成多种电压分布形态，在多种场景下测量各硅通孔组之间的短路情况，详细方法请见后续图5所示实施例。
图4A和图4B是本公开实施例中读出电路的示意图。
参考图4A，在本公开的一个实施例中，读出电路3包括移位寄存器31，移位寄存器31的多个输入端分别连接一个硅通孔组A，控制端连接第一读取控制信号RCN1，第一读取控制信号RCN1用于控制移位寄存器依次读取硅通孔组上的电信号。第一读取控制信号RCN1可以来自控制电路2。
参考图4B，在本公开的另一个实施例中，读出电路3包括多个开关单元32，每个开关单元32的第一端连接一个硅通孔组A，第二端输出硅通孔组A上的电信号，控制端连接一个第二读取控制信号RCN2i(i＝1、2、3、……)，多个第二读取控制信号RCN2i依次分别打开多个开关单元32，读出硅通孔组A上的电信号。第二读取控制信号RCN2i可以来自控制电路2。
控制电路2可以执行本公开实施例提供的硅通孔短路测试方法，控制各硅通孔组A的电压状态，并获取硅通孔组A上的读取数据，判断多个硅通孔组A之间是否存在短路现象。
图5是本公开示例性实施例中的硅通孔短路测试方法的流程图。
参考图5，方法500可以包括：
步骤S51，在多个硅通孔组中确定一个第一硅通孔组和与所述第一硅通孔组相邻的至少一个第二硅通孔组；
步骤S52，向第一硅通孔组提供第一电压，向第二硅通孔组提供第二电压；
步骤S53，依次读取第一硅通孔组和第二硅通孔组上的电信号；
步骤S54，根据电信号判断第一硅通孔组和第二硅通孔组之间是否短路。
在一个实施例中，步骤S51可以包括：将多个硅通孔组分为多个测试组，每个测试组包括至少两个相邻的硅通孔组，每个测试组中的硅通孔组数量不完全相同；将每个测试组中的一个硅通孔组设置为第一硅通孔组，将测试组中的其他硅通孔组均设置为第二硅通孔组，每个第二硅通孔组均与第一硅通孔组相邻。
此时，步骤S52可以包括：对多个测试组中的第一硅通孔组提供第一电压，同时对多个测试组中的第二硅通孔组提供第二电压。步骤S53可以包括：读取每个测试组中的第一硅通孔组和第二硅通孔组上的电信号；根据每个电信号的逻辑电平确定与每个测试组对应的测试数据。
图6A和图6B是本公开实施例中硅通孔组的俯视示意图。
在图6A和图6B所示实施例中，各硅通孔组A在平行于芯片的视角上的俯视示意图上，呈阵列排布。
参考图6A，在一个实施例中，4个硅通孔组为一个测试组600，每个测试组600中具有1个第一硅通孔组61，3个第二硅通孔组62，第二硅通孔组62均与第一硅通孔组61相邻。读取硅通孔组数据时，按照测试组形成测试数据组。
参考图6B，在另一个实施例中，8个硅通孔组为一个测试组601，每个测试组601中具有1个第一硅通孔组61，7个第二硅通孔组62，第二硅通孔组62均与第一硅通孔组61相邻，7个第二硅通孔组62环绕第一硅通孔组61。读取硅通孔组数据时，按照测试组形成测试数据组。
在图6A和图6B所示实施例，以及本公开其他实施例中，不同测试组之间可以具有相同的硅通孔组，即一个硅通孔组可以成为不同测试组中的成员，以更全面地测量每两个 相邻硅通孔组之间的短路路径。
图7是本公开实施例中硅通孔组短路检测的原理图。
参考图7，以图6A所示实施例中4个硅通孔组为一个检测组为例。对第一硅通孔组61连接的子电源电路11输入第一控制信号CON1，对第二硅通孔组62连接的子电源电路11输入第二控制信号CON2，使得第一硅通孔组61连接第一电压V1，第二硅通孔组62连接第二电压V2。
假设第一硅通孔组61与其相邻的第二硅通孔组62之间存在短路路径(如图中箭头所示)，以位于第一硅通孔组61左侧的一个第二硅通孔组62为例，则第一硅通孔组61被充到高电压(第一电压)之后，在读取之前，第一硅通孔组61通过短路路径与低电压的第二硅通孔组62导通，导致第二硅通孔组62电压上升。读取时，第一硅通孔组61的电信号和其左侧的第二硅通孔组62的电信号均为逻辑电平1的电信号。因此，可以在步骤S54根据电信号判断第一硅通孔组61和其相邻的第二硅通孔组62之间是否短路。
在一些实施例中，为了提高第一硅通孔组61和第二硅通孔组62之间的漏电速度，增强短路效应，可以提高第一电压V1，即“strong 1”。提高第一电压V1的方法例如为通过电荷泵提升电源电压，或者将各子电源电路11的上拉单元连接到较高的电源电压上，本公开对此不作特殊限制。第一电压V1的具体值可以根据集成电路的整体需求设置，在满足安全性要求的条件下，尽量高，以在第一硅通孔组61和第二硅通孔组62之间制造更大的电位差，提高第一硅通孔组61和第二硅通孔组62之间的漏电速度，增强短路效应，提高检测效率。
以图6A和图6B所示实施例为例说明步骤S53和步骤S54。在正常情况下，一个测试组的读取数据应该存在1位数据为1，其他位数据为0。而在存在短路的情况下，一个测试组的读取数据中，有可能存在多个数据为1或者所有数据均为0，总之，与正常情况完全不同。
因此，可以通过判断一个测试组的读出数据来确定该测试组是否为与第一硅通孔组位置对应的预设的正常情况，进而，在该测试组的读出数据不等于正常情况对应的数据时，判断该测试组中存在第一硅通孔组61和第二硅通孔组62之间的短路路径。
结合图6A所示实施例，可以设定读取顺序为先读取第一硅通孔组61再读取3个第二硅通孔组62，则该测试组对应的数据应该等于0001(二进制)。如果最终该测试组对应的数据不为0001，则可以判断该测试组存在第一硅通孔组61和第二硅通孔组62之间的短路路径。
当读取顺序为第1个第二硅通孔组62、第2个第二硅通孔组62、第一硅通孔组61、第3个第二硅通孔组62时，正常情况下，读取的数据应该是0010，如果读取的数据为0011、1010、0110等等错误数据时，可以判断该测试组中存在短路路径。甚至，在读取的数据为1110、0111等异常数据时，判断该测试组中存在不止一条短路路径。
使用读取数据与预设数据进行比对，可以更准确地判断一个测试组中短路路径的数量 和位置，进而定位存在故障的硅通孔组。
在另一个实施例中，还可以使用更便捷的方式来判断一个测试组中是否存在短路路径。
图8是本公开一个实施例中步骤S54的流程图。
参考图8，在本公开的一个示例性实施例中，步骤S54还包括：
步骤S541，判断第二硅通孔组的电信号是否包括逻辑电平1的电信号，根据第二硅通孔组的电信号判断第一硅通孔组和第二硅通孔组之间是否短路；
步骤S542，如果第二硅通孔组的电信号包括逻辑电平1的电信号，判断第一硅通孔组和第二硅通孔组之间短路；
步骤S543，如果第二硅通孔组的电信号不包括逻辑电平1的电信号，判断第一硅通孔组和第二硅通孔组未发生短路。
图8所示实施例是一种具体的逻辑判断示例。在第一电压V1较高的情况下，如果第一硅通孔组61和其相邻的第二硅通孔组62发生短路，则短路后的电压为逻辑电平1，此时，测量第二硅通孔组62中是否存在逻辑电平1，更能够准确测出是否存在短路现象。
仅判断第二硅通孔组62是否为逻辑电位1来判断是否存在短路现象可以提高判断效率。无论哪里出现短路，由各第二硅通孔组62的电信号组成的数据必然会存在1。这种方法相比于整体判断测试组的读取数据、根据整个测试组的读取数据的具体数值判断是否短路，要更加便捷和高效，无需因为第一硅通孔组61在测试组中的位置不同而修改判断的基准数据和判断逻辑。
更进一步地，在本公开的一个示例性实施例中，还可以在步骤S541中确定电信号为逻辑电平1的第二硅通孔组，从而确定与第一硅通孔组短路的第二硅通孔组的位置。
仍以图6A所示测试组为例，假设仅对第二硅通孔组62的数据进行判断，正常情况下多个第二硅通孔组62对应的数据均应该等于0，如果存在数值等于1的数据位，则可以根据该数据位与第二硅通孔组62的对应关系判断是哪个或者是哪几个第二硅通孔组62与第一硅通孔组61之间出现了短路。当然，可能存在多个第二硅通孔组62之中的两个短路，其中一个第二硅通孔组62又与第一硅通孔组61之间短路的现象，而并非这两个第二硅通孔组62均与第一硅通孔组61之间短路。
为了防止误判，在本公开实施例中，可以对一个测试组进行换位测量。例如，假设一个测试组包括a、b、c、d四个硅通孔组，在第一次测量时，将硅通孔组a设置为第一硅通孔组61，将硅通孔组b、c、d设置为第二硅通孔组62，测得第一组数据。在第二次测量时，将与硅通孔组a呈对角线的硅通孔组c设置为第一硅通孔组61，将硅通孔组a、b、d设置为第二硅通孔组62，测得第二组数据。
接下来，判断第一组数据、第二组数据的全部数据位是否均等于0。如果第一组数据、第二组数据的全部数据位均等于0，则说明相邻的硅通孔组a、b、d以及c、b、d之间不存在短路。如果第一组数据存在不等于0的数据位，说明硅通孔组a、b、d之间存在短路； 如果第二组数据存在不等于0的数据位，说明硅通孔组c、b、d之间存在短路。具体的短路路径可以根据第一组数值、第二组数值与对各硅通孔组的读取顺序确定。
以上测试策略仅为示例，在实际应用中，还可以根据各硅通孔组的相邻情况，调整对一个测试组的测试策略，本领域技术人员可以根据实际情况自行设置。通过使用多种方式测量一个测试组，可以准确而全面地定位到短路路径的位置，进而为后续的修复或者替代方案提供技术支持。
图6B所示实施例的测试原理同理。图6B所示实施例能够一次读取8个第二硅通孔组62的数据，相比图6A所示实施例能够极大提高测试效率，但是在对一个测试组进行多种测试的情况下，图6B所示实施例对应的测试方案也会更加复杂。
测量一个测试组内部的短路后，还可以更换测试组进行测试，或者，同时测试多个测试组，提高测试效率。在一些实施例中，不同测试组还可以共享相同的硅通孔组，以避免遗漏不同测试组的硅通孔组之间的短路现象。
此外，虽然本公开实施例中多个硅通孔组呈阵列排布，但是在其他场景下，多个硅通孔组还可以根据电路和芯片的实际情况(例如空闲区域分布情况)呈现无规则排布，此时测试组的划分可以根据各硅通孔组之间的距离确定(例如将距离小于预设值的两个硅通孔组确定为相邻硅通孔组)，每个测试组中的硅通孔组的数量不一定相同，不同的测试组也可以包括相同的硅通孔组，本公开对此不作特殊限制。
图9是本公开另一个实施例中读出电路的连接关系示意图。
参考图9，在一些实施例中，如果硅通孔组的两端均位于堆叠芯片/晶圆的边沿第二层，可以在硅通孔组不连接电源电路1的另一端连接读出电路3，进而，读出电路3可以在读取第一硅通孔组末端的电压的同时，判断第一电压V1是否从第一硅通孔组的一端传递到了另一端，进而判断第一硅通孔组是否存在断路。最后，结合断路和短路的判断结果进一步定位哪些硅通孔组存在短路。轮流将不同硅通孔组设置为第一硅通孔组，即可完成对全部硅通孔组的短路和断路测试。
综上所述，本公开实施例通过使用简单电路对相邻的硅通孔组施加第一电压或第二电压，制造电压差，进而引发短路现象，最后根据读取数据定位短路位置，相比于现有技术，无论芯片堆叠多少层，均具有更简单的电路设置和更高效的测试效率，测试准确度也更高。
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和构思由权利要求 指出。
工业实用性
本公开实施例通过对相邻的硅通孔组提供不同的第一电压和第二电压，并对硅通孔组进行读出检测，可以快速有效地检测出存在短路问题的硅通孔组，甚至检测到存在断路问题的硅通孔组。

Claims (15)

  1. 一种硅通孔测试结构，包括：
    多个硅通孔组，所述硅通孔组包括多个电连接的硅通孔；
    与多个所述硅通孔组连接的电源电路，所述电源电路用于向每个所述硅通孔组提供第一电压或第二电压，所述第一电压和所述第二电压不同；
    控制电路，连接所述电源电路，并向所述电源电路提供第一控制信号和第二控制信号，所述电源电路根据所述第一控制信号对至少一个硅通孔组输出所述第一电压，所述电源电路根据所述第二控制信号对至少一个硅通孔组输出所述第二电压；
    读出电路，电连接所述多个硅通孔组，被配置为在所述控制电路提供所述第一控制信号和所述第二控制信号后，读取多个所述硅通孔组上的电信号。
  2. 如权利要求1所述的硅通孔测试结构，其中，所述电源电路包括多个子电源电路，每一所述子电源电路分别对应连接一个所述硅通孔组，所述子电源电路被配置为向所述硅通孔组提供所述第一电压或所述第二电压。
  3. 如权利要求2所述的硅通孔测试结构，其中，所述控制电路分别向所述子电源电路提供所述第一控制信号或所述第二控制信号，所述第一控制信号被配置为控制所述子电源电路输出所述第一电压，所述第二控制信号被配置为控制所述子电源电路输出所述第二电压。
  4. 如权利要求3所述的硅通孔测试结构，其中，所述子电源电路包括上拉模块和下拉模块，所述上拉模块根据所述第一控制信号输出所述第一电压，所述下拉模块根据所述第二控制信号输出所述第二电压。
  5. 如权利要求4所述的硅通孔测试结构，其中，所述上拉模块包括第一晶体管，所述第一晶体管的第一极接收所述第一电压，所述第一晶体管的栅极接收所述第一控制信号，所述第一晶体管的第二极连接所述硅通孔组；所述下拉模块包括第二晶体管和第三晶体管，所述第二晶体管的第一极连接所述所述硅通孔组，所述第二晶体管的第二极连接所述第三晶体管的第一极，所述第二晶体管的栅极接收所述第二控制信号；所述第三晶体管的第二极接收所述第二电压，所述第三晶体管的栅极接收偏置电压。
  6. 如权利要求1-5任一项所述的硅通孔测试结构，其中，所述第一电压大于所述第二电压，所述第二电压小于等于零电位。
  7. 如权利要求1所述的硅通孔测试结构，其中，所述读出电路包括移位寄存器，所述移位寄存器的多个输入端分别连接一个所述硅通孔组，所述移位寄存器的控制端连接第一读取控制信号，所述第一读取控制信号用于控制所述移位寄存器依次读取所述硅通孔组上的电信号。
  8. 如权利要求1所述的硅通孔测试结构，其中，所述读出电路包括多个开关单元，每个所述开关单元的第一端连接一个所述硅通孔组，第二端输出所述硅通孔组上的电信 号，控制端连接一个第二读取控制信号，多个所述第二读取控制信号依次分别打开所述多个开关单元，读出所述硅通孔组上的电信号。
  9. 一种硅通孔短路测试方法，包括：
    在多个硅通孔组中确定一个第一硅通孔组和与所述第一硅通孔组相邻的至少一个第二硅通孔组；
    向所述第一硅通孔组提供第一电压，向所述第二硅通孔组提供第二电压；
    依次读取所述第一硅通孔组和所述第二硅通孔组上的电信号；
    根据所述电信号判断所述第一硅通孔组和所述第二硅通孔组之间是否短路。
  10. 如权利要求9所述的硅通孔短路测试方法，其中，所述第一电压大于所述第二电压，所述第二电压小于等于零电位。
  11. 如权利要求9所述的硅通孔短路测试方法，其中，所述根据所述电信号判断所述第一硅通孔组和所述第二硅通孔组之间是否短路包括：
    判断所述第二硅通孔组的电信号是否包括逻辑电平1的电信号，根据所述第二硅通孔组的电信号判断所述第一硅通孔组和所述第二硅通孔组之间是否短路；
    如果所述第二硅通孔组的电信号包括逻辑电平1的电信号，所述第一硅通孔组和所述第二硅通孔组之间短路；
    如果所述第二硅通孔组的电信号不包括逻辑电平1的电信号，所述第一硅通孔组和所述第二硅通孔组未发生短路。
  12. 如权利要求11所述的硅通孔短路测试方法，其中，所述判断所述第二硅通孔组的电信号是否包括逻辑电平1的电信号，根据所述第二硅通孔组的电信号判断所述第一硅通孔组和所述第二硅通孔组之间是否短路的步骤包括：
    确定电信号为逻辑电平1的所述第二硅通孔组，从而确定与所述第一硅通孔组短路的所述第二硅通孔组的位置。
  13. 如权利要求9所述的硅通孔短路测试方法，其中，所述在多个硅通孔组中确定一个第一硅通孔组和与所述第一硅通孔组相邻的至少一个第二硅通孔组包括：
    将多个硅通孔组分为多个测试组，每个所述测试组包括至少两个相邻的硅通孔组；
    将每个所述测试组中的一个硅通孔组设置为所述第一硅通孔组，将所述测试组中的其他所述硅通孔组均设置为所述第二硅通孔组，每个所述第二硅通孔组均与所述第一硅通孔组相邻。
  14. 如权利要求13所述的硅通孔短路测试方法，其中，所述向所述第一硅通孔组提供第一电压，向所述第二硅通孔组提供第二电压包括：
    对多个所述测试组中的所述第一硅通孔组提供所述第一电压，同时对多个所述测试组中的所述第二硅通孔组提供所述第二电压。
  15. 如权利要求13或14所述的硅通孔短路测试方法，其中，所述依次读取所述第一硅通孔组和所述第二硅通孔组上的电信号包括：
    读取每个所述测试组中的所述第一硅通孔组和所述第二硅通孔组上的电信号。
PCT/CN2022/099939 2022-03-14 2022-06-20 硅通孔测试结构以及硅通孔短路测试方法 WO2023173614A1 (zh)

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