WO2023170815A1

WO2023170815A1 - Pointer transfer device, pointer transfer method, and memory control device

Info

Publication number: WO2023170815A1
Application number: PCT/JP2022/010281
Authority: WO
Inventors: 進田中
Original assignee: 三菱電機株式会社
Priority date: 2022-03-09
Filing date: 2022-03-09
Publication date: 2023-09-14
Also published as: JPWO2023170815A1

Abstract

A read-side read pointer synchronization unit (109) synchronizes a read pointer (208) with a write clock (WCLK) and takes in the result, said read pointer (208) having been generated on the side of a memory read circuit (201) which synchronizes with a read clock (RCLK). A write-side agreement detection unit (113) performs an agreement comparison between the value of a write-side read pointer (110) that is calculated by a write-side read pointer calculation unit (112), and the value of a read-side read pointer (111) that was taken in by the read-side read pointer synchronization unit (109). As long as the write-side agreement detection unit (113) detects non-agreement, the write-side read pointer calculation unit (112) changes the write-side read pointer (110) by one each cycle of the write clock (WCLK).

Description

Pointer transfer device, pointer transfer method, and memory control device

The present disclosure relates to a pointer transfer device, a pointer transfer method, and a memory control device including the pointer transfer device.

When data is transferred between asynchronous clocks in a logic circuit, data is synchronized. As one method of data synchronization, as described in Japanese Patent Application Laid-Open No. 2007-233636 (Patent Document 1), data is transferred between asynchronous clocks via a memory, typically a FIFO (First In First Out) memory. Synchronization techniques for passing data are known.

Normally, in this type of synchronization method, clocks generated by both clocks are used to determine whether there is free space to write to the memory used for data exchange and whether data to be read is stored. It is necessary to use a pointer. At this time, Gray code is sometimes used to transfer data between different asynchronous clocks without changing the pointer value.

Japanese Unexamined Patent Publication No. 2006-074758 (Patent Document 2) describes a Gray code generation method that allows a Gray code corresponding to 2 ⁿ items to be expanded into an even number of items, and using this reduced Gray code, , a technique is described in which pointer values are correctly synchronized between asynchronous clocks.

JP2007-233636A Japanese Patent Application Publication No. 2006-074758

However, although Patent Document 1 shows an asynchronous transfer unit that performs synchronization before performing an operation using a pointer, it does not show a specific circuit configuration, and as a result, the pointer It is not described how the mistransfer of values is achieved. Therefore, it is unclear whether correct data can be exchanged.

Further, Patent Document 2 describes a technique for preventing erroneous transfer of pointer values by using the Gray code corresponding to the even-numbered items described above, but even if the number of items is an odd number, the memory capacity is reduced by 1. It is necessary to use a larger address, which poses problems such as an increase in circuit size and power consumption.

The present disclosure has been made to solve such problems, and the purpose of the present disclosure is to achieve correct pointer synchronization that avoids erroneous transfer of pointer values between asynchronous clocks through simple configuration and control. An object of the present invention is to provide a memory control device and a memory control method that can perform the following steps.

According to an aspect of the present disclosure, a pointer transfer device is provided. The pointer transfer device includes a first pointer generation section, a second pointer generation section, a first synchronization section, a first circuit side pointer value calculation section, and a first coincidence detection section. The first pointer generation unit changes the pointer by one in a predetermined direction of increasing or decreasing every time the first circuit executes the first operation according to the first clock. The second pointer generator changes the second pointer by one in a predetermined direction each time the second circuit executes the second operation according to the second clock. The first synchronization unit takes in the value of the second pointer generated by the second pointer generation unit into the first circuit side in synchronization with the first clock. The first circuit side pointer value calculation section calculates the value of the second pointer on the first circuit side. The first coincidence detection section executes a coincidence comparison between the value of the second pointer in the first circuit side pointer value calculation section and the value of the second pointer taken in by the first synchronization section. The first circuit side pointer value calculation section changes the value of the second pointer by 1 in a predetermined direction for each cycle of the first clock while the first coincidence detection section detects a mismatch. , when a match is detected by the first match detector, the value of the second pointer is maintained.

According to another aspect of the present disclosure, a pointer transfer method is provided in which a first operation is performed in a first circuit according to a first clock, and a second operation is performed in a second circuit according to a second clock. provided. The pointer transfer method includes the steps of changing the first pointer by 1 in a predetermined direction, either increasing or decreasing, on the first circuit side each time the first operation is executed, and each time the second operation is executed. a step of changing the second pointer by 1 in a predetermined direction on the second circuit side; and a step of importing the value of the second pointer on the second circuit side into the first circuit side in synchronization with the first clock. , calculating the value of the second pointer on the first circuit side, and comparing the value of the second pointer calculated on the first circuit side with the value of the second pointer fetched from the second circuit side. and a step of performing. The step of calculating the value of the second pointer is a step of changing the value of the second pointer by 1 in a predetermined direction every cycle of the first clock while a mismatch is detected in the step of performing the match comparison. and maintaining the value of the second pointer when a match is detected in the step of performing the match comparison.

According to the present disclosure, in pointer transfer between asynchronous clocks, a change in the pointer value on the transmitting side is detected and the pointer value calculated on the receiving side is changed by 1, so that the transmitting side and the receiving side It is possible to achieve correct pointer synchronization that avoids erroneous transfer of pointer values between the two.

1 is a block diagram illustrating the configuration of a memory control device according to an embodiment. FIG. 12 is a chart illustrating a process for calculating the number of writable data in data write. 12 is a chart illustrating an example of changes in a write pointer, a read pointer, a writable number, and a readable number due to data writing and data reading; 7 is a timing chart illustrating a specific example of a read pointer transfer process from a memory read circuit to a memory write circuit. 12 is a chart illustrating a process for calculating the number of readable data in data read. 5 is a timing chart illustrating a specific example of a write pointer transfer process from a memory write circuit to a memory read circuit.

Embodiments of the present disclosure will be described in detail below with reference to the drawings. In addition, below, the same code|symbol is attached|subjected to the same or equivalent part in a figure, and the description shall not be repeated in principle.

FIG. 1 is a block diagram illustrating the configuration of a memory control device 100 according to the present embodiment. As will become clear from the following description, the memory control device 100 can be used, for example, to transfer data between logic circuits used in electronic devices that operate with different asynchronous clocks.

(Explanation of circuit configuration)
As shown in FIG. 1, the memory control device 100 operates in response to different asynchronous write clocks WCLK and read clocks RCLK. The memory control device 100 includes a memory 300 for temporarily holding data, a memory write circuit 101 for writing data to the memory 300 in synchronization with a write clock WCLK, and a memory write circuit 101 in synchronization with a read clock RCLK. A memory read circuit 201 for reading data from the memory 300 is provided. The write clock WCLK and read clock RCLK are generated for each clock cycle and input to the memory control device 100. Note that, in the following, for each signal and clock, a logic high level is also expressed as "1", and a logic low level is also expressed as "0".

The memory write circuit 101 includes a write-side access control section 103, a write-side write pointer generation section 107, a read-side read pointer synchronization section 109, a write-side read pointer calculation section 112, and a write-side coincidence detection section 113. include.

The write-side access control unit 103 executes overall control regarding data writing to the memory 300. Specifically, as described later, the write-side access control unit 103 outputs write permission WPRM (WRPM="1") according to the determination result of whether or not writing to the memory 300 is possible. When the write-side access control unit 103 receives the write instruction WCMD and is in a writable state (WPRM="1"), the write-side write enable 104 is enabled (set to "1").Write-side access When the write-side write enable 104 is valid, the control unit 103 further outputs the write-side write pointer increment 106. The write-side write pointer generation unit 107 generates the write-side write pointer 108 indicating the write address of the memory 300.

When the write-side write enable 104 is valid, data writing is executed by writing write data WDAT to the write address of the memory 300 indicated by the write-side write pointer 108 in response to the rising edge of the write clock WCLK. Ru. The write side write pointer 108 increases by 1 in synchronization with the write clock WCLK every time the write data WDAT is written, that is, when the write side write pointer increment 106 is output (i.e., during the period when 106 = “1”). be done.

The read side read pointer synchronization unit 109 receives the read side read pointer 208 generated in the memory read circuit 201 according to the read clock RCLK. The read side read pointer synchronization unit 109 generates the read side read pointer 111 by synchronizing the read side read pointer 208 with the write clock WCLK.

The write-side coincidence detection unit 113 is based on the coincidence detection result between the value of the read-side read pointer 111 generated by the read-side read pointer synchronization unit 109 and the value of the write-side read pointer 110 by the write-side read pointer calculation unit 112. , outputs write-side read pointer increment 114.

The write-side read pointer calculation unit 112 calculates the value of the write-side read pointer 110 in synchronization with the write clock WCLK, based on the write-side read pointer increment 114 from the write-side coincidence detection unit 113. The write-side access control unit 103 uses the write-side read pointer 110 generated by the write-side read pointer calculation unit 112 instead of the read-side read pointer 111 generated by the read-side read pointer synchronization unit 109 to write data to the memory 300. Determine whether writing to WDAT is possible.

The memory read circuit 201 includes a read side access control section 203, a read side read pointer generation section 207, a write side write pointer synchronization section 209, a read side write pointer calculation section 212, and a read side coincidence detection section 213. include.

The read-side access control unit 203 executes overall control regarding reading data from the memory 300. Specifically, as described later, the read-side access control unit 203 outputs read permission RPRM (RRPM="1") according to the determination result of whether reading from the memory 300 is possible. When the read-side access control unit 203 receives the read instruction RCMD and is in a readable state (RPRM="1"), the read-side read enable 204 is enabled ("1"). The read-side access control unit 203 further outputs a read-side read pointer increment 206 when the read-side read enable 204 is enabled. The read side read pointer generation unit 207 generates a read side read pointer 208 indicating a read address of the memory 300.

When the read-side read enable 204 is enabled, data reading is executed by reading read data RDAT from the read address of the memory 300 indicated by the read-side read pointer 208 in response to the rising edge of the read clock RCLK. Ru. The read side read pointer 208 is incremented by 1 in synchronization with the read clock RCLK every time the read data RDAT is read, that is, when the read side read pointer increment 206 is output (that is, during the period when 206 = “1”). Ru.

The write side write pointer synchronization unit 209 receives the write side write pointer 108 generated in the memory write circuit 101 according to the write clock WCLK. The write side write pointer synchronization unit 209 generates a write side write pointer 211 by synchronizing the write side write pointer 108 with the read clock RCLK. The read-side coincidence detection unit 213 detects the read-side write based on the coincidence detection result between the write-side write pointer 211 generated by the write-side write pointer synchronization unit 209 and the read-side write pointer 210 by the read-side write pointer calculation unit 212. Pointer increment 214 is output.

The read-side write pointer calculation unit 212 calculates the value of the read-side write pointer 210 in synchronization with the read clock RCLK, based on the read-side write pointer increment 214 from the read-side coincidence detection unit 213. The read-side access control unit 203 uses the read-side write pointer 210 generated by the read-side write pointer calculation unit 212 instead of the write-side write pointer 211 generated by the write-side write pointer synchronization unit 209 to perform reading from the memory 300. Determine whether data RDAT can be read.

In this manner, the memory write circuit 101 executes data write to the address of the memory 300 indicated by the write-side write pointer 108 in accordance with the write clock WCLK. Similarly, in the memory read circuit 201, data is read from the address of the memory 300 indicated by the read-side read pointer 208 in accordance with the read clock RCLK.

Data writing by the memory write circuit 101 needs to be executed in such a way that the read status of the memory read circuit 201 from the memory 300 is grasped and unread data from the memory 300 is not overwritten and erased. At this time, the read status is grasped using the write-side read pointer 110, which is recognized on the memory write circuit 101 side through an operation synchronized with the write clock WCLK. Therefore, it is important to synchronize the read-side read pointer 208, which is incremented in synchronization with the read clock RCLK, with the write-side read pointer 110, which prevents erroneous transfer of pointer values.

Similarly, when reading data by the memory read circuit 201, the write status of the memory write circuit 101 to the memory 300 is grasped so as to avoid reading data from the memory 300 by mistake when there is no read data in the memory 300. In other words, it is necessary to sequentially read unread data. At this time, the write status is grasped by the read-side write pointer 210, which is recognized on the memory read circuit 201 side by an operation synchronized with the read clock RCLK. Therefore, it is important to synchronize the write-side write pointer 108, which is incremented in synchronization with the write clock WCLK, and the read-side write pointer 210, which prevents erroneous transfer of pointer values.

Next, the circuit operation related to pointer transfer in the memory control device 100 shown in FIG. 1 will be described in more detail. It is assumed that the depth of the memory 300 is seven stages, and that each pointer value is initialized to "0" in the initial state.

Hereinafter, it is assumed that the write pointer and the read pointer have a pointer part that changes within a value range according to the memory depth, and a flag part that is set to "0" or "1". The value of the flag part is inverted every time the value of the pointer part goes around. As described above, when the memory depth is 7, the value of the pointer section is initialized to "0" and increases by 1 each time data is written or read. When data is written or read while the value of the pointer section is "6", the value of the pointer section returns to "0" and the value of the flag section changes from "0" to "1". Or, it is inverted from "1" to "0".

First, the write operation will be explained. In the write operation, a write instruction WCMD is input to the write-side access control unit 103. At this time, if writing is possible, the write-side access control unit 103 enables the write-side write enable 104 (104=“1”). When the write-side write enable 104 is enabled, write data WDAT is written to the address of the memory 300 indicated by the write-side write pointer 108. At this time, if writing is not possible, no particular processing is performed on the memory 300 even if the write instruction WCMD is input.

FIG. 2 shows an example of a process for calculating the number of data that can be written in data writing. The writability determination can be performed according to the calculated value of the writable number illustrated in FIG. 2 .

In FIG. 2, wpf indicates the value of the flag section of the write-side write pointer 108, and wpp indicates the value of the pointer section of the write-side write pointer 108. Further, rpf indicates the value of the flag section of the write-side read pointer 110, and rpp indicates the value of the pointer section of the write-side read pointer 110. N is the memory depth. The determination result of write permission based on the number of write permissions determined according to FIG. 2 is reflected in the write permission WPRM and output from the write-side access control unit 103. Specifically, when the writable number is 0, WPRM="0" is set, and when the writable number is greater than or equal to a predetermined arbitrary natural number, WPRM="1" is set. .

FIG. 3 shows a diagram illustrating an example of changes in the write pointer (wpf, wpp) and read pointer (rpf, rpp), as well as the number of writable numbers and the number of readable numbers, due to data writing and data reading. It will be done.

The memory write circuit 101 uses the values of the flag part wpf and pointer part wpp of the write-side write pointer 108 and the flag part rpf and pointer part rpp of the write-side read pointer 110 to calculate the writeable number according to FIG. Then, a determination is made as to whether or not writing is possible.

In the example of FIG. 3, data write is executed five times from the initial state of wpf=wpp=rpf=rpp=0 (initial value) where no data exists in the memory 300. Correspondingly, wpp increases by 1 from 0 to 5 for each data write. At this time, since wpp<N, wpf=0 is maintained, and since data reading is not executed, rpf=rpp=0 is also maintained.

At this time, the writable number is 7 equal to N in the initial state, and thereafter decreases by 1 for each data write according to the arithmetic expression N-(wpp-rpp) shown in FIG. After data is written five times, the number of writable data is reduced to N-5=2.

After the above five data writes, the same five data reads are executed. Correspondingly, rpp increases by 1 from 0 to 5 for each data read. At this time, since rpp<N, rpf=0 is maintained, and data writing is not executed, so the write pointer values are changed to wpf=0, wpp=5. maintained.

At this time, the writable number increases by 1 according to the arithmetic expression N-(wpp-rpp) shown in FIG. 2 for each data read. When the same number of data reads as data writes have been completed, wpp = rpp (=5) and wpf = wpf (=0), and the number of writable data has returned to N (=7). .

Subsequently, when data is written seven times from the state of wpp=5 (wpf=0), when wpp is incremented from 6 in the second data write, wpp is returned to 0 and the flag is The part wpf is inverted from "0" to "1". Thereafter, wpp is incremented under wpf=1, so after the seventh data write, wpf=1 and wpp=5. Furthermore, regarding the write-side read pointer 110, rpf=0 and rpp=5 are maintained.

At this time, the number of writable numbers is calculated using the calculation formula N-(wpp-rpp) (when wpf=rpf, wpp>rpp), -(wpp-rpp) (wpf≠rpf, wpp<rpp) shown in FIG. ) and 0 (when wpf≠rpf, wpp=rpp), it is decreased by 1 for each data write. After seven data writes, the number of writable data has decreased to N-7=0. At this time, write permission WPRM is set to "0".

After the above seven data writes, the same seven data reads are executed. When data is read seven times from the state of rpp=5 (rpf=0), when rpp is incremented from 6 in the second data read, rpp=0 is returned and the flag part rpf is set. It is inverted from "0" to "1". Thereafter, rpp is incremented under rpf=1, so after the seventh data read, rpf=1 and rpp=5. At this time, the number of writable numbers is determined by the calculation formula shown in FIG. rpp) and N (when wpf=rpf, wpp=rpp), it increases by 1 for each data read. Write permission WPRM is also set to "1". After seven data reads, the number of writable data has returned to N (=7).

Next, a synchronization process between the read side and the write side of the read pointer will be described.
Referring again to FIG. 1, when data is read, the read side read pointer 208 changes. Since the read side read pointer 208 is synchronized with the read clock RCLK, it is necessary to synchronize it with the write clock WCLK by the read side read pointer synchronization unit 109.

For example, the configuration of the read-side read pointer synchronization unit 109 shown in FIG. 1 can be a commonly known two-stage flip-flop. The write-side coincidence detection unit 113 performs a coincidence comparison between the value of the read-side read pointer 111 synchronized on the write side and the value of the write-side read pointer 110 according to the write clock WCLK. If the value of the read-side read pointer 111 and the value of the write-side read pointer 110 do not match, the write-side coincidence detection unit 113 enables the write-side read pointer increment 114 (114=“1”). On the other hand, when the value of the read-side read pointer 111 and the value of the write-side read pointer 110 match, the write-side read pointer increment 114 is invalidated (114="0").

When the write-side read pointer increment 114 is valid (="1"), the write-side read pointer calculation unit 112 increments the write-side read pointer 110 (flag section rpf, pointer section rpp) every cycle of the write clock WCLK. Increment. As described above, when the value of the pointer part rpp after incrementing reaches the memory depth N, rpp is not set to N but is returned to rpp=0, and the value of the flag part rpf is inverted.

When the write-side read pointer 110 catches up with the read-side read pointer 111 synchronized on the write side and they match, the write-side read pointer increment 114 becomes invalid (="0"), and the write-side read pointer 110 becomes invalid. No increment is done. That is, the value of the write-side read pointer 110 is maintained.

Here, the read side read pointer 208 composed of a plurality of bits is also synchronized by the read side read pointer synchronization unit 109 using, for example, a two-stage flip-flop. Therefore, if the timing of the change in the read side read pointer 208 and the timing of the rising edge of the write clock WCLK overlap, a so-called meta-stable state occurs, and the read side read pointer 208 synchronized on the write side There is a possibility that the value of the read side read pointer 208 cannot be correctly transferred to the value of 111. As a result, if the write-side read pointer 110 is used to determine whether writing is possible with an incorrect value, there is a possibility that data writing will be executed even though there is no free space in the memory 300.

Therefore, in this embodiment, instead of using the value of the read-side read pointer 111 synchronized according to the write clock WCLK as the write-side read pointer 110, the value of the read-side read pointer 111 synchronized on the write side is used. , when the write-side coincidence detection unit 113 detects that the write-side read pointer 110 is different, the write-side read pointer 110 is changed by 1 until the read-side read pointer 111 and the write-side read pointer 110 become equal. The values of the pointer part wpp and the flag part wpf are changed so as to change the value of the pointer part wpp and the flag part wpf. By adding such processing, it becomes possible to transfer the write-side read pointer 110 from the read side to the write side, following the read-side read pointer 208, without making a mistake in value.

As mentioned above, it is possible to apply a two-stage flip-flop to the read-side read pointer synchronization section 109 as a synchronization circuit, but the read-side read pointer synchronization section 109 can be implemented using other synchronization methods. 109 is also possible. Furthermore, when the values of the read side read pointer 111 synchronized according to the write clock WCLK and the write side read pointer 110 do not match, the write side coincidence detection unit 113 reads the value of the write side read pointer 110 from the read side. Since the read-side read pointer synchronization unit 109 is configured to follow the value set, the read-side read pointer synchronization unit 109 can also be configured without using a synchronization circuit.

Next, a specific example of a read pointer transfer process from the memory read circuit 201 to the memory write circuit 101 will be described using FIG. 4. In FIG. 4, for each of the read-side read pointer 208, the read-side read pointer 111 synchronized on the write side, and the write-side read pointer 110, the values of the flag part rpf and pointer part rpp are ”.

For example, in the initial state of FIG. 4, the read-side read pointer 208 has a flag part rpf=0 and a pointer part rpp=3 ("0-3"), and the read-side read pointer 111 and Similarly, for the write-side read pointer 110, it is shown that the flag part rpf=0 and the pointer part rpp=3 ("0-3"). That is, the common value of the read pointers between the memory write circuit 101 and the memory read circuit 201 is correctly recognized.

From this state, in the memory read circuit 201, data is read from the memory 300 at every rising edge of the read clock RCLK during a period in which the read side read pointer increment 206 is valid (="1"). In response to data read execution, the read side read pointer 208 is incremented at every rising edge (RCLK).

In the example of FIG. 4, data reading is performed three times at each of three rising edges (RCLK), and the read-side read pointer 208 is incremented at each clock edge. As a result, the read side read pointer 208 changes from "0-3" to "0-6". After that, data read is performed twice each time, and the read side read pointer 208 changes from "0-6" to "1-0", and then from "1-0" to "1-1". ”.

The read-side read pointer synchronization unit 109 of the memory write circuit 101 captures the value of the read-side read pointer 208 in response to the rising edge of the write clock WCLK, which is asynchronous with the read clock RCLK. As a result, a read-side read pointer 111 synchronized according to the write clock WCLK is generated.

However, in the example of FIG. 4, at time t1, the timing at which the read pointer 208 on the read side changes from "0-3" to "0-4" overlaps with the rising edge of the write clock WCLK. As a result, a meta-stable state occurs, so that the value of the read-side read pointer 111 synchronized on the write side is not fixed at the first position. This phenomenon is expressed as "≠0-3" in FIG. 4 because it becomes an undefined value from "0-3".

In the example of FIG. 4, since the change timing of the other read side read pointers 208 does not overlap with the rising edge of the write clock WCLK, the value of the read side read pointer 208 is changed to the read side read pointer 111 synchronized on the write side. is correctly included. Specifically, "0-6", "1-0", and "1-1" of the read side read pointer 208 are synchronized with the read side read pointer at the rising edge (WCLK) of time t2, t5, and t7. The data is taken into the conversion unit 109 and reflected in the read-side read pointer 111 synchronized on the write side at the respective next rising edges at time t3, time t6, and time t8. As mentioned above, since the read side read pointer synchronization unit 109 is assumed to have a two-stage flip-flop configuration, the value of the read side read pointer 208 is synchronized on the write side with the above-mentioned delay. This is reflected in the read pointer 111 on the read side.

The write-side read pointer increment 114 is determined by the write-side coincidence detection unit 113 to be valid (=“1”) in a cycle in which the read-side read pointer 111 synchronized on the write side has a different value from the write-side read pointer 110. Ru. On the contrary, in a cycle in which the read-side read pointer 111 and the write-side read pointer 110 synchronized on the write side are the same, the write-side read pointer increment 114 is invalidated (="0").

When the write-side read pointer calculation unit 112 confirms that the write-side read pointer increment 114 is valid (="1"), it increments the write-side read pointer 110 at the next rising edge of the write clock WCLK. On the other hand, when the write-side read pointer increment 114 is invalid (="0"), the value of the write-side read pointer 110 is maintained.

As a result, in the example of FIG. 4, the write-side read pointer 110 is incremented at each rising edge of the write clock WCLK from time t3 to t5. As a result, the write-side read pointer 110 changes to "0-6", which is the value of the read-side read pointer 111 synchronized on the write side and coincides with the read-side read pointer 208, at time t5. In this way, the undefined value (“≠0-3”) that has become meta-stable is not taken into the read-side read pointer 111 that is synchronized on the write side.

Changes of the read-side read pointer 208 to "1-0" and "1-1" due to subsequent data reading are captured into the read-side read pointer 111 synchronized on the write side according to the write clock WCLK. Furthermore, the value of the write-side read pointer 110 is changed to the read-side read pointer 111 synchronized on the write side by enabling the write-side read pointer increment 114 (="1") by the write-side coincidence detection unit 113. is incremented until it catches up with the value of .

In this way, in this embodiment, instead of using the value of the read side read pointer 208 taken in in synchronization with the write clock WCLK as is, the value of the read pointer taken in (i.e., the value of the read side read pointer 111) is not used as is. When the values of the write-side read pointer 110 and the write-side read pointer 110 are different, a process of changing the write-side read pointer 110 by 1 is executed. As a result, the value of the write-side read pointer 110 can be changed without error by following the change in the read-side read pointer 208 that occurs when the memory read circuit 201 performs a data read.

In this way, pointer synchronization is achieved by transferring the read pointer from the memory read circuit 201 to the memory write circuit 101 without error between the memory read circuit 201 and the memory write circuit 101 that operate with different clocks. . As a result, by accurately determining whether data can be written in the memory write circuit 101, it becomes possible to transfer correct data between asynchronous clocks via the memory 300.

Next, referring to FIG. 1 again, the read operation will be explained. In the read operation, a read instruction RCMD is input to the read side access control unit 203. At this time, if reading is possible, the read side read enable 204 is enabled (“1”) from the read side access control unit 203. When the read-side read enable 204 is enabled, read data RDAT is read from the read address of the memory 300 indicated by the read-side read pointer 208. At this time, if reading is not possible, no particular processing is performed on the memory 300 even if the read instruction RCMD is input.

FIG. 5 shows an example of calculation processing for the number of readable data reads. Readability can be determined according to the calculated value of the readable number illustrated in FIG. 5 .

In FIG. 5, wpf indicates the value of the flag section of the read-side write pointer 210, and wpp indicates the value of the pointer section of the read-side write pointer 210. Furthermore, rpf indicates the value of the flag section of the read-side read pointer 208, and rpp indicates the value of the pointer section of the read-side read pointer 208. N indicates the memory depth as in FIG. The readability determination result based on the readability number calculated according to FIG. 5 is reflected in the read permission RPRM and output from the read side access control unit 203. Specifically, when the readable number is 0, RPRM="0" is set, and when the readable number is greater than or equal to a predetermined arbitrary natural number, RPRM="1" is set.

Referring again to FIG. 3, an example of changes in the write pointers (wpf, wpp), read pointers (rpf, rpp), and the readable number due to data writing and data reading will be described.

The memory read circuit 201 uses the values of the flag part wpf and pointer part wpp of the read-side write pointer 210 and the flag part rpf and pointer part rpp of the read-side read pointer 208 to find the readable number explained in FIG. In this way, it is determined whether reading is possible or not.

As mentioned above, in the example of FIG. 3, data write is executed five times from the initial state of wpf=wpp=rpf=rpp=0 (initial value), but data read is not executed during this time. , rpf=rpp=0 is also maintained. On the other hand, with wpf=0, wpp increases by 1 from 0 to 5 for each data write. At this time, while the readable number is 0 in the initial state, it increases by 1 each time data is written in accordance with the arithmetic expression wpp-rpp shown in FIG. After five data writes, the number of readable data has increased to wpp-rpp=5.

Next, when data is read five times after five data writes, rpp increases by 1 from 0 to 5 for each data read, but since rpp<N. , rpf=0. On the other hand, since no data write has been executed, the values of the write pointer are maintained at wpf=0 and wpp=5.

At this time, for each data read, the readable number decreases by 1 according to the arithmetic expression wpp-rpp shown in FIG. When the same number of data reads as data writes have been completed, wpp=rpp (=5) and wpf=wpf (=0), and the readable number has returned to 0. At this time, read permission RPRM is set to "0".

Subsequently, when data is written seven times from the state of rpp=5 (rpf=0), rpf=0 and rpp=5 are maintained for the read-side read pointer 208. On the other hand, as for the read-side write pointer 210, as described above, in the second data write, wpp is returned to 0, and the flag part wpf is inverted from "0" to "1". After the seventh data write, wpf=1 and wpp=5. At this time, the readable number is determined by the calculation formula shown in FIG. <rpp) and N (wpf≠rpf, wpp=rpp), it increases by 1 for each data write. After seven data writes, the number of readable data has increased to N=7.

After the above seven data writes, when the same seven data reads are executed, as mentioned above, in the second data read, rpp is returned to 0, and the flag part rpf changes from "0" to "1". ” is reversed. Thereafter, rpp is incremented under rpf=1, and after the seventh data read, rpf=1 and rpp=5. At this time, the readable number is determined by the calculation formula shown in FIG. >rpp) and 0 (when wpf=rpf, wpp=rpp), it is decreased by 1 for each data read. After the seventh data read, the readable number becomes 0. At this time, read permission RPRM is set to "0".

Next, a synchronization process between the write side and the read side of the write pointer will be explained.
Referring again to FIG. 1, when a data write is performed, the write side write pointer 108 changes. Since the write side write pointer 108 is synchronized with the write clock WCLK, it is necessary to synchronize it with the read clock RCLK by the write side write pointer synchronization unit 209.

The configuration of the write side write pointer synchronization unit 209 shown in FIG. The read-side coincidence detection unit 213 compares the value of the write-side write pointer 211 synchronized on the read side according to the read clock RCLK with the value of the read-side write pointer 210. If the value of the write-side write pointer 211 and the value of the read-side write pointer 210 do not match, the read-side coincidence detection unit 213 enables the read-side write pointer increment 214 (214=“1”). On the other hand, if the value of the write-side write pointer 211 and the value of the read-side write pointer 210 do not match, the read-side write pointer increment 214 is invalidated (214="0").

When the read-side write pointer increment 214 is valid (="1"), the read-side write pointer calculation unit 212 increments the read-side write pointer 210 (flag section wpf, pointer section wpp) every cycle of the read clock RCLK. ) is incremented. When the read-side write pointer 210 catches up with the write-side write pointer 211 synchronized on the read side and they match, the read-side write pointer increment 214 becomes invalid (="0"), and the read-side write pointer 210 becomes invalid. No increment is done. That is, the value of the read-side write pointer 210 is maintained.

Here, the write side write pointer 108 composed of multiple bits is also synchronized by the write side write pointer synchronization unit 209 using, for example, a two-stage flip-flop. Therefore, if the timing of the change in the write side write pointer 108 and the timing of the rising edge of the read clock RCLK overlap, a so-called meta-stable state occurs, and the write side write pointer synchronized on the read side There is a possibility that the value of the write pointer 108 on the write side cannot be correctly transferred to the value of 211. As a result, if the read-side write pointer 210 is used to determine whether reading is possible with an incorrect value, there is a possibility that data reading will be executed even though there is no unread data in the memory 300.

Therefore, in this embodiment, instead of using the value of the write-side write pointer 211 synchronized according to the read clock RCLK as the read-side write pointer 210, the value of the write-side write pointer 211 synchronized on the read side is used as the read-side write pointer 210. , when the read side coincidence detection unit 213 detects that the read side write pointer 210 is different, the read side write pointer 210 is synchronized on the read side until the write side write pointer 211 synchronized on the read side becomes equal to the read side write pointer 210 The values of the pointer part rpp and the flag part rpf are changed so that the write pointer 210 is changed by 1. By adding such processing, the read-side write pointer 210 can follow the write-side write pointer 108 and transfer the value from the write side to the read side without making a mistake.

As mentioned above, it is possible to apply a two-stage flip-flop as a synchronization circuit to the write-side write pointer synchronization unit 209, but it is also possible to synchronize the write-side write pointer using other synchronization methods. It is also possible to configure the section 209. Furthermore, the read side coincidence detection unit 213 changes the value of the read side write pointer 210 to the value on the write side when the values of the write side write pointer 211 synchronized on the read side and the read side write pointer 210 do not match. Since the write-side write pointer synchronization unit 209 can be configured to follow the synchronization circuit, the write-side write pointer synchronization unit 209 can also be configured without using a synchronization circuit.

Next, a specific example of the process of transferring the write pointer from the memory write circuit 101 to the memory read circuit 201 will be described using FIG. 6. In FIG. 6, the values of the flag part wpf and pointer part wpp are shown for each of the write side write pointer 108, the write side write pointer 211 synchronized on the read side, and the read side write pointer 210, as in FIG. is written as "wpf-wpp".

In FIG. 6, in the initial state, the write side write pointer 108 has a flag part wpf=0 and a pointer part wpp=3 ("0-3"), and the write side write pointer 211 and the read side write pointer 108 are synchronized on the read side. Similarly, for the side write pointer 210, the flag portion wpf=0 and the pointer portion wpp=3 (“0-3”). That is, the write pointers are in a state where a common value is correctly recognized between the memory read circuit 201 and the memory write circuit 101.

From this state, in the memory write circuit 101, data is written to the memory 300 at every rising edge of the write clock WCLK during a period in which the write side write pointer increment 106 is valid (="1"). In response to data write execution, the write side write pointer 108 is incremented at every rising edge (WCLK).

In the example of FIG. 6, data writes are performed three times at each of three rising edges (WCLK), and the write-side write pointer 108 is incremented at each clock edge. As a result, the write side write pointer 108 changes from "0-3" to "0-6". Thereafter, by performing one data write twice, the write side write pointer 108 changes from "0-6" to "1-0", and then from "1-0" to "1-1". ”.

The write-side write pointer synchronization unit 209 of the memory read circuit 201 takes in the value of the write-side write pointer 108 in response to the rising edge of the read clock RCLK, which is asynchronous with the write clock WCLK. As a result, a write side write pointer 211 synchronized on the read side is generated according to the read clock RCLK.

However, in the example of FIG. 6, at time t10, the timing at which the write side write pointer 108 changes from "0-3" to "0-4" overlaps with the rising edge of the read clock RCLK. As a result, a meta-stable state occurs, and the value of the write pointer 211 on the write side synchronized on the read side is not fixed at the first position, but is an undefined value (similar to FIG. 4, "≠0-3"). notation).

In the example of FIG. 6, since the change timing of the other write-side write pointers 108 does not overlap with the rising edge of the read clock RCLK, the value of the write-side write pointer 108 is changed to the write-side write pointer 211 synchronized on the read side. has been properly installed. Specifically, "0-4", "0-5", "0-6", "1-0", and "1-1" of the write side write pointer 108 correspond to times t11, t13, t15, and t18. At the rising edge (RCLK) of , and t21, it is taken into the write side write pointer synchronization unit 209, and synchronized on the read side at the respective next rising edges, times t12, t14, t16, t19, and t22. This is reflected in the converted write-side write pointer 211. As mentioned above, since the write side write pointer synchronization unit 209 is also assumed to have a two-stage flip-flop configuration, the value of the write side write pointer 108 is synchronized on the read side with the above-mentioned delay. It is reflected in the write side write pointer 211 that has been set.

The read-side write pointer increment 214 is determined by the read-side coincidence detection unit 213 to be valid (=“1”) in a cycle in which the write-side write pointer 211 synchronized on the read side has a different value from the read-side write pointer 210. Ru. On the contrary, in a cycle in which the write side write pointer 211 and the read side write pointer 210 that are synchronized on the read side are the same, the read side write pointer increment 214 is invalidated (="0").

When the read-side write pointer calculation unit 212 confirms that the read-side write pointer increment 214 is valid (="1"), it increments the read-side write pointer 210 at the next rising edge of the read clock RCLK. On the other hand, when the read-side write pointer increment 214 is invalid (="0"), the value of the read-side write pointer 210 is maintained.

As a result, in the example of FIG. 6, the read-side write pointer 210 is incremented at each rising edge of the read clock RCLK at times t12, t15, t17, t20, and t23. As a result, the read-side write pointer 210 changes to "1-1", which is the value of the write-side write pointer 211 synchronized on the read side and coincides with the write-side write pointer 108, at time t23. In this way, the undefined value (“≠0-3”) that has become meta-stable is not taken into the write-side write pointer 211 that is synchronized on the read side.

Further, when the value of the read-side write pointer 210 does not match the value of the write-side write pointer 211, which has taken in the correct value of the write-side write pointer 108, the read-side match detection unit 213 enables the read-side write pointer increment 214 ( = "1"), it is incremented until it catches up with the value of the write side write pointer 211 synchronized on the read side.

In this way, instead of using the value of the write side write pointer 108 taken in synchronization with the read clock RCLK as is, the read side write By performing a process of changing the read-side write pointer 210 by 1 when the value differs from the pointer 210, the change in the write-side write pointer 108 accompanying the execution of data write in the memory write circuit 101 can be followed. The value of the read-side write pointer 210 can be changed without making a mistake.

As a result, between the memory write circuit 101 and the memory read circuit 201 that operate with different clocks, the write pointer can be transferred from the memory write circuit 101 to the memory read circuit 201 without error, thereby avoiding erroneous transfer of pointer values. Pointer synchronization can be achieved. As a result, by accurately determining whether data can be read in the memory read circuit 201, it becomes possible to transfer correct data between asynchronous clocks via the memory 300.

As described above, according to the present embodiment, in pointer transfer between asynchronous clocks, a change in the value of the transmitting side pointer is detected and the receiving side pointer value is changed by 1 to follow it. By doing so, it is possible to correctly synchronize pointers while preventing erroneous transfers. As a result, correct data can be exchanged via the memory 300.

In addition, since Gray code as in Patent Document 2 is not used, it is no longer necessary to use a memory capacity that is one address larger than the memory capacity accessed when the number of pointers is an odd number, which reduces the increase in circuit size and power consumption. It can be prevented.

In the embodiment described above, the write clock WCLK corresponds to an example of the "first clock," the read clock RCLK corresponds to an example of the "second clock," and the memory write circuit 101 corresponds to an example of the "second clock." The memory read circuit 201 corresponds to an embodiment of the "first circuit", and the memory read circuit 201 corresponds to an embodiment of the "second circuit".

Further, in the memory write circuit 101, the write side write pointer 108 is a "first pointer", the write side write pointer generation section 107 is a "first pointer generation section", and the read side read pointer synchronization section 109 is a "first pointer". The write-side read pointer calculation unit 112 corresponds to an embodiment of the “first circuit-side pointer value calculation unit”, and the write-side coincidence detection unit 113 corresponds to an example of the “first coincidence detection unit”. Further, the write side read pointer 110 corresponds to "the second pointer calculated by the first circuit side pointer value calculation section", and the read side read pointer 111 generated by the read side read pointer synchronization section 109 corresponds to "the second pointer calculated by the first circuit side pointer value calculation section". "The second pointer fetched by the first synchronization unit".

Similarly, in the memory read circuit 201, the read-side read pointer 208 is a "second pointer," the read-side read pointer generation section 207 is a "second pointer generation section," and the write-side write pointer synchronization section 209 is a "second synchronization section." The read side write pointer calculation unit 212 corresponds to an example of a “second circuit side pointer value calculation unit”, and the read side coincidence detection unit 213 corresponds to an example of a “second coincidence detection unit”. Further, the read side write pointer 210 corresponds to "the first pointer calculated by the second circuit side pointer value calculation section", and the write side write pointer 211 generated by the write side write pointer synchronization section 209 corresponds to "the first pointer calculated by the second circuit side pointer value calculation section". "first pointer taken in by the second synchronization unit".

In this embodiment, an example is shown in which each pointer is incremented every time data is written and every time data is read. However, even if each pointer is decremented every time data is written and read, this embodiment It is possible to apply memory control related to. In this case, similar memory control can be realized by appropriately replacing "increment" with "decrement" in the description of this embodiment. That is, in this embodiment, each pointer value changes by 1 in a predetermined direction, either increasing or decreasing.

Furthermore, in this embodiment, the number of data stored in the memory 300 is not output to the outside, but information indicating the number of data stored may be output from the memory control device 100 to the outside. Furthermore, the number of clock cycles required for the operation of each circuit block is not limited to the above description and can be set freely. Furthermore, in the above, an example has been described in which the pointer transfer according to the present embodiment is applied to both write pointer transfer and read pointer transfer, that is, bidirectional pointer transfer. It is also possible to apply this embodiment to only one of the pointer transfers. For example, if this embodiment is applied only to write pointer transfer, the arrangement of the write-side read pointer calculation section 112 and the write-side coincidence detection section 113 on the write side can be omitted from the configuration example of FIG. can. On the other hand, if this embodiment is applied only to read pointer transfer, the arrangement of the read side write pointer calculation section 212 and the read side coincidence detection section 213 on the read side can be omitted from the configuration example of FIG. I can do it.

Furthermore, in this embodiment, memory control has been described as involving data writing and reading from the memory 300, but by applying this embodiment only to the part of pointer transfer between asynchronous clocks, this embodiment can be It is also possible to provide a pointer transfer device and a pointer control method according to the embodiment. In this case as well, the pointer transfer device and pointer control method can be configured so that the present embodiment is applied only to one-way pointer transfer out of two-way pointer transfer.

The embodiments disclosed this time should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is indicated by the claims rather than the above description, and it is intended that all changes within the meaning and range equivalent to the claims are included.

100 Memory control device, 101 Memory write circuit, 103 Write side access control unit, 104 Write side write enable, 106 Write side write pointer increment, 107 Write side write pointer generation unit, 108 Write side write pointer, 109 Read side read pointer synchronization conversion unit, 110 write side read pointer, 111 read side read pointer (write circuit side synchronization), 112 write side read pointer calculation unit, 113 write side coincidence detection unit, 114 write side read pointer increment, 201 memory read circuit, 203 Read side access control unit, 204 Read side read enable, 206 Read side read pointer increment, 207 Read side read pointer generation unit, 208 Read side read pointer, 209 Write side write pointer synchronization unit, 210 Read side write pointer, 211 Write side write pointer (read circuit side synchronization), 212 Read side write pointer calculation unit, 213 Read side coincidence detection unit, 214 Read side write pointer increment, 300 Memory, N memory depth, RCLK read clock, RCMD read instruction, RDAT read data, RPRM read permission, WCLK write clock, WCMD write instruction, WDAT write data, WPRM write permission, rpf flag section (read pointer), rpp pointer section (read pointer), rpf flag section (write pointer), wpp pointer part (light pointer).

Claims

a first pointer generation unit that changes the first pointer by one in a predetermined direction of increasing or decreasing each time the first circuit executes the first operation according to the first clock;
a second pointer generation unit that changes the second pointer by one in the predetermined direction each time a second operation is performed by a second circuit according to a second clock;
a first synchronization unit that imports the value of the second pointer from the second pointer generation unit into the first circuit side in synchronization with the first clock;
a first circuit side pointer value calculation unit that calculates the value of the second pointer on the first circuit side;
a first coincidence detection section that performs a coincidence comparison between the value of the second pointer calculated by the first circuit side pointer value calculation section and the value of the second pointer taken in by the first synchronization section; and
The first circuit-side pointer value calculation section changes the value of the second pointer by 1 in the predetermined direction for each cycle of the first clock while a mismatch is detected by the first coincidence detection section. The pointer transfer device maintains the value of the second pointer when a match is detected by the first match detector.
a second synchronization unit that imports the value of the first pointer from the first pointer generation unit into the second circuit side in synchronization with the second clock;
a second circuit side pointer value calculation unit that calculates the value of the first pointer on the second circuit side;
a second coincidence detection section that performs a coincidence comparison between the value of the first pointer being computed by the pointer value computing section on the second circuit side and the value of the first pointer taken in by the second synchronization section; further comprising:
The second circuit-side pointer value calculation section changes the value of the first pointer by 1 in the predetermined direction for each cycle of the second clock while a mismatch is detected by the second coincidence detection section. 2. The pointer transfer device according to claim 1, wherein the pointer transfer device maintains the value of the first pointer when a match is detected by the second match detector.
Comprising the point transfer device according to claim 1,
The first operation by the first circuit is one of writing data to a memory and reading data from the memory,
The second operation by the second circuit is the other operation of the data write and the data read,
the first pointer indicates an address of the memory that is a target of the one operation;
The second pointer indicates an address of the memory that is a target of the other operation.
Comprising the point transfer device according to claim 2,
The first operation by the first circuit is writing data to a memory,
The second operation by the second circuit is reading data from the memory,
the first pointer indicates an address of the memory to which the data is written;
The second pointer indicates an address of the memory from which the data is to be read.
The first circuit calculates the value of the first pointer generated by the first pointer generation unit, the value of the second pointer calculated by the first circuit side pointer value calculation unit, and the number of addresses of the memory. 5. The memory control device according to claim 4, wherein the possible number of times the data can be written to the memory is calculated based on a memory depth corresponding to .
The second circuit calculates the value of the second pointer generated by the second pointer generation unit, the value of the first pointer calculated by the second circuit side pointer value calculation unit, and the number of addresses of the memory. 5. The memory control device according to claim 4, wherein the possible number of times the data can be read from the memory is calculated based on a memory depth corresponding to .
A pointer transfer method in which a first operation is executed in a first circuit according to a first clock, and a second operation is executed in a second circuit according to a second clock, the method comprising:
changing a first pointer by one in a predetermined direction of increasing or decreasing on the first circuit side each time the first operation is executed;
changing a second pointer by one in the predetermined direction on the second circuit side each time the second operation is executed;
fetching the value of the second pointer on the second circuit side into the first circuit side in synchronization with the first clock;
calculating the value of the second pointer on the first circuit side;
comprising the step of performing a match comparison between the value of the second pointer calculated on the first circuit side and the value of the second pointer taken in from the second circuit side,
The step of calculating the value of the second pointer includes:
While a mismatch is detected in the step of performing the coincidence comparison, changing the value of the second pointer by 1 in the predetermined direction for each cycle of the first clock;
and maintaining the value of the second pointer when a match is detected in the step of performing the match comparison.
importing the value of the first pointer on the first circuit side into the second circuit side in synchronization with the second clock;
calculating the value of the first pointer on the second circuit side;
further comprising the step of performing a match comparison between the value of the first pointer calculated on the second circuit side and the value of the first pointer taken in from the first circuit side,
The step of calculating the value of the first pointer includes:
While a mismatch is detected in the step of performing the coincidence comparison, changing the value of the first pointer by 1 in the predetermined direction for each cycle of the second clock;
8. The pointer transfer method according to claim 7, further comprising the step of maintaining the value of the first pointer when a match is detected in the step of performing the match comparison.
The first operation by the first circuit is one of writing data to a memory and reading data from the memory,
The second operation by the second circuit is the other operation of the data write and the data read,
the first pointer indicates an address of the memory that is a target of the one operation;
8. The pointer transfer method according to claim 7, wherein said second pointer indicates an address of said memory that is a target of said other operation.
The first operation by the first circuit is writing data to a memory,
The second operation by the second circuit is reading data from the memory,
the first pointer indicates an address of the memory to which the data is written;
9. The pointer transfer method according to claim 8, wherein the second pointer indicates an address of the memory from which the data is to be read.
The possible number of times the data can be written to the memory is determined by the value of the first pointer generated on the first circuit side, the value of the second pointer calculated on the first circuit side, and the address of the memory. 11. The pointer transfer method according to claim 10, wherein the pointer transfer method is calculated on the first circuit side based on a memory depth corresponding to the number.
The possible number of times the data can be read from the memory is determined by the value of the second pointer generated on the second circuit side, the value of the first pointer calculated on the second circuit side, and the number of addresses of the memory. 11. The pointer transfer method according to claim 10, wherein the pointer transfer method is calculated on the second circuit side based on a memory depth corresponding to .