WO2023170815A1 - Dispositif de transfert de pointeur, procédé de transfert de pointeur, et dispositif de commande de mémoire - Google Patents

Dispositif de transfert de pointeur, procédé de transfert de pointeur, et dispositif de commande de mémoire Download PDF

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Publication number
WO2023170815A1
WO2023170815A1 PCT/JP2022/010281 JP2022010281W WO2023170815A1 WO 2023170815 A1 WO2023170815 A1 WO 2023170815A1 JP 2022010281 W JP2022010281 W JP 2022010281W WO 2023170815 A1 WO2023170815 A1 WO 2023170815A1
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pointer
read
write
value
memory
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PCT/JP2022/010281
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English (en)
Japanese (ja)
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進 田中
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三菱電機株式会社
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Priority to JP2024505719A priority Critical patent/JPWO2023170815A1/ja
Priority to PCT/JP2022/010281 priority patent/WO2023170815A1/fr
Publication of WO2023170815A1 publication Critical patent/WO2023170815A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Definitions

  • the present disclosure relates to a pointer transfer device, a pointer transfer method, and a memory control device including the pointer transfer device.
  • Patent Document 1 When data is transferred between asynchronous clocks in a logic circuit, data is synchronized.
  • Patent Document 1 data is transferred between asynchronous clocks via a memory, typically a FIFO (First In First Out) memory. Synchronization techniques for passing data are known.
  • clocks generated by both clocks are used to determine whether there is free space to write to the memory used for data exchange and whether data to be read is stored. It is necessary to use a pointer. At this time, Gray code is sometimes used to transfer data between different asynchronous clocks without changing the pointer value.
  • Patent Document 2 describes a Gray code generation method that allows a Gray code corresponding to 2 n items to be expanded into an even number of items, and using this reduced Gray code, , a technique is described in which pointer values are correctly synchronized between asynchronous clocks.
  • JP2007-233636A Japanese Patent Application Publication No. 2006-074758
  • Patent Document 1 shows an asynchronous transfer unit that performs synchronization before performing an operation using a pointer, it does not show a specific circuit configuration, and as a result, the pointer It is not described how the mistransfer of values is achieved. Therefore, it is unclear whether correct data can be exchanged.
  • Patent Document 2 describes a technique for preventing erroneous transfer of pointer values by using the Gray code corresponding to the even-numbered items described above, but even if the number of items is an odd number, the memory capacity is reduced by 1. It is necessary to use a larger address, which poses problems such as an increase in circuit size and power consumption.
  • An object of the present invention is to provide a memory control device and a memory control method that can perform the following steps.
  • a pointer transfer device includes a first pointer generation section, a second pointer generation section, a first synchronization section, a first circuit side pointer value calculation section, and a first coincidence detection section.
  • the first pointer generation unit changes the pointer by one in a predetermined direction of increasing or decreasing every time the first circuit executes the first operation according to the first clock.
  • the second pointer generator changes the second pointer by one in a predetermined direction each time the second circuit executes the second operation according to the second clock.
  • the first synchronization unit takes in the value of the second pointer generated by the second pointer generation unit into the first circuit side in synchronization with the first clock.
  • the first circuit side pointer value calculation section calculates the value of the second pointer on the first circuit side.
  • the first coincidence detection section executes a coincidence comparison between the value of the second pointer in the first circuit side pointer value calculation section and the value of the second pointer taken in by the first synchronization section.
  • the first circuit side pointer value calculation section changes the value of the second pointer by 1 in a predetermined direction for each cycle of the first clock while the first coincidence detection section detects a mismatch. , when a match is detected by the first match detector, the value of the second pointer is maintained.
  • a pointer transfer method in which a first operation is performed in a first circuit according to a first clock, and a second operation is performed in a second circuit according to a second clock.
  • the pointer transfer method includes the steps of changing the first pointer by 1 in a predetermined direction, either increasing or decreasing, on the first circuit side each time the first operation is executed, and each time the second operation is executed. a step of changing the second pointer by 1 in a predetermined direction on the second circuit side; and a step of importing the value of the second pointer on the second circuit side into the first circuit side in synchronization with the first clock.
  • the step of calculating the value of the second pointer is a step of changing the value of the second pointer by 1 in a predetermined direction every cycle of the first clock while a mismatch is detected in the step of performing the match comparison. and maintaining the value of the second pointer when a match is detected in the step of performing the match comparison.
  • FIG. 12 is a chart illustrating a process for calculating the number of writable data in data write.
  • 12 is a chart illustrating an example of changes in a write pointer, a read pointer, a writable number, and a readable number due to data writing and data reading;
  • 7 is a timing chart illustrating a specific example of a read pointer transfer process from a memory read circuit to a memory write circuit.
  • 12 is a chart illustrating a process for calculating the number of readable data in data read.
  • 5 is a timing chart illustrating a specific example of a write pointer transfer process from a memory write circuit to a memory read circuit.
  • FIG. 1 is a block diagram illustrating the configuration of a memory control device 100 according to the present embodiment.
  • the memory control device 100 can be used, for example, to transfer data between logic circuits used in electronic devices that operate with different asynchronous clocks.
  • the memory control device 100 operates in response to different asynchronous write clocks WCLK and read clocks RCLK.
  • the memory control device 100 includes a memory 300 for temporarily holding data, a memory write circuit 101 for writing data to the memory 300 in synchronization with a write clock WCLK, and a memory write circuit 101 in synchronization with a read clock RCLK.
  • a memory read circuit 201 for reading data from the memory 300 is provided.
  • the write clock WCLK and read clock RCLK are generated for each clock cycle and input to the memory control device 100. Note that, in the following, for each signal and clock, a logic high level is also expressed as "1", and a logic low level is also expressed as "0".
  • the memory write circuit 101 includes a write-side access control section 103, a write-side write pointer generation section 107, a read-side read pointer synchronization section 109, a write-side read pointer calculation section 112, and a write-side coincidence detection section 113. include.
  • WPRM write permission
  • the write-side write pointer generation unit 107 generates the write-side write pointer 108 indicating the write address of the memory 300.
  • write-side write enable 104 When the write-side write enable 104 is valid, data writing is executed by writing write data WDAT to the write address of the memory 300 indicated by the write-side write pointer 108 in response to the rising edge of the write clock WCLK. Ru.
  • the read side read pointer synchronization unit 109 receives the read side read pointer 208 generated in the memory read circuit 201 according to the read clock RCLK.
  • the read side read pointer synchronization unit 109 generates the read side read pointer 111 by synchronizing the read side read pointer 208 with the write clock WCLK.
  • the write-side coincidence detection unit 113 is based on the coincidence detection result between the value of the read-side read pointer 111 generated by the read-side read pointer synchronization unit 109 and the value of the write-side read pointer 110 by the write-side read pointer calculation unit 112. , outputs write-side read pointer increment 114.
  • the write-side read pointer calculation unit 112 calculates the value of the write-side read pointer 110 in synchronization with the write clock WCLK, based on the write-side read pointer increment 114 from the write-side coincidence detection unit 113.
  • the write-side access control unit 103 uses the write-side read pointer 110 generated by the write-side read pointer calculation unit 112 instead of the read-side read pointer 111 generated by the read-side read pointer synchronization unit 109 to write data to the memory 300. Determine whether writing to WDAT is possible.
  • the memory read circuit 201 includes a read side access control section 203, a read side read pointer generation section 207, a write side write pointer synchronization section 209, a read side write pointer calculation section 212, and a read side coincidence detection section 213. include.
  • RPRM read permission RPRM
  • read-side read enable 204 When the read-side read enable 204 is enabled, data reading is executed by reading read data RDAT from the read address of the memory 300 indicated by the read-side read pointer 208 in response to the rising edge of the read clock RCLK. Ru.
  • the write side write pointer synchronization unit 209 receives the write side write pointer 108 generated in the memory write circuit 101 according to the write clock WCLK.
  • the write side write pointer synchronization unit 209 generates a write side write pointer 211 by synchronizing the write side write pointer 108 with the read clock RCLK.
  • the read-side coincidence detection unit 213 detects the read-side write based on the coincidence detection result between the write-side write pointer 211 generated by the write-side write pointer synchronization unit 209 and the read-side write pointer 210 by the read-side write pointer calculation unit 212.
  • Pointer increment 214 is output.
  • the read-side write pointer calculation unit 212 calculates the value of the read-side write pointer 210 in synchronization with the read clock RCLK, based on the read-side write pointer increment 214 from the read-side coincidence detection unit 213.
  • the read-side access control unit 203 uses the read-side write pointer 210 generated by the read-side write pointer calculation unit 212 instead of the write-side write pointer 211 generated by the write-side write pointer synchronization unit 209 to perform reading from the memory 300. Determine whether data RDAT can be read.
  • the memory write circuit 101 executes data write to the address of the memory 300 indicated by the write-side write pointer 108 in accordance with the write clock WCLK.
  • data is read from the address of the memory 300 indicated by the read-side read pointer 208 in accordance with the read clock RCLK.
  • Data writing by the memory write circuit 101 needs to be executed in such a way that the read status of the memory read circuit 201 from the memory 300 is grasped and unread data from the memory 300 is not overwritten and erased.
  • the read status is grasped using the write-side read pointer 110, which is recognized on the memory write circuit 101 side through an operation synchronized with the write clock WCLK. Therefore, it is important to synchronize the read-side read pointer 208, which is incremented in synchronization with the read clock RCLK, with the write-side read pointer 110, which prevents erroneous transfer of pointer values.
  • the write status of the memory write circuit 101 to the memory 300 is grasped so as to avoid reading data from the memory 300 by mistake when there is no read data in the memory 300. In other words, it is necessary to sequentially read unread data.
  • the write status is grasped by the read-side write pointer 210, which is recognized on the memory read circuit 201 side by an operation synchronized with the read clock RCLK. Therefore, it is important to synchronize the write-side write pointer 108, which is incremented in synchronization with the write clock WCLK, and the read-side write pointer 210, which prevents erroneous transfer of pointer values.
  • the write pointer and the read pointer have a pointer part that changes within a value range according to the memory depth, and a flag part that is set to "0" or "1".
  • the value of the flag part is inverted every time the value of the pointer part goes around.
  • the value of the pointer section is initialized to "0" and increases by 1 each time data is written or read.
  • the value of the pointer section returns to "0” and the value of the flag section changes from “0” to "1". Or, it is inverted from "1" to "0".
  • a write instruction WCMD is input to the write-side access control unit 103.
  • write data WDAT is written to the address of the memory 300 indicated by the write-side write pointer 108.
  • no particular processing is performed on the memory 300 even if the write instruction WCMD is input.
  • FIG. 2 shows an example of a process for calculating the number of data that can be written in data writing.
  • the writability determination can be performed according to the calculated value of the writable number illustrated in FIG. 2 .
  • wpf indicates the value of the flag section of the write-side write pointer 108
  • wpp indicates the value of the pointer section of the write-side write pointer 108
  • rpf indicates the value of the flag section of the write-side read pointer 110
  • rpp indicates the value of the pointer section of the write-side read pointer 110.
  • N is the memory depth.
  • FIG. 3 shows a diagram illustrating an example of changes in the write pointer (wpf, wpp) and read pointer (rpf, rpp), as well as the number of writable numbers and the number of readable numbers, due to data writing and data reading. It will be done.
  • the memory write circuit 101 uses the values of the flag part wpf and pointer part wpp of the write-side write pointer 108 and the flag part rpf and pointer part rpp of the write-side read pointer 110 to calculate the writeable number according to FIG. Then, a determination is made as to whether or not writing is possible.
  • wpp increases by 1 from 0 to 5 for each data write.
  • rpp increases by 1 from 0 to 5 for each data read.
  • the writable number increases by 1 according to the arithmetic expression N-(wpp-rpp) shown in FIG. 2 for each data read.
  • N-(wpp-rpp) the arithmetic expression shown in FIG. 2 for each data read.
  • the read side read pointer 208 changes. Since the read side read pointer 208 is synchronized with the read clock RCLK, it is necessary to synchronize it with the write clock WCLK by the read side read pointer synchronization unit 109.
  • the configuration of the read-side read pointer synchronization unit 109 shown in FIG. 1 can be a commonly known two-stage flip-flop.
  • the read side read pointer 208 composed of a plurality of bits is also synchronized by the read side read pointer synchronization unit 109 using, for example, a two-stage flip-flop. Therefore, if the timing of the change in the read side read pointer 208 and the timing of the rising edge of the write clock WCLK overlap, a so-called meta-stable state occurs, and the read side read pointer 208 synchronized on the write side There is a possibility that the value of the read side read pointer 208 cannot be correctly transferred to the value of 111. As a result, if the write-side read pointer 110 is used to determine whether writing is possible with an incorrect value, there is a possibility that data writing will be executed even though there is no free space in the memory 300.
  • the value of the read-side read pointer 111 synchronized on the write side is used.
  • the write-side coincidence detection unit 113 detects that the write-side read pointer 110 is different, the write-side read pointer 110 is changed by 1 until the read-side read pointer 111 and the write-side read pointer 110 become equal.
  • the values of the pointer part wpp and the flag part wpf are changed so as to change the value of the pointer part wpp and the flag part wpf.
  • the read-side read pointer synchronization section 109 can be implemented using other synchronization methods. 109 is also possible. Furthermore, when the values of the read side read pointer 111 synchronized according to the write clock WCLK and the write side read pointer 110 do not match, the write side coincidence detection unit 113 reads the value of the write side read pointer 110 from the read side. Since the read-side read pointer synchronization unit 109 is configured to follow the value set, the read-side read pointer synchronization unit 109 can also be configured without using a synchronization circuit.
  • FIG. 4 For each of the read-side read pointer 208, the read-side read pointer 111 synchronized on the write side, and the write-side read pointer 110, the values of the flag part rpf and pointer part rpp are ”.
  • the read side read pointer 208 is incremented at every rising edge (RCLK).
  • the read-side read pointer synchronization unit 109 of the memory write circuit 101 captures the value of the read-side read pointer 208 in response to the rising edge of the write clock WCLK, which is asynchronous with the read clock RCLK. As a result, a read-side read pointer 111 synchronized according to the write clock WCLK is generated.
  • the read side read pointer synchronization unit 109 is assumed to have a two-stage flip-flop configuration, the value of the read side read pointer 208 is synchronized on the write side with the above-mentioned delay. This is reflected in the read pointer 111 on the read side.
  • the write-side read pointer 110 is incremented at each rising edge of the write clock WCLK from time t3 to t5.
  • the write-side read pointer 110 changes to "0-6", which is the value of the read-side read pointer 111 synchronized on the write side and coincides with the read-side read pointer 208, at time t5.
  • the undefined value (“ ⁇ 0-3”) that has become meta-stable is not taken into the read-side read pointer 111 that is synchronized on the write side.
  • the value of the read pointer taken in (i.e., the value of the read side read pointer 111) is not used as is.
  • the values of the write-side read pointer 110 and the write-side read pointer 110 are different, a process of changing the write-side read pointer 110 by 1 is executed. As a result, the value of the write-side read pointer 110 can be changed without error by following the change in the read-side read pointer 208 that occurs when the memory read circuit 201 performs a data read.
  • pointer synchronization is achieved by transferring the read pointer from the memory read circuit 201 to the memory write circuit 101 without error between the memory read circuit 201 and the memory write circuit 101 that operate with different clocks. .
  • the memory write circuit 101 by accurately determining whether data can be written in the memory write circuit 101, it becomes possible to transfer correct data between asynchronous clocks via the memory 300.
  • a read instruction RCMD is input to the read side access control unit 203.
  • the read side read enable 204 is enabled (“1”) from the read side access control unit 203.
  • read data RDAT is read from the read address of the memory 300 indicated by the read-side read pointer 208. At this time, if reading is not possible, no particular processing is performed on the memory 300 even if the read instruction RCMD is input.
  • FIG. 5 shows an example of calculation processing for the number of readable data reads. Readability can be determined according to the calculated value of the readable number illustrated in FIG. 5 .
  • wpf indicates the value of the flag section of the read-side write pointer 210
  • wpp indicates the value of the pointer section of the read-side write pointer 210
  • rpf indicates the value of the flag section of the read-side read pointer 208
  • rpp indicates the value of the pointer section of the read-side read pointer 208.
  • N indicates the memory depth as in FIG.
  • the memory read circuit 201 uses the values of the flag part wpf and pointer part wpp of the read-side write pointer 210 and the flag part rpf and pointer part rpp of the read-side read pointer 208 to find the readable number explained in FIG. In this way, it is determined whether reading is possible or not.
  • the write side write pointer 108 changes. Since the write side write pointer 108 is synchronized with the write clock WCLK, it is necessary to synchronize it with the read clock RCLK by the write side write pointer synchronization unit 209.
  • the read-side write pointer calculation unit 212 increments the read-side write pointer 210 (flag section wpf, pointer section wpp) every cycle of the read clock RCLK. ) is incremented.
  • the write side write pointer 108 composed of multiple bits is also synchronized by the write side write pointer synchronization unit 209 using, for example, a two-stage flip-flop. Therefore, if the timing of the change in the write side write pointer 108 and the timing of the rising edge of the read clock RCLK overlap, a so-called meta-stable state occurs, and the write side write pointer synchronized on the read side There is a possibility that the value of the write pointer 108 on the write side cannot be correctly transferred to the value of 211. As a result, if the read-side write pointer 210 is used to determine whether reading is possible with an incorrect value, there is a possibility that data reading will be executed even though there is no unread data in the memory 300.
  • the value of the write-side write pointer 211 synchronized on the read side is used as the read-side write pointer 210.
  • the read side coincidence detection unit 213 detects that the read side write pointer 210 is different, the read side write pointer 210 is synchronized on the read side until the write side write pointer 211 synchronized on the read side becomes equal to the read side write pointer 210
  • the values of the pointer part rpp and the flag part rpf are changed so that the write pointer 210 is changed by 1.
  • the read-side write pointer 210 can follow the write-side write pointer 108 and transfer the value from the write side to the read side without making a mistake.
  • the write-side write pointer synchronization unit 209 it is possible to apply a two-stage flip-flop as a synchronization circuit to the write-side write pointer synchronization unit 209, but it is also possible to synchronize the write-side write pointer using other synchronization methods. It is also possible to configure the section 209. Furthermore, the read side coincidence detection unit 213 changes the value of the read side write pointer 210 to the value on the write side when the values of the write side write pointer 211 synchronized on the read side and the read side write pointer 210 do not match. Since the write-side write pointer synchronization unit 209 can be configured to follow the synchronization circuit, the write-side write pointer synchronization unit 209 can also be configured without using a synchronization circuit.
  • FIG. 6 the values of the flag part wpf and pointer part wpp are shown for each of the write side write pointer 108, the write side write pointer 211 synchronized on the read side, and the read side write pointer 210, as in FIG. is written as "wpf-wpp".
  • the write-side write pointer synchronization unit 209 of the memory read circuit 201 takes in the value of the write-side write pointer 108 in response to the rising edge of the read clock RCLK, which is asynchronous with the write clock WCLK. As a result, a write side write pointer 211 synchronized on the read side is generated according to the read clock RCLK.
  • the write side write pointer synchronization unit 209 At the rising edge (RCLK) of , and t21, it is taken into the write side write pointer synchronization unit 209, and synchronized on the read side at the respective next rising edges, times t12, t14, t16, t19, and t22. This is reflected in the converted write-side write pointer 211.
  • the write side write pointer synchronization unit 209 is also assumed to have a two-stage flip-flop configuration, the value of the write side write pointer 108 is synchronized on the read side with the above-mentioned delay. It is reflected in the write side write pointer 211 that has been set.
  • the read-side write pointer 210 is incremented at each rising edge of the read clock RCLK at times t12, t15, t17, t20, and t23.
  • the read-side write pointer 210 changes to "1-1", which is the value of the write-side write pointer 211 synchronized on the read side and coincides with the write-side write pointer 108, at time t23.
  • the undefined value (“ ⁇ 0-3”) that has become meta-stable is not taken into the write-side write pointer 211 that is synchronized on the read side.
  • the read side write By performing a process of changing the read-side write pointer 210 by 1 when the value differs from the pointer 210, the change in the write-side write pointer 108 accompanying the execution of data write in the memory write circuit 101 can be followed.
  • the value of the read-side write pointer 210 can be changed without making a mistake.
  • the write pointer can be transferred from the memory write circuit 101 to the memory read circuit 201 without error, thereby avoiding erroneous transfer of pointer values.
  • Pointer synchronization can be achieved.
  • by accurately determining whether data can be read in the memory read circuit 201 it becomes possible to transfer correct data between asynchronous clocks via the memory 300.
  • Gray code as in Patent Document 2 is not used, it is no longer necessary to use a memory capacity that is one address larger than the memory capacity accessed when the number of pointers is an odd number, which reduces the increase in circuit size and power consumption. It can be prevented.
  • the write clock WCLK corresponds to an example of the "first clock”
  • the read clock RCLK corresponds to an example of the "second clock”
  • the memory write circuit 101 corresponds to an example of the "second clock.”
  • the memory read circuit 201 corresponds to an embodiment of the "first circuit”
  • the memory read circuit 201 corresponds to an embodiment of the "second circuit”.
  • the write side write pointer 108 is a "first pointer”
  • the write side write pointer generation section 107 is a “first pointer generation section”
  • the read side read pointer synchronization section 109 is a "first pointer”.
  • the write-side read pointer calculation unit 112 corresponds to an embodiment of the “first circuit-side pointer value calculation unit”
  • the write-side coincidence detection unit 113 corresponds to an example of the “first coincidence detection unit”.
  • the write side read pointer 110 corresponds to "the second pointer calculated by the first circuit side pointer value calculation section”
  • the read side read pointer 111 generated by the read side read pointer synchronization section 109 corresponds to "the second pointer calculated by the first circuit side pointer value calculation section”. "The second pointer fetched by the first synchronization unit”.
  • the read-side read pointer 208 is a "second pointer”
  • the read-side read pointer generation section 207 is a “second pointer generation section”
  • the write-side write pointer synchronization section 209 is a "second synchronization section.”
  • the read side write pointer calculation unit 212 corresponds to an example of a “second circuit side pointer value calculation unit”
  • the read side coincidence detection unit 213 corresponds to an example of a “second coincidence detection unit”.
  • the read side write pointer 210 corresponds to "the first pointer calculated by the second circuit side pointer value calculation section”
  • the write side write pointer 211 generated by the write side write pointer synchronization section 209 corresponds to "the first pointer calculated by the second circuit side pointer value calculation section”. "first pointer taken in by the second synchronization unit”.
  • each pointer is incremented every time data is written and every time data is read.
  • this embodiment It is possible to apply memory control related to. In this case, similar memory control can be realized by appropriately replacing "increment” with “decrement” in the description of this embodiment. That is, in this embodiment, each pointer value changes by 1 in a predetermined direction, either increasing or decreasing.
  • the number of data stored in the memory 300 is not output to the outside, but information indicating the number of data stored may be output from the memory control device 100 to the outside.
  • the number of clock cycles required for the operation of each circuit block is not limited to the above description and can be set freely.
  • the pointer transfer according to the present embodiment is applied to both write pointer transfer and read pointer transfer, that is, bidirectional pointer transfer. It is also possible to apply this embodiment to only one of the pointer transfers. For example, if this embodiment is applied only to write pointer transfer, the arrangement of the write-side read pointer calculation section 112 and the write-side coincidence detection section 113 on the write side can be omitted from the configuration example of FIG. can. On the other hand, if this embodiment is applied only to read pointer transfer, the arrangement of the read side write pointer calculation section 212 and the read side coincidence detection section 213 on the read side can be omitted from the configuration example of FIG. I can do it.
  • memory control has been described as involving data writing and reading from the memory 300, but by applying this embodiment only to the part of pointer transfer between asynchronous clocks, this embodiment can be It is also possible to provide a pointer transfer device and a pointer control method according to the embodiment. In this case as well, the pointer transfer device and pointer control method can be configured so that the present embodiment is applied only to one-way pointer transfer out of two-way pointer transfer.
  • 100 Memory control device 101 Memory write circuit, 103 Write side access control unit, 104 Write side write enable, 106 Write side write pointer increment, 107 Write side write pointer generation unit, 108 Write side write pointer, 109 Read side read pointer synchronization conversion unit, 110 write side read pointer, 111 read side read pointer (write circuit side synchronization), 112 write side read pointer calculation unit, 113 write side coincidence detection unit, 114 write side read pointer increment, 201 memory read circuit, 203 Read side access control unit, 204 Read side read enable, 206 Read side read pointer increment, 207 Read side read pointer generation unit, 208 Read side read pointer, 209 Write side write pointer synchronization unit, 210 Read side write pointer, 211 Write side write pointer (read circuit side synchronization), 212 Read side write pointer calculation unit, 213 Read side coincidence detection unit, 214 Read side write pointer increment, 300 Memory, N memory depth, RCLK read clock, RCMD read instruction, RDAT read data, RPRM read permission,

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Abstract

L'invention concerne une unité de synchronisation de pointeur de lecture côté lecture (109) qui synchronise un pointeur de lecture (208) avec une horloge d'écriture (WCLK) et prend en compte le résultat, ledit pointeur de lecture (208) ayant été généré sur le côté d'un circuit de lecture de mémoire (201) qui se synchronise avec une horloge de lecture (RCLK). Une unité de détection d'accord côté écriture (113) effectue une comparaison d'accord entre la valeur d'un pointeur de lecture côté écriture (110), qui est calculée par une unité de calcul de pointeur de lecture côté écriture (112), et la valeur d'un pointeur de lecture côté lecture (111), qui a été prise en compte par l'unité de synchronisation de pointeur de lecture côté lecture (109). Tant que l'unité de détection d'accord côté écriture (113) détecte l'absence d'accord, l'unité de calcul de pointeur de lecture côté écriture (112) change le pointeur de lecture côté écriture (110) d'une unité à chaque cycle de l'horloge d'écriture (WCLK).
PCT/JP2022/010281 2022-03-09 2022-03-09 Dispositif de transfert de pointeur, procédé de transfert de pointeur, et dispositif de commande de mémoire WO2023170815A1 (fr)

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* Cited by examiner, † Cited by third party
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US20130121100A1 (en) * 2011-11-11 2013-05-16 Qualcomm Incorporated Device and method to perform memory operations at a clock domain crossing
JP2014071929A (ja) * 2012-09-28 2014-04-21 Konica Minolta Inc Ｆｉｆｏ回路
US20160124889A1 (en) * 2014-11-03 2016-05-05 Chanpreet Singh Asynchronous fifo buffer with johnson code write pointer

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