WO2023169229A1 - 自动计算转子速度的电路及方法 - Google Patents

自动计算转子速度的电路及方法 Download PDF

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Publication number
WO2023169229A1
WO2023169229A1 PCT/CN2023/078098 CN2023078098W WO2023169229A1 WO 2023169229 A1 WO2023169229 A1 WO 2023169229A1 CN 2023078098 W CN2023078098 W CN 2023078098W WO 2023169229 A1 WO2023169229 A1 WO 2023169229A1
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WIPO (PCT)
Prior art keywords
signal
output
phase
count value
counting
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PCT/CN2023/078098
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English (en)
French (fr)
Inventor
李亚菲
赵旭东
华纯
刘欣洁
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华润微集成电路(无锡)有限公司
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Publication of WO2023169229A1 publication Critical patent/WO2023169229A1/zh

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P3/00—Measuring linear or angular speed; Measuring differences of linear or angular speeds
    • G01P3/64—Devices characterised by the determination of the time taken to traverse a fixed distance
    • G01P3/66—Devices characterised by the determination of the time taken to traverse a fixed distance using electric or magnetic means
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P6/00—Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor position; Electronic commutators therefor
    • H02P6/10—Arrangements for controlling torque ripple, e.g. providing reduced torque ripple
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P6/00—Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor position; Electronic commutators therefor
    • H02P6/14—Electronic commutators
    • H02P6/16—Circuit arrangements for detecting position
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P6/00—Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor position; Electronic commutators therefor
    • H02P6/14—Electronic commutators
    • H02P6/16—Circuit arrangements for detecting position
    • H02P6/17—Circuit arrangements for detecting position and for generating speed information

Definitions

  • the invention relates to the field of motor control, and in particular to a circuit and method for automatically calculating rotor speed.
  • Step 1 Install a Hall sensor in the motor to feedback the position information of the motor rotor;
  • Step 2 Compensate for Hall deviation
  • Step 3 Obtain the time difference between two adjacent transitions of the Hall signal
  • Step 4 Filter the time obtained in step 3;
  • Step 5 Calculate the speed of the rotor based on the change angle of the rotor and the filtered time.
  • the above method relies heavily on the position information of the rotor. If there is a deviation, the calculated rotor speed will be inaccurate. Hall sensors used in the prior art often have some mechanical deviations during installation, which biases the rotor position angle estimation, resulting in inaccurate calculation results. Therefore, the Hall deviation needs to be compensated. Most compensation methods use software compensation, which requires a large number of algorithms such as zero-order Taylor algorithm and Fourier decoupling transform. The implementation process is complicated and difficult. In addition, since external factors such as air and ground roughness will affect the operation of the motor, after obtaining the time difference between two adjacent jumps of the Hall signal, it is necessary to perform RC filtering or average filtering on the time difference to eliminate accidental Error, which requires higher knowledge reserves of software personnel.
  • the software takes a long time to calculate the rotor speed, which is not friendly to functions that require strict time control (such as FOC (field-oriented control) mode); and complex software programs will occupy the CPU for a long time, which is not conducive to other safety issues. control.
  • strict time control such as FOC (field-oriented control) mode
  • complex software programs will occupy the CPU for a long time, which is not conducive to other safety issues. control.
  • the purpose of the present invention is to provide a circuit and method for automatically calculating the rotor speed, which is used to solve the problem that the method of calculating the rotor speed in the prior art relies heavily on the position information of the rotor, and the operation is cumbersome and complicated. It takes a long time to calculate, is not friendly to functions that require strict time control, and occupies the CPU for a long time.
  • the present invention provides a circuit for automatically calculating the rotor speed.
  • the circuit for automatically calculating the rotor speed at least includes:
  • the edge generation module receives U, V, and W three-phase Hall signals, and generates edge response signals for each phase Hall signal;
  • a counting module connected to the output end of the edge generation module, counts the time difference between two adjacent transitions of each phase Hall signal based on the output signal of the edge generation module to obtain each phase count value, Output the current count value and generate a trigger signal when any phase Hall signal transitions;
  • the division module is connected to the output end of the counting module and divides the angle difference between two adjacent transitions of the Hall signal by the current count value to obtain the motor speed.
  • the counting module includes a first counting unit, a second counting unit, a third counting unit, a selection unit, or a logic unit and a flip-flop;
  • the first counting unit, the second counting unit, and the third counting unit receive the counting trigger signal and the corresponding edge response signal, and respectively calculate the time difference between two adjacent transitions of each phase Hall signal. Perform counting to obtain the count value of each phase;
  • the selection unit is connected to the output terminals of the first counting unit, the second counting unit and the third counting unit, and receives each edge response signal; when more than two phases of Hall signals jump at the same time, according to The priority order of U, V, and W outputs the count value corresponding to the Hall signal of the corresponding phase as the current count value; when the Hall signal of each phase jumps respectively, the count value corresponding to the jump is output as the current count value. ;
  • the OR logic unit receives each edge response signal and performs OR logic operations
  • the flip-flop is connected to the output end of the OR logic unit, and when the output signal of the OR logic unit is valid, the flip-flop outputs the trigger signal.
  • the first counting unit, the second counting unit or the third counting unit include a first selector, a second selector, a first D flip-flop and an adder;
  • the first input terminal of the first selector is connected to the output terminal of the first D flip-flop, the second input terminal is connected to the output terminal of the adder, and the control terminal is connected to the counting trigger signal;
  • the first input terminal of the second selector is connected to the output terminal of the first selector, the second input terminal is connected to a low level signal, and the control terminal is connected to the edge response signal of the corresponding phase Hall signal;
  • the data input terminal of the first D flip-flop is connected to the output terminal of the second selector
  • the input end of the adder is respectively connected to the output end of the first D flip-flop and the high-level signal.
  • the selection unit includes a third selector, a fourth selector and a fifth selector;
  • the first input terminal of the third selector is connected to a low level signal, the second input terminal is connected to the output terminal of the first counting unit, and the control terminal is connected to the edge response signal of the W-phase Hall signal;
  • the first input terminal of the fourth selector is connected to the output terminal of the third selector, the second input terminal is connected to the output terminal of the second counting unit, and the control terminal is connected to the edge response signal of the V-phase Hall signal;
  • the first input terminal of the fifth selector is connected to the output terminal of the fourth selector, the second input terminal is connected to the output terminal of the third counting unit, and the control terminal is connected to the edge response signal of the U-phase Hall signal;
  • the counting module further includes a filtering unit; the filtering unit is connected to the output end of the selection unit and the OR logic unit, and receives the upper counting limit value and the lower counting limit value; when any phase When the Er signal transitions and the current count value is between the upper counting limit value and the lower counting limit value, the current count value is output.
  • the filtering unit includes a first comparator, a second comparator, an AND logic gate, a sixth selector and a second D flip-flop;
  • the input terminal of the first comparator is respectively connected to the output terminal of the selection unit and the filtering lower limit value, and outputs the first comparison result
  • the input terminal of the second comparator is respectively connected to the output terminal of the selection unit and the filtering upper limit value, and outputs a second comparison result
  • the input terminals of the AND logic gate are respectively connected to the output terminals of the first comparator, the second comparator and the OR logic unit; when the current count value is greater than or equal to the filtering lower limit value, less than or equal to The filtering upper limit value, and when any phase Hall signal jumps, the AND logic gate outputs a valid filtering control signal;
  • the first input terminal of the sixth selector is connected to the output terminal of the second D flip-flop, the second input terminal is connected to the output terminal of the selection unit, and the control terminal is connected to the output terminal of the AND logic gate;
  • the sixth selector selects the output signal output of the selection unit;
  • the filtering control signal is invalid, the sixth selector selects the output signal output of the second D flip-flop;
  • the data input terminal of the second D flip-flop is connected to the output terminal of the sixth selector, and the filtered current count value is output.
  • the filtering lower limit value and the filtering upper limit value are provided by a register.
  • the angle difference between two adjacent transitions of the Hall signal is 180°.
  • the present invention also provides a method for automatically calculating the rotor speed.
  • the method for automatically calculating the rotor speed at least includes:
  • the edge response signal includes a rising edge response signal and a falling edge response signal.
  • step 2) count the time difference between two adjacent transitions of the Hall signal of each phase; when more than two phases of Hall signals transition at the same time, the time difference is counted according to the priority of U, V, and W.
  • the stages sequentially output the count value corresponding to the Hall signal of the corresponding phase as the current count value; when the Hall signal of each phase jumps respectively, the count value corresponding to the jump is output as the current count value.
  • step 2) also includes the step of filtering the current count value and outputting it.
  • the filtering method includes: when any phase Hall signal transitions and the current count value is between the upper counting limit value and the lower counting limit value, outputting the current count value, otherwise filtering out .
  • circuit and method for automatically calculating the rotor speed of the present invention have the following beneficial effects:
  • the circuit and method for automatically calculating the rotor speed of the present invention is based on the hardware circuit and uses the jump of the Hall signal of the same phase to calculate the rotation speed, and uses the register writing method to filter the time difference; it does not rely on the rotor position information, and the rotation speed calculation is accurate; the operation is convenient and simple, and the The requirements for technical personnel are not high, which can reduce development time; no complex software programs are required, and CPU resources are small; it is applicable to a wide range of scenarios and is suitable for ideal situations, Hall deviation situations and phase loss situations.
  • Figure 1 shows a schematic diagram of the relationship between the rotor angle and the three-phase Hall signal under ideal conditions.
  • Figure 2 shows a schematic diagram of the relationship between the rotor angle and the three-phase Hall signal in the presence of Hall deviation.
  • Figure 3 shows a schematic diagram of the relationship between the rotor angle and the three-phase Hall signal in the case of phase loss.
  • Figure 4 shows a schematic structural diagram of a circuit for automatically calculating the rotor speed of the present invention.
  • Figure 5 shows a schematic structural diagram of the counting module of the present invention.
  • Figure 6 shows a schematic structural diagram of the first counting unit of the present invention.
  • Three Hall sensors are evenly arranged on the integrated circuit board at the end of the motor according to an electrical angle of 120° to feed back the position information of the motor rotor.
  • the Hall sensors generate a logic level of 0 or 1 according to the polarity of the magnetic pole piece in the corresponding area.
  • the three-phase Hall signals ⁇ U, V, W ⁇ change periodically in the sequence of 5, 4, 6, 2, 3, and 1.
  • the angle difference between each two adjacent Hall signals is 60°, as shown in Figure 1, where PHU is the U-phase Hall signal, PHV is the V-phase Hall signal, and PHW is the W-phase Hall signal. .
  • the Hall signal will lead or lag, making the angle difference between two adjacent Hall signals greater than 60° or less than 60°, as shown in Figure 2, where the V-phase Hall The signal PHV lags behind, and the W-phase Hall signal PHW leads. Therefore, it is inaccurate to calculate the rotor speed using the angle difference and time difference between two adjacent jumps of the Hall signal.
  • phase loss as shown in Figure 3, the W-phase Hall signal PHW loses phase, and the angle difference between two adjacent Hall signals is no longer 60°, but becomes 120°, 60°, 120°, the calculated rotor speed at this time is also wrong and cannot be used.
  • the angle difference between two adjacent jumps of the same Hall signal is fixed, as shown in Figure 1 and Figure 2, whether it is an ideal situation or In the case of leading or lagging, the angle difference between two adjacent jumps of the U-phase Hall signal PHU is 180°, and the same is true for the V-phase Hall signal PHV and the W-phase Hall signal PHW. In the case of phase loss, except for the W-phase Hall signal PHW, the angle difference between the two adjacent jumps of the other two phases is 180°.
  • the invention calculates the rotor speed based on the angle difference and time difference between two adjacent jumps of the same Hall signal to obtain accurate rotor speed, avoids the complex procedure of compensating the Hall deviation, and is simple and convenient to operate. Specific aspects of the present invention are as follows.
  • this embodiment provides a circuit 1 for automatically calculating the rotor speed.
  • the circuit 1 for automatically calculating the rotor speed includes:
  • the edge generation module 11 receives U, V, and W three-phase Hall signals, and generates corresponding edge response signals for each phase Hall signal.
  • the edge generation module 11 receives the U-phase Hall signal PHU, the V-phase Hall signal PHV, and the W-phase Hall signal PHW.
  • the edge generation module 11 generates a signal on the rising edge and falling edge of the W-phase Hall signal PHW. respond and generate the first edge response signal Wchg; respond to the rising edge and falling edge of the V-phase Hall signal PHV, and generate the second edge response signal Vchg; respond to the rising edge of the U-phase Hall signal PHU and falling edge to respond, and generate the third edge response signal Uchg.
  • Any circuit structure that can realize double-edge (rising edge and falling edge) detection is applicable to the present invention, and will not be described in detail here.
  • a corresponding pulse signal is generated as an edge response signal.
  • the counting module 12 is connected to the output end of the edge generating module 11, and based on the output signal of the edge generating module 11, the count module 12 calculates the interval between two adjacent transitions of each phase Hall signal. The time difference is counted to obtain the count value of each phase, the current count value is output, and the trigger signal DivTrig is generated when the Hall signal of any phase transitions.
  • the counting module 12 includes a first counting unit 121, a second counting unit 122, a third counting unit 123, a selection unit 124, or a logic unit 125 and a flip-flop. 126.
  • the first counting unit 121 , the second counting unit 122 , and the third counting unit 123 receive the counting trigger signal Cnt_trig and the corresponding edge response signal, and respond to each phase signal respectively.
  • the time difference between two adjacent transitions of each Hall signal is counted; wherein, the first counting unit 121 receives the first edge response signal Wchg and the counting trigger signal Cnt_trig, and counts the adjacent W-phase Hall signal PHW.
  • the time difference between two transitions is counted; the second counting unit 122 receives the second edge response signal Vchg and the counting trigger signal Cnt_trig, and counts the time difference between two adjacent transitions of the V-phase Hall signal PHV.
  • the third counting unit 123 receives the third edge response signal Uchg and the counting trigger signal Cnt_trig, and counts the time difference between two adjacent transitions of the U-phase Hall signal PHU.
  • the first counting unit 121 includes a first selector 12a, a second selector 12b, a first D flip-flop 12c and an adder 12d; The input terminal is connected to the output terminal of the first D flip-flop 12c, the second input terminal is connected to the output terminal of the adder 12d, and the control terminal is connected to the counting trigger signal Cnt_trig; the first input of the second selector 12b The terminal is connected to the output terminal of the first selector 12a, the second input terminal is connected to the low level signal "0", the control terminal is connected to the first edge response signal Wchg; the data input terminal of the first D flip-flop 12c D is connected to the output terminal of the second selector 12b; the input terminal of the adder 12d is respectively connected to the output terminal
  • the structure of the second counting unit 122 and the third counting unit 123 is the same as that of the first counting unit 121, except that the control end of the second selector 12b in the second counting unit 122 Receive the second edge response signal Vchg, and finally output the V-phase count value V_Cnt; the control terminal of the second selector 12b in the third counting unit 123 receives the third edge response signal Uchg, and finally output the U-phase count value. U_Cnt; The specific structure will not be detailed here.
  • any circuit structure that can count the time difference between two adjacent transitions of the Hall signal is applicable to the present invention; further, the first counting unit 121 and the second counting unit
  • the structures of 122 and the third counting unit 123 may also be different, and are not limited to this embodiment.
  • the selection unit 124 is connected to the output terminals of the first counting unit 121 , the second counting unit 122 and the third counting unit 123 , and receives each edge response signal. ;When more than two phases of Hall signals jump at the same time, the count value corresponding to the Hall signal of the corresponding phase is output according to the priority order of U, V, and W (U phase has the highest priority, followed by V phase, and finally W phase) As the current count value UVW_Cnt (for example, if the U phase and V phase jump at the same time, then the count value corresponding to the U phase Hall signal is output as the current count value UVW_Cnt); when the Hall signals of each phase jump respectively, the output jumps accordingly The count value is used as the current count value UVW_Cnt.
  • the selection unit 124 includes a third selector 12e, a fourth selector 12f and a fifth selector 12g; the first input end of the third selector 12e is connected to the low level signal "0", and the second The input terminal is connected to the W-phase count value W_Cnt output by the first counting unit 121, the control terminal is connected to the first edge response signal Wchg; the first input terminal of the fourth selector 12f is connected to the third selector 12e The output terminal of the second input terminal is connected to the V-phase count value V_Cnt output by the second counting unit 122, and the control terminal is connected to the second edge response signal Vchg; The output terminal of the fourth selector 12f, the second input terminal is connected to the U-phase count value U_Cnt output by the third counting unit 123, the control terminal is connected to the third edge response signal Uchg, and the selection unit 124 finally outputs The current count value UVW_Cnt; wherein, when the control signal of each selector is valid, the signal
  • any circuit structure that can realize the above functions is applicable to the selection unit of the present invention, and is not limited to this embodiment.
  • the U, V, and W three-phase Hall signals jump alternately and periodically, and the count values corresponding to the Hall signals of each phase are output in the order of jumps; in the case of one phase missing, the count values corresponding to the Hall signals of each phase are output in the order of jumps.
  • the count value corresponding to the Hall signal that has not lost phase is output in sequence; in the case of two phases being lost, the count value corresponding to the Hall signal that has not lost phase is output.
  • the OR logic unit 125 receives each edge response signal and performs an OR logic operation; when the first edge response signal Wchg, the second edge response signal Vchg and the third edge response signal Vchg When any one of the three edge response signals Uchg is valid, the output signal of the OR logic unit 125 is valid (high level valid).
  • the OR logic unit 125 is implemented using a three-input OR gate. In actual use, the OR logic can be implemented based on multiple logic elements, which is not limited to this embodiment.
  • the flip-flop 126 is connected to the output end of the OR logic unit 125 .
  • the flip-flop 126 outputs the trigger signal. DivTrig; that is, when any phase Hall signal jumps, the trigger signal DivTrig is valid.
  • the counting module 12 also includes a filter Wave unit 127, the filter unit 127 is connected to the output end of the selection unit 124 and the OR logic unit 125, and receives the upper counting limit value rp_LmtH and the lower counting limit value rp_LmtL.
  • the filter unit 127 is connected to the output end of the selection unit 124 and the OR logic unit 125, and receives the upper counting limit value rp_LmtH and the lower counting limit value rp_LmtL.
  • the filter unit 127 is connected to the output end of the selection unit 124 and the OR logic unit 125, and receives the upper counting limit value rp_LmtH and the lower counting limit value rp_LmtL.
  • the filtering unit 127 includes a first comparator 12h, a second comparator 12i, an AND logic gate 12j, a sixth selector 12k and a second D flip-flop 12l; the input terminals of the first comparator 12h are respectively The output terminal of the selection unit 124 is connected to the filtering lower limit value rp_LmtL, and the first comparison result is output; the input terminal of the second comparator 12i is respectively connected to the output terminal of the selection unit 124 and the filtering upper limit value rp_LmtL.
  • the input terminals of the AND logic gate 12j are respectively connected to the output terminals of the first comparator 12h, the second comparator 12i and the OR logic unit 125.
  • the current count value UVW_Cnt is greater than or equal to the filtering lower limit value rp_LmtL and less than or equal to the filtering upper limit value rp_LmtH, and when any phase Hall signal jumps, a valid filtering control signal is output;
  • the sixth selector 12k The first input terminal is connected to the output terminal of the second D flip-flop 12l, the second input terminal is connected to the output terminal of the selection unit 124, the control terminal is connected to the output terminal of the AND logic gate 12j, and the filtered control signal is valid.
  • the sixth selector 12k selects the output signal output of the selection unit 124, when the filter control signal is invalid, the sixth selector 12k selects the output signal output of the second D flip-flop 12l;
  • the data input terminal D of the second D flip-flop 12l is connected to the output terminal of the sixth selector 12k, and outputs the filtered current count value Divisor.
  • the filtering lower limit value rp_LmtL and the filtering upper limit value rp_LmtH are provided by a register.
  • the register is set in the central processor 14, as shown in FIG. 4 .
  • the location of the register can be set as needed. Any circuit structure that can realize the above filtering function is applicable to the present invention and is not limited to this embodiment.
  • the present invention only needs to configure two registers to eliminate unreasonable count values to achieve the purpose of filtering. It does not require complex software programs, is easy to operate, has short calculation time, and can also reduce CPU occupancy time.
  • the dividing module 13 is connected to the output end of the counting module 12, and divides the angle difference between two adjacent transitions of the Hall signal by the count value output by the counting module 12 to obtain Get the motor speed Result.
  • the angle difference between two adjacent transitions of the Hall signal is 180°.
  • the trigger signal DivTrig is valid (as an example, the trigger signal DivTrig is active at high level)
  • the adjacent Hall signal transitions are The motor speed Result can be obtained by dividing the angle difference between two jumps by the time difference between two adjacent jumps of the same Hall signal.
  • the implementation method of the trigger module is not limited and will not be described in detail here.
  • the count value output by the counting module 12 is the filtered current count value Divisor. In actual use, the count value output by the counting module 12 may also be the current count value UVW_Cnt.
  • the installation positions of the three Hall sensors are accurate, and all three phases of UVW are working normally.
  • the Hall signal can accurately reflect the position information of the rotor.
  • the angle difference between two adjacent jumps of each phase of UVW They are all 180°.
  • the three-phase count values U_Cnt, V_Cnt, and W_Cnt are all normal.
  • the rotation speed can be accurately calculated six times in one cycle of motor operation.
  • phase count values U_Cnt, V_Cnt, and W_Cnt are all normal, and the rotation speed can be accurately calculated six times in one cycle of motor operation.
  • phase loss if U phase loses phase, V phase and W phase are working, then the angle difference between two adjacent jumps of each phase of V phase and W phase is 180°, V phase and W phase The count values V_Cnt and W_Cnt are normal, and the rotation speed can be accurately calculated four times in one cycle of motor operation. If the U phase and V phase are out of phase and the W phase is working, the angle difference between two adjacent jumps of the W phase is 180°, the count value W_Cnt of the W phase is normal, and can be accurately calculated within one cycle of the motor operation. 2 rpm.
  • the present invention is flexible and quick to operate and has a wide range of applications. It is not only suitable for ideal situations, but also for Hall deviation and phase loss situations.
  • This embodiment provides a method for automatically calculating the rotor speed.
  • the method for automatically calculating the rotor speed is implemented based on the circuit for automatically calculating the rotor speed in Embodiment 1.
  • any hardware that can implement this method can or software device.
  • the method for automatically calculating the rotor speed at least includes:
  • each phase Hall signal corresponds to an edge response signal
  • the edge response signal includes a rising edge response signal and a falling edge response signal.
  • a pulse signal is generated, where the transition of the Hall signal includes a rising edge transition and a falling edge transition, that is, the Hall signal transitions to a rising edge or to a falling edge.
  • Each edge will generate corresponding pulse signals.
  • the time difference between two adjacent transitions of each phase Hall signal is counted respectively. For any phase Hall signal, counting starts when the current pulse of the edge response signal is received, and when the next pulse is received Counting is restarted when pulse occurs, and so on, and the counting value is continuously updated.
  • the current count value UVW_Cnt is obtained by selecting the output sequence of each phase count value.
  • the phases are output in the order of priority of U, V, and W.
  • the count value corresponding to the Hall signal as an example, when the three-phase Hall signal jumps at the same time, the U-phase count value is output; when the U-phase and V jump when the same, the U-phase count value is output; when the U-phase sum When W jumps when they are the same, the U-phase count value is output; when V phase and W jump when they are the same, the V-phase count value is output. Under normal conditions, more than two phases of Hall signals will not jump at the same time.
  • the Hall signals of each phase will jump.
  • the signals jump individually.
  • the count value corresponding to the jump is output; that is, if any phase Hall signal is output and jumps, the count value corresponding to the Hall signal of that phase is output.
  • the present invention also includes the step of filtering and outputting the current count value UVW_Cnt.
  • the current count value will be output, otherwise it will be filtered out; thereby improving the final result accuracy.
  • the upper counting limit value rp_LmtH and the lower counting limit value rp_LmtL are provided by registers. Software personnel do not need to write complex filtering software programs based on motor theory and mathematical theory, and the operation is convenient and simple.
  • the angle difference between two adjacent jumps of the Hall signal is 180°. Divide 180° by the current count value to obtain the current motor speed Result.
  • This method calculates the motor speed based on the signal of the same Hall sensor, does not rely on the position information of the rotor, and does not affect the accuracy of the rotor speed calculation; in addition, even if two Hall sensors are out of phase, as long as one Hall sensor is working The rotor speed can be accurately calculated, so the application of the present invention is wider.
  • step 2 180° is divided by the filtered current count value Divisor in step 3), which will not be described again here.
  • the present invention provides a circuit and method for automatically calculating the rotor speed.
  • the circuit includes: an edge generation module for receiving U, V, and W three-phase Hall signals and generating respectively for each phase Hall signal. edge response signal; a counting module, connected to the output end of the edge generation module, counting the time difference between two adjacent transitions of each phase Hall signal based on the output signal of the edge generation module to obtain each The phase count value outputs the current count value and generates a trigger signal when any phase Hall signal transitions; the division module is connected to the output end of the counting module and divides the difference between two adjacent transitions of the Hall signal. The angle difference is divided by the current count value to obtain the motor speed.
  • the circuit and method for automatically calculating the rotor speed of the present invention is based on the hardware circuit and uses the jump of the Hall signal of the same phase to calculate the rotation speed, and uses the register writing method to filter the time difference; it does not rely on the rotor position information, and the rotation speed calculation is accurate; the operation is convenient and simple, and the The requirements for technical personnel are not high, which can reduce development time; no complex software programs are required, and the CPU takes up less resources; suitable for It is used in a wide range of scenarios and is suitable for ideal situations, Hall deviation situations and phase loss situations. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

Abstract

本发明提供一种自动计算转子速度的电路及方法，该电路包括：边沿产生模块，用于接收U、V、W三相霍尔信号，并针对各相霍尔信号分别产生边沿响应信号；计数模块，连接于所述边沿产生模块的输出端，基于所述边沿产生模块的输出信号分别对各相霍尔信号各自的相邻两次跳变之间的时间差进行计数得到各相计数值，输出当前计数值，并在任意相霍尔信号跳变时产生触发信号；除法模块，连接于所述计数模块的输出端，将霍尔信号的相邻两次跳变之间的角度差除以所述当前计数值，以得到电机转速。本发明转速计算准确、操作方便简单、开发时间少、CPU占用资源少、适用场景广泛。

Description

自动计算转子速度的电路及方法
相关申请的交叉引用
本申请要求于2022年3月9日提交中国专利局、申请号为202210225740.X、发明名称为“自动计算转子速度的电路及方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及电机控制领域，特别是涉及一种自动计算转子速度的电路及方法。
背景技术
现有技术大多采用软件计算电机的转子速度，包括如下步骤：
步骤一、在电机中安装霍尔传感器用于反馈电机转子的位置信息；
步骤二、补偿霍尔偏差；
步骤三、获取霍尔信号相邻两次跳变之间的时间差；
步骤四、对步骤三获取的时间进行滤波；
步骤五、根据转子的改变角度和滤波后的时间计算转子的速度。
上述方法严重依赖转子的位置信息，若有偏差，计算出来的转子速度就不准确。现有技术中使用的霍尔传感器在安装时往往会存在一些机械偏差，使转子位置角估计产生偏差，从而导致计算结果不准确，因此需要对霍尔偏差进行补偿。补偿方法大多采用软件补偿，需要做零阶泰勒算法、傅里叶解耦变换等大量算法，实现过程比较复杂困难。此外，由于空气、地面粗糙度等外部因素会对电机的运转产生影响，因此，获取霍尔信号相邻两次跳变之间的时间差后，还需要对时间差进行RC滤波或平均滤波以消除偶然误差，这对软件人员的知识储备要求较高。
进一步地，软件计算转子速度的时间较长，对于需要严格把控时间的功能(例如FOC(磁场定向控制)模式)不友好；而且复杂的软件程序还会长时间地占用CPU，不利于其它安全控制。
因此，如何克服以上问题已成为本领域技术人员亟待解决的问题之一。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种自动计算转子速度的电路及方法，用于解决现有技术中计算转子速度的方法严重依赖转子的位置信息、操作麻烦复杂、计算时间较长，对于需要严格把控时间的功能不友好、长时间占用CPU等问题。
为实现上述目的及其他相关目的，本发明提供一种自动计算转子速度的电路，所述自动计算转子速度的电路至少包括：
边沿产生模块，接收U、V、W三相霍尔信号，并针对各相霍尔信号分别产生边沿响应信号；
计数模块，连接于所述边沿产生模块的输出端，基于所述边沿产生模块的输出信号分别对各相霍尔信号各自的相邻两次跳变之间的时间差进行计数得到各相计数值，输出当前计数值，并在任意相霍尔信号跳变时产生触发信号；
除法模块，连接于所述计数模块的输出端，将霍尔信号的相邻两次跳变之间的角度差除以所述当前计数值，以得到电机转速。
可选地，所述计数模块包括第一计数单元、第二计数单元、第三计数单元、选择单元、或逻辑单元及触发器；
所述第一计数单元、所述第二计数单元、所述第三计数单元接收计数触发信号及对应的边沿响应信号，分别对各相霍尔信号的各自相邻两次跳变之间的时间差进行计数得到各相计数值；
所述选择单元连接于所述第一计数单元、所述第二计数单元及所述第三计数单元的输出端，并接收各边沿响应信号；当两相以上霍尔信号同时跳变时，按照U、V、W的优先级顺序输出相应相霍尔信号对应的计数值作为所述当前计数值；当各相霍尔信号分别跳变时，输出跳变相对应的计数值作为所述当前计数值；
所述或逻辑单元接收各边沿响应信号，并执行或逻辑运算；
所述触发器连接于所述或逻辑单元的输出端，当所述或逻辑单元的输出信号有效时，所述触发器输出所述触发信号。
可选地，所述第一计数单元、所述第二计数单元或所述第三计数单元包括第一选择器、第二选择器、第一D触发器及加法器；
所述第一选择器的第一输入端连接所述第一D触发器的输出端，第二输入端连接所述加法器的输出端，控制端连接所述计数触发信号；
所述第二选择器的第一输入端连接所述第一选择器的输出端，第二输入端连接低电平信号，控制端连接对应相霍尔信号的边沿响应信号；
所述第一D触发器的数据输入端连接所述第二选择器的输出端；
所述加法器的输入端分别连接所述第一D触发器的输出端及高电平信号，当所述第一D触发器的输出信号有效时执行加一操作，并输出对应相计数值；
其中，各选择器的控制信号有效时选择第二输入端的信号输出，控制信号无效时选择第一输入端的信号输出。
更可选地，所述选择单元包括第三选择器、第四选择器及第五选择器；
所述第三选择器的第一输入端连接低电平信号，第二输入端连接所述第一计数单元的输出端，控制端连接W相霍尔信号的边沿响应信号；
所述第四选择器的第一输入端连接所述第三选择器的输出端，第二输入端连接所述第二计数单元的输出端，控制端连接V相霍尔信号的边沿响应信号；
所述第五选择器的第一输入端连接所述第四选择器的输出端，第二输入端连接所述第三计数单元的输出端，控制端连接U相霍尔信号的边沿响应信号；
其中，各选择器的控制信号有效时选择第二输入端的信号输出，控制信号无效时选择第一输入端的信号输出。
更可选地，所述计数模块还包括滤波单元；所述滤波单元连接于所述选择单元及所述或逻辑单元的输出端，并接收计数上限值及计数下限值；当任意相霍尔信号跳变且所述当前计数值介于所述计数上限值和所述计数下限值之间时，将所述当前计数值输出。
更可选地，所述滤波单元包括第一比较器、第二比较器、与逻辑门、第六选择器及第二D触发器；
所述第一比较器的输入端分别连接所述选择单元的输出端及滤波下限值，并输出第一比较结果；
所述第二比较器的输入端分别连接所述选择单元的输出端及滤波上限值，并输出第二比较结果；
所述与逻辑门的输入端分别连接所述第一比较器、所述第二比较器及所述或逻辑单元的输出端；当所述当前计数值大于等于所述滤波下限值、小于等于所述滤波上限值，且任意相霍尔信号跳变时，所述与逻辑门输出有效的滤波控制信号；
所述第六选择器的第一输入端连接所述第二D触发器的输出端，第二输入端连接所述选择单元的输出端，控制端连接所述与逻辑门的输出端；所述滤波控制信号有效时，所述第六选择器选择所述选择单元的输出信号输出，所述滤波控制信号无效时，所述第六选择器选择所述第二D触发器的输出信号输出；
所述第二D触发器的数据输入端连接所述第六选择器的输出端，输出滤波后的当前计数值。
更可选地，所述滤波下限值及所述滤波上限值由寄存器提供。
可选地，霍尔信号的相邻两次跳变之间的角度差为180°。
为实现上述目的及其他相关目的，本发明还提供一种自动计算转子速度的方法，所述自动计算转子速度的方法至少包括：
1)分别产生U、V、W三相霍尔信号的边沿响应信号；
2)基于各相霍尔信号的边沿响应信号分别对各相霍尔信号的相邻两次跳变之间的时间差进行计数得到各相计数值，并输出当前计数值；
3)将霍尔信号的相邻两次跳变之间的角度差除以所述当前计数值，计算得到电机转速。
可选地，步骤1)中，所述边沿响应信号包括上升沿响应信号及下降沿响应信号。
可选地，步骤2)中，分别对各相霍尔信号的相邻两次跳变之间的时间差进行计数；当两相以上霍尔信号同时跳变时，按照U、V、W的优先级顺序输出相应相霍尔信号对应的计数值作为所述当前计数值；当各相霍尔信号分别跳变时，输出跳变相对应的计数值作为所述当前计数值。
更可选地，步骤2)中还包括对所述当前计数值滤波后输出的步骤。
更可选地，滤波方法包括：当任意相霍尔信号跳变且所述当前计数值介于计数上限值和计数下限值之间时，将所述当前计数值输出，否者滤除。
如上所述，本发明的自动计算转子速度的电路及方法，具有以下有益效果：
本发明的自动计算转子速度的电路及方法基于硬件电路采用同一相霍尔信号的跳变计算转速，采用寄存器写入的方式滤波时间差；不依赖转子位置信息，转速计算准确；操作方便简单，对技术人员要求不高，可以减少开发时间；不需要复杂的软件程序，CPU占用资源少；适用场景广泛，适用于理想情况、霍尔偏差的情况及掉相的情况。
附图说明
图1显示为理想情况下转子角度与三相霍尔信号之间的关系示意图。
图2显示为存在霍尔偏差情况下转子角度与三相霍尔信号之间的关系示意图。
图3显示为掉相情况下转子角度与三相霍尔信号之间的关系示意图。
图4显示为本发明的自动计算转子速度的电路的结构示意图。
图5显示为本发明的计数模块的结构示意图。
图6显示为本发明的第一计数单元的结构示意图。
元件标号说明
1                 自动计算转子速度的电路
11                边沿产生模块
12                计数模块
121               第一计数单元
12a               第一选择器
12b               第二选择器
12c               第一D触发器
12d               加法器
122               第二计数单元
123               第三计数单元
124               选择单元
12e               第三选择器
12f               第四选择器
12g               第五选择器
125               或逻辑单元
126               触发器
127               滤波单元
12h               第一比较器
12i               第二比较器
12j               与逻辑门
12k               第六选择器
12l               第二D触发器
13                除法模块
14                中央处理器
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1～图6。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
3个霍尔传感器按照120°电角度均匀排列在电机端部的集成电路板上用于反馈电机转子的位置信息，霍尔传感器根据所对应区域磁极片的极性产生0或1逻辑电平，电机旋转时三相霍尔信号{U,V,W}按5，4，6，2，3，1的顺序周期变化。理论上每相邻两个霍尔信号之间的角度差为60°，如图1所示，其中，PHU为U相霍尔信号，PHV为V相霍尔信号，PHW为W相霍尔信号。然而由于霍尔偏差，霍尔信号会出现超前或滞后的现象，使相邻两个霍尔信号之间的角度差大于60°或小于60°，如图2所示，其中，V相霍尔信号PHV滞后，W相霍尔信号PHW超前。因此采用霍尔信号相邻两次跳变之间的角度差和时间差计算转子的速度是不准确的。另外，对于掉相的情况，如图3所示，W相霍尔信号PHW掉相，相邻两个霍尔信号之间的角度差不再是60°，变成了120°、60°、120°，此时计算得到的转子速度也是有误的，不可以被采用。
但是无论3个霍尔传感器之间的霍尔偏差有多大，同一个霍尔信号相邻两次跳变之间的角度差是固定的，如图1及图2所示，无论是理想情况还是超前或滞后的情况，U相霍尔信号PHU相邻两次跳变之间的角度差均为180°，V相霍尔信号PHV和W相霍尔信号PHW也是如此。而对于掉相的情况，除掉相的W相霍尔信号PHW外，其它两相各自的相邻两次跳变之间的角度差均为180°。
本发明基于同一个霍尔信号相邻两次跳变之间的角度差和时间差计算转子的速度，以获得准确的转子速度，避免了补偿霍尔偏差的复杂程序，操作简单方便。本发明的具体方案如下所示。
实施例一
如图4所示，本实施例提供一种自动计算转子速度的电路1，所述自动计算转子速度的电路1包括：
边沿产生模块11、计数模块12及除法模块13。
如图4所示，所述边沿产生模块11接收U、V、W三相霍尔信号，并针对各相霍尔信号分别产生相应的边沿响应信号。
具体地，所述边沿产生模块11接收U相霍尔信号PHU、V相霍尔信号PHV及W相霍尔信号PHW。所述边沿产生模块11对所述W相霍尔信号PHW的上升沿及下降沿进行 响应，并产生第一边沿响应信号Wchg；对所述V相霍尔信号PHV的上升沿及下降沿进行响应，并产生第二边沿响应信号Vchg；对所述U相霍尔信号PHU的上升沿及下降沿进行响应，并产生第三边沿响应信号Uchg。任意能实现双沿(上升沿和下降沿)检测的电路结构均适用于本发明，在此不一一赘述。作为示例，当霍尔信号跳变时，产生一相应的脉冲信号作为边沿响应信号。
如图4所示，所述计数模块12连接于所述边沿产生模块11的输出端，基于所述边沿产生模块11的输出信号分别对各相霍尔信号各自的相邻两次跳变之间的时间差进行计数以得到各相计数值，输出当前计数值，并在任意相霍尔信号跳变时产生触发信号DivTrig。
具体地，如图5所示，在本实施例中，所述计数模块12包括第一计数单元121、第二计数单元122、第三计数单元123、选择单元124、或逻辑单元125及触发器126。
更具体地，如图5所示，所述第一计数单元121、所述第二计数单元122、所述第三计数单元123接收计数触发信号Cnt_trig及对应的边沿响应信号，分别对各相霍尔信号各自的相邻两次跳变之间的时间差进行计数；其中，所述第一计数单元121接收第一边沿响应信号Wchg及所述计数触发信号Cnt_trig，对W相霍尔信号PHW相邻两次跳变之间的时间差进行计数；所述第二计数单元122接收第二边沿响应信号Vchg及所述计数触发信号Cnt_trig，对V相霍尔信号PHV相邻两次跳变之间的时间差进行计数；所述第三计数单元123接收第三边沿响应信号Uchg及所述计数触发信号Cnt_trig，对U相霍尔信号PHU相邻两次跳变之间的时间差进行计数。作为示例，如图6所示，所述第一计数单元121包括第一选择器12a、第二选择器12b、第一D触发器12c及加法器12d；所述第一选择器12a的第一输入端连接所述第一D触发器12c的输出端，第二输入端连接所述加法器12d的输出端，控制端连接所述计数触发信号Cnt_trig；所述第二选择器12b的第一输入端连接所述第一选择器12a的输出端，第二输入端连接低电平信号“0”，控制端连接所述第一边沿响应信号Wchg；所述第一D触发器12c的数据输入端D连接所述第二选择器12b的输出端；所述加法器12d的输入端分别连接所述第一D触发器12c的输出端及高电平信号“1”，当所述第一D触发器12c的输出信号有效时执行加一操作，所述加法器12d输出W相计数值W_Cnt；各选择器的控制信号有效时选择第二输入端的信号输出，控制信号无效时选择第一输入端的信号输出。所述第二计数单元122及所述第三计数单元123的结构与所述第一计数单元121的结构相同，不同之处在于，所述第二计数单元122中第二选择器12b的控制端接收所述第二边沿响应信号Vchg，最终输出V相计数值V_Cnt；所述第三计数单元123中第二选择器12b的控制端接收所述第三边沿响应信号Uchg，最终输出U相计数值U_Cnt；具体结构在此不一一赘述。
需要说明的是，任意能实现对霍尔信号相邻两次跳变之间的时间差进行计数的电路结构均适用于本发明；进一步地，所述第一计数单元121、所述第二计数单元122及所述第三计数单元123的结构也可不相同，不以本实施例为限。
更具体地，如图5所示，所述选择单元124连接于所述第一计数单元121、所述第二计数单元122及所述第三计数单元123的输出端，并接收各边沿响应信号；当两相以上霍尔信号同时跳变时，按照U、V、W的优先级顺序(U相优先级最高、其次是V相，最后是W相)输出相应相霍尔信号对应的计数值作为当前计数值UVW_Cnt(例如，U相和V相同时跳变，则输出U相霍尔信号对应的计数值作为当前计数值UVW_Cnt)；当各相霍尔信号分别跳变时，输出跳变相对应的计数值作为当前计数值UVW_Cnt。作为示例，所述选择单元124包括第三选择器12e、第四选择器12f及第五选择器12g；所述第三选择器12e的第一输入端连接低电平信号“0”，第二输入端连接所述第一计数单元121输出的W相计数值W_Cnt，控制端连接所述第一边沿响应信号Wchg；所述第四选择器12f的第一输入端连接所述第三选择器12e的输出端，第二输入端连接所述第二计数单元122输出的V相计数值V_Cnt，控制端连接所述第二边沿响应信号Vchg；所述第五选择器12g的第一输入端连接所述第四选择器12f的输出端，第二输入端连接所述第三计数单元123输出的U相计数值U_Cnt，控制端连接所述第三边沿响应信号Uchg，并且所述选择单元124最终输出所述当前计数值UVW_Cnt；其中，各选择器的控制信号有效时选择第二输入端的信号输出，控制信号无效时选择第一输入端的信号输出。
需要说明的是，任意能实现上述功能的电路结构均适用于本发明的选择单元，不以本实施例为限。在正常工作状态下，U、V、W三相霍尔信号交替周期性跳变，按跳变顺序依次输出各相霍尔信号对应的计数值；在掉一相的情况下，按跳变顺序依次输出未掉相霍尔信号对应的计数值；在掉两相的情况下，输出未掉相霍尔信号对应的计数值。
更具体地，如图5所示，所述或逻辑单元125接收各边沿响应信号，并执行或逻辑运算；当所述第一边沿响应信号Wchg、所述第二边沿响应信号Vchg及所述第三边沿响应信号Uchg任意一个有效时，所述或逻辑单元125的输出信号有效(高电平有效)。作为示例，所述或逻辑单元125采用三输入或门实现，在实际使用中可基于多个逻辑元件实现或逻辑，不以本实施例为限。
更具体地，如图5所示，所述触发器126连接于所述或逻辑单元125的输出端，当所述或逻辑单元125的输出信号有效时，所述触发器126输出所述触发信号DivTrig；即当任意相霍尔信号跳变时，所述触发信号DivTrig有效。
更具体地，作为本发明的另一种实现方式，如图5所示，所述计数模块12还包括滤 波单元127，所述滤波单元127连接于所述选择单元124及所述或逻辑单元125的输出端，并接收计数上限值rp_LmtH及计数下限值rp_LmtL。当任意相霍尔信号跳变且所述当前计数值UVW_Cnt介于所述计数上限值rp_LmtH和所述计数下限值rp_LmtL之间(包括端点值rp_LmtH及rp_LmtL)时，将所述当前计数值UVW_Cnt输出。作为示例，所述滤波单元127包括第一比较器12h、第二比较器12i、与逻辑门12j、第六选择器12k及第二D触发器12l；所述第一比较器12h的输入端分别连接所述选择单元124的输出端及所述滤波下限值rp_LmtL，并输出第一比较结果；所述第二比较器12i的输入端分别连接所述选择单元124的输出端及所述滤波上限值rp_LmtH，并输出第二比较结果；所述与逻辑门12j的输入端分别连接所述第一比较器12h、所述第二比较器12i及所述或逻辑单元125的输出端，当所述当前计数值UVW_Cnt大于等于所述滤波下限值rp_LmtL、小于等于所述滤波上限值rp_LmtH，且任意相霍尔信号跳变时，输出有效的滤波控制信号；所述第六选择器12k的第一输入端连接所述第二D触发器12l的输出端，第二输入端连接所述选择单元124的输出端，控制端连接所述与逻辑门12j的输出端，所述滤波控制信号有效时所述第六选择器12k选择所述选择单元124的输出信号输出，所述滤波控制信号无效时所述第六选择器12k选择所述第二D触发器12l的输出信号输出；所述第二D触发器12l的数据输入端D连接所述第六选择器12k的输出端，输出滤波后的当前计数值Divisor。
需要说明的是，所述滤波下限值rp_LmtL及所述滤波上限值rp_LmtH由寄存器提供，在本实施例中，所述寄存器设置于中央处理器14中，如图4所示。在实际使用中，所述寄存器的位置可根据需要设置。任意能实现上述滤波功能的电路结构均适用于本发明，不以本实施例为限。本发明只需要配置两个寄存器即可将不合理的计数值排除以达到滤波的目的，不需要复杂的软件程序、操作方便简单、计算时间短，同时还能减少CPU的占用时间。
如图4所示，所述除法模块13连接于所述计数模块12的输出端，将霍尔信号相邻两次跳变之间的角度差除以所述计数模块12输出的计数值，以得到电机转速Result。
具体地，霍尔信号相邻两次跳变之间的角度差为180°，当所述触发信号DivTrig有效(作为示例，所述触发信号DivTrig高电平有效)时，将霍尔信号相邻两次跳变之间的角度差除以同一霍尔信号相邻两次跳变之间的时间差，即可得到所述电机转速Result。触发模块的实现方式不限，在此不一一赘述。在本实施例中，所述计数模块12输出的计数值为所述滤波后的当前计数值Divisor，在实际使用中，所述计数模块12输出的计数值也可以是所述当前计数值UVW_Cnt。
本发明的工作原理如下：
理想情况下，三个霍尔传感器的安装位置精准，UVW三相均正常工作，霍尔信号可以准确的反应转子的位置信息，此时UVW每相的相邻两次跳变之间的角度差均为180°，三相的计数值U_Cnt、V_Cnt、W_Cnt都正常，电机运转的一个周期内可以准确计算6次转速。
存在霍尔偏差的情况下，霍尔信号反应的转子位置信息有偏差，但UVW三相均可以工作，此时UVW每相的相邻两次跳变之间的角度差均为180°，三相的计数值U_Cnt、V_Cnt、W_Cnt都正常，电机运转的一个周期内可以准确计算6次转速。
掉相的情况下，如果U相掉相、V相和W相工作，此时V相和W相每相的相邻两次跳变之间的角度差均为180°，V相和W相的计数值V_Cnt和W_Cnt正常，电机运转的一个周期内可以准确计算4次转速。如果U相和V相掉相、W相工作，此时W相的相邻两次跳变之间的角度差为180°，W相的计数值W_Cnt正常，电机运转的一个周期内可以准确计算2次转速。
由此可见，本发明操作灵活快捷，适用范围广泛，不仅适用于理想情况，也适用于霍尔偏差和掉相的情况。
实施例二
本实施例提供一种自动计算转子速度的方法，作为示例，所述自动计算转子速度的方法基于实施例一中的自动计算转子速度的电路实现，在实际使用中，任意能实现本方法的硬件或软件装置均适用。所述自动计算转子速度的方法至少包括：
1)分别产生U、V、W三相霍尔信号的边沿响应信号。
具体地，每一相霍尔信号对应一路边沿响应信号，所述边沿响应信号包括上升沿响应信号及下降沿响应信号。作为示例，当霍尔信号跳变时，产生一脉冲信号，其中，霍尔信号的跳变包括上升沿跳变和下降沿跳变，即，霍尔信号跳变为上升沿或跳变为下降沿都会产生相应脉冲信号。
2)基于各相霍尔信号的边沿响应信号分别对各相霍尔信号的相邻两次跳变之间的时间差进行计数得到各相计数值，并输出当前计数值。
具体地，分别对各相霍尔信号的相邻两次跳变之间的时间差进行计数，对于任意一相霍尔信号，当接收到边沿响应信号的当前脉冲时开始计数，当接收到下一脉冲时重新开始计数，依次类推，不断更新计数值。
具体地，在本实施例中，通过选择各相计数值的输出顺序得到所述当前计数值UVW_Cnt。此时，当两相以上霍尔信号同时跳变时，按照U、V、W的优先级顺序输出相 应霍尔信号对应的计数值；作为示例，当三相霍尔信号同时跳变时，输出U相计数值；当U相和V相同时跳变时，输出U相计数值；当U相和W相同时跳变时，输出U相计数值；当V相和W相同时跳变时，输出V相计数值。正常状态下不会出现两相以上霍尔信号同时跳变的情况，如果出现这种情况说明发生了掉相或其它故障，而且这种情况不会持续很长时间，大部分时间各相霍尔信号是分别跳变的。当各相霍尔信号分别跳变时，输出跳变相对应的计数值；即任意一相霍尔信号有输出且发生跳变，则输出该相霍尔信号对应的计数值。
具体地，作为本发明的一种实现方式，还包括对所述当前计数值UVW_Cnt滤波后输出的步骤。当任意相霍尔信号跳变且所述当前UVW_Cnt计数值介于计数上限值rp_LmtH和计数下限值rp_LmtL之间时将，所述当前计数值输出，否者滤除；以此提高最终结果的准确性。
需要说明的是，所述计数上限值rp_LmtH及所述计数下限值rp_LmtL由寄存器提供，无需软件人员基于电机理论及数学理论撰写复杂的滤波软件程序，操作方便简单。
3)将霍尔信号相邻两次跳变之间的角度差除以所述当前计数值，计算得到电机转速。
具体地，霍尔信号相邻两次跳变之间的角度差为180°，将180°除以所述当前计数值，即可得到当前电机转速Result。该方法基于同一霍尔传感器的信号进行电机转速的计算，不依赖转子的位置信息，不影响转子速度计算的准确性；此外，即使有两个霍尔传感器掉相，只要有一个霍尔传感器工作都可以准确计算转子速度，因此本发明的适用情况更加广泛。
需要说明的是，当步骤2)中进行滤波操作后，步骤3)中将180°除以滤波后的当前计数值Divisor，在此不一一赘述。
综上所述，本发明提供一种自动计算转子速度的电路及方法，该电路包括：边沿产生模块，用于接收U、V、W三相霍尔信号，并针对各相霍尔信号分别产生边沿响应信号；计数模块，连接于所述边沿产生模块的输出端，基于所述边沿产生模块的输出信号分别对各相霍尔信号各自的相邻两次跳变之间的时间差进行计数得到各相计数值，输出当前计数值，并在任意相霍尔信号跳变时产生触发信号；除法模块，连接于所述计数模块的输出端，将霍尔信号的相邻两次跳变之间的角度差除以所述当前计数值，以得到电机转速。本发明的自动计算转子速度的电路及方法基于硬件电路采用同一相霍尔信号的跳变计算转速，采用寄存器写入的方式滤波时间差；不依赖转子位置信息，转速计算准确；操作方便简单，对技术人员要求不高，可以减少开发时间；不需要复杂的软件程序，CPU占用资源少；适 用场景广泛，适用于理想情况、霍尔偏差的情况及掉相的情况。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (15)

  1. 一种自动计算转子速度的电路，其特征在于，所述自动计算转子速度的电路至少包括：
    边沿产生模块，接收U、V、W三相霍尔信号，并针对各相霍尔信号分别产生边沿响应信号；
    计数模块，连接于所述边沿产生模块的输出端，基于所述边沿产生模块的输出信号分别对各相霍尔信号各自的相邻两次跳变之间的时间差进行计数得到各相计数值，输出当前计数值，并在任意相霍尔信号跳变时产生触发信号；
    除法模块，连接于所述计数模块的输出端，将霍尔信号的相邻两次跳变之间的角度差除以所述当前计数值，以得到电机转速。
  2. 根据权利要求1所述的自动计算转子速度的电路，其特征在于：所述计数模块包括第一计数单元、第二计数单元、第三计数单元、选择单元、或逻辑单元及触发器；
    所述第一计数单元、所述第二计数单元、所述第三计数单元接收计数触发信号及对应的边沿响应信号，分别对各相霍尔信号各自的相邻两次跳变之间的时间差进行计数得到各相计数值；
    所述选择单元连接于所述第一计数单元、所述第二计数单元及所述第三计数单元的输出端，并接收各边沿响应信号；当两相以上霍尔信号同时跳变时，按照U、V、W的优先级顺序输出相应相霍尔信号对应的计数值作为所述当前计数值；当各相霍尔信号分别跳变时，输出跳变相对应的计数值作为所述当前计数值；
    所述或逻辑单元接收各边沿响应信号，并执行或逻辑运算；
    所述触发器连接于所述或逻辑单元的输出端，当所述或逻辑单元的输出信号有效时，所述触发器输出所述触发信号。
  3. 根据权利要求2所述的自动计算转子速度的电路，其特征在于：所述第一计数单元、所述第二计数单元或所述第三计数单元包括第一选择器、第二选择器、第一D触发器及加法器；
    所述第一选择器的第一输入端连接所述第一D触发器的输出端，第二输入端连接所述加法器的输出端，控制端连接所述计数触发信号；
    所述第二选择器的第一输入端连接所述第一选择器的输出端，第二输入端连接低电平信号，控制端连接对应相霍尔信号的边沿响应信号；
    所述第一D触发器的数据输入端连接所述第二选择器的输出端；
    所述加法器的输入端分别连接所述第一D触发器的输出端及高电平信号，当所述第一 D触发器的输出信号有效时执行加一操作，并输出对应相计数值；
    其中，各选择器的控制信号有效时选择第二输入端的信号输出，控制信号无效时选择第一输入端的信号输出。
  4. 根据权利要求2所述的自动计算转子速度的电路，其特征在于：所述选择单元包括第三选择器、第四选择器及第五选择器；
    所述第三选择器的第一输入端连接低电平信号，第二输入端连接所述第一计数单元的输出端，控制端连接W相霍尔信号的边沿响应信号；
    所述第四选择器的第一输入端连接所述第三选择器的输出端，第二输入端连接所述第二计数单元的输出端，控制端连接V相霍尔信号的边沿响应信号；
    所述第五选择器的第一输入端连接所述第四选择器的输出端，第二输入端连接所述第三计数单元的输出端，控制端连接U相霍尔信号的边沿响应信号；
    其中，各选择器的控制信号有效时选择第二输入端的信号输出，控制信号无效时选择第一输入端的信号输出。
  5. 根据权利要求2-4中任意一项所述的自动计算转子速度的电路，其特征在于：所述计数模块还包括滤波单元；所述滤波单元连接于所述选择单元及所述或逻辑单元的输出端，并接收计数上限值及计数下限值；当任意相霍尔信号跳变且所述当前计数值介于所述计数上限值和所述计数下限值之间时，将所述当前计数值输出。
  6. 根据权利要求5所述的自动计算转子速度的电路，其特征在于：所述滤波单元包括第一比较器、第二比较器、与逻辑门、第六选择器及第二D触发器；
    所述第一比较器的输入端分别连接所述选择单元的输出端及滤波下限值，并输出第一比较结果；
    所述第二比较器的输入端分别连接所述选择单元的输出端及滤波上限值，并输出第二比较结果；
    所述与逻辑门的输入端分别连接所述第一比较器、所述第二比较器及所述或逻辑单元的输出端；当所述当前计数值大于等于所述滤波下限值、小于等于所述滤波上限值，且任意相霍尔信号跳变时，所述与逻辑门输出有效的滤波控制信号；
    所述第六选择器的第一输入端连接所述第二D触发器的输出端，第二输入端连接所述选择单元的输出端，控制端连接所述与逻辑门的输出端；所述滤波控制信号有效时，所述 第六选择器选择所述选择单元的输出信号输出；所述滤波控制信号无效时，所述第六选择器选择所述第二D触发器的输出信号输出；
    所述第二D触发器的数据输入端连接所述第六选择器的输出端，输出滤波后的当前计数值。
  7. 根据权利要求5所述的自动计算转子速度的电路，其特征在于：所述滤波下限值及所述滤波上限值由寄存器提供。
  8. 根据权利要求1所述的自动计算转子速度的电路，其特征在于：霍尔信号的相邻两次跳变之间的角度差为180°。
  9. 根据权利要求1所述的自动计算转子速度的电路，其特征在于：所述边沿产生模块对各相霍尔信号的上升沿及下降沿进行响应，以产生所述边沿响应信号。
  10. 根据权利要求2所述的自动计算转子速度的电路，其特征在于：当所述边沿响应信号任意一个有效时，所述或逻辑单元的输出信号有效。
  11. 一种自动计算转子速度的方法，其特征在于，所述自动计算转子速度的方法至少包括：
    1)分别产生U、V、W三相霍尔信号的边沿响应信号；
    2)基于各相霍尔信号的边沿响应信号分别对各相霍尔信号的相邻两次跳变之间的时间差进行计数得到各相计数值，并输出当前计数值；
    3)将霍尔信号的相邻两次跳变之间的角度差除以所述当前计数值，计算得到电机转速。
  12. 根据权利要求11所述的自动计算转子速度的方法，其特征在于：步骤1)中，所述边沿响应信号包括上升沿响应信号及下降沿响应信号。
  13. 根据权利要求11所述的自动计算转子速度的方法，其特征在于：步骤2)中，分别对各相霍尔信号的相邻两次跳变之间的时间差进行计数；当两相以上霍尔信号同时跳变时，按照U、V、W的优先级顺序输出相应相霍尔信号对应的计数值作为所述当前计数值；当各相霍尔信号分别跳变时，输出跳变相对应的计数值作为所述当前计数值。
  14. 根据权利要求11-13中任意一项所述的自动计算转子速度的方法，其特征在于：步骤2)中还包括对所述当前计数值滤波后输出的步骤。
  15. 根据权利要求14所述的自动计算转子速度的方法，其特征在于：滤波方法包括：当任意相霍尔信号跳变且所述当前计数值介于计数上限值和计数下限值之间时，将所述当前计数值输出，否者滤除。
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