WO2023168965A1

WO2023168965A1 - Circuit for realizing bus communication, bus communication system, and power source energy storage device

Info

Publication number: WO2023168965A1
Application number: PCT/CN2022/129789
Authority: WO
Inventors: 陈雄伟; 邓勇明
Original assignee: 深圳市驰普科达科技有限公司
Priority date: 2022-03-08
Filing date: 2022-11-04
Publication date: 2023-09-14
Also published as: CN114301732B; CN114301732A

Abstract

The present application provides a circuit for realizing bus communication, a bus communication system, and a power source energy storage device. The circuit for realizing bus communication is applied to the bus communication system; the bus communication system comprises a bus; the circuit for realizing bus communication comprises a processing module and a transceiving circuit; the processing module is provided with a UART transmitting end and a UART receiving end; the UART receiving end is electrically connected to the bus; an input end of the transceiving circuit is connected to the UART transmitting end; and an output end of the transceiving circuit is respectively electrically connected to the UART receiving end and the bus.

Description

Circuits, bus communication systems and power supply energy storage devices that realize bus communication

This application claims priority to the Chinese patent application with application number 202210218161.2 filed on March 8, 2022.

Technical field

The present application relates to the field of bus communication technology, and in particular to a circuit for realizing bus communication, a bus communication system and a power supply energy storage device.

Background technique

The UART interface is a very common industrial interface and is a standard configuration on many chips. However, the UART interface has certain limitations and can only meet the communication requirements between two circuit modules with UART interfaces. If a live device, such as an energy storage power supply device, is provided with multiple circuit modules, an additional bus communication module needs to be provided in each circuit module to achieve communication between multiple different circuit modules.

technical problem

The main purpose of this application is to provide a circuit, bus communication system and power supply energy storage device for realizing bus communication, aiming to use the UART interface to realize bus communication.

Technical solutions

This application proposes a circuit for realizing bus communication, which is applied to a bus communication system. The bus communication system includes a bus, and the circuit for realizing bus communication includes:

A processing module, the processing module has a UART transmitter and a UART receiver, and the UART receiver is electrically connected to the bus;

A transceiver circuit, the input end of the transceiver circuit is connected to the UART transmitter, and the output end of the transceiver circuit is electrically connected to the UART receiver and the bus respectively;

Wherein, the processing module is used to receive the first data sent on the bus through the UART receiving end;

The processing module is also configured to output the second data to the bus and the UART receiving end via the UART transmitting end and the transceiver circuit;

The processing module is also configured to, when outputting the second data via the UART transmitter and the transceiver circuit, if the data received via the UART receiver is different from the second data, stop processing. The UART transmitting end outputs the second data, and confirms that no data has been received by the UART receiving end within the delay time corresponding to the preset source address, and then passes the UART transmitting end and the transceiver again. The circuit outputs the second data to the bus and the UART receiving end.

In one embodiment, the processing module is further configured to output a reception completion signal to the bus via the UART transmitter and the transceiver circuit after receiving the first data transmitted on the bus through the UART receiving end. .

In one implementation, both the second data and the first data include address characters corresponding to the preset source address;

The processing module is also configured to encode the characters that are the same as the address characters in the data to be sent according to the preset encoding method corresponding to the address characters to generate the second data, and then use the UART to generate the second data. The transmitting end and the transceiver circuit output the second data to the bus;

The processing module is also configured to, after outputting the second data to the bus via the UART transmitter and the transceiver circuit, if the reception completion signal is not received within the preset completion feedback time, re- The second data is output to the bus via the UART transmitter and the transceiver circuit.

The processing module is also configured to decode the first data according to the address characters of the first data when receiving the first data;

The processing module is further configured to determine that the first data including the previous address character is junk data if the address character is repeatedly received when the first data is received; and the subsequent The data after one of the address characters starts to be received as the new first data.

In one embodiment, the processing module also has a bus status detection terminal, and the bus status detection terminal is electrically connected to the UART receiving terminal;

The processing module is configured to detect the level status of the UART receiving end through the bus status detection end, and determine that the bus is in an idle state when the level status does not change within a preset detection time;

The processing module is also configured to output the second data to the bus and the UART receiving end via the UART transmitting end and the transceiver circuit when it is confirmed that the bus is in an idle state.

In one embodiment, the circuit for realizing bus communication further includes:

A first isolation circuit, the first isolation circuit is connected in series between the UART receiving end and the bus; the first isolation circuit is used to isolate and transmit the first data to the UART receiving end; And also for isolating and transmitting the second data to the UART receiving end;

A second isolation circuit, the second isolation circuit is connected in series between the input end of the transceiver circuit and the UART transmitting end; the second isolation circuit is used to isolate and transmit the second data to the bus and all Described UART receiver.

In one embodiment, the circuit for realizing bus communication further includes a first current limiting circuit and a second current limiting circuit. The first current limiting circuit is connected in series between the UART receiving end and the bus. The second current limiting circuit is connected in series between the UART transmitting end and the transceiver circuit.

In one embodiment, the transceiver circuit includes a first switch and a first resistor, the first current limiting circuit includes a second resistor, and the second current limiting circuit includes a third resistor and a first capacitor;

Wherein, the first end of the first switch tube, the second end of the first resistor and the second end of the second resistor are respectively connected to the bus line, and the first end of the first resistor is connected to the first end of the first resistor. A power supply end is connected, the second end of the first switch tube and the second end of the third resistor are respectively connected to the second end of the first capacitor, and the third end of the first switch tube is grounded, so The first end of the second resistor is connected to the UART receiving end, and the first end of the third resistor and the first end of the first capacitor are electrically connected to the UART transmitting end respectively.

This application also proposes a bus communication system, which includes a bus and a plurality of circuits for realizing bus communication as described in any one of the above items that are electrically connected to the bus.

This application also proposes a power supply energy storage device. The power supply energy storage device includes a bus and a plurality of circuit modules. Each of the plurality of circuit modules includes any one of the above-mentioned devices for realizing bus communication that is electrically connected to the bus. circuit.

In one embodiment, the power supply energy storage device further includes an interface, the interface is electrically connected to the bus, the interface is used to electrically connect to an external terminal, and the interface is used to access updates sent by the external terminal. The data is transmitted to the circuit module via the bus and the UART receiving end to update the data in the circuit module.

beneficial effects

The circuit for realizing bus communication in this application includes a processing module and a transceiver circuit. The processing module has a UART transmitter and a UART receiver. The UART receiver is electrically connected to the bus. The input end of the transceiver circuit is connected to the UART transmitter. The output ends of the transceiver circuit are respectively Electrically connected to the UART receiving end and bus. Among them, the processing module is used to receive the first data sent on the bus through the UART receiving end, and is used to output the second data to the bus and UART receiving end through the UART transmitting end and the transceiver circuit, and is used to transmit the data to the bus through the UART transmitting end. When the transceiver circuit outputs the second data, if the data received through the UART receiving end is different from the second data, the output of the second data through the UART transmitting end will be stopped, and it will be confirmed within the delay time corresponding to the preset source address. When the UART receiving end receives any data, the second data is output to the bus and the UART receiving end again through the UART transmitting end and the transceiver circuit. In this way, this application implements bus communication using the UART interface. In an actual power supply energy storage device, multiple circuit modules do not need to install additional bus communication modules. You only need to use the UART interface of the processor of each circuit module and the above-mentioned circuit of the present application to realize communication between multiple circuit modules. bus communication.

Description of the drawings

In order to explain the embodiments of the present application or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are only These are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on the structures shown in these drawings without exerting creative efforts.

Figure 1 is a module schematic diagram of an embodiment of a circuit for realizing bus communication in this application;

Figure 2 is a module schematic diagram of another embodiment of a circuit for realizing bus communication in this application;

Figure 3 is a module schematic diagram of a circuit for realizing bus communication according to another embodiment of the present application;

Figure 4 is a circuit schematic diagram of an embodiment of a circuit for realizing bus communication in this application;

Figure 5 is a circuit schematic diagram of an embodiment of the bus communication system of the present application.

Explanation of reference numbers:

标号 label	名称 name	标号 label	名称 name
10 10	处理模块 processing module	20 20	收发电路 Transceiver circuit
41 41	第一隔离电路 first isolation circuit	42 42	第二隔离电路 Second isolation circuit
31 31	第一限流电路 First current limiting circuit	32 32	第二限流电路 Second current limiting circuit

The realization of the purpose, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings.

Embodiments of the invention

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

To this end, this application proposes a circuit for realizing bus communication, which is applied to the bus communication system. The bus communication system includes a bus, and the circuit for realizing bus communication includes:

Processing module 10, the processing module 10 has a UART transmitting end TXD and a UART receiving end RXD, and the UART receiving end RXD is electrically connected to the bus;

Transceiver circuit 20, the input end of the transceiver circuit 20 is connected to the UART transmitter TXD, and the output end of the transceiver circuit 20 is electrically connected to the UART receiver RXD and the bus;

Among them, the processing module 10 is used to receive the first data sent on the bus through the UART receiving terminal RXD;

The processing module 10 is also used to output the second data to the bus and the UART receiving end RXD via the UART transmitter TXD and the transceiver circuit 20;

The processing module 10 is also configured to stop outputting the second data via the UART transmitting end TXD if the data received through the UART receiving end RXD is different from the second data when outputting the second data through the UART transmitting end TXD and the transceiver circuit 20 , and when it is confirmed that no data has been received by the UART receiving end RXD within the delay time corresponding to the preset source address, the second data is output to the bus and the UART receiving end RXD via the UART transmitting end TXD and the transceiver circuit 20 again.

In this embodiment, the processing module 10 can be implemented using any main controller with a UART transmitter TXD and a UART receiver RXD, such as MCU, DSP (Digital Signal Process, digital signal processing chip), FPGA (Field Programmable Gate) Array, programmable logic gate array chip), etc.

In this embodiment, referring to Figure 4, the processing module 10 also has a bus status detection terminal IN, and the bus status detection terminal IN is electrically connected to the UART receiving terminal RXD;

The processing module 10 is used to detect the level status of the UART receiving end RXD through the bus status detection terminal IN, and determine that the bus is in an idle state when the level status does not change within the preset detection time;

The processing module 10 is also configured to output the second data to the bus and the UART receiving terminal RXD via the UART transmitting terminal TXD and the transceiver circuit 20 when it is confirmed that the bus is in an idle state.

In this embodiment, the bus status detection terminal IN of the processing module 10 can detect the level state of the UART receiving terminal RXD. When the bus status detecting terminal IN of the processing module 10 detects the level state of the UART receiving terminal RXD, it always remains unchanged. , for example, if it remains high, then there will be no level change on the current bus, thus determining that the current bus is in an idle state. Since the start character of UART communication is low level, when the processing module 10 detects that the UART receiving end RXD has a low level through the bus status detection end IN, it is determined that the current bus is not in an idle state. At this time, the processing module 10 will only The first data transmitted from the bus is received through the UART receiving end RXD, and the data will not be sent out. Similarly, when it is determined that the level of the UAER receiving end has not changed, that is, when it is determined that the current bus is idle, the processing module 10 can output the second data to the bus and the UART receiving end RXD via the UART transmitting end TXD and the transceiver circuit 20 .

In this embodiment, it should be understood that in a bus communication system, a bus is often electrically connected to multiple circuits for implementing bus communication in this application. Therefore, during the bus communication process, developers in each processing module 10 will set different preset source addresses for differentiation. When at least two processing modules 10 simultaneously output the second data through the UART transmitting terminal TXD and the transceiver circuit 20, this will cause the two data to interfere with each other, thereby causing data transmission errors on the bus. At this time, since the processing module 10 will simultaneously send the second data to its own UART receiving end RXD when outputting it through the UART transmitting end TXD and the transceiver circuit 20, if at this time the processing module 10 finds that it receives the second data through the UART receiving end RXD, If the data is inconsistent with the sent data, it will be determined that there are other processing modules 10 on the current bus that are sending data at the same time. Similarly, other processing modules 10 that are sending data at the same time will also find that they received the first data through the UART receiving end RXD. If the data is inconsistent with the sent data, it will also be determined that there are other processing modules 10 on the current bus sending data at the same time. When it is determined that there are other processing modules 10 on the current bus sending data at the same time, the processing module 10 will stop outputting the second data through the UART transmitter TXD, and confirm that no second data has been sent through the UART receiver RXD within the delay time corresponding to the preset source address. When any data is received, the second data is output to the bus and UART receiving end RXD via the UART transmitter TXD and the transceiver circuit 20 again.

Specifically, three circuits of the present application for realizing bus communication are electrically connected to the bus. Each processing module 10 has a preset source address pre-stored in it, which is "No. 1", "No. 2" and "No. 3" respectively. , the corresponding delay times are "1mS", "2mS" and "3mS" respectively. When the No. 1 processing module 10 and the No. 2 processing module 10 simultaneously output the second When receiving data, the No. 1 processing module 10 and the No. 2 processing module 10 will simultaneously find that the data they receive through the UART receiving end RXD is inconsistent with the data sent, and both will stop sending data. At this time, the bus enters the idle state. When the No. 1 processing module 10 fails to receive any data within 1 mS, it is considered that the current bus is already in the idle state, and will start outputting through its UART transmitter TXD and transceiver circuit 20 Second data. At this moment, processing module No. 2 10 will receive the first data from the bus via the UART receiving end RXD (which is the second data sent by No. 1 above). At this time, it will consider that the bus is in a non-idle state and will not send any data. , after receiving the first data, if the No. 2 processing module 10 finds that no data can be received within 2 mS, it will consider that the current bus is already in an idle state, and will start to pass its UART transmitter TXD and transceiver circuit 20 outputs the second data that processing module No. 2 10 needs to send. In this way, in the application of actual bus communication system, the UART interface can be used to realize bus communication.

At the same time, it can be understood that if the current processing module 10 is interfered when outputting the second data through its UART transmitting end TXD and the transceiver circuit 20, causing the second data output to the bus to be inconsistent with the data actually intended to be output, the processing module 10 will also find through its UART receiving end RXD that the second data output is inconsistent with the actual data to be output, and will stop output, and confirm that it has not been received by the UART receiving end RXD within the delay time corresponding to the preset source address. After receiving any data, the second data is output again through its UART transmitting end TXD and the transceiver circuit 20 . In this way, the processing module 10 can verify and correct the output data, thereby improving the stability of the bus communication system.

In this embodiment, referring to Figure 2, the circuit for realizing bus communication also includes a first current limiting circuit 31 and a second current limiting circuit 32. The first current limiting circuit 31 is connected in series between the UART receiving end RXD and the bus. The current limiting circuit 32 is connected in series between the UART transmitting terminal TXD and the transceiver circuit 20 .

In this embodiment, the first current limiting circuit 31 and the second current limiting circuit 32 can be implemented using resistors. It should be understood that the UART receiving end RXD and the UART transmitting end TXD of the processing module 10 generally can withstand relatively low currents. , excessive current may cause damage to the above two ports. Therefore, setting up the first current limiting circuit 31 and the second current limiting circuit 32 can reduce the input and output currents to the UART receiving end RXD and the UART transmitting end TXD, effectively improving the stability and reliability of the circuit that implements bus communication. sex.

Specifically, in one embodiment of the present application, referring to FIG. 4 , the transceiver circuit 20 includes a first switch Q1 and a first resistor R1 , the first current limiting circuit 31 includes a second resistor R2 , and the second current limiting circuit 32 includes a third resistor. three resistors R3 and the first capacitor C1;

Among them, the first end of the first switch Q1, the second end of the first resistor R1, and the second end of the second resistor R2 are respectively connected to the bus, and the first end of the first resistor R1 is connected to the first power terminal V1. The second terminal of the first switch Q1 and the second terminal of the third resistor R3 are respectively connected to the second terminal of the first capacitor C1. The third terminal of the first switch Q1 is connected to the ground. The first terminal of the second resistor R2 is connected to the UART. The receiving end RXD is connected, the first end of the third resistor R3 and the first end of the first capacitor C1 are electrically connected to the UART transmitting end TXD respectively, and the bus status detection end IN of the processing module 10 is electrically connected to the UART receiving end RXD.

In this embodiment, the voltage of the first power terminal V1 is the bus voltage, and the first switch Q1 is a PNP transistor.

When the processing module 10 wants to output data through the UART transmitting terminal TXD, if the processing module 10 outputs a low-level signal through the UART transmitting terminal TXD, the first switch Q1 will be turned on. At this time, the voltage at the second end of the first resistor R1 It will be pulled to the bottom, that is, the same voltage as the low-level signal. At this time, the UART receiving end RXD will receive the low-level signal and will output a low-level signal to the bus. In the same way, when the processing module 10 outputs a high-level signal through the UART transmitting terminal TXD, the first switch tube Q1 fails to meet the conduction condition, and the first switch tube Q1 is not turned on. At this time, the UART receiving terminal RXD will receive a high-level signal. level signal. In this way, the data output by the processing module 10 through the UART receiving terminal RXD can be simultaneously output to the bus and fed back to the UART receiving terminal RXD.

When the processing module 10 has not output any data through the UART transmitting terminal TXD, and when other processing modules 10 connected to the bus are sending data from the bus, the bus status detection terminal IN will detect the level change on the current bus. At this time The processing module 10 will not output any data via the UART transmitting terminal TXD, and will receive any data via the UART receiving terminal RXD.

The circuit for realizing bus communication in this application includes a processing module 10 and a transceiver circuit 20. The processing module 10 has a UART transmitter TXD and a UART receiver RXD. The UART receiver RXD is electrically connected to the bus. The input end of the transceiver circuit 20 is connected to the UART transmitter TXD. connection, the output end of the transceiver circuit 20 is electrically connected to the UART receiving end RXD and the bus respectively. Among them, the processing module 10 is used to receive the first data sent on the bus via the UART receiving terminal RXD, and is used to output the second data to the bus and the UART receiving terminal RXD via the UART transmitting terminal TXD and the transceiver circuit 20, and is used to When the second data is output via the UART transmitting terminal TXD and the transceiver circuit 20, if the data received via the UART receiving terminal RXD is different from the second data, the output of the second data via the UART transmitting terminal TXD is stopped, and the preset source address is When it is confirmed that no data has been received by the UART receiving end RXD within the corresponding delay time, the second data is output to the bus and the UART receiving end RXD via the UART transmitting end TXD and the transceiver circuit 20 again. In this way, this application implements bus communication using the UART interface. In an actual power supply energy storage device, multiple circuit modules do not need to install additional bus communication modules. You only need to use the UART interface of the processor of each circuit module and the above-mentioned circuit of the present application to realize communication between multiple circuit modules. bus communication.

In an embodiment of the present application, the processing module 10 is also configured to output a reception completion signal to the bus via the UART transmitter TXD and the transceiver circuit 20 after receiving the first data transmitted on the bus via the UART receiver RXD.

Both the second data and the first data include address characters corresponding to the preset source address;

The processing module 10 is also used to generate the second data after encoding the characters that are the same as the address characters in the data to be sent according to the preset encoding method corresponding to the address characters, and then encode the second data through the UART transmitter TXD and the transceiver circuit 20. 2. Data output to the bus;

The processing module 10 is also used to output the second data to the bus via the UART transmitter TXD and the transceiver circuit 20, if the reception completion signal is not received within the preset completion feedback time, then re-transmit the data via the UART transmitter TXD and the transceiver circuit 20. Circuit 20 outputs the second data to the bus.

The processing module 10 is also configured to decode the first data according to the address characters of the first data when receiving the first data;

The processing module 10 is also configured to, when receiving the first data, if address characters are repeatedly received, determine that the first data including the previous address character is junk data; and use the data after the next address character as new The first data starts to be received.

In practical applications, it is known from the above that each circuit mounted on the bus to implement bus communication will pre-store different preset source addresses in the processing module 10 according to the user's needs. Therefore, when the processing module 10 sends data to the outside, it will also include the address characters related to the preset source address as the beginning. It can be understood that the data sent out through the UART transmitter will also include the data that needs to be transmitted via the bus. The address characters of the default source address corresponding to other processing modules 10.

In this embodiment, when the processing module 10 needs to send data via the UART transmitter, the characters that are the same as the address characters in the data to be sent will be encoded according to the preset encoding method. For example, the preset encoding corresponding to the current processing module 10 Assuming that the address character of the source address is "05", any "05" character in the data to be output, except the address character, will be modified to "V", and the second data will be generated after encoding, and then transmitted via UART The terminal TXD and the transceiver circuit 20 output the second data to the bus.

Similarly, when the processing module 10 receives the first data from the bus through the UART receiving end RXD, it will also first receive the address characters of the first data, and then decode the contents of the remaining characters according to the preset encoding method. Specifically, taking the received first data as the second data output by the processing module 10 in the above embodiment as an example, the processing module 10 receives the first data through the UART receiving end RXD, and determines that the address character of the first data is " 05", all subsequent "V" characters will be decoded into "05".

It should be understood that in actual applications, UART transmission data will have data length variables in accordance with protocol requirements, so that when the processing module 10 receives the first data via the UART receiving end RXD, the time to end the reception is determined based on the data length variable. . During the process of receiving data, the data may be interfered by the environment in which the receiving processing module 10 is located, which may cause the data length variable to change. This causes the processing module 10 to receive the first data even though it has actually received all the data. data, but it will still be considered that the data has not been completely received and is always in the receiving state, resulting in the inability to feed back the completion signal to the bus. At this time, it can be known from the above that after the processing module 10 outputs the second data to the bus via the UART transmitter TXD and the transceiver circuit 20, if the reception completion signal is not received within the preset completion feedback time, it will re-transmit via the UART. The terminal TXD and the transceiver circuit 20 output the second data to the bus. In this way, when the processing module 10 of the receiver reads the address character again, it immediately determines that all the previously received data is junk data, and starts to receive the data after the address character as the new first data again, thereby preventing the data from being read. The data length variable is disturbed and modified, causing the processing module 10 to be in the receiving state for a long time.

Specifically, referring to FIG. 5 , the address character corresponding to the source address prestored by the receiver processing module 10 is 01, and the address character corresponding to the source address prestored by the transmitter processing module 10 is 02, and the preset completion feedback time is 1S. Example to illustrate.

When the transmitter processing module 10 needs to output data, the character that is the same as the address character 02 in the data to be output will be modified to "II" to generate the second data, and the data length variable of the second data will be set to 5 bytes. During the transmission process, due to interference, the data length variable of the second data became 10,000 bytes.

At this time, when the receiving party's processing module 10 receives the first data that is the above-mentioned interfered second data, it will determine that its address character is "02" and determine that the data length variable is 10,000 bytes. The receiving party's processing module 10 will be in the receiving state for a long time, and the reception completion signal will not be fed back to the transmitter through the bus. Therefore, since the transmitter processing module 10 does not receive the reception completion signal within the preset completion feedback time, the transmitter processing module 10 will re-output the second data to the bus via the UART transmitter TXD and the transceiver circuit 20 . At this moment, the receiver processing module 10 will again receive the first data, which is the second data after the interference, from the bus via the UART receiving end RXD, and will receive the unique address character "02" again, and the receiver will process The module 10 will consider that the data before this new address character are junk data, and start receiving the data after the next address character as the new first data. In this way, in practical applications, compared with the existing method of verifying all data after receiving it, changes in data length variables can be discovered faster, thereby shortening the error correction time.

It can be understood that a check code is also set in the transmitted UART data. If the processing module 10 receives the first data from the bus via the UART receiving end RXD, the data length variable is not wrong, but the intermediate data occurs. If there is an error, the processing module 10 will perform verification according to the check code in the received first data after completing the reception of the data to determine whether there is an error in the intermediate data.

Referring to Figure 3, in an embodiment of the present application, a circuit for realizing bus communication also includes:

The first isolation circuit 41 is connected in series between the UART receiving end RXD and the bus; the first isolation circuit 41 is used to isolate and transmit the first data to the UART receiving end RXD; the first isolation circuit 41 also Used to isolate and transmit the second data to the UART receiving end RXD;

The second isolation circuit 42 is connected in series between the input terminal of the transceiver circuit 20 and the UART transmitting terminal TXD; the second isolation circuit 42 is used to transmit the second data in isolation to the bus and the UART receiving terminal RXD.

It should be understood that in actual applications, the voltage level of the application environment of the bus communication system using UART communication may be different from the voltage level of the circuit module used in the circuit of the present application to implement bus communication. For example, the voltage of the application environment The level is 48V, while the working voltage of the sensor is 3.3V, and the working voltage limit of its processing module 10 is also 3.3V. At this time, the UART receiving end RXD and the UART transmitting end TXD on the processing module 10 in the sensor can only withstand a voltage of 3.3V, which is much less than 48V. This causes the processing module 10 of the sensor to be unable to withstand the bus voltage and unable to drive the transceiver circuit 20 Work.

For this reason, in this embodiment, both the first isolation circuit and the second isolation circuit 42 can be implemented using voltage isolation devices, such as optocouplers, transformers, etc. In this way, in practical applications, the first isolation circuit 41 can convert the first data of a high voltage level on the bus, such as the first data of 48V, into the first data of a low voltage level, such as the first data of 3.3V. , so that the UART receiving end RXD of the processing module 10 in a low-voltage working environment can normally receive the first data. Similarly, the second isolation circuit 42 can also convert the low-voltage second data output by the UART transmitting end TXD of the processing module 10 into high-voltage second data, and output it to the bus through the transceiver circuit 20 .

Through the above settings, multiple communication modules with different voltage levels can realize bus communication with each other in the bus communication system, thereby improving the compatibility of the bus communication system of the present application.

This application also proposes a bus communication system, including a bus and any of the above-mentioned circuits for realizing bus communication.

It is worth noting that since the bus communication system of the present application is based on the above-mentioned circuit for realizing bus communication, the embodiments of the bus communication system of the present application include all the technical solutions of all the embodiments of the above-mentioned circuit for realizing bus communication, and the technology achieved The effect is exactly the same and will not be repeated here.

This application also proposes a power supply energy storage device. The power supply energy storage device includes a bus and multiple circuit modules. Each of the multiple circuit modules includes any of the above-mentioned circuits for realizing bus communication that are electrically connected to the bus.

It is worth noting that since the power supply energy storage device of the present application is based on the above-mentioned circuit for realizing bus communication, the embodiments of the power supply energy storage device of the present application include all the technical solutions of all the embodiments of the above-mentioned circuit for realizing bus communication, and achieve The technical effects are also exactly the same and will not be repeated here.

What needs to be understood is that conventional processors are generally equipped with a UART interface. In practical applications, there will be multiple circuit modules inside the power supply energy storage device, such as DC/DC circuit boards, AC/DC circuit boards and BMS circuit boards. In order to meet the circuit control requirements, multiple circuit modules are often equipped with processors. Multiple circuit modules can realize UART interface communication with each other through only one bus and the above-mentioned bus communication circuit, without the need to set up other additional circuit modules. The bus communicates, reducing the cost of circuit wiring and devices.

In another embodiment, the power supply energy storage device also includes an interface, the interface is electrically connected to the bus, the interface is used to electrically connect to the external terminal, the interface is used to access update data sent by the external terminal, and transmits it via the bus and the UART receiving end. RXD is transmitted to the circuit module to update the data in the circuit module.

In this embodiment, the interface can be a charging interface of the power supply energy storage device, such as a TYPE-C interface, a Micro USB interface, etc., and the bus can be connected to the data line of the charging interface. In this way, in practical applications, R&D personnel or after-sales personnel can send data to the bus through the charging interface, and then transmit update data to the circuit module connected to the bus, thereby achieving online upgrade of the internal circuit module program of the power supply energy storage device. There is no need to disassemble and assemble the housing of the power supply energy storage device, which improves the convenience of using the power supply energy storage device.

The above are only optional embodiments of the present application, and do not limit the patent scope of the present application. Under the inventive concept of the present application, equivalent structural transformations made by using the contents of the description and drawings of the present application, or directly/indirectly used in Other related technical fields are included in the patent protection scope of this application.

Claims

A circuit for realizing bus communication, applied to a bus communication system, the bus communication system includes a bus, wherein the circuit for realizing bus communication includes:

A processing module, the processing module has a UART transmitter and a UART receiver, and the UART receiver is electrically connected to the bus;

A transceiver circuit, the input end of the transceiver circuit is connected to the UART transmitter, and the output end of the transceiver circuit is electrically connected to the UART receiver and the bus respectively;

Wherein, the processing module is used to receive the first data sent on the bus through the UART receiving end;

The processing module is also configured to output the second data to the bus and the UART receiving end via the UART transmitting end and the transceiver circuit;

The processing module is also configured to, when outputting the second data via the UART transmitter and the transceiver circuit, if the data received via the UART receiver is different from the second data, stop processing. The UART transmitting end outputs the second data, and confirms that no data has been received by the UART receiving end within the delay time corresponding to the preset source address, and then passes the UART transmitting end and the transceiver again. The circuit outputs the second data to the bus and the UART receiving end.
The circuit for realizing bus communication according to claim 1, wherein the processing module is further configured to, after receiving the first data transmitted on the bus through the UART receiving end, transmit the data via the UART transmitting end and the The transceiver circuit outputs a reception completion signal to the bus.
The circuit for realizing bus communication according to claim 2, wherein both the second data and the first data include address characters corresponding to the preset source address;

The processing module is also configured to encode the characters that are the same as the address characters in the data to be sent according to the preset encoding method corresponding to the address characters to generate the second data, and then use the UART to generate the second data. The transmitting end and the transceiver circuit output the second data to the bus;

The processing module is also configured to, after outputting the second data to the bus via the UART transmitter and the transceiver circuit, if the reception completion signal is not received within the preset completion feedback time, re- Output the second data to the bus via the UART transmitter and the transceiver circuit;

The processing module is also configured to decode the first data according to the address characters of the first data when receiving the first data;

The processing module is further configured to determine that the first data including the previous address character is junk data if the address character is repeatedly received when the first data is received; and the subsequent The data after one of the address characters starts to be received as the new first data.
The circuit for realizing bus communication according to claim 1, wherein the processing module also has a bus status detection terminal, and the bus status detection terminal is electrically connected to the UART receiving terminal;

The processing module is configured to detect the level status of the UART receiving end through the bus status detection end, and determine that the bus is in an idle state when the level status does not change within a preset detection time;

The processing module is also configured to output the second data to the bus and the UART receiving end via the UART transmitting end and the transceiver circuit when it is confirmed that the bus is in an idle state.
The circuit for realizing bus communication according to claim 1, wherein the circuit for realizing bus communication further includes:

A first isolation circuit, the first isolation circuit is connected in series between the UART receiving end and the bus; the first isolation circuit is used to isolate and transmit the first data to the UART receiving end; And also for isolating and transmitting the second data to the UART receiving end;

A second isolation circuit, the second isolation circuit is connected in series between the input end of the transceiver circuit and the UART transmitting end; the second isolation circuit is used to isolate and transmit the second data to the bus and all Described UART receiving end.
The circuit for realizing bus communication according to claim 1, wherein the circuit for realizing bus communication further includes a first current limiting circuit and a second current limiting circuit, and the first current limiting circuit is connected in series to the UART receiving end. and the bus, the second current limiting circuit is connected in series between the UART transmitting end and the transceiver circuit.
The circuit for realizing bus communication according to claim 6, wherein the transceiver circuit includes a first switch tube and a first resistor, the first current limiting circuit includes a second resistor, and the second current limiting circuit includes a third three resistors and the first capacitor;

Wherein, the first end of the first switch tube, the second end of the first resistor and the second end of the second resistor are respectively connected to the bus line, and the first end of the first resistor is connected to the first end of the first resistor. A power supply end is connected, the second end of the first switch tube and the second end of the third resistor are respectively connected to the second end of the first capacitor, and the third end of the first switch tube is grounded, so The first end of the second resistor is connected to the UART receiving end, and the first end of the third resistor and the first end of the first capacitor are electrically connected to the UART transmitting end respectively.
A bus communication system includes a bus and a plurality of circuits for realizing bus communication as described in any one of claims 1 to 7 that are electrically connected to the bus.
A power supply energy storage device, wherein the power supply energy storage device includes a bus and a plurality of circuit modules, and each of the plurality of circuit modules includes a circuit module according to any one of claims 1-7 electrically connected to the bus. A circuit that implements bus communication.
The power supply energy storage device according to claim 9, wherein the power supply energy storage device further includes an interface, the interface is electrically connected to the bus, the interface is used to electrically connect to an external terminal, and the interface is used to The update data sent by the external terminal is accessed and transmitted to the circuit module via the bus and the UART receiving end to update the data in the circuit module.