JPH0787105A - Data transmission equipment - Google Patents

Data transmission equipment

Info

Publication number
JPH0787105A
JPH0787105A JP5224547A JP22454793A JPH0787105A JP H0787105 A JPH0787105 A JP H0787105A JP 5224547 A JP5224547 A JP 5224547A JP 22454793 A JP22454793 A JP 22454793A JP H0787105 A JPH0787105 A JP H0787105A
Authority
JP
Japan
Prior art keywords
transmission
data
circuit
reception
receiving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP5224547A
Other languages
Japanese (ja)
Inventor
Katsumi Isobe
勝己 磯部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Priority to JP5224547A priority Critical patent/JPH0787105A/en
Publication of JPH0787105A publication Critical patent/JPH0787105A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Computer And Data Communications (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To obtain a data transmitter whereby power consumption is saved by stopping the useless operation of a receiving circuit. CONSTITUTION:Multiple transmission/reception terminals 6 are connected to a common data bus 7 and the transmission/reception operation of data is executed between among the respective transmission/reception terminals 6. The transmission/reception terminal 6 is constituted of a transmitting circuit 9 outputting transmission data to a data bus 7, the receiving circuit 8 receiving transmission data outputted to the data bus 7 and a controller 12 controlling the operations of the transmitting circuit 9 and the receiving circuit 8. The controller 12 stops the operation of the receiving circuit 8 when transmission data of the transmitting circuit 9 connected to the controller 12 coincides with reception data of the receiving circuit 8 connected to the controller 12.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】この発明は、複数の送受信端末を
共通のデータバスに接続して各送受信端末間でデータの
伝送を行うデータ伝送装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission device for connecting a plurality of transmission / reception terminals to a common data bus and transmitting data between the transmission / reception terminals.

【０００２】近年、データ伝送装置の一種類として共通
のデータバスに多数の送受信端末を接続し、各送受信端
末間で送受信動作を行うようにしたものがある。このよ
うなデータ伝送装置では各送受信端末の消費電力を低減
することが必要となっている。In recent years, as one type of data transmission device, there has been one in which a large number of transmission / reception terminals are connected to a common data bus and transmission / reception operations are performed between the transmission / reception terminals. In such a data transmission device, it is necessary to reduce the power consumption of each transmission / reception terminal.

【０００３】[0003]

【従来の技術】従来のデータ伝送装置の一例を図６に従
って説明すると、データバス１には多数の送受信端末２
ａ〜２ｄが接続され、各送受信端末２ａ〜２ｄ間で送受
信動作が行われる。2. Description of the Related Art An example of a conventional data transmission apparatus will be described with reference to FIG.
a to 2d are connected, and a transmission / reception operation is performed between the transmission / reception terminals 2a to 2d.

【０００４】図７に示すように、各送受信端末２ａ〜２
ｄは受信回路３と送信回路４及び制御回路５とから構成
され、制御回路５は受信回路３及び送信回路４による送
受信動作を制御する。As shown in FIG. 7, each transmitting / receiving terminal 2a-2
d is composed of the receiving circuit 3, the transmitting circuit 4 and the control circuit 5, and the control circuit 5 controls the transmitting / receiving operation by the receiving circuit 3 and the transmitting circuit 4.

【０００５】このように構成されたデータ伝送装置の動
作を説明すると、各送受信端末２ａ〜２ｄのうち、少な
くとも二つの送受信端末が同時に送信動作を開始する
と、各送受信端末２ａ〜２ｄは送信を行うための競合動
作を行う。The operation of the data transmission apparatus configured as described above will be described. When at least two transmission / reception terminals of the transmission / reception terminals 2a to 2d simultaneously start transmission operation, the transmission / reception terminals 2a to 2d perform transmission. For competing actions.

【０００６】すなわち、各送受信端末２ａ〜２ｄは送信
データをデータバス１に出力し、同時にデータバス１に
伝送されている送信データを受信する状態となる。ここ
で、送信動作を行っている各送受信端末は、自身の出力
している送信データと、データバス１から受信した受信
データとを比較し、両者が一致しない場合は競合に負け
たことを認識し、両者が一致する場合は競合に勝ったこ
とを認識する。That is, each of the transmission / reception terminals 2a to 2d outputs the transmission data to the data bus 1 and simultaneously receives the transmission data transmitted to the data bus 1. Here, each transmission / reception terminal performing the transmission operation compares the transmission data output by itself with the reception data received from the data bus 1, and recognizes that it has lost the competition if they do not match. However, if they match, it recognizes that the competition has been won.

【０００７】そして、競合に勝った場合は送信動作を継
続し、競合に負けた場合は送信動作を停止する。If the competition is won, the transmission operation is continued, and if the competition is lost, the transmission operation is stopped.

【０００８】[0008]

【発明が解決しようとする課題】上記のようなデータ伝
送装置では、上記競合動作に勝った送受信端末２ａ〜２
ｄにおいては、データバス１上の伝送データと自身の出
力する送信データとは一致するため、伝送データの受信
動作は不必要である。In the data transmission apparatus as described above, the transmission / reception terminals 2a-2 which have won the above-mentioned competing operation.
At d, since the transmission data on the data bus 1 and the transmission data output by itself match, the operation of receiving the transmission data is unnecessary.

【０００９】ところが、各送受信端末２ａ〜２ｄはデー
タバス１に伝送されている送信データを各受信回路３で
常時受信している。従って、競合に勝った送受信端末の
受信回路３で無用な伝送データを受信するために、無駄
な電力を消費しているという問題点がある。However, each of the transmission / reception terminals 2a to 2d always receives the transmission data transmitted to the data bus 1 by each reception circuit 3. Therefore, there is a problem that useless power is consumed in order to receive useless transmission data by the receiving circuit 3 of the transmitting / receiving terminal that has won the competition.

【００１０】この発明の目的は、受信回路の無用な動作
を停止させることにより、消費電力の低減を図り得るデ
ータ伝送装置を提供することにある。An object of the present invention is to provide a data transmission device capable of reducing power consumption by stopping useless operation of a receiving circuit.

【００１１】[0011]

【課題を解決するための手段】図１は本発明の原理説明
図である。すなわち、多数の送受信端末６が共通のデー
タバス７に接続され、各送受信端末６間でデータの送受
信動作が行われる。前記送受信端末６は前記データバス
７に送信データを出力する送信回路９と、前記データバ
ス７に出力された送信データを受信する受信回路８と、
該送信回路９及び受信回路８の動作を制御する制御装置
１２とから構成され、前記制御装置１２は該制御装置に
接続された送信回路９の送信データと、該制御装置１２
に接続された受信回路８の受信データとが一致したと
き、前記受信回路８の動作を停止させる。FIG. 1 is a diagram for explaining the principle of the present invention. That is, a large number of transmission / reception terminals 6 are connected to the common data bus 7, and data transmission / reception operations are performed between the transmission / reception terminals 6. The transmission / reception terminal 6 includes a transmission circuit 9 that outputs transmission data to the data bus 7, and a reception circuit 8 that receives the transmission data output to the data bus 7.
And a control device 12 for controlling the operations of the transmission circuit 9 and the reception circuit 8. The control device 12 includes transmission data of the transmission circuit 9 connected to the control device and the control device 12.
When the received data of the receiving circuit 8 connected to the input terminal matches, the operation of the receiving circuit 8 is stopped.

【００１２】また、図２に示すように前記制御装置１２
はカウンタ回路１１が備えられ、前記送信データと受信
データの一致に基づいて前記カウンタ回路１１が起動さ
れ、前記カウンタ回路１１のカウントアップ時間に基づ
いて前記受信回路８が停止される。Further, as shown in FIG.
Is provided with a counter circuit 11, the counter circuit 11 is activated on the basis of a match between the transmission data and the reception data, and the reception circuit 8 is stopped on the basis of the count-up time of the counter circuit 11.

【００１３】[0013]

【作用】送信データと受信データとが一致する送受信端
末６では、制御装置１２により受信回路８の動作が停止
される。この結果、無用な受信動作が防止され、その受
信動作にともなう電力消費が削減される。In the transmitting / receiving terminal 6 in which the transmitted data and the received data match, the controller 12 stops the operation of the receiving circuit 8. As a result, useless reception operation is prevented, and power consumption associated with the reception operation is reduced.

【００１４】[0014]

【実施例】図２〜図５は本発明を具体化した一実施例を
示す。図２に示すように、多数の送受信端末６ａ〜６ｃ
はデータバス７に接続され、同データバス７を介して送
受信動作を行う。各送受信端末６ａ〜６ｃはそれぞれ受
信回路８と、送信回路９と、制御回路１０と、カウンタ
回路１１とから構成される。2 to 5 show an embodiment embodying the present invention. As shown in FIG. 2, a large number of transmission / reception terminals 6a to 6c
Are connected to the data bus 7 and perform transmission / reception operations via the data bus 7. Each of the transmission / reception terminals 6a to 6c is composed of a reception circuit 8, a transmission circuit 9, a control circuit 10, and a counter circuit 11.

【００１５】前記送信回路９から出力される送信データ
は、ホームバスシステム（ＨＢＳ）規格（ＥＴ−２１０
１）に基づき、図３に示すフォーマットで出力される。
すなわち、キャラクタＰＲ〜ＡＣＫ／ＮＡＫで１つのフ
レームＦが構成され、各フレームＦ間には１０μｓの休
止時間ｔが設定されている。The transmission data output from the transmission circuit 9 is the home bus system (HBS) standard (ET-210).
Based on 1), it is output in the format shown in FIG.
That is, the characters PR to ACK / NAK form one frame F, and a pause time t of 10 μs is set between the frames F.

【００１６】各キャラクタＰＲ〜ＡＣＫ／ＮＡＫは、図
４に示すようにビットＳＴ〜ＳＴＰからなる１１ビット
で構成され、各ビットは例えば５Ｖ，２．５Ｖ，０Ｖの
３値の値をもつＡＭＩ（Alternate Mark Inversion）信
号で構成される。そして、各ビットのレベルが５Ｖ若し
くは０Ｖのレベルを含む場合は論理値「０」であり、
２．５Ｖの場合は論理値「１」である。Each character PR to ACK / NAK is composed of 11 bits consisting of bits ST to STP as shown in FIG. 4, and each bit has an AMI (value having three values of 5V, 2.5V, 0V, for example. Alternate Mark Inversion) signal. When the level of each bit includes the level of 5V or 0V, the logical value is “0”,
In the case of 2.5V, the logical value is "1".

【００１７】前記受信回路８はデータバス７上に伝送さ
れている送信データを受信して前記制御回路１０に出力
する。制御回路１０は受信回路８から受信された受信デ
ータの各フレームＦのキャラクタＰＲ，ＳＡと、当該制
御回路１０の制御に基づいて送信回路９から出力される
送信データの各フレームＦのキャラクタＰＲ，ＳＡの各
ビットの値を比較する。The receiving circuit 8 receives the transmission data transmitted on the data bus 7 and outputs it to the control circuit 10. The control circuit 10 receives the characters PR and SA of each frame F of the received data received from the reception circuit 8, and the characters PR and SA of each frame F of the transmission data output from the transmission circuit 9 under the control of the control circuit 10. The value of each bit of SA is compared.

【００１８】そして、その比較結果が一致した場合は、
送信回路９による送信動作を続行させ、比較結果が不一
致の場合は送信回路９による送信動作を停止させるよう
に動作する。If the comparison results are in agreement,
The transmission operation by the transmission circuit 9 is continued, and when the comparison result does not match, the transmission operation by the transmission circuit 9 is stopped.

【００１９】また、前記制御回路１０は受信データのキ
ャラクタＤＡと、当該制御回路１０の制御に基づいて送
信回路９から出力される送信データのキャラクタＤＡと
を比較する。The control circuit 10 also compares the character DA of the received data with the character DA of the transmission data output from the transmission circuit 9 under the control of the control circuit 10.

【００２０】そして、その比較結果が一致した場合は、
受信回路８による受信動作を停止させ、比較結果が不一
致の場合は受信回路８による受信動作を続行させるよう
に動作する。If the comparison results are in agreement,
The receiving operation by the receiving circuit 8 is stopped, and if the comparison result does not match, the receiving operation by the receiving circuit 8 is continued.

【００２１】前記制御回路１０は前記受信回路８に対す
る受信動作停止信号の出力と同時に、前記カウンタ回路
１１にカウント動作を開始させるためのカウント開始信
号を出力する。The control circuit 10 outputs a count start signal for starting the counting operation to the counter circuit 11 at the same time as the reception operation stop signal is output to the reception circuit 8.

【００２２】前記カウンタ回路１１は前記カウント開始
信号に基づいてカウント動作を開始する。カウンタ回路
１１はキャラクタＤＡ〜ＡＣＫ／ＮＡＫまでの７７ビッ
ト分の時間でカウントアップするように設定され、カウ
ントアップ後にカウントアップ信号を制御回路１０に出
力する。The counter circuit 11 starts counting operation based on the count start signal. The counter circuit 11 is set to count up in 77-bit time from the character DA to ACK / NAK, and outputs a count-up signal to the control circuit 10 after the count-up.

【００２３】前記制御回路１０は前記カウントアップ信
号に基づいて、前記受信回路８の受信動作を再開させ
る。次に、上記のように構成されたデータ伝送装置の動
作を説明する。The control circuit 10 restarts the receiving operation of the receiving circuit 8 based on the count-up signal. Next, the operation of the data transmission device configured as described above will be described.

【００２４】さて、送受信端末６ａ，６ｂが送受信端末
６ｃに同時に送信データを送信しようとすると、各送受
信端末６ａ，６ｂの送信回路９からそれぞれデータバス
７に送信データが出力される。When the transmission / reception terminals 6a and 6b try to transmit the transmission data to the transmission / reception terminal 6c at the same time, the transmission data is output from the transmission circuit 9 of each of the transmission / reception terminals 6a and 6b to the data bus 7.

【００２５】このとき、各送受信端末６ａ〜６ｃの受信
回路８はデータバス７に伝送されている送信データを受
信している。この状態で、送受信端末６ａ，６ｂの制御
回路１０はデータバス７から各受信回路８を介して入力
される受信データのキャラクタＰＲ，ＳＡと、各送受信
端末６ａ，６ｂの送信回路９から出力される送信データ
のキャラクタＰＲ，ＳＡとを比較する。At this time, the reception circuit 8 of each of the transmission / reception terminals 6a-6c is receiving the transmission data transmitted to the data bus 7. In this state, the control circuit 10 of the transmission / reception terminals 6a and 6b outputs the characters PR and SA of the reception data input from the data bus 7 via the reception circuits 8 and the transmission circuits 9 of the transmission / reception terminals 6a and 6b. The transmitted data characters PR and SA are compared.

【００２６】ここで、各送受信端末６ａ，６ｂから図５
に示す内容でキャラクタＰＲ，ＳＡが出力され、データ
バス７には送受信端末６ａの送信回路９から出力された
送信データが伝送されているとすると、送受信端末６ｂ
の制御回路１０はキャラクタＳＡのビットｂ２において
データバス７上の伝送データと送受信端末６ｂの送信デ
ータとが一致しないことを認識する。Here, from the transmitting / receiving terminals 6a and 6b, as shown in FIG.
Assuming that the characters PR and SA are output with the contents shown in FIG. 2 and the transmission data output from the transmission circuit 9 of the transmission / reception terminal 6a is transmitted to the data bus 7, the transmission / reception terminal 6b
The control circuit 10 recognizes that the transmission data on the data bus 7 and the transmission data of the transmission / reception terminal 6b do not match at bit b2 of the character SA.

【００２７】すると、送受信端末６ｂの制御回路１０は
競合に負けたことを認識し、送信回路９の送信動作を停
止させる。次いで、各送受信端末６ａ〜６ｃの各制御回
路１０はデータバス７から各受信回路８を介して入力さ
れる受信データのキャラクタＤＡと、各送信回路９から
出力される送信データのキャラクタＤＡとを比較する。Then, the control circuit 10 of the transmission / reception terminal 6b recognizes that the competition has been lost and stops the transmission operation of the transmission circuit 9. Next, each control circuit 10 of each of the transmission / reception terminals 6a to 6c outputs the character DA of the received data input from the data bus 7 via each receiving circuit 8 and the character DA of the transmission data output from each transmitting circuit 9. Compare.

【００２８】すると、送受信端末６ｂ，６ｃでは送信動
作を停止し、送受信端末６ａのみが送信動作を行ってい
るため、同送受信端末６ａでは受信回路８を介して制御
回路１０に入力されるキャラクタＤＡと、送信回路９を
介して出力されるキャラクタＤＡとが一致する。Then, the transmission / reception terminals 6b and 6c have stopped the transmission operation, and only the transmission / reception terminal 6a is performing the transmission operation. And the character DA output via the transmission circuit 9 match.

【００２９】すると、送受信端末６ａの制御回路１０は
同送受信端末６ａの受信回路８の動作を停止させ、カウ
ンタ回路１１のカウント動作を開始させる。次いで、カ
ウンタ回路１１がキャラクタＤＡ〜ＡＣＫ／ＮＡＫまで
の７７ビット分の時間をカウントアップすると、同カウ
ンタ回路１１は制御回路１０にカウントアップ信号を出
力する。そして、制御回路１０は受信回路８の受信動作
を再開させ、データバス７に伝送される次のフレームＦ
を受信して、再び競合動作を行い得る状態となる。Then, the control circuit 10 of the transmitting / receiving terminal 6a stops the operation of the receiving circuit 8 of the transmitting / receiving terminal 6a and starts the counting operation of the counter circuit 11. Next, when the counter circuit 11 counts up the 77-bit time from the character DA to ACK / NAK, the counter circuit 11 outputs a count-up signal to the control circuit 10. Then, the control circuit 10 restarts the receiving operation of the receiving circuit 8, and the next frame F transmitted to the data bus 7 is transmitted.
Is received, and the contention operation can be performed again.

【００３０】以上のようにこのデータ伝送装置では、競
合に勝った送受信端末では、送信回路９から送信する送
信データと、受信回路８で受信する受信データとが一致
する場合には、データバス７上の伝送データを受信する
必要はないので、当該送受信端末の受信回路８の動作が
停止される。As described above, in this data transmission device, in the transmission / reception terminal which has won the competition, when the transmission data transmitted from the transmission circuit 9 and the reception data received by the reception circuit 8 match, the data bus 7 Since it is not necessary to receive the above transmission data, the operation of the receiving circuit 8 of the transmitting / receiving terminal is stopped.

【００３１】従って、受信回路８の無用な動作にともな
う消費電力の増大を防止することができる。Therefore, it is possible to prevent the power consumption from increasing due to the unnecessary operation of the receiving circuit 8.

【００３２】[0032]

【発明の効果】以上詳述したように、この発明は受信回
路の無用な動作を停止させることにより、消費電力の低
減を図り得るデータ伝送装置を提供することができる優
れた効果を発揮する。As described above in detail, the present invention exerts an excellent effect that it is possible to provide the data transmission device capable of reducing the power consumption by stopping the unnecessary operation of the receiving circuit.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の原理説明図である。FIG. 1 is a diagram illustrating the principle of the present invention.

【図２】一実施例のデータ伝送装置を示すブロック図で
ある。FIG. 2 is a block diagram showing a data transmission device according to an embodiment.

【図３】フレームの内容を示す説明図である。FIG. 3 is an explanatory diagram showing contents of a frame.

【図４】各キャラクタの一例を示す説明図である。FIG. 4 is an explanatory diagram showing an example of each character.

【図５】競合動作を示す説明図である。FIG. 5 is an explanatory diagram showing a competing operation.

【図６】従来例のデータ伝送装置を示すブロック図であ
る。FIG. 6 is a block diagram showing a conventional data transmission device.

【図７】従来例の送受信端末を示すブロック図である。FIG. 7 is a block diagram showing a transmission / reception terminal of a conventional example.

【符号の説明】 ６ 送受信端末 ７ データバス ８ 受信回路 ９ 送信回路 １２ 制御装置[Explanation of Codes] 6 Transmission / Reception Terminal 7 Data Bus 8 Reception Circuit 9 Transmission Circuit 12 Control Device

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 多数の送受信端末（６）を共通のデータ
バス（７）に接続し、各送受信端末（６）間でデータの
送受信動作を行うデータ伝送装置であって、 前記送受信端末（６）は前記データバス（７）に送信デ
ータを出力する送信回路（９）と、前記データバス
（７）に出力された送信データを受信する受信回路
（８）と、該送信回路（９）及び受信回路（８）の動作
を制御する制御装置（１２）とから構成し、前記制御装
置（１２）は該制御装置に接続された送信回路（９）の
送信データと、該制御装置（１２）に接続された受信回
路（８）の受信データとが一致したとき、前記受信回路
（８）の動作を停止させることを特徴とするデータ伝送
装置。1. A data transmission device for connecting a large number of transmission / reception terminals (6) to a common data bus (7) and performing a data transmission / reception operation between the transmission / reception terminals (6), said transmission / reception terminals (6). ) Is a transmission circuit (9) for outputting transmission data to the data bus (7), a reception circuit (8) for receiving the transmission data output to the data bus (7), the transmission circuit (9) and A control device (12) for controlling the operation of the receiving circuit (8), the control device (12) transmitting data of a transmission circuit (9) connected to the control device, and the control device (12). A data transmission device, which stops the operation of the receiving circuit (8) when the received data of the receiving circuit (8) connected to the same coincide with each other. 【請求項２】 前記制御装置（１２）はカウンタ回路
（１１）を備え、前記送信データと受信データの一致に
基づいて前記カウンタ回路（１１）を起動し、前記カウ
ンタ回路（１１）のカウントアップ時間に基づいて前記
受信回路（８）を停止させることを特徴とする請求項１
記載のデータ伝送装置。2. The control device (12) includes a counter circuit (11), starts the counter circuit (11) based on a match between the transmission data and the reception data, and counts up the counter circuit (11). 2. The receiving circuit (8) is stopped based on time.
The described data transmission device.
JP5224547A 1993-09-09 1993-09-09 Data transmission equipment Withdrawn JPH0787105A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5224547A JPH0787105A (en) 1993-09-09 1993-09-09 Data transmission equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5224547A JPH0787105A (en) 1993-09-09 1993-09-09 Data transmission equipment

Publications (1)

Publication Number Publication Date
JPH0787105A true JPH0787105A (en) 1995-03-31

Family

ID=16815507

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5224547A Withdrawn JPH0787105A (en) 1993-09-09 1993-09-09 Data transmission equipment

Country Status (1)

Country Link
JP (1) JPH0787105A (en)

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