WO2023168563A1 - 显示面板和母板结构、显示装置 - Google Patents

显示面板和母板结构、显示装置 Download PDF

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Publication number
WO2023168563A1
WO2023168563A1 PCT/CN2022/079573 CN2022079573W WO2023168563A1 WO 2023168563 A1 WO2023168563 A1 WO 2023168563A1 CN 2022079573 W CN2022079573 W CN 2022079573W WO 2023168563 A1 WO2023168563 A1 WO 2023168563A1
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WIPO (PCT)
Prior art keywords
display panel
crack
layer
area
display
Prior art date
Application number
PCT/CN2022/079573
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English (en)
French (fr)
Inventor
代俊秀
白露
周洋
屈忆
王思雨
刘松
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/079573 priority Critical patent/WO2023168563A1/zh
Priority to CN202280000395.8A priority patent/CN117242916A/zh
Publication of WO2023168563A1 publication Critical patent/WO2023168563A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes

Definitions

  • the present disclosure relates to the field of display technology, and specifically to a display panel and motherboard structure, and a display device.
  • the purpose of this disclosure is to overcome the above-mentioned shortcomings of the prior art, provide a display panel and motherboard structure, and a display device to reduce edge crack defects.
  • a display panel including a display area and a peripheral area surrounding the display area; the peripheral area has an inner cutting lane surrounding the display area and is located near the inner cutting lane.
  • the first crack retaining wall on one side of the display area.
  • the display panel in at least part of the peripheral area, further has an outer cutting track located on a side of the inner cutting track away from the display area; an end of the outer cutting track The part intersects with the inner cutting channel.
  • an identification mark is provided on a side of the inner cutting lane away from the display area; at least part of the identification mark is disposed in the outer cutting lane.
  • the second crack retaining wall is provided between the identification mark and the inner cutting lane.
  • an identification mark is provided on a side of the inner cutting lane away from the display area; at least part of the identification mark is located between the outer cutting lane and the inner cutting lane, and the The width of the portion of the outer cutting track close to the identification mark is smaller than the width of other portions of the outer cutting track;
  • the second crack retaining wall is disposed between the identification mark and the inner cutting lane.
  • a crack blocking groove is provided between two adjacent second crack retaining walls, and the crack blocking groove is filled with organic material.
  • the display panel in the area where the second crack barrier is located, includes an organic substrate, an inorganic material layer and an organic material layer that are stacked in sequence;
  • the groove bottom of at least one of the crack blocking grooves is located in the inorganic material layer.
  • the display panel in the area where the second crack barrier is located, includes an organic substrate, an inorganic material layer and an organic material layer that are stacked in sequence;
  • the groove bottom of at least one of the crack blocking trenches is located on the organic substrate.
  • the inorganic material layer includes an inorganic barrier layer, an inorganic buffer layer, a gate insulating layer, and an interlayer dielectric layer sequentially stacked on one side of the organic substrate;
  • the bottom of the crack blocking trench is located on the inorganic buffer layer, the inorganic barrier layer or the organic substrate.
  • the number of the second crack retaining walls ranges from 2 to 8.
  • the width of the second crack retaining wall is in the range of 5 to 15 microns.
  • the crack blocking groove has a width in a range of 5 to 10 microns.
  • the ratio of the width of the second crack blocking wall to the width of the crack blocking groove is between 0.8 and 1.2.
  • the peripheral area includes a first peripheral area, a second peripheral area, a third peripheral area and a fourth peripheral area that surround the display area and are connected end to end in sequence; the first peripheral area It is arranged opposite to the third peripheral area; the first peripheral area has a bonding pad for bonding external circuits;
  • the outer cutting lane is provided in the first peripheral area and/or the third peripheral area.
  • the display panel has rounded corners; an edge of at least one of the rounded corners partially coincides with the outer cutting lane.
  • the number of the outer cutting lanes is multiple and they are arranged sequentially in a direction away from the display area;
  • the second crack retaining wall is provided between the outer cutting lane closest to the display area and the inner cutting lane.
  • the display panel is provided with crack detection wiring in the peripheral area; the crack detection wiring is provided between the first crack blocking wall and the display area.
  • a motherboard structure wherein the motherboard structure includes the above-mentioned display panel; between the display panels, the motherboard structure has main cutting lanes;
  • an outer cutting lane is provided in at least part of the area; the end of the outer cutting lane intersects with the inner cutting lane; the outer cutting lane and A second crack retaining wall is provided between the inner cutting lanes.
  • a display device including the above-mentioned display panel.
  • Figure 1 is a schematic structural diagram of a motherboard structure in an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of the film structure of a display panel in an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of a display panel in an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a portion of the display panel within the inner cutting lane in an embodiment of the present disclosure.
  • Figure 5 is a schematic structural diagram of a sub-board structure in an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of the cutting track of the sub-board structure in an embodiment of the present disclosure.
  • Figure 7 is a schematic structural diagram of the cutting track of the sub-board structure in an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of the cutting track of the sub-board structure in an embodiment of the present disclosure.
  • Figure 9 is a partial structural schematic diagram of the sub-board structure in a compatible cutting area in an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of the film layer structure near the edge of the display panel in an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of the first crack blocking trench filled with an organic material layer in an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of a second crack blocking trench filled with an organic material layer in an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of a third crack blocking trench filled with an organic material layer in an embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of an embodiment of the present disclosure in which each crack blocking trench is a first crack blocking trench.
  • FIG. 15 is a schematic structural diagram of an embodiment of the present disclosure in which each crack blocking trench is a second crack blocking trench.
  • FIG. 16 is a schematic structural diagram of an embodiment of the present disclosure in which each crack blocking trench is a third crack blocking trench.
  • FIG. 17 is a schematic structural diagram of an embodiment of the present disclosure, in which the crack blocking trenches are both first crack blocking trenches and second crack blocking trenches.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • the present disclosure provides a motherboard structure and a display panel PNL cut out from the motherboard structure.
  • the display panel PNL can be used as a display panel or as part of a display module for display.
  • the display panel may include an organic substrate BP, a driving circuit layer F200 and a pixel layer F300 that are stacked in sequence.
  • the material of the organic substrate BP may be polyimide (PI), polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA) , polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate Polyethylene terephthalate (PET), polyethylene naphthalate (PEN) or combinations thereof.
  • the organic substrate BP may be a flexible substrate BP, and its material may be polyimide.
  • the organic substrate BP may also be a composite of multiple layers of materials.
  • the organic substrate BP may include a bottom film layer (Bottom Film), a pressure-sensitive adhesive layer, a first polyimide layer and a second polyimide layer that are stacked in sequence.
  • the drive circuit layer F200 is provided with a pixel drive circuit for driving sub-pixels.
  • any pixel driving circuit may include a transistor F200M and a storage capacitor.
  • the transistor F200M may be a thin film transistor, and the thin film transistor may be selected from a top gate thin film transistor, a bottom gate thin film transistor, or a dual gate thin film transistor;
  • the material of the active layer of the thin film transistor may be an amorphous silicon semiconductor material, a low temperature Polycrystalline silicon semiconductor material, metal oxide semiconductor material, organic semiconductor material or other types of semiconductor materials;
  • the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor.
  • the types of any two transistors may be the same or different.
  • some transistors may be N-type transistors and some transistors may be P-type transistors.
  • the material of the active layer of some transistors may be a low-temperature polysilicon semiconductor material, and the material of the active layer of some of the transistors may be metal. Oxide semiconductor materials.
  • the thin film transistor is a low temperature polysilicon transistor. In other embodiments of the present disclosure, some thin film transistors are low temperature polysilicon transistors, and some thin film transistors are metal oxide transistors.
  • the driving circuit layer F200 may include a semiconductor layer SEMI, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD and a source and drain metal layer SD stacked between the organic substrate BP and the pixel layer F300. wait.
  • Each thin film transistor and storage capacitor can be formed by a semiconductor layer SEMI, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source-drain metal layer SD and other film layers. The positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor.
  • the semiconductor layer SEMI can be used to form the channel region of the transistor; the gate layer can be used to form gate layer wiring such as scan leads, reset control leads, light emission control leads, etc., and can also be used to form the gate of the transistor. It can also be used to form part or all of the electrode plates of the storage capacitor; the source-drain metal layer can be used to form source-drain metal layer wiring such as data leads and driving power leads, and can also be used to form part of the electrode plates of the storage capacitor.
  • the driving circuit layer F200 may include a semiconductor layer SEMI, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD and a source and drain metal layer SD that are stacked in sequence.
  • the thin film transistor formed in this way is a top gate thin film transistor.
  • the driving circuit layer F200 may include a gate layer GT, a gate insulating layer GI, a semiconductor layer SEMI, an interlayer dielectric layer ILD and a source and drain metal layer SD that are stacked in sequence.
  • the thin film transistor formed in this way is a bottom gate thin film transistor.
  • the gate layer may be two layers or three layers.
  • the gate layer GT may include a first gate layer and a second gate layer
  • the gate insulating layer GI may include a semiconductor layer SEMI for isolating the first gate layer. a first gate insulating layer, and a second gate insulating layer for isolating the first gate layer and the second gate layer.
  • the driving circuit layer F200 may include a semiconductor layer SEMI, a first gate insulating layer, a first gate layer, a second gate insulating layer, and a second gate that are sequentially stacked on one side of the organic substrate BP. layer, interlayer dielectric layer ILD and source-drain metal layer SD.
  • the gate layer GT may include a first gate layer and a second gate layer, and the semiconductor layer SEMI may be sandwiched between the first gate layer and the second gate layer.
  • the gate insulating layer GI may include a first gate insulating layer for isolating the semiconductor layer SEMI and the first gate electrode layer, and a second gate electrode for isolating the second gate electrode layer and the semiconductor layer SEMI. Insulation.
  • the driving circuit layer F200 may include a first gate layer, a first gate insulating layer, a semiconductor layer SEMI, a first gate electrode layer and a first gate electrode layer disposed on one side of the organic substrate BP.
  • the semiconductor layer SEMI may include a low-temperature polysilicon semiconductor layer and a metal oxide semiconductor layer; the gate layer includes a first gate layer and a second gate layer, and the gate insulation The layers include first and second gate insulating layers.
  • the driving circuit layer F200 may include a low-temperature polysilicon semiconductor layer, a first gate insulating layer, a first gate layer, a metal oxide semiconductor layer, a second gate insulating layer, and a second gate insulating layer which are sequentially stacked on one side of the organic substrate BP.
  • the semiconductor layer SEMI may include a low-temperature polysilicon semiconductor layer and a metal oxide semiconductor layer; the gate electrode layer includes first to third gate electrode layers, and the gate insulating layer includes a third gate electrode layer. first to third gate insulating layers.
  • the driving circuit layer F200 may include a low-temperature polysilicon semiconductor layer, a first gate insulating layer, a first gate layer, an insulating buffer layer, a second gate layer, and a second gate layer that are sequentially stacked on one side of the organic substrate BP. Insulating layer, metal oxide semiconductor layer, third gate insulating layer, third gate layer, interlayer dielectric layer ILD and source-drain metal layer SD.
  • the source and drain metal layers may be two layers or three layers.
  • the source-drain metal layer may include a first source-drain metal layer and a second source-drain metal layer sequentially stacked on the side of the interlayer dielectric layer ILD away from the base substrate.
  • An insulating layer such as a passivation layer and/or a planarization layer, may be sandwiched between the first source-drain metal layer and the second source-drain metal layer.
  • the source-drain metal layer may include a first source-drain metal layer and a second source-drain metal layer sequentially stacked on the side of the interlayer dielectric layer ILD away from the base substrate.
  • the third source-drain metal layer; the first source-drain metal layer and the second source-drain metal layer may be sandwiched by an insulating layer, such as a passivation layer and/or a resin layer; the second source-drain metal layer and the third source-drain metal layer
  • the three source and drain metal layers may be sandwiched by an insulating layer, such as a passivation layer and/or a planarization layer.
  • the driving circuit layer F200 may also include a passivation layer, and the passivation layer may be provided on the surface of the source and drain metal layer SD away from the organic substrate BP, so as to protect the source and drain metal layer SD.
  • the driving circuit layer F200 may also include an inorganic buffer layer Buff disposed between the organic substrate BP and the semiconductor layer SEMI, and the semiconductor layer SEMI, gate layer GT, etc. are located away from the inorganic buffer layer Buff and away from the organic substrate.
  • the material of the inorganic buffer layer Buff can be inorganic insulating materials such as silicon oxide and silicon nitride.
  • the buffer material layer may be a layer of inorganic material, or may be multiple layers of laminated inorganic material.
  • the driving circuit layer F200 may also include an inorganic barrier layer Barr disposed between the organic substrate BP and the inorganic buffer layer Buff.
  • the barrier layer may shield the organic substrate BP to avoid formation of the organic substrate BP. SEMI penetrates into the semiconductor layer and affects the stability of the pixel drive circuit.
  • the driving circuit layer F200 may also include a planarization layer PLN located between the source-drain metal layer SD and the pixel layer F300.
  • the planarization layer PLN may provide a planarized surface for the pixel electrode.
  • the material of the planarization layer PLN may be an organic material.
  • each layer of inorganic material may constitute the inorganic material layer BIL of the display panel PNL.
  • the inorganic material layer BIL of the display panel PNL may include an inorganic barrier layer Barr, an inorganic buffer layer Buff, a gate insulating layer GI, and an inorganic barrier layer Barr layered on the organic substrate BP in sequence. Interlayer dielectric layer ILD, etc.
  • the inorganic material layer BIL may also include a passivation layer PVX. It can be understood that in the display panel PNL shown in FIG.
  • the gate insulating layer GI includes two layers: a first gate insulating layer GI1 and a second gate insulating layer GI2. In other embodiments of the present disclosure, the gate insulating layer GI may be one layer, or three or more layers.
  • the thickness of the inorganic barrier layer Barr can be in the range of 450 to 650 nanometers, for example, it can be 550 nanometers.
  • the thickness of the inorganic buffer layer Buff can be in the range of 300 to 500 nanometers, for example, can be 400 nanometers.
  • the thickness of the first gate insulating layer GI1 may be in the range of 100 to 150 nanometers, for example, 120 nanometers.
  • the thickness of the second gate insulating layer GI2 may be in the range of 100 to 150 nanometers, for example, 130 nanometers.
  • the thickness of the interlayer dielectric layer ILD may be in the range of 400 to 600 nanometers, for example, 500 nanometers.
  • the thickness of the passivation layer PVX can be in the range of 100 to 200 nanometers, for example, it can be 150 nanometers.
  • the pixel layer F300 may be provided with sub-pixels.
  • the pixel electrode, the common electrode and the liquid crystal layer may form an optical switch that controls the polarization direction of light, and the optical switch may serve as a sub-pixel of the present disclosure.
  • the pixel layer may be provided with a light-emitting element electrically connected to the pixel driving circuit, and the light-emitting element may serve as a sub-pixel of the display panel.
  • the pixel layer is provided with light-emitting elements distributed in an array, and each light-emitting element emits light under the control of the pixel driving circuit.
  • the light-emitting element may be an organic electroluminescent diode (OLED), a micro-light emitting diode (Micro LED), a quantum dot-organic electroluminescent diode (QD-OLED), a quantum dot light-emitting diode (QLED), or other types light-emitting components.
  • the light-emitting element is an organic electroluminescent diode (OLED), then the display panel is an OLED display panel.
  • OLED organic electroluminescent diode
  • the pixel layer F300 may be disposed on a side of the driving circuit layer F200 away from the organic substrate BP, and may include a pixel electrode layer F301, a pixel definition layer F302, a support pillar layer F303, and an organic light-emitting functional layer that are stacked in sequence. F304 and common electrode layer F305.
  • the pixel electrode layer F301 has multiple pixel electrodes in the display area of the display panel;
  • the pixel definition layer F302 has multiple through pixel openings in the display area that are arranged in one-to-one correspondence with the multiple pixel electrodes. Any one pixel opening exposes the corresponding At least part of the pixel electrode.
  • the support pillar layer F303 includes a plurality of support pillars in the display area, and the support pillars are located on the surface of the pixel definition layer F302 away from the organic substrate BP to support the fine metal mask (Fine Metal MAsk, FMM) during the evaporation process.
  • the organic light-emitting functional layer F304 covers at least the pixel electrode exposed by the pixel defining layer F302.
  • the organic light-emitting functional layer F304 may include an organic electroluminescent material layer, and may include one of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer and an electron injection layer. Or multiple.
  • Each layer of the organic light-emitting functional layer F304 can be prepared through an evaporation process, and a fine metal mask or an open mask (Open MAsk) can be used to define the pattern of each layer during evaporation.
  • the common electrode layer F305 can cover the organic light-emitting functional layer F304 in the display area. In this way, the pixel electrode, the common electrode layer F305 and the organic light-emitting functional layer F304 located between the pixel electrode and the common electrode layer F305 form an organic electroluminescent diode F300D. Any organic electroluminescent diode can be used as a sub-pixel of the display panel.
  • the pixel layer F300 may also include a light extraction layer located on the side of the common electrode layer F305 away from the organic substrate BP to enhance the light extraction efficiency of the organic light emitting diode.
  • the organic material layer BOL may include film layers such as a planarization layer and a pixel definition layer. It can be understood that in the motherboard structure and display panel PNL of the present disclosure, depending on the type and process of the display panel PNL, the inorganic material layer BIL can be a combination of other different inorganic layers, and the organic material layer BOL can be other organic materials. layer or other combination of organic layers.
  • the display panel may further include a film encapsulation layer F400.
  • the thin film encapsulation layer F400 is provided on the surface of the pixel layer F300 away from the organic substrate BP, and may include alternately stacked inorganic encapsulation layers and organic encapsulation layers.
  • the inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the organic light-emitting functional layer F304 and causing material degradation.
  • the edge of the inorganic encapsulation layer may be located in the peripheral area.
  • the organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers.
  • the edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer.
  • the thin film encapsulation layer F400 includes a first inorganic encapsulation layer F401, an organic encapsulation layer F402 and a second inorganic encapsulation layer F403 sequentially stacked on the side of the pixel layer F300 away from the organic substrate BP.
  • the display panel may also include a touch functional layer F500.
  • the touch functional layer F500 is provided on a side of the thin film encapsulation layer F400 away from the organic substrate BP, and is used to implement a touch operation of the display panel.
  • the display panel may also include an anti-reflection layer F600.
  • the anti-reflection layer F600 may be disposed on a side of the film encapsulation layer F400 away from the pixel layer F300 to reduce the reflection of ambient light by the display panel, thereby reducing the impact of ambient light on the display. effect.
  • the anti-reflection layer F600 may include a stacked color filter layer and a black matrix layer, which can avoid reducing the light transmittance of the display panel while reducing ambient light interference.
  • the anti-reflection layer F600 may be a polarizer, such as a patterned coated circular polarizer. Further, the anti-reflection layer F600 may be disposed on a side of the touch function layer F500 away from the organic substrate BP.
  • FIG. 1 shows a schematic plan view of the motherboard structure.
  • a motherboard structure has a plurality of display panels PNL, such as display panels PNL having an array distribution. Between the display panels PNL, a main cutting track MCUT is provided on the motherboard structure.
  • Each sub-board structure MM includes one display panel PNL.
  • the main cutting track MCUT defines the edge of the sub-board structure MM.
  • the sub-board structure MM is further cut to obtain the required display panel PNL.
  • Figure 3 shows a schematic plan view of the display panel PNL
  • Figure 4 shows a schematic plan view of the display panel PNL within the inner cutting lane ICUT
  • Figure 5 shows a schematic plan view of the sub-board structure MM
  • Figure 8 shows a schematic structural diagram of the display panel PNL that can be obtained based on the sub-board structure MM of Figure 5.
  • the display panel PNL includes a display area AA and a peripheral area BB surrounding the display area AA.
  • the display panel PNL has an inner cutting track ICUT surrounding the display area AA.
  • the area between the inner cutting lane ICUT and the main cutting lane MCUT (including the inner cutting lane ICUT) is at least partially a compatible cutting area MA, and an outer cutting lane OCUT is provided in the compatible cutting area MA.
  • at least part of the area between the inner cutting track ICUT and the main cutting track MCUT is provided with the outer cutting track OCUT, and these areas where the outer cutting track OCUT is provided are the compatible cutting areas MA.
  • the inorganic materials in the inner cutting lane ICUT and the outer cutting lane OCUT are removed or thinned to reduce the risk of cracks during cutting and reduce the size of the cracks, providing a good quality of the display panel. efficiency and reliability.
  • one end of the outer cutting channel OCUT intersects with the inner cutting channel ICUT, and the other end intersects with the inner cutting channel ICUT or with the main cutting channel MCUT. .
  • the cutting track is within the inner cutting lane ICUT.
  • cutting can be done along the inner cutting track ICUT or the outer cutting track OCUT; that is, in the compatible cutting area MA, the cutting track can be within the inner cutting track ICUT or the outer cutting track OCUT.
  • the cutting lane selected when cutting the sub-board structure MM ultimately defines the edge EE of the display panel PNL; the area between the edge EE of the display panel PNL and the main cutting lane MCUT is the area to be removed.
  • the motherboard structure is provided with an outer cutting track OCUT in the compatible cutting area MA, it is possible to combine different cutting tracks by selecting different cutting tracks to obtain different display panels PNL, thus achieving the goal of using the same motherboard.
  • the purpose of preparing different display panels PNL with a board structure is to improve the versatility of the motherboard structure, reduce the cost of the display panel PNL, and meet the individual needs of different display products for the display panel PNL.
  • the start node and the end node of the compatible cutting area MA can be defined according to the intersection node of the outer cutting track OCUT and the inner cutting track ICUT.
  • Figure 5 shows that the sub-board structure MM has a compatible cutting area MA, and the compatible cutting area MA has three external cutting tracks: a first outer cutting track OCUT1, a second outer cutting track OCUT2 and a third outer cutting track OCUT3.
  • Example of cutting lane OCUT It can be understood that in other embodiments of the present disclosure, the sub-board structure MM may have multiple compatible cutting areas MA, and the compatible cutting areas MA may have more or less outer cutting lanes OCUT. Taking the sub-board structure MM shown in Figure 5 as an example, there are two first outer cutting lanes OCUT1.
  • the first outer cutting lanes OCUT1 correspond one to one, one end of the third outer cutting lane OCUT3 intersects with the main cutting lane MCUT, and the other end intersects with the end of the corresponding first outer cutting lane OCUT1 away from the display area AA.
  • the cutting track outside the compatible cutting area MA can be set along the inner cutting track ICUT.
  • the compatible cutting area MA in the above example there are three different cutting trajectories that can be selected, namely, select the inner cutting lane ICUT as the cutting trajectory, select the first outer cutting lane OCUT1-the second outer cutting lane OCUT2-the first The outer cutting track OCUT1 is used as the cutting track, and the first outer cutting track OCUT1 - the third outer cutting track OCUT3 - the third outer cutting track OCUT3 - the first outer cutting track OCUT1 are selected as the cutting track.
  • the inner cutting track ICUT is selected as the cutting track in the compatible cutting area MA; the thick line EE in Figure 6 indicates the cutting track, and the thick line EE also indicates the cut display panel PNL edge; the overall shape and extent of the display panel PNL is illustrated by dot matrix filling.
  • the first outer cutting track OCUT1-the second outer cutting track OCUT2-the first outer cutting track OCUT1 is selected as the cutting track in the compatible cutting area MA; shown in Figure 7 by the thick line EE
  • the thick line EE also represents the edge of the cut display panel PNL; the overall shape and range of the display panel PNL is indicated by dot matrix filling.
  • the first outer cutting lane OCUT1-the third outer cutting lane OCUT3-the third outer cutting lane OCUT3-the first outer cutting lane OCUT1 are selected as the cutting track in the compatible cutting area MA;
  • the thick line EE represents the cutting trajectory, and the thick line EE also represents at least part of the edge of the cut display panel PNL; the overall shape and range of the display panel PNL is illustrated by dot matrix filling. It can be seen from this that in the compatible cutting area MA, different cutting tracks are selected to form different cutting tracks, and different display panels PNL can be cut; the actual cutting track defines the edge of the display panel PNL.
  • the obtained display panel PNL may not have a compatible cutting area MA, that is, parts other than each inner cutting lane ICUT (including each outer cutting lane) OCUT) can be cut out.
  • the motherboard structure of the present disclosure can have display panels PNL distributed in an array, and the edges of the display panel PNL are defined by the inner cutting lane ICUT; the outer cutting lane OCUT can be provided outside the display panel PNL to improve the versatility of the motherboard structure.
  • These outer cutting lanes OCUT and the like are cut off when cutting to form the display panel PNL.
  • the display panel PNL when the outer cutting track OCUT is selected as the cutting track in a certain compatible cutting area MA, the display panel PNL retains at least part of the compatible cutting area MA.
  • FIG. 10 shows a schematic diagram of the film structure of the display panel PNL in the area near the edge.
  • the display panel PNL includes an organic substrate BP, an inorganic material layer BIL and an organic material layer BOL that are stacked in sequence.
  • the inorganic material layer BIL can be thinned or removed to form an annular cutting groove, and the cutting groove is filled with the organic material layer BOL.
  • the inner cutting channel ICUT has less or no inorganic material, which can reduce the occurrence of cracks both during and after cutting.
  • the inorganic material in the inner cutting lane ICUT may be completely removed.
  • a first crack retaining wall DAM1 is provided in the peripheral area BB, inside the inner cutting lane ICUT (ie, the side of the inner cutting lane ICUT close to the display area AA) .
  • the first crack blocking wall DAM1 can prevent cracks from spreading from the edge of the display panel PNL to the display area AA during cutting, thereby achieving the purpose of protecting the display panel PNL.
  • the first crack retaining wall DAM1 includes multiple strips and is composed of an inorganic material layer BIL.
  • a trench is provided between two adjacent first crack retaining walls DAM1, and the trench is filled with an organic material layer. BOL.
  • the inorganic material layer BIL can be thinned or removed to form a trench, and the remaining part of the inorganic material layer BIL can serve as the first crack retaining wall DAM1.
  • the trenches between the first crack retaining walls DAM1 can also be covered with inorganic materials, such as covering the passivation layer, as long as the inorganic material does not fill the trenches.
  • the display panel PNL is also provided with a crack detection trace PCD between the display area AA and the first crack blocking wall DAM1 for detecting cracks at the edge of the display panel PNL. . If the crack passes through the first crack retaining wall DAM1 and extends to the vicinity of the crack detection trace PCD, the crack detection trace PCD may be disconnected or its resistance may change. In this way, the crack at the edge of the display panel PNL can be monitored by monitoring the state of the crack detection trace PCD.
  • the number of crack detection wiring PCDs is multiple to improve the sensitivity and accuracy of crack monitoring.
  • the peripheral area BB includes a first peripheral area B1, a second peripheral area B2, a third peripheral area B3 and a fourth peripheral area B1, B2, B3 and a fourth peripheral area B1, B2, B2, B2, B2, B3, B3, B3, B3 and B3, which surround the display area AA and are connected end to end.
  • the outer cutting track OCUT is provided in the first peripheral area B1 and/or the third peripheral area B3.
  • one end close to the first peripheral area B1 can be defined as the proximal end of the display panel PNL or the sub-board structure MM
  • the end close to the third peripheral area B3 can be defined as the far end of the display panel PNL or the sub-board structure MM. end.
  • the outer cutting track OCUT may be disposed in the proximal region or the distal region of the sub-board structure MM, or may be disposed in the proximal region or the distal region at the same time.
  • part or all of the first peripheral area B1 is a part of the compatible cutting area MA, and an outer cutting track OCUT is provided in the compatible cutting area MA.
  • part or all of the third peripheral area B3 is a part of the compatible cutting area MA, and the outer cutting track OCUT is provided in the compatible cutting area MA.
  • part or the whole of the first peripheral area B1 is part of the compatible cutting area MA, and an outer cutting track OCUT is provided in the compatible cutting area MA; and part or the whole of the third peripheral area B3 is part of the compatible cutting area MA.
  • a part of the compatible cutting area MA is provided with an outer cutting track OCUT.
  • the compatible cutting area MA may not be limited to the first peripheral area B1 and the third peripheral area B3, but may also extend to the second peripheral area B2 or the fourth peripheral area B4.
  • the display panel PNL has at least one rounded corner; the outer cutting track OCUT is at least partially disposed at the rounded corner.
  • the area where at least one fillet is located can be part of the compatible cutting area MA.
  • the display panel PNL can select different cutting trajectories at the rounded corners and thus have different rounded corners.
  • the display panel PNL selects the outer cutting track OCUT as the cutting track at the rounded corner, at least one edge of the rounded corner of the display panel PNL partially coincides with the outer cutting track OCUT.
  • an identification mark MK is provided between the inner cutting track ICUT and the main cutting track MCUT (not shown in Figure 9) for alignment and effect evaluation during the preparation process of the display panel PNL.
  • the inorganic material layer BIL in the area where the identification mark MK is located needs to be retained.
  • This conflict is particularly prominent in the narrow-frame display panel PNL, which reduces the ability of the outer cutting track OCUT to suppress cracks.
  • the outer cutting lane OCUT generally reduces the inorganic material in the cutting lane by thinning or removing the inorganic material layer BIL.
  • the inner cutting lane ICUT generally reduces the inorganic material in the cutting lane by thinning or removing the inorganic material layer BIL.
  • the preset cutting trajectory line ICUL so that the film layers on both sides of the cutting trajectory ICUL have been reduced or removed from the inorganic material.
  • the area where part of the identification mark MK is located overlaps with the outer cutting track OCUT, and especially may overlap with the cutting trajectory line OCUL in the outer cutting track OCUT.
  • the outer cutting track OCUT can be disconnected (that is, the inorganic material layer BIL is not thinned or removed) to avoid the identification mark MK, thereby ensuring that the identification mark MK is clear and accurate.
  • the part passed by the cutting trajectory line OCUL does not necessarily thin or remove the inorganic material layer BIL.
  • cracks are prone to occur during cutting.
  • the width of the outer cutting track OCUT can be narrowed to avoid the identification mark MK, thereby ensuring that the identification mark MK is clear and accurate.
  • the outer cutting track OCUT is arranged adjacent to part of the identification mark MK, and the width of the portion of the outer cutting track OCUT close to the identification mark MK is smaller than the width of other parts of the outer cutting track OCUT.
  • the width of the outer cutting track OCUT is narrowed, making it prone to cracks during cutting. In particular, if these identification marks MK that narrow the outer cutting lane OCUT are disposed between the inner cutting lane ICUT and the outer cutting lane OCUT, it will be even less conducive to blocking the extension of cracks.
  • a second crack retaining wall DAM2 can be set between the outer cutting lane OCUT and the inner cutting lane ICUT to block the cracks generated during cutting of the outer cutting lane OCUT from extending to the display area AA. Compensate for the crack suppression ability of the outer cutting track OCUT.
  • the second crack retaining wall DAM2 may be disposed between the identification mark MK and the inner cutting channel ICUT. In this way, the cracks generated during cutting of the outer cutting channel OCUT need to break through the second crack retaining wall DAM2 before they can extend to the inner cutting channel ICUT, and then are further blocked by the inner cutting channel ICUT and the first crack retaining wall DAM1.
  • the motherboard structure of the present disclosure can compensate for the crack suppression ability of the outer cutting track OCUT and reduce the risk of cracks generated by the outer cutting track OCUT extending to within the first crack retaining wall DAM1; in this way, the motherboard structure can flexibly Preparing different display panels PNL can avoid the reduction in the yield of the display panel PNL.
  • the second crack retaining wall DAM2 may be provided only between each identification mark MK and the inner cutting lane ICUT, so that each outer cutting lane OCUT and each identification mark MK are located at the second crack retaining wall DAM2 is on the side away from ICUT. In this way, the second crack retaining wall DAM2 is provided between the outer cutting track OCUT and the inner cutting track ICUT closest to the display area AA.
  • a second crack retaining wall DAM2 can also be provided between two adjacent outer cutting lanes OCUT to achieve better effects.
  • the number of second crack retaining walls DAM2 may be multiple; a crack blocking groove DAMG is provided between two adjacent second crack retaining walls DAM2, the The crack stop trench DAMG is filled with organic material.
  • the inorganic material between the second crack retaining walls DAM2 is thinned or removed, and the organic material is spaced between two adjacent second crack retaining walls DAM2; when the crack extends to the crack blocking groove DAMG, the organic material can be effectively Absorb and disperse the stress at the crack tip, thereby preventing the crack from continuing to extend.
  • the material of the second crack retaining wall DAM2 can be an inorganic material.
  • the crack blocking trench DAMG between the second crack blocking walls DAM2 may be completely filled with organic material, or may be partially covered with new inorganic material and filled with organic material. Furthermore, the crack blocking groove DAMG can also be provided on the inside of the innermost second crack blocking wall DAM2 (the side close to the display area AA) and on the outside of the outermost second crack blocking wall DAM2 (the side away from the display area AA). side), so that any second crack blocking wall DAM2 is sandwiched between two adjacent crack blocking trenches DAMG.
  • the second crack barrier DAM2 can be prepared by patterning the inorganic material layer BIL, for example, by thinning or removing the layout area of the inorganic material layer BIL to form the crack barrier trench DAMG.
  • the second crack The other inorganic material layer BIL in the area where the retaining wall DAM2 is located forms the required second crack retaining wall DAM2. It can be understood that after the second crack retaining wall DAM2 is formed, the second crack retaining wall DAM2 and the crack blocking trench DAMG can also be covered with other inorganic layers, so that there are crack blocking trenches between the second crack retaining walls DAM2 DAMG shall prevail.
  • the number of the second crack retaining wall DAM2 is in the range of 2 to 8.
  • the depths of any two crack blocking trenches DAMG can be the same or different; the two crack blocking trenches DAMG can be prepared in the same patterning process or in different patterning processes.
  • the groove bottom of at least one crack blocking trench DAMG is located in the inorganic material layer BIL, for example, the groove bottom of at least one crack blocking trench DAMG Located in the inorganic buffer layer Buff or the inorganic barrier layer Barr.
  • a groove bottom of at least one crack blocking trench DAMG is located on the organic substrate BP.
  • the inorganic material layer BIL includes an inorganic barrier layer Barr, an inorganic buffer layer Buff, a gate insulating layer GI, and an interlayer dielectric layer sequentially stacked on one side of the organic substrate BP.
  • ILD inorganic barrier layer Barr
  • the inorganic buffer layer Buff the inorganic buffer layer Buff
  • a gate insulating layer GI the gate insulating layer GI
  • an interlayer dielectric layer sequentially stacked on one side of the organic substrate BP.
  • ILD the groove bottom of the crack blocking trench DAMG is located on the inorganic buffer layer Buff, the inorganic barrier layer Barr or the organic substrate BP.
  • the crack barrier trench DAMG can be obtained by etching the inorganic material layer BIL, and the etching process of the crack barrier trench DAMG can be adjusted according to the process requirements of the display panel PNL.
  • the display panel PNL has a bending area in the first peripheral area B1.
  • the part of the inorganic material layer BIL in the bending area needs to be etched to improve the bending ability of the bending area.
  • the inorganic material layer BIL in the bending area can be etched using two etching processes, one etching process, or three or more etching processes.
  • the inorganic material layer BIL located outside the inner cutting track ICUT can also be etched at the same time to form the required crack blocking trench DAMG.
  • the formation of the crack blocking trench DAMG may also be asynchronous with the etching of the bending area.
  • the display panel PNL uses two etching processes in the bending area, that is, the first etching (EBI, edge bending step A+ILD etch) process and the second etching (EBB, edge bending step B) Craftsmanship.
  • the EBI process the interlayer dielectric layer ILD and the film layer below the interlayer dielectric layer ILD (the side of the interlayer dielectric layer ILD close to the organic substrate BP) can be patterned to form openings to expose the semiconductor layer; at the same time , perform preliminary etching on the bending area.
  • the EBI process can also be used to form crack blocking trenches DAMG, and these crack blocking trenches DAMG can be defined as first crack blocking trenches DAMG1.
  • the bending area is further etched to further thin or remove the inorganic material layer BIL in the bending area. In this way, the display panel PNL can be bent in the bending area, thereby reducing the frame of the display device.
  • the EBB process can also be used to form crack blocking trenches DAMG, and these crack blocking trenches DAMG can be defined as second crack blocking trenches DAMG2.
  • the EBI process can be used for preliminary etching, and then the EBB process can be used for further etching. Then the formed crack blocking trenches DAMG can be It is defined as the third crack blocking trench DAMG3 (see Figure 13).
  • the depth of the first crack blocking trench DAMG1 is smaller than the depth of the second crack blocking trench DAMG2, but the bottoms of both grooves are located in the inorganic buffer layer Buff, or the first The groove bottom of the crack blocking trench DAMG1 is located on the inorganic buffer layer Buff and the groove bottom of the second crack blocking trench DAMG2 is located on the inorganic barrier layer Barr.
  • the groove bottoms of the first crack blocking trench DAMG1 and the second crack blocking trench DAMG2 may also pass through the inorganic buffer layer Buff and extend into the inorganic barrier layer Barr.
  • the depth of the third crack blocking trench DAMG3 may be greater than the first crack blocking trench DAMG1 and the second crack blocking trench DAMG2.
  • the third crack blocking trench DAMG3 penetrates the inorganic material layer BIL along the normal direction of the display panel PNL and is located on the organic substrate BP.
  • each crack barrier trench DAMG may be the same or different, that is, the depths of any two crack barrier trenches DAMG may be the same or different.
  • each crack blocking trench DAMG is the first crack blocking trench DAMG1 , that is, each crack blocking trench DAMG is prepared in the EBI process.
  • each crack blocking trench DAMG is a second crack blocking trench DAMG2, that is, each crack blocking trench DAMG is prepared in an EBB process.
  • each crack blocking trench DAMG is the third crack blocking trench DAMG3, that is, each crack blocking trench DAMG is prepared using the EBI process + the peripheral area BBB process.
  • At least part of the crack blocking trench DAMG is the first crack blocking trench DAMG1, and at least part of the crack blocking trench DAMG is the second crack blocking trench DAMG2, that is, two crack blocking trenches
  • the depths of the slots DAMG can be the same or different.
  • the first crack blocking trench DAMG1 and the second crack blocking trench DAMG2 are arranged in sequence.
  • the combination of the crack blocking grooves DAMG in the above example is only an example of the present disclosure.
  • the crack blocking grooves DAMG in the display panel PNL of the present disclosure can also be presented in other combinations, and the disclosure is not limited to this.
  • the width of the second crack barrier DAM2 is in the range of 5 to 15 microns.
  • the width of the second crack retaining wall DAM2 may also be wider or narrower.
  • the width of the crack blocking trench DAMG is in the range of 5 to 10 microns.
  • the width of the crack blocking groove DAMG can also be wider or narrower.
  • the ratio of the width of the second crack blocking wall DAM2 to the width of the crack blocking groove DAMG is between 0.8 and 1.2.
  • the ratio of the width of the second crack blocking wall DAM2 to the width of the crack blocking groove DAMG is 1:1.
  • An embodiment of the present disclosure also provides a display device, which includes any of the display panels described in the above display panel embodiments.
  • the display device may be a smartphone screen, a smart watch screen, or other types of display devices. Since the display device has any of the display panels described in the above display panel embodiments, it has the same beneficial effects and will not be described in detail here.
  • Other embodiments of the disclosure will be readily apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure that follow the general principles of the disclosure and include common knowledge or customary technical means in the technical field that are not disclosed in the disclosure. . It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

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Abstract

一种显示面板（PNL）和母板结构、显示装置。显示面板（PNL）具有显示区（AA）和围绕显示区（AA）的外围区（BB）；外围区（BB）具有环绕显示区（AA）的内切割道（ICUT）。母板结构包括多个显示面板（PNL）；在显示面板（PNL）之间，母板结构具有主切割道（MCUT）。在主切割道（MCUT）与显示面板（PNL）的内切割道（ICUT）之间，在至少部分区域设置有外切割道（OCUT）；外切割道（OCUT）的端部与内切割道（ICUT）交汇；外切割道（OCUT）与内切割道（ICUT）之间设置有第二裂纹挡墙（DAM2）。

Description

显示面板和母板结构、显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示面板和母板结构、显示装置。
背景技术
随着显示技术的发展，人们对显示装置的外形的个性化需求越来越多。显示面板在设计时，可以在母板结构的局部位置设置多道切割道，以便通过切割道的选择来制备不同形状的显示面板。然而，从具有多道切割道的母板结构上制备的显示面板，容易出现边缘裂纹不良。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于克服上述现有技术的不足，提供一种显示面板及母板结构、显示装置，降低边缘裂纹不良。
根据本公开的一个方面，提供一种显示面板，包括显示区和围绕所述显示区的外围区；所述外围区具有环绕所述显示区的内切割道以及位于所述内切割道靠近所述显示区一侧的第一裂纹挡墙。
根据本公开的一种实施方式，在所述外围区的至少部分区域，所述显示面板还具有位于所述内切割道远离所述显示区一侧的外切割道；所述外切割道的端部与所述内切割道交汇。
根据本公开的一种实施方式，所述内切割道远离所述显示区的一侧设置有识别标记；至少部分所述识别标记的至少部分设置于所述外切割道内。
根据本公开的一种实施方式，所述第二裂纹挡墙设置于所述识别标记与所述内切割道之间。
根据本公开的一种实施方式，所述内切割道远离所述显示区的一侧设置有识别标记；至少部分所述识别标记位于所述外切割道与所述内切割道 之间，且所述外切割道靠近所述识别标记的部分的宽度小于所述外切割道的其他部分的宽度；
所述第二裂纹挡墙设置于所述识别标记与所述内切割道之间。
根据本公开的一种实施方式，所述第二裂纹挡墙的数量为多个；相邻两个所述第二裂纹挡墙之间设置有裂纹阻挡沟槽，所述裂纹阻挡沟槽填充有有机材料。
根据本公开的一种实施方式，在所述第二裂纹挡墙所在的区域，所述显示面板包括依次层叠设置的有机衬底基板、无机材料层和有机材料层；
至少一个所述裂纹阻挡沟槽的槽底位于所述无机材料层。
根据本公开的一种实施方式，在所述第二裂纹挡墙所在的区域，所述显示面板包括依次层叠设置的有机衬底基板、无机材料层和有机材料层；
至少一个所述裂纹阻挡沟槽的槽底位于所述有机衬底基板。
根据本公开的一种实施方式，所述无机材料层包括依次层叠于所述有机衬底基板一侧的无机阻挡层、无机缓冲层、栅极绝缘层、层间电介质层；
所述裂纹阻挡沟槽的槽底位于所述无机缓冲层、所述无机阻挡层或者所述有机衬底基板。
根据本公开的一种实施方式，所述第二裂纹挡墙的数量在2～8范围内。
根据本公开的一种实施方式，所述第二裂纹挡墙的宽度在5～15微米范围内。
根据本公开的一种实施方式，所述裂纹阻挡沟槽的宽度在5～10微米范围内。
根据本公开的一种实施方式，所述第二裂纹挡墙的宽度与所述裂纹阻挡沟槽的宽度的比值，在0.8～1.2之间。
根据本公开的一种实施方式，所述外围区包括环绕所述显示区且依次首尾连接的第一外围区、第二外围区、第三外围区和第四外围区；所述第一外围区和所述第三外围区相对设置；所述第一外围区中具有用于绑定外部电路的绑定焊盘；
所述外切割道设置于所述第一外围区和/或所述第三外围区。
根据本公开的一种实施方式，所述显示面板具有圆角；至少一个所述圆角的边缘与所述外切割道部分重合。
根据本公开的一种实施方式，在至少部分区域，所述外切割道的数量为多条且沿远离所述显示区的方向依次排列；
最靠近所述显示区的外切割道与所述内切割道之间设置有所述第二裂纹挡墙。
根据本公开的一种实施方式，所述显示面板在所述外围区设置有裂纹检测走线；所述裂纹检测走线设置于所述第一裂纹挡墙和所述显示区之间。
根据本公开的另一个方面，提供一种母板结构，其中，所述母板结构包括上述的显示面板；在所述显示面板之间，所述母板结构具有主切割道；
在所述主切割道与所述显示面板的内切割道之间，在至少部分区域设置有外切割道；所述外切割道的端部与所述内切割道交汇；所述外切割道与所述内切割道之间设置有第二裂纹挡墙。
根据本公开的另一个方面，提供一种显示装置，包括上述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一种实施方式中，母板结构的结构示意图。
图2为本公开一种实施方式中，显示面板的膜层结构示意图。
图3为本公开一种实施方式中，显示面板的结构示意图。
图4为本公开一种实施方式中，显示面板在内切割道内的部分的结构示意图。
图5为本公开一种实施方式中，子板结构的结构示意图。
图6为本公开一种实施方式中，子板结构的切割轨迹的结构示意图。
图7为本公开一种实施方式中，子板结构的切割轨迹的结构示意 图。
图8为本公开一种实施方式中，子板结构的切割轨迹的结构示意图。
图9为本公开一种实施方式中，子板结构在兼容切割区的局部结构示意图。
图10为本公开一种实施方式中，显示面板在临近边缘处的膜层结构示意图。
图11为本公开一种实施方式中，第一裂纹阻挡沟槽被有机材料层填充的结构示意图。
图12为本公开一种实施方式中，第二裂纹阻挡沟槽被有机材料层填充的结构示意图。
图13为本公开一种实施方式中，第三裂纹阻挡沟槽被有机材料层填充的结构示意图。
图14为本公开一种实施方式中，各个裂纹阻挡沟槽均为第一裂纹阻挡沟槽的结构示意图。
图15为本公开一种实施方式中，各个裂纹阻挡沟槽均为第二裂纹阻挡沟槽的结构示意图。
图16为本公开一种实施方式中，各个裂纹阻挡沟槽均为第三裂纹阻挡沟槽的结构示意图。
图17为本公开一种实施方式中，裂纹阻挡沟槽均为第一裂纹阻挡沟槽和第二裂纹阻挡沟槽的结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个 或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
参见图1，本公开提供一种母板结构以及从母板结构上切割出的显示面板PNL，该显示面板PNL可以作为显示面板或者作为显示模组的一部分以用于显示。
参见图2，显示面板可以包括依次层叠设置的有机衬底基板BP、驱动电路层F200和像素层F300。
在本公开的一些实施方式中，有机衬底基板BP的材料可以为聚酰亚胺(Polyimide，PI)、聚甲基丙烯酸甲酯(Polymethyl methacrylate，PMMA)、聚乙烯醇(Polyvinyl alcohol，PVA)、聚乙烯基苯酚(Polyvinyl phenol，PVP)、聚醚砜(Polyether sulfone，PES)、聚酰亚胺、聚酰胺、聚缩醛、聚碳酸酯(Poly carbonate，PC)、聚对苯二甲酸乙二酯(Polyethylene terephthalate，PET)、聚萘二甲酸乙二酯(Polyethylene naphthalate，PEN)或其组合。在一种示例中，有机衬底基板BP可以为柔性衬底基板BP，其材料可以为聚酰亚胺。
在另外一些实施方式中，有机衬底基板BP还可以为多层材料的复合。举例而言，有机衬底基板BP可以包括依次层叠设置的底膜层(Bottom Film)、压敏胶层、第一聚酰亚胺层和第二聚酰亚胺层。
驱动电路层F200设置有用于驱动子像素的像素驱动电路。在驱动电路层F200中，任意一个像素驱动电路可以包括有晶体管F200M和存储电容。进一步地，晶体管F200M可以为薄膜晶体管，薄膜晶体管可以选自顶栅型薄膜晶体管、底栅型薄膜晶体管或者双栅型薄膜晶体管；薄膜晶体管的有源层的材料可以为非晶硅半导体材料、低温多晶硅半导体材料、金属氧化物半导体材料、有机半导体材料或者其他类型的半导体材料；薄膜晶体管可以为N型薄膜晶体管或者P型薄膜晶体管。
可以理解的是，像素驱动电路中的各个晶体管中，任意两个晶体管之间的类型可以相同或者不相同。示例性地，在一种实施方式中，在一个像素驱动电路中，部分晶体管可以为N型晶体管且部分晶体管可以为P型晶体管。再示例性地，在本公开的另一种实施方式中，在一个像素驱动电路 中，部分晶体管的有源层的材料可以为低温多晶硅半导体材料，且部分晶体管的有源层的材料可以为金属氧化物半导体材料。在本公开的一些实施方式中，薄膜晶体管为低温多晶硅晶体管。在本公开的另外一些实施方式中，部分薄膜晶体管为低温多晶硅晶体管，部分薄膜晶体管为金属氧化物晶体管。
可选地，驱动电路层F200可以包括层叠于有机衬底基板BP和像素层F300之间的半导体层SEMI、栅极绝缘层GI、栅极层GT、层间电介质层ILD和源漏金属层SD等。各个薄膜晶体管和存储电容可以由半导体层SEMI、栅极绝缘层GI、栅极层GT、层间电介质层ILD、源漏金属层SD等膜层形成。其中，各个膜层的位置关系可以根据薄膜晶体管的膜层结构确定。进一步地，半导体层SEMI可以用于形成晶体管的沟道区；栅极层可以用于形成扫描引线、复位控制引线、发光控制引线等栅极层走线，也可以用于形成晶体管的栅极，还可以用于形成存储电容的部分或者全部电极板；源漏金属层可以用于形成数据引线、驱动电源引线等源漏金属层走线，也可以用于形成存储电容的部分电极板。
举例而言，在本公开的一些实施方式中，驱动电路层F200可以包括依次层叠设置的半导体层SEMI、栅极绝缘层GI、栅极层GT、层间电介质层ILD和源漏金属层SD，如此所形成的薄膜晶体管为顶栅型薄膜晶体管。
再举例而言，在本公开的一些实施方式中，驱动电路层F200可以包括依次层叠设置的栅极层GT、栅极绝缘层GI、半导体层SEMI、层间电介质层ILD和源漏金属层SD，如此所形成的薄膜晶体管为底栅型薄膜晶体管。
在一些实施方式中，栅极层可以为两层或者三层。举例而言，在本公开的一种实施方式中，栅极层GT可以包括第一栅极层和第二栅极层，栅极绝缘层GI可以包括用于隔离半导体层SEMI和第一栅极层的第一栅极绝缘层，以及包括用于隔离第一栅极层和第二栅极层的第二栅极绝缘层。示例性地，驱动电路层F200可以包括依次层叠设置于有机衬底基板BP一侧的半导体层SEMI、第一栅极绝缘层、第一栅极层、第二栅极绝缘层、第二栅极层、层间电介质层ILD和源漏金属层SD。再举例而言，在本公 开的一种实施方式中，栅极层GT可以包括第一栅极层和第二栅极层，半导体层SEMI可以夹设于第一栅极层和第二栅极层之间；栅极绝缘层GI可以包括用于隔离半导体层SEMI和第一栅极层的第一栅极绝缘层，以及包括用于隔离第二栅极层和半导体层SEMI的第二栅极绝缘层。示例性地，在本公开的一种实施方式中，驱动电路层F200可以包括依次层叠设置于有机衬底基板BP一侧的第一栅极层、第一栅极绝缘层、半导体层SEMI、第二栅极绝缘层、第二栅极层、层间电介质层ILD和源漏金属层SD。这样，可以形成具有双栅结构的晶体管。再举例而言，在本公开的一种实施方式中，半导体层SEMI可以包括低温多晶硅半导体层和金属氧化物半导体层；栅极层包括第一栅极层和第二栅极层，栅极绝缘层包括第一和第二栅极绝缘层。驱动电路层F200可以包括依次层叠设置于有机衬底基板BP一侧的低温多晶硅半导体层、第一栅极绝缘层、第一栅极层、金属氧化物半导体层、第二栅极绝缘层、第二栅极层、层间电介质层ILD和源漏金属层SD。再举例而言，在本公开的一种实施方式中，半导体层SEMI可以包括低温多晶硅半导体层和金属氧化物半导体层；栅极层包括第一至第三栅极层，栅极绝缘层包括第一至第三栅极绝缘层。驱动电路层F200可以包括依次层叠设置于有机衬底基板BP一侧的低温多晶硅半导体层、第一栅极绝缘层、第一栅极层、绝缘缓冲层、第二栅极层、第二栅极绝缘层、金属氧化物半导体层、第三栅极绝缘层、第三栅极层、层间电介质层ILD和源漏金属层SD。
在一些实施方式中，源漏金属层可以为两层或者三层。举例而言，在本公开的一种实施方式中，源漏金属层可以包括依次层叠于层间电介质层ILD远离衬底基板一侧的第一源漏金属层和第二源漏金属层，第一源漏金属层和第二源漏金属层之间可以夹设于绝缘层，例如夹设有钝化层和/或平坦化层。再举例而言，在本公开的一种实施方式中，源漏金属层可以包括依次层叠于层间电介质层ILD远离衬底基板一侧的第一源漏金属层、第二源漏金属层、第三源漏金属层；第一源漏金属层和第二源漏金属层之间可以夹设于绝缘层，例如夹设有钝化层和/或树脂层；第二源漏金属层和第三源漏金属层之间可以夹设于绝缘层，例如夹设有钝化层和/或平坦化层。
可选地，驱动电路层F200还可以包括有钝化层，钝化层可以设于源 漏金属层SD远离有机衬底基板BP的表面，以便保护源漏金属层SD。
可选地，驱动电路层F200还可以包括设于有机衬底基板BP与半导体层SEMI之间的无机缓冲层Buff，且半导体层SEMI、栅极层GT等均位于无机缓冲层Buff远离有机衬底基板BP的一侧。无机缓冲层Buff的材料可以为氧化硅、氮化硅等无机绝缘材料。缓冲材料层可以为一层无机材料，也可以为多层层叠的无机材料。
可选地，驱动电路层F200还可以包括设于有机衬底基板BP与无机缓冲层Buff之间的无机阻挡层Barr，阻挡层可以屏蔽有机衬底基板BP，避免有机衬底基板BP中的组分向半导体层SEMI渗透而影响像素驱动电路的稳定性。
可选地，驱动电路层F200还可以包括位于源漏金属层SD和像素层F300之间的平坦化层PLN，平坦化层PLN可以为像素电极提供平坦化表面。可选地，平坦化层PLN的材料可以为有机材料。
参见图10，在临近显示面板PNL的边缘处，各层无机材料可以组成显示面板PNL的无机材料层BIL。在一种示例中，在临近显示面板PNL的边缘处，显示面板PNL的无机材料层BIL可以包括依次层叠于有机衬底基板BP的无机阻挡层Barr、无机缓冲层Buff、栅极绝缘层GI、层间电介质层ILD等。在另外一些示例中，无机材料层BIL还可以包括钝化层PVX。可以理解的是，在图10所示的显示面板PNL中，栅极绝缘层GI包括第一栅极绝缘层GI1和第二栅极绝缘层GI2等两层。在本公开的其他实施方式中，栅极绝缘层GI可以为一层，也可以为三层或者更多层。
在一种示例中，无机阻挡层Barr的厚度可以在450～650纳米范围内，例如可以为550纳米。
在一种示例中，无机缓冲层Buff的厚度可以在300～500纳米范围内，例如可以为400纳米。
在一种示例中，第一栅极绝缘层GI1的厚度可以在100～150纳米范围内，例如可以为120纳米。
在一种示例中，第二栅极绝缘层GI2的厚度可以在100～150纳米范围内，例如可以为130纳米。
在一种示例中，层间电介质层ILD的厚度可以在400～600纳米范围内， 例如可以为500纳米。
在一种示例中，钝化层PVX的厚度可以在100～200纳米范围内，例如可以为150纳米。
像素层F300可以设置有子像素。在一些实施方式中，例如在液晶显示面板中，像素电极、公共电极和液晶层可以形成控制光线偏振方向的光开关，该光开关可以作为本公开的子像素。在另外一些实施方式中，像素层可以设置有与像素驱动电路对应电连接的发光元件，发光元件可以作为显示面板的子像素。
示例性地，像素层设置有阵列分布的发光元件，且各个发光元件在像素驱动电路的控制下发光。在本公开中，发光元件可以为有机电致发光二极管(OLED)、微发光二极管(Micro LED)、量子点-有机电致发光二极管(QD-OLED)、量子点发光二极管(QLED)或者其他类型的发光元件。示例性地，在本公开的一种实施方式中，发光元件为有机电致发光二极管(OLED)，则该显示面板为OLED显示面板。如下，以发光元件为有机电致发光二极管为例，对像素层的一种可行结构进行示例性的介绍。
可选地，像素层F300可以设置于驱动电路层F200远离有机衬底基板BP的一侧，其可以包括依次层叠设置的像素电极层F301、像素定义层F302、支撑柱层F303、有机发光功能层F304和公共电极层F305。其中，像素电极层F301在显示面板的显示区具有多个像素电极；像素定义层F302在显示区具有与多个像素电极一一对应设置的多个贯通的像素开口，任意一个像素开口暴露对应的像素电极的至少部分区域。支撑柱层F303在显示区包括多个支撑柱，且支撑柱位于像素定义层F302远离有机衬底基板BP的表面，以便在蒸镀制程中支撑精细金属掩模版(Fine Metal MAsk，FMM)。有机发光功能层F304至少覆盖被像素定义层F302所暴露的像素电极。其中，有机发光功能层F304可以包括有机电致发光材料层，以及可以包括有空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一种或者多种。可以通过蒸镀工艺制备有机发光功能层F304的各个膜层，且在蒸镀时可以采用精细金属掩模版或者开放式掩膜板(Open MAsk)定义各个膜层的图案。公共电极层F305在显示区可以覆盖有机发光功能层F304。如此，像素电极、公共电极层F305和位于像素 电极和公共电极层F305之间的有机发光功能层F304形成有机发电致光二极管F300D，任意一个有机电致发光二极管可以作为显示面板的一个子像素。
在一些实施方式中，像素层F300还可以包括位于公共电极层F305远离有机衬底基板BP一侧的光取出层，以增强有机发光二极管的出光效率。
在一种示例中，有机材料层BOL可以包括平坦化层、像素定义层等膜层。可以理解的是，在本公开的母板结构和显示面板PNL中，根据显示面板PNL的类型和工艺的不同，无机材料层BIL可以为其他不同无机层的组合，有机材料层BOL可以为其他有机层或者其他有机层的组合。
可选地，显示面板还可以包括薄膜封装层F400。薄膜封装层F400设于像素层F300远离有机衬底基板BP的表面，可以包括交替层叠设置的无机封装层和有机封装层。其中，无机封装层可以有效的阻隔外界的水分和氧气，避免水氧入侵有机发光功能层F304而导致材料降解。可选地，无机封装层的边缘可以位于外围区。有机封装层位于相邻的两层无机封装层之间，以便实现平坦化和减弱无机封装层之间的应力。其中，有机封装层的边缘，可以位于显示区的边缘和无机封装层的边缘之间。示例性地，薄膜封装层F400包括依次层叠于像素层F300远离有机衬底基板BP一侧的第一无机封装层F401、有机封装层F402和第二无机封装层F403。
可选地，显示面板还可以包括触控功能层F500，触控功能层F500设于薄膜封装层F400远离有机衬底基板BP的一侧，用于实现显示面板的触控操作。
可选地，显示面板还可以包括降反层F600，降反层F600可以设置于薄膜封装层F400远离像素层F300的一侧，用于降低显示面板对环境光线的反射，进而降低环境光线对显示效果的影响。在本公开的一种实施方式中，降反层F600可以包括层叠设置的彩膜层和黑矩阵层，如此可以在实现降低环境光线干扰的同时，可以避免降低显示面板的透光率。在本公开的另一种实施方式中，降反层F600可以为偏光片，例如可以为图案化的涂布型圆偏光片。进一步地，降反层F600可以设置于触控功能层F500远离有机衬底基板BP的一侧。
图1示出了母板结构的平面示意图。参见图1，母板结构具有多个显 示面板PNL，例如具有阵列分布的显示面板PNL。在显示面板PNL之间，母板结构上设置有主切割道MCUT。在通过切割制备显示面板PNL时，可以先沿主切割道MCUT切割，将母板结构切割成多个子板结构MM，每个子板结构MM均包括一个显示面板PNL。这样，主切割道MCUT定义出了子板结构MM的边缘。然后，再对子板结构MM做进一步的切割，以获得所需的显示面板PNL。
图3示出了显示面板PNL的一种平面结构示意图；图4示出了显示面板PNL在内切割道ICUT以内的平面结构示意图；图5示出了子板结构MM的平面结构示意图；图6～图8示出了基于图5的子板结构MM而能够获得的显示面板PNL的结构示意图。参见图3，显示面板PNL包括显示区AA和围绕显示区AA的外围区BB。参见图4～图8，在显示面板PNL的边缘EE或者临近边缘EE的区域，显示面板PNL具有环绕显示区AA的内切割道ICUT。参见图5，子板结构MM中，在内切割道ICUT至主切割道MCUT之间的区域(包括内切割道ICUT)至少部分为兼容切割区MA，兼容切割区MA内设置有外切割道OCUT。换言之，内切割道ICUT至主切割道MCUT之间的至少部分区域设置有外切割道OCUT，这些设置有外切割道OCUT的区域为兼容切割区MA。其中，在无特别指出的情况下，内切割道ICUT和外切割道OCUT中的无机材料被去除或者被减薄，以降低在切割时产生裂纹的风险并降低裂纹的大小，提供显示面板的良率和信赖性。
参见图5(仅仅示意了一个兼容切割区MA)，在任意一个兼容切割区MA内，外切割道OCUT一端与内切割道ICUT交汇，另一端与内切割道ICUT交汇或者与主切割道MCUT交汇。这样，在切割子板结构MM以获得显示面板PNL时，在兼容切割区MA以外可以沿着内切割道ICUT切割；即，在兼容切割区MA以外，切割轨迹在内切割道ICUT内。在兼容切割区MA，可以沿着内切割道ICUT或者外切割道OCUT切割；即，在兼容切割区MA，切割轨迹可以在内切割道ICUT内或者外切割道OCUT内。在切割子板结构MM时所选择的切割道，最终定义了显示面板PNL的边缘EE；显示面板PNL的边缘EE与主切割道MCUT之间为待切除区域。在本公开中，由于母板结构在兼容切割区MA设置有外切割道OCUT， 这使得可以通过选择不同的切割道组合出不同的切割轨迹以获得不同的显示面板PNL，进而达到了通过同一母板结构制备不同的显示面板PNL的目的，提高了母板结构的通用性，降低了显示面板PNL的成本并能够满足不同显示产品对显示面板PNL的个性化需求。在本公开的一种实施方式中，可以根据外切割道OCUT与内切割道ICUT交汇节点来定义兼容切割区MA的起始节点和终止节点。
在图5中示出了子板结构MM具有一个兼容切割区MA，且该兼容切割区MA内具有第一外切割道OCUT1、第二外切割道OCUT2和第三外切割道OCUT3等三种外切割道OCUT的例子。可以理解的是，在本公开的其他实施方式中，子板结构MM可以具有多个兼容切割区MA，兼容切割区MA内可以具有更多或者更少的外切割道OCUT。以图5所示的子板结构MM为例，第一外切割道OCUT1的数量为两条，第一外切割道OCUT1靠近内切割道ICUT的一端与内切割道ICUT交汇；第二外切割道OCUT2位于两个第一外切割道OCUT1之间，且两端分别与两个第一外切割道OCUT1远离内切割道ICUT的端部交汇；第三外切割道OCUT3的数量为两个且与两条第一外切割道OCUT1一一对应，第三外切割道OCUT3的一端与主切割道MCUT交汇，另一端与对应的第一外切割道OCUT1远离显示区AA的端部交汇。在切割子板结构MM时，在兼容切割区MA以外的切割轨迹可以沿内切割道ICUT设置。在上述示例的兼容切割区MA中，可以有如下三种可选择的不同的切割轨迹，即选择内切割道ICUT作为切割轨迹、选择第一外切割道OCUT1-第二外切割道OCUT2-第一外切割道OCUT1作为切割轨迹、选择第一外切割道OCUT1-第三外切割道OCUT3-第三外切割道OCUT3-第一外切割道OCUT1作为切割轨迹。参见图6，在一种示例中，在兼容切割区MA选择内切割道ICUT作为切割轨迹；图6中用粗线EE表示出了切割轨迹，该粗线EE还表示所切割出的显示面板PNL的边缘；显示面板PNL的整体形状和范围通过点阵填充进行示意。参见图7，在另一种示例中，在兼容切割区MA选择第一外切割道OCUT1-第二外切割道OCUT2-第一外切割道OCUT1作为切割轨迹；图7中用粗线EE表示出了切割轨迹，该粗线EE还表示所切割出的显示面板PNL的边缘；显示面板PNL的整体形状和范围通过点阵填充进行示 意。参见图8，在另一种示例中，在兼容切割区MA选择第一外切割道OCUT1-第三外切割道OCUT3-第三外切割道OCUT3-第一外切割道OCUT1作为切割轨迹；图8中用粗线EE表示出了切割轨迹，该粗线EE还表示所切割出的显示面板PNL的至少部分边缘；显示面板PNL的整体形状和范围通过点阵填充进行示意。由此可知，在兼容切割区MA通过选择不同的切割道组成不同的切割轨迹，进而可以切割出不同的显示面板PNL；实际切割的轨迹定义了显示面板PNL的边缘。
在本公开的一种实施方式中，在全部选择内切割道ICUT作为切割轨迹时，所获得的显示面板PNL可以不具有兼容切割区MA，即各个内切割道ICUT以外的部分(包括各个外切割道OCUT)可以被切割出去。这样，本公开的母板结构可以具有阵列分布的显示面板PNL，显示面板PNL的边缘由内切割道ICUT定义；显示面板PNL以外可以设置有外切割道OCUT以提高母板结构的通用性，但是这些外切割道OCUT等均在切割以形成显示面板PNL时被切除。
在本公开的另一种实施方式中，在某一个兼容切割区MA内选择外切割道OCUT作为切割轨迹时，则该显示面板PNL保留该兼容切割区MA的至少部分。
图10示出了显示面板PNL在临近边缘的区域的膜层结构示意图。参见图10，在靠近边缘的区域，显示面板PNL包括依次层叠设置的有机衬底基板BP、无机材料层BIL和有机材料层BOL。在内切割道ICUT，无机材料层BIL可以被减薄或者被去除以形成环形的切割槽，且切割槽内被有机材料层BOL填充。这样，内切割道ICUT具有较少或者不具有无机材料，这在切割时和在切割后，均可以减少裂纹的产生。在一种示例中，可以完全去除内切割道ICUT中的无机材料。
在本公开的一些实施方式中，参见图3和图4，在外围区BB，在内切割道ICUT的内侧(即内切割道ICUT靠近显示区AA的一侧)设置有第一裂纹挡墙DAM1。这样，当沿内切割道ICUT进行切割时，第一裂纹挡墙DAM1可以阻挡切割时的裂纹由显示面板PNL的边缘向显示区AA扩散，达成保护显示面板PNL的目的。
可选的，参见图9，第一裂纹挡墙DAM1包括多条且由无机材料层 BIL组成，相邻两条第一裂纹挡墙DAM1之间设置有沟槽，沟槽内填充有有机材料层BOL。换言之，在第一裂纹挡墙DAM1所在区域，可以通过对无机材料层BIL进行减薄或者去除以形成沟槽，无机材料层BIL剩余的部分可以作为第一裂纹挡墙DAM1。裂纹向显示区AA延伸的过程中，可以被第一裂纹挡墙DAM1所阻挡。当然的，依据制备工艺的不同，第一裂纹挡墙DAM1之间的沟槽内也可以再覆盖无机材料，例如覆盖钝化层，以无机材料不填充满沟槽为准。
参见图4，在本公开的一种实施方式中，在显示区AA与第一裂纹挡墙DAM1之间，显示面板PNL还设置有裂纹检测走线PCD，以用于检测显示面板PNL边缘的裂纹。如果裂纹穿过第一裂纹挡墙DAM1而延伸至裂纹检测走线PCD附近，可以使得裂纹检测走线PCD断线或者电阻等特性改变。如此，可以通过监测裂纹检测走线PCD的状态来监测显示面板PNL边缘的裂纹。可选的，裂纹检测走线PCD的数量为多个，以提高对裂纹监测的灵敏度和准确性。
参见图3，在本公开的一些实施方式中，所述外围区BB包括环绕所述显示区AA且依次首尾连接的第一外围区B1、第二外围区B2、第三外围区B3和第四外围区B4；所述第一外围区B1和所述第三外围区B3相对设置；所述第一外围区B1中具有用于绑定外部电路的绑定焊盘。所述外切割道OCUT设置于所述第一外围区B1和/或所述第三外围区B3。在本公开中，可以将靠近第一外围区B1的一端定义为显示面板PNL或者子板结构MM的近端，将靠近第三外围区B3的一端定义为显示面板PNL或者子板结构MM的远端。在该实施方式中，外切割道OCUT可以设置于子板结构MM的近端区域或者远端区域，亦或同时设置在近端区域或者远端区域。
作为一种示例，第一外围区B1的局部或者整体为兼容切割区MA的一部分，兼容切割区MA内设置有外切割道OCUT。作为另一种示例，第三外围区B3的局部或者整体为兼容切割区MA的一部分，兼容切割区MA内设置有外切割道OCUT。作为再一种示例，第一外围区B1的局部或者整体为兼容切割区MA的一部分，兼容切割区MA内设置有外切割道OCUT；且第三外围区B3的局部或者整体为兼容切割区MA的一部分， 兼容切割区MA内设置有外切割道OCUT。
可选的，兼容切割区MA可以不局限于第一外围区B1和第三外围区B3，也可以向第二外围区B2或者第四外围区B4延伸。
举例而言，参见图5，所述显示面板PNL具有至少一个圆角；所述外切割道OCUT至少部分设置于所述圆角处。换言之，至少一个圆角所在的区域，可以为兼容切割区MA的一部分。这样，显示面板PNL可以在圆角处选择不同的切割轨迹，进而具有不同的圆角。当显示面板PNL在圆角处选择外切割道OCUT作为切割轨迹时，显示面板PNL的至少一个所述圆角的边缘与所述外切割道OCUT部分重合。
参见图9，在子板结构MM上，内切割道ICUT与主切割道MCUT(图9中未示出)之间设置有识别标记MK，以便在显示面板PNL制备过程中进行对位和效果评估，例如用于曝光机进行对位和对曝光效果进行检测。为了保证能够准确识别识别标记MK，识别标记MK所在区域的无机材料层BIL需要被保留。然而，识别标记MK所在区域与外切割道OCUT所在区域之间经常存在冲突，该冲突在窄边框的显示面板PNL中尤为突出，这降低了外切割道OCUT对裂纹的抑制能力。
参见图9，外切割道OCUT一般通过对无机材料层BIL进行减薄或者去除以减少该切割道内的无机材料。在切割时，一般需要沿着预设的切割轨迹线OCUL进行切割，以使得切割轨迹线OCUL两侧的膜层均已经减少或者去除了无机材料。相应的，内切割道ICUT一般通过对无机材料层BIL进行减薄或者去除以减少该切割道内的无机材料。在切割时，一般需要沿着预设的切割轨迹线ICUL进行切割，以使得切割轨迹线ICUL两侧的膜层均已经减少或者去除了无机材料。
在一些情况下，参见图9，部分识别标记MK所在的区域与外切割道OCUT存在重叠部分，尤其是可能会与外切割道OCUT中的切割轨迹线OCUL交叠。此时，可以使得外切割道OCUT断开(即不对无机材料层BIL进行减薄或者去除)以避让识别标记MK，进而确保识别标记MK的清晰准确。这样，切割轨迹线OCUL所经过的部分并不必然对无机材料层BIL进行了减薄或者去除。在切割轨迹线OCUL与识别标记MK交叠的部分，在切割时容易出现裂纹。
在另外一些情况下，参见图9，部分识别标记MK所在的区域与外切割道OCUT所在的区域存在一定的交叠。此时可以收窄外切割道OCUT的宽度以避让识别标记MK，进而确保识别标记MK的清晰准确。换言之，外切割道OCUT与部分识别标记MK相邻设置，且外切割道OCUT靠近识别标记MK的部分的宽度，小于外切割道OCUT其他部分的宽度。然而，外切割道OCUT的宽度收窄，使得其在切割时容易产生裂纹。尤其是，这些使得外切割道OCUT收窄的识别标记MK如果设置在内切割道ICUT与外切割道OCUT之间，则更不利于阻挡裂纹的延伸。
在本公开的母板结构中，参见图9，可以在外切割道OCUT与内切割道ICUT之间设置第二裂纹挡墙DAM2，以阻挡外切割道OCUT切割时产生的裂纹向显示区AA延伸，对外切割道OCUT的裂纹抑制能力进行补偿。
在本公开的一种实施方式中，参见图9，第二裂纹挡墙DAM2可以设置在识别标记MK与内切割道ICUT之间。这样，外切割道OCUT在切割时产生的裂纹需要先突破第二裂纹挡墙DAM2才能够延伸至内切割道ICUT，然后被内切割道ICUT和第一裂纹挡墙DAM1进一步阻挡。如此，本公开的母板结构可以对外切割道OCUT的裂纹抑制能力进行补偿，降低外切割道OCUT产生的裂纹延伸至第一裂纹挡墙DAM1以内的风险；这样，该母板结构既能够灵活地制备不同的显示面板PNL，又能够避免显示面板PNL的良率降低。
在本公开的一种实施方式中，可以仅仅在各个识别标记MK与内切割道ICUT之间设置第二裂纹挡墙DAM2，以使得各个外切割道OCUT和各个识别标记MK位于第二裂纹挡墙DAM2远离内切割道ICUT的一侧。这样，最靠近所述显示区AA的外切割道OCUT与所述内切割道ICUT之间设置有所述第二裂纹挡墙DAM2。当然的，在本公开的其他实施方式中，还可以在相邻两个外切割道OCUT之间设置第二裂纹挡墙DAM2，以达到更佳的效果。
在本公开的一些实施方式中，参见图9，第二裂纹挡墙DAM2的数量可以为多个；相邻两个所述第二裂纹挡墙DAM2之间设置有裂纹阻挡沟槽DAMG，所述裂纹阻挡沟槽DAMG填充有有机材料。这样，第二裂纹挡墙DAM2之间的无机材料被减薄或者去除，相邻两个第二裂纹挡墙 DAM2之间间隔有有机材料；裂纹延伸至裂纹阻挡沟槽DAMG时，有机材料可以有效吸收和分散裂纹尖端的应力，进而阻挡裂纹的继续延伸。可选的，第二裂纹挡墙DAM2的材料可以为无机材料。在第二裂纹挡墙DAM2之间的裂纹阻挡沟槽DAMG中，既可以完全填充有机材料，也可以部分覆盖新的无机材料且被有机材料填充。进一步的，裂纹阻挡沟槽DAMG还可以设置于最内侧的第二裂纹挡墙DAM2的内侧(靠近显示区AA的一侧)以及最外侧的第二裂纹挡墙DAM2的外侧(远离显示区AA的一侧)，以使得任意一个第二裂纹挡墙DAM2夹设于相邻两个裂纹阻挡沟槽DAMG之间。
在该实施方式中，第二裂纹挡墙DAM2可以由无机材料层BIL图案化而制备，例如可以通过对无机材料层BIL的布局区域进行减薄或者去除以形成裂纹阻挡沟槽DAMG，第二裂纹挡墙DAM2所在区域的其他无机材料层BIL形成所需的第二裂纹挡墙DAM2。可以理解的是，在形成第二裂纹挡墙DAM2后，第二裂纹挡墙DAM2和裂纹阻挡沟槽DAMG内还可以覆盖其他无机层，以使得第二裂纹挡墙DAM2之间具有裂纹阻挡沟槽DAMG为准。
在本公开的实施方式中，在第二裂纹挡墙DAM2所在区域，所述第二裂纹挡墙DAM2的数量在2～8范围内。任意两个裂纹阻挡沟槽DAMG的深度可以相同或者不同；两个裂纹阻挡沟槽DAMG可以在同一图案化过程中制备，也可以在不同的图案化过程中制备。
在本公开的一种实施方式中，参见图11和图12，至少一个所述裂纹阻挡沟槽DAMG的槽底位于所述无机材料层BIL，例如至少一个所述裂纹阻挡沟槽DAMG的槽底位于无机缓冲层Buff或者所述无机阻挡层Barr。
在本公开的另一种实施方式中，参见图13，至少一个所述裂纹阻挡沟槽DAMG的槽底位于所述有机衬底基板BP。
在本公开的一种实施方式中，所述无机材料层BIL包括依次层叠于所述有机衬底基板BP一侧的无机阻挡层Barr、无机缓冲层Buff、栅极绝缘层GI、层间电介质层ILD；所述裂纹阻挡沟槽DAMG的槽底位于所述无机缓冲层Buff、所述无机阻挡层Barr或者所述有机衬底基板BP。
可选的，裂纹阻挡沟槽DAMG可以通过对无机材料层BIL的刻蚀而 获得，裂纹阻挡沟槽DAMG的刻蚀过程可以根据显示面板PNL的工艺过程需要进行调整。举例而言，在本公开的一种实施方式中，显示面板PNL在第一外围区B1具有弯折区。无机材料层BIL在弯折区的部分需要被刻蚀，以提高弯折区的弯折能力。弯折区的无机材料层BIL可以采用两次刻蚀工艺进行刻蚀，也可以采用一次刻蚀工艺，或者三次及三次以上的刻蚀工艺。在对弯折区的无机材料层BIL进行刻蚀时，也可以同时对位于内切割道ICUT外侧的无机材料层BIL进行刻蚀以形成所需的裂纹阻挡沟槽DAMG。当然的，在本公开的其他实施方式中，裂纹阻挡沟槽DAMG的形成也可以与弯折区的刻蚀不同步。
作为一种示例，显示面板PNL在弯折区采用两次刻蚀工艺，即采用第一刻蚀(EBI，edge bending step A+ILD etch)工艺和第二刻蚀(EBB，edge bending step B)工艺。在EBI工艺中，可以对层间电介质层ILD以及层间电介质层ILD以下(层间电介质层ILD靠近有机衬底基板BP一侧)的膜层进行图案化以形成开口，以便暴露半导体层；同时，对弯折区进行初步的刻蚀。参见图11，通过对掩膜版的调整，该EBI工艺也可以用于形成裂纹阻挡沟槽DAMG，这些裂纹阻挡沟槽DAMG可以被定义为第一裂纹阻挡沟槽DAMG1。在EBB工艺中，对弯折区进行进一步刻蚀，以进一步减薄或者去除弯折区的无机材料层BIL。这样，显示面板PNL在弯折区可以进行弯折，进而减小显示装置的边框。参见图12，通过对掩膜版的调整，该EBB工艺也可以用于形成裂纹阻挡沟槽DAMG，这些裂纹阻挡沟槽DAMG可以被定义为第二裂纹阻挡沟槽DAMG2。当然的，在一些实施方式中，对于一些裂纹阻挡沟槽DAMG，可以先采用EBI工艺进行初步的刻蚀，然后再采用EBB工艺进行进一步的刻蚀，则所形成的裂纹阻挡沟槽DAMG可被定义为第三裂纹阻挡沟槽DAMG3(参见图13)。
在本公开的一些实施方式中，参见图11～图13，第一裂纹阻挡沟槽DAMG1的深度小于第二裂纹阻挡沟槽DAMG2，但是两者的槽底均位于无机缓冲层Buff，或者第一裂纹阻挡沟槽DAMG1的槽底位于无机缓冲层Buff而第二裂纹阻挡沟槽DAMG2的槽底位于无机阻挡层Barr。当然的，在另外一些实施方式中，第一裂纹阻挡沟槽DAMG1和第二裂纹阻挡沟槽DAMG2的槽底也可以穿过无机缓冲层Buff而伸入至无机阻挡层Barr。
第三裂纹阻挡沟槽DAMG3的深度可以大于第一裂纹阻挡沟槽DAMG1和第二裂纹阻挡沟槽DAMG2。在本公开的一种实施方式中，第三裂纹阻挡沟槽DAMG3沿显示面板PNL的法线方向贯穿无机材料层BIL而位于有机衬底基板BP。
在本公开的显示面板PNL中，各个裂纹阻挡沟槽DAMG的所采用的制备工艺可以相同或者不相同，即任意两个裂纹阻挡沟槽DAMG的深度可以相同或者不相同。
在一种示例中，参见图14，各个裂纹阻挡沟槽DAMG均为第一裂纹阻挡沟槽DAMG1，即各个裂纹阻挡沟槽DAMG均在EBI工艺中制备。
在另一种示例中，参见图15，各个裂纹阻挡沟槽DAMG均为第二裂纹阻挡沟槽DAMG2，即各个裂纹阻挡沟槽DAMG均在EBB工艺中制备。
在另一种示例中，参见图16，各个裂纹阻挡沟槽DAMG均为第三裂纹阻挡沟槽DAMG3，即各个裂纹阻挡沟槽DAMG均采用EBI工艺+外围区BBB工艺的方式进行制备。
在另一种示例中，参见图17，至少部分裂纹阻挡沟槽DAMG为第一裂纹阻挡沟槽DAMG1，且至少部分裂纹阻挡沟槽DAMG为第二裂纹阻挡沟槽DAMG2，即两个裂纹阻挡沟槽DAMG的深度可以相同或者不同。进一步的，参见图17，沿垂直于裂纹阻挡沟槽DAMG的延伸方向，第一裂纹阻挡沟槽DAMG1和第二裂纹阻挡沟槽DAMG2依次间隔排列。
当然的，上述示例的裂纹阻挡沟槽DAMG的组合形式仅仅为本公开的示例，本公开的显示面板PNL中的裂纹阻挡沟槽DAMG还可以呈现为其他组合方式，本公开对此不作限定。
在本公开的一种实施方式中，所述第二裂纹挡墙DAM2的宽度在5～15微米范围内。当然的，在本公开的其他实施方式中，第二裂纹挡墙DAM2的宽度也可以更宽或者更窄。
在本公开的一种实施方式中，所述裂纹阻挡沟槽DAMG的宽度在5～10微米范围内。当然的，在本公开的其他实施方式中，裂纹阻挡沟槽DAMG的宽度也可以更宽或者更窄。
在本公开的一种实施方式中，所述第二裂纹挡墙DAM2的宽度与所述裂纹阻挡沟槽DAMG的宽度的比值，在0.8～1.2之间。示例性的，第二 裂纹挡墙DAM2的宽度与所述裂纹阻挡沟槽DAMG的宽度的比值为1:1。
本公开实施方式还提供一种显示装置，该显示装置包括上述显示面板实施方式所描述的任意一种显示面板。该显示装置可以为智能手机屏幕、智能手表屏幕或者其他类型的显示装置。由于该显示装置具有上述显示面板实施方式所描述的任意一种显示面板，因此具有相同的有益效果，本公开在此不再赘述。本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (19)

  1. 一种显示面板，包括显示区和围绕所述显示区的外围区；所述外围区具有环绕所述显示区的内切割道以及位于所述内切割道靠近所述显示区一侧的第一裂纹挡墙。
  2. 根据权利要求1所述的显示面板，其中，在所述外围区的至少部分区域，所述显示面板还具有位于所述内切割道远离所述显示区一侧的外切割道；所述外切割道的端部与所述内切割道交汇；
    在所述外切割道与所述内切割道之间，所述显示面板具有第二裂纹挡墙。
  3. 根据权利要求2所述的显示面板，其中，所述内切割道远离所述显示区的一侧设置有识别标记；至少部分所述识别标记的至少部分设置于所述外切割道内。
  4. 根据权利要求2所述的显示面板，其中，所述内切割道远离所述显示区的一侧设置有识别标记；至少部分所述识别标记位于所述外切割道与所述内切割道之间，且所述外切割道靠近所述识别标记的部分的宽度小于所述外切割道的其他部分的宽度。
  5. 根据权利要求3或4所述的显示面板，其中，所述第二裂纹挡墙设置于所述识别标记与所述内切割道之间。
  6. 根据权利要求2～5任意一项所述的显示面板，其中，所述第二裂纹挡墙的数量为多个；相邻两个所述第二裂纹挡墙之间设置有裂纹阻挡沟槽，所述裂纹阻挡沟槽填充有有机材料。
  7. 根据权利要求6所述的显示面板，其中，在所述第二裂纹挡墙所在的区域，所述显示面板包括依次层叠设置的有机衬底基板、无机材料层和有机材料层；
    至少一个所述裂纹阻挡沟槽的槽底位于所述无机材料层。
  8. 根据权利要求6所述的显示面板，其中，在所述第二裂纹挡墙所在的区域，所述显示面板包括依次层叠设置的有机衬底基板、无机材料层和有机材料层；
    至少一个所述裂纹阻挡沟槽的槽底位于所述有机衬底基板。
  9. 根据权利要求7或8所述的显示面板，其中，所述无机材料层包 括依次层叠于所述有机衬底基板一侧的无机阻挡层、无机缓冲层、栅极绝缘层、层间电介质层；
    所述裂纹阻挡沟槽的槽底位于所述无机缓冲层、所述无机阻挡层或者所述有机衬底基板。
  10. 根据权利要求2～9任意一项所述的显示面板，其中，所述第二裂纹挡墙的数量在2～8范围内。
  11. 根据权利要求2～9任意一项所述的显示面板，其中，所述第二裂纹挡墙的宽度在5～15微米范围内。
  12. 根据权利要求6～9任意一项所述的显示面板，其中，所述裂纹阻挡沟槽的宽度在5～10微米范围内。
  13. 根据权利要求6～9任意一项所述的显示面板，其中，所述第二裂纹挡墙的宽度与所述裂纹阻挡沟槽的宽度的比值，在0.8～1.2之间。
  14. 根据权利要求2～13任意一项所述的显示面板，其中，所述外围区包括环绕所述显示区且依次首尾连接的第一外围区、第二外围区、第三外围区和第四外围区；所述第一外围区和所述第三外围区相对设置；所述第一外围区中具有用于绑定外部电路的绑定焊盘；
    所述外切割道设置于所述第一外围区和/或所述第三外围区。
  15. 根据权利要求2～13任意一项所述的显示面板，其中，所述显示面板具有圆角；至少一个所述圆角的边缘与所述外切割道部分重合。
  16. 根据权利要求2～13任意一项所述的显示面板，其中，在至少部分区域，所述外切割道的数量为多条且沿远离所述显示区的方向依次排列；
    最靠近所述显示区的外切割道与所述内切割道之间设置有所述第二裂纹挡墙。
  17. 根据权利要求1～16任意一项所述的显示面板，其中，所述显示面板在所述外围区设置有裂纹检测走线；所述裂纹检测走线设置于所述第一裂纹挡墙和所述显示区之间。
  18. 一种母板结构，其中，所述母板结构包括多个权利要求1～17任意一项所述的显示面板；在所述显示面板之间，所述母板结构具有主切割道；
    在所述主切割道与所述显示面板的内切割道之间，在至少部分区域设 置有外切割道；所述外切割道的端部与所述内切割道交汇；所述外切割道与所述内切割道之间设置有第二裂纹挡墙。
  19. 一种显示装置，包括权利要求1～17任意一项所述的显示面板。
PCT/CN2022/079573 2022-03-07 2022-03-07 显示面板和母板结构、显示装置 WO2023168563A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109872634A (zh) * 2019-03-28 2019-06-11 武汉华星光电半导体显示技术有限公司 一种显示面板
CN110391350A (zh) * 2019-07-29 2019-10-29 云谷（固安）科技有限公司 显示面板以及显示装置
CN111146211A (zh) * 2020-01-02 2020-05-12 京东方科技集团股份有限公司 待切割基板、显示面板及微显示芯片
CN111965870A (zh) * 2020-08-05 2020-11-20 武汉华星光电技术有限公司 显示基板母板及其切割方法
CN113888971A (zh) * 2021-09-30 2022-01-04 京东方科技集团股份有限公司 柔性显示面板及其制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109872634A (zh) * 2019-03-28 2019-06-11 武汉华星光电半导体显示技术有限公司 一种显示面板
CN110391350A (zh) * 2019-07-29 2019-10-29 云谷（固安）科技有限公司 显示面板以及显示装置
CN111146211A (zh) * 2020-01-02 2020-05-12 京东方科技集团股份有限公司 待切割基板、显示面板及微显示芯片
CN111965870A (zh) * 2020-08-05 2020-11-20 武汉华星光电技术有限公司 显示基板母板及其切割方法
CN113888971A (zh) * 2021-09-30 2022-01-04 京东方科技集团股份有限公司 柔性显示面板及其制作方法

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