WO2023166827A1 - 半導体装置および半導体モジュール - Google Patents

半導体装置および半導体モジュール Download PDF

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Publication number
WO2023166827A1
WO2023166827A1 PCT/JP2022/047319 JP2022047319W WO2023166827A1 WO 2023166827 A1 WO2023166827 A1 WO 2023166827A1 JP 2022047319 W JP2022047319 W JP 2022047319W WO 2023166827 A1 WO2023166827 A1 WO 2023166827A1
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Prior art keywords
layer
region
interlayer insulating
insulating layer
emitter
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PCT/JP2022/047319
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English (en)
French (fr)
Japanese (ja)
Inventor
武士 岡本
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to CN202280087530.7A priority Critical patent/CN118511281A/zh
Priority to JP2024504375A priority patent/JPWO2023166827A1/ja
Publication of WO2023166827A1 publication Critical patent/WO2023166827A1/ja
Priority to US18/820,361 priority patent/US20240421049A1/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/035—Etching a recess in the emitter region 
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/415—Insulated-gate bipolar transistors [IGBT] having edge termination structures
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/417—Insulated-gate bipolar transistors [IGBT] having a drift region having a doping concentration that is higher at the collector side relative to other parts of the drift region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/418—Insulated-gate bipolar transistors [IGBT] having a drift region having a doping concentration that is higher at the emitter side relative to other parts of the drift region
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/01—Manufacture or treatment
    • H10D48/021—Manufacture or treatment of two-electrode devices
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/50—Physical imperfections
    • H10D62/53—Physical imperfections the imperfections being within the semiconductor body 
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
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    • H10D8/00—Diodes
    • H10D8/411—PN diodes having planar bodies
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D8/50—PIN diodes 
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/481—Leadframes for devices being provided for in groups H10D8/00 - H10D48/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • the present disclosure relates to semiconductor devices and semiconductor modules.
  • the semiconductor device described in Patent Document 1 includes a semiconductor layer having a front surface, a back surface, and an end face extending in a direction intersecting the front surface, a p-type body region formed in the surface portion of the semiconductor layer, and a surface of the body region.
  • a p-type body region formed in the surface portion of the semiconductor layer, and a surface of the body region.
  • an n + -type source region formed in the rear surface of the semiconductor layer an n ⁇ -type drift region formed so as to be exposed on the back surface of the semiconductor layer and separated from the source region by a body region, and a body with a gate insulating film interposed therebetween.
  • a gate electrode facing the region a drain electrode having a Schottky junction with the drift region on the back surface and having a peripheral edge at a position spaced inward from the end surface of the semiconductor layer, and a drain electrode formed on the back surface side and overlapping the peripheral edge portion of the drain electrode.
  • a back termination structure arranged to:
  • An embodiment of the present disclosure provides a semiconductor device capable of suppressing a decrease in breakdown voltage due to exposure of an interlayer insulating layer to moisture.
  • a semiconductor device includes: a semiconductor chip having a first main surface in which an element formation region including an element structure is formed; A breakdown voltage holding structure formed in a peripheral region and holding a breakdown voltage of the element structure; an interlayer insulating layer formed on the first main surface of the semiconductor chip; a plurality of first conductive layers connected to the breakdown voltage holding structure through the interlayer insulating layer, and insulated from the semiconductor chip by the interlayer insulating layer; a second conductive layer overlapping spaces between the plurality of adjacent first conductive layers; and a protective layer formed on the interlayer insulating layer so as to cover the plurality of first conductive layers and the second conductive layer.
  • FIG. 1 is a schematic external view of a semiconductor device according to an embodiment of the present disclosure.
  • 2 is a schematic plan view of the element chip of FIG. 1.
  • FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2.
  • FIG. 4A and 4B are schematic cross-sectional views of the outer area and the element formation area of the element chip, respectively.
  • FIG. 5 is a schematic cross-sectional view for explaining the structures of the emitter lead-out electrode layer and the gate lead-out electrode layer.
  • FIG. 6 is a diagram schematically showing a planar pattern of the sealing conductive layer.
  • FIG. 7 is a diagram schematically showing a planar pattern of the sealing conductive layer.
  • 8A and 8B are diagrams showing part of the manufacturing process of the semiconductor device.
  • Figures 9A and 9B are diagrams illustrating the steps following Figures 8A and 8B.
  • FIGS. 10A and 10B are diagrams showing the steps following FIGS. 9A and 9B.
  • FIGS. 11A and 11B are diagrams showing the next steps of FIGS. 10A and 10B.
  • Figures 12A and 12B are diagrams illustrating the next steps of Figures 11A and 11B.
  • Figures 13A and 13B are diagrams illustrating the steps following Figures 12A and 12B.
  • Figures 14A and 14B are diagrams illustrating the steps following Figures 13A and 13B.
  • Figures 15A and 15B are diagrams illustrating the steps following Figures 14A and 14B.
  • Figures 16A and 16B are diagrams illustrating the steps following Figures 15A and 15B.
  • Figures 17A and 17B are diagrams illustrating the steps following Figures 16A and 16B.
  • 18A and 18B are schematic cross-sectional views of the outer area and the element formation area of the element chip, respectively.
  • 19A and 19B are schematic cross-sectional views of the outer area and the element forming area of the element chip, respectively.
  • 20A and 20B are schematic cross-sectional views of the outer area and element formation area of the element chip, respectively.
  • FIG. 21 is a diagram schematically showing a planar pattern of a sealing conductive layer.
  • FIG. 22 is a diagram schematically showing a planar pattern of a sealing conductive layer.
  • 23A and 23B are schematic cross-sectional views of the outer area and the element formation area of the element chip, respectively.
  • FIG. 24A and 24B are schematic cross-sectional views of the outer area and the element formation area of the element chip, respectively.
  • FIG. 25 is a schematic cross-sectional view of the outer region of the element chip.
  • 26A and 26B are schematic cross-sectional views of the outer area and the element forming area of the element chip, respectively.
  • FIG. 27 is a schematic external view of a semiconductor module according to an embodiment of the present disclosure; 28 is a circuit diagram showing the electrical structure of the semiconductor module of FIG. 27.
  • FIG. 1 is a schematic external view of a semiconductor device 1 according to an embodiment of the present disclosure.
  • the internal structure of the package body 2 is seen through by showing the package body 2 with a dashed line.
  • the semiconductor device 1 is an IGBT discrete semiconductor including a rectangular parallelepiped package body 2 .
  • the package body 2 is made of mold resin.
  • the package body 2 may include a matrix resin (eg, epoxy resin), multiple fillers and multiple flexible particles (flexibilizers).
  • the package body 2 has a first surface 3 on one side, a second surface 4 on the other side, and first to fourth side walls 5A to 5D connecting the first surface 3 and the second surface 4. As shown in FIG.
  • the first surface 3 and the second surface 4 are formed in a quadrangular shape when viewed from the normal direction Z thereof.
  • the first side wall 5A and the second side wall 5B extend in the first direction X and face the second direction Y perpendicular to the first direction X.
  • the third side wall 5C and the fourth side wall 5D extend in the second direction Y and face the first direction X. As shown in FIG.
  • the semiconductor device 1 includes a metal plate 6 (conductor plate) arranged inside the package body 2 .
  • the metal plate 6 may be called a "die pad".
  • the metal plate 6 is formed in a square shape (specifically, a rectangular shape) in plan view.
  • the metal plate 6 includes a drawer plate portion 7 drawn out of the package body 2 from the first side wall 5A.
  • the drawer plate portion 7 has a circular through hole 8 .
  • the metal plate 6 may be exposed from the second surface 4 .
  • the semiconductor device 1 includes a plurality of (three in this embodiment) lead terminals 9 drawn out from the inside of the package body 2 to the outside.
  • a plurality of lead terminals 9 are arranged on the side of the second side wall 5B.
  • the plurality of lead terminals 9 are each formed in a strip shape extending in the direction perpendicular to the second side wall 5B (that is, the second direction Y).
  • the lead terminals 9 on both sides of the plurality of lead terminals 9 are spaced apart from the metal plate 6 , and the central lead terminal 9 is integrally formed with the metal plate 6 .
  • the arrangement of the lead terminals 9 connected to the metal plate 6 is arbitrary.
  • a semiconductor device 1 includes an element chip 10 arranged on a metal plate 6 within a package body 2 .
  • the element chip 10 has an emitter terminal electrode 11 and a gate terminal electrode 12 on the front side, and has a collector terminal electrode 13 on the back side.
  • the element chip 10 is placed on the metal plate 6 with the collector terminal electrode 13 facing the metal plate 6 and electrically connected to the metal plate 6 .
  • the semiconductor device 1 includes a conductive adhesive 14 interposed between the collector terminal electrode 13 and the metal plate 6 to bond the element chip 10 to the metal plate 6 .
  • Conductive adhesive 14 may include solder or metal paste.
  • the solder may be lead-free solder.
  • the metal paste may contain at least one of Au, Ag and Cu.
  • the Ag paste may consist of Ag sintered paste.
  • the Ag sintering paste consists of a paste in which nano-sized or micro-sized Ag particles are added to an organic solvent.
  • the semiconductor device 1 includes at least one (in this embodiment, a plurality) conducting wires 15 (conductive connection members) electrically connected to the lead terminals 9 and the element chips 10 within the package body 2 .
  • Conductor 15 consists of a metal wire (that is, a bonding wire) in this embodiment.
  • Conductors 15 may include at least one of gold wire, copper wire and aluminum wire.
  • the conducting wire 15 may be made of a metal plate such as a metal clip instead of the metal wire.
  • FIG. 2 is a schematic plan view of the element chip 10 of FIG. 1.
  • FIG. 2 is a schematic plan view of the element chip 10 of FIG. 1.
  • the element chip 10 includes a semiconductor chip 16 formed in a square chip shape when viewed from above.
  • the semiconductor chip 16 has a first main surface 17, a second main surface 18 opposite to the first main surface 17, first to fourth side surfaces 19A connecting the first main surface 17 and the second main surface 18, 19B, 19C, and 19D.
  • the first main surface 17 and the second main surface 18 are formed in a quadrangular shape when viewed from the normal direction Z thereof.
  • the first side surface 19A and the second side surface 19B extend in the first direction X and face the second direction Y orthogonal to the first direction X.
  • the third side surface 19C and the fourth side surface 19D extend in the second direction Y and face the first direction X. As shown in FIG.
  • an element forming area 20 and an outer area 21 and a scribe area 22, which are areas outside the element forming area 20, are set.
  • the element forming region 20 is set in the central region of the semiconductor chip 16 in plan view from the normal direction of the first main surface 17 of the semiconductor chip 16 .
  • the outer region 21 is set in a region outside the element formation region 20 .
  • the scribe area 22 is set in an area outside the outer area 21 .
  • the element formation region 20 is a region in which an IGBT (Insulated Gate Bipolar Transistor) is formed in this embodiment.
  • the element formation region 20 may be called an active region.
  • the element forming region 20 is set to have a square shape in plan view having four sides parallel to the first to fourth side surfaces 19A, 19B, 19C, and 19D of the semiconductor chip 16 in plan view.
  • the element forming region 20 is set inside the semiconductor chip 16 at intervals from the first to fourth side surfaces 19A, 19B, 19C, and 19D of the semiconductor chip 16 .
  • the outer region 21 is a region that defines the outer periphery of the element formation region 20 .
  • the outer region 21 is set in an endless shape (square annular shape in plan view) surrounding the element forming region 20 in the region between the first to fourth side surfaces 19A, 19B, 19C, 19D of the semiconductor chip 16 and the element forming region 20. It is The outer region 21 may be defined as the outer peripheral region of the semiconductor chip 16 from the viewpoint of forming the outer periphery of the element formation region 20 .
  • the scribe area 22 is an area through which a cutting member such as a dicing blade passes during manufacturing.
  • the scribe region 22 is set in an endless shape (quadrangular ring shape in a plan view) surrounding the outer region 21 in a region between the first to fourth side surfaces 19A, 19B, 19C, 19D of the semiconductor chip 16 and the outer region 21.
  • a surface electrode 23 is formed on the first main surface 17 of the semiconductor chip 16 .
  • Surface electrode 23 may include gate terminal electrode 12 , emitter terminal electrode 11 , field plate electrode 24 and equipotential potential electrode 25 .
  • the gate terminal electrode 12, the emitter terminal electrode 11, the field plate electrode 24, and the equipotential electrode 25 are electrically insulated by insulating regions 26 bordering them.
  • the gate terminal electrode 12 is mainly formed in the outer region 21.
  • Gate terminal electrode 12 includes gate pad 27 and gate fingers 28 .
  • the gate pad 27 is formed along the central region of the second side surface 19C in plan view.
  • the gate pad 27 is formed in a square shape in plan view in this embodiment.
  • the gate pad 27 is drawn out from the outer region 21 into the element forming region 20 and crosses the boundary between the element forming region 20 and the outer region 21 .
  • the gate fingers 28 are drawn out from the gate pad 27 in the outer region 21 and surround the element formation region 20 from three directions.
  • the gate finger 28 has a pair of open ends 29, 30 on the side of the fourth side surface 19D.
  • the gate finger 28 extends in a band shape between the pair of open ends 29 and 30 and the gate pad 27 .
  • Gate finger 28 more specifically includes first gate finger 31 and second gate finger 32 .
  • the first gate finger 31 is pulled out from the end of the gate pad 27 on the side of the first side surface 19A.
  • the first gate finger 31 has an open end 29 on the side of the fourth side surface 19D.
  • First gate finger 31 extends in a strip shape along third side surface 19C and first side surface 19A in a region between gate pad 27 and open end 29 .
  • the second gate finger 32 is pulled out from the end of the gate pad 27 on the second side surface 19B side.
  • the second gate finger 32 has an open end 30 on the side of the fourth side surface 19D.
  • the second gate finger 32 extends in a strip shape along the third side surface 19C and the second side surface 19B in the region between the gate pad 27 and the open end 30. As shown in FIG.
  • the emitter terminal electrode 11 includes an emitter pad 33 , an emitter lead-out portion 34 and an emitter connection portion 35 .
  • the emitter pad 33 is formed within a recessed area defined by the peripheral edge of the gate pad 27 and the peripheral edge of the gate finger 28 .
  • the emitter pad 33 is formed in a concave shape along the peripheral edge of the gate pad 27 and the peripheral edge of the gate finger 28 in plan view.
  • the emitter pad 33 covers almost the entire element formation region 20 outside the gate pad 27 .
  • a peripheral edge of the emitter pad 33 extends from the element forming region 20 into the outer region 21 and crosses the boundary between the element forming region 20 and the outer region 21 .
  • the emitter lead-out portion 34 is formed in the outer region 21 .
  • the emitter routing portion 34 is routed in a strip shape in the region outside the gate finger 28 .
  • the emitter lead-out portion 34 is formed in an endless shape (quadrangular annular shape in plan view) surrounding the gate finger 28 .
  • the emitter lead-out portion 34 may be formed in an end-like shape surrounding the gate finger 28 .
  • the emitter connecting portion 35 is drawn out from the emitter pad 33 .
  • An emitter connection portion 35 is connected to the emitter routing portion 34 across the region between the pair of open ends 29 and 30 of the gate finger 28 .
  • the emitter lead-out portion 34 is electrically connected to the emitter pad 33 via the emitter connection portion 35 .
  • the IGBT formed in the element formation region 20 includes an npn-type parasitic bipolar transistor due to its structure.
  • the parasitic bipolar transistor is turned on. In this case, the control of the IGBT becomes unstable due to, for example, latch-up.
  • the emitter terminal electrode 11 including the emitter pad 33, the emitter lead-out portion 34, and the emitter connection portion 35 forms the avalanche current recovery structure 36 for recovering the avalanche current generated in the region outside the element formation region 20. are doing. More specifically, an avalanche current generated in a region outside the element forming region 20 is recovered by the emitter lead-out portion 34 . The recovered avalanche current is extracted from emitter pad 33 via emitter connection 35 . As a result, it is possible to prevent the parasitic bipolar transistor from being turned on by an unwanted current generated in a region outside the element formation region 20 . Therefore, since latch-up can be suppressed, the stability of IGBT control can be enhanced.
  • a field plate electrode 24 is formed in the outer region 21 .
  • the field plate electrodes 24 are indicated by black lines.
  • a plurality of field plate electrodes 24 (four in this embodiment) are formed at intervals in the outer region 21 .
  • Each field plate electrode 24 is routed in a belt shape along the emitter route portion 34 .
  • Each field plate electrode 24 is formed in an endless shape (quadrangular annular shape in plan view) surrounding the emitter lead-out portion 34 in this embodiment. At least one field plate electrode 24 may be formed in an end-like shape.
  • the equipotential potential electrode 25 is formed in the scribe area 22 .
  • the equipotential potential electrode 25 is routed in a belt shape along the field plate electrode 24 .
  • the equipotential potential electrode 25 is formed in an endless shape (quadrangular ring in plan view) surrounding the field plate electrode 24 .
  • the equipotential potential electrode 25 is formed as a so-called EQR (EQui-potential Ring) electrode.
  • EQR EQui-potential Ring
  • FIG. 5 is a schematic cross-sectional view for explaining the structures of the emitter lead-out electrode layer 57 and the gate lead-out electrode layer 56.
  • FIG. 6 and 7 are diagrams schematically showing planar patterns of the sealing conductive layer 83.
  • FIG. 3 it should be noted that the relative proportions of the dimensions of each component (e.g., thickness, width, length, etc.) to each other are not consistent with the dimensional proportions explicitly shown in Figures 3-7. Make a note in advance. Also, FIG. 3 omits some of the components shown in FIGS. 4A and 4B for clarity.
  • semiconductor chip 16 has a single layer structure including n ⁇ -type semiconductor substrate 37 .
  • the semiconductor substrate 37 may be a silicon FZ substrate formed by the FZ (Floating Zone) method in this embodiment. Since the semiconductor chip 16 is formed in layers as a whole, it may be called a semiconductor layer.
  • Semiconductor chip 16 includes an n ⁇ -type drift region 38 .
  • the drift region 38 is formed all over the semiconductor chip 16 in the first direction X and the second direction Y.
  • drift region 38 is also formed in outer region 21 and scribe region 22 in addition to element formation region 20 .
  • the drift region 38 is formed in the surface layer portion of the first main surface 17 of the semiconductor chip 16 in the normal direction Z (thickness direction of the semiconductor chip 16).
  • the n-type impurity concentration of the drift region 38 may be 1.0 ⁇ 10 13 cm ⁇ 3 or more and 1.0 ⁇ 10 15 cm ⁇ 3 or less.
  • the semiconductor device 1 includes a collector terminal electrode 13 as an example of a back electrode formed on the second main surface 18 of the semiconductor chip 16 .
  • Collector terminal electrode 13 is electrically connected to second main surface 18 .
  • Collector terminal electrode 13 forms an ohmic contact with second main surface 18 .
  • Collector terminal electrode 13 may include at least one of a Ti layer, Ni layer, Au layer, Ag layer and Al layer.
  • Collector terminal electrode 13 may have a single layer structure including a Ti layer, Ni layer, Au layer, Ag layer, or Al layer.
  • Collector terminal electrode 13 may have a laminated structure in which at least two of a Ti layer, a Ni layer, an Au layer, an Ag layer and an Al layer are laminated in an arbitrary manner.
  • the semiconductor device 1 includes an n-type buffer layer 39 formed on the surface layer portion of the second main surface 18 of the semiconductor chip 16 .
  • the buffer layer 39 may be formed over the entire surface layer portion of the second main surface 18 .
  • the n-type impurity concentration of the buffer layer 39 is higher than the n-type impurity concentration of the drift region 38 .
  • the n-type impurity concentration of the buffer layer 39 may be 1.0 ⁇ 10 15 cm ⁇ 3 or more and 1.0 ⁇ 10 17 cm ⁇ 3 or less.
  • the thickness of the buffer layer 39 may be 0.5 ⁇ m or more and 30 ⁇ m or less.
  • the thickness of the buffer layer 39 may be 0.5 ⁇ m to 5 ⁇ m, 5 ⁇ m to 10 ⁇ m, 10 ⁇ m to 15 ⁇ m, 15 ⁇ m to 20 ⁇ m, 20 ⁇ m to 25 ⁇ m, or 25 ⁇ m to 30 ⁇ m.
  • the element formation region 20 includes a p-type collector region 40 formed in the surface layer portion of the second main surface 18 of the semiconductor chip 16 .
  • Collector region 40 is exposed from second main surface 18 .
  • the collector region 40 may be formed over the entire surface of the semiconductor chip 16 on the surface layer of the second main surface 18 .
  • collector region 40 is also formed in outer region 21 and scribe region 22 in addition to element formation region 20 .
  • the collector region 40 is also formed in a non-facing region that does not face the body region 46, in addition to the facing region that faces the body region 46, which will be described later.
  • the p-type impurity concentration of the collector region 40 may be 1.0 ⁇ 10 15 cm ⁇ 3 or more and 1.0 ⁇ 10 18 cm ⁇ 3 or less.
  • Collector region 40 forms an ohmic contact with collector terminal electrode 13 .
  • element formation region 20 includes FET structure 41 formed on first main surface 17 of semiconductor chip 16 .
  • the device formation region 20 includes a trench gate type FET structure 41 in this embodiment.
  • FET structure 41 specifically includes a trench gate structure 42 formed in first major surface 17 .
  • a plurality of trench gate structures 42 are formed at intervals along the first direction X in the element formation region 20 .
  • a distance between two trench gate structures 42 adjacent to each other in the first direction X may be 1 ⁇ m or more and 8 ⁇ m or less.
  • the distance between the two trench gate structures 42 is 1 ⁇ m to 2 ⁇ m, 2 ⁇ m to 3 ⁇ m, 3 ⁇ m to 4 ⁇ m, 4 ⁇ m to 5 ⁇ m, 5 ⁇ m to 6 ⁇ m, 6 ⁇ m to 7 ⁇ m, or 7 ⁇ m to 8 ⁇ m.
  • the plurality of trench gate structures 42 may be formed in a strip shape extending along the second direction Y in plan view.
  • the plurality of trench gate structures 42 may be formed in stripes as a whole.
  • the multiple trench gate structures 42 each have one end on one side in the second direction Y and the other end on the other side in the second direction Y. As shown in FIG.
  • the trench gate structure 42 may be formed in a grid pattern in plan view.
  • each trench gate structure 42 includes a gate trench 43, a gate insulating layer 44 and a gate electrode layer 45. As shown in FIG. Gate trench 43 is formed in first main surface 17 . Gate trench 43 includes sidewalls and a bottom wall. A sidewall of gate trench 43 may be formed perpendicular to first main surface 17 .
  • the side walls of the gate trench 43 may slope downward from the first main surface 17 toward the bottom wall.
  • Gate trench 43 may be formed in a tapered shape in which the opening area on the opening side is larger than the bottom area.
  • a bottom wall of gate trench 43 may be formed parallel to first main surface 17 .
  • the bottom wall of gate trench 43 may be curved toward second main surface 18 .
  • Gate trench 43 includes a bottom wall edge. The bottom wall edge portion connects the side wall and the bottom wall of gate trench 43 .
  • the bottom wall edge portion may be curved toward the second major surface 18 .
  • the depth of the gate trench 43 may be 2 ⁇ m or more and 10 ⁇ m or less.
  • the depth of the gate trench 43 may be 2 ⁇ m to 3 ⁇ m, 3 ⁇ m to 4 ⁇ m, 4 ⁇ m to 5 ⁇ m, 5 ⁇ m to 6 ⁇ m, 6 ⁇ m to 7 ⁇ m, 8 ⁇ m to 9 ⁇ m, or 9 ⁇ m to 10 ⁇ m.
  • the depth of gate trench 43 may be defined as the distance between the deepest position of the bottom wall of gate trench 43 and first main surface 17 .
  • the width of the gate trench 43 may be 0.5 ⁇ m or more and 3 ⁇ m or less.
  • the width of the gate trench 43 is the width in the first direction X of the gate trench 43 .
  • the width of the gate trench 43 may be 0.5 ⁇ m to 1 ⁇ m, 1 ⁇ m to 1.5 ⁇ m, 1.5 ⁇ m to 2 ⁇ m, 2 ⁇ m to 2.5 ⁇ m, or 2.5 ⁇ m to 3 ⁇ m.
  • the gate insulating layer 44 is formed like a film along the inner wall of the gate trench 43 .
  • the gate insulating layer 44 defines a recess space within the gate trench 43 .
  • Gate insulating layer 44 includes a silicon oxide film in this embodiment.
  • the gate insulating layer 44 may include a silicon nitride film instead of or in addition to the silicon oxide film.
  • the gate electrode layer 45 is embedded in the gate trench 43 with the gate insulating layer 44 interposed therebetween. Specifically, the gate electrode layer 45 is embedded in a recess space partitioned by the gate insulating layer 44 in the gate trench 43 .
  • the gate electrode layer 45 is controlled by a gate signal.
  • Gate electrode layer 45 may comprise conductive polysilicon.
  • the gate electrode layer 45 is formed in a wall shape extending along the normal direction Z when viewed in cross section. Gate electrode layer 45 has an upper end located on the opening side of gate trench 43 . The upper end of gate electrode layer 45 is located on the bottom wall side of gate trench 43 with respect to first main surface 17 .
  • FET structure 41 includes a p-type body region 46 formed in the surface layer of first main surface 17 of semiconductor chip 16 .
  • the body region 46 may have a p-type impurity concentration of 1.0 ⁇ 10 17 cm ⁇ 3 or more and 1.0 ⁇ 10 18 cm ⁇ 3 or less.
  • a body region 46 is formed on each side of the trench gate structure 42 .
  • Body region 46 is formed in a strip shape extending along trench gate structure 42 in plan view. Body region 46 is exposed from the sidewall of gate trench 43 .
  • the bottom of body region 46 is formed in a region between first main surface 17 and the bottom wall of gate trench 43 with respect to normal direction Z. As shown in FIG.
  • FET structure 41 includes an n + -type emitter region 47 formed in the surface layer of body region 46 .
  • the n-type impurity concentration of emitter region 47 is higher than the n-type impurity concentration of drift region 38 .
  • the n-type impurity concentration of the emitter region 47 may be 1.0 ⁇ 10 19 cm ⁇ 3 or more and 1.0 ⁇ 10 20 cm ⁇ 3 or less.
  • FET structure 41 includes a plurality of emitter regions 47 formed on opposite sides of trench gate structure 42 in this embodiment.
  • the emitter region 47 is formed in a strip shape extending along the trench gate structure 42 in plan view. Emitter region 47 is exposed from first main surface 17 and sidewalls of gate trench 43 .
  • the bottom of emitter region 47 is formed in a region between the top of gate electrode layer 45 and the bottom of body region 46 with respect to normal direction Z. As shown in FIG.
  • the FET structure 41 includes an n + -type carrier storage region 48 formed in a region on the second main surface 18 side with respect to the body region 46 in the semiconductor chip 16 in this embodiment.
  • the n-type impurity concentration of carrier storage region 48 is greater than the n-type impurity concentration of drift region 38 .
  • the n-type impurity concentration of the carrier storage region 48 may be 1.0 ⁇ 10 15 cm ⁇ 3 or more and 1.0 ⁇ 10 17 cm ⁇ 3 or less.
  • FET structure 41 includes a plurality of carrier storage regions 48 formed on either side of trench gate structure 42 in this embodiment.
  • the carrier storage region 48 is formed in a strip shape extending along the trench gate structure 42 in plan view. Carrier storage region 48 is exposed from the sidewalls of gate trench 43 .
  • the bottom of carrier storage region 48 is formed in the region between the bottom of body region 46 and the bottom wall of gate trench 43 with respect to normal direction Z.
  • the carrier storage region 48 prevents the carriers (holes) supplied to the semiconductor chip 16 from being pulled back (ejected) to the body region 46 . As a result, holes are accumulated in the region immediately below the FET structure 41 in the semiconductor chip 16 . As a result, it is possible to reduce the on-resistance and the on-voltage.
  • FET structure 41 includes contact trenches 49 formed in first major surface 17 of semiconductor chip 16 .
  • FET structure 41 includes a plurality of contact trenches 49 formed on opposite sides of trench gate structure 42 in this embodiment.
  • Contact trench 49 exposes emitter region 47 .
  • Contact trench 49 extends through emitter region 47 in this embodiment.
  • the contact trench 49 is spaced in the first direction X from the trench gate structure 42 .
  • the contact trench 49 extends in a strip shape along the trench gate structure 42 in plan view.
  • FET structure 41 includes p + -type contact region 50 formed in a region along the bottom wall of contact trench 49 in body region 46 .
  • the p-type impurity concentration of contact region 50 is higher than the p-type impurity concentration of body region 46 .
  • the p-type impurity concentration of the contact region 50 may be 1.0 ⁇ 10 19 cm ⁇ 3 or more and 1.0 ⁇ 10 20 cm ⁇ 3 or less.
  • Contact region 50 is exposed from the bottom wall of contact trench 49 .
  • the contact region 50 extends in a strip shape along the contact trench 49 in plan view.
  • the bottom of contact region 50 is formed in a region between the bottom wall of contact trench 49 and the bottom of body region 46 with respect to normal direction Z.
  • the gate electrode layer 45 faces the body region 46 and the emitter region 47 with the gate insulating layer 44 interposed therebetween.
  • the gate electrode layer 45 also faces the carrier storage region 48 with the gate insulating layer 44 interposed therebetween.
  • the channel of the IGBT is formed in the body region 46 in the region between the emitter region 47 and the drift region 38 (carrier storage region 48). Channel on/off is controlled by a gate signal.
  • element formation region 20 includes emitter trench structure 51 on first main surface 17 of semiconductor chip 16 .
  • Emitter trench structure 51 is formed in a region adjacent to trench gate structure 42 in the surface layer portion of first main surface 17 .
  • the emitter trench structure 51 is formed in a strip shape extending along the second direction Y in plan view.
  • the plurality of emitter trench structures 51 may be formed in stripes as a whole.
  • the emitter trench structure 51 may be strip-shaped parallel to the trench gate structure 42 .
  • the trench gate structures 42 and the emitter trench structures 51 are alternately arranged along the first direction X at intervals.
  • Trench gate structures 42 and emitter trench structures 51 may be equally spaced and alternating.
  • a distance (pitch) between two trench gate structures 42 and emitter trench structures 51 adjacent to each other in the first direction X may be, for example, 1.0 ⁇ m or more and 3.5 ⁇ m or less.
  • trench gate structure 42 extends longer than emitter trench structure 51 in second direction Y, and has a portion extending in first direction X in a region away from the end of emitter trench structure 51. Referring to FIG. You may have
  • the emitter trench structure 51 includes an emitter trench 52, an emitter insulating layer 53 and an emitter potential electrode layer .
  • Emitter trench 52 is formed in first main surface 17 of semiconductor chip 16 .
  • Emitter trench 52 includes sidewalls and a bottom wall. A sidewall of emitter trench 52 may be formed perpendicular to first main surface 17 .
  • the side walls of the emitter trench 52 may slope downward from the first main surface 17 toward the bottom wall.
  • the emitter trench 52 may be formed in a tapered shape in which the opening area on the opening side is larger than the bottom area.
  • Emitter region 47 , body region 46 and carrier storage region 48 are exposed from sidewalls (outer sidewalls) of emitter trench 52 facing trench gate structure 42 .
  • a bottom wall of emitter trench 52 may be formed parallel to first main surface 17 .
  • the bottom wall of emitter trench 52 may be curved toward second main surface 18 .
  • Emitter trench 52 includes bottom wall edges. The bottom wall edge connects the side and bottom walls of emitter trench 52 .
  • the bottom wall edge portion may be curved toward the second main surface 18 of the semiconductor chip 16 .
  • the depth of the emitter trench 52 may be 2 ⁇ m or more and 10 ⁇ m or less.
  • the depth of the emitter trench 52 may be 2 ⁇ m to 3 ⁇ m, 3 ⁇ m to 4 ⁇ m, 4 ⁇ m to 5 ⁇ m, 5 ⁇ m to 6 ⁇ m, 6 ⁇ m to 7 ⁇ m, 8 ⁇ m to 9 ⁇ m, or 9 ⁇ m to 10 ⁇ m.
  • the depth of emitter trench 52 may be equal to the depth of gate trench 43 .
  • the width of the emitter trench 52 may be 0.5 ⁇ m or more and 3 ⁇ m or less.
  • the width of the emitter trench 52 is the width in the first direction X of the emitter trench 52 .
  • the width of the emitter trench 52 may be 0.5 ⁇ m to 1 ⁇ m, 1 ⁇ m to 1.5 ⁇ m, 1.5 ⁇ m to 2 ⁇ m, 2 ⁇ m to 2.5 ⁇ m, or 2.5 ⁇ m to 3 ⁇ m.
  • the width of emitter trench 52 may be equal to the width of gate trench 43 .
  • the emitter insulating layer 53 is formed like a film along the inner wall of the emitter trench 52 .
  • the emitter insulating layer 53 defines a recess space within the emitter trench 52 .
  • Emitter insulating layer 53 includes a silicon oxide film in this embodiment.
  • Emitter insulating layer 53 may include a silicon nitride film instead of or in addition to the silicon oxide film.
  • the emitter potential electrode layer 54 is embedded in the emitter trench 52 with the emitter insulating layer 53 interposed therebetween. Specifically, the emitter potential electrode layer 54 is embedded in a recess space partitioned by the emitter insulating layer 53 in the emitter trench 52 . Emitter potential electrode layer 54 may include conductive polysilicon. Emitter potential electrode layer 54 is controlled by an emitter signal.
  • the emitter potential electrode layer 54 is formed like a wall extending along the normal direction Z when viewed in cross section. Emitter potential electrode layer 54 has an upper end positioned on the opening side of emitter trench 52 . The upper end of emitter potential electrode layer 54 is located on the bottom wall side of emitter trench 52 with respect to first main surface 17 .
  • a first surface insulating film 55 covering the first main surface 17 is formed.
  • the gate insulating layer 44 and the emitter insulating layer 53 continue to the first surface insulating film 55 outside the gate trench 43 and the emitter trench 52 .
  • the first surface insulating film 55 is formed integrally with the gate insulating layer 44 and the emitter insulating layer 53 from the same insulating material as the gate insulating layer 44 and the emitter insulating layer 53 .
  • a gate lead-out electrode layer 56 and an emitter lead-out electrode layer 57 are formed on the first surface insulating film 55 .
  • the gate lead-out electrode layer 56 is an electrode layer led out of the gate trench 43 from the upper end portion of the gate electrode layer 45 .
  • the gate extraction electrode layer 56 is formed integrally with the gate electrode layer 45 from the same conductive material as the gate electrode layer 45 .
  • the gate lead-out electrode layer 56 is in contact with the first main surface 17 in FIG. Referring to FIG. 3, the gate extraction electrode layer 56 is extracted to a region immediately below the gate finger 28 (gate terminal electrode 12).
  • Gate lead-out electrode layer 56 is electrically connected to gate finger 28 . This electrically connects the trench gate structure 42 to the gate terminal electrode 12 .
  • the emitter extraction electrode layer 57 is an electrode layer that is extracted from the upper end of the emitter potential electrode layer 54 to the outside of the emitter trench 52 .
  • the emitter extraction electrode layer 57 is formed integrally with the emitter potential electrode layer 54 from the same conductive material as the emitter potential electrode layer 54 . Referring to FIG. 5, emitter extraction electrode layer 57 is extracted to a region immediately below emitter terminal electrode 11 .
  • Emitter extraction electrode layer 57 is electrically connected to emitter terminal electrode 11 .
  • Emitter extraction electrode layer 57 and emitter terminal electrode 11 may be connected by a laminated structure of barrier layer 105 (eg, titanium-based metal) and contact plug 106 (eg, tungsten). Thereby, the emitter trench structure 51 is electrically connected to the emitter terminal electrode 11 .
  • a second surface insulating film 58 is formed on the first main surface 17 of the semiconductor chip 16. As shown in FIG. The second surface insulating film 58 is formed on the surfaces of the gate electrode layer 45, the gate lead-out electrode layer 56, the emitter potential electrode layer 54 and the emitter lead-out electrode layer 57, and the gate electrode layer 45, the gate lead-out electrode layer 56, the emitter It covers the potential electrode layer 54 and the emitter extraction electrode layer 57 . Second surface insulating film 58 may be an insulating film in contact with gate electrode layer 45 , gate lead-out electrode layer 56 , emitter potential electrode layer 54 and emitter lead-out electrode layer 57 .
  • the second surface insulating film 58 includes a silicon oxide film in this embodiment.
  • the second surface insulating film 58 may include a silicon nitride film instead of or in addition to the silicon oxide film.
  • termination region 59 as an example of a breakdown voltage holding structure is formed in the surface layer portion of first main surface 17 of semiconductor chip 16 .
  • the termination region 59 is a p-type impurity region formed by introducing a p-type impurity into the n ⁇ -type drift region 38 .
  • Termination region 59 is formed in an endless shape surrounding element formation region 20 .
  • the termination region 59 includes a resurf layer 60 and a field limit region 61.
  • the RESURF layer 60 relaxes the electric field in the outer region 21 .
  • the RESURF layer 60 may be a high-concentration, low-resistance region having a p-type impurity concentration higher than that of the body region 46 .
  • the RESURF layer 60 is formed in an endless shape (quadrangular annular shape in plan view) so as to surround the element formation region 20 .
  • the bottom of the resurf layer 60 is formed closer to the second main surface 18 of the semiconductor chip 16 than the bottom of the body region 46 in the thickness direction of the semiconductor chip 16 .
  • the bottom of the resurf layer 60 is formed closer to the second main surface 18 of the semiconductor chip 16 than the bottoms of the trench gate structure 42 and the emitter trench structure 51 in the thickness direction of the semiconductor chip 16 .
  • the RESURF layer 60 overlaps the bottoms of the trench gate structure 42 and the emitter trench structure 51 .
  • the end of the stripe of trench gate structure 42 and emitter trench structure 51 aligned in first direction X is emitter trench structure 51 , so resurf layer 60 covers the entire bottom of emitter trench structure 51 and trench gate structure 42 . It overlaps part of the bottom.
  • the RESURF layer 60 may overlap the entire bottom of the trench gate structure 42 and part of the bottom of the emitter trench structure 51. good.
  • the bottom of the RESURF layer 60 is formed with a gap from the collector region 40 to the first main surface 17 side of the semiconductor chip 16 .
  • the RESURF layer 60 faces the collector region 40 with a partial region of the drift region 38 interposed therebetween.
  • the RESURF layer 60 faces the emitter terminal electrode 11 and the gate terminal electrode 12 (gate fingers 28) with the first surface insulating film 55 (not shown in FIG. 3) interposed therebetween.
  • the RESURF layer 60 faces the gate extraction electrode layer 56 with the first surface insulating film 55 (not shown in FIG. 3) interposed therebetween.
  • the field limit region 61 relaxes the electric field in the outer region 21.
  • the field limit region 61 has substantially the same p-type impurity concentration as the resurf layer 60 .
  • the field limit region 61 may have approximately the same depth as the resurf layer 60 .
  • a field limit region 61 is formed along the resurf layer 60 in the outer region 21 .
  • the field limit region 61 is formed in an endless shape (quadrangular annular shape in plan view) so as to surround the resurf layer 60 .
  • the field limit area 61 is formed as an FLR (Field Limiting Ring) area.
  • the field limit regions 61 in this embodiment include a plurality of (four in this embodiment) field limit regions 61 formed at intervals from the element formation region 20 toward the scribe region 22 . At least one field limit region 61 may be formed. Therefore, four or more field limit regions 61 may be formed.
  • a field insulating layer 62 is formed on the first main surface 17 of the semiconductor chip 16 in the outer region 21. As shown in FIG. The field insulating layer 62 is selectively formed in a region where the termination region 59 is not formed on the first main surface 17 and the n-type impurity region (drift region 38 in this embodiment) is exposed. More specifically, it is formed to cover drift region 38 in a region between adjacent termination regions 59 .
  • FIG. 4A shows the field insulating layer 62 on the region sandwiched between the adjacent field limit regions 61, but the region between the field limit region 61 and the resurf layer 60, and the field limit region 61, which will be described later.
  • a field insulating layer 62 may also be formed in the region between it and the channel stop region 65 .
  • the field insulating layer 62 may have a plurality of openings 63 selectively exposing the first major surface 17 , and the termination regions 59 may be exposed from the openings 63 .
  • the field insulating layer 62 may be a LOCOS (Local oxidation of silicon) oxide film in this embodiment. Also, the thickness TF of the field insulating layer 62 may be, for example, 5000 ⁇ or more and 20000 ⁇ or less.
  • a third surface insulating film 64 is formed on the first main surface 17 exposed from the opening 63 of the field insulating layer 62 .
  • the third surface insulating film 64 includes a silicon oxide film in this embodiment.
  • the third surface insulating film 64 may include a silicon nitride film instead of or in addition to the silicon oxide film.
  • a third surface insulating film 64 is formed over the entire opening 63 to cover the surface of the termination region 59 .
  • n + -type channel stop regions 65 are formed in the surface layer portion of first main surface 17 of semiconductor chip 16 in scribe region 22 .
  • the channel stop region 65 is a high-concentration, low-resistance region having an n-type impurity concentration higher than that of the n ⁇ -type drift region 38 .
  • the channel stop region 65 suppresses expansion of the depletion layer from the pn junction formed in the inner region of the semiconductor chip 16 .
  • a channel stop region 65 is formed along the field limit region 61 .
  • the channel stop region 65 is formed in an endless shape (quadrangular annular shape in plan view) surrounding the field limit region 61 .
  • Channel stop region 65 may be formed across the boundary between outer region 21 and scribe region 22 .
  • an interlayer insulating layer 66 is formed on the first main surface 17 of the semiconductor chip 16 .
  • the interlayer insulating layer 66 covers the element formation region 20 , the outer region 21 and the scribe region 22 .
  • the interlayer insulating layer 66 has a different thickness for each region of the semiconductor chip 16 that is covered with the interlayer insulating layer 66, and there is a difference in thickness between a plurality of regions.
  • the thickness TA of the element covering portion 67 of the interlayer insulating layer 66 covering the element formation region 20 is thinner than the thickness TC of the outer covering portion 68 of the interlayer insulating layer 66 covering the outer region 21 . ing.
  • the thickness TA may be 3000 ⁇ or more and 20000 ⁇ or less, and the thickness TC may be 4000 ⁇ or more and 30000 ⁇ or less. Both the thickness TA and the thickness TC may be thicker than the thickness TF of the field insulating layer 62 (see FIG. 4A).
  • a step 70 is formed on the surface of the interlayer insulating layer 66 at the boundary 69 between the element forming region 20 and the outer region 21 due to the difference between the thickness TA and the thickness TC.
  • the field insulating layer 62 and the interlayer insulating layer 66 may be collectively referred to simply as an interlayer insulating layer.
  • the interlayer insulating layer 66 is formed with a first contact hole 71, a second contact hole 72 and a third contact hole 73 for the emitter terminal electrode 11. As shown in FIG.
  • the first contact hole 71 communicates with the contact trench 49 .
  • the first contact hole 71 may be called an emitter contact hole.
  • the second contact hole 72 penetrates the interlayer insulating layer 66 and is formed by digging a part of the first main surface 17 (resurf layer 60 ) of the semiconductor chip 16 .
  • the second contact hole 72 may be formed to extend along the stripes of the FET structure 41 .
  • a p + -type contact region 77 is formed at the bottom of the second contact hole 72 .
  • the contact region 77 may be a high-concentration region in which the p-type impurity concentration in the RESURF layer 60 is higher than that of other regions.
  • the second contact hole 72 may be referred to as a first outer emitter contact hole.
  • the third contact hole 73 penetrates the interlayer insulating layer 66 and is formed by digging a part of the first main surface 17 (resurf layer 60 ) of the semiconductor chip 16 .
  • Third contact hole 73 may be formed to extend along emitter routing portion 34 .
  • a p + -type contact region 78 is formed at the bottom of the third contact hole 73 .
  • the contact region 78 may be a high-concentration region in which the p-type impurity concentration in the RESURF layer 60 is higher than that of other regions (excluding the contact region 77).
  • Contact region 78 may have substantially the same impurity concentration as contact region 77 .
  • the third contact hole 73 may be referred to as a second outer emitter contact hole.
  • a fourth contact hole 74 for the gate terminal electrode 12 is formed in the interlayer insulating layer 66 .
  • the gate extraction electrode layer 56 is exposed through the fourth contact hole 74 .
  • the fourth contact hole 74 may be formed to extend along the gate finger 28 .
  • the fourth contact hole 74 may be called a gate contact hole.
  • a fifth contact hole 75 for the field plate electrode 24 is formed in the interlayer insulating layer 66 .
  • a plurality of fifth contact holes 75 are formed in a one-to-one correspondence with the plurality of field limit regions 61 .
  • Each fifth contact hole 75 penetrates the interlayer insulating layer 66 and is formed by digging a portion of the first main surface 17 (field limit region 61 ) of the semiconductor chip 16 .
  • Each fifth contact hole 75 is formed along the first to fourth side surfaces 19A to 19D of the semiconductor chip 16, and may be formed in an endless shape (quadrangular ring shape in a plan view) surrounding the element forming region 20.
  • a field limit region 61 is exposed from the bottom of each fifth contact hole 75 .
  • the fifth contact hole 75 may be called a field contact hole.
  • a sixth contact hole 76 for the equipotential electrode 25 is formed in the interlayer insulating layer 66 .
  • the sixth contact hole 76 penetrates the interlayer insulating layer 66 and is formed by digging a part of the first main surface 17 (channel stop region 65 ) of the semiconductor chip 16 .
  • the sixth contact hole 76 further extends to the first to fourth side surfaces 19A to 19D (fourth side surface 19D is shown in FIG. 3) of the semiconductor chip 16 and is open at the first to fourth side surfaces 19A to 19D.
  • the sixth contact hole 76 is formed along the first to fourth side surfaces 19A to 19D of the semiconductor chip 16, and is formed in an endless shape (quadrangular ring shape in a plan view) surrounding the outer region 21 and the element formation region 20.
  • the sixth contact hole 76 may be referred to as a peripheral stepped portion of the semiconductor chip 16 from the viewpoint of being a stepped portion formed in the peripheral portion of the semiconductor chip 16 .
  • a p + -type contact region 79 is formed in a region along the bottom of the sixth contact hole 76 in the semiconductor chip 16 .
  • Contact region 79 may have approximately the same impurity concentration as contact regions 77 and 78 .
  • the above-described surface electrode 23 is formed on the interlayer insulating layer 66 .
  • the surface electrode 23 is a conductive film formed on the outermost surface of the semiconductor chip 16, and may be called a surface electrode film or a surface conductive film.
  • surface electrodes 23 include emitter terminal electrode 11 , gate terminal electrode 12 , field plate electrode 24 and equipotential potential electrode 25 .
  • the emitter terminal electrode 11 is electrically connected to the FET structure 41 through the first contact hole 71 and electrically connected to the RESURF layer 60 through the second contact hole 72 and the third contact hole 73 .
  • the gate terminal electrode 12 is electrically connected to the gate extraction electrode layer 56 through the fourth contact hole 74 .
  • Field plate electrode 24 is electrically connected to field limit region 61 through fifth contact hole 75 .
  • the equipotential electrode 25 is electrically connected to the channel stop region 65 through the sixth contact hole 76 .
  • the semiconductor chip 16 is formed between the first electrode portion on the element forming region 20 and the second electrode portion on the outer region 21 and the scribe region 22 of the surface electrode 23 . are different in height from the first main surface 17 to the surface.
  • the surface height H2 of the second electrode portion is higher than the surface height H1 of the first electrode portion.
  • the second electrode portion conceptually includes, for example, the gate finger 28, the emitter lead-out portion 34, the field plate electrode 24, the equipotential electrode 25, and the like.
  • the first electrode part conceptually includes an emitter pad 33 .
  • the surface height H1 and the surface height H2 may be distances from the first main surface 17 of the semiconductor chip 16 to the surface of each portion of the surface electrode 23, as shown in FIG. 3, for example. Thereby, a height difference G is formed on the surface electrode 23 with the boundary portion 69 interposed therebetween.
  • the height difference G may be, for example, 3000 ⁇ or more and 20000 ⁇ or less.
  • a protective layer 80 is formed on the interlayer insulating layer 66 .
  • the protective layer 80 is an insulating layer covering the outermost surface of the semiconductor chip 16, and may be called a surface protective layer or an organic resin layer.
  • Protective layer 80 may be made of, for example, polyimide resin or PBO (Polybenzoxazole) resin.
  • the thickness of protective layer 80 may be, for example, 3 ⁇ m or more and 15 ⁇ m or less.
  • the protective layer 80 selectively covers the surface electrodes 23 . More specifically, the protective layer 80 has an opening 81 that exposes the emitter pad 33 in the element formation region 20 and covers the surface electrode 23 in the outer region 21 .
  • spaces 82 are provided between portions of the surface electrode 23 in the outer region 21 .
  • the spaces 82 are, for example, sequentially from right to left on the paper surface of FIG. a space 82 sandwiched between two adjacent field plate electrodes 24 (three in FIG. 3), and a space 82 sandwiched between the field plate electrode 24 and the equipotential potential electrode 25 adjacent thereto. and may include
  • the organic resin layer has sufficient resistance to mechanical stress such as scratches from the outside, but it is resistant to the intrusion of moisture (OH ⁇ , H + etc.) from the outside. Therefore, it cannot be said that it has sufficient resistance. Therefore, moisture passing through the protective layer 80 and the space 82 enters the interlayer insulating layer 66 and is polarized, which may disrupt the electric field balance of the breakdown voltage holding structure such as the termination region 59 and cause breakdown voltage fluctuations. Therefore, in this embodiment, as shown in FIGS. 4A, 6 and 7, a part of the interlayer insulation layer 66 is partially covered by providing the interlayer insulation layer 66 with a sealing conductive layer 83 insulated from the semiconductor chip 16. It is coated to prevent moisture (OH ⁇ , H + etc.) from entering from the outside.
  • the sealing conductive layer 83 may be called a covering conductive layer from the viewpoint of covering part of the interlayer insulating layer 66 .
  • FIG. 4A shows the sealing conductive layer 83 facing the space 82 sandwiched between the field plate electrodes 24 adjacent to each other, similar sealing conductive layers 83 may be arranged in other spaces 82 as well. can be done.
  • field plate electrode 24 includes contact portion 84 and surface layer portion 85 .
  • the contact portion 84 is embedded in the interlayer insulating layer 66 and connected to the field limit region 61 .
  • the interlayer insulating layer 66 has a laminated structure of a first layer 86 and a second layer 87 on the first layer 86 .
  • the contact portion 84 reaches the field limit region 61 through a fifth contact hole 75 that continuously penetrates the first layer 86 and the second layer 87 .
  • the first layer 86 and the second layer 87 of the interlayer insulating layer 66 clearly show the boundary 88 in FIG. 4A.
  • the boundary portion 88 may not be confirmed.
  • the portion corresponding to the first layer 86 may be referred to as the first portion
  • the portion corresponding to the second layer 87 may be referred to as the second portion based on the height from the first major surface 17 .
  • the first layer 86 and the second layer 87 have uniform first thickness T1 and second thickness T2 along the first major surface 17, respectively.
  • the first thickness T1 of the first layer 86 may be thicker than the second thickness T2 of the second layer 87 .
  • the first thickness T1 may be 3000 ⁇ or more and 20000 ⁇ or less
  • the second thickness T2 may be 1000 ⁇ or more and 10000 ⁇ or less.
  • the thickness TC of the outer covering portion 68 of the interlayer insulating layer 66 shown in FIG. 3 may be the total thickness of the first thickness T1 and the second thickness T2. Note that in FIG. 4A, the structure of the semiconductor chip 16 is deformed and a part of the second layer 87 is shown to be thick, so the apparent thickness TC is greater than the total thickness of the first thickness T1 and the second thickness T2. is also thicker.
  • the thickness TA of the element covering portion 67 of the interlayer insulating layer 66 is thinner than the thickness TC of the outer covering portion 68 of the interlayer insulating layer 66 covering the outer region 21 .
  • the thickness TA may be substantially the same as the first thickness T1. Therefore, the thickness TA may be, for example, 3000 ⁇ or more and 20000 ⁇ or less.
  • the difference between the thickness TA and the thickness TC forms the height difference G (see FIG. 3) on the surface electrode 23 .
  • the surface height H1 of the surface electrode 23 is 10000 ⁇ or more and 75000 ⁇ or less.
  • surface height H2 of surface electrode 23 on outer covering portion 68, which is relatively thicker than element covering portion 67, may be, for example, 15000 ⁇ or more and 95000 ⁇ or less.
  • a height difference G corresponding to, for example, the second thickness T2 of the second layer 87 may be formed between the surface height H1 and the surface height H2.
  • the fifth contact hole 75 may include a lower contact hole 89 and an upper contact hole 90 .
  • a lower contact hole 89 is formed in the first layer 86 and an upper contact hole 90 is formed in the second layer 87 .
  • the lower contact hole 89 may have a narrower width than the upper contact hole 90 .
  • the lower contact hole 89 penetrates the first layer 86 of the interlayer insulating layer 66 and is formed by digging a part of the first main surface 17 (field limit region 61 ) of the semiconductor chip 16 .
  • a p + -type contact region 91 is formed at the bottom of the lower contact hole 89 .
  • the contact region 91 may be a high-concentration region in which the p-type impurity concentration in the field limit region 61 is higher than that in other regions.
  • the contact portion 84 of the field plate electrode 24 may include a first embedded portion 92 embedded in the lower contact hole 89 and a second embedded portion 93 embedded in the upper contact hole 90 .
  • the first buried portion 92 has a laminated structure including a barrier layer 94 and contact plugs 95 in this embodiment.
  • the first buried portion 92 may be called a field plug electrode.
  • Barrier layer 94 is formed in a film shape along the inner wall of lower contact hole 89 so as to be in contact with interlayer insulating layer 66 .
  • the barrier layer 94 defines a recess space within the lower contact hole 89 .
  • the barrier layer 94 may have a single layer structure including a titanium-based metal, more specifically a titanium layer or a titanium nitride layer.
  • Barrier layer 94 may have a laminated structure including a titanium layer and a titanium nitride layer. In this case, the titanium nitride layer may be laminated on the titanium layer.
  • the barrier layer 94 is further drawn out from the lower contact hole 89 to the surface of the first layer 86 and selectively formed on the surface of the first layer 86 .
  • the contact plug 95 is embedded in the lower contact hole 89 with the barrier layer 94 interposed therebetween. Specifically, the contact plug 95 is embedded in a recess space defined by the barrier layer 94 in the lower contact hole 89 .
  • the contact plug 95 may contain tungsten.
  • the second embedded portion 93 is made of a conductive material different from that of the contact plug 95 .
  • the second embedded portion 93 is made of an aluminum-based metal. More specifically, the second embedded portion 93 may contain at least one of aluminum, copper, an aluminum-silicon-copper alloy, an aluminum-silicon alloy, and an aluminum-copper alloy.
  • an emitter plug electrode 96 is embedded in the first contact hole 71 .
  • the emitter plug electrode 96 has a laminated structure including a barrier layer 97 and a contact plug 98 in this embodiment.
  • the barrier layer 97 is formed in a film shape along the inner wall of the first contact hole 71 so as to be in contact with the interlayer insulating layer 66 .
  • the barrier layer 97 defines a recess space within the first contact hole 71 .
  • the barrier layer 97 may have a single layer structure including a titanium-based metal, more specifically a titanium layer or a titanium nitride layer.
  • Barrier layer 97 may have a laminated structure including a titanium layer and a titanium nitride layer.
  • the titanium nitride layer may be laminated on the titanium layer.
  • the barrier layer 97 is further extracted from the first contact hole 71 to the surface of the interlayer insulating layer 66 and selectively formed on the surface of the interlayer insulating layer 66 .
  • the contact plug 98 is embedded in the first contact hole 71 with the barrier layer 97 interposed therebetween. Specifically, the contact plug 98 is embedded in a recess space defined by the barrier layer 97 in the first contact hole 71 . Contact plug 98 may contain tungsten.
  • the emitter terminal electrode 11 is made of a conductive material different from that of the contact plug 98 .
  • the emitter terminal electrode 11 is made of an aluminum-based metal. More specifically, emitter terminal electrode 11 may contain at least one of aluminum, copper, aluminum-silicon-copper alloy, aluminum-silicon alloy, and aluminum-copper alloy.
  • the gate terminal electrode 12 and the equipotential potential electrode 25 which are other portions of the surface electrode 23 , may also be made of the same conductive material as the emitter terminal electrode 11 .
  • the surface electrode 23 is formed of a metal material in this way, the surface electrode 23 may be called a surface metal.
  • the surface layer portion 85 is formed as a lead portion led from the contact portion 84 to the surface of the interlayer insulating layer 66 (second layer 87).
  • the surface layer portion 85 is formed integrally with the second embedded portion 93 from the same material as the second embedded portion 93 . More specifically, the surface layer portion 85 extends laterally along the surface of the interlayer insulating layer 66 from the periphery of the fifth contact hole 75 (in this embodiment, the periphery of the upper contact hole 90).
  • the surface region of the interlayer insulating layer 66 having a constant width from the periphery of the hole 75 is contacted and covered.
  • a portion formed of the same material as the surface layer portion 85 (in this embodiment, the surface layer portion 85 and the second embedded portion 93) is called a main electrode layer, and is formed of a material different from that of the main electrode layer.
  • the portion formed and directly connected to the termination region 59 (in this embodiment, the first embedded portion 92) may be referred to as a contact electrode layer.
  • the sealing conductive layer 83 is formed as an embedded conductive layer embedded in the interlayer insulating layer 66 in this embodiment. More specifically, the sealing conductive layer 83 is formed on the first layer 86 of the interlayer insulating layer 66 in the thickness direction (longitudinal direction) of the interlayer insulating layer 66 and is covered with the second layer 87 . ing. In addition, the sealing conductive layer 83 is arranged directly above the field insulating layer 62 with respect to the thickness direction (longitudinal direction) of the interlayer insulating layer 66 , and the interlayer insulating layer 66 (first layer 86 ) and the field insulating layer 62 are separated from each other.
  • the sealing conductive layer 83 is arranged in a region between the field plate electrodes 24 adjacent to each other in the lateral direction along the surface of the interlayer insulating layer 66 .
  • a sealing conductive layer 83 is disposed on the surface region of the first layer 86 sandwiched between adjacent contact portions 84 .
  • the sealing conductive layer 83 is made of a conductive material supported by the barrier layer 94 on the first layer 86 .
  • This conductive material may be the same material as the contact portion 84 (in this embodiment, the second embedded portion 93). That is, the sealing conductive layer 83 is made of an aluminum-based metal. More specifically, encapsulation conductive layer 83 may include at least one of aluminum, copper, an aluminum-silicon-copper alloy, an aluminum-silicon alloy, and an aluminum-copper alloy. When the sealing conductive layer 83 is formed of a metal material in this way, the sealing conductive layer 83 may be called a sealing metal. Also, the sealing conductive layer 83 may be defined as having a laminated structure of the barrier layer 94 and a main conductive layer made of an aluminum-based metal.
  • the contact portion 84 of the field plate electrode 24 includes a protruding portion 100 that selectively protrudes into a region on the first layer 86 toward the sealing conductive layer 83 .
  • the projecting portion 100 and the surface layer portion 85 are pulled out vertically from the contact portion 84, so the projecting portion 100 is referred to as a first lead portion 101, and the surface layer portion 85 outside the fifth contact hole 75 is pulled out.
  • a portion may be referred to as a second drawer portion 102 .
  • a first lead portion 101 is embedded inside the interlayer insulating layer 66 , and a second lead portion 102 is formed on the surface of the interlayer insulating layer 66 .
  • the first lead-out portion 101 and the second lead-out portion 102 face each other vertically with a portion of the interlayer insulating layer 66 (the second layer 87 in this embodiment) interposed therebetween.
  • the distance D2 from the peripheral surface of the contact portion 84 to the lateral end of the second lead portion 102 is the distance from the peripheral surface of the contact portion 84 to the lateral end of the first lead portion 101 (protruding portion 100). Longer than D1.
  • the distance D1 may be 0 ⁇ m or more and 10 ⁇ m or less, and the distance D2 may be 5 ⁇ m or more and 15 ⁇ m or less.
  • First lead-out portion 101 (protruding portion 100 ) extends outside opening 63 of field insulating layer 62 in the direction along first main surface 17 .
  • the entire opening 63 is covered from above by the contact portion 84 and the first lead-out portion 101 (protruding portion 100 ), and the peripheral portion of the field insulating layer 62 near the opening 63 is covered by the first lead-out portion 101 . ing.
  • the second lead-out portion 102 of the surface layer portion 85 is formed as an overlapping portion that overlaps the sealing conductive layer 83 in the thickness direction of the interlayer insulating layer 66 .
  • the sealing conductive layer 83 faces part of the surface layer portion 85 in the thickness direction of the interlayer insulating layer 66 . Therefore, in FIG. 4A, the sealing conductive layer 83 faces the space 82 at its lateral central portion and faces the second lead portions 102 of the surface layer portion 85 at both lateral ends.
  • the first spacing W1 between the first lead-out portion 101 (protruding portion 100) and the sealing conductive layer 83 is equal to the second spacing between the ends 99 of the second lead-out portions 102 of the adjacent field plate electrodes 24. Narrower than W2 (the width of the space 82).
  • the first interval W1 may be 1 ⁇ m or more
  • the second interval W2 may be 10 ⁇ m or more
  • the first interval W1 may be 1 ⁇ m or more and 5 ⁇ m or less
  • the second interval W2 may be 10 ⁇ m or more and 15 ⁇ m or less. preferable.
  • FIGS. 6 and 7 the planar patterns of the field plate electrode 24 and the sealing conductive layer 83 will be described with reference to FIGS. 6 and 7.
  • FIG. 6 and 7 for clarity, only the constituent elements necessary for explaining the planar pattern of the sealing conductive layer 83 are shown, and some of the constituent elements shown in FIGS. 2 to 5 are other configurations. are omitted.
  • the field plate electrode 24 is shown hatched, and the sealing conductive layer 83 is shown with broken lines.
  • spaces 82 between the plurality of field plate electrodes 24 are formed in a line shape in plan view. More specifically, since each field plate electrode 24 is endless surrounding the element forming region 20 , the space 82 is also endless surrounding the element forming region 20 .
  • the sealing conductive layer 83 is formed in a line shape extending along the line-shaped space 82 in plan view.
  • the sealing conductive layer 83 may be formed in an endless shape in a plan view and may overlap the endless space 82 over the entire circumference.
  • a plurality of line-shaped (linear or curved) sealing conductive layers 83 may be arranged at intervals along the circumferential direction of the space 82 .
  • the sealing conductive layer 83 may include an inner peripheral edge portion 103 overlapping the circumferentially inner field plate electrode 24 and an outer peripheral edge portion 104 overlapping the circumferentially outer field plate electrode 24 in plan view. Inner perimeter 103 and outer perimeter 104 may each overlap field plate electrode 24 over the entire length of encapsulation conductive layer 83 .
  • the sealing conductive layer 83 is arranged so as to face the space 82 (so as to overlap in plan view). This can prevent moisture (OH ⁇ , H + , etc.) from entering the interlayer insulating layer 66 through the space 82 . As a result, it is possible to suppress variations in breakdown voltage due to polarization caused by moisture or the like, and to suppress a decrease in breakdown voltage in the vicinity of the field limit region 61 .
  • the second lead portion 102 of the field plate electrode 24 and the sealing conductive layer 83 overlap each other in the thickness direction of the interlayer insulating layer 66 .
  • the space 82 completely overlaps the sealing conductive layer 83 in the region where the sealing conductive layer 83 is arranged.
  • the effect of preventing moisture (OH ⁇ , H + , etc.) from entering the interlayer insulating layer 66 can be further enhanced.
  • the field plate electrode 24 has a protruding portion 100 (first lead portion 101 ) protruding toward the sealing conductive layer 83 .
  • the first gap W1 between the field plate electrode 24 (contact portion 84) and the sealing conductive layer 83 can be narrowed.
  • the entry path of moisture (OH ⁇ , H + , etc.) can be narrowed, so that the effect of preventing moisture (OH ⁇ , H + , etc.) from entering the interlayer insulating layer 66 can be further enhanced.
  • FIG. 8A and 8B to 17A and 17B are diagrams showing part of the manufacturing process of the semiconductor device 1 in order of process, mainly showing the manufacturing process of the element chip 10.
  • FIG. 8A and 8B to 17A and 17B, the drawings numbered with “A” show the cross section corresponding to FIG. 4A, and the drawings numbered with "B” correspond to FIG. 4B. It shows a cross section.
  • the element chip 10 may be prepared first.
  • a semiconductor substrate 37 in the form of a semiconductor wafer is prepared.
  • a plurality of device formation regions corresponding to the semiconductor devices 1 are set on the semiconductor substrate 37 .
  • Each device formation region includes an element formation region 20 , an outer region 21 and a scribe region 22 .
  • the same structure is simultaneously formed in the plurality of device formation regions.
  • the semiconductor substrate 37 is cut along the periphery of the scribe region 22 in each device formation region. The structure of one device formation region will be described below.
  • field insulating layer 62 is selectively formed on first main surface 17 of semiconductor substrate 37 .
  • field insulating layer 62 for example, the entire surface of first main surface 17 is thermally oxidized to form a thermal oxide film.
  • a nitride film having an opening exposing a region where field insulating layer 62 is to be formed in this thermal oxide film is selectively formed on the thermal oxide film.
  • a field insulating layer 62 is then formed by LOCOS oxidation of the thermal oxide film exposed from the opening of the nitride film. After forming the field insulating layer 62, the nitride layer is removed.
  • the next step is the step of forming the termination region 59 .
  • the entire surface of first main surface 17 is thermally oxidized to form thermal oxide film 109 .
  • an ion introduction mask (not shown) having a predetermined pattern is formed on the thermal oxide film 109 .
  • the iontophoresis mask has a plurality of openings exposing regions where a plurality of termination regions 59 are to be formed.
  • p-type impurities are introduced into semiconductor substrate 37 through an ion introduction mask.
  • a plurality of termination regions 59 field limit regions 61 in FIG. 9A
  • the ion introduction mask and thermal oxide film 109 are removed.
  • an FET structure 41 is formed in the element formation region 20.
  • a hard mask eg, a CVD oxide such as a deposited oxide
  • the hard mask has a plurality of openings that expose regions where gate trenches 43 and emitter trenches 52 are to be formed, respectively. Unnecessary portions of the semiconductor substrate 37 are then removed by etching through the hard mask. As a result, gate trenches 43 and emitter trenches 52 are formed in the element formation region 20 .
  • the hard mask is then removed.
  • a gate insulating layer 44, an emitter insulating layer 53 and a first surface insulating film 55 are formed.
  • the gate insulating layer 44, the emitter insulating layer 53 and the first surface insulating film 55 may be formed by CVD or thermal oxidation.
  • a gate electrode layer 45, an emitter potential electrode layer 54, a gate lead-out electrode layer 56 and an emitter lead-out electrode layer 57 are formed.
  • Gate electrode layer 45 and emitter potential electrode layer 54 include conductive polysilicon.
  • Gate electrode layer 45, emitter potential electrode layer 54, gate lead-out electrode layer 56 and emitter lead-out electrode layer 57 may be formed by the CVD method.
  • a second surface insulating film 58 is formed on the surfaces of the gate electrode layer 45 and the emitter potential electrode layer 54 by, for example, thermal oxidation treatment, and a third surface insulating film 64 is formed on the first main surface 17 of the semiconductor substrate 37 . It is formed.
  • a plurality of n + type carrier storage regions 48 are then formed.
  • an ion implantation mask (not shown) having a predetermined pattern is formed on the first major surface 17 .
  • the iontophoresis mask has a plurality of openings exposing respective regions where a plurality of carrier storage regions 48 are to be formed.
  • n-type impurities are introduced into semiconductor substrate 37 through an ion introduction mask.
  • a plurality of carrier storage regions 48 are then formed by thermal diffusion of n-type impurities. The iontophoresis mask is then removed.
  • a plurality of p-type body regions 46 are formed.
  • an ion implantation mask (not shown) having a predetermined pattern is formed on the first major surface 17 .
  • the iontophoresis mask has a plurality of openings exposing regions where a plurality of body regions 46 are to be formed.
  • p-type impurities are introduced into semiconductor substrate 37 through an ion introduction mask.
  • a plurality of body regions 46 are then formed by thermal diffusion of p-type impurities.
  • the iontophoresis mask is then removed.
  • a plurality of n + -type emitter regions 47 are formed.
  • an ion implantation mask (not shown) having a predetermined pattern is formed on the first major surface 17 .
  • the iontophoresis mask has a plurality of openings exposing regions where a plurality of emitter regions 47 are to be formed.
  • n-type impurities are introduced into semiconductor substrate 37 through an ion introduction mask.
  • a plurality of emitter regions 47 are formed by thermal diffusion of n-type impurities. The iontophoretic mask is then removed.
  • a first layer 86 of interlayer insulating layer 66 is formed to cover first main surface 17 .
  • the first layer 86 may be formed by a CVD method.
  • the first layer 86 may have a thickness of 3000 ⁇ or more and 20000 ⁇ or less, for example.
  • a plurality of contact trenches 49 and a plurality of lower contact holes 89 are formed in first layer 86.
  • a plurality of p + -type contact regions 50 and contact regions 91 are formed.
  • p-type impurities are introduced into semiconductor substrate 37 through contact trenches 49 and lower contact holes 89 through an ion introduction mask (not shown) having a predetermined pattern.
  • a barrier layer 94 and a barrier layer 97 are formed by sputtering, for example.
  • tungsten is deposited by, eg, CVD to form a plug base electrode layer (not shown) covering the entire first main surface 17 .
  • unnecessary portions of the plug base electrode layer are removed.
  • An unnecessary portion of the plug base electrode layer may be removed by an etching method (etchback). Unnecessary portions of the plug base electrode layer are removed until the first layer 86 is exposed. Thereby, contact plugs 95 and contact plugs 98 are formed.
  • the first electrode layer 107 is a conductive layer that serves as a base for the sealing conductive layer 83, the contact portion 84 (second embedded portion 93) of the field plate electrode 24, the emitter terminal electrode 11, and the like.
  • the sealing conductive layer 83 and the second embedded portion 93 are formed in the outer region 21 by forming and patterning the first electrode layer 107 .
  • the lower portion of emitter terminal electrode 11 is formed.
  • the first electrode layer 107 is made of an aluminum-based metal.
  • the first electrode layer 107 may contain at least one of aluminum, copper, an aluminum-silicon-copper alloy, an aluminum-silicon alloy, and an aluminum-copper alloy.
  • the first electrode layer 107 may be formed by a sputtering method.
  • first layer 86 is formed so that second layer 87 of interlayer insulating layer 66 covers sealing conductive layer 83, second embedded portion 93 and emitter terminal electrode 11.
  • the second layer 87 may be formed by CVD.
  • the second layer 87 may have a thickness of 1000 ⁇ or more and 10000 ⁇ or less, for example. At this point, both the element formation region 20 and the outer region 21 are covered with the second layer 87. As shown in FIG.
  • the second layer 87 is selectively removed by, for example, an etching method.
  • an upper contact hole 90 is formed and the emitter terminal electrode 11 is exposed in the element forming region 20.
  • the contact portion 84 has a projecting portion 100 and is formed wider than the design opening width of the upper contact hole 90 . Therefore, even if the opening position of the upper contact hole 90 is slightly shifted in the lateral direction, the contact portion 84 can be exposed.
  • the second electrode layer 108 is a conductive layer that serves as the base of the surface layer portion 85 of the field plate electrode 24, the emitter terminal electrode 11, and the like.
  • the surface layer portion 85 is formed in the outer region 21 by forming and patterning the second electrode layer 108 .
  • the upper portion of the emitter terminal electrode 11 is formed, so that the emitter terminal electrode 11 is thickened.
  • the second electrode layer 108 is made of an aluminum-based metal. More specifically, the second electrode layer 108 may contain at least one of aluminum, copper, aluminum-silicon-copper alloy, aluminum-silicon alloy, and aluminum-copper alloy. Alternatively, the second electrode layer 108 may be formed by a sputtering method. Thereby, the surface electrode 23 is formed.
  • a protective layer 80 is formed on the interlayer insulating layer 66 so as to cover the surface electrodes 23.
  • a material for the protective layer 80 for example, a photosensitive resin liquid made of polyimide
  • a photosensitive resin liquid made of polyimide is sprayed onto the semiconductor substrate 37 from above the interlayer insulating layer 66 to form the photosensitive resin protective layer 80. be done.
  • an opening 81 see FIG. 3 that exposes the emitter terminal electrode 11 is formed.
  • the thinning step includes thinning the semiconductor substrate 37 by a grinding method for the second main surface 18 .
  • the grinding method may be a CMP (Chemical Mechanical Polishing) method.
  • the thinning step may include a step of thinning the semiconductor substrate 37 by an etching method for the second main surface 18 instead of the grinding method.
  • the etching method may be a wet etching method.
  • an n-type buffer layer 39 is formed on the surface layer portion of the second main surface 18 .
  • n-type impurities are introduced into the entire second main surface 18 of the semiconductor substrate 37 .
  • an n-type buffer layer 39 is formed.
  • a p + -type collector region 40 is formed in the surface layer portion of the second main surface 18 .
  • p-type impurities are introduced into the entire second main surface 18 of the semiconductor substrate 37 .
  • a collector region 40 is formed.
  • a collector terminal electrode 13 is formed on the second main surface 18 .
  • the collector terminal electrode 13 may be formed by a sputtering method. After that, the semiconductor substrate 37 is cut along the scribe area 22 of each device formation area to cut out the element chips 10 (semiconductor chips 16).
  • each element chip 10 is joined to the metal plate 6 , and the lead terminal 9 is connected to the emitter terminal electrode 11 and the gate terminal electrode 12 by the conductor 15 . Then, by sealing the element chip 10 with the package body 2, the semiconductor device 1 shown in FIG. 1 is obtained.
  • 18A and 18B are schematic cross-sectional views of the outer region 21 and the device formation region 20 of the device chip 10, respectively.
  • 18A and 18B are diagrams corresponding to FIGS. 4A and 4B described above, respectively.
  • 18A and 18B show a second embodiment of the breakdown voltage drop prevention structure of the element chip 10.
  • FIG. 4A and 4B, and descriptions of components common to FIGS. 4A and 4B are made by using the same reference numerals in FIGS. 18A and 18B as in FIGS. omitted.
  • the contact portion 84 of the field plate electrode 24 is formed of a single conductive material integrally embedded in the first layer 86 and the second layer 87 of the interlayer insulating layer 66. It has an embedded portion 110 . Also, the emitter plug electrode 111 and the emitter terminal electrode 11 are formed integrally with a single conductive material. This point is different from the element chip 10 of FIGS. 4A and 4B having the contact portion 84 including the first embedded portion 92 and the second embedded portion 93 and the emitter plug electrode 96 including the contact plug 98 (tungsten plug). .
  • the embedded portion 110 and the emitter plug electrode 111 are made of an aluminum-based metal. More specifically, the embedded portion 110 and the emitter plug electrode 111 may contain at least one of aluminum, copper, aluminum-silicon-copper alloy, aluminum-silicon alloy, and aluminum-copper alloy.
  • Barrier layer 94 is interposed between embedded portion 110 and interlayer insulating layer 66 (first layer 86 in this embodiment) and first main surface 17 .
  • Buried portion 110 is connected to contact region 91 via barrier layer 94
  • barrier layer 97 is interposed between emitter plug electrode 111 and interlayer insulating layer 66 and first main surface 17 .
  • Emitter plug electrode 111 is connected to emitter region 47 and contact region 50 via barrier layer 97 .
  • [Breakdown prevention structure of element chip 10 (third embodiment)] 19A and 19B are schematic cross-sectional views of the outer region 21 and the device formation region 20 of the device chip 10, respectively.
  • 19A and 19B are diagrams corresponding to FIGS. 18A and 18B described above, respectively.
  • FIG. 18A and 18B show a third embodiment of the breakdown voltage drop prevention structure of the element chip 10.
  • FIG. 18A and 18B are described below, and descriptions of components common to FIGS. 18A and 18B are made by using the same reference numerals in FIGS. omitted.
  • the element chip 10 of FIGS. 19A and 19B differs from the element chip 10 of FIGS. 18A and 18B in that the barrier layer 94 is omitted. Thereby, the embedding portion 110 is directly connected to the field limit region 61 .
  • a diode structure 112 is formed instead of the FET structure 41 in the element formation region 20 .
  • the diode structure 112 includes a p-type anode region 113 formed on the surface layer of the first main surface 17 and an n-type cathode region 114 formed by part of the drift region 38 on the surface layer of the second main surface 18 . including.
  • the p-type impurity concentration of the anode region 113 may be 1.0 ⁇ 10 13 cm ⁇ 3 or more and 1.0 ⁇ 10 17 cm ⁇ 3 or less.
  • the n-type impurity concentration of cathode region 114 may be 1.0 ⁇ 10 13 cm ⁇ 3 or more and 1.0 ⁇ 10 15 cm ⁇ 3 or less.
  • Crystal defects 115 may be formed in the cathode region 114 by, for example, diffusion of heavy metals (eg, Au, Pt, etc.), electron beam irradiation, or the like.
  • the diode structure 112 may be configured as a fast recovery diode (fast diode) with a relatively small reverse recovery time (trr).
  • the surface electrode 23 may include the anode terminal electrode 116 in the element formation region 20 .
  • the anode terminal electrode 116 is made of an aluminum-based metal. More specifically, anode terminal electrode 116 may include at least one of aluminum, copper, an aluminum-silicon-copper alloy, an aluminum-silicon alloy, and an aluminum-copper alloy.
  • Anode terminal electrode 116 includes contact portion 117 embedded in first contact hole 71 , and is electrically connected to anode region 113 by direct contact of contact portion 117 with anode region 113 .
  • the element formation region 20 also includes an n + -type contact region 118 formed in the surface layer portion of the second main surface 18 of the semiconductor chip 16 .
  • Contact region 118 is exposed from second main surface 18 .
  • the contact region 118 may be formed over the entire surface of the semiconductor chip 16 on the surface layer of the second main surface 18 .
  • the n-type impurity concentration of the contact region 118 may be 1.0 ⁇ 10 19 cm ⁇ 3 or more and 1.0 ⁇ 10 20 cm ⁇ 3 or less.
  • the second main surface 18 of the semiconductor chip 16 includes a cathode terminal electrode 119 as an example of a back surface electrode.
  • Cathode terminal electrode 119 forms ohmic contact with second main surface 18 (contact region 118).
  • Cathode terminal electrode 119 may include at least one of a Ti layer, Ni layer, Au layer, Ag layer and Al layer.
  • Cathode terminal electrode 119 may have a single layer structure including a Ti layer, Ni layer, Au layer, Ag layer, or Al layer.
  • Cathode terminal electrode 119 may have a laminated structure in which at least two of a Ti layer, Ni layer, Au layer, Ag layer and Al layer are laminated in an arbitrary manner.
  • FIGS. 4A and 4B are schematic cross-sectional views of the outer region 21 and the device formation region 20 of the device chip 10, respectively.
  • 20A and 20B are diagrams corresponding to FIGS. 4A and 4B described above, respectively.
  • 20A and 20B show a fourth embodiment of the breakdown voltage drop prevention structure of the element chip 10.
  • FIG. 21 and 22 are diagrams schematically showing planar patterns of the sealing conductive layer 83.
  • FIG. 4A and 4B are described below, and descriptions of components common to FIGS. 4A and 4B are made by using the same reference numerals in FIGS. omitted.
  • the interlayer insulating layer 66 is formed not of a laminated structure of the first layer 86 and the second layer 87 but of a single layer structure.
  • a surface electrode 23 and a sealing conductive layer 83 are both formed on the surface of the interlayer insulating layer 66 .
  • a sealing conductive layer 83 is disposed in the space 82 between adjacent field plate electrodes 24 .
  • the sealing conductive layer 83 is arranged directly above the field insulating layer 62 with respect to the thickness direction (longitudinal direction) of the interlayer insulating layer 66, and the semiconductor chip 16 with the interlayer insulating layer 66 and the field insulating layer 62 interposed therebetween. (drift region 38 in this embodiment).
  • FIG. 21 and 22 show only the components necessary for explaining the planar pattern of the sealing conductive layer 83 for clarity. 21 and 22, the field plate electrode 24 is hatched.
  • spaces 82 between the plurality of field plate electrodes 24 are formed in a line shape in plan view. More specifically, since each field plate electrode 24 is endless surrounding the element forming region 20 , the space 82 is also endless surrounding the element forming region 20 .
  • the sealing conductive layer 83 is formed in a line shape extending along the line-shaped space 82 in plan view.
  • the sealing conductive layer 83 may be formed in an endless shape in plan view and may overlap the endless space 82 over the entire circumference.
  • a plurality of line-shaped (linear or curved) sealing conductive layers 83 may be arranged at intervals along the circumferential direction of the space 82 .
  • the sealing conductive layer 83 is arranged in a region sandwiched between the inner peripheral edge portion 120 and the outer peripheral edge portion 121 of the field plate electrode 24 in plan view. Sealing conductive layer 83 is spaced from both inner peripheral edge 120 and outer peripheral edge 121 . Thereby, the sealing conductive layer 83 has a width narrower than that of the space 82 .
  • a sealing conductive layer 83 is placed in the space 82 .
  • This can prevent moisture (OH ⁇ , H + , etc.) from entering the interlayer insulating layer 66 through the space 82 .
  • moisture OH ⁇ , H + , etc.
  • it is possible to suppress variations in breakdown voltage due to polarization caused by moisture or the like, and to suppress a decrease in breakdown voltage in the vicinity of the field limit region 61 .
  • 23A and 23B are schematic cross-sectional views of the outer region 21 and the device formation region 20 of the device chip 10, respectively.
  • 23A and 23B are diagrams corresponding to FIGS.
  • FIG. 20A and 20B show a fifth embodiment of the breakdown voltage drop prevention structure of the element chip 10.
  • FIG. 20A and 20B, and descriptions of components common to FIGS. 20A and 20B are made by using the same reference numerals in FIGS. omitted.
  • the contact portion 84 of the field plate electrode 24 has an embedded portion 122 integrally embedded in the interlayer insulating layer 66 and made of a single conductive material. Also, the emitter plug electrode 123 is integrally formed with the emitter terminal electrode 11 from a single conductive material. This point is different from the element chip 10 of FIGS. 20A and 20B having the contact portion 84 including the contact plug 95 (tungsten plug) and the emitter plug electrode 96 including the contact plug 98 (tungsten plug).
  • the embedded portion 122 and the emitter plug electrode 123 are made of an aluminum-based metal. More specifically, embedded portion 122 and emitter plug electrode 123 may contain at least one of aluminum, copper, aluminum-silicon-copper alloy, aluminum-silicon alloy, and aluminum-copper alloy.
  • Barrier layer 94 is interposed between embedded portion 122 and interlayer insulating layer 66 and first main surface 17 .
  • Buried portion 122 is connected to contact region 91 via barrier layer 94
  • barrier layer 97 is interposed between emitter plug electrode 123 and interlayer insulating layer 66 and first main surface 17 .
  • Emitter plug electrode 123 is connected to emitter region 47 and contact region 50 via barrier layer 97 .
  • 24A and 24B are schematic cross-sectional views of the outer region 21 and the device formation region 20 of the device chip 10, respectively.
  • 24A and 24B are diagrams corresponding to FIGS. 23A and 23B described above, respectively.
  • FIG. 24A and 24B show a sixth embodiment of the breakdown voltage drop preventing structure of the element chip 10.
  • FIG. 23A and 23B are described below, and descriptions of components common to FIGS. 23A and 23B are made by using the same reference numerals in FIGS. omitted.
  • the element chip 10 of FIGS. 24A and 24B differs from the element chip 10 of FIGS. 23A and 23B in that the barrier layer 94 is omitted. Thereby, the embedded portion 122 is directly connected to the field limit region 61 .
  • a diode structure 124 is formed instead of the FET structure 41 in the element forming region 20 .
  • the diode structure 124 includes a p-type anode region 125 formed on the surface layer of the first principal surface 17 and an n-type cathode region 126 formed by part of the drift region 38 on the surface layer of the second principal surface 18 . including.
  • the p-type impurity concentration of the anode region 125 may be 1.0 ⁇ 10 13 cm ⁇ 3 or more and 1.0 ⁇ 10 16 cm ⁇ 3 or less.
  • the n-type impurity concentration of the cathode region 126 may be 1.0 ⁇ 10 13 cm ⁇ 3 or more and 1.0 ⁇ 10 15 cm ⁇ 3 or less.
  • Crystal defects 127 may be formed in the cathode region 126 by, for example, diffusion of heavy metals (eg, Au, Pt, etc.), electron beam irradiation, or the like.
  • the diode structure 124 may be configured as a fast recovery diode (fast diode) with a relatively small reverse recovery time (trr).
  • the surface electrode 23 may include the anode terminal electrode 128 in the element formation region 20 .
  • the anode terminal electrode 128 is made of an aluminum-based metal. More specifically, anode terminal electrode 128 may include at least one of aluminum, copper, an aluminum-silicon-copper alloy, an aluminum-silicon alloy, and an aluminum-copper alloy.
  • Anode terminal electrode 128 includes contact portion 129 embedded in first contact hole 71 , and is electrically connected to anode region 125 by direct contact of contact portion 129 with anode region 125 .
  • the element formation region 20 also includes an n + -type contact region 130 formed in the surface layer portion of the second main surface 18 of the semiconductor chip 16 .
  • Contact region 130 is exposed from second main surface 18 .
  • the contact region 130 may be formed over the entire surface of the semiconductor chip 16 on the surface layer of the second main surface 18 .
  • the n-type impurity concentration of the contact region 130 may be 1.0 ⁇ 10 19 cm ⁇ 3 or more and 1.0 ⁇ 10 20 cm ⁇ 3 or less.
  • the second main surface 18 of the semiconductor chip 16 includes a cathode terminal electrode 131 as an example of a back surface electrode.
  • the cathode terminal electrode 131 forms an ohmic contact with the second main surface 18 (contact region 130).
  • Cathode terminal electrode 131 may include at least one of a Ti layer, Ni layer, Au layer, Ag layer and Al layer.
  • the cathode terminal electrode 131 may have a single layer structure including a Ti layer, Ni layer, Au layer, Ag layer, or Al layer.
  • Cathode terminal electrode 131 may have a laminated structure in which at least two of a Ti layer, a Ni layer, an Au layer, an Ag layer and an Al layer are laminated in an arbitrary manner.
  • FIG. 25 is a schematic cross-sectional view of the outer region 21 of the element chip 10.
  • FIG. FIG. 25 shows a seventh embodiment of the breakdown voltage drop prevention structure of the element chip 10. As shown in FIG. 4A and 4B will be described below, and the description of components common to FIGS. 4A and 4B will be omitted by using the same reference numerals as in FIGS. 4A and 4B in FIG.
  • the sealing conductive layer 133 is formed to face the space 134 between the emitter potential electrodes 132 .
  • Emitter potential electrode 132 is connected to RESURF layer 60 in termination region 59 . Therefore, the sealing conductive layer 133 can suppress a decrease in breakdown voltage in the vicinity of the RESURF layer 60 .
  • 26A and 26B are schematic cross-sectional views of the outer region 21 and the device formation region 20 of the device chip 10, respectively. 26A and 26B are diagrams corresponding to FIGS.
  • 26A and 26B show an eighth embodiment of the breakdown voltage drop prevention structure of the element chip 10.
  • FIG. 4A and 4B, and descriptions of components common to FIGS. 4A and 4B are made by using the same reference numerals in FIGS. 26A and 26B as in FIGS. omitted.
  • the FET structure 41 is configured as a MOSFET structure instead of an IGBT structure.
  • the emitter region 47 may be the n + -type source region 135 and the collector region 40 may be the n + -type drain region 136 .
  • the emitter terminal electrode 11 may be the source terminal electrode 137 and the collector terminal electrode 13 may be the drain terminal electrode 138 .
  • FIG. 27 is a schematic external view of a semiconductor module 200 according to an embodiment of the present disclosure.
  • a semiconductor module 201 incorporates one or more semiconductor chips 202 .
  • the semiconductor module 201 in this form has a structure in which two semiconductor chips 202 are incorporated.
  • the two semiconductor chips 202 are hereinafter referred to as a first semiconductor chip 202A and a second semiconductor chip 202B, respectively.
  • the element chip 10 described above may be applied to the first semiconductor chip 202A and the second semiconductor chip 202B.
  • semiconductor module 201 includes a housing 203 that accommodates first semiconductor chip 202A and second semiconductor chip 202B.
  • Housing 203 includes resin case 204 and support substrate 205 .
  • the support substrate 205 is a substrate that supports the first semiconductor chip 202A and the second semiconductor chip 202B.
  • the resin case 204 includes a bottom wall 206 and side walls 207A, 207B, 207C, 207D.
  • the bottom wall 206 is formed in a square shape (rectangular shape in this embodiment) in a plan view seen from the normal direction.
  • a through hole 208 is formed in the bottom wall 206 .
  • a through hole 208 is formed in the bottom wall 206 in a region spaced from the periphery to the inner region.
  • the through-hole 208 is formed in a square shape (rectangular shape in this embodiment) in plan view.
  • the side walls 207A to 207D are erected from the periphery of the bottom wall 206 toward the side opposite to the bottom wall 206. As shown in FIG. Sidewalls 207A-207D define an opening 209 on the side opposite bottom wall 206 .
  • Side walls 207A-207D define an interior space 210 with bottom wall 206. As shown in FIG.
  • the side walls 207A and 207C extend along the width direction of the bottom wall 206. Side wall 207A and side wall 207C face each other in the longitudinal direction of bottom wall 206 . Side wall 207B and side wall 207D extend along the longitudinal direction of bottom wall 206 . Side wall 207B and side wall 207D face each other in the lateral direction of bottom wall 206 .
  • the internal space 210 is closed by a lid member or sealing member (for example, sealing gel) (not shown).
  • the cover member is bolted to the bolt insertion holes 211, 212, 213, 214 with bolts.
  • the resin case 204 includes a plurality of terminal support portions 215, 216, 217, 218.
  • the plurality of terminal supports 215-218 includes a first terminal support 215, a second terminal support 216, a third terminal support 217 and a fourth terminal support 218 in this embodiment.
  • the first terminal support portion 215 and the second terminal support portion 216 are attached to the outer wall of the side wall 207A.
  • the first terminal support portion 215 and the second terminal support portion 216 are formed integrally with the outer wall of the side wall 207A in this embodiment.
  • the first terminal support portion 215 and the second terminal support portion 216 are formed with a space therebetween in the lateral direction.
  • the first terminal support portion 215 and the second terminal support portion 216 are each formed in a block shape.
  • the first terminal support portion 215 and the second terminal support portion 216 protrude longitudinally outward from the outer wall of the side wall 207A.
  • the third terminal support portion 217 and the fourth terminal support portion 218 are attached to the side wall 207C.
  • the third terminal support portion 217 and the fourth terminal support portion 218 are formed integrally with the outer wall of the side wall 207C in this embodiment.
  • the third terminal support portion 217 and the fourth terminal support portion 218 are formed with a space therebetween in the lateral direction.
  • the third terminal support portion 217 and the fourth terminal support portion 218 are each formed in a block shape.
  • the third terminal support portion 217 and the fourth terminal support portion 218 protrude longitudinally outward from the side wall 207C.
  • the first terminal support portion 215 , the second terminal support portion 216 , the third terminal support portion 217 and the fourth terminal support portion 218 each have a support wall 219 .
  • Each support wall 219 is located in a region closer to the opening 209 than the bottom wall 206 .
  • Each support wall 219 is formed in a square shape in plan view.
  • a first bolt insertion hole 221 is formed in a region between the first terminal support portion 215 and the second terminal support portion 216 .
  • a second bolt insertion hole 222 is formed in a region between the third terminal support portion 217 and the fourth terminal support portion 218 .
  • the support substrate 205 includes a heat sink 225 , an insulating material 226 and a circuit section 227 .
  • the support substrate 205 is attached to the outer surface of the resin case 204 so that the circuit portion 227 is exposed from the through hole 208 of the bottom wall 206 .
  • the support substrate 205 may be attached to the outer surface of the resin case 204 by bonding the heat sink 225 to the outer surface of the resin case 204 .
  • the radiator plate 225 may be a metal plate.
  • the radiator plate 225 may be an insulating plate covered with a metal film.
  • the heat sink 225 is formed in a quadrangular shape (rectangular shape in this embodiment) when viewed from the normal direction.
  • the insulating material 226 is formed on the radiator plate 225 .
  • Insulator 226 may be a mounting substrate that includes an insulating material.
  • the insulating material 226 may be an insulating film formed on the heat sink 225 in the form of a film.
  • the circuit section 227 is formed on the radiator plate 225 with an insulating material 226 interposed therebetween.
  • Circuit section 227 includes a plurality of wirings 231, 232, 233, first semiconductor chip 202A and second semiconductor chip 202B.
  • the wirings 231 to 233 include a first collector wiring 231, a second collector wiring 232 and an emitter wiring 233 in this form.
  • the first collector wiring 231 is formed in a plate shape or a film shape.
  • the first collector wiring 231 is formed in a square shape in plan view.
  • the first collector wiring 231 is arranged in a region on one side in the longitudinal direction (side wall 207A) and one side in the width direction (side wall 207D) of the radiator plate 225 .
  • the second collector wiring 232 is formed in a plate shape or a film shape.
  • the second collector wiring 232 is formed in a square shape in plan view.
  • the second collector wiring 232 is spaced apart from the first collector wiring 231 and arranged on the other longitudinal side (side wall 207C side) and one widthwise side (side wall 207D side) of the radiator plate 225 .
  • the emitter wiring 233 is formed in a plate shape or a film shape.
  • the emitter wiring 233 is formed in a square shape in plan view.
  • the emitter wiring 233 is formed in a rectangular shape extending along the longitudinal direction of the radiator plate 225 in this embodiment.
  • the emitter wiring 233 is spaced apart from the first collector wiring 231 and the second collector wiring 232 and arranged in a region of the radiator plate 225 on the other side in the short direction (side wall 207B side).
  • the first semiconductor chip 202A is arranged on the first collector wiring 231 with the collector terminal electrode 13 facing the heat sink.
  • the collector terminal electrode 13 of the first semiconductor chip 202A is joined to the first collector wiring 231 via a conductive joint material.
  • the collector terminal electrode 13 of the first semiconductor chip 202A is electrically connected to the first collector wiring 231.
  • the conductive bonding material may contain solder or conductive paste.
  • the second semiconductor chip 202B is arranged on the second collector wiring 232 with the collector terminal electrode 13 facing the heat sink.
  • the collector terminal electrode 13 of the second semiconductor chip 202B is bonded to the second collector wiring 232 via a conductive bonding material.
  • the collector terminal electrode 13 of the second semiconductor chip 202B is electrically connected to the second collector wiring 232.
  • the conductive bonding material may contain solder or conductive paste.
  • the semiconductor module 201 includes a plurality of terminals 234,235,236,237.
  • the plurality of terminals 234 - 237 includes a collector terminal 234 , a first emitter terminal 235 , a common terminal 236 and a second emitter terminal 237 .
  • the collector terminal 234 is arranged on the first terminal support portion 215 .
  • the collector terminal 234 is electrically connected to the first collector wiring 231 .
  • Collector terminal 234 includes first region 238 and second region 239 .
  • a first region 238 of the collector terminal 234 is located outside the interior space 210 .
  • a second region 239 of collector terminal 234 is located within interior space 210 .
  • a first region 238 of the collector terminal 234 is supported by the support wall 219 of the first terminal support portion 215 .
  • a second region 239 of the collector terminal 234 extends from the first region 238 through the side wall 207A into the internal space 210 .
  • a second region 239 of the collector terminal 234 is electrically connected to the first collector wiring 231 .
  • the first emitter terminal 235 is arranged on the second terminal support portion 216 .
  • the first emitter terminal 235 is electrically connected to the emitter wiring 233 .
  • First emitter terminal 235 includes first region 240 and second region 241 .
  • a first region 240 of the first emitter terminal 235 is located outside the interior space 210 .
  • a second region 241 of the first emitter terminal 235 is located within the interior space 210 .
  • a first region 240 of the first emitter terminal 235 is supported by the support wall 219 of the second terminal support portion 216 .
  • a second region 241 of the first emitter terminal 235 extends from the first region 240 through the side wall 207A into the internal space 210 .
  • a second region 241 of the first emitter terminal 235 is electrically connected to the emitter wiring 233 .
  • the common terminal 236 is arranged on the third terminal support portion 217 .
  • Common terminal 236 is electrically connected to second collector wiring 232 .
  • Common terminal 236 includes first region 242 and second region 243 .
  • a first region 242 of the common terminal 236 is located outside the interior space 210 .
  • a second region 243 of the common terminal 236 is located within the interior space 210 .
  • the first region 242 of the common terminal 236 is supported by the support wall 219 of the second terminal support portion 216.
  • a second region 243 of the common terminal 236 extends from the first region 240 through the side wall 207C into the internal space 210 .
  • a second region 243 of the common terminal 236 is electrically connected to the second collector wiring 232 .
  • the second emitter terminal 237 is arranged on the fourth terminal support portion 218 .
  • the second emitter terminal 237 is electrically connected to the emitter wiring 233 .
  • Second emitter terminal 237 includes first region 244 and second region 245 .
  • a first region 244 of the second emitter terminal 237 is located outside the interior space 210 .
  • a second region 245 of the second emitter terminal 237 is located within the interior space 210 .
  • the first region 244 of the second emitter terminal 237 is supported by the support wall 219 of the fourth terminal support portion 218.
  • a second region 245 of the second emitter terminal 237 extends from the first region 244 through the side wall 207C into the internal space 210 .
  • a second region 245 of the second emitter terminal 237 is electrically connected to the emitter wiring 233 .
  • the semiconductor module 201 includes a plurality (six in this embodiment) of sidewall terminals 246A to 246H.
  • a plurality of sidewall terminals 246A-246H are spaced apart along sidewall 207D in interior space 210. As shown in FIG.
  • the plurality of side wall terminals 246A-246H each include an internal connection portion 247 and an external connection portion 248.
  • An internal connection 247 is located on the bottom wall 206 .
  • the external connection portion 248 extends linearly from the internal connection portion 247 along the side wall 207 ⁇ /b>D and is drawn out of the internal space 210 .
  • the plurality of sidewall terminals 246A-246H includes three sidewall terminals 246A-246D for the first semiconductor chip 202A and three sidewall terminals 246E-246H for the second semiconductor chip 202B.
  • the side wall terminals 246A to 246D are opposed to the first collector wiring 231 along the lateral direction.
  • the sidewall terminal 246A is formed as a gate terminal connected to the gate terminal electrode 12 of the first semiconductor chip 202A.
  • the sidewall terminals 246B to 246D are respectively formed as terminals connected to, for example, current detection terminal electrodes (not shown) of the first semiconductor chip 202A. At least one of sidewall terminals 246B-246D may be an open terminal.
  • the side wall terminals 246E to 246H are opposed to the second collector wiring 232 along the lateral direction.
  • the sidewall terminal 246E is formed as a gate terminal connected to the gate terminal electrode 12 of the second semiconductor chip 202B.
  • the sidewall terminals 246F to 246H are formed as terminals to be connected to terminal electrodes (not shown) for current detection of the second semiconductor chip 202B. At least one of sidewall terminals 246F-246H may be an open terminal.
  • the semiconductor module 201 includes a plurality of conductors 249A-249J.
  • the plurality of conductors 249A-249J may each include at least one of gold, silver, copper and aluminum.
  • Conductors 249A-249J may each include a bonding wire.
  • Conductors 249A-249J may each include a conductive plate.
  • the plurality of conductors 249A to 249J includes a first conductor 249A, a second conductor 249B, a third conductor 249C, a fourth conductor 249D, a fifth conductor 249E, a sixth conductor 249F, a seventh conductor 249G, an eighth conductor 249H, and a ninth conductor 249H. It includes conductor 249I and tenth conductor 249J.
  • the first conductor 249A connects the collector terminal 234 and the first collector wiring 231 .
  • a second conductor 249B connects the first emitter terminal 235 and the emitter wiring 233 .
  • a third conductor 249C connects the common terminal 236 and the second collector wiring 232 .
  • a fourth conductor 249D connects the second emitter terminal 237 and the emitter wiring 233 .
  • the fifth conducting wire 249E connects the emitter terminal electrode 11 and the second collector wiring 232 of the first semiconductor chip 202A.
  • the sixth conducting wire 249F connects the emitter terminal electrode 11 and the emitter wiring 233 of the second semiconductor chip 202B.
  • the seventh conducting wire 249G connects the gate terminal electrode 12 and the side wall terminal 246A of the first semiconductor chip 202A.
  • the eighth conducting wire 249H connects the gate terminal electrode 12 and the side wall terminal 246E of the second semiconductor chip 202B.
  • the ninth conducting wire 249I connects a terminal electrode (not shown) for current detection of the first semiconductor chip 202A and the side wall terminals 246B to 246D.
  • the tenth conducting wire 249J connects a terminal electrode (not shown) for current detection of the second semiconductor chip 202B and the side wall terminals 246F to 246H.
  • FIG. 28 is a circuit diagram showing the electrical structure of the semiconductor module 201 of FIG.
  • semiconductor module 201 includes half bridge circuit 250 .
  • Half bridge circuit 250 includes first semiconductor chip 202A and second semiconductor chip 202B.
  • the first semiconductor chip 202A constitutes the high voltage side arm of the half bridge circuit 250.
  • the second semiconductor chip 202B constitutes the low voltage side arm of the half bridge circuit 250. As shown in FIG.
  • a gate terminal (side wall terminal 246A) is connected to the gate terminal electrode 12 of the first semiconductor chip 202A.
  • a collector terminal 234 is connected to the collector terminal electrode 13 of the first semiconductor chip 202A.
  • the collector terminal electrode 13 of the second semiconductor chip 202B is connected to the emitter terminal electrode 11 of the first semiconductor chip 202A.
  • a common terminal 236 is connected to the connecting portion of the emitter terminal electrode 11 of the first semiconductor chip 202A and the collector terminal electrode 13 of the second semiconductor chip 202B.
  • a gate terminal (side wall terminal 246D) is connected to the gate terminal electrode 12 of the second semiconductor chip 202B.
  • a first emitter terminal 235 (second emitter terminal 237) is connected to the emitter terminal electrode 11 of the second semiconductor chip 202B.
  • a gate driver IC or the like may be connected to the gate terminal electrode 12 of the first semiconductor chip 202A via a gate terminal (side wall terminal 246A).
  • a gate driver IC or the like may be connected to the gate terminal electrode 12 of the second semiconductor chip 202B through a gate terminal (side wall terminal 246D).
  • the semiconductor module 201 may be an inverter module that drives any one of the U, V and W phases in a three-phase motor having U, V and W phases.
  • An inverter device for driving a three-phase motor may be configured by three semiconductor modules 201 corresponding to the U-phase, V-phase and W-phase of the three-phase motor.
  • a DC power supply is connected to the collector terminal 234 and the first emitter terminal 235 (second emitter terminal 237) of each semiconductor module 201 . Also, one of the U-phase, V-phase and W-phase of the three-phase motor is connected as a load to the common terminal 236 of each semiconductor module 201 .
  • the first semiconductor chip 202A and the second semiconductor chip 202B are driven and controlled according to a predetermined switching pattern.
  • the DC voltage is converted into a three-phase AC voltage, and the three-phase motor is sinusoidally driven.
  • the p-type portion may be formed to be n-type
  • the n-type portion may be formed to be p-type
  • a p-type impurity region formed by introducing a p-type impurity into the semiconductor chip 16 is taken as an example.
  • a buried conductive layer (conductive polysilicon or the like) embedded in the trench via an insulating layer may be formed as the field limit region 61 .
  • a p-type impurity region may be formed along the inner surface of the trench.
  • the element chip 10 having the MOSFET structure as the FET structure may be applied as the first semiconductor chip 202A and the second semiconductor chip 202B mounted on the semiconductor module 201 of FIG.
  • a semiconductor device (1) comprising:
  • said second conductive layer (83, 133) comprises a buried conductive layer embedded within said interlayer insulating layer (66); Supplementary Note 1, wherein the embedded conductive layer faces the spaces (82, 134) between the plurality of first conductive layers (23, 24, 34, 132) in the thickness direction of the interlayer insulating layer (66).
  • the first conductive layers (23, 24, 34, 132) are provided in contact holes (75) formed in the interlayer insulating layer (66) and connected to the breakdown voltage holding structures (59, 60, 61).
  • a first lead-out portion (101) led out from an intermediate portion of the contact portion (84) toward the embedded conductive layer in the depth direction of the contact hole (75);
  • the distance (D2) from the peripheral surface of the contact portion (84) to the lateral end of the second lead portion (102) is equal to the distance from the peripheral surface of the contact portion (84) to the distance of the first lead portion (101).
  • One and the other of the adjacent first conductive layers (23, 24, 34, 132) respectively have the second lead portions (102), and the one and the other of the second lead portions (102) are the interlayer insulating layers. facing a second distance (W2) on the surface of the layer (66),
  • the first distance (W1) between the first lead portion (101) of the one first conductive layer (23, 24, 34, 132) and the buried conductive layer is equal to the one second lead portion (102).
  • the semiconductor device (1) according to appendix 1-2-1 or appendix 1-2-2, which is narrower than the second distance (W2) between the second lead-out portion (102) and the other second lead-out portion (102).
  • the interlayer insulating layer (66) is formed on a first portion (86) having a first thickness (T1) closer to the semiconductor chip (16) than the embedded conductive layer, and on the first portion (86). and a second portion (87) covering the embedded conductive layer and having a second thickness (T2) less than the first thickness (T1). (1).
  • the first conductive layer (23, 24, 34, 132) comprises a surface layer portion (85) formed on the interlayer insulating layer (66) and the interlayer insulating layer (66) from the surface layer portion (85). a contact portion (84) connected to the breakdown voltage holding structure (59, 60, 61) through the Supplementary Note 1, wherein the embedded conductive layer faces a part of the surface layer portion (85) of the first conductive layer (23, 24, 34, 132) in the thickness direction of the interlayer insulating layer (66). -2, the semiconductor device (1).
  • the first conductive layers (23, 24, 34, 132) are provided in contact holes (75) formed in the interlayer insulating layer (66) and connected to the breakdown voltage holding structures (59, 60, 61). and an overlap portion (102) drawn out from the contact portion (84) onto the surface of the interlayer insulating layer (66) and overlapping the embedded conductive layer in plan view. -2, the semiconductor device (1).
  • the interlayer insulating layer (66) is formed on a first portion (86) closer to the semiconductor chip (16) than the embedded conductive layer and on the first portion (86) to cover the embedded conductive layer. a second portion (87);
  • the contact portion (84) of the first conductive layer (23, 24, 34, 132) has a protruding portion (100) selectively protruding into a region on the first portion (86) toward the buried conductive layer. ), the semiconductor device according to appendix 1-3 or appendix 1-4 (1).
  • the interlayer insulating layer (66) is formed on a first portion (86) closer to the semiconductor chip (16) than the embedded conductive layer and on the first portion (86) to cover the embedded conductive layer. a second portion (87);
  • the contact portion (84) is formed by a barrier layer (94) and a contact plug (95) embedded in the first portion (86) of the interlayer insulating layer (66) via the barrier layer (94). and a second buried portion (93) buried in the second portion (87) of the interlayer insulating layer (66) and formed of a conductive material different from that of the contact plug (95). ), the semiconductor device (1) according to any one of appendices 1-2 to 1-4.
  • the contact plug (95) comprises a tungsten plug;
  • the interlayer insulating layer (66) is formed on a first portion (86) closer to the semiconductor chip (16) than the embedded conductive layer and on the first portion (86) to cover the embedded conductive layer. a second portion (87);
  • the contact portion (84) is an embedded portion ( 110, 122) and a barrier layer (94) formed between said first portion (86) and said buried portion (110, 122). 5.
  • the semiconductor device (1) according to any one of 4.
  • the barrier layer (94) comprises a titanium-based metal
  • the interlayer insulating layer (66) is formed on a first portion (86) closer to the semiconductor chip (16) than the embedded conductive layer and on the first portion (86) to cover the embedded conductive layer. a second portion (87);
  • the contact portion (84) is formed of a single conductive material integrally embedded in the first portion (86) and the second portion (87) of the interlayer insulating layer (66),
  • a semiconductor device (1) according to any one of clauses 1-2 to 1-4, comprising buried contacts (110, 122) directly connected to structures (59, 60, 61).
  • Appendix 1-8-1 The semiconductor device (1) according to Appendix 1-8, wherein the device structure (42, 112, 124) comprises a diode structure (112, 124).
  • Appendix 1-8-2 The semiconductor device (1) according to Appendix 1-8-1, wherein the diode structure (112, 124) includes a fast recovery diode.
  • the active thickness (TA) of the interlayer insulating layer (66) in the device formation region (20) is thinner than the peripheral thickness (TC) of the interlayer insulating layer (66) in the peripheral region (21).
  • the semiconductor device (1) according to any one of 1-1 to 1-8.
  • Appendices 1-1 to 1-1 wherein a step (70) is formed on the surface of the interlayer insulating layer (66) at a boundary portion (69) between the element forming region (20) and the peripheral region (21).
  • a semiconductor device (1) according to any one of 1-9.
  • Appendix 1-11 including first output electrodes (11, 116, 128, 137) exposed from the protective layer (80) in the device formation region (20) and connected to the device structures (42, 112, 124);
  • the height from the first main surface (17) of the semiconductor chip (16) to the surface (H2) of the first conductive layers (23, 24, 34, 132) is The semiconductor according to any one of Appendixes 1-1 to 1-11, which is higher than the height (H1) from one main surface (17) to the first output electrodes (11, 116, 128, 137).
  • Device (1)
  • Spaces (82, 134) between the plurality of first conductive layers (23, 24, 34, 132) are formed in a line shape in plan view, According to any one of Appendixes 1-1 to 1-13, the second conductive layer (83, 133) is formed in a line shape extending along the line-shaped space (82, 134) in plan view. 1.
  • Spaces (82, 134) between the plurality of first conductive layers (23, 24, 34, 132) are formed in an endless ring shape surrounding the element formation region (20) in plan view,
  • the peripheral region (21) surrounds the element forming region (20) and includes an outer region (21) formed at the peripheral edge of the semiconductor chip (16).
  • a semiconductor device (1) according to any one of the preceding claims.
  • the semiconductor chip (16) includes a first conductivity type first impurity region (38) formed on the first main surface (17) side,
  • the breakdown voltage holding structure (59, 60, 61) includes a second impurity region formed by introducing a second conductivity type impurity into the first impurity region (38).
  • the semiconductor device (1) according to any one of 15.
  • the breakdown voltage holding structure (59, 60, 61) includes at least one of an FLR (Field Limiting Ring) structure (61) surrounding the element formation region (20) and a RESURF (Reduced Surface Field) layer (60). , the semiconductor device (1) according to appendix 1-16.
  • FLR Field Limiting Ring
  • RESURF Reduced Surface Field
  • the element structure (42, 112, 124) includes at least one of an IGBT (Insulated Gate Bipolar Transistor) structure, a diode structure and a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure, Appendix 1-1 to Appendix 1-17
  • IGBT Insulated Gate Bipolar Transistor
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • Appendix 1-20 The semiconductor device (1) according to any one of Appendixes 1-1 to 1-19, which is a discrete semiconductor including a sealing resin (2) for sealing the semiconductor chip (16).
  • Appendix 1-21 a resin housing (203); and a plurality of semiconductor devices (1) installed in the housing (203) and including at least one semiconductor device (1) according to any one of Appendices 1-1 to 1-19. (201).
  • Appendix 1-22 including a plurality of the breakdown voltage holding structures (59, 60, 61) spaced apart from each other;
  • the second conductive layers (83, 133) are arranged so that the portion of the interlayer insulating layer (66) straddling between the adjacent breakdown voltage holding structures (59, 60, 61) is formed on the opposite side of the semiconductor layer (16).
  • the semiconductor device (1) of Appendix 1-1 comprising an encapsulation conductive layer (83) encapsulating from.
  • a first conductivity type semiconductor layer (16) having a first main surface (17) formed with an element formation region (20) including element structures (42, 112, 124); including impurity regions of the second conductivity type formed in an outer region (21) around the element formation region (20) in the first main surface (17) of the semiconductor layer (16) and spaced apart from each other a plurality of breakdown voltage holding structures (59, 60, 61) formed; interlayer insulating layers (62, 66) formed on the first main surface (17) of the semiconductor chip (16); A surface metal (23) formed on the surfaces of the interlayer insulating layers (62, 66), passing through the interlayer insulating layers (62, 66) to the plurality of breakdown voltage holding structures (59, 60, 61).
  • the peripheral electrode metals (23, 24, 34, 132) are provided in contact holes (75) formed in the interlayer insulating layers (62, 66) and connected to the breakdown voltage holding structures (59, 60, 61). and an overlap portion (84) drawn out from the contact portion (84) onto the surface of the interlayer insulating layers (62, 66) and overlapping the sealing metal (83, 133) in plan view. 102), and the semiconductor device according to Appendix 2-1 (1).
  • a portion of the interlayer insulating layer (66) straddling between the plurality of adjacent breakdown voltage holding structures (59, 60, 61) is a thermal oxide film (62) partially buried in the first main surface (17). ) and a deposited oxide (66) on said thermal oxide,
  • the semiconductor device (1) according to any one of Appendices 2-1 to 2-3, wherein the sealing metal (83, 133) is provided on the surface of the deposited oxide film (66).

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  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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JP2008227238A (ja) * 2007-03-14 2008-09-25 Toyota Central R&D Labs Inc 半導体装置
WO2013021727A1 (ja) * 2011-08-05 2013-02-14 富士電機株式会社 半導体装置および半導体装置の製造方法
JP2013179327A (ja) * 2013-04-23 2013-09-09 Mitsubishi Electric Corp 半導体装置
WO2013140572A1 (ja) * 2012-03-22 2013-09-26 トヨタ自動車株式会社 半導体装置
JP2016225363A (ja) * 2015-05-27 2016-12-28 トヨタ自動車株式会社 半導体装置

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JP2008227238A (ja) * 2007-03-14 2008-09-25 Toyota Central R&D Labs Inc 半導体装置
WO2013021727A1 (ja) * 2011-08-05 2013-02-14 富士電機株式会社 半導体装置および半導体装置の製造方法
WO2013140572A1 (ja) * 2012-03-22 2013-09-26 トヨタ自動車株式会社 半導体装置
JP2013179327A (ja) * 2013-04-23 2013-09-09 Mitsubishi Electric Corp 半導体装置
JP2016225363A (ja) * 2015-05-27 2016-12-28 トヨタ自動車株式会社 半導体装置

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