WO2023160589A1 - 半导体激光器及其封装结构 - Google Patents

半导体激光器及其封装结构 Download PDF

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Publication number
WO2023160589A1
WO2023160589A1 PCT/CN2023/077719 CN2023077719W WO2023160589A1 WO 2023160589 A1 WO2023160589 A1 WO 2023160589A1 CN 2023077719 W CN2023077719 W CN 2023077719W WO 2023160589 A1 WO2023160589 A1 WO 2023160589A1
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WIPO (PCT)
Prior art keywords
layer
light
type semiconductor
semiconductor laser
electrode structure
Prior art date
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PCT/CN2023/077719
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English (en)
French (fr)
Inventor
钟昕展
徐子杰
吕俊亿
杨琇如
陈守龙
黄冠智
陈翰毅
Original Assignee
晶智达光电股份有限公司
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Publication of WO2023160589A1 publication Critical patent/WO2023160589A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]

Definitions

  • Embodiments of the present disclosure relate to a semiconductor laser and its packaging structure.
  • Vertical Cavity Surface Emitting Laser (Vertical Cavity Surface Emitting Laser, VCSEL) is a kind of semiconductor laser.
  • vertical cavity surface emitting laser components have gradually expanded from the Netcom product market to various smart products (for example, optical communication light source modules, proximity sensors in smart tablet phones ⁇ smart earphones (Proximity Sensor) ), depth ⁇ distance ⁇ 3D sensors, lidar sensors for advanced driver assistance systems, micro-projection display light sources or panels, eye trackers in interactive devices (Eye Tracker) and other products).
  • the present disclosure provides semiconductor lasers in various embodiments and packaging structures including the semiconductor lasers.
  • the electrode structure can be arranged on the oblique side of the semiconductor stack of the semiconductor laser, so that the size of the packaging structure can be reduced after the laser element is packaged;
  • An embodiment of the present disclosure provides a semiconductor laser, which includes: a semiconductor stack, a first electrode structure, and a first insulating layer.
  • the semiconductor stack has a first surface, a second surface and side surfaces. The first surface is opposite to the second surface, and the side is located between the first surface and the second surface.
  • the semiconductor stack includes a first type semiconductor layer, a second type semiconductor layer and an active layer. The active layer is located between the first type semiconductor layer and the second type semiconductor layer.
  • the first electrode structure is located on the first surface and the side surface. In this embodiment, the first electrode structure is located on the first surface and extends to the side.
  • the first insulating layer is located between the semiconductor stack and the first electrode structure.
  • the first insulating layer has a first opening, the first opening is located on the first surface, and the first electrode structure is further located in the first opening and contacts the first type semiconductor layer.
  • the side surface has an included angle ⁇ relative to the first surface, and the angle distribution range of the included angle ⁇ is between 90 degrees (inclusive) and 120 degrees (inclusive).
  • the semiconductor laser further includes a base layer located on a side of the second-type semiconductor layer opposite to the first-type semiconductor layer.
  • the semiconductor laser further includes: a second electrode structure located on the first surface and side surfaces, wherein the first insulating layer is further located between the semiconductor stack and the second electrode structure.
  • the second electrode structure and the first insulating layer further extend and distribute on the base layer from the side, and the first insulating layer further has a second opening on the surface of the base layer, and the second electrode structure distributes to the second The opening is in contact with the base layer, so that the second electrode structure is electrically connected to the second type semiconductor layer through the base layer.
  • the base layer has a surface and sides connected to the surface.
  • the second-type semiconductor layer in the semiconductor stack further includes a first platform portion and a second platform portion extending laterally on the surface, and the first insulating layer and the second electrode structure are further located between the first platform portion and the second platform portion On the surface, the first insulating layer has a second opening on the first platform portion, and the second electrode structure is distributed into the second opening and contacts the first platform portion of the second-type semiconductor layer.
  • the second electrode structure is not only located in the second opening of the first insulating layer, but also extends to the side of the base layer, and the first electrode structure also extends from the side of the semiconductor stack through the second platform portion to the side of the base.
  • the semiconductor laser further includes a second insulating layer and an adhesive layer, wherein the second The insulating layer is located between the semiconductor stack and the second electrode structure, and the adhesive layer is located between the semiconductor stack and the base layer.
  • the second electrode structure is located on the first surface, the side surface and the second surface.
  • the first insulating layer is located between the semiconductor stack and the second electrode structure, wherein the first insulating layer has a plurality of second openings, the second openings are located on the second surface, and the second electrode structure is further located in the second openings and contacts Second-type semiconductor layer.
  • the second electrode structure is not only located in the second opening of the first insulating layer, but also located on the first surface of the semiconductor stack and extending to the side and the second surface.
  • the adhesive layer and the base layer are transparent, the adhesive layer is located on the second-type semiconductor layer and covers the second electrode structure and the second insulating layer, and the base layer is located on the adhesive layer.
  • the semiconductor stack further includes: a first current confinement layer located between the active layer and the first-type semiconductor layer, the first current confinement layer includes a first current confinement region and a first current conduction region, and The first current conduction region is surrounded by the first current confinement region.
  • the semiconductor stack further includes a first current confinement layer and a second current confinement layer.
  • the first current confinement layer is located between the active layer and the first-type semiconductor layer, the first current confinement layer includes a first current confinement region and a first current conduction region, and the first current conduction region is surrounded by the first current confinement region surround.
  • the second current confinement layer is located between the first type semiconductor layer and the second type semiconductor layer, the second current confinement layer includes a second current confinement region and a second current conduction region, and the second current conduction region is controlled by the second Surrounded by a current limiting zone.
  • the active layer has a first quantum well layer, a second quantum well layer and a spacer layer, and the active layer further includes a tunnel junction (Tunnel Junction) layer located between the first quantum well layer and the second quantum well layer.
  • the first current confinement layer is located on the first quantum well layer
  • the spacer layer is located between the first quantum well layer and the tunnel junction layer
  • the second quantum well layer is located between the second current confinement layer and the second type semiconductor layer .
  • the semiconductor laser further includes a first conductive connection part, a second conductive connection part and a third insulating layer.
  • the first conductive connection part is located on a side away from the base layer and connected to the first electrode structure.
  • the second conductive connection part is located on a side away from the base layer and connected to the second electrode structure.
  • the third insulating layer is located between the first electrode structure and the first conductive connection part and between the second electrode structure and the second conductive connection part.
  • the second electrode structure on the second surface has electrode openings corresponding to the positions of the first current conduction region and the second current conduction region, wherein the width of the electrode opening is greater than the width of the first current conduction region , and the width of the electrode opening is greater than or equal to the width of the second current conducting region.
  • a packaging structure which includes: a packaging substrate, a semiconductor laser, and a packaging layer.
  • the semiconductor laser has a light-emitting surface and the surface is opposite to the light-emitting surface.
  • the semiconductor laser is located on the packaging substrate and its surface is in contact with the packaging substrate.
  • the first electrode structure and the second electrode structure located on the side of the semiconductor laser are respectively electrically connected through the connection structure. to the first conductive pad structure and the second conductive pad structure of the packaging substrate.
  • the encapsulation layer includes encapsulation material, and the encapsulation layer covers the semiconductor laser. There are multiple filler particles in the encapsulation layer.
  • one side of the semiconductor laser (on the side adjacent to the second electrode structure) further has a third insulating layer, wherein the third insulating layer extends to the light-emitting surface to cover part of the first electrode structure.
  • the distance is 30 to 50 microns.
  • a barrier wall is further provided on the first surface of the substrate body of the packaging substrate, and the semiconductor laser is disposed on the first surface and surrounded by the barrier wall, and the encapsulation layer fills the area surrounded by the barrier wall and covers A semiconductor laser.
  • the first conductive pad structure of the packaging substrate includes a first conductive pad portion, a first interconnection portion, and a second conductive pad portion
  • the second conductive pad structure of the packaging substrate includes a third The conductive pad part, the second inner connection part and the fourth conductive pad part; wherein, the first conductive pad part and the third conductive pad part are located on the first surface of the packaging substrate and surrounded by a barrier wall, and the first inner The connection part and the second inner connection part are penetrated in the substrate main body and individually connected to the first conductive pad part and the third conductive pad part, and the second conductive pad part and the fourth conductive pad part are located on the second side of the substrate main body.
  • the first internal connection part and the second internal connection part are connected on the surface and individually.
  • a semiconductor laser which includes: a semiconductor stack, a first electrode structure, a first insulating layer, a base layer, a second electrode structure, and a second insulating layer, wherein the base layer is a conductive layer, and the first
  • the two-electrode structure includes a second contact electrode portion and a second extension electrode portion.
  • the semiconductor stack has a first surface, a second surface and a side surface, the second surface is relative to the first surface, the side surface is located between the first surface and the second surface, the side surface has an angle ⁇ with respect to the first surface, and the angle ⁇ is The angle is substantially 90 degrees.
  • the semiconductor stack includes a first type semiconductor layer, a second type semiconductor layer and an active layer, wherein the active layer is located between the first type semiconductor layer and the second type semiconductor layer.
  • the first electrode structure is located on the first surface.
  • the first insulating layer is located between the semiconductor stack and the first electrode structure, wherein the first insulating layer has a first opening, the first opening is located on the first surface, and the first electrode structure is further located in the first opening and contacts the first electrode structure.
  • type semiconductor layer is located on a side of the second-type semiconductor layer opposite to the first-type semiconductor layer.
  • the first insulating layer is further located between the semiconductor stack and the second electrode structure and between the first electrode structure and the second electrode structure, wherein the first insulating layer has a through hole, the through hole passes through the semiconductor stack, and the second electrode structure
  • the second contact electrode portion is located in the through hole and contacts the base layer, so that the second electrode structure is electrically connected to the second type semiconductor layer through the base layer.
  • the second insulating layer is located in the through hole, and the second insulating layer is located between the second contact electrode part and the semiconductor stack to isolate the second contact electrode part from the first type semiconductor layer, and to isolate the second contact electrode part from the active layer. layer.
  • the second extension electrode part of the second electrode structure is connected to the second contact electrode part and extends from the first surface to the side surface.
  • a packaging structure which includes: a packaging substrate and a semiconductor laser, wherein the packaging substrate includes a substrate body, a first conductive pad structure, and a second conductive pad structure.
  • the semiconductor laser has a light-emitting surface and a surface. The surface of the semiconductor stack of the semiconductor laser faces the substrate body and the base layer is away from the substrate body.
  • the first electrode structure and the second electrode structure on the side of the semiconductor stack can be electrically connected through the connection structure.
  • the first conductive pad structure and the second conductive pad structure connected to the packaging substrate.
  • a semiconductor laser which includes: a semiconductor stack, a first electrode structure, a second electrode structure, an electrode substrate, an adhesive layer, and an insulating layer.
  • the semiconductor laser further has a through hole, wherein the through hole passes through the semiconductor stack and the adhesive layer.
  • the semiconductor stack has a first surface, a second surface and a side surface, the second surface is relative to the first surface, the side surface is located between the first surface and the second surface, the side surface has an angle ⁇ with respect to the first surface, and the angle ⁇ is The angle is substantially 90 degrees.
  • the semiconductor stack includes a first type semiconductor layer, a second type semiconductor layer and an active layer. The active layer is located between the first type semiconductor layer and the second type semiconductor layer.
  • the first electrode structure is located on the first surface to be in electrical contact with the first type semiconductor layer.
  • the second electrode structure is located on the second surface to be in electrical contact with the second type semiconductor layer.
  • the electrode substrate has a body, a first electrode unit and a second electrode unit, wherein the body is non-conductive, and the first electrode unit and the second electrode unit are respectively located on two sides of the body and extend to the upper and lower surfaces of the body, and the first electrode The unit and the second electrode unit are not in contact with each other.
  • the adhesive layer is located between the first type semiconductor layer and the electrode substrate, and the adhesive layer is non-conductive.
  • the insulating layer is located in the through hole, And the insulating layer is located between the semiconductor stack and the second electrode structure to electrically insulate the active layer, the first-type semiconductor layer and the second electrode structure, and the second electrode structure extends from the second surface and is distributed in the through hole and contacts The second electrode unit of the electrode substrate.
  • the first electrode structure is more electrically connected to the first electrode unit.
  • a packaging structure which includes: a packaging substrate, a semiconductor laser, and a connection structure, wherein the packaging substrate includes a substrate body, a first conductive pad structure, and a second conductive pad structure.
  • the semiconductor laser has a light-emitting surface and a surface.
  • the semiconductor laser is placed on the package substrate.
  • the electrode substrate of the semiconductor laser is located on the side close to the substrate body, and the semiconductor stack of the semiconductor laser is located on the other side away from the substrate body.
  • the first electrode structure and The first electrode unit is electrically connected to the first conductive pad structure of the packaging substrate through the connection structure, and the second electrode structure and the second electrode unit are electrically connected to the second conductive pad structure through the connection structure.
  • a semiconductor laser which includes: a semiconductor stack, a first electrode structure, a first insulating layer, a second electrode structure, a second insulating layer, an adhesive layer, a base layer, and an optical element.
  • Optical elements are on the base layer.
  • the semiconductor laser may have a plurality of optical elements located at different positions on the base layer.
  • the first optical element is located on the base layer and the second optical element is located below the base layer.
  • the base layer includes a first base layer, a second base layer and an adhesion layer, and the second base layer is bonded to the first base layer through the adhesion layer.
  • the second base layer has optical elements on it.
  • the structure of the optical element can be located in the surface area of the substrate or in the bulk of the substrate.
  • the semiconductor laser further includes a third optical element.
  • the structure of the third optical element is located on the second surface of the semiconductor stack, the structure of the third optical element is located in the light outlet of the second electrode structure, and the structure of the third optical element is located between the second insulating layer and the adhesive layer, wherein The position of the light outlet corresponds to the position of the first current conduction region in the semiconductor stack.
  • the third optical element has a metasurface (Metasurface) structure, wherein the metasurface structure is a nanostructure having a plurality of periodic arrays.
  • a fourth optical element is further included between the adhesive layer and the base layer of the semiconductor laser to change the traveling direction of light incident on the base layer. Furthermore, there is a fifth optical element on the light-emitting side of the base layer to further The direction of travel of light exiting the base layer is varied.
  • the fourth optical element is a structural layer between the second insulating layer and the adhesive layer, but embodiments of the present disclosure are not limited thereto.
  • the third optical element may be an interface structure between the second insulating layer and the adhesive layer.
  • the aforementioned optical element may include, for example, a diffractive optical element (Diffraction Optical Element, DOE) structure, a micro lens array (Micro Lens Array, MLA) structure, a metasurface structure or a metal lens (Metalens), or each of the foregoing A combination of optical element structures.
  • DOE diffractive optical element
  • MLA micro Lens Array
  • Metalens metal lens
  • the structure of the optical element may be located in the surface area of the base layer or in the main body of the base layer, but the embodiments of the present disclosure are not limited thereto.
  • the structure of the optical element may also be located in the main body of the adhesive layer, and the embodiments of the present disclosure are not limited thereto.
  • a semiconductor laser which includes: a semiconductor stack, a first electrode structure, a first insulating layer, a base layer, and a second electrode structure.
  • the semiconductor laser further includes a light-transmitting conductive layer, a current confinement layer, and an insulating layer.
  • the light-transmitting conductive layer is stacked between the semiconductor stack and the first electrode structure
  • the current confinement layer is stacked between the light-transmitting conductive layer and the semiconductor stack
  • the current confinement layer is light-transmissible.
  • the semiconductor stack of a semiconductor laser includes: a first type semiconductor layer, a second type semiconductor layer, an active layer and a current confinement layer.
  • the active layer is stacked between the first type semiconductor layer and the second type semiconductor layer.
  • the current confinement layer is stacked between the first type semiconductor layer and the active layer.
  • the current confinement layer includes a current conduction region and a current confinement region.
  • the current confinement layer on the first type semiconductor layer has a conduction opening, wherein the position of the conduction opening corresponds to the current conduction region.
  • the light-transmitting conductive layer is located on the current confinement layer and in the conduction opening and contacts the first-type semiconductor layer.
  • the insulating layer is located on the light-transmitting conductive layer and has an insulating opening, wherein the insulating opening does not overlap with the conducting opening.
  • the first electrode layer is located on the insulating layer and in the insulating opening and contacts the light-transmitting conductive layer to electrically connect the first-type semiconductor layer.
  • the second electrode layer is located under the second-type semiconductor layer and electrically connected to the second-type semiconductor layer.
  • the light-transmitting conductive layer is formed on the current confinement layer and in the conducting opening, the light-transmitting conducting layer located in the conducting opening has a first thickness, and the light-transmitting conducting layer not located in the conducting opening has a second thickness , the first thickness is greater than the second thickness.
  • the light-transmitting conductive layer of the semiconductor laser has an upper surface and a lower surface, and the lower surface The surface is opposite to the upper surface, and the upper surface is a plane, and the lower surface has a downward protruding surface located in the conduction opening.
  • the position of the current conduction region corresponds to the position of the conduction opening.
  • the current conduction region has a conduction width
  • the conduction opening has an opening width
  • the conduction width is greater than the opening width
  • the light-transmitting conductive layer of the semiconductor laser is formed on the current confinement layer and has a first recessed area, the first recessed area is located on the conduction opening, and the light-transmissive conductive layer located in the first recessed area has a first Thickness, the light-transmitting conductive layer not located in the first recessed area has a second thickness, and the first thickness is equal to or close to the second thickness.
  • the light-transmitting conductive layer is conformally formed on the current confinement layer.
  • the insulating layer of the semiconductor laser is formed on the light-transmitting conductive layer and has a second recessed area, the second recessed area is located on the first recessed area, and the insulating layer located in the second recessed area has a third thickness.
  • the insulating layer located in the second recessed area has a fourth thickness, and the third thickness is equal to or close to the fourth thickness.
  • the insulating layer is conformally formed on the transparent conductive layer.
  • the first-type semiconductor layer of the semiconductor laser further has a doped region.
  • the position of the doped region corresponds to the center position above the current conduction region and does not overlap the current conduction region. .
  • the light-transmitting conductive layer of the semiconductor laser includes a first light-transmitting conductive region and a second light-transmitting conductive region, the second light-transmitting conductive region surrounds the first light-transmitting conductive region, and the conduction opening is located in the first transparent conductive region. Between the photoconductive region and the second transparent conductive region.
  • the semiconductor laser further includes a reflective layer located on the upper surface of the light-transmitting conductive layer, and the reflective layer is located in the opening defined by the first electrode structure, and an insulating layer is distributed between the reflective layer and the first electrode structure so as to The reflective layer is electrically insulated from the first electrode structure.
  • the reflective layer may be, for example, a Bragg reflective (DBR) structure, and further, the reflective layer may be formed by alternately stacking two or more dielectric layers with different refractive indices, such as silicon oxide layers and titanium oxide layers.
  • DBR Bragg reflective
  • the width of the reflective layer is less than or equal to the width of the via opening.
  • a semiconductor laser includes: a semiconductor stack, a base layer, a first electrode structure, a second electrode structure, and a first insulating layer.
  • the semiconductor stack is located on the base layer, and the first insulating layer is located Between the semiconductor stack and the first electrode structure, and the first insulating layer has a first opening, the first electrode structure is distributed on the first insulating layer and extends into the first opening to be electrically connected with the semiconductor stack.
  • the base layer is located between the semiconductor stack and the second electrode structure, and the base layer is conductive so that the second electrode structure is electrically connected to the semiconductor stack.
  • the semiconductor stack includes an upper reflector layer, a lower reflector layer and an active layer, and the active layer is located between the upper reflector layer and the upper reflector layer.
  • the lower mirror layer is a second-type semiconductor layer and has a Bragg reflection structure (DBR).
  • the upper reflector layer includes a first upper reflector layer and a second upper reflector layer, the first upper reflector layer is located between the active layer and the second upper reflector layer, and the second upper reflector layer is located on the first upper reflector layer Between the layer and the first electrode structure, wherein the first upper mirror layer is a first-type semiconductor layer and has a Bragg reflection structure (DBR).
  • the second upper mirror layer includes a middle reflection area and a current path area, the current path area is located on both sides of the middle reflection area, and the first electrode structure passes through the first opening of the first insulating layer and the second upper mirror layer. The current path area is electrically connected.
  • the upper mirror layer has a Bragg reflective structure (DBR), wherein the Bragg reflective structure located in the current path region has doping or a higher concentration of doping (compared to the middle reflective region).
  • DBR Bragg reflective structure
  • the semiconductor stack further includes a current confinement layer located between the active layer and the upper mirror layer.
  • the current confinement layer includes a current confinement area and a current conduction area, and the current conduction area is surrounded by the current confinement area.
  • the current conduction region surrounded by the current confinement region has a first distribution width.
  • the first electrode structure defines an electrode opening on the first insulating layer, the position of the electrode opening corresponds to the position of the current conduction region, and the electrode opening has an opening width.
  • the middle reflective area located between the current path areas on both sides has a second distribution width, and the position of the middle reflective area corresponds to the position of the current conduction area.
  • the opening width of the first electrode structure is smaller than or equal to the second distribution width of the middle reflective region.
  • the opening width of the first electrode structure is greater than or equal to the first distribution width of the current conduction region.
  • the opening width of the first electrode structure is greater than or equal to the second distribution width of the middle reflective region, and the second distribution width is greater than or equal to the first distribution width of the current conduction region.
  • 1A is a schematic cross-sectional view of an epitaxial stack structure of a vertical cavity surface emitting laser (VCSEL);
  • VCSEL vertical cavity surface emitting laser
  • 1B is a schematic cross-sectional view of a vertical cavity surface emitting laser element
  • FIG. 2 is a schematic cross-sectional view of a semiconductor laser according to at least one embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional view of a semiconductor laser according to at least one embodiment of the present disclosure
  • FIG. 4 is a schematic cross-sectional view of a semiconductor laser according to at least one embodiment of the present disclosure
  • FIG. 5 is a schematic cross-sectional view of a semiconductor laser according to at least one embodiment of the present disclosure
  • FIG. 6 is a schematic cross-sectional view of a semiconductor laser according to at least one embodiment of the present disclosure.
  • FIG. 7A is a schematic cross-sectional view of a package structure of at least one embodiment of the present disclosure.
  • FIG. 7B is another schematic cross-sectional view of the packaging structure of at least one embodiment of the present disclosure.
  • FIG. 7C is another schematic cross-sectional view of the packaging structure of at least one embodiment of the present disclosure.
  • 7D is another schematic cross-sectional view of the packaging structure of at least one embodiment of the present disclosure.
  • 7E is a schematic cross-sectional view of a package structure of at least one embodiment of the present disclosure.
  • FIG. 8 is a schematic cross-sectional view of a semiconductor laser according to at least one embodiment of the present disclosure.
  • FIG. 9 is a schematic cross-sectional view of a package structure of at least one embodiment of the present disclosure.
  • FIG. 10 is a schematic cross-sectional view of a semiconductor laser according to at least one embodiment of the present disclosure.
  • FIG. 11 is a schematic cross-sectional view of a package structure of at least one embodiment of the present disclosure.
  • FIG. 12A is a schematic cross-sectional view of a semiconductor laser according to at least one embodiment of the present disclosure
  • FIG. 12B is a schematic cross-sectional view of a semiconductor laser according to at least one embodiment of the present disclosure
  • 12C is a schematic cross-sectional view of a semiconductor laser according to at least one embodiment of the present disclosure.
  • FIG. 13 is a schematic cross-sectional view of a semiconductor laser according to at least one embodiment of the present disclosure.
  • FIG. 14A is a schematic cross-sectional view of a semiconductor laser according to at least one embodiment of the present disclosure.
  • 14B is a schematic modal diagram of a semiconductor laser according to at least one embodiment of the present disclosure.
  • 15A is a schematic cross-sectional view of a semiconductor laser according to at least one embodiment of the present disclosure.
  • FIG. 15B is a schematic modal diagram of a semiconductor laser according to at least one embodiment of the present disclosure.
  • FIG. 16A and FIG. 16B are schematic top views of a light emitting hole of a semiconductor laser according to at least one embodiment of the present disclosure
  • 17 is a schematic cross-sectional view of a semiconductor laser according to at least one embodiment of the present disclosure.
  • 18A is a schematic cross-sectional view of a semiconductor laser according to at least one embodiment of the present disclosure.
  • FIG. 18B is a schematic modal diagram of a semiconductor laser according to at least one embodiment of the present disclosure.
  • 18C to 18E are schematic top views of the light emitting hole of the semiconductor laser according to at least one embodiment of the present disclosure.
  • 19 is a schematic cross-sectional view of a semiconductor laser according to at least one embodiment of the present disclosure.
  • 20 is a schematic cross-sectional view of a semiconductor laser according to at least one embodiment of the present disclosure.
  • 21A to 21F are schematic cross-sectional structural diagrams of multiple steps in the manufacturing process of the embodiment of FIG. 3;
  • 22A to 22G are schematic cross-sectional structural diagrams of multiple steps in the manufacturing process of the embodiment of FIG. 4;
  • 23A to 23K are schematic cross-sectional structural diagrams of multiple steps in the manufacturing process of the embodiment of FIG. 5;
  • 24A to 24C are respectively a schematic cross-sectional view, a bottom perspective schematic diagram and a top perspective schematic diagram of a semiconductor laser according to at least one embodiment of the present disclosure
  • 25 is a schematic cross-sectional view of a packaging structure of a light emitting device according to at least one embodiment of the present disclosure
  • 26 is a schematic cross-sectional view of a packaging structure of a light emitting device according to at least one embodiment of the present disclosure
  • FIG. 27 is a schematic cross-sectional view of a packaging structure of a light emitting device according to at least one embodiment of the present disclosure
  • FIG. 28 is a schematic cross-sectional view of a packaging structure of a light emitting device according to at least one embodiment of the present disclosure
  • 29 is a schematic cross-sectional view of a packaging structure of a light emitting device according to at least one embodiment of the present disclosure.
  • FIG. 30A is a schematic diagram of the light-emitting angle of a light-emitting device without an adjustment layer
  • FIG. 30B is a schematic diagram of the light-emitting angle of the light-emitting device further comprising an adjustment layer according to the embodiment of FIG. 30A;
  • 31A is a schematic side perspective view of a packaging structure of an optical transceiver according to at least one embodiment of the present disclosure
  • Fig. 31B is a top view of the packaging structure of the optical transceiver device according to the embodiment of Fig. 31A;
  • Fig. 32 is a top view of the packaging structure of an optical transceiver device according to at least one embodiment of the present disclosure
  • FIG. 33 is a top view of a package structure of at least one embodiment of the present disclosure.
  • 34 is a schematic cross-sectional view of a package structure of at least one embodiment of the present disclosure.
  • 35 is a schematic cross-sectional view of a package structure of at least one embodiment of the present disclosure.
  • 36 is a schematic cross-sectional view of a package structure of at least one embodiment of the present disclosure.
  • 37 is a schematic cross-sectional view of a package structure of at least one embodiment of the present disclosure.
  • 38 is a schematic cross-sectional view of a package structure of at least one embodiment of the present disclosure.
  • 39 is a schematic cross-sectional view of a package structure of at least one embodiment of the present disclosure.
  • 40 is a schematic cross-sectional view of a package structure of at least one embodiment of the present disclosure.
  • 41 is a schematic cross-sectional view of a package structure of at least one embodiment of the present disclosure.
  • 43 is a schematic cross-sectional view of a package structure of at least one embodiment of the present disclosure.
  • 44A is a schematic cross-sectional view of a package structure of at least one embodiment of the present disclosure.
  • FIG. 44B is a top view of the package structure of the embodiment in FIG. 44A.
  • the positive electrode pad and the negative electrode pad on the circuit substrate are too close, apply solder paste during the flip-chip packaging process
  • the positive electrode pad and the negative electrode pad may be connected to each other, thereby causing a short circuit; and if the positive and negative electrode pads on the circuit board and/or the electrode pads on the laser grain component If the size is too small, during the alignment process of the flip-chip packaging, it may also be caused by the alignment of the alignment mechanism.
  • the error causes the electrode of the laser grain component to be misaligned with the electrode pad on the circuit substrate, which in turn causes short circuit, open circuit or poor bonding.
  • the distance between the positive electrode pad and the negative electrode pad on the circuit substrate needs to be greater than a certain interval (for example, the interval of about 90 microns needs to be maintained), and the size of the electrode pad (electrode pad) also needs to be There is sufficient size (for example, generally 80 microns ⁇ 50 microns) to provide sufficient voltage, but this will make it difficult to greatly reduce the overall package size after the laser components are packaged.
  • FIG. 1A is a schematic cross-sectional view of an epitaxial stack structure of a vertical cavity surface emitting laser
  • FIG. 1B is a schematic cross-sectional view of a vertical cavity surface emitting laser element
  • the vertical cavity surface emitting laser element 1 includes a semiconductor epitaxial technology formed on The semiconductor stack 10 of the conductive growth substrate 40G, wherein the semiconductor stack 10 includes a first-type semiconductor mirror layer 101U, a second-type semiconductor mirror layer 102D, and an active layer (active layer) 103A stacked on the first-type semiconductor mirror layer. between the mirror layer 101U and the second-type semiconductor mirror layer 102D.
  • the first type and the second type respectively refer to semiconductor structures with different electrical properties. If the semiconductor structure uses holes (holes) as the majority carrier (carrier), it is a P-type semiconductor. If the semiconductor structure uses electrons (electrons) The majority carrier is an N-type semiconductor.
  • the first-type semiconductor layer is a P-type semiconductor, and the second-type semiconductor layer is an N-type semiconductor, and vice versa.
  • the VCSEL device 1 further includes an electrode structure 20 electrically connected to the first-type semiconductor mirror layer 101U and an electrode structure 50 electrically connected to the second-type semiconductor mirror layer 102D.
  • Both the first-type semiconductor mirror layer 101U and the second-type semiconductor mirror layer 102D are high-reflectivity layers, because the active layer 103A is located in the resonance between the first-type semiconductor mirror layer 101U and the second-type semiconductor mirror layer 102D. In the cavity region, the light emitted by the active layer 103A can be reflected back and forth therein to form coherent light.
  • the first-type semiconductor mirror layer 101U and the second-type semiconductor mirror layer 102D may include a distributed Bragg reflector (Distributed Bragg Reflector, DBR) structure, as shown in FIG.
  • DBR distributed Bragg Reflector
  • the distributed Bragg reflector can be formed by stacking two or more film layers with different refractive indices, such as AlAs/GaAs, AlGaAs/GaAs or InGaP/GaAs.
  • the reflectivity of one mirror layer in the first type semiconductor mirror layer 101U and the second type semiconductor mirror layer 102D is lower than that of the other.
  • the reflectivity of the mirror layer for example, when the reflectivity of the first type semiconductor mirror layer 101U is lower than the reflectivity of the second type semiconductor mirror layer 102D, then in the first type semiconductor mirror layer 101U and the second type semiconductor reflector layer Most of the coherent light formed between the mirror layers 102D will pass through the first-type semiconductor mirror layer 101U to form the light L emitted from the semiconductor stack 10 on the surface 101S.
  • the VCSEL device 1 further includes a current confinement layer 104A between the active layer 103A and the first-type semiconductor layer 101U.
  • the current confinement layer 104A includes a current confinement region 1041A and a current conduction region 1042A, and the current conduction region 1042A is surrounded by the current confinement region 1041A.
  • the conductivity of the current conduction region 1042A is higher than that of the current confinement region 1041A, so that the current conducts concentratedly in the current conduction region 1042A.
  • FIG. 2 is a schematic cross-sectional view of a semiconductor laser 1001 according to at least one embodiment of the present disclosure; the semiconductor laser 1001 of this embodiment includes: a semiconductor stack 10 , an electrode structure 20 and an insulating layer 30 .
  • the semiconductor stack 10 has a surface 11 , a surface 12 and a side surface 13 .
  • the surface 12 is opposite to the surface 11 , and the side surface 13 is between the surface 11 and the surface 12 .
  • the semiconductor stack 10 includes a first-type semiconductor layer 101 , a second-type semiconductor layer 102 and an active layer 103 .
  • the active layer 103 is between the first-type semiconductor layer 101 and the second-type semiconductor layer 102 .
  • the first-type semiconductor layer 101 is a P-type semiconductor layer
  • the second-type semiconductor layer 102 is an N-type semiconductor layer, but the embodiments of the present disclosure are not limited thereto.
  • the electrode structure 20 is located on the surface 11 and the side surface 13 .
  • the electrode structure 20 is located on the surface 11 and extends to the side surface 13 . Therefore, when the semiconductor laser 1001 is electrically bonded to the conductive pads on the package substrate, the electrodes of the semiconductor laser 1001 can be increased without increasing the size of the semiconductor laser 1001 because the electrode structure 20 extends to the side surface 13. The bondable area between the structure 20 and the package substrate. In this way, when the semiconductor laser 1001 is packaged, the chip size can be reduced under the premise of maintaining the distance between the conductive pads of the package substrate.
  • the insulating layer 30 is between the semiconductor stack 10 and the electrode structure 20 .
  • the insulating layer 30 has an opening 31 on the surface 11 , and the electrode structure 20 is further distributed in the opening 31 and contacts the first-type semiconductor layer 101 .
  • the side surface 13 has an included angle ⁇ relative to the surface 11 , and the angle distribution range of the included angle ⁇ is between 90 degrees and 120 degrees.
  • the included angle ⁇ is 120 degrees
  • the original chip size is 240 microns ⁇ 140 microns
  • the chip size obtained through the configuration of this embodiment will be reduced to 217 microns ⁇ 128 microns.
  • the electrode structure 20 that is originally rectangular and has a height of 30 microns, if the included angle ⁇ is 120 degrees, the original chip size is 240 microns ⁇ 140 microns, and the chip size obtained through the configuration of this embodiment is It will be further scaled down to 171 microns x 105 microns. Therefore, by disposing the electrodes on the side surface 13 of the semiconductor stack 10, the size of the packaging structure of the semiconductor laser 1001 can be reduced after packaging.
  • FIG. 3 and 4 are schematic cross-sectional views of semiconductor lasers 1002 and 1003 in at least one embodiment of the present disclosure; Similar in structure, the semiconductor lasers 1002 and 1003 further include a base layer 40 located on the side of the second-type semiconductor layer 102 opposite to the first-type semiconductor layer 101 .
  • the base layer 40 can be the growth substrate of the semiconductor stack 10, that is, the semiconductor stack 10 is directly grown on the base layer 40, or, referring to FIG. 5, the base layer 40 can also be the packaging substrate of the semiconductor stack 10, That is, the semiconductor stack 10 is first grown on the growth substrate, and then transferred to the base layer 40 for subsequent packaging procedures.
  • the semiconductor lasers 1002 and 1003 further include an electrode structure 50 on the surface 11 and the side surface 13 , and the insulating layer 30 is further located between the semiconductor stack 10 and the electrode structure 50 .
  • the base layer 40 is conductive
  • the electrode structure 50 and the insulating layer 30 are further distributed from the side surface 13 to the base layer 40
  • the insulating layer 30 further has an opening 32 located on the surface of the base layer 40
  • the electrode structure 50 is distributed into the opening 32 and contacts the base layer 40 , so that the electrode structure 50 is electrically connected to the second-type semiconductor layer 102 through the base layer 40 . Therefore, according to the semiconductor laser 1002 of this embodiment, the bonding area between the electrode structure 20 and the electrode structure 50 of the semiconductor laser 1002 and the conductive pads of the packaging substrate can be further increased.
  • the base layer 40 is conductive or electrically insulating, the base layer 40 has a surface 41 and a side 42 connecting the surface 41, and the second-type semiconductor layer 102 in the semiconductor stack 10 further includes a platform.
  • Parts 1022A and 1022B extend laterally on the surface 41, the insulating layer 30 and the electrode structure 50 are further located on the surface of the platform parts 1022A and 1022B, the insulating layer 30 has an opening 32 on the platform part 1022A, and the electrode structure 50 is distributed to the opening 32 middle and touch second half The platform portion 1022A of the conductor layer 102 .
  • the electrode structure 50 is not only located in the opening 32 of the insulating layer 30, but also extends to the side surface 42 of the base layer 40, and the electrode structure 20 also extends from the side surface 13 of the semiconductor stack 10 through the platform portion 1022B to the base layer. 40 side 42 . Therefore, according to the semiconductor laser 1003 of this embodiment, the bonding area between the electrode structure 20 and the electrode structure 50 of the semiconductor laser 1003 and the conductive pads of the packaging substrate can be further increased.
  • the semiconductor laser 1004 further includes an insulating layer 60 and an adhesive layer 70, wherein the insulating layer 60 is located between the semiconductor stack 10 and the electrode structure 50 Between, the adhesive layer 70 is located between the semiconductor stack 10 and the base layer 40 .
  • the electrode structure 50 is located on the surface 11 , on the side 13 and on the surface 12 .
  • the side 13 of the semiconductor stack 10 is further divided into a first side 13a (upper side) and a second side 13b (lower side).
  • the insulating layer 30 is located between the semiconductor stack 10 and the electrode structure 50, wherein the insulating layer 30 has a plurality of openings 32 on the surface 12 , and the electrode structure 50 is further located in the openings 32 and contacts the second-type semiconductor layer 12 .
  • the electrode structure 50 is not only located in the opening 32 of the insulating layer 30 , but also located on the surface 11 of the semiconductor stack 10 and extending to the side surface 13 and the surface 12 .
  • the first-type semiconductor layer 101 of the semiconductor stack 10 has platform portions 1012A and 1012B extending laterally and protruding from the first side 13a. Therefore, according to the semiconductor laser 1004 of this embodiment, the electrode structure can be further increased The contact area between the electrode structure 50 and the conductive pad on the packaging substrate and the contact area between the electrode structure 50 and the conductive pad on the packaging substrate.
  • the adhesive layer 70 and the base layer 40 are light-transmissive, the adhesive layer 70 is located on the second-type semiconductor layer 12 and covers the electrode structure 50 and the insulating layer 60 , and the base layer 40 is located on the adhesive layer 70 .
  • the first-type semiconductor layer 101 and the second-type semiconductor layer 102 have a distributed Bragg mirror structure, so that the light emitted by the active layer 103 can be reflected in the two mirrors to form coherent light.
  • the semiconductor stack 10 further includes a current confinement layer 104 located between the active layer 103 and the first-type semiconductor layer 101 .
  • the current confinement layer 104 includes a current confinement region 1041 and a current conduction region 1042, and the current confinement region 1042 is surrounded by the current confinement region 1041 surround.
  • the conductivity of the current conduction region 1042 is higher than that of the current confinement region 1041 , so that the current is conducted concentratedly in the current conduction region 1042 .
  • the current confinement layer can also be disposed between the active layer 103 and the second-type semiconductor layer 102; or, in the semiconductor stack 10, a plurality of current confinement layers are respectively disposed on the active layer 103 and the first-type semiconductor layer 101 and between the active layer 103 and the second-type semiconductor layer 102 .
  • FIGS. 21A-21F , 22A-22G , and 23A-23K respectively.
  • FIG. 21A to 21F are schematic cross-sectional structural diagrams of multiple steps in the manufacturing process of the semiconductor laser 1002 in the embodiment of FIG. 3 ; as shown in FIG. 21A , an epitaxial chip 2 is provided.
  • the epitaxial chip 2 includes a semiconductor stack 10 formed on a base layer 40.
  • the semiconductor stack 10 sequentially includes a first-type semiconductor layer 101, an active layer 103 and a second-type semiconductor layer 102 on the base layer 40, wherein the first type
  • the semiconductor layer 101 and/or the second-type semiconductor layer 102 may be a multi-layer structure.
  • the first-type semiconductor layer 101 is a P-type semiconductor layer
  • the second-type semiconductor layer 102 is an N-type semiconductor layer.
  • the semiconductor stack 10 can be grown on the base layer 40 by epitaxial methods, including but not limited to metal organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, liquid phase epitaxy, and the like.
  • the base layer 40 includes but is not limited to III-V materials whose lattice constants are matched with the semiconductor stack 10 .
  • the material of the base layer 40 in this embodiment is gallium arsenide (GaAs).
  • the material of the base layer 40 may be indium phosphide (InP), sapphire, gallium nitride (GaN), or silicon carbide (SiC).
  • a protective layer PL is first formed to cover the first-type semiconductor layer 101 of the epitaxial chip 2 , wherein the material of the protective layer PL can be an insulating material, including but not limited to silicon nitride.
  • an etching procedure is performed on the aforementioned chip 2, and a mask of a specific pattern is used to etch and remove part of the first-type semiconductor layer 101, part of the active layer 103, and part of the second-type semiconductor layer 102 and expose part of the base layer 40, thereby
  • the mesa structure P1 is formed on the side of the first-type semiconductor layer 101 and defines the side surface 13 of the semiconductor stack 10 .
  • the contact electrode portion 50 a of the electrode structure 50 is formed on the base layer 40 .
  • a current confinement layer 104 is formed in the semiconductor stack 10 .
  • the method for forming the current confinement layer 104 may be to oxidize the material in the region where the current confinement region 1041 is intended to be formed through an oxidation process.
  • At least one layer of the first-type semiconductor layer 101 has an aluminum content greater than 97% (defined as a layer intended to form the current confining layer 104) and greater than the active Therefore, when the oxidation process is performed, the high aluminum content layer region (defined as the intended formation of the current confinement layer 104) in the semiconductor stack 10 is oxidized inwardly from the side surface 13 The rate of is higher than that of other regions, thereby forming the current confinement region 1041 with low conductivity in the current confinement layer 104 .
  • the low-conductivity current confinement region 1041 can be formed in the semiconductor stack 10 through an ion implantation process, and the above-mentioned current conduction region 1042 can be defined at the same time through a shield. Ion implantation can be realized by implanting hydrogen ions, helium ions or argon ions in the area where the current confinement region 1041 is scheduled to be formed. lower conductivity.
  • an insulating layer 30 is formed to cover the side surface 13 , the upper surface 11 and part of the surface of the base layer 40 of the semiconductor stack 10 .
  • An opening 31 is further formed in the insulating layer 30 to expose part of the first type semiconductor layer 101 .
  • an insulating layer 30 is formed to cover the surface of the contact electrode portion 50 a.
  • An opening 32 is further formed in the insulating layer 30 to expose the contact electrode portion 50a.
  • the top view shapes of the opening 31 and the opening 32 can be circular, circular, elliptical, polygonal, square, or irregular. In this embodiment, the opening 31 and the opening 32 are circular in shape, but the disclosed Embodiments are not limited thereto.
  • an electrode structure 20 is formed in the opening 31 and on the insulating layer 30 extending to the position of the side surface 13, so that the electrode structure 20 is electrically connected to the first-type semiconductor layer 101 and passes through the semiconductor stack 10.
  • the side surface 13 of the electrode structure 20 is enlarged to increase the distribution range.
  • the extended electrode portion 50b is formed in the opening 32 and extends to the insulating layer 30 at the position of the other side 13 to form the electrode structure 50 and pass through the side 13 of the semiconductor stack 10 to enlarge the distribution range of the electrode structure 50 .
  • the base layer 40 is conductive, such as a GaAs substrate, and the electrode structure 50 is electrically connected to the second-type semiconductor layer 102 through the conductive base layer 40 .
  • FIG. 22A to FIG. 22G are schematic cross-sectional structure diagrams of multiple steps in the manufacturing process of the semiconductor laser 1003 in the embodiment of FIG. 4 .
  • an epitaxial chip 3 is provided and a protection layer PL is formed to cover the first-type semiconductor layer 101 , wherein the material of the protection layer PL can be an insulating material, including but not limited to silicon nitride.
  • the epitaxial chip 3 includes a semiconductor stack 10 formed on the base layer 40, the semiconductor stack 10 sequentially includes a first-type semiconductor layer 101, an active layer 103 and a second-type semiconductor layer 102 on the base layer 40, wherein the first Type semiconductor layer 101 and/or second type semiconductor layer 102 can be a multi-layer structure, in this implementation
  • the first-type semiconductor layer 101 is a P-type semiconductor layer
  • the second-type semiconductor layer 102 is an N-type semiconductor layer
  • the base layer 40 is a semi-insulating GaAs substrate, but the embodiments of the present disclosure are not limited thereto.
  • an etching process is performed on the aforementioned epitaxial chip 3, and a mask of a specific pattern is used to etch and remove part of the first-type semiconductor layer 101, part of the active layer 103, and part of the second-type semiconductor layer 102, And expose the end surface 102a of the second-type semiconductor layer 102 , thereby forming a mesa structure P2 on the side of the first-type semiconductor layer 101 and defining the side surface 13 , the platform portion 1022A, and the platform portion 1022B of the semiconductor stack 10 .
  • the contact electrode portion 50 a of the electrode structure 50 is formed on the end surface 102 a of the platform portion 1022A of the second-type semiconductor layer 102 , so that the contact electrode portion 50 a is electrically connected to the second-type semiconductor layer 102 .
  • a current confinement layer 104 is formed in the semiconductor stack 10 .
  • the above-mentioned epitaxial chip 3 is etched from the side of the first-type semiconductor layer 101, and a mask with a specific pattern is used to etch and remove part of the platform portions 1022A, 1022B and part of the second-type semiconductor layer 102.
  • the base layer 40 so that the second-type semiconductor layer 102 and the base layer 40 form a plateau structure P3 and define the inclined side surface 42 of the base layer 40 .
  • an insulating layer 30 is formed to cover the upper surface 11 and the side surface 13 of the semiconductor stack 10 .
  • An opening 31 is further formed in the insulating layer 30 to expose part of the first type semiconductor layer 101 .
  • the insulating layer 30 is formed successively to cover the end surfaces 102a of the platform portions 1022A and 1022B of the second-type semiconductor layer 102 , the contact electrode portion 50a and the inclined side surface 42 covering the base layer.
  • An opening 32 is further formed in the insulating layer 30 to expose the contact electrode portion 50a.
  • the electrode structure 20 is formed in the opening 31, so that the electrode structure 20 is electrically connected to the first-type semiconductor layer 101, and the electrode structure 20 is extended to the side surface 13, the platform portion 1022B and the base layer 40. on the insulating layer 30 on the side 42 to increase the distribution range of the electrode structures 20 .
  • the extended electrode portion 50b is formed at the position of the opening 32 and extends to the insulating layer 30 on the side surface 42 of the base layer 40, so that the contact electrode portion 50a and the extended electrode portion 50b contact each other and pass through the side surface 42 of the base layer 40 to enlarge the electrode The distribution range of the structure 50.
  • FIG. 23A to FIG. 23K are schematic cross-sectional structure diagrams of multiple steps in the manufacturing process of the semiconductor laser 1004 in the embodiment of FIG. 5 .
  • an epitaxial chip 4 is provided.
  • the epitaxial chip 4 includes a growth substrate formed on The semiconductor stack 10 on 2000, the semiconductor stack 10 sequentially includes the first type semiconductor layer 101, the active layer 103 and the second type semiconductor layer 102 on the growth substrate 2000, wherein the first type semiconductor layer 101 and/or the second type semiconductor layer
  • the second-type semiconductor layer 102 can be a multi-layer structure.
  • the first-type semiconductor layer 101 is an N-type semiconductor layer
  • the second-type semiconductor layer 102 is a P-type semiconductor layer, but the embodiments of the present disclosure are not limited thereto.
  • the semiconductor stack 10 can be epitaxially grown on the growth substrate 2000 .
  • the growth substrate 2000 includes Group III and V materials whose lattice constants match the semiconductor stack 10 .
  • the material of the growth substrate 2000 in this embodiment is gallium arsenide (GaAs), but the embodiments of the present disclosure are not limited thereto.
  • the material of the growth substrate 2000 may be indium phosphide (InP), sapphire, gallium nitride (GaN), or silicon carbide (SiC).
  • a protection layer PL is firstly formed to cover the second-type semiconductor layer 102 , wherein the material of the protection layer PL can be an insulating material, including but not limited to silicon nitride.
  • an etching process is performed on the aforementioned epitaxial chip 4, and a mask of a specific pattern is used to etch and remove part of the second-type semiconductor layer 102 and part of the active layer 103, and expose part of the end surface 101a of the first-type semiconductor layer 101,
  • the plateau structure P4 , the platform portion 1012A and the platform portion 1012B of the first-type semiconductor layer 101 are formed on the side of the second-type semiconductor layer 102 .
  • a current confinement layer 104 is formed in the semiconductor stack 10 .
  • an insulating layer 60 is formed to cover the second-type semiconductor layer 102 and extend to cover the platform portion 1012A and the end surface 101 a of the platform portion 1012B of the first-type semiconductor layer 101 .
  • An opening 32 is further formed in the insulating layer 60 on the mesa structure P4 to expose part of the second-type semiconductor layer 102 .
  • the electrode structure 50 is formed in the opening 32 , and the electrode structure 50 is extended to cover the side of the plateau structure P4 and the insulating layer 60 on the platform portion 1012A and the platform portion 1012B.
  • the epitaxial chip 4 formed with the insulating layer 60 and the electrode structure 50 is bonded to the base layer 40 through the adhesive layer 70 .
  • the base layer 40 is a material with high transmittance to the light emitted by the active layer 103 , such as sapphire with a transmittance greater than 80%.
  • the contact electrode part 20a of the electrode structure 20 is formed on the first type semiconductor
  • the bulk layer 101 is on a side away from the base layer 40 (that is, formed on the surface 11 of the semiconductor stack 10 ).
  • the aforementioned epitaxial chip 4 is subjected to an etching process, and a mask of a specific pattern is used to etch and remove part of the first-type semiconductor layer 101, and expose part of the insulating layer 60, thereby forming a first-type semiconductor layer.
  • the plateau structure P5 of 101 also defines the side surface 13 of the semiconductor stack 10 .
  • an insulating layer 30 is formed covering the first-type semiconductor layer 101 and covering the contact electrode portion 20 a.
  • An opening 31 is further formed in the insulating layer 30 to expose the contact electrode portion 20 a, and an opening 33 is formed in the insulating layer 60 to expose the electrode structure 50 .
  • the semiconductor stack 10 further includes a current confinement layer 105 located between the first type semiconductor layer 101 and the second type semiconductor layer 102 .
  • the current confinement layer 105 also includes a current confinement region 1051 and a current conduction region 1052 , and the current conduction region 1052 is surrounded by the current confinement region 1051 .
  • the active layer 103 has a quantum well layer 1031 , a quantum well layer 1034 and a spacer layer 1032 . Furthermore, the active layer 103 further includes a tunnel junction layer 1033 located between the quantum well layer 1031 and the quantum well layer 1034 .
  • the current confinement layer 104 is located on the quantum well layer 1031
  • the spacer layer 1032 is located between the quantum well layer 1031 and the tunneling layer 1033
  • the quantum well layer 1034 is located between the current confinement layer 105 and the tunnel layer 1033. between the second-type semiconductor layers 102 .
  • the tunneling layer 1033 includes a highly doped semiconductor material layer
  • the highly doped semiconductor material layer is at least one of a highly doped P-type semiconductor material layer and a highly doped N-type semiconductor material layer.
  • the highly doped semiconductor The material layer may be a highly doped P-type semiconductor material layer or a highly doped N-type semiconductor material layer or a mixed layer of a highly doped P-type semiconductor material layer and a highly doped N-type semiconductor material layer.
  • the material of the tunneling layer 1033 can be a material matching the base layer 40 , for example, the base layer 40 uses GaAs, and the tunneling layer 1033 can use GaAs, AlGaAs, InGaP, AlInP, AlGaInP or GaP.
  • the semiconductor laser 1005 further includes a conductive connection part 91 , a conductive connection part 92 and an insulating layer 93 .
  • the conductive connection portion 91 is located on a side away from the base layer 40 and connected to the electrode structure 20 .
  • the conductive connection portion 92 is located on a side away from the base layer 40 and connected to the electrode structure 50 .
  • the insulating layer 93 is located between the electrode structure 20 and the conductive connection portion 91 and between the electrode structure 50 and the conductive connection portion 92 to avoid short circuit caused by the electrical connection between the electrode structure 20 and the electrode structure 50 .
  • the electrode structure 50 on the surface 12 has the position of the electrode opening 52 corresponding to the current conduction region 1042 and the current conduction region 1052, wherein the electrode opening 52 has a width W1, and the current conduction region 1042 has a width W2, the current conduction region 1052 has a width W3, and the width W1 is greater than the width W2, and the width W1 is greater than or equal to the width W3. Therefore, the spatial mode distribution and light output angle of the semiconductor laser 1005 can be adjusted.
  • the thickness of the highly doped semiconductor material layer in the tunneling layer 1033 is less than 100 angstroms.
  • the thickness of the spacer layer 1032 is greater than the thickness of the quantum well layer 1031 , greater than the thickness of the quantum well layer 1034 , and greater than the thickness of the tunneling layer 1033 .
  • the energy gap of the spacer layer 1032 is larger than the energy gap of the quantum well layer 1031 and also larger than the energy gap of the quantum well layer 1034 .
  • the energy gap of the spacer layer 1032 is greater than the energy gap of the tunneling layer 1033 .
  • the spacer layer 1032 contains InGaP or AlGaAsP.
  • the semiconductor lasers 1001-1005 can be flip-chip (Flip Chip Type) vertical cavity surface-emitting laser elements, and the semiconductor lasers 1001-1005 can be flip-chip bonded to a circuit substrate (such as : printed circuit board) or packaging substrate.
  • a circuit substrate such as : printed circuit board
  • the materials of the insulating layer 30 , the insulating layer 60 and the insulating layer 93 include non-conductive materials.
  • the non-conductive material can be an organic material or an inorganic material.
  • Organic materials include epoxy resin photoresist (for example: SU8), benzocyclobutene resin (B-staged bisbenzocyclobutene, BCB), Perfluorocyclobutane (Perfluorocyclobutane, PFCB), epoxy resin (Epoxy Resin), acrylic resin (Acrylic Resin), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate Diester (PET), polycarbonate (PC), polyetherimide (Polyetherimide) or fluorocarbon polymer (Fluorocarbon Polymer).
  • epoxy resin photoresist for example: SU8
  • benzocyclobutene resin B-staged bisbenzocyclobutene, BCB
  • the inorganic material includes silica gel (Silicone) or glass (Glass), aluminum oxide, silicon nitride, silicon oxide, titanium oxide, or magnesium fluoride.
  • the insulating layer 30, the insulating layer 60 and/or the insulating layer 93 comprise a multi-layer structure (such as a distributed Bragg mirror structure formed by stacking two material layers, such as a silicon oxide layer and an oxide titanium layer).
  • the materials of the electrode structure 20, the electrode structure 50, the conductive connection part 91 and the conductive connection part 92 may include metals, such as: aluminum (Al), silver (Ag), chromium (Cr), platinum (Pt), Nickel (Ni), Germanium (Ge), Beryllium (Be), Gold (Au), Titanium (Ti), Tungsten (W) or Zinc (Zn).
  • the material of the electrode structure 20 and the electrode structure 50 can be a metal material, such as gold (Au), tin (Sn), titanium (Ti) or alloys thereof.
  • the electrode structure 20 and the electrode structure 50 may have the same material and structural composition, and the electrode structure 20 and the electrode structure 50 may each be formed as a multilayer structure with different compositions.
  • the electrode structure 20 and the electrode structure 50 may be multilayer structures.
  • the electrode structure 20 and the electrode structure 50 may be multi-layer structures.
  • the electrode structure 20 and the electrode structure 50 include, for example, a titanium (Ti)/gold (Au) layer, or a titanium (Ti)/platinum (Pt)/gold (Au) layer, or a titanium Tungsten (TiW)/gold (Au) layer.
  • the material of the current confinement layer 104 and the current confinement layer 105 can be a III-V semiconductor material.
  • the material of the current confinement layer 104 and the current confinement layer 105 is AlGaAs
  • the quantum well layer 1031, Materials of the quantum well layer 1034 , the first-type semiconductor layer 101 and the second-type semiconductor layer 102 all include aluminum.
  • the aluminum content of the current confinement layer 104 and the current confinement layer 105 is greater than the aluminum content of the quantum well layer 1031, the quantum well layer 1034, the first type semiconductor layer 101 and the second type semiconductor layer 102, for example, the current confinement layer 104, the current confinement layer
  • the aluminum content of the confinement layer 105 is greater than 97%.
  • the oxygen content of the current confinement region 1041 and the current confinement region 1051 is greater than the oxygen content of the current conduction region 1042 and the current conduction region 1052 respectively, so that the conductivity of the current confinement region 1041 and the current confinement layer 105 are respectively low.
  • the electrical conductivity of the current conduction region 1042 and the current conduction region 1052 is also important.
  • the adhesive layer 70 is a material with high light transmittance to the light emitted by the quantum well layer 1031 and the quantum well layer 1034, such as the light transmittance is greater than 80%, and the material of the adhesive layer 70 is an insulating material.
  • materials such as: benzocyclobutene resin, epoxy resin, polyimide (Polyimide), spin-on glass (spin-on glass, SOG), silica gel or perfluorocyclobutane.
  • the quantum well layer 1031 and the quantum well layer 1034 can emit infrared light with a peak wavelength between 700nm and 1700nm, red light with a peak wavelength between 610nm and 700nm, and peak wavelength between 610nm and 700nm. Yellow light with a wavelength between 530nm and 570nm, green light with a peak wavelength between 490nm and 550nm, blue or deep blue light with a peak wavelength between 400nm and 490nm, or a peak wavelength between 250nm and 400nm UV light in between.
  • the peak wavelengths of the quantum well layer 1031 and the quantum well layer 1034 are infrared light between 750 nm and 1200 nm.
  • the first-type semiconductor layer 101 and the second-type semiconductor layer 102 include a plurality of film layers with different refractive indices stacked alternately and periodically (for example: AlGaAs layers with high Al content and AlGaAs layers with low Al content alternately. Periodically stacked) to form a structure of distributed Bragg reflectors, so that the light emitted by the active layer 103 can be reflected in the two reflectors to form coherent light.
  • the materials of the first-type semiconductor layer 101 and the second-type semiconductor layer 102 include Group III and V compound semiconductors, such as AlGaInAs series, AlGaInP series, AlInGaN series, AlAsSb series, InGaAsP series, InGaAsN series, AlGaAsP series, etc., such as AlGaInP, GaAs, InGaAs, AlGaAs, GaAsP, GaP, InGaP, AlInP, GaN, InGaN, AlGaN and other compounds.
  • Group III and V compound semiconductors such as AlGaInAs series, AlGaInP series, AlGaInP series, AlInGaN series, AlAsSb series, InGaAsP series, InGaAsN series, AlGaAsP series, etc., such as AlGaInP, GaAs, InGaAs, AlGaAs, GaAsP, GaP, InGaP,
  • the above-mentioned chemical expressions include “compounds that conform to stoichiometry” and “compounds that do not conform to stoichiometry", wherein, “compounds that conform to stoichiometry” are, for example, elements of Group III
  • the total element count is the same as that of Group V elements, and conversely, the total element count of "non-stoichiometric compounds" such as Group III elements is different from that of Group V elements.
  • AlGaInAs series represents the group three elements aluminum (Al) and/or gallium (Ga) and/or indium (In), and the five group elements arsenic (As), where the three group elements (aluminum and/or gallium and/or indium) may be the same or different from the total elemental balance of the Group V element (arsenic).
  • the AlGaInAs series represents (Aly1Ga(1-y1))1-x1Inx1As, wherein, 0 ⁇ x1 ⁇ 1, 0 ⁇ y1 ⁇ 1; AlGaInP The series represents (Aly2Ga(1-y2))1-x2Inx2P, where 0 ⁇ x2 ⁇ 1, 0 ⁇ y2 ⁇ 1; the AlInGaN series represents (Aly3Ga(1-y3))1-x3Inx3N, where 0 ⁇ x3 ⁇ 1 , 0 ⁇ y3 ⁇ 1; AlAsSb series generation Table AlAsx4Sb(1-x4), where 0 ⁇ x4 ⁇ 1; InGaAsP series represents Inx5Ga1-x5As1-y4Py4, where 0 ⁇ x5 ⁇ 1, 0 ⁇ y4 ⁇ 1; InGaAsN series represents Inx6Ga1-x6
  • the packaging structure 1a includes a packaging substrate 200, a semiconductor laser 1000, and a packaging layer 300, wherein the packaging substrate 200 includes a conductive pad structure 220 and The conductive pad structure 250 .
  • the semiconductor laser 1000 in the package structure 1 a may be the aforementioned semiconductor laser 1003 .
  • the semiconductor laser 1003 includes a semiconductor stack 10 , an electrode structure 20 , an insulating layer 30 , a base layer 40 , and an electrode structure 50 .
  • the semiconductor laser 1003 has a light-emitting surface 1100 and a surface 1200 relative to the light-emitting surface 1100, the semiconductor laser 1003 is located on the package substrate 200 and the surface 1200 contacts the package substrate 200, wherein the side surface 13 of the semiconductor laser 1003
  • the electrode structure 20 and the electrode structure 50 are respectively electrically connected to the conductive pad structure 220 and the conductive pad structure 250 of the packaging substrate 200 through the connection structure 700 .
  • the electrode structure 20 and the electrode structure 50 of the semiconductor laser 1003 are extended and distributed to the side surface 13 to increase
  • the contact area with the connection structure 700 is large to avoid the problem of poor electrical contact between the semiconductor laser 1003 and the package substrate 200 in the package structure 1a (eg, electrical short circuit, electrical disconnection, etc.).
  • the encapsulation layer 300 is transparent.
  • the encapsulation layer 300 includes an encapsulation material 301, and the encapsulation layer 300 covers the semiconductor laser 1003. Further, there are a plurality of filling particles 302 in the encapsulation layer 300, thus, the distribution density or the particle size of the filling particles 302 in the encapsulation layer 300 can be varied. etc. to change the light output angle (for example, light output direction, light output range, etc.) or light output intensity distribution of the package structure 1a.
  • Fig. 7B is another schematic cross-sectional view of the package structure 1b of at least one embodiment of the present disclosure; the embodiment of Fig. 7B is similar to the embodiment of Fig. 7A, see Fig. 7B and Fig. 4 together, the main differences are as follows:
  • an insulating layer 90 is further provided on one side of the semiconductor laser 1003 (on the side 13c adjacent to the electrode structure 50), wherein the insulating layer 90 extends to the light-emitting surface 1100 to cover part of the electrode structure 20, so that when the electrode structure 50 of the semiconductor laser 1003 is electrically connected to the conductive pad structure 250 of the packaging substrate 200, an electrical short circuit caused by the connection structure 700 contacting the electrode structure 20 can be avoided. problem occurs.
  • the electrode structure 20 and the electrode structure 50 do not contact the packaging substrate 200.
  • a distance d wherein the distance d is 30 to 50 microns, so as to avoid the problem of electrical short circuit between the bottom of the semiconductor laser 1003 and the conductive structure on the packaging substrate 200 .
  • the encapsulation layer 300 (not shown) may also be covered on the semiconductor laser 1003 of the encapsulation structure 1b of this embodiment, but the embodiment of the present disclosure is not limited thereto.
  • Fig. 7C is another schematic cross-sectional view of the package structure 1c of at least one embodiment of the present disclosure; the embodiment of Fig. 7C is similar to the embodiment of Fig. 7A, and the main differences are as follows: as shown in Fig. In the structure 1c, the surface 201 of the substrate body 210 of the packaging substrate 200 is further provided with a barrier wall 400, and the semiconductor laser 1003 is disposed on the surface 201 and surrounded by the barrier wall 400, and the encapsulation layer 300 fills the area surrounded by the barrier wall 400 In and covering the semiconductor laser 1003, there are a plurality of filling particles 302 in the encapsulation layer 300, thus, the distribution density or particle size of the filling particles 302 in the encapsulation layer 300 can be changed to change the light exit angle of the encapsulation structure 1c (for example, light output direction, light output range, etc.) or light intensity distribution.
  • the light exit angle of the encapsulation structure 1c for example, light output direction, light output range, etc.
  • the conductive pad structure 220 of the packaging substrate 200 includes a conductive pad portion 220U, an internal connection portion 220I, and a conductive pad portion 220O
  • the conductive pad structure 250 of the packaging substrate 200 includes a conductive pad portion 250U, an internal connection portion 250I and conductive pad portion 250O; wherein, the conductive pad portions 220U, 250U are located on the surface 201 and surrounded by the retaining wall 400, and the inner connection portions 220I, 250I are penetrated in the substrate main body 210 and individually connected to the conductive pad portions 220U, 250U, the conductive pads 220O, 250O are located on the surface 203 of the substrate body 210 and are individually connected to the internal connection portions 220I, 250I. Referring to FIG.
  • the conductive pads 220U and 250U are provided in the area surrounded by the retaining wall 400 and covered by the encapsulation layer 300 , they can pass through the internal connection portion 220I in the substrate main body 210 , 250I and the conductive pads 220O, 250O disposed on the surface 203 of the substrate body 210, electrically connect the semiconductor laser 1003 in the package structure 1c to the external driving power through the conductive pads 220, 250.
  • FIG. 7D is another schematic cross-sectional view of the packaging structure 1d of at least one embodiment of the present disclosure.
  • FIG. 7D The embodiment of FIG. 7A is similar to the embodiment of FIG. 7A , and the main differences are as follows: As shown in FIG. 7D , the packaging structure 1 d of this embodiment further includes an adjustment layer 350 protruding from the packaging layer 300 . Thus, the surface shape of the adjustment layer 350 can be further utilized to change the light output angle (for example, light output direction, light output range, etc.) or light output intensity distribution of the encapsulation structure 1d.
  • the encapsulation layer 300 may not contain filling particles. 302, but embodiments of the present disclosure are not limited thereto.
  • Fig. 7E is a schematic cross-sectional view of a package structure 1e of at least one embodiment of the present disclosure; the embodiment of Fig. 7E is similar to the embodiment of Fig. 7D, and the main differences are as follows: as shown in Fig. 7E, the package structure 1e of this embodiment
  • the encapsulation layer 300 and the adjustment layer 350 are further filled with a plurality of filling particles 302 .
  • the adjustment layer 350 is a lens, and the upper surface of the lens may be curved or toothed. In some embodiments, the upper surface of the lens can be concave or convex.
  • the adjustment layer 350 and the encapsulation layer 300 may be made of different materials, but embodiments of the present disclosure are not limited thereto; in some embodiments, the adjustment layer 350 and the encapsulation layer 300 may also be made of the same material; In some embodiments, the adjustment layer 350 may also include a plurality of filling particles 302; in some embodiments, the adjustment layer 350 and the encapsulation layer 300 may have a one-piece structure.
  • the semiconductor laser 1000 in the package structures 1a, 1c, 1d, and 1e can be replaced by the semiconductor laser 1002 as shown in FIG. 3 .
  • the semiconductor laser 1002 is arranged on the substrate main body 210 of the packaging substrate 200 in a flip-chip manner, that is, the surface 11 of the semiconductor stack 10 of the semiconductor laser 1002 faces the substrate main body 210 and the base layer 40 is away from the substrate main body 210.
  • the electrode structures 20 and 50 on the side surface 13 of the laminated layer 10 can be electrically connected to the conductive pad structure 220 and the conductive pad structure 250 of the packaging substrate 200 respectively through the connection structure 700 .
  • the electrode structure 20 and the electrode structure 50 of the semiconductor laser 1002 are extended and distributed to the side 13 to increase
  • the contact area with the connection structure 700 is large to avoid the problem of poor electrical contact between the semiconductor laser 1002 and the package substrate 200 in the package structure.
  • the semiconductor laser 1000 in the package structure 1a, 1b, 1c, 1d, 1e can be replaced by a semiconductor laser 1004 as shown in FIG. 5 .
  • the semiconductor laser 1004 is arranged on the substrate main body 210 of the packaging substrate 200 in a flip-chip manner, that is, the surface 11 of the semiconductor stack 10 of the semiconductor laser 1004 faces the substrate main body 210 and the base layer 40 is away from the substrate main body 210.
  • the electrode structures 20 and 50 on the side surface 13 of the laminated layer 10 can be electrically connected to the conductive pad structure 220 and the conductive pad structure 250 of the packaging substrate 200 respectively through the connection structure 700 .
  • the electrode structure 20 and the electrode structure 50 of the semiconductor laser 1004 are extended and distributed to the side 13 to increase
  • the contact area with the connection structure 700 is large to avoid the problem of poor electrical contact between the semiconductor laser 1002 and the package substrate 200 in the package structure.
  • the material of the connection structure 700 includes tin.
  • the distribution area of the electrode structures 20, 30 can be increased by extending the electrode structures 20, 30 to the side surface 13 of the semiconductor stack 10, so as to facilitate transparent
  • the via connection structure 700 is electrically connected to the conductive pad structures 220 and 250 on the package substrate respectively, so that when the semiconductor laser is packaged, the distance between the conductive pad structure 220 and the conductive pad structure 250 can be reduced. The chip size is saved and the problem of poor electrical contact can be avoided.
  • the semiconductor laser 1006 in this embodiment includes a semiconductor stack 10, an electrode structure 20, an insulating layer 30, a base layer 40, an electrode structure 50, and an insulating layer 60, wherein
  • the base layer 40 is a conductive layer and can transmit light
  • the electrode structure 50 includes a contact electrode portion 50 a and an extension electrode portion 50 b.
  • the semiconductor stack 10 has a surface 11, a surface 12, and a side surface 13, the surface 12 is relative to the surface 11, the side surface 13 is located between the surface 11 and the surface 12, and the side surface 13 has an included angle ⁇ with respect to the surface 11.
  • the included angle ⁇ is substantially 90 degrees.
  • the semiconductor stack 10 includes a first-type semiconductor layer 101 , a second-type semiconductor layer 102 and an active layer 103 , wherein the active layer 103 is located between the first-type semiconductor layer 101 and the second-type semiconductor layer 102 .
  • electrode structures 20 are located on surface 11 .
  • the insulating layer 30 is located between the semiconductor stack 10 and the electrode structure 20 , wherein the insulating layer 30 has an opening 31 on the surface 11 , and the electrode structure 20 is further located in the opening 31 and contacts the first-type semiconductor layer 101 .
  • Grassroots 40 is located at the The side of the second-type semiconductor layer 102 opposite to the first-type semiconductor layer 101 .
  • the insulating layer 30 is further located between the semiconductor stack 10 and the electrode structure 50 and between the electrode structure 20 and the electrode structure 50, wherein the insulating layer 30 has a through hole 65, the through hole 65 passes through the semiconductor stack 10, and the contact of the electrode structure 50
  • the electrode portion 50 a is located in the through hole 65 and contacts the base layer 40 , so that the electrode structure 50 is electrically connected to the second-type semiconductor layer 102 through the base layer 40 .
  • the insulating layer 60 is located in the through hole 65, and the insulating layer 60 is located between the contact electrode portion 50a and the semiconductor stack 10 to isolate the contact electrode portion 50a from the first type semiconductor layer 101, and to isolate the contact electrode portion 50a from the active layer 103.
  • the extension electrode portion 50 b of the electrode structure 50 is connected to the contact electrode portion 50 a and extends from the surface 11 to the side surface 13 .
  • FIG. 8 may also have a current confinement layer (such as the current confinement layer 104 shown in FIG. 2 ), which includes a current confinement region 1041 and a current conduction region 1042 (not shown in FIG. 8 ).
  • a current confinement layer such as the current confinement layer 104 shown in FIG. 2
  • a current confinement region 1041 and a current conduction region 1042 not shown in FIG. 8 .
  • the package structure 1f of this embodiment includes a package substrate 200 and a semiconductor laser 1006, wherein the package substrate 200 includes a substrate body 210, The conductive pad structure 220 and the conductive pad structure 250 .
  • the semiconductor laser 1006 has a light-emitting surface 1100 and a surface 1200, and the semiconductor laser 1006 is arranged on the substrate body 210 in a flip-chip manner, that is, the surface 1200 of the semiconductor laser 1006 faces the substrate body 210 and the base layer 40 away from the substrate main body 210 , the electrode structures 20 and 50 on the side surface 13 of the semiconductor stack 10 can be electrically connected to the conductive pad structure 220 and the conductive pad structure 250 of the package substrate 200 through the connection structure 700 respectively.
  • FIG. 9 may also have a current confinement layer (such as the current confinement layer 104 shown in FIG. 2 ), which includes a current confinement region 1041 and a current conduction region 1042 (not shown in FIG. 9 ).
  • a current confinement layer such as the current confinement layer 104 shown in FIG. 2
  • a current confinement region 1041 and a current conduction region 1042 not shown in FIG. 9 .
  • the semiconductor laser 1007 in this embodiment includes a semiconductor stack 10, an electrode structure 20, an electrode structure 50, an electrode substrate 49, an adhesive layer 70, and an insulating layer 90. Furthermore, the semiconductor laser 1007 further has a through hole 95 , wherein the through hole 95 passes through the semiconductor stack 10 and the adhesive layer 70 .
  • the semiconductor laminate 10 has a surface 11, a surface 12 and a side surface 13, the surface 12 is relative to the surface 11, the side surface 13 is located between the surface 11 and the surface 12, and the side surface 13 has an included angle ⁇ with respect to the surface 11, in this embodiment In an example, the included angle ⁇ is substantially 90 degrees.
  • the semiconductor stack 10 includes a first-type semiconductor layer 101 , a second-type semiconductor layer 102 and an active layer 103 . Active layer 103 Located between the first type semiconductor layer 101 and the second type semiconductor layer 102 .
  • the electrode structure 20 is located on the surface 11 to be in electrical contact with the first-type semiconductor layer 101 .
  • the electrode structure 50 is located on the surface 12 to be in electrical contact with the second-type semiconductor layer 102 .
  • the electrode substrate 49 has a body 491, an electrode unit 492 and an electrode unit 493, wherein the body 491 is non-conductive, and the electrode unit 492 and the electrode unit 493 are respectively located on two sides of the body 491 and extend to the upper and lower surfaces of the body 491, and the electrode unit 492 and the electrode unit 493 are not in contact with each other.
  • the adhesive layer 70 is located between the first-type semiconductor layer 101 and the electrode substrate 49 , and the adhesive layer 70 is non-conductive.
  • the insulating layer 90 is located in the through hole 95, and the insulating layer 90 is located between the semiconductor stack 10 and the electrode structure 50 to electrically insulate the active layer 103, the first-type semiconductor layer 101 and the electrode structure 50, and the electrode structure 50 is formed from the surface 12
  • the electrode unit 493 is distributed in the through hole 95 and contacts the electrode substrate 40 .
  • the electrode structure 20 is further electrically connected to the electrode unit 492 .
  • FIG. 11 is a schematic cross-sectional view of a package structure of at least one embodiment of the present disclosure; as shown in FIG. 11 , for the aforementioned semiconductor laser 1007, the present disclosure further provides a corresponding package structure 1g, including: a package substrate 200, a semiconductor laser 1007 and a connection structure 700 , wherein the packaging substrate 200 includes a substrate body 210 , a conductive pad structure 220 and a conductive pad structure 250 .
  • the semiconductor laser 1007 has a light-emitting surface 1100 and a surface 1200.
  • the semiconductor laser 1007 is disposed on the packaging substrate 200.
  • the surface 1200 of the semiconductor laser 1007 faces the packaging substrate 200, and the light-emitting surface 1100 is away from the packaging substrate.
  • 200 that is, the electrode substrate 49 of the semiconductor laser 1007 is located on one side close to the substrate body 210, and the semiconductor stack 10 of the semiconductor laser 1007 is located on the other side away from the substrate body 210, the electrode structure 20 and the electrode unit 492 pass through the connection structure 700
  • the electrode structure 50 and the electrode unit 493 are electrically connected to the conductive pad structure 250 through the connection structure 700 .
  • the semiconductor laser 1007 of the embodiment shown in FIG. 10 may also have a current confinement layer (the current confinement layer 104 shown in FIG. 2 ), which includes a current confinement region 1041 and a current conduction region 1042 (FIG. not shown).
  • Fig. 12A is a schematic cross-sectional view of a semiconductor laser 1000a in at least one embodiment of the present disclosure;
  • the semiconductor laser 1000a of the embodiment includes half Conductor stack 10 , electrode structure 20 , insulating layer 30 , electrode structure 50 , insulating layer 60 , adhesive layer 70 , base layer 40 and optical element 80 .
  • the optical element 80 is located on the base layer 40, wherein the optical element 80 has a patterned structure, and the light emitted from the surface 12 of the semiconductor stack 10 further passes through the optical element 80 on the base layer 40 to change the direction of light travel. This changes the light output angle (eg, light output direction, light output range, etc.) or light output intensity distribution of the semiconductor laser 1000a.
  • FIG. 12B is a schematic cross-sectional view of a semiconductor laser 1000a1 in at least one embodiment of the present disclosure; as shown in FIG. 12B , in this embodiment, the semiconductor laser 1000a1 may have a plurality of optical elements 80, 85 located at different positions on the base layer 40, for example, As shown in FIG. 12B , optical element 80 is located on base layer 40 and optical element 85 is located below base layer 40 .
  • the laser chip 4 formed with the insulating layer 60 and the electrode structure 50 is bonded to the base layer 40 through the adhesive layer 70.
  • the base layer 40 has the structure of the optical element 80 and/or the optical element 85.
  • the base layer 40 with optical elements is directly bonded and packaged to the laser chip 4, so that the base layer 40 with a corresponding optical element structure can be provided according to different light output requirements, and a wafer-level optical package can be produced. Structured semiconductor lasers to meet the needs of miniaturization and various light output applications.
  • the base layer 40 can be a multi-layer structure.
  • the base layer 40 includes a first base layer 40a, a second base layer 40b and an attachment Layer 40c, second base layer 40b is bonded to first base layer 40a by adhesive layer 40c.
  • the second base layer 40b has the aforementioned optical element 80, and the optical element 80 of the second base layer 40b further changes the direction of light travel, thus changing the light output angle of the semiconductor laser 1000a2 (for example, light output direction, light range, etc.) or light intensity distribution.
  • FIG. 23F the schematic diagram of the production process of FIG. 23K and FIG. 12C together.
  • the second base layer 40b with the optical element 80 is bonded and packaged on the first base layer 40a through the adhesive layer 40c, but embodiments of the present disclosure are not limited thereto, that is, in another embodiment (not shown), the optical element 80 of the second base layer 40b faces the first base layer 40a and is bonded to the first base layer 40a through the adhesive layer 40c.
  • the structures of the optical elements 80 , 85 may be located in the surface area of the base layer 40 , or in the bulk of the base layer 40 .
  • FIG. 13 is a schematic cross-sectional view of a semiconductor laser 1000a3 in at least one embodiment of the present disclosure; as shown in FIG. 13 , the structure of the semiconductor laser 1000a3 in this embodiment is similar to that of the semiconductor laser 1004 shown in FIG. 4 , and the semiconductor laser 1000a3 further includes optical elements
  • the structure of 82 is located on the surface 12 of the semiconductor stack 10, the structure of the optical element 82 is located in the light outlet 15, and the structure of the optical element 82 is located between the insulating layer 60 and the adhesive layer 70, wherein the light outlet 15 is the electrode structure 50
  • the position of the opening, the light outlet 15 corresponds to the position of the current conduction region 1042 in the semiconductor stack 10 .
  • the optical element 82 has a metasurface structure, wherein the metasurface structure is a nanostructure with a plurality of periodic arrangements, whereby the optical element 82 can be directly formed on the semiconductor stack 10 In the light outlet 15 on the surface 12, the optical element 82 on the surface 12 can further change the light output angle (light output direction, light output range) or light output intensity distribution of the semiconductor laser 1000a3.
  • an optical element 84 is further included between the adhesive layer 70 and the base layer 40 of the semiconductor laser 1000 a 3 to change the direction of light incident on the base layer 40 .
  • an optical element 86 is provided on the light emitting side of the base layer 40 to further change the traveling direction of the light emitted from the base layer 40 .
  • the optical element 84 is a structural layer between the insulating layer 60 and the adhesive layer 70, but embodiments of the present disclosure are not limited thereto, that is, in some embodiments, the optical element 82 may be an interface structure between the insulating layer 60 and the adhesive layer 70 .
  • the optical elements 80 , 82 , 84 , 85 , and 86 can be diffractive optical element structures, microlens array structures, metasurface structures, or metalenses, or a combination of the foregoing optical element structures.
  • the structures of the optical elements 84 , 86 may be located in the surface area of the base layer 40 or in the bulk of the base layer 40 .
  • the structure of the optical element 84 can also be located in the main body of the adhesive layer 70 .
  • FIG. 14A is a schematic cross-sectional view of a semiconductor laser 1000b in at least one embodiment of the present disclosure
  • FIG. 14B is a schematic modal view of a semiconductor laser 1000b in at least one embodiment of the present disclosure
  • the semiconductor laser 1000b Including: a semiconductor stack 10, an electrode structure 20, an insulating layer 30, a base layer 40 and an electrode structure 50, wherein the base layer 40 is a semiconductor stack
  • the growth base layer of 10 that is, the base layer 40 is, for example, the growth substrate of the semiconductor stack 10 , but the embodiments of the present disclosure are not limited thereto.
  • the structure of the semiconductor laser 1000b is similar to that of the VCSEL 1 shown in FIG. 1B.
  • layer 106 and insulating layer 108 wherein the light-transmitting conductive layer 107 is stacked between the semiconductor stack 10 and the electrode structure 20, the current confinement layer 106 is stacked between the light-transmitting conductive layer 107 and the semiconductor stack 10, and the current confinement layer 106 is transparent.
  • the semiconductor stack 10 of the semiconductor laser 1000 b includes: a first-type semiconductor layer 101 , a second-type semiconductor layer 102 , an active layer 103 and a current confinement layer 104 .
  • the active layer 103 is stacked between the first-type semiconductor layer 101 and the second-type semiconductor layer 102
  • the current confinement layer 104 is stacked between the first-type semiconductor layer 101 and the active layer 103 .
  • the current confinement layer 104 includes a current conduction region 1042 and a current confinement region 1041 .
  • the current confinement layer 106 on the first-type semiconductor layer 101 has an opening 1061 , where the position of the opening 1061 corresponds to the current conducting region 1042 .
  • the light-transmitting conductive layer 107 is located on the current confinement layer 106 and in the opening 1061 and contacts the first-type semiconductor layer 101 .
  • the insulating layer 108 is located on the transparent conductive layer 107 and has an opening 1081 , wherein the opening 1081 does not overlap with the opening 1061 .
  • the first electrode layer 20 is located on the insulating layer 108 and in the opening 1081 and contacts the light-transmitting conductive layer 107 to be electrically connected to the first-type semiconductor layer 101 .
  • the second electrode layer 50 is located under the second-type semiconductor layer 102 and electrically connected to the second-type semiconductor layer 102 .
  • the light LB1 corresponding to the opening 1061 of the current confinement layer 106 after being emitted from the active layer 103, it passes through the first-type semiconductor layer 101, the light-transmitting conductive layer 107, and the insulating layer 108 in sequence, thereby Has the first light emission mode (main light emission mode); on the other hand, for the light LB2 that does not correspond to the opening 1061 of the current confinement layer 106, after it is emitted from the active layer 103, it passes through the first type semiconductor layer 101 , the current confinement layer 106, the conductive light-transmitting layer 107 and the insulating layer 108, thereby having the second light emitting mode (non-main light emitting mode).
  • the thickness configuration of the current confinement layer 106, the light-transmitting conductive layer 107, and the insulating layer 108 reduces the reflectivity of the light LB2 in the semiconductor laser 1000b, resulting in The light LB2 with the non-dominant light emitting mode cannot be emitted by the semiconductor laser 1000 d because of insufficient reflectivity.
  • the semiconductor laser of this embodiment The 1000b can only emit the light LB1 having the main emission mode, thereby reducing the emission angle of the semiconductor laser 1000b.
  • the light-transmitting conductive layer 107 is formed on the current confinement layer 106 and in the opening 1061, the light-transmitting conductive layer 107 located in the opening 1061 has a first thickness D1, and the transparent conductive layer 107 not located in the opening 1061
  • the photoconductive layer 107 has a second thickness D2, and the first thickness D1 is greater than the second thickness D2.
  • the light-transmitting conductive layer 107 of the semiconductor laser 1000b has an upper surface 1071 and a lower surface 1072, the lower surface 1072 is opposite to the upper surface 1071, and, as shown in Figure 14A, the upper surface 1071 is a plane, and the lower surface 1072
  • the opening 1061 has a downwardly protruding surface.
  • the position of the current conduction region 1042 corresponds to the position of the opening 1061
  • the current conduction region 1042 has a conduction width W4
  • the opening 1061 has an opening width W5
  • the conduction width W4 is greater than the opening width W5.
  • the insulating layer 108 is a light-permeable single-layer or multi-layer structure.
  • the light-transmitting conductive layer 107 is a single-layer or multi-layer structure.
  • the material of the current confinement layer 106 may be, but not limited to, silicon nitride or silicon dioxide.
  • the material of the light-transmitting conductive layer 107 may be, but not limited to, indium tin oxide (ITO) or indium zinc oxide (IZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the material of the insulating layer 108 may be but not limited to silicon nitride or silicon dioxide.
  • the current confinement layer 106 and the insulating layer 108 may be made of the same material, and different component names are used because they have different functions for the semiconductor laser. Specifically, in this embodiment, the current path injected into the semiconductor laser 1000 b does not pass through the current confinement layer 106 .
  • the total thickness of the current confinement layer 106, the light-transmitting conductive layer 107, and the insulating layer 108 corresponding to the region of the main light emitting mode and the current confinement layer 106, the transparent conductive layer 108 corresponding to the region of the non-main light emitting mode is ⁇ /4n, where ⁇ is the wavelength emitted by the semiconductor laser 1000b, and n is the refractive index.
  • FIG. 15A is a schematic cross-sectional view of a semiconductor laser 1000b1 according to at least one embodiment of the present disclosure
  • FIG. 15B is a schematic modal view of a semiconductor laser 1000b1 according to at least one embodiment of the present disclosure.
  • the light-transmitting conductive layer 107 of the semiconductor laser 1000b1 is formed on the current confinement layer 106 and has a first recessed region 1073, the first recessed region 1073 is located on the opening 1061, and the light-transmitting layer located in the first recessed region 1073
  • the conductive layer 107 has a first thickness D1
  • the transparent conductive layer 107 not located in the first recessed area 1073 has a second thickness D2
  • the first thickness D1 is equal to or close to the second thickness D2.
  • the light-transmissive conductive layer 107 is conformally formed on the current confinement layer 106 .
  • the insulating layer 108 of the semiconductor laser 1000b1 is formed on the light-transmitting conductive layer 107 and has a second recessed region 1082, the second recessed region 1082 is located on the first recessed region 1073, and is located in the second recessed region
  • the insulating layer 108 in the region 1082 has a third thickness D3, the insulating layer 108 not located in the second recessed region 1082 has a fourth thickness D4, and the third thickness D3 is equal to or close to the fourth thickness D4.
  • the insulating layer 108 is conformally formed on the transparent conductive layer 107 .
  • the light LB1' corresponding to the opening 1061 of the current confinement layer 106 after it is emitted from the active layer 103, it passes through the first-type semiconductor layer 101, the light-transmitting conductive layer 107 and the insulating layer in sequence.
  • Layer 108 thus having the first light emitting mode (main light emitting mode);
  • the type-one semiconductor layer 101 , the current confinement layer 106 , the conductive light-transmitting layer 107 and the insulating layer 108 have a second light-emitting mode (a non-main light-emitting mode).
  • the thickness configuration of the current confinement layer 106, the light-transmitting conductive layer 107 and the insulating layer 108 reduces the reflectivity of the light LB2' in the semiconductor laser 1000b1.
  • the semiconductor laser 1000b1 of this embodiment can only emit the light LB1' having the main emission mode, thereby narrowing the emission angle of the semiconductor laser 1000b1.
  • 16A and 16B are schematic top views of the light-emitting hole O of a semiconductor laser (for example, the semiconductor laser 1000b in FIG. 14A or the semiconductor laser 1000b1 in FIG. 15A ) of at least one embodiment of the present disclosure, to illustrate the opening 1061 of the light-emitting hole O. configuration.
  • the opening 1061 and the light-emitting hole O can be circular, and further, the opening 1061 and the light-emitting hole O can be arranged in concentric circles, but it is not limited thereto; see FIG. 16B, in this embodiment , the opening 1061 can also be multi-sided Shaped configurations, such as triangular configurations.
  • the light emitted from the active layer 103 and emitted by the light area A (for example, light LB1 or light LB1 ') is different from the light emitted from the active layer 103 and emitted by the area B (
  • light ray LB2 or light ray LB2') due to the difference in the structural layers of their individual travels (for example, light ray LB1 and light LB2, or light ray LB1' and light LB2'), the light output formed in area B is suppressed or suppressed.
  • a semiconductor laser with a small light emitting angle range that is attenuated and mainly emitted from the region A, but the embodiments of the present disclosure are not limited thereto.
  • FIG. 17 is a schematic cross-sectional view of a semiconductor laser 1000b2 in at least one embodiment of the present disclosure; as shown in FIG.
  • the position of 101DP corresponds to the center position above the current conduction region 1042 and not overlapping the current conduction region 1042 , but embodiments of the present disclosure are not limited thereto.
  • the doped region 101DP is produced by a high temperature process, so that the diffusion material (such as zinc) diffuses to the region of the current conduction region 1042 not corresponding to the opening 1061 .
  • the light corresponding to the opening 1061 of the current confinement layer 106 After it is emitted from the active layer 103, it passes through the first-type semiconductor layer 101, the light-transmitting conductive layer 107 and the insulating layer 108 in sequence, thereby having the first light emitting mode (main emission mode); on the other hand, for the light not corresponding to the opening 1061 of the current confinement layer 106, after it is emitted from the active layer 103, it passes through the first-type semiconductor layer 101, the doped region 101DP, and the current confinement Layer 106, conductive light-transmitting layer 107, and insulating layer 108, thereby having a second light emitting mode (non-main light emitting mode).
  • the configuration of the doped region 101DP is matched with the thickness configuration of the current confinement layer 106, the light-transmitting conductive layer 107, and the insulating layer 108 to reduce the non-dominant light-emitting mode.
  • the reflectivity of the light in the semiconductor laser 1000b2 leads to the fact that light with non-main emission modes cannot be emitted by the semiconductor laser 1000b2 because of insufficient reflectivity.
  • the semiconductor laser 1000b2 of this embodiment can only emit light with the main emission mode, thereby narrowing the emission angle of the semiconductor laser 1000b2.
  • FIG. 18A is a schematic cross-sectional view of a semiconductor laser 1000b3 in at least one embodiment of the present disclosure
  • FIG. 18B is a schematic modal view of a semiconductor laser 1000b3 in at least one embodiment of the present disclosure
  • the light-transmitting conductive layer 107 of the semiconductor laser 1000b3 includes a first light-transmitting conductive region 1074 and a second light-transmitting conductive region 1075
  • the second light-transmitting conductive region 1075 surrounds the first light-transmitting conductive region 1074
  • the opening 1061 is located at Between the first transparent conductive region 1074 and the second transparent conductive region 1075 .
  • the first light emission mode main light emission mode
  • the light LB1′′ not corresponding to the opening 1061 of the current confinement layer 106 after it is emitted from the active layer 103, it passes through the first type semiconductor
  • the light LB1" not corresponding to the opening 1061 of the current confinement layer 106 after it is emitted from the active layer 103, it passes through the first type semiconductor
  • the layer 101 , the current confinement layer 106 , the conductive light-transmitting layer 107 and the insulating layer 108 have a second light emission mode (non-main light emission mode).
  • the thickness configuration of the current confinement layer 106, the light-transmitting conductive layer 107 and the insulating layer 108 reduces the reflectivity of the light LB1" in the semiconductor laser 1000b3, As a result, the light LB1" having a non-main emission mode cannot be emitted by the semiconductor laser 1000b3 because of insufficient reflectivity.
  • the semiconductor laser 1000b3 of this embodiment can only emit light with a main emission mode light LB2", thereby narrowing the emission angle of the semiconductor laser 1000b3.
  • FIG. 18C to 18E are schematic top plan views of the light emitting hole O of the semiconductor laser 1000b3 according to at least one embodiment of the present disclosure, for illustrating the configuration of the opening 1061 of the current confinement layer 106 within the light emitting hole O, wherein.
  • the openings 1061 are arranged in a ring shape, but not limited thereto; referring to Fig. 18D, in this embodiment, there may be multiple openings 1061 arranged in a circle, and each opening 1061 is located at Peripheral area of the light-emitting hole; referring to FIG.
  • each opening 1061 is located in the peripheral area of the light-emitting hole. Therefore, as mentioned above, for the light with the main light emission mode, it will be emitted from the position of the area A corresponding to the opening 1061, and for the light with the non-main light emission mode, it will be emitted from the area of the light emission hole O
  • the inner region B corresponding to the distribution of the first light-transmitting conductive region 1074 emits light.
  • the light emitted from the active layer 103 and emitted by the region A for example, the light LB2 ′′
  • the light emitted from the active layer 103 and emitted by the region B for example, the light LB1 ′′
  • the structural layers passing through are different (for example, the light LB1" and the light LB2"), so the light output in the area B is suppressed or attenuated, and the light is mainly emitted from the area A.
  • the semiconductor laser with a larger light output angle range but this The disclosed embodiments are not limited thereto.
  • FIG. 19 is a schematic cross-sectional view of a semiconductor laser 1000b4 according to at least one embodiment of the present disclosure; as shown in FIG. In the defined opening, the insulating layer 108 is distributed between the reflective layer 112 and the electrode structure 20 to electrically insulate the reflective layer 112 from the electrode structure 20 .
  • the reflective layer 112 can be a distributed Bragg reflector structure. Furthermore, the reflective layer 112 can be formed by stacking two or more dielectric film layers with different refractive indices, for example: oxidation Layers of silicon and titanium oxide layers stacked on top of each other.
  • the current (carrier flow) injected from the electrode structure 20 into the first-type semiconductor layer 101 is mainly injected into the active layer 103 along the shortest impedance path PT, so the first-type semiconductor layer 101 can be reduced.
  • the number of layers of Bragg reflector layers formed by alternate stacking of semiconductor film sub-layers in the first-type semiconductor layer 101 is replaced by the dielectric Bragg reflector layer 112, so that the number of semiconductor Bragg reflector layers reduced can be reduced.
  • the light absorption effect of the layer 101 on the light output of the active layer 103 is mainly injected into the active layer 103 along the shortest impedance path PT, so the first-type semiconductor layer 101 can be reduced.
  • the number of layers of Bragg reflector layers formed by alternate stacking of semiconductor film sub-layers in the first-type semiconductor layer 101 is replaced by the dielectric Bragg reflector layer 112, so that the number of semiconductor Bragg reflector layers reduced can be reduced.
  • the width of the reflective layer 112 is less than or equal to the width of the opening 1061 .
  • the light corresponding to the opening 1061 of the current confinement layer 106 After it is emitted from the active layer 103, it passes through the first-type semiconductor layer 101, the light-transmitting conductive layer 107, the reflective layer 112, and the insulating layer 108 in sequence, thereby having a first
  • the light that does not correspond to the opening 1061 of the current confinement layer 106 after it is emitted from the active layer 103, it passes through the first type semiconductor layer 101, the current confinement layer 106, the conductive light-transmitting layer 107 and the insulating layer 108, so as to have the second light emitting mode (non-main light emitting mode).
  • the configuration of the transmissive reflective layer 112 improves the reflectivity of the light in the main light emitting mode in the semiconductor laser 1000b4, and further passes through the current confinement layer 106, the light-transmitting conductive layer 107 and the thickness of the insulating layer 108
  • the configuration reduces the reflectivity of light having non-dominant emission modes in the semiconductor laser 1000b4.
  • the semiconductor laser 1000b4 of this embodiment can only emit light with the main emission mode, thereby narrowing the emission angle of the semiconductor laser 1000b4.
  • FIG. 20 is a schematic cross-sectional view of a semiconductor laser 1000b5 in at least one embodiment of the present disclosure; as shown in FIG.
  • the semiconductor stack 10 is located on the base layer 40, and the insulating layer 30 Located between the semiconductor stack 10 and the electrode structure 20 , and the insulating layer 30 has an opening 31 , the electrode structure 20 is distributed on the insulating layer 30 and extends into the opening 31 to be electrically connected to the semiconductor stack 10 .
  • the base layer 40 is located between the semiconductor stack 10 and the electrode structure 50 .
  • the base layer 40 is conductive so that the electrode structure 50 is electrically connected to the semiconductor stack 10 .
  • the semiconductor stack 10 includes an upper mirror layer 101A, a lower mirror layer 102A and an active layer 103 , and the active layer 103 is located between the upper mirror layer 101A and the lower mirror layer 102A.
  • the lower reflector layer 102A is a second-type semiconductor layer and has a distributed Bragg reflector structure.
  • the upper reflector layer 101A includes a reflector layer 101E and a reflector layer 101I, the reflector layer 101E is located between the active layer 103 and the reflector layer 101I, and the reflector layer 101I is located between the reflector layer 101I Between the layer 101E and the electrode structure 20 , the reflector layer 101E is a first-type semiconductor layer and has a distributed Bragg reflector structure.
  • the second-type semiconductor layer is an N-type semiconductor layer
  • the first-type semiconductor layer is a P-type semiconductor layer
  • embodiments of the present disclosure are not limited thereto, that is, in another embodiment, the first-type semiconductor layer
  • the first layer is an N-type semiconductor layer
  • the second-type semiconductor layer is a P-type semiconductor layer.
  • the mirror layer 101I includes an intermediate reflection area 101I1 and a current path area 101I2.
  • the current path area 101I2 is located on both sides of the intermediate reflection area 101I1, and the electrode structure 20 passes through the opening 31 of the insulating layer 30 and the mirror layer.
  • the current path area 101I2 in 101I is electrically connected.
  • the upper reflector layer 101A has a distributed Bragg reflector structure, wherein the Bragg reflector structure located in the current path region 101I2 has doping or a higher concentration of doping (compared to the middle reflective region 101I1), and the doping in the current path region 101I2 can be formed through ion implantation or ion diffusion processes.
  • the semiconductor stack 10 further includes a current confinement layer 104 located between the active layer 103 and the upper mirror layer 101A.
  • the current confinement layer 104 includes a current confinement region 1041 and a current conduction region 1042 , and the current conduction region 1042 is surrounded by the current confinement region 1041 , and the current conduction region 1042 surrounded by the current confinement region 1041 has a distribution width W42.
  • the electrode structure 20 has an opening 21 located on the insulating layer 30 and the position of the opening 21 corresponds to the position of the current conduction region 1042 .
  • the opening 21 has an opening width W21 .
  • the middle reflective region 101I1 located between the current path regions 101I2 on both sides has The distribution width W11 and the position of the middle reflective region 101I1 correspond to the position of the current conduction region 1042 .
  • the opening width W21 of the electrode structure 20 is less than or equal to the distribution width W11 of the middle reflective region 101I1 .
  • the opening width W21 of the electrode structure 20 is greater than or equal to the distribution width W42 of the current conduction region 1042 .
  • the opening width W21 of the electrode structure 20 is greater than or equal to the distribution width W11 of the middle reflective region 101I1 , and the distribution width W11 is greater than or equal to the distribution width W42 of the current conduction region 1042 .
  • the current (carrier flow) injected from the electrode structure 20 into the upper mirror layer 101A will mainly be injected into the active layer 103 along the shortest impedance path PT, because in the middle reflective region 101I1 The Bragg mirror layer has no doping (or the middle reflective region 101I1 has a lower doping concentration compared to the mirror layer 101E), so the current (carrier flow) will follow the current flow in the upper mirror layer 101A.
  • the path region 101I2 is injected into the active layer 103 after passing through the mirror layer 101E having the second-type semiconductor layer and the current conduction region 1042, and the upward light emitted from the active layer 103 adjacent to the current conduction region 1042 will pass through the upper reflector layer 101A.
  • the middle reflective region 101I1 is emitted from the surface 11A, since the path of the main light output in the semiconductor laser 1000b5 is separated from the path of the current (carrier flow), the carrier in the upper mirror layer 101A can be reduced to the active layer. 103's light-absorbing effect.
  • the current path region 101I2 in the upper mirror layer 101A can be distributed close to the active layer 103, so as to reduce the number of layers of the second-type semiconductor layer with the mirror layer 101E, and further The light absorption effect of the second-type semiconductor layer of the mirror layer 101E on the light emitted by the active layer 103 is reduced.
  • 24A to 24C are respectively a cross-sectional schematic diagram, a bottom perspective schematic diagram and a top perspective schematic diagram of a semiconductor laser 2400 according to at least one embodiment of the present disclosure; wherein, FIG. 24A is shown along the line AA' in FIG.
  • a semiconductor laser 2400 includes a plurality of semiconductor laser units (for example, a semiconductor laser unit 2400U1 and a semiconductor laser unit 2400U2), wherein the semiconductor laser unit 2400U1 includes a plurality of high platform structures (for example, a high platform structure P1A and P2A) are located on the first type semiconductor layer 101U1, and the semiconductor laser unit 2400U2 includes a plurality of mesa structures (for example, mesa structures P3A and P4A) located on the first type on the semiconductor layer 101U2.
  • the semiconductor laser unit 2400U1 includes a plurality of high platform structures (for example, a high platform structure P1A and P2A) are located on the first type semiconductor layer 101U1
  • the semiconductor laser unit 2400U2 includes a plurality of mesa structures (for example, mesa structures P3A and P4A) located on the first type on the semiconductor layer 101U2.
  • the plateau structures P1A and P2A are columnar structures protruding on the surface of the first-type semiconductor layer 101U1
  • the plateau structures P3A and P4A are columnar structures protruding on the surface of the first-type semiconductor layer 101U2 .
  • the semiconductor laser 2400 also includes a light-transmitting base layer 40 and an adhesive layer 70.
  • the adhesive layer 70 is located between the base layer 40 and a plurality of high platform structures P1A-P4, that is, the base layer 40 is bonded to multiple high platforms through the adhesive layer 70.
  • Structures P1A-P4A As shown in FIG. 24A, a plurality of plateau structures P1A, P2A protrude upward from the surface of the first-type semiconductor layer 101U1 in the adhesive layer 70, and a plurality of plateau structures P3A, P4A protrude upward from the surface of the first-type semiconductor layer 101U2 in the adhesive layer.
  • the adhesive layer 70 covers the plateau structures P1A ⁇ P4A therebetween.
  • the plateau structures P1A, P2A, P3A, and P4A respectively include second-type semiconductor layers 102U1, 102U2, 102U3, and 102U4 and active layers 103U1, 103U2, 103U3, and 103U4, wherein the active layer 103U1 is different from the first-type semiconductor layers.
  • the active layer 103U2 is between the first-type semiconductor layer 101U1 and the second-type semiconductor layer 102U2, and the active layer 103U3 is between the first-type semiconductor layer 101U2 and the second-type semiconductor layer 102U3 between, and the active layer 103U4 is between the first-type semiconductor layer 101U2 and the second-type semiconductor layer 102U4.
  • the semiconductor laser unit 2400U1 has an electrode structure 20U1 distributed on the lower surface of the first-type semiconductor layer 101U1 and is in electrical contact with the first-type semiconductor layer 101U1 .
  • the semiconductor laser unit 2400U2 has an electrode structure 20U2 distributed on the lower surface of the first-type semiconductor layer 101U2 and is in electrical contact with the first-type semiconductor layer 101U2 .
  • the semiconductor laser unit 2400U1 has an insulating layer 60U1 located on the upper surface of the second-type semiconductor layers 102U1 and 102U2 and extending to the side surfaces of the platform structures P1A and P2A.
  • the insulating layer 60U1 is located on the electrode structure 50U1 and the platform structure P1A.
  • P2 and the insulating layer 60U1 has a plurality of openings 61U1-61U4 respectively located on the upper surfaces of the second-type semiconductor layers 102U1 and 102U2, and the electrode structure 50U1 of the semiconductor laser unit 2400U1 is located in the openings 61U1-61U4 to be compatible with the second-type semiconductor layer 102U1-61U4.
  • the semiconductor layers 102U1 and 102U2 are in electrical contact, and the electrode structure 50U1 extends from the openings 61U1 - 61U4 to the insulating layer 60U1 on the sides of the plateau structures P1A and P2A. As shown in FIG. 24A, the insulating layer 60U1 further extends from the side surface of the mesa structure P2A to the first The upper surface of the type semiconductor layer 101U1 has an opening 33U1.
  • the first-type semiconductor layer 101U1 of the semiconductor laser unit 2400U1 has a through-hole 101V1 corresponding to the position of the opening 33U1, and the electrode structure 50U1 extends along the surface of the insulating layer 60U1 on the side of the platform structure P2A to the first-type semiconductor layer.
  • the upper surface of the layer 101U1 merges into the through-hole 101V1, and the electrode structure 50U1 further extends from the through-hole 101V1 to the bottom of the first-type semiconductor layer 101U1, that is, part of the electrode structure 50U1 and the electrode structure 20U1 are both located in the first-type semiconductor layer 101U1.
  • the semiconductor laser unit 2400U1 includes an insulating layer 30U1 located between the electrode structure 50U1 and the first-type semiconductor layer 101U1 to electrically isolate the electrode structure 50U1 from the first-type semiconductor layer 101U1 .
  • the semiconductor laser unit 2400U2 has an insulating layer 60U2 located on the upper surface of the second-type semiconductor layers 102U3 and 102U4 and extending to the side surfaces of the platform structures P3A and P4A.
  • the insulating layer 60U2 is located on the electrode structure 50U2 and the platform structure P3A.
  • P4 and the insulating layer 60U2 has a plurality of openings 61U5-61U8 located on the upper surfaces of the second-type semiconductor layers 102U3 and 102U4 respectively, and the electrode structure 50U2 of the semiconductor laser unit 2400U2 is located in the openings 61U5-61U8 to be compatible with the second-type semiconductor layer 102U3-61U8.
  • the semiconductor layers 102U3 and 102U4 are in electrical contact, and the electrode structure 50U2 extends from the openings 61U5 - 61U8 to the insulating layer 60U2 on the side surfaces of the mesa structures P3A and P4A. As shown in FIG. 24A , the insulating layer 60U2 further extends from the side surface of the mesa structure P4A to the upper surface of the first-type semiconductor layer 101U2 and has an opening 33U2 .
  • the first-type semiconductor layer 101U2 of the semiconductor laser unit 2400U2 has a through hole 101V2 corresponding to the position of the opening 33U2, and the electrode structure 50U2 is extended and distributed along the surface of the insulating layer 60U2 on the side of the platform structure P4A to the first-type semiconductor
  • the upper surface of the layer 101U2 extends into the through hole 101V2, and the electrode structure 50U2 further extends from the through hole 101V2 to the bottom of the first-type semiconductor layer 101U2, that is, part of the electrode structure 50U2 and part of the electrode structure 20U2 are located below the first-type semiconductor layer 101U2.
  • the semiconductor laser unit 2400U2 includes an insulating layer 30U2 located between the electrode structure 50U2 and the first-type semiconductor layer 101U2 to electrically isolate the electrode structure 50U2 from the first-type semiconductor layer 101U2 .
  • an insulating layer 30B is filled between the first-type semiconductor layer 101U1 of the semiconductor laser unit 2400U1 and the first-type semiconductor layer 101U2 of the semiconductor laser unit 2400U2 .
  • the insulating layer structures of the insulating layers 30U1, 30B and 30U2 are connected as The insulating layer 30 is filled between the electrode structure 20U1 , the electrode structure 50U1 , the electrode structure 20U2 and the electrode structure 50U2 to isolate the electrode structure 20U1 , the electrode structure 50U1 , the electrode structure 20U2 and the electrode structure 50U2 .
  • the insulating layer 30 has a plurality of openings located on the lower surfaces of the first-type semiconductor layer 101U1 and the first-type semiconductor layer 101U2 to individually expose the electrode structure 20U1 and the electrodes at the bottom of the semiconductor laser unit 2400U1.
  • the semiconductor laser 2400 is divided into a plurality of light emitting regions 2400A, 2400B, 2400C, and 2400D, and each light emitting region has an independent pair of electrodes for addressing control of each light emitting region, but the implementation of the present disclosure
  • the number of light-emitting regions and the number of electrode structures in the example are not limited thereto, and the light-emitting position (which light-emitting region emits light) of the semiconductor laser 2400 can be controlled according to actual application requirements (for example, sensing applications, or lighting applications, etc.) and luminance (the number of luminous regions that emit light).
  • the semiconductor laser unit 2400U1 located in the light emitting region 2400A has a pair of electrode structures 20U1, 50U1
  • the semiconductor laser unit 2400U2 located in the light emitting region 2400B has another pair of electrode structures 20U2, 50U2
  • the electrode structure pair 20U1, 50U1, and the electrode structure pair 20U2, 50U2 are electrically connected to the current control device (not shown in the figure), and the current control device can judge whether to apply current to a specific electrode structure pair (electrode structure pair) according to the intensity of external light. 20U1, 50U1 and/or the pair of electrode structures 20U2, 50U2), thereby lighting up different light emitting regions of the semiconductor laser 2400, so as to achieve the effect of addressing and controlling light emission.
  • the plateau structures P1A-P4A have current confinement layers 104 respectively, which are respectively located between the active layer 103U1 and the second-type semiconductor layer 102U1, and between the active layer 103U2 and the second-type semiconductor layer 102U2. between the active layer 103U3 and the second-type semiconductor layer 102U3 , and between the active layer 103U4 and the second-type semiconductor layer 102U4 , but embodiments of the present disclosure are not limited thereto.
  • the current confinement layer 104 includes a current confinement region 1041 and a current conduction region 1042, the current confinement region 1041 surrounds the current conduction region 1042, and the conductivity of the current confinement region 1042 is higher than that of the current confinement region 1041, so that the current is concentrated conduction in the current conduction region 1042 .
  • the semiconductor laser 2400 is a package structure of a flip-chip vertical cavity surface emitting laser, and the semiconductor laser 2400 can be bonded to an external circuit substrate (such as a printed circuit board) or a package substrate using solder later.
  • an external circuit substrate such as a printed circuit board
  • the second-type semiconductor layers 102U1-102U4 and the first-type semiconductor layers 101U1, 101U2 include multiple layers with different refractive indices stacked alternately (for example: AlGaAs layers with high aluminum content and AlGaAs layers with low aluminum content content AlGaAs layers are alternately stacked periodically) to form a structure of distributed Bragg reflectors, so that the light emitted by the active layers 103U1-103U4 can be reflected in the two reflectors to form coherent light.
  • the reflectivity of the second-type semiconductor layers 102U1 and 102U2 is lower than that of the first-type semiconductor layer 101U1, and the reflectivity of the second-type semiconductor layers 102U3 and 102U4 is lower than that of the first-type semiconductor layer 101U2. reflectivity, thereby causing the coherent light to be emitted toward the direction of the base layer 40 .
  • the materials of the first-type semiconductor layers 101U1, 101U2 and the second-type semiconductor layers 102U1, 102U2, 102U3, and 102U4 include III-V compound semiconductors, for example: AlGaInAs series, AlGaInP series, AlInGaN series, AlAsSb series, InGaAsP series, InGaAsN series, AlGaAsP series, etc., such as AlGaInP, GaAs, InGaAs, AlGaAs, GaAsP, GaP, InGaP, AlInP, GaN, InGaN, AlGaN and other compounds.
  • III-V compound semiconductors for example: AlGaInAs series, AlGaInP series, AlInGaN series, AlAsSb series, InGaAsP series, InGaAsN series, AlGaAsP series, etc., such as AlGaInP, GaAs, InGaAs, AlGaAs,
  • the active layers 103U1, 103U2, 103U3, and 103U4 can emit infrared light with peak wavelengths between 700nm and 1700nm, red light with peak wavelengths between 610nm and 700nm, and peak wavelengths between 530nm and Yellow light between 570nm, green light with peak wavelength between 490nm and 550nm, blue or deep blue light with peak wavelength between 400nm and 490nm, or ultraviolet light with peak wavelength between 250nm and 400nm.
  • the peak wavelengths of the active layers 103U1 , 103U2 , 103U3 , 103U4 are infrared light between 750 nm and 1200 nm.
  • the material of the current confinement layer 104 can be the above-mentioned Group III and V semiconductor materials. As shown in FIG. Contains aluminum. The aluminum content of the current confinement layer 104 is greater than that of the active layers 103U1 , 103U2 , 103U3 , 103U4 , for example, the aluminum content of the current confinement layer 104 is greater than 97%. In this embodiment, the oxygen content of the current confinement region 1041 is greater than that of the current conduction region 1042A, so that the conductivity of the current confinement region 1041 is much lower than that of the current conduction region 1042 .
  • the adhesive layer 70 is a material with high light transmittance to the light emitted by the active layers 103U1 , 103U2 , 103U3 , 103U4 , for example, the light transmittance is greater than 80%.
  • Adhesive layer 70 comprises insulating material (non-conductive material), for example: benzocyclobutene resin, epoxy resin resin, polyimide, spin-on-glass, silicone, or perfluorocyclobutane.
  • the insulating layer 30U1, 30U2, 30B material comprises a non-conductive material.
  • the non-conductive material can be an organic material or an inorganic material.
  • Organic materials include epoxy photoresist, benzocyclobutene resin, perfluorocyclobutane, epoxy resin, acrylic resin, cycloolefin polymer, polymethyl methacrylate, polyethylene terephthalate , polycarbonate, polyetherimide or fluorocarbon polymers.
  • Inorganic materials include silica gel or glass, aluminum oxide, silicon nitride, silicon oxide, titanium oxide, or magnesium fluoride.
  • the insulating layers 30U1 , 30U2 , and 30B are one or more layers (for example, a distributed Bragg mirror structure formed by stacking two material layers, such as a silicon oxide layer and a titanium oxide layer).
  • the material of the electrode structures 20U1 , 20U2 may include metals such as aluminum, silver, chromium, platinum, nickel, germanium, beryllium, gold, titanium, tungsten or zinc.
  • the material of the electrode structures 50U1 and 50U2 can be a metal material, such as gold, tin, titanium or alloys thereof.
  • the electrode structures 20U1, 20U2 and the electrode structures 50U1, 50U2 may be one-layer or multi-layer structures.
  • the electrode structures 20U1, 20U2 and the electrode structures 50U1, 50U2 may each be formed as a multilayer structure having a different composition.
  • Fig. 25 is a schematic cross-sectional view of the packaging structure of the light emitting device 100 in at least one embodiment of the present disclosure; in this embodiment, the packaging structure of the light emitting device 100 includes: a packaging substrate 200, a semiconductor laser 1000, and an adjustment layer 300'.
  • the semiconductor laser 1000 may be a vertical resonator surface emitting laser element as shown in FIG. 1B to provide a laser light source.
  • the semiconductor laser 1000 has a light emitting surface 1001 and a surface 1002 , the surface 1002 is opposite to the light emitting surface 1001 , and the semiconductor laser 1000 is electrically connected to the packaging substrate 200 .
  • the adjustment layer 300' is located on the light-emitting surface 1001 of the semiconductor laser 1000, wherein the adjustment layer 300' includes an encapsulation material 301 and a plurality of particles 302, wherein the particles 302 are filled in the encapsulation material 301, and these particles 302 are light-transmissive or semi-transparent and dispersed in the encapsulation material 301 .
  • the bottom electrode of the semiconductor laser 1000 (for example, the electrode structure 50 of the vertical cavity surface-emitting laser device shown in FIG. 1B ) is connected to the conductive pad 2002 on the packaging substrate 200, and the top of the semiconductor laser 1000
  • the electrode (for example, the electrode structure 20 of the vertical resonator surface-emitting laser element shown in FIG. 1B ) is connected to another conductive pad 2004 on the packaging substrate 200 through wire bonding, so as to be electrically connected to the packaging substrate 200. connection, wherein the bottom electrode and the top electrode of the semiconductor laser 1000 have different electrical properties.
  • the adjustment layer 300' covers the semiconductor laser 1000, so as to contact the light emitting surface 1001 of the semiconductor laser 1000 and the packaging substrate 200.
  • the doping (filling) concentration of the filling particles 302 in the encapsulation material 301 can be changed or the size of the particles can be changed, so as to change the range of the light emitting angle or the light emitting direction of the light emitting device 1 .
  • the packaging substrate 200 can be a ceramic substrate, an injection molded or molded plastic substrate, an epoxy glass multilayer substrate (FR4), bismaleimide-triazine resin ( Bismaleimide Triazine, BT) substrate, aluminum substrate, or other substrates with conductive lines. Correspondingly designed conductive structures (not shown) are provided in the substrate for power supply connection.
  • the encapsulation material 301 of the adjustment layer 300' can be silicone, epoxy resin, a mixed form of encapsulation material, or an adhesive material used as encapsulation.
  • the filling particles 302 of the adjustment layer 300' can be silica gel, glass powder, filler or materials that can change the angle of the light source after being filled.
  • the size range of filler particles 302 may vary in size depending on the composition or form of the material.
  • the doping (filling) concentration of the filling particles 302 may have different doping (filling) concentrations due to different material components or forms and final required light angles.
  • 26 is a schematic cross-sectional view of the packaging structure of the light emitting device 100a in at least one embodiment of the present disclosure;
  • the optical encapsulation layer 500 is in contact with the light emitting surface 1001 of the semiconductor laser 1000 and the encapsulation substrate 200 , and the adjustment layer 300 ′ is located on the transparent encapsulation layer 500 .
  • the material of the light-transmitting encapsulation layer 500 may be the same as or different from the encapsulation material 301 of the adjustment layer 300'.
  • FIG. 27 is a schematic cross-sectional view of the packaging structure of the light emitting device 100b according to at least one embodiment of the present disclosure;
  • the semiconductor laser 1000 is located in the accommodating space 401
  • the adjustment layer 300 ′ is located on the supporting member 400 ′ to cover the accommodating space 401 and the semiconductor laser 1000 .
  • the supporting member 400 may be the structure of the aforementioned retaining wall 400 , but the embodiments of the present disclosure are not limited thereto.
  • the accommodating space 401 can be filled with air, or inert gas, Nitrogen or maintain vacuum.
  • the packaging structure of the light emitting device 100c also includes a barrier wall 400, wherein the barrier wall 400 and the package substrate 200 jointly define an accommodating space 401.
  • the semiconductor laser 100 and the adjustment layer 300' are located in the accommodating space 401, and the adjustment layer 300' is in contact with the light-emitting surface 1001 of the semiconductor laser 1000.
  • the adjustment layer 300' is filled into the accommodating space 401 defined by the barrier wall 400 and the packaging substrate 200, and covers the semiconductor laser 1000, thereby contacting the light-emitting surface 1001 of the semiconductor laser 1000 and the package Substrate 200.
  • the material of the retaining wall 400 can be silicone, epoxy, hybrid materials, ceramic materials (such as but not limited to alumina or aluminum nitride), metal materials, or any other material that can be used as a support. Material.
  • Fig. 29 is a schematic cross-sectional view of the packaging structure of the light emitting device 100d in at least one embodiment of the present disclosure; in this embodiment, the packaging structure of the light emitting device 100d includes: a semiconductor laser 1000 and an adjustment layer 300'.
  • the semiconductor laser 1000 has a light emitting surface 1001 and a surface 1002 , and the surface 1002 is opposite to the light emitting surface 1001 .
  • Both the electrode 1020 and the electrode 1050 of the semiconductor laser 1000 are located on the surface 1002 for subsequent electrical connection with the packaging substrate or the circuit substrate.
  • the adjustment layer 300' is located on the light-emitting surface 1001 of the semiconductor laser 1000, wherein the adjustment layer 300' includes an encapsulation material 301 and a plurality of particles 302, wherein the particles 302 are doped (filled) in the encapsulation material 301, and these particles 302 are light-transmitting Or translucent and dispersed in the encapsulation material 301 .
  • the semiconductor laser 1000 is a horizontal electrode structure, that is, the positive electrode pad and the negative electrode pad of the semiconductor laser 1000 are distributed on the same side (for example, the electrode structure 20 and electrode structure 20 of the semiconductor laser 1006 shown in FIG. 8
  • the structures 50 are distributed on the same side of the semiconductor stack 10 ), and are disposed on the packaging substrate through a flip-chip process, so as to achieve a chip scale package (Chip Scale Package, CSP).
  • CSP Chip Scale Package
  • Fig. 30A is a schematic view of the light-emitting angle of a light-emitting device without an adjustment layer 300'.
  • Fig. 30B is a schematic diagram of the light-emitting angle of the light-emitting device further comprising the adjustment layer 300' according to the embodiment of Fig. 30A.
  • the packaging structure can make the light emitting angle of the semiconductor laser 1000 change from 30 degrees (-15 degrees to +15 degrees. ) is increased to about 60 degrees (-30 degrees to +30 degrees) to meet the requirements of light emitting devices with a large light emitting angle range.
  • Fig. 31A is a schematic side perspective perspective view of the packaging structure of the optical transmitting and receiving device 200a according to at least one embodiment of the present disclosure
  • Fig. 31B is a top view of the packaging structure of the optical transmitting and receiving device 200a according to the embodiment of Fig. 31A; the optical transmitting and receiving device of this embodiment
  • the packaging structure of the transceiver device 200 a includes: a packaging substrate 200 ′, at least one light emitting element 1000 , at least one light receiving element R, and an encapsulation layer 320 .
  • the number of the light-emitting element 1000 and the light-receiving element R is 1, but it is only an example and is not limited thereto.
  • the packaging substrate 200' has a first portion 221, a second portion 222 and an insulating portion 223, the insulating portion 223 is located between the first portion 221 and the second portion 222, and the first portion 221 has a bending angle ⁇ .
  • the first portion 221 of the packaging substrate 200' can be further divided into a bent portion 2211 and an extending portion 2212, and there is a bending angle ⁇ between the bent portion 2211 and the extending portion 2212 of the packaging substrate.
  • the light-emitting element 1000 has a light-emitting surface 1201 and a surface 1202.
  • the surface 1202 is opposite to the light-emitting surface 1201 and is located on the bending portion 2211 of the first part 221 of the package substrate 200', and the light-receiving element R is located on the second part 222 of the package substrate 200'. .
  • the encapsulation layer 320 is located on the light emitting surface 1201 of the light emitting element 1200 and the light receiving surface R1 of the light receiving element R.
  • the encapsulation layer 320 has a light emitting surface 320 a and a light receiving surface 320 b corresponding to the light emitting element 1200 and the light receiving element R respectively. Since there is a bending angle ⁇ between the bending portion 2211 and the extending portion 2212 of the packaging substrate, the normal line Na corresponding to the light-emitting surface 320a of the light-emitting element 1200 and the normal line Nb corresponding to the light-receiving surface 320b of the light-receiving element R are not the same.
  • Parallel means that there is an included angle between the normal Na of the light emitting surface 320 a and the normal Nb of the light receiving surface 320 b, wherein ⁇ is not 0 degrees.
  • the included angle ⁇ is substantially equal to the bending angle ⁇ , but the embodiments of the present disclosure are not limited thereto.
  • the first part 221 of the package substrate 200' can be divided into the connected area A, area B (collectively referred to as area AB), and the connected area C, area D (collectively referred to as region CD), there is an insulating portion 223 between the region A and the region C, and an insulating portion 223 is also formed between the region B and the region D.
  • the second portion 222 of the packaging substrate 200 ′ can be divided into a region E and a region F, and an insulating portion 223 is also provided between the region E and the region F.
  • the insulating portion 223 presents a cross shape, and separates the region AB and the region CD of the first part, separates the region E and the region F of the second part, and separates the region E and the region F of the second part.
  • the area AB of the portion is separated from the area E of the second portion and the area CD of the first portion is separated from the area F of the second portion.
  • the light emitting element 1000 is located in the area A of the first part 221,
  • the bottom electrode of the light emitting element 1000 is electrically connected to the electrode pad in area A, and the top electrode of the light emitting element 1000 is electrically connected to the electrode pad in area C through the wire W;
  • the light receiving element R is located in the area of the second part 222 E, the bottom electrode of the light receiving element R is electrically connected to the electrode pad in the area E, and the top electrode of the light receiving element R is electrically connected to the electrode pad in the area F through the wire W.
  • the electrical connection between the light emitting element 1200 and the light receiving element R and the package substrate 200 ′ can be individually completed.
  • the encapsulation material is applied to cover the light-emitting element 1200 and the light-receiving element R by dispensing, and the encapsulation layer 320 is formed after the encapsulation material is shaped, so that the encapsulation structure of the light-emitting-receiving device 200 a can be obtained.
  • the encapsulation material is applied to cover the light-emitting element 1200 and the light-receiving element R by dispensing, and the encapsulation layer 320 is formed after the encapsulation material is shaped, so that the encapsulation structure of the light-emitting-receiving device 200 a can be obtained.
  • the packaging structure of the device 200 a may further include an outer frame 400 disposed on the periphery of the packaging substrate 200 ′ to surround the first portion 221 , the second portion 222 and the insulating portion 223 of the packaging substrate 200 ′.
  • the encapsulation material that has not yet been finalized but may still flow can be positioned through the configuration of the outer frame 400 .
  • the packaging structure of the optical transceiver 200a is, for example, applied to a proximity sensor (Proximity Sensor). Specifically, there is an included angle ⁇ between the normal of the light-emitting surface 320a and the normal of the light-receiving surface 320b, so that the light emitted by the light-emitting element 1000 will not be directly received by the light-receiving element R adjacent to the light-emitting element 1000 .
  • the proximity sensor when the proximity sensor is in use (such as applied to mobile phones or other electronic devices), the light emitted by the light emitting element 1000 can be prevented from being directly received by the light receiving element R, thereby avoiding false sensing of the proximity sensor. Therefore, the light emitted by the light emitting element 1000 can be reflected by the obstacle to the light receiving element R, so that the proximity sensor can sense the existence of the obstacle.
  • Fig. 32 is a top view of the packaging structure of the optical transmitting and receiving device 200b in at least one embodiment of the present disclosure.
  • the packaging structure of the optical transmitting and receiving device 200b in this embodiment includes: a packaging substrate 200', a plurality of light emitting elements Light receiving elements Ra, Rb and encapsulation layer 320 .
  • the number of light-emitting elements and light-receiving elements is the same, but it is not limited thereto; in some embodiments, one light-emitting element can be matched with multiple light-receiving elements or multiple light-emitting elements Light receiving element.
  • the first part 221 of the packaging substrate 200' further includes a plurality of first regions A', B', C', D', the insulating part 223 is further located between these first regions, and the light emitting element 1200a, 1200b is located on some of the different first regions, and the light emitting elements 1200a, 1200b are electrically connected to the rest of the different first regions through wires W. As shown in FIG.
  • the top electrodes of the light-emitting elements 1200a, 1200b are electrically connected to the first regions A' and D' on both sides through wires W, and
  • the light emitting elements 1200a, 1200b are located on different first regions, so that the bottom electrodes of the light emitting elements 1200a, 1200b are respectively electrically connected to the first regions B' and C' where they are located.
  • the second part 222 further includes a plurality of second regions E', F', G', H', the insulating part 223 is further located between these second regions, and these light-receiving regions
  • the elements Ra, Rb are located on some of the different second regions, and the light receiving elements Ra, Rb are individually electrically connected to the remaining different second regions through the wiring W.
  • the top electrodes of the light-receiving elements Ra and Rb are electrically connected to the second regions E' and H' on both sides through wires W, respectively.
  • the light-receiving elements Ra and Rb are located on different second regions F' and G', so that the bottom electrodes of the light-receiving elements Ra and Rb are individually electrically connected to the second regions F' and G where they are located. 'superior.
  • the first area of the first part 221 includes the area A' to the area D'
  • the second area of the second part 222 includes the area E' to the area H'.
  • the light-emitting element 1200a is located in the area B', the bottom electrode of the light-emitting element 1200a is electrically connected to the conductive pad in the area B', and the front electrode of the light-emitting element 1200a is electrically connected to the conductive pad in the area A' through the wiring W;
  • the device 1200b is located in the region C', the bottom electrode of the light emitting device 1200b is electrically connected to the conductive pad in the region C', and the front electrode of the light emitting device 1200b is electrically connected to the conductive pad in the region D' through the wire W.
  • the light-receiving element Ra is located in the region F', the bottom electrode of the light-receiving element Ra is electrically connected to the conductive pad in the region F', and the front electrode of the light-receiving element Ra is electrically connected to the conductive pad in the region E' through the wiring W.
  • the light receiving element Rb is located in the area G', the bottom electrode of the light receiving element Rb is electrically connected to the conductive pad in the area G', and the front electrode of the light receiving element Rb is electrically connected to the area H' through the wiring W on the conductive pad. Therefore, through this embodiment, the independent electrode configuration between the light emitting element 1200a and the light emitting element 1200b and the independent electrode configuration between the light receiving element Ra and the light receiving element Rb can be achieved.
  • Fig. 33 is a top view of a packaging structure 200b in at least one embodiment of the present disclosure; the packaging structure 200b of this embodiment includes: a packaging substrate 200', a plurality of light emitting elements 1200c, 1200d, a plurality of light receiving elements Rc, Rd, and an encapsulation layer 320.
  • the number of light-emitting elements and light-receiving elements is also two, but it is not limited thereto.
  • the first part 221 further includes a plurality of first regions, the insulating part 223 is further located between these first regions, and the light emitting elements 1200c, 1200d are located on some of the different first regions, and The light emitting elements 1200c, 1200d are electrically connected to the remaining same first region through the wiring W.
  • the light emitting elements 1200c, 1200d are located on the first areas on both sides, and the light emitting elements 1200c, 1200d are electrically connected to the on this first region in the middle.
  • the second part 222 further includes a plurality of second regions, the insulating part 223 is further located between the second regions, and the light receiving elements Rc, Rd are located in different parts of the part. On the second area, and the light receiving elements Rc, Rd are electrically connected to the remaining same second area through the wiring W. As shown in FIG. 33, viewed from the top view of the package structure 200b, the light-receiving elements Rc, Rd are located on the second regions on both sides, and the light-receiving elements Rc, Rd are electrically connected through the wiring W. connected to the second region in the middle.
  • the first area of the first part 221 includes the area A"-C
  • the second area of the second part 222 includes the area D"-F".
  • the light-emitting element 1200c is located in area A", the bottom electrode of the light-emitting element 1200c is electrically connected to the conductive pad in area A", and the front electrode of the light-emitting element 1200c is electrically connected to the conductive pad in area B" through the wiring W;
  • the device 1200d is located in the region C", the bottom electrode of the light emitting device 1200d is electrically connected to the conductive pad in the region C", and the front electrode of the light emitting device 1200d is also electrically connected to the conductive pad in the region B" through the wire W.
  • the light-receiving element Rc is located in the region D", the bottom electrode of the light-receiving element Rc is electrically connected to the conductive pad of the region D", and the front electrode of the light-receiving element Rc is electrically connected to the electrode of the region E" through the wiring W.
  • the light receiving element Rd is located in the area F"
  • the bottom electrode of the light receiving element Rd is electrically connected to the conductive pad in the area F
  • the front electrode of the light receiving element Rd is electrically connected to the area E" through the wiring W on the conductive pad.
  • the common electrode configuration between the light-emitting element 1200c and the light-emitting element 1200d and the configuration between the light-receiving element Rc and the light-receiving element Rd can be achieved.
  • common electrode configuration
  • the light emitting wavelengths of the light emitting elements may be the same or different.
  • the light emitting element may be a vertical cavity surface emitting laser (VCSEL), and the light receiving element may be a photo-detector integrated circuit (PDIC).
  • VCSEL vertical cavity surface emitting laser
  • PDIC photo-detector integrated circuit
  • the packaging structure 300a of this embodiment includes: a packaging substrate 230 , a light emitting element 1300 , a light receiving element R and an encapsulation layer 330 .
  • the packaging substrate 230 has a first portion 231 , a second portion 232 and an insulating portion 233 , and the insulating portion 233 is located between the first portion 231 and the second portion 232 .
  • the light-emitting element 1300 has a light-emitting surface 1301 and a surface 1302 .
  • the surface 1302 is opposite to the light-emitting surface 1301 and located on the package substrate 230 , and the light-emitting element 1300 is electrically connected to the package substrate 230 .
  • the light receiving element R has a light receiving surface R1 , wherein the light receiving element R is electrically connected to the packaging substrate 230 .
  • the encapsulation layer 330 includes a first encapsulation area 331 and a second encapsulation area 332 , the first encapsulation area 331 is located on the light emitting surface 1301 of the light emitting element 1300 , and the second encapsulation area 332 is located on the light receiving surface R1 of the light receiving element R.
  • the first packaging area 331 has a first packaging surface 3311
  • the second packaging area 332 has a second packaging surface 3321, and there is no difference between the normal direction N1 of the first packaging surface 3311 and the normal direction N2 of the second packaging surface 3321. parallel.
  • the first packaging area 331 has a first protrusion 3312
  • the first packaging surface 3311 is the surface of the first protrusion 3312 .
  • the first protrusion 3312 is an inclined plane, and the inclined plane climbs from the first encapsulation area 331 toward the second encapsulation area 332 of the encapsulation layer 320 , but it is not limited thereto.
  • the package structure 300a is also applied to the proximity sensor.
  • the normal direction N1 passing through the first packaging surface 3311 and the normal direction N2 of the second packaging surface 3321 are not parallel, so that the light emitted by the light emitting element 1300 will not be absorbed by the adjacent light emitting element 1300.
  • the light element R receives directly.
  • the proximity sensor when the proximity sensor is in use (such as applied to mobile phones or other electronic devices), the light emitted by the light emitting element 1300 can be prevented from being directly received by the light receiving element R, thereby avoiding false sensing of the proximity sensor. Therefore, the light emitted by the light emitting element 1300 can be reflected by the obstacle to the light receiving element R, so that the proximity sensor can sense the existence of the obstacle.
  • FIG. 35 is a schematic cross-sectional view of a packaging structure 300b according to at least one embodiment of the present disclosure.
  • the first packaging area 331 has a first convex portion 3312
  • the second packaging area 332 has a second convex portion 3322
  • the first packaging surface 3311 is the surface of the first convex portion 3312
  • the second packaging surface 3321 is the second convex portion 3322. The surface of portion 3322.
  • both the first protrusion 3312 and the second protrusion 3322 form an inclined plane
  • the inclined plane of the first protrusion 3312 climbs from the first encapsulation area 331 of the encapsulation layer 320 toward the second encapsulation area 332
  • the slope of the second protrusion 3322 climbs from the second encapsulation area 332 of the encapsulation layer 320 toward the first encapsulation area 331, so that the highest point of the first protrusion 3312 and the highest point of the second protrusion 3322 are adjacent to each other, but not This is the limit.
  • FIG. 36 is a schematic cross-sectional view of a packaging structure 300c according to at least one embodiment of the present disclosure.
  • the first packaging region 331 has a first concave portion 3313
  • the first packaging surface 3311 is a surface of the first concave portion 3313 .
  • the first concave portion 3313 completely corresponds to 1300 the light emitting surface 1301 of the light emitting element 1300 .
  • the entire light emitting surface 1301 of the light emitting element 1300 is within the range of the first concave portion 3313 .
  • FIG. 37 is a schematic cross-sectional view of a packaging structure 300d according to at least one embodiment of the present disclosure.
  • the first packaging region 331 has a first concave portion 3313
  • the first packaging surface 3311 is a surface of the first concave portion 3313 .
  • the first concave portion 3313 partly corresponds to the light emitting surface 1301 of the light emitting element 1300 . In other words, in this embodiment, part of the light emitting surface 1301 of the light emitting element 1300 is within the range of the first concave portion 3313 .
  • FIG. 38 is a schematic cross-sectional view of a packaging structure 300e according to at least one embodiment of the present disclosure.
  • the first packaging area 331 has a first molding portion 3312b, and the first molding portion 3312b protrudes from the first packaging surface 3311 .
  • the first forming portion 3312b is in a dome shape, but it is not limited thereto.
  • FIG. 39 is a schematic cross-sectional view of a packaging structure 300f according to at least one embodiment of the present disclosure.
  • the packaging structure 300 f of this embodiment includes: a packaging substrate 240 , a light emitting element 1400 , a light receiving element R, and a packaging layer 340 .
  • the packaging substrate 240 has a first portion 241 , a second portion 242 and an insulating portion 243 , and the insulating portion 243 is located between the first portion 241 and the second portion 242 .
  • the light-emitting element 1400 has a light-emitting surface 1401 and a surface 1402 .
  • the surface 1402 is opposite to the light-emitting surface 1401 and located on the package substrate 240 , and the light-emitting element 1400 is electrically connected to the package substrate 240 .
  • the light receiving element R has a light receiving surface R1 , wherein the light receiving element R is electrically connected to the packaging substrate 240 .
  • the encapsulation layer 340 includes a first encapsulation region 341 And the second encapsulation area 342, the first encapsulation area 341 is located on the light emitting surface 1401 of the light emitting element 1400, the second encapsulation area 342 is located on the light receiving surface R1 of the light receiving element R, wherein the first encapsulation area 341 has a first encapsulation surface 3411 , the first packaging area 341 further has a first molding portion 3412 , the second packaging area 342 has a second packaging surface 3421 , and the first molding portion 3412 protrudes from the first packaging surface 3411 .
  • the first forming portion 3412 is in a dome shape, but it is not limited thereto.
  • FIG. 40 is a schematic cross-sectional view of a packaging structure 300g according to at least one embodiment of the present disclosure.
  • the package substrate 240 a of this embodiment further includes a surrounding portion 244 surrounding the first portion 241 , the second portion 242 and the insulating portion 243 , thereby surrounding the encapsulation layer 340 .
  • FIG. 41 is a schematic cross-sectional view of a packaging structure 300h according to at least one embodiment of the present disclosure.
  • the package structure 300h of this embodiment further includes a barrier layer BL located between the first package region 341 and the second package region 342 .
  • the blocking layer BL is made of opaque material, such as plastic or black epoxy resin.
  • the cross-sectional shape of the barrier layer BL is not rectangular. In other words, in some embodiments, the cross-sectional shape of the barrier layer BL may also be trapezoidal or irregular.
  • FIG. 42 is a schematic cross-sectional view of a packaging structure 300i according to at least one embodiment of the present disclosure.
  • the encapsulation layer 340 of the encapsulation structure 300i of this embodiment has a gap GS located between the first encapsulation area 341 and the second encapsulation area 342 .
  • the gap GS between the first encapsulation area 341 and the second encapsulation area 342 can pass through, so that the side light emitted by the light emitting element 1400 needs to pass through the first encapsulation area 341 of the encapsulation layer 340, the gap GS and the encapsulation layer 340.
  • the second encapsulation region 342 of the layer 340 and because the encapsulation layer 340 and the gap GS have different refractive indices, the lateral light emitted by the light emitting element 1400 is less likely to be directly received by the light receiving element R, thereby avoiding the sensing of the proximity sensor error.
  • FIG. 43 is a schematic cross-sectional view of a packaging structure 300j according to at least one embodiment of the present disclosure.
  • the packaging structure 300j further includes a retaining wall 400a, wherein the retaining wall 400a and the packaging substrate 240 jointly define a first accommodating space 401a and a second accommodating space 402a, and the light emitting element 1400 is located in the first accommodating space 401a, and the light receiving element R is located in the second accommodating space 402a.
  • first storage space 401a has a first opening 401a1
  • the second accommodating space 402a has a second opening 402a1.
  • a part of the first packaging surface 3411 is exposed from the first opening 401a1, and a part of the second packaging surface 3421 is exposed from the second opening 402a1.
  • a part of the first packaging surface 3411 is blocked by the barrier wall 400a, and a part of the second packaging surface 3421 is similarly blocked by the barrier wall 400a.
  • the barrier wall 400a can be made of opaque material, such as plastic or black epoxy resin. Therefore, according to this embodiment, part of the first encapsulation surface 3411 and part of the second encapsulation surface 3421 can be shielded through the barrier wall 400a, so that the light emitted by the light emitting element 1400 is not easily received by the light receiving element R directly, thereby Avoid sensing errors caused by proximity sensors.
  • FIG. 44A is a schematic cross-sectional view of a packaging structure 300k according to at least one embodiment of the present disclosure
  • FIG. 44B is a top view of the packaging structure 300k according to the embodiment of FIG. 44A
  • the package structure 300k of this embodiment includes: a package substrate 250a, a plurality of light emitting elements 1500a, 1500b, at least one light receiving element R, and a package layer 350'.
  • the number of light-emitting elements 1500a and 1500b is two, and the number of light-receiving element R is one, so that a single light-receiving element is combined with multiple light-emitting elements, but it is not limited thereto.
  • the packaging substrate 250 has a first portion 251 , a second portion 252 and an insulating portion 253 , and the insulating portion 253 is located between the first portion 251 and the second portion 252 .
  • the first part 251 has a plurality of regions, respectively corresponding to the light emitting elements 1500a, 1500b.
  • Each light-emitting element 1500a, 1500b has a light-emitting surface 1501 and a surface 1502.
  • the surface 1502 is opposite to the light-emitting surface 1501 and is located on the package substrate 250, and each light-emitting element 1500a, 1500b is electrically connected to the package substrate 250.
  • the light receiving element R has a light receiving surface R1 , wherein the light receiving element R is electrically connected to the packaging substrate 250 .
  • the sub-region B1 of the first part 251 corresponds to the light-emitting element 1500a
  • the sub-region C1 of the first part 251 corresponds to the light-emitting element 1500b
  • the light-emitting element 1500a is located in area B1
  • the bottom electrode of the light-emitting element 1500a is electrically connected to the conductive pad in area B1
  • the front electrode of the light-emitting element 1500a is electrically connected through the wiring W.
  • the light-emitting element 1500b is located in the area C1, the bottom electrode of the light-emitting element 1500b is electrically connected to the conductive pad in the area C1, and the front electrode of the light-emitting element 1500b is electrically connected to the area through the wiring W on the conductive pad of D1.
  • the light receiving element R is located in the area E1, and the bottom electrode of the light receiving element R is electrically connected to connected to the conductive pad in the area E1, and the front electrode of the light receiving element R is electrically connected to the conductive pad in the area F1 through the wire W.
  • the encapsulation layer 350' includes a first encapsulation area 351 and a second encapsulation area 352, the first encapsulation area 351 is located on the light emitting surface 1501 of the light emitting element 1500a, 1500b, and the second encapsulation area 352 is located on the light receiving surface R1 of the light receiving element R superior.
  • the first encapsulation area 351 corresponding to the sub-area A1 and the sub-area B1 has an encapsulation surface 3511a
  • the first encapsulation area 351 corresponding to the sub-area C1 and the sub-area D1 has an encapsulation surface 3511b
  • the second encapsulation area 352 has a second encapsulation surface 3521 .
  • the surface of the first encapsulation area 351 corresponding to the sub-area A1 and the sub-area B1 of the first part 251 is the encapsulation surface 3511a
  • the first encapsulation area 351 corresponds to the sub-area C1 and the sub-area of the first part 251.
  • the surface of the region D1 is the package surface 3511 b
  • the surface of the second package region 352 corresponding to the sub-region E1 and the sub-region F1 of the second portion 252 is the second package surface 3521 .
  • the normal directions N1a, N1b of the packaging surfaces 3511a, 3511b are not parallel to each other, and the normal direction N1a, N1b of each of the packaging surfaces 3511a, 3511b is different from the normal direction N2 of the second packaging surface 3521. are not parallel to each other.
  • the package structure 300k is also applied to the proximity sensor.
  • the normal directions N1a, N1b passing through the packaging surfaces 3511a, 3511b are not parallel to each other, and the normal directions N1a, N1b of each of the packaging surfaces 3511a, 3511b are in line with the normal direction of the second packaging surface 3521.
  • the line directions N2 are not parallel to each other, so that the light emitted from the light emitting elements 1500a, 1500b will not be directly received by the light receiving elements R adjacent to the light emitting elements 1500a, 1500b.
  • the proximity sensor when the proximity sensor is in use (such as applied to mobile phones or other electronic devices), the light emitted by the light-emitting elements 1500a and 1500b can be prevented from being directly received by the light-receiving element R, thereby avoiding false sensing of the proximity sensor. Therefore, the light emitted by the light-emitting elements 1500a and 1500b can be reflected by the obstacle to the light-receiving element R, so that the proximity sensor can sense the existence of the obstacle.

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Abstract

一种半导体激光器（1000、1001、1002、1003、1004、1005、1006、1007、1000a、1000a1、1000a2、1000a3、1000b、1000b1、1000b2、1000b3、1000b4、1000b5、2400），包括半导体叠层（10）、第一电极结构、第二电极结构以及绝缘层（30、30B、30U1、30U2、60、60U1、60U2、90、93、108）。半导体叠层（10）具有第一表面（11）、第二表面（12）以及侧面（13）。半导体叠层（10）包括第一型半导体层（101、101U1、101U2）、第二型半导体层（102、102U1、102U2、102U3、102U4）以及位于第一型半导体层（101、101U1、101U2）与第二型半导体层（102、102U1、102U2、102U3、102U4）之间的活性层（103、103A、103U1、103U2、103U3、103U4）。第一电极结构位于第一表面（11）及侧面（13）上。第二电极结构位于第二型半导体层（102、102U1、102U2、102U3、102U4）上并且电性连接第二型半导体层（102、102U1、102U2、102U3、102U4）。绝缘层（30、30B、30U1、30U2、60、60U1、60U2、90、93、108）位于半导体叠层（10）与第一电极结构之间以及位于半导体叠层（10）与第二电极结构之间。绝缘层（30、30B、30U1、30U2、60、60U1、60U2、90、93、108）具有开口（31）位于第一表面（11）上，且第一电极结构分布至开口（31）中并接触第一型半导体层（101、101U1、101U2）。

Description

半导体激光器及其封装结构
本申请要求于2022年2月25日递交的美国申请63/313,768以及2022年6月30日递交的美国申请63/357,203的优先权，在此全文引用上述美国申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种半导体激光器及其封装结构。
背景技术
垂直腔面发射激光(Vertical Cavity Surface Emitting Laser，VCSEL)是半导体激光器的一种，由于其为外延面出光的结构优点，并随着各种物联网产品、智能电子产品及智能感测产品等更多应用需求浮现及市场需求驱动，垂直腔面发射激光元件已逐步从网通产品市场拓展深入到各类智能产品中(例如，光通讯光源模块、智能平板手机\智能耳机中的近接传感器(Proximity Sensor)、深度\距离\3D传感器、先进驾驶辅助系统的光达传感器、微投影显示器光源或面板、互动装置中的眼动追踪器(Eye Tracker)等产品中)。
上述大多数的应用产品中，由于产品开发及产品使用上的各种需求(例如，低成本、轻便易携、小型化、与其他元件间的整合匹配性高、车用应用上的严格环境可靠度、长产品寿命、低电耗\长使用时间、高频率电性驱动运作等)，因此垂直腔面发射激光装置的封装结构需针对不同应用产品的需求做适应性的调整，以满足前述各项需求规格。
发明内容
本公开提供多个实施例的半导体激光器以及包含所述半导体激光器的封装结构。在一些实施例中，可利用将电极结构配置于半导体激光器的半导体叠层的斜侧面，因此，可使得激光元件于封装后，其封装结构的尺寸得以减缩；
或是，在一些实施例中，在不能加大封装结构的限制下，通过半导体叠层的斜侧面上的电极结构已进行电性邦定，以维持或提升封装结构的可靠性。
本公开的实施例提供一种半导体激光器，其包括：半导体叠层、第一电极结构以及第一绝缘层。半导体叠层具有第一表面、第二表面以及侧面。第一表面相对该第二表面，侧面位于第一表面及第二表面之间。半导体叠层包含第一型半导体层、第二型半导体层以及活性层。活性层位于第一型半导体层及第二型半导体层之间。第一电极结构位于第一表面及侧面上。本实施例中，第一电极结构位于第一表面并延伸至侧面。第一绝缘层位于半导体叠层与第一电极结构之间。第一绝缘层具有第一开口，第一开口位于第一表面上，并且第一电极结构更位于第一开口中并接触第一型半导体层。
在一些实施例中，该侧面相对于该第一表面具有夹角θ，该夹角θ的角度分布范围为90度(含)至120度(含)之间。
在一些实施例中，半导体激光器更包含一基层，位于该第二型半导体层相对于该第一型半导体层的一侧。
在该些实施例中，半导体激光器更包括：第二电极结构，位于第一表面及侧面上，其中，第一绝缘层更位于该半导体叠层与该第二电极结构之间。
在一些实施例中，第二电极结构及第一绝缘层更从侧面上延伸分布至基层上，且第一绝缘层更具有第二开口位于基层的表面上，且第二电极结构分布至第二开口中并接触基层，以使第二电极结构透过基层而电性连接至第二型半导体层。
在一些实施例中，该基层具有表面以及连接该表面的侧面。半导体叠层中的第二型半导体层更包含第一平台部与第二平台部侧向延伸分布于表面上，第一绝缘层及第二电极结构更位于第一平台部及第二平台部的表面上，第一绝缘层具有第二开口于第一平台部上，且第二电极结构分布至第二开口中并接触第二型半导体层的第一平台部。
在一些实施例中，第二电极结构不仅位于第一绝缘层的第二开口中，并延伸至基层的侧面上，第一电极结构亦从半导体叠层的侧面延伸分布经第二平台部上至基层的侧面。
在本实施例中，半导体激光器更包括第二绝缘层以及黏着层，其中第二 绝缘层位于半导体叠层与第二电极结构之间，黏着层位于半导体叠层与基层之间。第二电极结构位于第一表面上、侧面上及第二表面上。第一绝缘层位于半导体叠层与第二电极结构之间，其中第一绝缘层具有多个第二开口，第二开口位于第二表面上，且第二电极结构更位于第二开口中并接触第二型半导体层。
在一些实施例中，第二电极结构不仅位于第一绝缘层的第二开口中，还位于半导体叠层的第一表面并延伸至侧面以及第二表面上。
在一些实施例中，黏着层及基层为可透光，黏着层位于第二型半导体层上并覆盖第二电极结构以及第二绝缘层，而基层位于黏着层上。
在一些实施例中，半导体叠层更包括：第一电流限制层，位于活性层与第一型半导体层之间，第一电流限制层包括第一电流限制区以及第一电流导通区，且第一电流导通区被第一电流限制区环绕。
在一些实施例中，第一型半导体层中或该第二型半导体层中、或该第一型半导体层中与该第二型半导体层中具有反射镜层。
在一些实施例中，该半导体叠层更包括第一电流限制层以及第二电流限制层。第一电流限制层位于活性层与第一型半导体层之间，第一电流限制层包括第一电流限制区以及第一电流导通区，该第一电流导通区被该第一电流限制区环绕。第二电流限制层位于第一型半导体层与第二型半导体层之间，第二电流限制层包括第二电流限制区以及第二电流导通区，该第二电流导通区被该第二电流限制区环绕。该活性层具有第一量子井层、第二量子井层以及间隔层，且活性层更包括隧穿结(Tunnel Junction)层，位于第一量子井层与第二量子井层之间。第一电流限制层位于第一量子井层上，间隔层位于第一量子井层与穿隧接面层之间，而第二量子井层位于第二电流限制层与第二型半导体层之间。
在一些实施例中，半导体激光器更包括第一导电连接部、第二导电连接部以及第三绝缘层。第一导电连接部位于远离基层的一侧并连接第一电极结构。第二导电连接部位于远离基层的一侧并连接第二电极结构。第三绝缘层位于第一电极结构与第一导电连接部之间以及第二电极结构与第二导电连接部之间。
在一些实施例中，位于第二表面上的第二电极结构具有电极开口对应第一电流导通区及第二电流导通区的位置，其中电极开口的宽度大于第一电流导通区的宽度，且电极开口的宽度大于或等于第二电流导通区宽度。
在一实施例中，提供一种封装结构，其包括：封装基板、半导体激光器以及封装层。半导体激光器具有出光面以及表面相对于出光面，半导体激光器位于封装基板上且表面接触封装基板，其中，位于半导体激光器的侧面上的第一电极结构及第二电极结构分别透过连接结构电性连接至封装基板的第一导电接垫结构及第二导电接垫结构。封装层包括封装材料，封装层覆盖半导体激光器。封装层中具有多个填充粒子。
在一些实施例中，半导体激光器的一侧面上(邻近第二电极结构的侧面上)更具有第三绝缘层，其中第三绝缘层延伸分布至出光面上以覆盖部分的第一电极结构。第一电极结构与第二电极结构的最低处至封装基板的上表面之间相隔有间距，其中间距为30至50微米。
在一些实施例中，封装基板的基板主体的第一表面上更设有挡墙，且半导体激光器设于第一表面上并被挡墙围绕，封装层填充于挡墙所围绕的区域中并覆盖半导体激光器。
在一些实施例中，封装基板的第一导电接垫结构包括第一导电接垫部、第一内连接部及第二导电接垫部，且，封装基板的第二导电接垫结构包括第三导电接垫部、第二内连接部及第四导电接垫部；其中，第一导电接垫部及第三导电接垫部位于封装基板的第一表面上并被挡墙围绕，第一内连接部及第二内连接部穿设于基板主体中且个别连接第一导电接垫部及第三导电接垫部，第二导电接垫部及第四导电接垫部位于基板主体的第二表面上且个别连接第一内连接部及第二内连接部。
在一实施例中，提供一种半导体激光器，其包括：半导体叠层、第一电极结构、第一绝缘层、基层、第二电极结构以及第二绝缘层，其中，基层为可导电层，第二电极结构包含第二接触电极部及第二延伸电极部。半导体叠层具有第一表面、第二表面以及侧面，第二表面相对于第一表面，侧面位于第一表面及第二表面之间，侧面相对于第一表面具有夹角θ，夹角θ的角度实质上为90度。半导体叠层包含第一型半导体层、第二型半导体层以及活性 层，其中，活性层位于第一型半导体层与第二型半导体层之间。第一电极结构位于第一表面上。第一绝缘层位于半导体叠层与第一电极结构之间，其中第一绝缘层具有第一开口，第一开口位于第一表面上，且第一电极结构更位于第一开口中并接触第一型半导体层。基层位于第二型半导体层相对于第一型半导体层的一侧。第一绝缘层更位于半导体叠层与第二电极结构之间以及第一电极结构与第二电极结构之间，其中第一绝缘层具有通孔，通孔穿过半导体叠层，第二电极结构的第二接触电极部位于通孔中并接触基层，以使第二电极结构透过基层电性连接第二型半导体层。第二绝缘层位于通孔中，且第二绝缘层位于第二接触电极部与半导体叠层之间，以隔绝第二接触电极部与第一型半导体层，以及隔绝第二接触电极部与活性层。第二电极结构的第二延伸电极部连接第二接触电极部并自第一表面上延伸分布至侧面上。
在一实施例中，提供一种封装结构，其包括：封装基板以及半导体激光器，其中封装基板包括基板主体、第一导电接垫结构及第二导电接垫结构。半导体激光器具有出光面以及表面，半导体激光器的半导体叠层的表面朝向基板主体且基层远离基板主体，位于半导体叠层的侧面上的第一电极结构及第二电极结构可分别透过连接结构电性连接至封装基板的第一导电接垫结构及第二导电接垫结构。
在一实施例中，提供一种半导体激光器，其包括：半导体叠层、第一电极结构、第二电极结构、电极基板、黏着层以及绝缘层。半导体激光器更具有贯孔，其中贯孔穿过半导体叠层及黏着层。半导体叠层具有第一表面、第二表面以及侧面，第二表面相对于第一表面，侧面位于第一表面及第二表面之间，侧面相对于第一表面具有夹角θ，夹角θ的角度实质上为90度。半导体叠层包含第一型半导体层、第二型半导体层以及活性层。活性层位于第一型半导体层与第二型半导体层之间。第一电极结构位于第一表面上以与第一型半导体层电性接触。第二电极结构位于第二表面上以与第二型半导体层电性接触。电极基板具有本体、第一电极单元以及第二电极单元，其中本体为不导电，且第一电极单元与第二电极单元分别位于本体的二侧面并延伸分布至本体的上下表面，且第一电极单元与第二电极单元彼此不接触。黏着层位于第一型半导体层与电极基板之间，且黏着层为不导电。绝缘层位于贯孔中， 且绝缘层位于半导体叠层与第二电极结构之间以使活性层、第一型半导体层与第二电极结构电性绝缘，第二电极结构自第二表面上延伸分布于贯孔中并接触电极基板的第二电极单元。其中，第一电极结构更电性连接第一电极单元。
在一实施例中，提供一种封装结构，其包括：封装基板、半导体激光器以及连接结构，其中封装基板包括基板主体、第一导电接垫结构及第二导电接垫结构。半导体激光器具有出光面以及表面，半导体激光器置于封装基板上，半导体激光器的电极基板位于接近基板主体的一侧，且半导体激光器的半导体叠层位于远离基板主体的另一侧，第一电极结构与第一电极单元透过连接结构电性连接至封装基板的第一导电接垫结构，第二电极结构与第二电极单元透过连接结构电性连接第二导电接垫结构。
在一实施例中，提供一种半导体激光器，其包括：半导体叠层、第一电极结构、第一绝缘层、第二电极结构、第二绝缘层、黏着层、基层以及光学元件。光学元件位于基层上。
在一些实施例中，半导体激光器可具有多个光学元件分别位于基层的不同位置。在一些实施例中，第一光学元件位于基层上，而第二光学元件位于基层下。
在一些实施例中，基层包含第一基层、第二基层及附着层，第二基层通过附着层邦定至第一基层。在一些实施例中，第二基层上具有光学元件。
在一些实施例中，光学元件的结构可位于基层的表面区域或位于基层的主体中。
在一些实施例中，半导体激光器更包括第三光学元件。第三光学元件的结构位于半导体叠层的第二表面上，第三光学元件的结构位于第二电极结构的出光口中，且第三光学元件的结构位于第二绝缘层及黏着层之间，其中出光口的位置会对应于半导体叠层中第一电流导通区的位置。
在一些实施例中，第三光学元件具有超表面(Metasurface)结构，其中，超表面结构为具有复数个周期排列奈米结构体。在一些实施例中，半导体激光器的黏着层与基层之间更包括第四光学元件，用以变化入射至基层的光的行进方向。更进一步地，在基层的出光侧更具有第五光学元件，以再进一步 变化出射基层的光的行进方向。
在一些实施例中，第四光学元件为介于第二绝缘层及黏着层之间的结构层，但本公开的实施例不限于此。在一些实施例中，第三光学元件可为第二绝缘层与黏着层之间的接口结构。
在一些实施例中，前述光学元件可例如包含衍射光学元件(Diffraction Optical Element，DOE)结构、微透镜阵列(Micro Lens Array，MLA)结构、超表面结构或超颖透镜(Metalens)、或前述各种光学元件结构的组合。
在一些实施例中，光学元件的结构可位于基层的表面区域或位于基层的主体中，本公开的实施例不以此为限。
在一些实施例中，光学元件的结构亦可位于黏着层的主体中，本公开的实施例不以此为限。
在一实施例中，提供一种半导体激光器，其包括：半导体叠层、第一电极结构、第一绝缘层、基层以及第二电极结构。
在一些实施例中，半导体激光器更包含透光导电层、电流局限层以及绝缘层。其中，透光导电层堆叠于半导体叠层与第一电极结构之间，电流局限层堆叠于透光导电层与半导体叠层之间，且电流局限层为可透光。半导体激光器的半导体叠层包括：第一型半导体层、第二型半导体层、活性层以及电流限制层。活性层堆叠于第一型半导体层及第二型半导体层之间。电流限制层堆叠于第一型半导体层及活性层之间。其中，电流限制层包括电流导通区及电流限制区。位于第一型半导体层上的电流局限层具有导通开口，其中导通开口的位置对应于电流导通区。透光导电层位于电流局限层上及导通开口中并接触第一型半导体层。绝缘层位于透光导电层上，并具有绝缘开口，其中绝缘开口与导通开口不重迭。第一电极层位于绝缘层上及绝缘开口中并接触透光导电层以电性连接第一型半导体层。第二电极层位于第二型半导体层下并电性连接第二型半导体层。
在一些实施例中，透光导电层形成于电流局限层上及导通开口中，位于导通开口的透光导电层具有第一厚度，不位于导通开口的透光导电层具有第二厚度，第一厚度大于第二厚度。
在一些实施例中，半导体激光器的透光导电层具有上表面及下表面，下 表面相对于上表面，且，上表面为平面，下表面具有向下凸出面位于导通开口中。
在一些实施例中，电流导通区的位置对应导通开口的位置。
在一些实施例中，电流导通区具有导通宽度，导通开口具有开口宽度，导通宽度大于开口宽度。
在一些实施例中，半导体激光器的透光导电层形成于电流局限层上并具有第一凹陷区，第一凹陷区位于导通开口上，位于该第一凹陷区的透光导电层具有第一厚度，不位于第一凹陷区的透光导电层具有第二厚度，且第一厚度等于或接近第二厚度。在一实施例中，透光导电层是共形(Conformal)形成于电流局限层上。
在一些实施例中，半导体激光器的绝缘层形成于透光导电层上并具有第二凹陷区，第二凹陷区位于第一凹陷区上，位于第二凹陷区的绝缘层具有第三厚度，不位于第二凹陷区的绝缘层具有第四厚度，第三厚度等于或接近第四厚度。在一些实施例中，绝缘层是共形(Conformal)形成于透光导电层上。
在一些实施例中，半导体激光的第一型半导体层中更具有掺杂区，在本实施例中，掺杂区的位置对应于电流导通区上方且不重叠于电流导通区的中心位置。
在一些实施例中，半导体激光器的透光导电层包含第一透光导电区及第二透光导电区，第二透光导电区围绕第一透光导电区，且导通开口位于第一透光导电区与第二透光导电区之间。
在一些实施例中，半导体激光器更包括反射层位于透光导电层的上表面，且反射层位于第一电极结构所界定的开口中，且绝缘层分布于反射层与第一电极结构之间以使反射层与第一电极结构电性绝缘。
在一些实施例中，反射层可例如为布拉格反射(DBR)结构，更进一步反射层可由不同折射率的两种以上的介电层交替堆叠而形成，例如氧化硅层和氧化钛层。
在一些实施例中，反射层的宽度会小于等于导通开口的宽度。
在一些实施例中，半导体激光器包括：半导体叠层、基层、第一电极结构、第二电极结构以及第一绝缘层。半导体叠层位于基层上，第一绝缘层位 于半导体叠层与第一电极结构之间，且第一绝缘层具有第一开口，第一电极结构分布于第一绝缘层上并延伸至第一开口中以与半导体叠层电性连接。基层位于半导体叠层与第二电极结构之间，基层为可导电，以使第二电极结构电性连接半导体叠层。半导体叠层包含上反射镜层、下反射镜层以及活性层，活性层位于上反射镜层及上反射镜层之间。本实施例中，下反射镜层为第二型半导体层且具有布拉格反射结构(DBR)。上反射镜层包含第一上反射镜层及第二上反射镜层，第一上反射镜层位于活性层与第二上反射镜层之间，第二上反射镜层位于第一上反射镜层与第一电极结构之间，其中第一上反射镜层为第一型半导体层且具有布拉格反射结构(DBR)。第二上反射镜层包含中间反射区及电流路径区，电流路径区位于中间反射区的两侧，且第一电极结构透过第一绝缘层的第一开口与第二上反射镜层中的电流路径区电性连接。
在一些实施例中，上反射镜层具有布拉格反射结构(DBR)，其中位于电流路径区中的布拉格反射结构具有掺杂或较高浓度的掺杂(相较于中间反射区)。
在一些实施例中，半导体叠层更包括电流限制层，位于活性层与上反射镜层之间。电流限制层包括电流限制区以及电流导通区，且电流导通区被电流限制区环绕。其中，被电流限制区环绕的电流导通区具有第一分布宽度。
在一些实施例中，第一电极结构界定电极开口位于第一绝缘层上且电极开口的位置对应电流导通区的位置，电极开口具有开口宽度。位于两侧电流路径区之间的中间反射区具有第二分布宽度，中间反射区的位置对应电流导通区的位置。
在一些实施例中，第一电极结构的开口宽度小于或等于中间反射区的第二分布宽度。
在一些实施例中，第一电极结构的开口宽度大于或等于电流导通区的第一分布宽度。
在一些实施例中，第一电极结构的开口宽度大于或等于中间反射区的第二分布宽度，且第二分布宽度大于等于电流导通区的第一分布宽度。
附图说明
附图用于更好地理解本公开的实施例，不构成对本公开的实施例的不当限定，其中：
图1A为垂直腔面发射激光(VCSEL)的外延叠层结构的剖面示意图；
图1B为一种垂直腔面发射激光元件剖面示意图；
图2为本公开至少一实施例的半导体激光器的剖面示意图；
图3为本公开至少一实施例的半导体激光器的剖面示意图；
图4为本公开至少一实施例的半导体激光器的剖面示意图；
图5为本公开至少一实施例的半导体激光器的剖面示意图；
图6为本公开至少一实施例的半导体激光器的剖面示意图；
图7A为本公开至少一实施例的封装结构的剖面示意图；
图7B为本公开至少一实施例的封装结构的另一剖面示意图；
图7C为本公开至少一实施例的封装结构的另一剖面示意图；
图7D为本公开至少一实施例的封装结构的另一剖面示意图；
图7E为本公开至少一实施例的封装结构的剖面示意图；
图8为本公开至少一实施例的半导体激光器的剖面示意图；
图9为本公开至少一实施例的封装结构的剖面示意图；
图10为本公开至少一实施例的半导体激光器的剖面示意图；
图11为本公开至少一实施例的封装结构的剖面示意图；
图12A为本公开至少一实施例的半导体激光器的剖面示意图；
图12B为本公开至少一实施例的半导体激光器的剖面示意图；
图12C为本公开至少一实施例的半导体激光器的剖面示意图；
图13为本公开至少一实施例的半导体激光器的剖面示意图；
图14A为本公开至少一实施例的半导体激光器的剖面示意图；
图14B为本公开至少一实施例的半导体激光器的模态示意图；
图15A为本公开至少一实施例的半导体激光器的剖面示意图；
图15B为本公开至少一实施例的半导体激光器的模态示意图；
图16A与图16B为本公开至少一实施例的半导体激光器的发光孔上视示意图；
图17为本公开至少一实施例的半导体激光器的剖面示意图；
图18A为本公开至少一实施例的半导体激光器的剖面示意图；
图18B为本公开至少一实施例的半导体激光器的模态示意图；
图18C至图18E为本公开至少一实施例的半导体激光器的发光孔上视示意图；
图19为本公开至少一实施例的半导体激光器的剖面示意图；
图20为本公开至少一实施例的半导体激光器的剖面示意图；
图21A至图21F为图3实施例的制作流程的多个步骤的剖面结构示意图；
图22A至图22G为图4实施例的制作流程的多个步骤的剖面结构示意图；
图23A至图23K为图5实施例的制作流程的多个步骤的剖面结构示意图；
图24A至图24C分别为本公开至少一实施例的半导体激光器的剖面示意图、下视透视示意图和上视透视示意图；
图25为本公开至少一实施例发光装置的封装结构的剖面示意图；
图26为本公开至少一实施例发光装置的封装结构的剖面示意图；
图27为本公开至少一实施例的发光装置的封装结构的剖面示意图；
图28为本公开至少一实施例的发光装置的封装结构的剖面示意图；
图29为本公开至少一实施例的发光装置的封装结构的剖面示意图；
图30A为未具有调整层的发光装置的发光角度示意图；
图30B是根据图30A实施例更包含调整层的发光装置的发光角度示意图；
图31A为本公开至少一实施例的光发收装置的封装结构的侧视透视示意图；
图31B是根据图31A实施例的光发收装置的封装结构的上视图；
图32为本公开至少一实施例的光发收装置的封装结构上视图；
图33为本公开至少一实施例的封装结构的上视图；
图34为本公开至少一实施例的封装结构的剖面示意图；
图35为本公开至少一实施例的封装结构的剖面示意图；
图36为本公开至少一实施例的封装结构的剖面示意图；
图37为本公开至少一实施例的封装结构的剖面示意图；
图38为本公开至少一实施例的封装结构的剖面示意图；
图39为本公开至少一实施例的封装结构的剖面示意图；
图40为本公开至少一实施例的封装结构的剖面示意图；
图41为本公开至少一实施例的封装结构的剖面示意图；
图42为本公开至少一实施例的封装结构的剖面示意图；
图43为本公开至少一实施例的封装结构的剖面示意图；
图44A为本公开至少一实施例的封装结构的剖面示意图；以及
图44B为图44A实施例的封装结构的上视图。
具体实施方式
以下结合附图对本公开的示范性实施例做出说明，其中包括本公开实施例的各种细节以助于理解，应当将它们认为仅仅是示范性的。因此，本领域普通技术人员应当认识到，可以对这里描述的实施例做出各种改变、组合或调整，而不会背离本公开的范围和精神。
本说明书中使用的「第一」、「第二」、「第三」等名词用语是用以标示及说明各对应实施例的特征，并不必然具有任何顺序、阶层或前后的意思(例如，空间位置、时间顺序、步骤顺序等)。
本说明书中使用的「上」、「下」、「左」、「右」、「前」、「后」、「较低」、「较高」、「顶部」或「底部」等用词，是用以描述各图式中的一个元件对于另一元件(或一个结构对于另一结构)的空间分布相对关系。能理解的是，如果将图式所示的结构上下颠倒，则所叙述在「下」、「较低」侧的元件将会成为在「上」、「较高」侧的元件。
在以倒装芯片(flip-chip)封装方式将激光晶粒元件邦定至电路基板时，若电路基板上的正电极垫与负电极垫过于接近，则于倒装芯片封装过程中施用锡膏时，有可能因锡膏侧溢而将正电极垫与负电极垫相互连接，进而造成短路的问题；又若电路基板上的正负电极垫及/或激光器晶粒元件上的电极接垫的尺寸太小，则于倒装芯片封装对位过程中，也有可能因对位机构的对位 误差而造成激光器晶粒元件的电极与电路基板上的电极垫错位，进而造成短路、断路或邦定不良的问题。因此，为了避免所述问题，电路基板上的正电极垫与负电极垫之间的距离需大于一定的间距(例如，约需维持90微米的间距)，且电极垫(electrode pad)大小亦需要有足够的尺寸(例如，一般为80微米×50微米)以提供足够的电压，然而这样会造成激光器元件于封装后，整体封装尺寸难以再大幅减缩。
图1A为垂直腔面发射激光的外延叠层结构的剖面示意图；图1B为一种垂直腔面发射激光元件的剖面示意图；参见图1A，垂直腔面发射激光元件1包含以半导体外延技术形成在导电成长基板40G的半导体叠层10，其中，半导体叠层10包括第一型半导体反射镜层101U、第二型半导体反射镜层102D、及活性层(active layer)103A堆叠于第一型半导体反射镜层101U及第二型半导体反射镜层102D之间。
本公开以第一型及第二型分别指称不同电性的半导体结构，若半导体结构以空穴(hole)作为多数载流子(carrier)即为P型半导体，若半导体结构以电子(electron)作为多数载流子即为N型半导体，举例而言，第一型半导体层为P型半导体，且第二型半导体层为N型半导体，反之亦可。
参见图1B，垂直腔面发射激光元件1还包含电连接第一型半导体反射镜层101U的电极结构20及电连接第二型半导体反射镜层102D的电极结构50。经由电极结构20及电极结构50提供驱动电源至半导体叠层结构10中，驱使第一型半导体反射镜层101U与第二型半导体反射镜层102D的载流子(电子及空穴)注入活性层103A中，以使活性层103A发光。
第一型半导体反射镜层101U及第二型半导体反射镜层102D皆为高反射率层，因为活性层103A位于第一型半导体反射镜层101U及第二型半导体反射镜层102D之间的谐振腔区域中，使得由活性层103A发射的光可以在其中来回反射以形成相干光(coherent light)。其中，第一型半导体反射镜层101U及第二型半导体反射镜层102D可包含分布式布拉格反射镜(Distributed Bragg Reflector，DBR)结构，如图1B所示，在本实施例中，分布式布拉格反射镜结构可由不同折射率的两种以上的膜层相互堆叠而形成，例如由AlAs/GaAs、AlGaAs/GaAs或InGaP/GaAs所形成。
如图1B所示，在垂直腔面发射激光元件1中，第一型半导体反射镜层101U及第二型半导体反射镜层102D两者中的一个反射镜层的反射率较低于另一个反射镜层的反射率，例如，当第一型半导体反射镜层101U的反射率低于第二型半导体反射镜层102D的反射率，则于第一型半导体反射镜层101U及第二型半导体反射镜层102D之间形成的相干光会大部分穿透第一型半导体反射镜层101U以形成半导体叠层10于表面101S的出光L。
如图1B所示，垂直腔面发射激光元件1更包括电流限制层104A在活性层103A与第一型半导体层101U之间。电流限制层104A包括电流限制区1041A及电流导通区1042A，且电流导通区1042A被电流限制区1041A环绕。电流导通区1042A的导电率高于电流限制区1041A，以使电流集中导通于电流导通区1042A中。
图2为本公开至少一实施例的半导体激光器1001的剖面示意图；本实施例的半导体激光器1001包括：半导体叠层10、电极结构20及绝缘层30。半导体叠层10具有表面11、表面12及侧面13。表面12相对表面11，侧面13在表面11及表面12之间。半导体叠层10包含第一型半导体层101、第二型半导体层102及活性层103。活性层103在第一型半导体层101及第二型半导体层102之间。本实施例中，第一型半导体层101为P型半导体层，第二型半导体层102为N型半导体层，但本公开的实施例不限于此。
参见图2，电极结构20位于表面11及侧面13上。本实施例中，电极结构20位于表面11且延伸至侧面13上。因此，后续在将半导体激光器1001电性邦定至封装基板上的导电接垫时，由于电极结构20延伸至侧面13，而可在不加大半导体激光器1001的尺寸下，增加半导体激光器1001的电极结构20与封装基板之间的可邦定面积。如此，使得半导体激光器1001在进行封装时，可以在维持封装基板的导电接垫间距的前提下减省芯片尺寸。
如图2所示，绝缘层30在半导体叠层10与电极结构20之间。绝缘层30具有开口31位于表面11上，电极结构20更分布于开口31中并且接触第一型半导体层101。
如图2所示，侧面13相对于表面11具有夹角θ，夹角θ的角度分布范围为90度至120度之间。举例来说，对于原本呈长方形且高度为10微米的 半导体叠层10而言，若夹角θ是120度时，则原本的芯片尺寸为240微米×140微米，透过此实施例的配置而得到的芯片尺寸将缩小为217微米×128微米。又对于原本呈长方形且高度为30微米的电极结构20而言，若夹角θ是120度时，则原本的芯片尺寸为240微米×140微米，透过此实施例的配置而得到的芯片尺寸将更缩小为171微米×105微米。因此，透过将电极配置于半导体叠层10的侧面13，从而可使得半导体激光器1001于封装后，其封装结构的尺寸得以减缩。
图3及图4分别为本公开至少一实施例的半导体激光器1002、1003的剖面示意图；在这些实施例中，半导体激光器1002、1003的半导体叠层与图2的半导体激光器1001的半导体叠层10结构相似，半导体激光器1002、1003更包含基层40，基层40位于第二型半导体层102相对于第一型半导体层101的一侧。
参见图3及图4，基层40可以是半导体叠层10的成长基板，即半导体叠层10直接成长于基层40上，或者，参见图5，基层40也可以是半导体叠层10的封装基板，即半导体叠层10先成长在成长基板上，然后再转移至基层40上，以进行后续各项封装程序。
参见图3及图4，半导体激光器1002、1003更包括电极结构50位于表面11及侧面13上，且绝缘层30更位于半导体叠层10与电极结构50之间。
在一些实施例中，如图3所示，基层40为可导电，电极结构50及绝缘层30更从侧面13延伸分布至基层40上，且绝缘层30更具有开口32位于基层40的表面上，且电极结构50分布至开口32中并接触基层40，以使电极结构50透过基层40而电性连接至第二型半导体层102。因此，依据本实施例的半导体激光器1002，可以更进一步增加半导体激光器1002的电极结构20及电极结构50个别与封装基板的导电接垫之间的可邦定面积。
在一些实施例中，如图4所示，基层40为可导电或电性绝缘，基层40具有表面41以及连接表面41的侧面42，半导体叠层10中的第二型半导体层102更包含平台部1022A及1022B侧向延伸分布于表面41上，绝缘层30及电极结构50更位于平台部1022A及1022B的表面上，绝缘层30具有开口32于平台部1022A上，且电极结构50分布至开口32中并接触第二型半 导体层102的平台部1022A。在本实施例中，电极结构50不仅位于绝缘层30的开口32中，并延伸至基层40的侧面42上，电极结构20亦从半导体叠层10的侧面13延伸分布经平台部1022B上至基层40的侧面42。因此，依据本实施例的半导体激光器1003，可以更进一步增加半导体激光器1003的电极结构20及电极结构50个别与封装基板的导电接垫之间的可邦定面积。
图5为本公开至少一实施例的半导体激光器1004的剖面示意图；在本实施例中，半导体激光器1004更包括绝缘层60以及黏着层70，其中绝缘层60位于半导体叠层10与电极结构50之间，黏着层70位于半导体叠层10与基层40之间。
参见图5，在本实施例中，电极结构50位于表面11上、侧面13上及表面12上。本实施例中，半导体叠层10的侧面13进一步分为第一侧面13a(上侧面)及第二侧面13b(下侧面)绝缘层30位于半导体叠层10与电极结构50之间，其中绝缘层30具有多个开口32，开口32位于表面12上，且电极结构50更位于开口32中并接触第二型半导体层12。在本实施例中，电极结构50不仅位于绝缘层30的开口32中，还位于半导体叠层10的表面11并延伸至侧面13以及表面12上。此外，本实施例中，半导体叠层10的第一型半导体层101具有侧向延伸突出于第一侧面13a的平台部1012A、1012B因此，依据本实施例的半导体激光器1004，可以进一步增加电极结构20与封装基板上的导电接垫之间的接触面积以及电极结构50与封装基板上的导电接垫之间的接触面积。
参见图5，本实施例中，黏着层70及基层40为可透光，黏着层70位于第二型半导体层12上并覆盖电极结构50以及绝缘层60，而基层40位于黏着层70上。
在一些实施例中，第一型半导体层101及第二型半导体层102具有分布式布拉格反射镜的结构，使得由活性层103发射的光可以在两个反射镜中反射以形成相干光。
参见图3至图5，在一些实施例中，半导体叠层10更包括电流限制层104，位于活性层103与第一型半导体层101之间。电流限制层104包括电流限制区1041以及电流导通区1042，且电流导通区1042被电流限制区1041 环绕。电流导通区1042的导电率高于电流限制区1041，以使电流集中导通于电流导通区1042中。在一些实施例中(未示出)，电流限制层亦可设置在活性层103与第二型半导体层102之间；或者，于半导体叠层10中，多个电流限制层分别设置在活性层103与第一型半导体层101之间以及活性层103与第二型半导体层102之间。
为了说明图3至图5实施例所示的半导体激光器1002～1004的制程，请先分别参见图21A至图21F、图22A至图22G以及图23A至图23K。
图21A至图21F为图3实施例的半导体激光器1002的制作流程的多个步骤的剖面结构示意图；如图21A所示，提供外延芯片2。所述外延芯片2包括形成于基层40上的半导体叠层10，半导体叠层10依序包含第一型半导体层101、活性层103与第二型半导体层102位于基层40上，其中第一型半导体层101及/或第二型半导体层102可为多层结构，在本实施例中，第一型半导体层101为P型半导体层，第二型半导体层102为N型半导体层。半导体叠层10可以外延方式成长于基层40上，外延方式包含但不限于金属有机化学气相沉积法、氢化物气相外延法、分子束外延法、液相外延法等。基层40包含但不限于三五族材料，其晶格常数与半导体叠层10互相匹配，本实施例的基层40的材料为砷化镓(GaAs)。在其他实施例中，基层40的材料可为磷化铟(InP)、蓝宝石(sapphire)、氮化镓(GaN)或碳化硅(SiC)等。
接着，如图21B所示，首先形成保护层PL覆盖于外延芯片2的第一型半导体层101上，其中保护层PL的材料可为绝缘材料，包含但不限于氮化硅。接着，对前述芯片2实施蚀刻程序，搭配使用特定图样的屏蔽以蚀刻去除部分的第一型半导体层101、部分的活性层103与部分的第二型半导体层102并暴露部分基层40，从而在第一型半导体层101侧形成高台结构P1并界定出半导体叠层10的侧面13。
接着，如图21C所示，形成电极结构50的接触电极部50a在基层40上。
接着，如图21D所示，在半导体叠层10中形成电流限制层104。本实施例中，电流限制层104的形成方法可以是透过氧化制程以将预定形成电流限制区1041的区域产生材料氧化。举例来说，第一型半导体层101的其中至少一层的铝含量大于97％(定义为预定形成电流限制层104的层)且大于活 性层103及第二型半导体层102的铝含量，因此，在进行氧化制程时，半导体叠层10中的高铝含量层区域(定义为预定形成电流限制层104)从侧面13向内被氧化的速率高于其他区域，进而形成电流限制层104中具有低导电率的电流限制区1041。或者，可透过离子布植制程在半导体叠层10中形成低导电率的电流限制区1041，并通过屏蔽同时定义上述的电流导通区1042。离子布植可以是通过在预定形成电流限制区1041的区域布植氢离子、氦离子或氩离子等来实现，电流限制区1041的离子浓度远大于电流导通区1042，使电流限制区1041具有较低的导电率。
接着，如图21E所示，再形成绝缘层30覆盖在半导体叠层10的侧面13、上表面11以及部份的基层40的表面。进一步在绝缘层30中形成开口31以暴露部分的第一型半导体层101。同样地，如图21E所示，再形成绝缘层30覆盖在接触电极部50a的表面。进一步在绝缘层30中形成开口32以暴露接触电极部50a。开口31与开口32的上视形状可为环形、圆形、椭圆形、多边形、正方形、或不规则形状等，在本实施例中，开口31与开口32的形状为环状，但本公开的实施例不限于此。
最后，如图21F所示，形成电极结构20在开口31中及延伸至侧面13的位置的绝缘层30上，以使电极结构20与第一型半导体层101电性连接并通过半导体叠层10的侧面13以加大电极结构20的分布范围。并且，形成延伸电极部50b在开口32中并延伸至另一侧面13的位置的绝缘层30上，以形成电极结构50并通过半导体叠层10的侧面13以加大电极结构50的分布范围。本实施例中，基层40为可导电，例如GaAs基板，电极结构50通过导电基层40与第二型半导体层102电性导通。
图22A至图22G为图4实施例的半导体激光器1003的制作流程的多个步骤的剖面结构示意图。
如图22A所示，提供外延芯片3并形成保护层PL覆盖在第一型半导体层101上，其中保护层PL的材料可为绝缘材料，包含但不限于氮化硅。所述外延芯片3包括形成在基层40上的半导体叠层10，半导体叠层10依序包含第一型半导体层101、活性层103与第二型半导体层102位在基层40上，其中第一型半导体层101及/或第二型半导体层102可为多层结构，在本实施 例中，第一型半导体层101为P型半导体层，第二型半导体层102为N型半导体层，基层40为半绝缘GaAs基板，但本公开的实施例不限于此。
接着，如图22B所示，对前述外延芯片3实施蚀刻程序，搭配使用特定图样的屏蔽以蚀刻去除部分的第一型半导体层101、部分的活性层103与部分的第二型半导体层102，并暴露出第二型半导体层102的端面102a，从而在第一型半导体层101侧形成高台结构P2并界定出半导体叠层10的侧面13、平台部1022A及平台部1022B。
接着，如图22C所示，形成电极结构50的接触电极部50a在第二型半导体层102的平台部1022A的端面102a上，以使接触电极部50a与第二型半导体层102电性连接。
接着，如图22D所示，在半导体叠层10中形成电流限制层104。
接着，如图22E所示，从第一型半导体层101侧对前述外延芯片3实施蚀刻程序，搭配使用特定图样的屏蔽以蚀刻去除部分的第二型半导体层102的平台部1022A、1022B以及部分的基层40，从而使第二型半导体层102与基层40形成高台结构P3并界定出基层40的倾斜侧面42。
接着，如图22F所示，形成绝缘层30覆盖在半导体叠层10的上表面11以及侧面13。进一步在绝缘层30中形成开口31以暴露部分的第一型半导体层101。同样地，如图22F所示，接续形成绝缘层30覆盖在第二型半导体层102的平台部1022A、1022B的端面102a、接触电极部50a以及覆盖基层的倾斜侧面42。进一步在绝缘层30中形成开口32以暴露接触电极部50a。
接着，如图22G所示，形成电极结构20在开口31中，以使电极结构20与第一型半导体层101电性连接，且延伸形成电极结构20至侧面13、平台部1022B及基层40的侧面42的绝缘层30上，以加大电极结构20的分布范围。并且，形成延伸电极部50b在开口32的位置并延伸至基层40的侧面42的绝缘层30上，由此接触电极部50a与延伸电极部50b相互接触并通过基层40的侧面42以加大电极结构50的分布范围。
图23A至图23K为图5实施例的半导体激光器1004的制作流程的多个步骤的剖面结构示意图。
如图23A所示，提供外延芯片4。所述外延芯片4包括形成在成长基板 2000上的半导体叠层10，半导体叠层10依序包含第一型半导体层101、活性层103与第二型半导体层102位在成长基板2000上，其中第一型半导体层101及/或第二型半导体层102可为多层结构，本实施例的第一型半导体层101为N型半导体层，第二型半导体层102为P型半导体层，但本公开的实施例不限于此。半导体叠层10可以外延方式成长于成长基板2000上。成长基板2000包含三五族材料，其晶格常数与半导体叠层10互相匹配，本实施例的成长基板2000的材料为砷化镓(GaAs)，但本公开的实施例不限于此。在其他实施例中，成长基板2000的材料可为磷化铟(InP)、蓝宝石(sapphire)、氮化镓(GaN)或碳化硅(SiC)等。
接着，如图23B所示，首先形成保护层PL覆盖在第二型半导体层102上，其中保护层PL的材料可为绝缘材料，包含但不限于氮化硅。接着，对前述外延芯片4实施蚀刻程序，搭配使用特定图样的屏蔽以蚀刻去除部分的第二型半导体层102与部分的活性层103，并暴露出部分的第一型半导体层101的端面101a，从而在第二型半导体层102侧形成高台结构P4、第一型半导体层101的平台部1012A及平台部1012B。
接着，如图23C所示，在半导体叠层10中形成电流限制层104。
接着，如图23D所示，形成绝缘层60覆盖在第二型半导体层102上并延伸覆盖至第一型半导体层101的平台部1012A及平台部1012B的端面101a。进一步在高台结构P4上的绝缘层60中形成开口32以暴露部分的第二型半导体层102。
接着如图23E所示，形成电极结构50在开口32中，并使电极结构50延伸覆盖至高台结构P4的侧边以及平台部1012A及平台部1012B上的绝缘层60上。
接着如图23F所示，通过黏着层70将形成有绝缘层60与电极结构50的外延芯片4邦定至基层40。本实施例中，基层40为对活性层103发出的光具有高透光率的材料，如透光率大于80％的蓝宝石。当形成有绝缘层30与电极结构50的外延芯片4邦定至基层40后，移除位于第一型半导体层101侧的成长基板2000，而形成如图23G所示的结构。
接着如图23H所示，形成电极结构20的接触电极部20a在第一型半导 体层101远离基层40的一侧(即形成于半导体叠层10的表面11上)。
接着如图23I所示，对前述外延芯片4实施蚀刻程序，搭配使用特定图样的屏蔽以蚀刻去除部分的第一型半导体层101，并暴露出部分的绝缘层60，从而形成第一型半导体层101的高台结构P5并界定出半导体叠层10的侧面13。
接着，如图23J所示，形成绝缘层30覆盖在第一型半导体层101上以及覆盖在接触电极部20a。进一步在绝缘层30中形成开口31以暴露接触电极部20a，在绝缘层60中形成开口33以暴露电极结构50。
接着，如图23K所示，形成延伸电极部20b在至开口31中并使延伸电极部20b延伸形成至侧面13上的绝缘层30表面上，以使电极结构20与第一型半导体层101电性连接，并通过半导体叠层10的侧面13以加大电极结构20的分布范围。另，形成延伸电极部50b在开口33中并使延伸电极部50b延伸形成至侧面13上的绝缘层30表面上，以使电极结构50从第二型半导体层102侧延伸分布至第一型半导体层101侧，并通过半导体叠层10的侧面13以加大电极结构50的分布范围。
图6为本公开至少一实施例的半导体激光器1005的剖面示意图；本实施例的半导体激光器1005与图5的半导体激光器1004的结构相似，在本实施例中，夹角θ实质上为90度，但本公开的实施例不限于此。此外，本实施例中，半导体叠层10除了第一电流限制层104以外，更包括电流限制层105位在第一型半导体层101及第二型半导体层102之间。电流限制层105亦包括电流限制区1051以及电流导通区1052，且电流导通区1052被电流限制区1051环绕。本实施例中，活性层103具有量子阱层1031、量子阱层1034以及间隔层1032，更进一步，活性层103更包括隧穿结层1033位在量子阱层1031与量子阱层1034之间。
参见图6，本实施例中，电流限制层104位在量子阱层1031上，间隔层1032位在量子阱层1031与隧穿层1033之间，而量子阱层1034位在电流限制层105与第二型半导体层102之间。其中，隧穿层1033包括高掺杂半导体材料层，且高掺杂半导体材料层为高掺杂P型半导体材料层以及高掺杂N型半导体材料层中的至少其中一者。换句话说，本实施例中，高掺杂半导体 材料层可以是高掺杂P型半导体材料层或是高掺杂N型半导体材料层或者是高掺杂P型半导体材料层与高掺杂N型半导体材料层的混合层。另外，隧穿层1033的材料可以是与基层40匹配的材料，例如基层40使用GaAs，则隧穿层1033可以使用GaAs、AlGaAs、InGaP、AlInP、AlGaInP或GaP。
在一些实施例中，参见图6，半导体激光器1005更包括导电连接部91、导电连接部92以及绝缘层93。导电连接部91位在远离基层40的一侧并连接电极结构20。导电连接部92位在远离基层40的一侧并连接电极结构50。绝缘层93位在电极结构20与导电连接部91之间以及电极结构50与导电连接部92之间，以避免电极结构20与电极结构50之间的电性连接而造成短路。
在一些实施例中，参见图6，位在表面12上的电极结构50具有电极开口52对应电流导通区1042及电流导通区1052的位置，其中电极开口52具有宽度W1，电流导通区1042具有宽度W2，电流导通区1052具有宽度W3，并且宽度W1大于宽度W2，且宽度W1大于或等于宽度W3。此，可以调变半导体激光器1005的空间模态分布与出光角度。
在一些实施例中，隧穿层1033中的高掺杂半导体材料层的厚度小于100埃。
在一些实施例中，间隔层1032的厚度大于量子阱层1031的厚度，大于量子阱层1034的厚度，亦大于隧穿层1033的厚度。
在一些实施例中，间隔层1032的能隙大于量子阱层1031的能隙，亦大于量子阱层1034的能隙。
在一些实施例中，间隔层1032的能隙大于隧穿层1033的能隙。
在一实施例中，间隔层1032中含有InGaP或AlGaAsP。
依据一些实施例，半导体激光器1001～1005可为倒装芯片式(Flip Chip Type)垂直腔面发射激光元件，并且，后续可使用焊料将半导体激光器1001-1005倒装芯片邦定至电路基板(例如：印刷电路板)或封装基板。
依据一些实施例，绝缘层30、绝缘层60及绝缘层93的材料包含非导电材料。非导电材料可以是有机材料或无机材料。有机材料包含环氧树脂光刻胶(例如：SU8)、苯并环丁烯树脂(B-staged bisbenzocyclobutene，BCB)、 全氟环丁烷(Perfluorocyclobutane，PFCB)、环氧树脂(Epoxy Resin)、丙烯酸树脂(Acrylic Resin)、环烯烃聚合物(COC)、聚甲基丙烯酸甲酯(PMMA)、聚对苯二甲酸乙二酯(PET)、聚碳酸酯(PC)、聚醚酰亚胺(Polyetherimide)或氟碳聚合物(Fluorocarbon Polymer)。无机材料包含硅胶(Silicone)或玻璃(Glass)、氧化铝、氮化硅、氧化硅、氧化钛或氟化镁。在一些实施例中，绝缘层30、绝缘层60及/或绝缘层93包含多层结构(例如为分布式布拉格反射镜结构，通过相互堆叠的两种材料层来形成，例如氧化硅层和氧化钛层)。
依据一些实施例，电极结构20、电极结构50、导电连接部91以及导电连接部92的材料可以包含金属，例如：铝(Al)、银(Ag)、铬(Cr)、铂(Pt)、镍(Ni)、锗(Ge)、铍(Be)、金(Au)、钛(Ti)、钨(W)或锌(Zn)。电极结构20、电极结构50的材料可为金属材料，例如金(Au)、锡(Sn)、钛(Ti)或其合金。电极结构20、电极结构50可具有相同的材料及结构组成，又电极结构20、电极结构50可各形成为具有不同组成的多层结构。电极结构20、电极结构50可为多层结构。
依据一些实施例，电极结构20、电极结构50可为多层结构。举例来说，往远离基层40的方向，电极结构20、电极结构50例如包含钛(Ti)/金(Au)层、或钛(Ti)/铂(Pt)/金(Au)层、或钛钨(TiW)/金(Au)层。
依据一些实施例，电流限制层104、电流限制层105的材料可为三五族半导体材料，在本实施例中，电流限制层104、电流限制层105的材料为AlGaAs，且量子阱层1031、量子阱层1034、第一型半导体层101与第二型半导体层102的材料皆包含铝。电流限制层104、电流限制层105的铝含量大于量子阱层1031、量子阱层1034、第一型半导体层101与第二型半导体层102的铝含量，举例而言，电流限制层104、电流限制层105的铝含量大于97％。在本实施例中，电流限制区1041及电流限制区1051的氧含量分别大于电流导通区1042及电流导通区1052的氧含量，使电流限制区1041、电流限制层105的导电率分别低于电流导通区1042、电流导通区1052的导电率。
依据一些实施例，黏着层70为对量子阱层1031、量子阱层1034所发出的光具有高透光率的材料，如透光率大于80％，黏着层70的材料为绝缘材 料，例如：苯并环丁烯树脂、环氧树脂、聚酰亚胺(Polyimide)、旋涂玻璃(spin-on glass，SOG)、硅胶或全氟环丁烷。
依据一些实施例，视其材料不同，量子阱层1031、量子阱层1034可发出峰值波长(peak wavelength)介于700nm及1700nm的红外光、峰值波长介于610nm及700nm之间的红光、峰值波长介于530nm及570nm之间的黄光、峰值波长介于490nm及550nm之间的绿光、峰值波长介于400nm及490nm之间的蓝光或深蓝光、或是峰值波长介于250nm及400nm之间的紫外光。在本实施例中，量子阱层1031、量子阱层1034的峰值波长为介于750nm及1200nm之间的红外光。
在一些实施例中，第一型半导体层101与第二型半导体层102包含多个不同折射率的膜层交互周期性的堆叠(例如：高铝含量的AlGaAs层及低铝含量的AlGaAs层交互周期性堆叠)，以形成分布式布拉格反射镜的结构，使得由活性层103发射的光可以在两个反射镜中反射以形成相干光。第一型半导体层101与第二型半导体层102的材料包含三五族化合物半导体，例如可为AlGaInAs系列、AlGaInP系列、AlInGaN系列、AlAsSb系列、InGaAsP系列、InGaAsN系列、AlGaAsP系列等，例如AlGaInP、GaAs、InGaAs、AlGaAs、GaAsP、GaP、InGaP、AlInP、GaN、InGaN、AlGaN等化合物。
在本公开的实施例中，若无特别说明，上述化学表示式包含「符合化学计量的化合物」及「非符合化学计量的化合物」，其中，「符合化学计量的化合物」例如为三族元素的总元素计量与五族元素的总元素计量相同，反之，「非符合化学计量的化合物」例如为三族元素的总元素计量与五族元素的总元素计量不同。举例而言，化学表示式为AlGaInAs系列代表包含三族元素铝(Al)及/或镓(Ga)及/或铟(In)，以及包含五族元素砷(As)，其中三族元素(铝及/或镓及/或铟)的总元素计量可以与五族元素(砷)的总元素计量相同或相异。
另外，若上述由化学表示式表示的各化合物为符合化学计量的化合物时，AlGaInAs系列代表(Aly1Ga(1-y1))1-x1Inx1As，其中，0≦x1≦1，0≦y1≦1；AlGaInP系列代表(Aly2Ga(1-y2))1-x2Inx2P，其中，0≦x2≦1，0≦y2≦1；AlInGaN系列代表(Aly3Ga(1-y3))1-x3Inx3N，其中，0≦x3≦1，0≦y3≦1；AlAsSb系列代 表AlAsx4Sb(1-x4)，其中，0≦x4≦1；InGaAsP系列代表Inx5Ga1-x5As1-y4Py4，其中，0≦x5≦1，0≦y4≦1；InGaAsN系列代表Inx6Ga1-x6As1-y5Ny5，其中，0≦x6≦1，0≦y5≦1；AlGaAsP系列代表Alx7Ga1-x7As1-y6Py6，其中，0≦x7≦1，0≦y6≦1。
图7A为本公开至少一实施例的封装结构1a的剖面示意图；本实施例中，封装结构1a包括封装基板200、半导体激光器1000以及封装层300，其中，封装基板200包括导电接垫结构220及导电接垫结构250。
一并参见图7A及图4，在一些实施例中，封装结构1a中的半导体激光器1000可以是前述半导体激光器1003。具体来说，请对应参见图4，半导体激光器1003包括半导体叠层10、电极结构20、绝缘层30、基层40、以及电极结构50。
在本实施例中，半导体激光器1003具有出光面1100以及表面1200相对于出光面1100，半导体激光器1003位在封装基板200上且表面1200接触封装基板200，其中，位于半导体激光器1003的侧面13上的电极结构20及电极结构50分别透过连接结构700电性连接至封装基板200的导电接垫结构220及导电接垫结构250。故可无需加大半导体激光器1003的宽度、或无需缩短导电接垫结构220及导电接垫结构250之间的间距，通过半导体激光器1003的电极结构20及电极结构50延伸扩大分布至侧面13以加大与连接结构700的接触面积，以避免封装结构1a中半导体激光器1003与封装基板200电性接触不良(例如，电性短路、电性断路等)的问题。
参见图7A，封装层300为可透光。封装层300包括封装材料301，封装层300覆盖半导体激光器1003，更进一步，封装层300中具有多个填充粒子302，由此，可以利用变化封装层300中填充粒子302的分布密度或粒子尺寸大小等以变化封装结构1a的出光角度(例如，出光方向、出光范围等)或出光强度分布。
图7B为本公开至少一实施例的封装结构1b的另一剖面示意图；图7B的实施例与图7A的实施例相似，一并参见图7B及图4，主要差异如下所示：在本实施例中的封装结构1b，半导体激光器1003的一侧面上(邻近电极结构50的侧面13c上)更具有绝缘层90，其中绝缘层90延伸分布至出光面 1100上以覆盖部分电极结构20，如此，在将半导体激光器1003的电极结构50电性连接至封装基板200的导电接垫结构250时，可避免因连接结构700接触电极结构20而造成电性短路的问题发生。
更进一步，在本实施例中的封装结构1b，电极结构20与电极结构50不接触封装基板200，参见图7B，电极结构20与电极结构50的最低位置至封装基板200的上表面之间相隔有间距d，其中间距d为30至50微米，由此以避免在半导体激光器1003底部与封装基板200上的导电结构电性短路的问题发生。本实施例的封装结构1b的半导体激光器1003上亦可覆盖有封装层300(未示出)，但本公开的实施例不限于此。
图7C为本公开至少一实施例的封装结构1c的另一剖面示意图；图7C的实施例与图7A的实施例相似，主要差异如下所示：如图7C所示，在本实施例的封装结构1c中，封装基板200的基板主体210的表面201上更设有挡墙400，且半导体激光器1003设在表面201上并被挡墙400围绕，封装层300填充于挡墙400所围绕的区域中并覆盖半导体激光器1003，封装层300中具有多个填充粒子302，由此，可以利用变化封装层300中填充粒子302的分布密度或粒子尺寸大小等以变化封装结构1c的出光角度(例如，出光方向、出光范围等)或出光强度分布。
更进一步，封装基板200的导电接垫结构220包括导电接垫部220U、内连接部220I及导电接垫部220O，且，封装基板200的导电接垫结构250包括导电接垫部250U、内连接部250I及导电接垫部250O；其中，导电接垫部220U、250U位在表面201上并被挡墙400围绕，内连接部220I、250I穿设在基板主体210中且个别连接导电接垫部220U、250U，导电接垫部220O、250O位在基板主体210的表面203上且个别连接内连接部220I、250I。参见图7C，在本实施例中，由于导电接垫部220U、250U设在挡墙400所围绕的区域中且被封装层300覆盖，故可通过穿设在基板主体210中的内连接部220I、250I及设在基板主体210的表面203上的导电接垫部220O、250O，将封装结构1c中的半导体激光器1003透过导电接垫结构220、250以与外部驱动电源电性连接。
图7D为本公开至少一实施例的封装结构1d的另一剖面示意图；图7D 的实施例与图7A的实施例相似，主要差异如下所示：如图7D所示，本实施例的封装结构1d更包括调整层350凸设在封装层300上。由此，可以进一步利用变化调整层350的表面形状以变化封装结构1d的出光角度(例如，出光方向、出光范围等)或出光强度分布，在本实施例中，封装层300中可不含有填充粒子302，但本公开的实施例不限于此。
图7E为本公开至少一实施例的封装结构1e的剖面示意图；图7E的实施例与图7D的实施例相似，主要差异如下所示：如图7E所示，本实施例的封装结构1e的封装层300及调整层350中更填充有多个填充粒子302。由此，可以利用变化封装层300中填充粒子302的分布密度或粒子尺寸大小以及利用变化调整层350的表面形状等以变化封装结构1e的出光角度(例如，出光方向、出光范围等)或出光强度分布。
在一些实施例中，调整层350为透镜，且透镜的上表面可为曲面或齿状。在一些实施例中，透镜的上表面可为凹面或凸面。
在一些实施例中，调整层350与封装层300可由不同材料制成，但本公开的实施例不限于此；在一些实施例中，调整层350与封装层300也可由相同材料制成；在一些实施例中，调整层350中也可包括多个填充粒子302；在一些实施例中，调整层350与封装层300可为一体成型结构(one-piece structure)。
在一些实施例中，封装结构1a、1c、1d、1e中的半导体激光器1000可以替换为如图3所示的半导体激光器1002。具体来说，半导体激光器1002以倒装芯片的方式设置在封装基板200的基板主体210上，即半导体激光器1002的半导体叠层10的表面11朝向基板主体210且基层40远离基板主体210，位于半导体叠层10的侧面13上的电极结构20及50可分别透过连接结构700电性连接至封装基板200的导电接垫结构220及导电接垫结构250。故可无需加大半导体激光器1002的宽度、或无需缩短导电接垫结构220及导电接垫结构250之间的间距，通过半导体激光器1002的电极结构20及电极结构50延伸扩大分布至侧面13以加大与连接结构700的接触面积，以避免封装结构中半导体激光器1002与封装基板200电性接触不良的问题。
在一些实施例中，封装结构1a、1b、1c、1d、1e中的半导体激光器1000 可以替换为如图5所示的半导体激光器1004。具体来说，半导体激光器1004以倒装芯片的方式设置在封装基板200的基板主体210上，即半导体激光器1004的半导体叠层10的表面11朝向基板主体210且基层40远离基板主体210，位于半导体叠层10的侧面13上的电极结构20及50可分别透过连接结构700电性连接至封装基板200的导电接垫结构220及导电接垫结构250。故可无需加大半导体激光器1004的宽度、或无需缩短导电接垫结构220及导电接垫结构250之间的间距，通过半导体激光器1004的电极结构20及电极结构50延伸扩大分布至侧面13以加大与连接结构700的接触面积，以避免封装结构中半导体激光器1002与封装基板200电性接触不良的问题。
在一些实施例中，参见图7A至图7E所示的封装结构1a、1b、1c、1d、1e，其中，连接结构700的材料包括锡。
依据封装结构1a、1b、1c、1d、1e的一些实施例，可以通过使电极结构20、30延伸分布至半导体叠层10的侧面13上，增加电极结构20、30的分布面积，以容易透过连接结构700分别与封装基板上的导电接垫结构220、250电性连接，从而使得半导体激光器在进行封装时，可以在维持导电接垫结构220与导电接垫结构250的间距的前提下减省芯片尺寸且可避免电性接触不良的问题。
图8为本公开至少一实施例的半导体激光器1006的剖面示意图；本实施例的半导体激光器1006包括半导体叠层10、电极结构20、绝缘层30、基层40、电极结构50以及绝缘层60，其中，基层40为可导电层且可透光，电极结构50包含接触电极部50a及延伸电极部50b。
参见图8，半导体叠层10具有表面11、表面12以及侧面13，表面12相对于表面11，侧面13位于表面11及表面12之间，侧面13相对于表面11具有夹角θ，在本实施例中，夹角θ的角度实质上为90度。半导体叠层10包含第一型半导体层101、第二型半导体层102以及活性层103，其中，活性层103位于第一型半导体层101及第二型半导体层102之间。
参见图8，电极结构20位于表面11上。绝缘层30位于半导体叠层10与电极结构20之间，其中绝缘层30具有开口31，开口31位于表面11上，且电极结构20更位于开口31中并接触第一型半导体层101。基层40位于第 二型半导体层102相对于第一型半导体层101的一侧。绝缘层30更位于半导体叠层10与电极结构50之间以及电极结构20与电极结构50之间，其中绝缘层30具有通孔65，通孔65穿过半导体叠层10，电极结构50的接触电极部50a位于通孔65中并接触基层40，以使电极结构50透过基层40电性连接第二型半导体层102。绝缘层60位于通孔65中，且绝缘层60位于接触电极部50a与半导体叠层10之间，以隔绝接触电极部50a与第一型半导体层101，以及隔绝接触电极部50a与活性层103。电极结构50的延伸电极部50b连接接触电极部50a并自表面11上延伸分布至侧面13上。
需要说明的是，图8的实施例亦可具有电流限制层(如图2所示的电流限制层104)，其包括电流限制区1041以及电流导通区1042(图8未示出)。
图9为本公开至少一实施例的封装结构的剖面示意图；一并参见图9及图8，本实施例的封装结构1f包括封装基板200以及半导体激光器1006，其中封装基板200包括基板主体210、导电接垫结构220及导电接垫结构250。
再一并参见图8及图9，半导体激光器1006具有出光面1100及表面1200，半导体激光器1006以倒装芯片的方式设置在基板主体210上，即半导体激光器1006的表面1200朝向基板主体210且基层40远离基板主体210，位于半导体叠层10的侧面13上的电极结构20及50可分别透过连接结构700电性连接至封装基板200的导电接垫结构220及导电接垫结构250。
需要说明的是，图9的实施例亦可具有电流限制层(如图2所示的电流限制层104)，其包括电流限制区1041以及电流导通区1042(图9未示出)。
图10为本公开至少一实施例的半导体激光器1007的剖面示意图；本实施例的半导体激光器1007包括半导体叠层10、电极结构20、电极结构50、电极基板49、黏着层70以及绝缘层90。更进一步，半导体激光器1007更具有贯孔95，其中贯孔95穿过半导体叠层10及黏着层70。
参见图10，半导体叠层10具有表面11、表面12以及侧面13，表面12相对于表面11，侧面13位于表面11及表面12之间，侧面13相对于表面11具有夹角θ，在本实施例中，夹角θ的角度实质上为90度。半导体叠层10包含第一型半导体层101、第二型半导体层102以及活性层103。活性层103 位于第一型半导体层101及第二型半导体层102之间。
参见图10，电极结构20位于表面11上以与第一型半导体层101电性接触。电极结构50位于表面12上以与第二型半导体层102电性接触。电极基板49具有本体491、电极单元492以及电极单元493，其中本体491为不导电，且电极单元492与电极单元493分别位于本体491的二侧面并延伸分布至本体491的上下表面，且电极单元492与电极单元493彼此不接触。黏着层70位于第一型半导体层101与电极基板49之间，且黏着层70为不导电。绝缘层90位于贯孔95中，且绝缘层90位于半导体叠层10与电极结构50之间以使活性层103、第一型半导体层101与电极结构50电性绝缘，电极结构50自表面12上延伸分布于贯孔95中并接触电极基板40的电极单元493。其中，电极结构20更电性连接电极单元492。
图11为本公开至少一实施例的封装结构的剖面示意图；如图11所示，针对前述半导体激光器1007，本公开更提供对应的封装结构1g，包括：封装基板200、半导体激光器1007以及连接结构700，其中封装基板200包括基板主体210、导电接垫结构220及导电接垫结构250。
请再一并参见图11及图10，半导体激光器1007具有出光面1100以及表面1200，半导体激光器1007设置在封装基板200上，半导体激光器1007的表面1200朝向封装基板200，且出光面1100远离封装基板200，即半导体激光器1007的电极基板49位于接近基板主体210的一侧，且半导体激光器1007的半导体叠层10位于远离基板主体210的另一侧，电极结构20与电极单元492透过连接结构700电性连接至封装基板200的导电接垫结构220，电极结构50与电极单元493透过连接结构700电性连接导电接垫结构250。
需要说明的是，图10所示实施例的半导体激光器1007中亦可具有电流限制层(如图2所示的电流限制层104)，其包括电流限制区1041以及电流导通区1042(图10未示出)。
图12A为本公开至少一实施例的半导体激光器1000a的剖面示意图；如图12A所示，本实施例的半导体激光器1000a的结构与前述图5及图6所示的半导体激光器1004及1005相似，本实施例的半导体激光器1000a包括半 导体叠层10、电极结构20、绝缘层30、电极结构50、绝缘层60、黏着层70、基层40以及光学元件80。
在本实施例，光学元件80位于基层40上，其中，光学元件80具有图案化结构，从半导体叠层10的表面12的出光，进一步通过基层40上的光学元件80改变光行进的方向，由此变化半导体激光器1000a的出光角度(例如，出光方向、出光范围等)或出光强度分布。
图12B为本公开至少一实施例的半导体激光器1000a1的剖面示意图；如图12B所示，本实施例中，半导体激光器1000a1可具有多个光学元件80、85分别位于基层40的不同位置，例如，如图12B所示，光学元件80位于基层40上，光学元件85位于基层40下。
请再一并参见图23E至图23F的制作流程示意图以及图12A及图12B，在一些实施例中，通过黏着层70将形成有绝缘层60与电极结构50的激光器芯片4邦定至基层40，其中基层40具有光学元件80及\或光学元件85的结构。在激光器芯片4的制程过程中直接将具有光学元件的基层40结合封装至激光器芯片4，由此，可依据不同出光需求提供具对应光学元件结构的基层40，且产出具有晶圆级光学封装结构的半导体激光器，以满足微型化多种出光需求的应用。
图12C为本公开至少一实施例的半导体激光器1000a2，如图12C所示，在一些实施例中，基层40可为多层结构，例如，基层40包含第一基层40a、第二基层40b及附着层40c，第二基层40b通过附着层40c邦定至第一基层40a。在本实施例中，第二基层40b上具有如前所述的光学元件80，进一步通过第二基层40b的光学元件80改变光行进的方向，由此变化半导体激光器1000a2的出光角度(例如，出光方向、出光范围等)或出光强度分布。
请再一并参见图23F、图23K的制作流程示意图以及图12C，在本实施例中，可于进行至图23F的流程时，先将第一基层40a结合至激光器芯片4，之后，在完成图23K的流程后，再通过附着层40c将具有光学元件80的第二基层40b邦定封装至第一基层40a上，但本公开的实施例不限于此，即，在另一实施例中(未示出)，第二基层40b的光学元件80会面向第一基层40a并通过附着层40c结合至第一基层40a上。
在一些实施例中，光学元件80、85的结构可位于基层40的表面区域、或位于基层40的主体中。
图13为本公开至少一实施例的半导体激光器1000a3的剖面示意图；如图13所示，本实施例的半导体激光器1000a3与图4所示的半导体激光器1004的结构相似，半导体激光器1000a3更包括光学元件82的结构位于半导体叠层10的表面12上，光学元件82的结构位于出光口15中，且光学元件82的结构位于绝缘层60及黏着层70之间，其中出光口15为电极结构50的开口，出光口15的位置会对应于半导体叠层10中电流导通区1042的位置。
参见图13，在本实施例中，光学元件82具有超表面结构，其中，超表面结构为具有多个周期排列的奈米结构体，据此可将光学元件82直接形成于半导体叠层10的表面12上的出光口15中，以通过表面12上的光学元件82进一步变化半导体激光器1000a3的出光角度(出光方向、出光范围)或出光强度分布。
在本实施例中，如图13所示，半导体激光器1000a3的黏着层70与基层40之间更包括光学元件84，用以变化入射至基层40的光的行进方向。更进一步，在基层40的出光侧更具有光学元件86，再进一步变化从基层40射出的光的行进方向。
在本实施例中，如图13所示，光学元件84为介于绝缘层60及黏着层70之间的结构层，但本公开的实施例不限于此，即在一些实施例中，光学元件82可为绝缘层60与黏着层70之间的界面(interface)结构。
在一些实施例中，光学元件80、82、84、85、86可为衍射光学元件结构、微透镜阵列结构、超表面结构或超颖透镜、或前述各种光学元件结构的组合。
在一些实施例中，光学元件84、86的结构可位于基层40的表面区域或位于基层40的主体中。
在一些实施例中，光学元件84的结构亦可位于黏着层70的主体中。
图14A为本公开至少一实施例的半导体激光器1000b的剖面示意图；图14B为本公开至少一实施例的半导体激光器1000b的模态示意图；在一些实施例中，如图14A所示，半导体激光器1000b包括：半导体叠层10、电极结构20、绝缘层30、基层40以及电极结构50，其中，基层40为半导体叠层 10的成长基层，即基层40例如为半导体叠层10的成长基板，但本公开的实施例不限于此。
一并参见图14A及图1B，半导体激光器1000b的结构与图1B所示的垂直腔面发射激光元件1的结构相似，如图14A所示，半导体激光器1000b更包含透光导电层107、电流局限层106以及绝缘层108，其中，透光导电层107堆叠于半导体叠层10与电极结构20之间，电流局限层106堆叠于透光导电层107与半导体叠层10之间，且电流局限层106为可透光。
如图14A所示，本实施例中，半导体激光器1000b的半导体叠层10包括：第一型半导体层101、第二型半导体层102、活性层103以及电流限制层104。活性层103堆叠于第一型半导体层101及第二型半导体层102之间，电流限制层104堆叠于第一型半导体层101及活性层103之间。其中，电流限制层104包括电流导通区1042及电流限制区1041。
如图14A所示，本实施例中，位于第一型半导体层101上的电流局限层106具有开口1061，其中开口1061的位置对应于电流导通区1042。透光导电层107，位于电流局限层106上及开口1061中并接触第一型半导体层101。绝缘层108，位于透光导电层107上，并具有开口1081，其中开口1081与开口1061不重叠。第一电极层20位于绝缘层108上及开口1081中并接触透光导电层107以电性连接第一型半导体层101。第二电极层50位于第二型半导体层102下并且电性连接第二型半导体层102。
如图14B所示，对于对应电流局限层106的开口1061的光线LB1来说，其自活性层103发出后，依序经过第一型半导体层101、透光导电层107以及绝缘层108，从而具有第一种发光模态(主要发光模态)；另一方面，对于未对应电流局限层106的开口1061的光线LB2来说，其自活性层103发出后，依据经过第一型半导体层101、电流局限层106、导电透光层107以及绝缘层108，从而具有第二种发光模态(非主要发光模态)。在本实施例中，为抑制非主要发光模态的光线LB2，透过电流局限层106、透光导电层107以及绝缘层108的厚度配置降低光线LB2在半导体激光器1000b中的反射率，从而导致具有非主要发光模态的光线LB2因为反射率不足而较为无法被半导体激光器1000d射出。换句话说，透过此方式，本实施例的半导体激光器 1000b可仅射出具有主要发光模态的光线LB1，从而缩小的半导体激光器1000b的发光角度。
在一些实施例中，如图14A所示，透光导电层107形成于电流局限层106上及开口1061中，位于开口1061的透光导电层107具有第一厚度D1，不位于开口1061的透光导电层107具有第二厚度D2，且第一厚度D1大于第二厚度D2。
在一些实施例中，半导体激光器1000b的透光导电层107具有上表面1071及下表面1072，下表面1072相对于上表面1071，且，如图14A所示，上表面1071为平面，下表面1072具有向下凸出面位于开口1061中。
在一些实施例中，如图14A所示，电流导通区1042的位置对应开口1061的位置，电流导通区1042具有导通宽度W4，开口1061具有开口宽度W5，导通宽度W4大于开口宽度W5。
在一些实施例中，绝缘层108为可透光的单层或多层结构。
在一些实施例中，透光导电层107为单层或多层结构。
在一些实施例中，电流局限层106的材料可以是但不限于氮化硅或二氧化硅。
在一些实施例中，透光导电层107的材料可以是但不限于氧化铟锡(ITO)或者氧化铟锌(IZO)。
在一些实施例中，绝缘层108的材料可以是但不限于氮化硅或二氧化硅。
需要说明的是，电流局限层106与绝缘层108可以是相同材料，因其对于半导体激光器而言所赋予的作用不同，因而使用不同元件名称。具体来说，在本实施例中，注入半导体激光器1000b的电流路径并不会经过电流局限层106。
另外，本实施例中，对应到主要发光模态的区域的电流局限层106、透光导电层107与绝缘层108的总厚度与对应到非主要发光模态的区域的电流局限层106、透光导电层107与绝缘层108的总厚度的差值为λ/4n，其中λ为半导体激光器1000b所发出的波长，n为折射率。
图15A为本公开至少一实施例的半导体激光器1000b1的剖面示意图；图15B为本公开至少一实施例的半导体激光器1000b1的模态示意图。
如图15A所示，半导体激光器1000b1的透光导电层107形成于电流局限层106上并具有第一凹陷区1073，第一凹陷区1073位于开口1061上，位于该第一凹陷区1073的透光导电层107具有第一厚度D1，不位于第一凹陷区1073的透光导电层107具有第二厚度D2，第一厚度D1等于或接近第二厚度D2。在一些实施例中，透光导电层107是共形(Conformal)形成于电流局限层106上。
参见图15A，在一些实施例中，半导体激光器1000b1的绝缘层108形成于透光导电层107上并具有第二凹陷区1082，第二凹陷区1082位于第一凹陷区1073上，位于第二凹陷区1082的绝缘层108具有第三厚度D3，不位于第二凹陷区1082的绝缘层108具有第四厚度D4，第三厚度D3等于或接近第四厚度D4。在一些实施例中，绝缘层108是共形(Conformal)形成于透光导电层107上。
如图15A及图15B所示，对于对应电流局限层106的开口1061的光线LB1’来说，其自活性层103发出后，依序经过第一型半导体层101、透光导电层107以及绝缘层108，从而具有第一种发光模态(主要发光模态)；另一方面，对于未对应电流局限层106的开口1061的光线LB2’来说，其自活性层103发出后，依据经过第一型半导体层101、电流局限层106、导电透光层107以及绝缘层108，从而具有第二种发光模态(非主要发光模态)。在本实施例中，为抑制非主要发光模态的光线LB2’，透过电流局限层106、透光导电层107以及绝缘层108的厚度配置降低光线LB2’在半导体激光器1000b1中的反射率，从而导致具有非主要发光模态的光线LB2’因为反射率不足而较为无法被半导体激光器1000b1射出。换句话说，透过此方式，本实施例的半导体激光器1000b1可仅射出具有主要发光模态的光线LB1’，从而缩小半导体激光器1000b1的发光角度。
图16A与图16B为本公开至少一实施例的半导体激光器(例如，图14A的半导体激光器1000b或图15A的半导体激光器1000b1)的发光孔O上视示意图，用以说明发光孔O的开口1061的配置。参见图16A，本实施例中，开口1061与发光孔O可为圆形，更进一步开口1061与发光孔O可为同心圆配置，但并不以此为限；参见图16B，本实施例中，开口1061亦可为多边 形配置，例如三角形配置。是以，如同前述，对于具有主要发光模态的光线来说，会从开口1061所对应的区域A的位置射出，而对于具有非主要发光模态的光线来说，则会从开口1061外且介于发光孔O内所对应的区域B射出。并且，参见图14A及14B或图15A及15B，自活性层103发出并由光区域A出射的光(例如，光线LB1或光线LB1’)与自活性层103发出并由区域B出射的光(例如，光线LB2或光线LB2’)，由于其个别行经的结构层有所差异(例如，光线LB1与光线LB2、或者光线LB1’与光线LB2’)，因而形成于区域B的出光被抑制或被衰减而主要由区域A出光的具较小出光角度范围的半导体激光器，但本公开的实施例不限于此。
图17为本公开至少一实施例的半导体激光器1000b2的剖面示意图；如图17所示，半导体激光器1000b2的第一型半导体层101中更具有掺杂区101DP，在本实施例中，掺杂区101DP的位置对应于电流导通区1042上方且不重叠于电流导通区1042的中心位置，但本公开的实施例不限于此。
在一些实施例中，掺杂区101DP是以高温制程产生，使扩散材料(例如锌)扩散至电流导通区1042未对应开口1061的区域。
对于对应电流局限层106的开口1061的光线来说，其自活性层103发出后，依序经过第一型半导体层101、透光导电层107以及绝缘层108，从而具有第一种发光模态(主要发光模态)；另一方面，对于未对应电流局限层106的开口1061的光线来说，其自活性层103发出后，依据经过第一型半导体层101、掺杂区101DP、电流局限层106、导电透光层107以及绝缘层108，从而具有第二种发光模态(非主要发光模态)。在本实施例中，为抑制非主要发光模态的光线，透过掺杂区101DP的配置搭配电流局限层106、透光导电层107以及绝缘层108的厚度配置降低具有非主要发光模态的光线在半导体激光器1000b2中的反射率，从而导致具有非主要发光模态的光线因为反射率不足而较为无法被半导体激光器1000b2射出。换句话说，透过此方式，本实施例的半导体激光器1000b2可仅射出具有主要发光模态的光线，从而缩小半导体激光器1000b2的发光角度。
图18A为本公开至少一实施例的半导体激光器1000b3的剖面示意图；图18B为本公开至少一实施例的半导体激光器1000b3的模态示意图；如图 18A所示，半导体激光器1000b3的透光导电层107包含第一透光导电区1074及第二透光导电区1075，第二透光导电区1075围绕第一透光导电区1074，且开口1061位于第一透光导电区1074与第二透光导电区1075之间。
如图18B所示，对于对应电流局限层106的开口1061的光线LB2”来说，其自活性层103发出后，依序经过第一型半导体层101、透光导电层107以及绝缘层108，从而具有第一种发光模态(主要发光模态)；另一方面，对于未对应电流局限层106的开口1061的光线LB1”来说，其自活性层103发出后，依据经过第一型半导体层101、电流局限层106、导电透光层107以及绝缘层108，从而具有第二种发光模态(非主要发光模态)。在本实施例中，为抑制非主要发光模态的光线LB1”，透过电流局限层106、透光导电层107以及绝缘层108的厚度配置降低光线LB1”在半导体激光器1000b3中的反射率，从而导致具有非主要发光模态的光线LB1”因为反射率不足而较为无法被半导体激光器1000b3射出。换句话说，透过此方式，本实施例的半导体激光器1000b3可仅射出具有主要发光模态的光线LB2”，从而缩小半导体激光器1000b3的发光角度。
图18C至图18E为本公开至少一实施例的半导体激光器1000b3的发光孔O上视平面示意图，用以说明发光孔O范围内电流局限层106的开口1061的配置，其中。参见图18C，本实施例中，开口1061呈环状配置，但并不以此为限；参见图18D，本实施例中，可具有多个呈圆形配置的开口1061，且各开口1061位于发光孔的外围区域；再参见图18E，本实施例中，可具有多个呈三角形配置的开口1061，且各开口1061位于发光孔的外围区域。是以，如同前述，对于具有主要发光模态的光线来说，会从开口1061所对应的区域A的位置射出，而对于具有非主要发光模态的光线来说，则会从发光孔O范围内对应第一透光导电区1074所分布的区域B射出。并且，参见图18A及18B，自活性层103发出并由区域A出射的光(例如光线LB2”)与自活性层103发出并由区域B出射的光(例如，光线LB1”)，由于其个别行经的结构层有所差异(例如，光线LB1”与光线LB2”)，因而形成于区域B的出光被抑制或被衰减而主要由区域A出光的具较大出光角度范围的半导体激光器，但本公开的实施例不限于此。
图19为本公开至少一实施例的半导体激光器1000b4的剖面示意图；如图19所示，半导体激光器1000b4更包括反射层112位于透光导电层107的上表面1071，且反射层112位于电极结构20所界定的开口中，且绝缘层108分布于反射层112与电极结构20之间以使反射层112与电极结构20电性绝缘。
在一些实施例中，如图19所示，反射层112可为分布式布拉格反射镜结构，更进一步反射层112可由不同折射率的两种以上的介电膜层相互堆叠而形成，例如：氧化硅层和氧化钛层的相互堆叠层。
在一些实施例中，如图19所示，由电极结构20注入至第一型半导体层101的电流(载流子流)主要会沿着阻抗最短路径PT注入活性层103中，因此可减少第一型半导体层101中由半导体膜副层交替堆叠而成的布拉格反射镜层的层数，由介电布拉格反射镜层112取代该些减少的半导体布拉格反射镜层，如此可减少第一型半导体层101对活性层103的出光的吸光影响。
在一些实施例中，反射层112的宽度会小于等于开口1061的宽度。
对于对应电流局限层106的开口1061的光线来说，其自活性层103发出后，依序经过第一型半导体层101、透光导电层107、反射层112以及绝缘层108，从而具有第一种发光模态(主要发光模态)；另一方面，对于未对应电流局限层106的开口1061的光线来说，其自活性层103发出后，依据经过第一型半导体层101、电流局限层106、导电透光层107以及绝缘层108，从而具有第二种发光模态(非主要发光模态)。在本实施例中，可透过反射层112的配置提升主要发光模态的光线在半导体激光器1000b4中的反射率，并进一步透过电流局限层106、透光导电层107以及绝缘层108的厚度配置降低具有非主要发光模态的光线在半导体激光器1000b4中的反射率。换句话说，透过此方式，本实施例的半导体激光器1000b4可仅射出具有主要发光模态的光线，从而缩小半导体激光器1000b4的发光角度。
图20为本公开至少一实施例的半导体激光器1000b5的剖面示意图；如图20所示，半导体激光器1000b5包括：半导体叠层10、基层40、电极结构20、电极结构50以及绝缘层30。
如图20所示，本实施例中，半导体叠层10位于基层40上，绝缘层30 位于半导体叠层10与电极结构20之间，且绝缘层30具有开口31，电极结构20分布于绝缘层30上并延伸至开口31中以与半导体叠层10电性连接。基层40位于半导体叠层10与电极结构50之间，本实施例中，基层40为可导电，以使电极结构50电性连接半导体叠层10。
如图20所示，本实施例中，半导体叠层10包含上反射镜层101A、下反射镜层102A以及活性层103，活性层103位于上反射镜层101A及下反射镜层102A之间。本实施例中，下反射镜层102A为第二型半导体层且具有分布式布拉格反射镜结构。
如图20所示，本实施例中，上反射镜层101A包含反射镜层101E及反射镜层101I，反射镜层101E位于活性层103与反射镜层101I之间，反射镜层101I位于反射镜层101E与电极结构20之间，其中反射镜层101E为第一型半导体层且具有分布式布拉格反射镜结构。本实施例中，第二型半导体层为N型半导体层，第一型半导体层为P型半导体层，但本公开的实施例不限于此，即，在另一实施例中，第一型半导体层为N型半导体层，第二型半导体层为P型半导体层。
如图20所示，反射镜层101I包含中间反射区101I1及电流路径区101I2，电流路径区101I2位于中间反射区101I1的两侧，且电极结构20透过绝缘层30的开口31与反射镜层101I中的电流路径区101I2电性连接。
如图20所示，本实施例中，上反射镜层101A具有分布式布拉格反射镜结构，其中位于电流路径区101I2中的布拉格反射结构具有掺杂或较高浓度的掺杂(相较于中间反射区101I1)，电流路径区101I2中的掺杂可透过离子布植(ion implantation)或离子扩散(ion diffusion)的制程形成。
如图20所示，本实施例中，半导体叠层10更包括电流限制层104，位于活性层103与上反射镜层101A之间。电流限制层104包括电流限制区1041以及电流导通区1042，且电流导通区1042被电流限制区1041环绕，被电流限制区1041环绕的电流导通区1042具有分布宽度W42。
如图20所示，电极结构20具有开口21位于绝缘层30上且开口21的位置对应电流导通区1042的位置，开口21具有开口宽度W21。
如图20所示，位于两侧电流路径区101I2之间的中间反射区101I1具有 分布宽度W11，中间反射区101I1的位置对应电流导通区1042的位置。
在一些实施例中，如图20所示，电极结构20的开口宽度W21小于或等于中间反射区101I1的分布宽度W11。
在一些实施例中，如图20所示，电极结构20的开口宽度W21大于或等于电流导通区1042的分布宽度W42。
在一些实施例中，如图20所示，电极结构20的开口宽度W21大于或等于中间反射区101I1的分布宽度W11，且分布宽度W11大于等于电流导通区1042的分布宽度W42。
在一些实施例中，如图20所示，由电极结构20注入至上反射镜层101A的电流(载流子流)主要会沿着阻抗最短路径PT注入活性层103中，由于中间反射区101I1中的布拉格反射镜层不具有掺杂(或相较于反射镜层101E，中间反射区101I1的掺杂浓度较低)，因此电流(载流子流)会沿着上反射镜层101A中的电流路径区101I2，经过具有第二型半导体层的反射镜层101E及电流导通区1042后注入活性层103中，邻近电流导通区1042的活性层103的向上出光会经过上反射镜层101A的中间反射区101I1后再射出于表面11A，由于半导体激光器1000b5中主要出光的行经路径与电流(载流子流)的行经路径分开，如此可降低上反射镜层101A中的载流子对活性层103的出光的吸光影响。
在一些实施例中，参见图20，上反射镜层101A中的电流路径区101I2可分布接近至活性层103，以减少具有反射镜层101E的第二型半导体层的层数，据此可进一步降低反射镜层101E的第二型半导体层对活性层103的出光的吸光影响。
图24A至图24C分别为本公开至少一实施例的半导体激光器2400的剖面示意图、下视透视示意图和上视透视示意图；其中，图24A为沿着图24C中的线A-A’剖面所显示的剖面示意图；如图24A所示，半导体激光器2400包含多个半导体激光器单元(例如，半导体激光器单元2400U1及半导体激光器单元2400U2)，其中，半导体激光器单元2400U1包括多个高台结构(例如，高台结构P1A及P2A)位于第一型半导体层101U1上，半导体激光器单元2400U2包括多个高台结构(例如，高台结构P3A及P4A)位于第一型 半导体层101U2上。
如图24A所示，高台结构P1A、P2A为凸设于第一型半导体层101U1表面上的柱状结构、高台结构P3A、P4A为凸设于第一型半导体层101U2表面上的柱状结构。
如图24A所示，半导体激光器2400还包含透光的基层40及黏着层70，黏着层70位于基层40与多个高台结构P1A～P4之间A，即基层40通过黏着层70黏合至多个高台结构P1A～P4A。如图24A所示，多个高台结构P1A、P2A自第一型半导体层101U1表面向上凸设于黏着层70中且多个高台结构P3A、P4A自第一型半导体层101U2表面向上凸设于黏着层70中，即黏着层70包覆该些高台结构P1A～P4A于其间。
如图24A所示，高台结构P1A、P2A、P3A、P4A分别包括第二型半导体层102U1、102U2、102U3、102U4以及活性层103U1、103U2、103U3、103U4，其中，活性层103U1于第一型半导体层101U1与第二型半导体层102U1之间，活性层103U2于第一型半导体层101U1与第二型半导体层102U2之间，活性层103U3于第一型半导体层101U2与第二型半导体层102U3之间，以及活性层103U4于第一型半导体层101U2与第二型半导体层102U4之间。
如图24A所示，半导体激光器单元2400U1具有电极结构20U1分布于第一型半导体层101U1的下表面并与第一型半导体层101U1电性接触。如图24A所示，半导体激光器单元2400U2具有电极结构20U2分布于第一型半导体层101U2的下表面并与第一型半导体层101U2电性接触。
如图24A所示，半导体激光器单元2400U1具有绝缘层60U1位于第二型半导体层102U1、102U2的上表面并延伸分布至高台结构P1A、P2A的侧表面，绝缘层60U1位于电极结构50U1及高台结构P1A、P2之间A，且绝缘层60U1具有多个开口61U1～61U4分别位于第二型半导体层102U1、102U2的上表面，半导体激光器单元2400U1的电极结构50U1位于开口61U1～61U4中以与第二型半导体层102U1、102U2电性接触，且电极结构50U1自开口61U1～61U4延伸分布至高台结构P1A、P2A的侧面的绝缘层60U1上。如图24A所示，绝缘层60U1更进一步自高台结构P2A的侧表面延伸分布至第一 型半导体层101U1的上表面且具有开口33U1。
如图24A所示，半导体激光器单元2400U1的第一型半导体层101U1具有贯孔101V1对应开口33U1的位置，电极结构50U1再沿着高台结构P2A侧面的绝缘层60U1的表面延伸分布至第一型半导体层101U1的上表面上并至贯孔101V1中，且电极结构50U1进一步从贯孔101V1中延伸分布至第一型半导体层101U1的下方，即部分的电极结构50U1与电极结构20U1皆位于第一型半导体层101U1的下方。如图24A所示，半导体激光器单元2400U1包含绝缘层30U1位于电极结构50U1与第一型半导体层101U1之间，以电性隔绝电极结构50U1与第一型半导体层101U1。
如图24A所示，半导体激光器单元2400U2具有绝缘层60U2位于第二型半导体层102U3、102U4的上表面并延伸分布至高台结构P3A、P4A的侧表面，绝缘层60U2位于电极结构50U2及高台结构P3A、P4之间A，且绝缘层60U2具有多个开口61U5～61U8分别位于第二型半导体层102U3、102U4的上表面，半导体激光器单元2400U2的电极结构50U2位于开口61U5～61U8中以与第二型半导体层102U3、102U4电性接触，且电极结构50U2自开口61U5～61U8延伸分布至高台结构P3A、P4A的侧表面的绝缘层60U2上。如图24A所示，绝缘层60U2更进一步自高台结构P4A的侧表面延伸分布至第一型半导体层101U2的上表面且具有开口33U2。
如图24A所示，半导体激光器单元2400U2的第一型半导体层101U2具有贯孔101V2对应开口33U2的位置，电极结构50U2再沿着高台结构P4A侧面的绝缘层60U2的表面延伸分布至第一型半导体层101U2的上表面并延伸分布至贯孔101V2中，且电极结构50U2进一步从贯孔101V2中延伸分布至第一型半导体层101U2的下方，即部分的电极结构50U2与部分的电极结构20U2皆位于第一型半导体层101U2的下方。如图24A所示，半导体激光器单元2400U2包含绝缘层30U2位于电极结构50U2与第一型半导体层101U2之间，以电性隔绝电极结构50U2与第一型半导体层101U2。
如图24A与图24B所示，半导体激光器单元2400U1的第一型半导体层101U1与半导体激光器单元2400U2的第一型半导体层101U2之间填充有绝缘层30B。如图24B所示，绝缘层30U1、30B及30U2的绝缘层结构连通为 绝缘层30，且绝缘层30填充于电极结构20U1、电极结构50U1、电极结构20U2及电极结构50U2之间以隔绝电极结构20U1、电极结构50U1、电极结构20U2及电极结构50U2。
如图24A与图24B所示，绝缘层30更具多个开口位于第一型半导体层101U1及第一型半导体层101U2的下表面上以个别暴露出半导体激光器单元2400U1底部的电极结构20U1及电极结构50U1，以及个别暴露出半导体激光器单元2400U2底部的电极结构20U2及电极结构50U2。
如图24A至图24C所示，半导体激光器2400分为多个发光区2400A、2400B、2400C和2400D，各发光区具有独立的一对电极以进行各发光区的寻址控制，但本公开的实施例中的发光区数量及电极结构的数量并不限于此，即可依实际应用所需(例如，感测应用、或照明应用等)来控制半导体激光器2400的发光位置(哪一发光区发光)和亮度(发光的发光区数量)。以发光区2400A及2400B作为例示说明，例如位于发光区2400A中的半导体激光器单元2400U1具有一对电极结构20U1、50U1，位于发光区2400B中的半导体激光器单元2400U2具有另一对电极结构20U2、50U2，且电极结构对20U1、50U1、电极结构对20U2、50U2电性连接于电流控制装置(图未示)，电流控制装置可依据外界光的强度判断是否施加电流予特定的电极结构对(电极结构对20U1、50U1及/或电极结构对20U2、50U2)，由此点亮半导体激光器2400的不同发光区，以达到寻址控制发光的效果。
如图24A所示，在本实施例中，高台结构P1A～P4A中分别具有电流限制层104，分别位于活性层103U1与第二型半导体层102U1之间、活性层103U2与第二型半导体层102U2之间、活性层103U3与第二型半导体层102U3之间以及活性层103U4与第二型半导体层102U4之间，但本公开的实施例不限于此。如图24A，电流限制层104包括电流限制区1041和电流导通区1042，电流限制区1041围绕电流导通区1042，电流导通区1042的导电率高于电流限制区1041，以使电流集中导通于电流导通区1042中。
参见图24A，半导体激光器2400为倒装芯片式垂直腔面发射激光器的封装结构，后续可使用焊料将半导体激光器2400邦定至外部电路基板(例如：印刷电路板)或封装基板。
参见图24A，在本实施例中，第二型半导体层102U1～102U4及第一型半导体层101U1、101U2包含多个不同折射率的膜层交互堆叠(例如：高铝含量的AlGaAs层及低铝含量的AlGaAs层交互周期性堆叠)，以形成分布式布拉格反射镜的结构，使得由活性层103U1～103U4发射的光可以在两个反射镜中反射以形成同调光。在本实施例中，第二型半导体层102U1、102U2的反射率低于第一型半导体层101U1的反射率，且第二型半导体层102U3、102U4的反射率低于第一型半导体层101U2的反射率，由此使同调光朝向基层40的方向射出。
在一些实施例中，第一型半导体层101U1、101U2及第二型半导体层102U1、102U2、102U3、102U4的材料包含三五族化合物半导体，例如：AlGaInAs系列、AlGaInP系列、AlInGaN系列、AlAsSb系列、InGaAsP系列、InGaAsN系列、AlGaAsP系列等，例如AlGaInP、GaAs、InGaAs、AlGaAs、GaAsP、GaP、InGaP、AlInP、GaN、InGaN、AlGaN等化合物。
视其材料不同，活性层103U1、103U2、103U3、103U4可发出峰值波长(Peak Wavelength)介于700nm及1700nm的红外光、峰值波长介于610nm及700nm之间的红光、峰值波长介于530nm及570nm之间的黄光、峰值波长介于490nm及550nm之间的绿光、峰值波长介于400nm及490nm之间的蓝光或深蓝光或是峰值波长介于250nm及400nm之间的紫外光。在本实施例中，活性层103U1、103U2、103U3、103U4的峰值波长为介于750nm及1200nm之间的红外光。
在一些实施例中，电流限制层104的材料可为上述的三五族半导体材料，如图1A所示，电流限制层104的材料为AlGaAs，且活性层103U1、103U2、103U3、103U4的材料皆包含铝。电流限制层104的铝含量大于活性层103U1、103U2、103U3、103U4的铝含量，举例而言，电流限制层104的铝含量大于97％。在本实施例中，电流限制区1041的氧含量大于电流导通区1042A的氧含量，使电流限制区1041的导电率远低于电流导通区1042的导电率。
黏着层70为对活性层103U1、103U2、103U3、103U4所发出的光具有高透光性，例如透光率大于80％的材料。
黏着层70包含绝缘材料(非导电材料)，例如：苯并环丁烯树脂、环氧树 脂、聚酰亚胺、旋涂玻璃、硅胶或全氟环丁烷。
绝缘层30U1、30U2、30B材料包含非导电材料。非导电材料可以是有机材料或无机材料。有机材料包含环氧树脂光刻胶、苯并环丁烯树脂、全氟环丁烷、环氧树脂、丙烯酸树脂、环烯烃聚合物、聚甲基丙烯酸甲酯、聚对苯二甲酸乙二酯、聚碳酸酯、聚醚酰亚胺或氟碳聚合物。无机材料包含硅胶或玻璃、氧化铝、氮化硅、氧化硅、氧化钛、或氟化镁。在一些实施例中，绝缘层30U1、30U2、30B为一层或多层(例如，分布式布拉格反射镜结构，通过相互堆叠的两种材料层来形成，例如氧化硅层和氧化钛层)。
电极结构20U1、20U2的材料可以包含金属，例如：铝、银、铬、铂、镍、锗、铍、金、钛、钨或锌。电极结构50U1、50U2的材料可为金属材料，例如金、锡、钛或其合金。电极结构20U1、20U2和电极结构50U1、50U2可为一层或多层结构。电极结构20U1、20U2和电极结构50U1、50U2可各形成为具有不同组成的多层结构。
图25为本公开至少一实施例发光装置100的封装结构的剖面示意图；本实施例中，发光装置100的封装结构包括：封装基板200、半导体激光器1000以及调整层300’。
一并参见图25及图1B，半导体激光器1000可以是如图1B所示的垂直共振腔面射激光元件，用以提供激光光源。
如图25所示，半导体激光器1000具有出光面1001以及表面1002，表面1002相对于出光面1001，且半导体激光器1000电性连接该封装基板200。调整层300’位于半导体激光器1000的出光面1001上，其中调整层300’包括封装材料301以及多个粒子302，其中粒子302填充于封装材料301中，该些粒子302呈透光或半透光并散布于封装材料301中。
如图25所示，半导体激光器1000的底部电极(例如，图1B所示的垂直共振腔面射激光元件的电极结构50)连接至封装基板200上的导电接垫2002，且半导体激光器1000的顶部电极(例如，图1B所示的垂直共振腔面射激光元件的电极结构20)经走线邦定(wire bonding)至封装基板200上的另一导电接垫2004，从而与封装基板200电性连接，其中，半导体激光器1000的底部电极与顶部电极具有不同电性。
再参见图25，本实施例中，调整层300’覆盖半导体激光器1000，从而接触半导体激光器1000的出光面1001以及封装基板200。由此，可以变化填充粒子302于封装材料301中的掺杂(填充)浓度或变化粒子尺寸，以变化发光装置1的发光角度范围或出光方向。
在一些实施例中，封装基板200可为陶瓷基板、经射出成型或铸模成形(Molding)的塑料基板、环氧玻璃多层基板(FR4)、双马来酰亚胺-三氮杂环树脂(Bismaleimide Triazine，BT)基板、铝基板、或其他具有导电线路的基板。基板中具有相应的设计导电结构(未示)以供电性连接用。
在一些实施例中，调整层300’的封装材料301可以是硅胶、环氧树脂、混合形式的封装材料或可以是作为封装的胶材。
在一些实施例中，调整层300’的填充粒子302可以是硅胶、玻璃粉末、填料或填充后可以改变光源角度的材料。
在一些实施例中，填充粒子302的尺寸范围可能因为材料成分或形式不同而有不同的尺寸。
在一些实施例中，填充粒子302的掺杂(填充)浓度会因材料成分或形式不同及最终需求的发光角度而有不同的掺杂(填充)浓度。
图26为本公开至少一实施例发光装置100a的封装结构的剖面示意图；本实施例中，发光装置100a的封装结构更包括透光封装层500，位于激光元件1000的出光面1001上，其中透光封装层500接触半导体激光器1000的出光面1001以及封装基板200，且调整层300’位于透光封装层500上。
在一些实施例中，透光封装层500的材料可以与调整层300’的封装材料301相同或不同。
图27为本公开至少一实施例的发光装置100b的封装结构的剖面示意图；本实施例中，发光装置100b的封装结构更包括支撑件400’，其中支撑件400与封装基板200共同界定容置空间401，半导体激光器1000位于容置空间401内，且调整层300’位于支撑件400’上而覆盖容置空间401及半导体激光器1000。在一些实施例，支撑件400可为前述挡墙400的结构，但本公开的实施例不限于此。
在一些实施例中，容置空间401中可以充填空气，也可以充填惰性气体、 氮气或者维持真空。
图28为本公开至少一实施例的发光装置100c的封装结构的剖面示意图；本实施例中，发光装置100c的封装结构同样包括挡墙400，其中挡墙400与封装基板200共同界定容置空间401。本实施例中，半导体激光100与调整层300'是位于容置空间401内，且调整层300’接触半导体激光器1000的出光面1001。换句话说，本实施例中，调整层300’是填入挡墙400与封装基板200所共同界定的容置空间401中，并且覆盖半导体激光器1000，从而接触半导体激光器1000的出光面1001以及封装基板200。
在一些实施例中，挡墙400的材料可以是硅胶、环氧树脂、混合形式的材料、陶瓷材料(例如但不限于氧化铝或氮化铝)、金属材料，或是任何可以作为支撑件的材料。
图29为本公开至少一实施例的发光装置100d的封装结构的剖面示意图；本实施例中，发光装置100d的封装结构包括：半导体激光器1000以及调整层300’。半导体激光器1000具有出光面1001以及表面1002，表面1002相对于出光面1001。半导体激光器1000的电极1020及电极1050皆位于表面1002上，以后续与封装基板或电路基板电性连接。调整层300’位于半导体激光器1000的出光面1001上，其中调整层300’包括封装材料301以及多个粒子302，其中粒子302掺杂(填充)于封装材料301中，该些粒子302呈透光或半透光并散布于封装材料301中。换句话说，本实施例中，半导体激光器1000为水平式电极架构，即半导体激光器1000的正电极垫及负电极垫分布于同一侧(例如，图8所示半导体激光器1006的电极结构20及电极结构50分布于半导体叠层10的同一侧)，并透过倒装芯片制程设置于封装基板上，从而达成芯片尺寸封装(Chip Scale Package，CSP)。
图30A为未具有调整层300’的发光装置的发光角度示意图。图30B是根据图30A实施例更包含调整层300’的发光装置的发光角度示意图。
如图30A及图30B所示，相较于未具有调整层300’的封装结构，根据本申請一些实施例的封装结构可使半导体激光器1000的发光角度由30度(-15度至+15度)增加至约60度(-30度至+30度)，以满足大出光角度范围的发光装置需求。
图31A为本公开至少一实施例的光发收装置200a的封装结构的侧视透视示意图，图31B是根据图31A实施例的光发收装置200a的封装结构的上视图；本实施例的光发收装置200a的封装结构包括：封装基板200’、至少一个发光元件1000、至少一个收光元件R以及封装层320。本实施例中，发光元件1000与收光元件R的数量为1，但仅为例示，并不以此为限制。
如图31A所示，封装基板200’具有第一部分221、第二部分222以及绝缘部分223，绝缘部分223位于第一部分221与第二部分222之间，且第一部分221具有弯折角度α。换句话说，本实施例中，封装基板200’的第一部分221可再分为弯折部2211与延伸部2212，且封装基板的弯折部2211与延伸部2212之间具有弯折角度α。
发光元件1000具有出光面1201以及表面1202，表面1202相对出光面1201并位于封装基板200’的第一部分221的弯折部2211上，且收光元件R位于封装基板200’的第二部分222上。
封装层320位于发光元件1200的出光面1201以及收光元件R的收光面R1上。封装层320具有一出光表面320a以及一收光表面320b，分别对应发光元件1200以及收光元件R。由于封装基板的弯折部2211与延伸部2212之间具有弯折角度α，故使对应发光元件1200的出光表面320a的法线Na与对应收光元件R的收光表面320b的法线Nb不平行，即出光表面320a的法线Na与收光表面320b的法线Nb之间具有夹角，其中β不为0度。在本实施例中，夹角β实质上等于弯折角度α，但本公开的实施例不以此为限。
如图31B所示，本实施例中，由上视图观之，封装基板200’的第一部分221可分为相连接的区域A、区域B(合称区域AB)以及相连接的区域C、区域D(合称区域CD)，区域A与区域C之间具有绝缘部分223，且区域B与区域D之间亦具有绝缘部分223。封装基板200’的第二部分222可分为区域E与区域F，且区域E与区域F之间亦具有绝缘部分223。本实施例中，由上视图观之，绝缘部分223呈现十字型，而将第一部份的区域AB与区域CD相互分隔、将第二部分的区域E与区域F相互分隔、将第一部份的区域AB与第二部分的区域E相互分隔以及将第一部份的区域CD与第二部分的区域F相互分隔。本实施例中，发光元件1000位于第一部分221的区域A， 发光元件1000的底部电极电性连接至区域A的电极垫上，且发光元件1000的顶部电极通过接线W电性连接至区域C的电极垫上；对应地，收光元件R位于第二部分222的区域E，收光元件R的底部电极电性连接至区域E的电极垫上，并且收光元件R的顶部电极通过接线W电性连接至区域F的电极垫上。由此，可个别完成发光元件1200及收光元件R与封装基板200’之间的电性连接。之后，再将封装材料透过点胶方式包覆发光元件1200及收光元件R，封装材料定型后形成封装层320，从而可以得到光发收装置200a的封装结构。在一些实施例中，如图7A及图7B所示，为了固定封装材料于封装基板200’上，以使封装材料可透过点胶方式包覆发光元件1200及收光元件R，光发收装置200a的封装结构可更包括外框400，设置于封装基板200’的外围而环绕封装基板200’的第一部分221、第二部分222以及绝缘部分223。由此，当使用点胶方式将封装材料设置于封装基板200’上而包覆发光元件1200及收光元件R时，可以通过外框400的配置，定位尚未定型而仍可能流动的封装材料。
本实施例中，光发收装置200a的封装结构例如是应用于近接传感器(Proximity Sensor)。具体来说，透过出光表面320a的法线与收光表面320b的法线之间具有夹角β，使得由发光元件1000射出的光线不会被邻接于发光元件1000的收光元件R直接接收。如此，可以避免近接传感器在使用时(例如应用于手机或者其他电子装置)，由发光元件1000射出的光线直接被收光元件R接收，从而可以避免近接传感器的误感应。因此，由发光元件1000所发出的光线可以由障碍物反射至收光元件R，从而让近接传感器感测到障碍物的存在。
图32为本公开至少一实施例的光发收装置200b的封装结构上视图，本实施例的光发收装置200b的封装结构包括：封装基板200’、多个发光元件1200a、1200b、多个收光元件Ra、Rb以及封装层320。
本实施例中，发光元件与收光元件的数量都是二个，但并不以此为限。此外，本实施例中，发光元件与收光元件的数量相同，但亦不以此为限；在一些实施例中，也可以是一个发光元件搭配多个收光元件或者多个发光元件搭配一个收光元件。
本实施例中，封装基板200’的第一部分221更包括多个第一区域A’、B’、C’、D’，绝缘部分223更进一步位于该些第一区域之间，发光元件1200a、1200b位于部分的不同的该些第一区域上，且该些发光元件1200a、1200b透过接线W电性连接至剩余的不同的该些第一区域上。如图32所示，从封装结构2a的顶视图观之，发光元件1200a、1200b的顶部电极个别透过接线W电性连接至位于二侧的该些第一区域A’及D’上，而发光元件1200a、1200b位于不同的该些第一区域上，从而使发光元件1200a、1200b的底部电极个别电性连接至其所在的该些第一区域B’及C’上。
类似地，本实施例中，第二部份222更包括多个第二区域E’、F’、G’、H’，绝缘部分223更进一步位于该些第二区域之间，该些收光元件Ra、Rb位于部分的不同的该些第二区域上，且该些收光元件Ra、Rb透过接线W个别电性连接至剩余的不同的该些第二区域上。如图32所示，从封装结构2a的顶视图观之，收光元件Ra、Rb的顶部电极个别透过接线W电性连接至位于二侧的该些第二区域E’及H’上，而收光元件Ra、Rb位于不同的该些第二区域F’及G’上，从而使收光元件Ra、Rb的底部电极个别电性连接至其所在的该些第二区域F’及G’上。
具体来说，本实施例中，第一部分221的第一区域包含区域A’至区域D’，第二部分222的第二区域包含区域E’至区域H’。发光元件1200a位于区域B’，发光元件1200a的底部电极电性连接至区域B’的导电接垫上，且发光元件1200a的正面电极是通过接线W电性连接至区域A’的导电接垫上；发光元件1200b位于区域C’，发光元件1200b的底部电极电性连接至区域C’的导电接垫上，且发光元件1200b的正面电极是通过接线W电性连接至区域D’的导电接垫上。对应地，收光元件Ra位于区域F’，收光元件Ra的底部电极电性连接至区域F’的导电接垫上，且收光元件Ra的正面电极通过接线W电性连接至区域E’的导电接垫上；收光元件Rb位于区域G’，收光元件Rb的底部电极电性连接至区域G’的导电接垫上，且收光元件Rb的正面电极通过接线W电性连接至区域H’的导电接垫上。因此，透过本实施例，可达成发光元件1200a与发光元件1200b之间的独立电极配置以及收光元件Ra与收光元件Rb之间的独立电极配置。
图33为本公开至少一实施例的封装结构200b的上视图；本实施例的封装结构200b包括：封装基板200’、多个发光元件1200c、1200d、多个收光元件Rc、Rd以及封装层320。
本实施例中，发光元件与收光元件的数量同样也都是二个，但并不以此为限。
本实施例中，第一部分221更包括多个第一区域，绝缘部分223更进一步位于该些第一区域之间，该些发光元件1200c、1200d位于部分的不同的该些第一区域上，且该些发光元件1200c、1200d透过接线W电性连接至剩余的相同的该第一区域上。如图33所示，从封装结构200b的顶视图观之，该些发光元件1200c、1200d位于二侧的该些第一区域上，且该些发光元件1200c、1200d透过接线W电性连接至位于中间的该第一区域上。
类似地，本实施例中，第二部分222更包括多个第二区域，该绝缘部分223更进一步位于该些第二区域之间，该些收光元件Rc、Rd位于部分的不同的该些第二区域上，且该些收光元件Rc、Rd透过接线W电性连接至剩余的相同的该第二区域上。如图33所示，从封装结构200b的顶视图观之，该些收光元件Rc、Rd位于二侧的该些第二区域上，且该些收光元件Rc、Rd透过接线W电性连接至位于中间的该第二区域上。
本实施例中，第一部分221的第一区域包含区域A”-C”，第二部分222的第二区域包含区域D”-F”。发光元件1200c位于区域A”，发光元件1200c的底部电极电性连接至区域A”的导电接垫上，且发光元件1200c的正面电极是通过接线W电性连接至区域B”的导电接垫上；发光元件1200d位于区域C”，发光元件1200d的底部电极电性连接至区域C”的导电接垫上，且发光元件1200d的正面电极是通过接线W同样地电性连接至区域B”的导电接垫上。对应地，收光元件Rc位于区域D”，收光元件Rc的底部电极电性连接至区域D”的导电接垫上，且收光元件Rc的正面电极通过接线W电性连接至区域E”的导电接垫上；收光元件Rd位于区域F”，收光元件Rd的底部电极电性连接至区域F”的导电接垫上，且收光元件Rd的正面电极通过接线W电性连接至区域E”的导电接垫上。因此，透过本实施例，可达成发光元件1200c与发光元件1200d之间的共电极配置以及收光元件Rc与收光元件Rd之间 的共电极配置。
在一些实施例中，该些发光元件的发光波长可为相同或不同。
在一些实施例中，发光元件可以是垂直腔面发射激光(VCSEL)，而收光元件可以是光侦测器集成电路(Photo-Detector Integrated Circuit，PDIC)。
图34为本公开至少一实施例的封装结构300a的剖面示意图；本实施例的封装结构300a包括：封装基板230、发光元件1300、收光元件R以及封装层330。
封装基板230具有第一部分231、第二部分232以及绝缘部分233，绝缘部分233位于第一部分231与第二部分232之间。发光元件1300具有出光面1301以及表面1302，表面1302相对出光面1301并位于封装基板230上，且发光元件1300电性连接封装基板230。收光元件R具有收光面R1，其中收光元件R电性连接封装基板230。封装层330包含第一封装区域331以及第二封装区域332，第一封装区域331位于发光元件1300的出光面1301上，且第二封装区域332位于收光元件R的收光面R1上。其中第一封装区域331具有第一封装表面3311，第二封装区域332具有第二封装表面3321，且第一封装表面3311的法线方向N1与第二封装表面3321的法线方向N2之间不平行。
请继续参见图34，在本实施例中，该第一封装区域331具有第一凸部3312，且第一封装表面3311为第一凸部3312的表面。
另外，在本实施例中，第一凸部3312为斜面，且该斜面自封装层320的第一封装区域331朝向第二封装区域332爬升，但并不以此为限。
本实施例中，封装结构300a同样地应用于近接传感器。具体来说，透过第一封装表面3311的法线方向N1与第二封装表面3321的法线方向N2之间不平行，使得由发光元件1300射出的光线不会被邻接于发光元件1300的收光元件R直接接收。如此，可以避免近接传感器在使用时(例如应用于手机或者其他电子装置)，由发光元件1300射出的光线直接被收光元件R接收，从而可以避免近接传感器的误感应。因此，由发光元件1300所发出的光线可以由障碍物反射至收光元件R，从而让近接传感器感测到障碍物的存在。
图35为本公开至少一实施例的封装结构300b的剖面示意图。本实施例 中，第一封装区域331具有第一凸部3312，第二封装区域332具有第二凸部3322，第一封装表面3311为第一凸部3312的表面，且第二封装表面3321为第二凸部3322的表面。另外，在本实施例中，第一凸部3312与第二凸部3322皆呈一斜面，且第一凸部3312的斜面自封装层320的第一封装区域331朝向第二封装区域332爬升，第二凸部3322的斜面自封装层320的第二封装区域332朝向第一封装区域331爬升，进而使得第一凸部3312的最高点与第二凸部3322的最高点相互邻接，但并不以此为限。
图36为本公开至少一实施例的封装结构300c的剖面示意图。在一些实施例中，第一封装区域331具有第一凹部3313，且第一封装表面3311为第一凹部3313的表面。本实施例中，第一凹部3313完全地对应1300发光元件1300的出光面1301。换句话说，本实施例中，发光元件1300的整个出光面1301都在第一凹部3313的范围内。
图37为本公开至少一实施例的封装结构300d的剖面示意图。在一些实施例中，第一封装区域331具有第一凹部3313，且第一封装表面3311为第一凹部3313的表面。并且，本实施例中，第一凹部3313部分地对应发光元件1300的出光面1301。换句话说，本实施例中，发光元件1300的部分出光面1301在第一凹部3313的范围内。
图38为本公开至少一实施例的封装结构300e的剖面示意图。在一些实施例中，第一封装区域331具有第一成型部3312b，第一成型部3312b凸出于第一封装表面3311。本实施例中，第一成型部3312b呈圆顶状，但并不以此为限。
图39为本公开至少一实施例的封装结构300f的剖面示意图。本实施例的封装结构300f包括：封装基板240、发光元件1400、收光元件R以及封装层340。
封装基板240具有第一部分241、第二部分242以及绝缘部分243，绝缘部分243位于第一部分241与第二部分242之间。发光元件1400具有出光面1401以及表面1402，表面1402相对出光面1401并位于封装基板240上，且发光元件1400电性连接封装基板240。收光元件R具有收光面R1，其中收光元件R电性连接封装基板240。封装层340包含第一封装区域341 以及第二封装区域342，第一封装区域341位于发光元件1400的出光面1401上，第二封装区域342位于收光元件R的收光面R1上，其中第一封装区域341具有第一封装表面3411，第一封装区域341还具有第一成型部3412，第二封装区域342具有第二封装表面3421，且第一成型部3412突出于第一封装表面3411。本实施例中，第一成型部3412呈圆顶状，但并不以此为限。
图40为本公开至少一实施例的封装结构300g的剖面示意图。相较于第十一实施例，本实施例的封装基板240a更包括环绕部244，环绕第一部分241、第二部分242以及绝缘部分243，从而围绕封装层340。
图41为本公开至少一实施例的封装结构300h的剖面示意图。相较于第十一实施例，本实施例的封装结构300h更包括一阻挡层BL，位于该第一封装区域341与该第二封装区域342之间。其中，阻挡层BL是由不透光材料所制成，例如塑料或黑色环氧树脂。由此，可透过位于该第一封装区域341与该第二封装区域342之间的阻挡层BL将光线吸收，从而避免由发光元件1400所射出的侧向光线直接被收光元件R接收而造成近接传感器的感测误差。
在一些实施例中，阻挡层BL的截面形状非呈现矩形。换句话说，在一些实施例中，阻挡层BL的截面形状也可以是梯形或者不规则形。
图42为本公开至少一实施例的封装结构300i的剖面示意图。相较于第十一实施例，本实施例的封装结构300i的封装层340更具有间隙GS，位于该第一封装区域341与该第二封装区域342之间。由此，可透过第一封装区域341与第二封装区域342之间的间隙GS，使得由发光元件1400所射出的侧向光线需经过封装层340的第一封装区域341、间隙GS以及封装层340的第二封装区域342，而由于封装层340与间隙GS具有不同折射率，由发光元件1400所射出的侧向光线较不易直接被收光元件R接收，从而避免造成近接传感器的感测误差。
图43为本公开至少一实施例的封装结构300j的剖面示意图。在一些实施例中，封装结构300j更包括一挡墙400a，其中该挡墙400a与封装基板240共同界定第一容置空间401a与第二容置空间402a，发光元件1400位于第一容置空间401a内，而收光元件R位于第二容置空间402a内。第一容置空间 401a具有第一开口401a1，且第二容置空间402a具有第二开口402a1。其中，一部分的第一封装表面3411自第一开口401a1露出，且一部分的第二封装表面3421自第二开口402a1露出。换句话说，本实施例中，一部分的第一封装表面3411被挡墙400a遮挡，且一部分的第二封装表面3421亦同样地被挡墙400a遮挡。挡墙400a可以由不透光材料所制成，例如塑料或黑色环氧树脂。由此，依据本实施例，可透过挡墙400a遮挡部分的第一封装表面3411以及部分的第二封装表面3421，从而使得由发光元件1400所射出的不易直接被收光元件R接收，从而避免造成近接传感器的感测误差。
图44A为本公开至少一实施例的封装结构300k的剖面示意图，图44B为图44A实施例的封装结构300k的上视图。本实施例的封装结构300k包括：封装基板250a、多个发光元件1500a、1500b、至少一收光元件R以及封装层350’。
本实施例中，发光元件1500a、1500b的数量是二个，而收光元件R的数量是一个，从而构成单一收光元件搭配多个发光元件的态样，但并不以此为限。
封装基板250具有第一部分251、第二部分252以及绝缘部分253，绝缘部分253位于第一部分251与第二部分252之间。其中，第一部分251具有多个区域，分别对应该些发光元件1500a、1500b。各发光元件1500a、1500b具有出光面1501以及表面1502，表面1502相对出光面1501并位于封装基板250上，且各发光元件1500a、1500b电性连接该封装基板250。收光元件R具有收光面R1，其中收光元件R电性连接封装基板250。
本实施例中，请同时参照图44A及图44B，第一部分251的子区域B1对应发光元件1500a，而第一部分251的子区域C1对应发光元件1500b。具体而言，请参见图44B，本实施例中，发光元件1500a位于区域B1，发光元件1500a的底部电极电性连接至区域B1的导电接垫上，且发光元件1500a的正面电极是通过接线W电性连接至区域A1的导电接垫上；发光元件1500b位于区域C1，发光元件1500b的底部电极电性连接至区域C1的导电接垫上，且发光元件1500b的正面电极是通过接线W电性连接至区域D1的导电接垫上。对应地，收光元件R位于区域E1，收光元件R的底部电极电性连 接至区域E1的导电接垫上，且收光元件R的正面电极通过接线W电性连接至区域F1的导电接垫上。
封装层350’包含第一封装区域351以及第二封装区域352，第一封装区域351位于发光元件1500a、1500b的出光面1501上，而第二封装区域352位于收光元件R的收光面R1上。
请再参见图44A及图44B。对应子区域A1与子区域B1的第一封装区域351具有封装表面3511a，对应子区域C1与子区域D1的第一封装区域351具有封装表面3511b，而第二封装区域352具有第二封装表面3521。换句话说，本实施例中，第一封装区域351对应到第一部分251的子区域A1与子区域B1的表面为封装表面3511a，第一封装区域351对应到第一部分251的子区域C1与子区域D1的表面为封装表面3511b，而第二封装区域352对应到第二部分252的子区域E1与子区域F1的表面为第二封装表面3521。其中，该些封装表面3511a、3511b的法线方向N1a、N1b之间彼此不平行，且各该封装表面3511a、3511b的法线方向N1a、N1b与该第二封装表面3521的法线方向N2之间彼此亦不平行。
本实施例中，封装结构300k同样地应用于近接传感器。具体来说，透过该些封装表面3511a、3511b的法线方向N1a、N1b之间彼此不平行，且各该封装表面3511a、3511b的法线方向N1a、N1b与该第二封装表面3521的法线方向N2之间彼此亦不平行，使得由发光元件1500a、1500b射出的光线不会被邻接于发光元件1500a、1500b的收光元件R直接接收。如此，可以避免近接传感器在使用时(例如应用于手机或者其他电子装置)，由发光元件1500a、1500b射出的光线直接被收光元件R接收，从而可以避免近接传感器的误感应。因此，由发光元件1500a、1500b所发出的光线可以由障碍物反射至收光元件R，从而让近接传感器感测到障碍物的存在。
上述具体实施方式，并不构成对本公开保护范围的限制。本领域技术人员应该明白的是，取决于设计要求和其他因素，可以发生各种各样的修改、组合、子组合和替代。任何在本公开的精神和原则的内所作的修改、等同替换和改进等，均应包含在本公开的保护范围内。

Claims (9)

  1. 一种半导体激光器，包括：
    半导体叠层，具有第一表面、第二表面以及侧面，所述第二表面与所述第一表面相对，所述侧面位于所述第一表面及所述第二表面之间，所述半导体叠层包括：
    第一型半导体层；
    第二型半导体层；以及
    活性层，位于所述第一型半导体层与所述第二型半导体层之间；
    第一电极结构，位于所述第一表面及所述侧面上；
    第二电极结构，位于所述第二型半导体层上且电性连接所述第二型半导层；以及
    绝缘层，位于所述半导体叠层与所述第一电极结构之间，以及位于所述半导体叠层与所述第二电极结构之间，其中，所述绝缘层具有位于所述第一表面上的第一开口，所述第一电极结构分布至所述第一开口中并接触所述第一型半导体层。
  2. 根据权利要求1所述的半导体激光器，其中，所述侧面相对于所述第一表面具有夹角，所述夹角的角度分布范围为90度(含)至120度(含)之间。
  3. 根据权利要求1或2所述的半导体激光器，还包含基层，其中，所述基层位于所述第二型半导体层相对于所述第一型半导体层的一侧。
  4. 根据权利要求3所述的半导体激光器，其中，所述第二电极结构位于所述基层上；以及所述绝缘层还具有第二开口，所述第二开口位于所述第二型半导体层的表面上，所述第二电极结构分布至所述第二开口中并接触所述第二型半导体层。
  5. 根据权利要求3或4所述的半导体激光器，其中，所述绝缘层位于所述第一表面及所述侧面上。
  6. 根据权利要求3-5任一项所述的半导体激光器，其中所述基层具有第三表面以及连接所述第三表面的侧面，所述绝缘层及所述第二电极结构分布 至所述基层的所述侧面上。
  7. 根据权利要求3-6任一项所述的半导体激光器，还包括：
    黏着层，位于所述第二型半导体层与所述基层之间，其中，所述基层通过所述黏着层邦定至所述半导体叠层。
  8. 根据权利要求1-7任一项所述的半导体激光器，其中，所述第一型半导体层中或所述第二型半导体层中、或所述第一型半导体层中与所述第二型半导体层中具有反射镜层。
  9. 根据权利要求3所述的半导体激光器，其中，
    所述基层为导电层且接触所述第二型半导体层，
    所述绝缘层具有第二开口位于所述基层的表面上，
    所述第二电极结构包含接触电极部及延伸电极部，其中，所述延伸电极部连接所述接触电极部，所述接触电极部位于所述第二开口且所述延伸电极部自所述第二开口延伸分布至所述侧面上。
PCT/CN2023/077719 2022-02-25 2023-02-22 半导体激光器及其封装结构 WO2023160589A1 (zh)

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