WO2023159669A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023159669A1
WO2023159669A1 PCT/CN2022/079222 CN2022079222W WO2023159669A1 WO 2023159669 A1 WO2023159669 A1 WO 2023159669A1 CN 2022079222 W CN2022079222 W CN 2022079222W WO 2023159669 A1 WO2023159669 A1 WO 2023159669A1
Authority
WO
WIPO (PCT)
Prior art keywords
power supply
supply line
nth
column
positive power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2022/079222
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English (en)
French (fr)
Inventor
霍雯雪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
TCL China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TCL China Star Optoelectronics Technology Co Ltd filed Critical TCL China Star Optoelectronics Technology Co Ltd
Priority to US17/755,515 priority Critical patent/US12154483B2/en
Publication of WO2023159669A1 publication Critical patent/WO2023159669A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and a display device.
  • Self-illuminating pixel circuits usually require positive and negative power supply lines to provide power to achieve normal display functions. The difference changes, resulting in large differences in the power supply voltage transmitted to each pixel circuit, which in turn causes the luminance of each pixel circuit to be different, reducing the display quality.
  • the present application provides a display panel and a display device, so as to alleviate the technical problem that the power supply voltage transmitted to each pixel circuit in the same column is greatly different.
  • the present application provides a display panel, which includes M columns of pixel circuits, M negative power supply lines, and M positive power supply lines.
  • the M columns of pixel circuits are arranged in sequence along the first direction, and each column of pixel circuits includes A plurality of pixel circuits arranged in sequence along the second direction, M is a positive integer;
  • M negative power supply lines are arranged in sequence along the first direction, wherein the Nth negative power supply line is located in the Nth column of the pixel circuit in the first On one side of the direction, the Nth negative power supply line is electrically connected to each pixel circuit in the Nth column of pixel circuits, N is a positive integer less than or equal to M;
  • the M positive power supply lines are arranged in sequence along the first direction cloth, wherein the Nth positive power supply line is located on the other side of the Nth column of pixel circuits in the first direction, and the Nth positive power supply line is electrically connected to each pixel circuit in the Nth column of pixel circuits; wherein ,
  • the display panel is provided with a first area, a second area and a third area distributed in sequence along the second direction, the input terminal of the Nth negative power supply line or the input end of the Nth positive power supply line One of the terminals is located in the first area, the other of the input end of the Nth negative power supply line or the input end of the Nth positive power supply line is located in the third area, and the M column pixel circuits are located in the second area.
  • the Nth negative power supply wiring, the Nth column of pixel circuits, and the Nth positive power supply wiring are sequentially arranged along the first direction, or, the Nth positive power supply wiring, the Nth column of pixels The circuit and the Nth negative power supply line are sequentially arranged along the first direction.
  • the transmission paths from the input end of the Nth negative power supply line and the input end of the Nth positive power supply line to any pixel circuit in the Nth column of pixel circuits are equal in length.
  • the N-1th negative power supply line is located on one side of the N-1th column pixel circuit in the first direction, and the N-1th negative power supply line is connected to the N-1th column pixel circuit
  • Each pixel circuit in is electrically connected, and N is an even number
  • the N-1th positive power supply line is located on the other side of the N-1th column pixel circuit in the first direction, and the N-1th positive power supply line It is electrically connected to each pixel circuit in the N-1th column of pixel circuits; wherein, the input end of the N-1th negative power supply line is set on the same side as the input end of the N-1th positive power supply line.
  • the N+1th negative power supply line is located on one side of the N+1th column pixel circuit in the first direction, and the N+1th negative power supply line is connected to the N+1th column pixel circuit
  • Each pixel circuit in is electrically connected, N+1 is less than or equal to M and N is an odd number
  • the N+1th positive power supply line is located on the other side of the pixel circuit in the N+1th column in the first direction, and the Nth
  • the +1 positive power supply line is electrically connected to each pixel circuit in the N+1th column of pixel circuits; wherein, the input end of the N+1th negative power supply line is connected to the input of the N+1th positive power supply line Set on the same side as the end.
  • the display panel is provided with a first area, a second area and a third area distributed in sequence along the second direction, the input end of the N+1th negative power supply line, the N+1th positive power supply line
  • the input ends of the wires are all located in the first area or the third area; the M columns of pixel circuits are located in the second area.
  • the N+1th negative power supply wiring, the N+1th column of pixel circuits, and the N+1th positive power supply wiring are sequentially arranged along the first direction, or, the N+1th positive power supply wiring
  • the power supply wiring, the N+1th column of pixel circuits, and the N+1th negative power supply wiring are sequentially arranged along the first direction.
  • the transmission path lengths from the input end of the N+1th negative power supply line and the input end of the N+1th positive power supply line to any pixel circuit in the N+1th column of pixel circuits are respectively equal.
  • the Nth negative power supply wiring, the Nth column of pixel circuits, the Nth positive power supply wiring, the N+1th negative power supply wiring, the N+1th column of pixel circuits, and the N+th One positive power supply line is sequentially arranged along the first direction.
  • the present application provides a display device, which includes the display panel in at least one embodiment above, at least one of the M negative power supply lines is used to transmit a power supply negative signal, and at least one of the M positive power supply lines One is used to transmit the power positive signal.
  • a negative power supply line and a positive power supply line are respectively arranged on both sides of a column of pixel circuits, and the input end of the negative power supply line is on the opposite side to the input end of the positive power supply line Setting, the voltage in the positive power supply line can be gradually reduced, while the voltage in the negative power supply line is gradually increased, thereby reducing or eliminating the difference in power supply voltage transmitted to each pixel circuit in the same column, and improving the brightness of the display Uniformity.
  • FIG. 1 is a schematic structural diagram of a display panel in the related art.
  • FIG. 2 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 3 is another schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of the pixel circuit shown in FIG. 2 or FIG. 3 .
  • first and second are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of said features.
  • “plurality” means two or more, unless otherwise specifically defined.
  • connection should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected, or integrally connected; it can be mechanically connected, electrically connected or can communicate with each other; it can be directly connected or indirectly connected through an intermediary, and it can be the internal communication of two components or the interaction of two components relation. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present disclosure according to specific situations.
  • a first feature being “on” or “under” a second feature may include the first feature being in direct contact with the second feature, or may include the first feature and the second feature.
  • the two features are not in direct contact but through a third feature other than them.
  • “above”, “above” and “above” the first feature on the second feature include that the first feature is directly above and obliquely above the second feature, or simply means that the level of the first feature is higher than that of the second feature.
  • "Below”, “beneath” and “under” the first feature to the second feature include that the first feature is directly below and obliquely below the second feature, or simply means that the horizontal height of the first feature is smaller than that of the second feature.
  • FIG. 1 is a schematic structural diagram of a display panel in the related art.
  • the display panel includes M columns of pixel circuits, where M can be a positive integer, for example, column pixel circuits PL1 , column pixel circuits PL2 . . . and column pixel circuits PLM.
  • M can be a positive integer, for example, column pixel circuits PL1 , column pixel circuits PL2 . . . and column pixel circuits PLM.
  • Each column of pixel circuits includes a plurality of pixel circuits. It should be noted that, in this embodiment, each pixel circuit is represented by a diode symbol as shown in FIG. 1 .
  • the display panel shown in FIG. 1 also includes M negative power supply lines, for example, negative power supply lines VSL1, negative power supply lines VSL2... and negative power supply lines VSLM, each negative power supply line is connected to a corresponding row of pixels
  • the circuit is electrically connected to transmit the negative signal of the power supply to the pixel circuit of the corresponding row.
  • the arrow close to VSL1 in Figure 1 is used to represent the input end of the negative power supply line VSL1. It can be understood that as the power supply negative signal is connected from the input end of the negative power supply line VSL1 and transmitted in the direction indicated by the arrow Or during the transmission process, due to the resistance of the negative power supply line VSL1 itself, the potential of the negative signal of the power supply is gradually raised.
  • the display panel shown in FIG. 1 also includes M positive power supply lines, for example, positive power supply lines VDL1, positive power supply lines VDL2... and positive power supply lines VDLM, each positive power supply line is connected to a corresponding row of pixels
  • the circuit is electrically connected to transmit the positive signal of the power supply to the pixel circuit of the corresponding row.
  • the arrow close to VDL1 in Figure 1 is used to represent the input end of the positive power supply line VDL1. It can be understood that as the positive power signal is connected from the input end of the positive power supply line VDL1 and transmitted in the direction indicated by the arrow Or during the transmission process, due to the resistance of the positive power supply line VDL1 itself, the potential of the positive power signal is gradually pulled down.
  • each column of pixel circuits in FIG. 1 is respectively configured with a negative power supply line and a positive power supply line.
  • one side of the M column pixel circuit PLM is configured with a negative power supply line VSLM and a positive power supply line VDLM, and Since the input terminal of the negative power supply line VSLM and the input terminal of the positive power supply line VDLM are located at the same end of the pixel circuit, for example, both are located below the pixel circuit, so, with the gradual increase of the negative power supply signal and the positive power supply signal The signal is gradually pulled down, and the voltage difference between the positive power supply signal and the negative power supply signal transmitted to the same pixel circuit is gradually changing, for example, gradually decreasing, which makes the distance between the negative power supply line and/or the positive power supply line As the input ends get farther and farther away, the luminance of each column of pixel circuits decreases gradually when the luminance of other pixel circuits that affect them remains unchanged, which in turn causes differences in the luminance of the entire display panel and affects the display quality
  • this embodiment provides a display panel, as shown in FIG. 2 or FIG. 3, the display panel includes M columns of pixel circuits, for example, column pixel circuits PL1, column pixel circuits PL2. .. and column pixel circuits PLM, M columns of pixel circuits are arranged sequentially along the first direction DR1, each column of pixel circuits includes a plurality of pixel circuits arranged in sequence along the second direction DR2, for example, the column pixel circuit PL2 includes a plurality of pixel circuits along the second direction DR2 The pixel circuits P10 are sequentially arranged in the second direction DR2.
  • M is a positive integer.
  • the display panel when M is equal to 1, the display panel only includes the column pixel circuit PL1; when M is equal to 2, the display panel includes the column pixel circuit PL1 and the column pixel circuit PL2; it can be understood that, M can also be other positive integers such as 3, 4 or 5.
  • the display panel as shown in FIG. 2 or FIG. 3 may further include M negative power supply lines, for example, negative power supply lines VSL1, negative power supply lines VSL2... and negative power supply lines VSLM , the M negative power supply lines are sequentially arranged along the first direction DR1.
  • M negative power supply lines for example, negative power supply lines VSL1, negative power supply lines VSL2... and negative power supply lines VSLM , the M negative power supply lines are sequentially arranged along the first direction DR1.
  • the Nth negative power supply line is located on the side of the Nth column of pixel circuits in the first direction DR1, the Nth negative power supply line is electrically connected to each pixel circuit in the Nth column of pixel circuits, and N is less than Or a positive integer equal to M, for example, the negative power supply line VSL1 is located on the left side of the column pixel circuit PL1 in the first direction DR1, and the negative power supply line VSL1 is electrically connected to each pixel circuit in the column pixel circuit PL1.
  • the negative power supply line VSL1 is located on the left side of the column pixel circuit PL1 in the first direction DR1. It can be understood that the negative power supply line VSL1 is located on the left side of the column pixel circuit PL1. On the right side in the first direction DR1 is also possible.
  • the display panel shown in FIG. 2 or FIG. 3 may further include M positive power supply lines, for example, positive power supply lines VDL1, positive power supply lines VDL2... and positive power supply lines VDLM , the M positive power supply lines are sequentially arranged along the first direction DR1.
  • M positive power supply lines for example, positive power supply lines VDL1, positive power supply lines VDL2... and positive power supply lines VDLM , the M positive power supply lines are sequentially arranged along the first direction DR1.
  • the Nth positive power supply line is located on the other side of the Nth column of pixel circuits in the first direction DR1, and the Nth positive power supply line is electrically connected to each pixel circuit in the Nth column of pixel circuits, for example,
  • the positive power supply line VDL1 is located on the right side of the column pixel circuit PL1 in the first direction DR1 , and the positive power supply line VDL1 is electrically connected to each pixel circuit in the column pixel circuit PL1 .
  • the positive power supply line VDL1 is located on the right side of the column pixel circuit PL1 in the first direction DR1. It can be understood that the positive power supply line VDL1 is located on the right side of the column pixel circuit PL1 It is also possible to be on the left side in the first direction DR1 , as long as the positive power supply line VDL1 and the negative power supply line VSL1 are located on the same side of the column pixel circuit PL1 as long as it is avoided.
  • the input end of the Nth negative power supply line is arranged opposite to the input end of the Nth positive power supply line.
  • the input end of the negative power supply line VSL1 is located above the pixel circuit in the second direction DR2, specifically the upper frame area of the display panel; the input end of the positive power supply line VDL1 is located above the pixel circuit in the second direction DR2.
  • the lower part may specifically be the lower frame area of the display panel.
  • the input end of the negative power supply line VSL1 is located below the pixel circuit in the second direction DR2, which may be specifically the lower frame area of the display panel; the input end of the positive power supply line VDL1 is located at the pixel circuit in the second direction
  • the upper side in the direction DR2 may specifically be the upper frame area of the display panel.
  • a negative power supply line and a positive power supply line are respectively arranged on both sides of a column of pixel circuits, and the input terminal of the negative power supply line is connected to the input terminal of the positive power line End-to-side arrangement, for example, each column of pixel circuits in the display panel shown in Figure 2 is configured in this way, while only odd-numbered or even-numbered pixel circuits in the display panel shown in Figure 3 are configured in this way, understandably Yes, all of them can make the voltage in the positive power supply line gradually decrease, and the voltage in the negative power supply line gradually increase, thereby reducing or eliminating the difference in power supply voltage transmitted to each pixel circuit in the same column, which can improve the display performance. uniformity of brightness.
  • the power supply voltage may be the voltage difference between the power supply positive signal and the power supply negative signal.
  • the display panel is provided with a first area NA1, a second area AA1, and a third area NA2 sequentially distributed along the second direction DR2, the input end of the Nth negative power supply line or the Nth positive power supply line One of the input ends of the wiring is located in the first area NA1, the other of the input end of the Nth negative power supply wiring or the input end of the Nth positive power supply wiring is located in the third area NA2, and the M column pixel circuits are located in The second area AA1.
  • the first area NA1 may be one of the upper frame area or the lower frame area of the display panel, and the third area NA2 may be the other of the upper frame area or the lower frame area of the display panel.
  • the first area NA1 may also be one of the left frame area or the right frame area of the display panel, and the third area NA2 may also be the other of the left frame area or the right frame area of the display panel. It can be understood that, in this way, the input end of the negative power supply line and the input end of the positive power line electrically connected to the same column of pixel circuits can be configured as opposite sides.
  • the Nth negative power supply wiring, the Nth column of pixel circuits, and the Nth positive power supply wiring are sequentially arranged along the first direction DR1, or, the Nth positive power supply wiring, the Nth column
  • the pixel circuit and the Nth negative power supply line are sequentially arranged along the first direction DR1.
  • the negative power supply line VSL1, the column pixel circuit PL1 and the positive power supply line VDL1 are sequentially arranged along the first direction DR1, or the positive power supply line VDL1, the column pixel circuit PL1 and the negative power supply line VSL1 are arranged along the first direction DR1. Arranged in sequence. It can be understood that, in this way, it can be ensured that the negative power supply trace VSL1 and the positive power supply trace VDL1 are respectively located on both sides of the column pixel circuit PL1 in the first direction DR1, so that the negative power supply trace and the positive power supply trace can be extended and routed to the corresponding Column pixel circuits without crossing or overlapping of negative power supply lines and positive power supply lines in the thickness direction of the display panel.
  • the lengths of the transmission paths from the input end of the Nth negative power supply line and the input end of the Nth positive power supply line to any pixel circuit in the same column of pixel circuits are equal, which can It is further ensured that the voltage difference between the positive power signal and the negative power signal in the corresponding transmission paths is consistent, thereby helping to improve the brightness uniformity of the display panel.
  • the N-1th negative power supply line is located on one side of the N-1th column pixel circuit in the first direction, and the N-1th negative power supply line is connected to the N-1th column pixel circuit
  • Each pixel circuit in is electrically connected, and N is an even number
  • the N-1th positive power supply line is located on the other side of the N-1th column pixel circuit in the first direction, and the N-1th positive power supply line It is electrically connected to each pixel circuit in the N-1th column of pixel circuits; wherein, the input end of the N-1th negative power supply line is set on the same side as the input end of the N-1th positive power supply line.
  • the N+1th negative power supply line is located on the side of the N+1th column of pixel circuits in the first direction DR1, and the N+1th negative power supply line is connected to the Each pixel circuit in the N+1th column of pixel circuits is electrically connected, N+1 is less than or equal to M and N is an odd number; the N+1th positive power supply line is located in the N+1th column of the pixel circuit in the first direction DR1 On the other side, the N+1th positive power supply line is electrically connected to each pixel circuit in the N+1th column of pixel circuits; wherein, the input end of the N+1th negative power supply line is connected to the N+th The input terminal of 1 positive power supply line is set on the same side.
  • the input terminal of the negative power supply line VSLM-1 electrically connected to the column pixel circuit PLM-1 is located above the pixel circuit in the second direction DR2, and the input end of the negative power supply line VSLM electrically connected to the column pixel circuit PLM The input terminal is located below the pixel circuit in the second direction DR2; and the input terminal of the positive power supply line VDLM-1 electrically connected to the column pixel circuit PLM-1, and the positive power supply line electrically connected to the column pixel circuit PLM The input terminals of VDLM are located below the pixel circuit in the second direction DR2.
  • every other row of pixel circuits adjusts the input end of the negative power supply line to be on the opposite side to the input end of the corresponding positive power supply line. setting, the attenuation ability of the potential of the negative power signal transmitted to two adjacent pixel circuits can be reversed, and the difference in current and brightness caused by the large difference in the potential of the negative power signal between the pixel circuits in the entire display panel can be reduced. Further, the brightness uniformity of the display panel is improved.
  • the display panel shown in Figure 3 only adjusts the setting position of the input end of part of the negative power supply line, and does not adjust all of the display panel shown in Figure 2
  • the setting position of the input end of the negative power supply line can improve the brightness uniformity of the display panel with a small change.
  • the display panel is provided with a first area NA1, a second area AA1 and a third area NA2 which are sequentially distributed along the second direction DR2, and the N+1th negative power supply line Both the input end and the input end of the N+1th positive power supply line are located in the first area NA1 or the third area NA2 ; the M columns of pixel circuits are located in the second area AA1 .
  • the N+1th negative power supply line, the N+1th column of pixel circuits, and the N+1th positive power supply line are sequentially arranged along the first direction DR1, or , the N+1th positive power supply line, the N+1th column of pixel circuits and the N+1th negative power supply line are sequentially arranged along the first direction DR1.
  • the transmission path lengths from the input end of the N+1th negative power supply line and the input end of the N+1th positive power supply line to any pixel circuit in the N+1th column of pixel circuits are respectively equal.
  • the Nth negative power supply wiring, the Nth column of pixel circuits, the Nth positive power supply wiring, the N+1th negative power supply wiring, the N+1th column of pixel circuits, and the N+th One positive power supply line is sequentially arranged along the first direction DR1.
  • the Nth negative power supply line in the above embodiment may be, but not limited to, the negative power supply line VSL1, and the Nth positive power supply line may be, but not limited to, the positive power supply line VDL1.
  • the N+1th negative power supply line may be a negative power supply line VSL2, and the N+1th positive power supply line may be a positive power supply line VDL2.
  • the Nth negative power supply line can be, but not limited to, a negative power supply line VSLM-1
  • the Nth positive power supply line can be, but not limited to, a positive power supply line VDLM-1.
  • the N+1th line The negative power supply line may be a negative power supply line VSLM, and the N+1th positive power supply line may be a positive power supply line VDLM.
  • any pixel circuit P10 in FIG. 1 to FIG. 3 may be as shown in FIG. LED, one of the source/drain of the driving transistor T2 is connected to the positive power signal VDD transmitted by the positive power supply line, the other of the source/drain of the driving transistor T2 is connected to one end of the storage capacitor Cst, and the terminal of the transistor T3
  • One of the source/drain is electrically connected to the anode of the light-emitting device LED
  • the other of the source/drain of the transistor T3 is connected to the reference voltage signal Vref
  • the gate of the transistor T3 is connected to the sensing control signal Vsensing
  • the cathode of the light-emitting device LED is connected to the negative power supply signal VSS transmitted by the negative power supply line
  • the gate of the driving transistor T2 is electrically connected to the other end of the storage capacitor Cst
  • one of the source/drain of the transistor T1 The other of the source/drain is connected to the data signal
  • the pixel circuit P10 shown in FIG. 4 may further include at least one of a parasitic capacitance Cgs, a parasitic capacitance Cgs1, and a parasitic capacitance Cgs2. Parasitic capacitance generated between gate and drain or source.
  • the light emitting device LED may be any one of submillimeter light emitting diodes, micro light emitting diodes and organic light emitting diodes.
  • this embodiment provides a display device, which includes the display panel in at least one embodiment above, at least one of the M negative power supply lines is used to transmit the negative signal of the power supply, and the M positive power supply lines At least one of the lines is used to transmit a power positive signal.
  • a negative power supply line and a positive power supply line are respectively arranged on both sides of a column of pixel circuits, and the input terminal of the negative power supply line is connected with the input terminal of the positive power line
  • the end-to-side arrangement can make the voltage in the positive power supply line gradually decrease, while the voltage in the negative power supply line gradually increases, thereby reducing or eliminating the difference in power supply voltage transmitted to each pixel circuit in the same column, which can improve Display brightness uniformity.
  • the above-mentioned display panel may be, but not limited to, a direct display panel constructed of submillimeter light-emitting diodes.
  • At least one of the positive power supply trace and the negative power supply trace is usually thickened and/or thickened to solve the problem of the difference in power supply voltage, but this solution will be limited by the process capability and Due to the limitation of layout space, the complexity and difficulty of improvement are relatively large, and the effect of improvement needs to be further improved.

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Abstract

一种显示面板及显示装置，显示面板包括M列像素电路（PL1,PL2，…，PLM）、M条负电源走线（VSL1,VSL2，…，VSLM）以及M条正电源走线（VDL1,VDL2，…，VDLM），通过在一列像素电路的两侧分别配置一负电源走线、一正电源走线，负电源走线与正电源走线的输入端对侧设置，正电源走线中的电压逐渐减低，负电源走线中的电压逐渐抬高，减小了传输至各像素电路的电源电压差异。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板及显示装置。
 背景技术
自发光型像素电路通常需要正电源走线、负电源走线来提供电源，以实现正常的显示功能，但是，正电源走线、负电源走线在传输电源的过程中由于自身的损耗存在压差变化，导致传输至每个像素电路的电源电压的差异较大，进而会导致每个像素电路的发光亮度不同，降低了显示品质。
需要注意的是，上述关于背景技术的介绍仅仅是为了便于清楚、完整地理解本申请的技术方案。因此，不能仅仅由于其出现在本申请的背景技术中，而认为上述所涉及到的技术方案为本领域所属技术人员所公知。
 技术问题
本申请提供一种显示面板及显示装置，以缓解传输至同一列中各像素电路的电源电压差异较大的技术问题。
 技术解决方案
第一方面，本申请提供一种显示面板，其包括M列像素电路、M条负电源走线以及M条正电源走线，M列像素电路沿第一方向依次排布，每列像素电路包括多个沿第二方向依次排布的像素电路，M为正整数；M条负电源走线沿第一方向依次排布，其中，第N条负电源走线位于第N列像素电路在第一方向上的一侧，第N条负电源走线与第N列像素电路中每个像素电路电性连接，N为小于或者等于M的正整数；M条正电源走线沿第一方向依次排布，其中，第N条正电源走线位于第N列像素电路在第一方向上的另一侧，第N条正电源走线与第N列像素电路中每个像素电路电性连接；其中，第N条负电源走线的输入端与第N条正电源走线的输入端对侧设置。
在其中一些实施方式中，显示面板设置有沿第二方向依次分布的第一区域、第二区域以及第三区域，第N条负电源走线的输入端或者第N条正电源走线的输入端中的一个位于第一区域，第N条负电源走线的输入端或者第N条正电源走线的输入端中的另一个位于第三区域，M列像素电路位于第二区域。
在其中一些实施方式中，第N条负电源走线、第N列像素电路以及第N条正电源走线沿第一方向依次排布，或者，第N条正电源走线、第N列像素电路以及第N条负电源走线沿第一方向依次排布。
在其中一些实施方式中，第N条负电源走线的输入端、第N条正电源走线的输入端分别至第N列像素电路中任一像素电路的传输路径长度相等。
在其中一些实施方式中，第N-1条负电源走线位于第N-1列像素电路在第一方向上的一侧，第N-1条负电源走线与第N-1列像素电路中每个像素电路电性连接，且N为偶数；第N-1条正电源走线位于第N-1列像素电路在第一方向上的另一侧，第N-1条正电源走线与第N-1列像素电路中每个像素电路电性连接；其中，第N-1条负电源走线的输入端与第N-1条正电源走线的输入端同侧设置。
在其中一些实施方式中，第N+1条负电源走线位于第N+1列像素电路在第一方向上的一侧，第N+1条负电源走线与第N+1列像素电路中每个像素电路电性连接，N+1小于或者等于M且N为奇数；第N+1条正电源走线位于第N+1列像素电路在第一方向上的另一侧，第N+1条正电源走线与第N+1列像素电路中每个像素电路电性连接；其中，第N+1条负电源走线的输入端与第N+1条正电源走线的输入端同侧设置。
在其中一些实施方式中，显示面板设置有沿第二方向依次分布的第一区域、第二区域以及第三区域，第N+1条负电源走线的输入端、第N+1条正电源走线的输入端均位于第一区域或者第三区域；M列像素电路位于第二区域。
在其中一些实施方式中，第N+1条负电源走线、第N+1列像素电路以及第N+1条正电源走线沿第一方向依次排布，或者，第N+1条正电源走线、第N+1列像素电路以及第N+1条负电源走线沿第一方向依次排布。
在其中一些实施方式中，第N+1条负电源走线的输入端、第N+1条正电源走线的输入端分别至第N+1列像素电路中任一像素电路的传输路径长度相等。
在其中一些实施方式中，第N条负电源走线、第N列像素电路、第N条正电源走线、第N+1条负电源走线、第N+1列像素电路以及第N+1条正电源走线沿第一方向依次排布。
第二方面，本申请提供一种显示装置，其包括上述至少一实施方式中的显示面板，M条负电源走线中的至少一条用于传输电源负信号，M条正电源走线中的至少一条用于传输电源正信号。
 有益效果
本申请提供的显示面板及显示装置，通过在一列像素电路的两侧分别配置一条负电源走线、一条正电源走线，且负电源走线的输入端与正电源走线的输入端对侧设置，可以使得正电源走线中的电压逐渐减低，而负电源走线中的电压逐渐抬高，进而减小或者消除了传输至同一列中各像素电路的电源电压差异，能够提高显示的亮度均一性。
 附图说明
图1为相关技术中显示面板的结构示意图。
图2为本申请实施例提供的显示面板的一种结构示意图。
图3为本申请实施例提供的显示面板的另一种结构示意图。
图4为图2或者图3中所示像素电路的结构示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
在本公开的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系均为基于附图所示的方位或位置关系，仅是为了便于简化描述本公开，而不是指示或暗示所指的装置或组件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本公开的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本公开的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个组件内部的连通或两个组件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
在本公开中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一特征和第二特征直接接触，也可以包括第一特征和第二特征不是直接接触而是通过它们之外的第三特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征的水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征的水平高度小于第二特征。
如图1所示为相关技术中显示面板的结构示意图，该显示面板包括M列像素电路，M可以为正整数，例如，列像素电路PL1、列像素电路PL2...以及列像素电路PLM。每列像素电路包括多个像素电路，需要进行说明的是，在本实施例中，每个像素电路被表征为如图1中所示的二极管符号。
图1所示的显示面板还包括M条负电源走线，例如，负电源走线VSL1、负电源走线VSL2...以及负电源走线VSLM，每条负电源走线与一对应列像素电路电性连接以传输电源负信号至对应列的像素电路。图1中与VSL1靠近的箭头用于表征负电源走线VSL1的输入端，可以理解的是，随着电源负信号从负电源走线VSL1的输入端接入并向该箭头所指示方向的传送或者传输的过程中，由于负电源走线VSL1自身线路存在的电阻，电源负信号的电位逐渐地被抬高。
图1所示的显示面板还包括M条正电源走线，例如，正电源走线VDL1、正电源走线VDL2...以及正电源走线VDLM，每条正电源走线与一对应列像素电路电性连接以传输电源正信号至对应列的像素电路。图1中与VDL1靠近的箭头用于表征正电源走线VDL1的输入端，可以理解的是，随着电源正信号从正电源走线VDL1的输入端接入并向该箭头所指示方向的传送或者传输的过程中，由于正电源走线VDL1自身线路存在的电阻，电源正信号的电位逐渐地被拉低。
而图1每列像素电路分别被配置了一条负电源走线和一条正电源走线，例如，M列像素电路PLM的一侧配置了一条负电源走线VSLM和一条正电源走线VDLM，且由于负电源走线VSLM的输入端与正电源走线VDLM的输入端位于像素电路的同一端，例如，两者均位于像素电路的下方，如此以来，随着负电源信号的逐步抬高和正电源信号逐步拉低，传输至同一像素电路的正电源信号与负电源信号之间的压差在逐步变化，例如，逐步减小，这使得随着距离负电源走线和/或正电源走线的输入端越来越远，在其他影响像素电路发光亮度不变的情况下，每列像素电路的发光亮度在逐步降低，进而使得整个显示面板的亮度出现差异，影响显示品质。
有鉴于图1中所存在的缺陷，本实施例提供了一种显示面板，如图2或者图3所示，该显示面板包括M列像素电路，例如，列像素电路PL1、列像素电路PL2...以及列像素电路PLM，M列像素电路沿第一方向DR1依次排布，每列像素电路包括多个沿第二方向DR2依次排布的像素电路，例如，列像素电路PL2包括多个沿第二方向DR2依次排布的像素电路P10。其中，M为正整数，例如，M等于1时，则该显示面板仅包括列像素电路PL1；M等于2时，则该显示面板包括列像素电路PL1和列像素电路PL2；可以理解的是，M还可以为3、4或者5等其他正整数。
在其中一个实施例中，如图2或者图3所示的显示面板还可以包括M条负电源走线，例如，负电源走线VSL1、负电源走线VSL2...以及负电源走线VSLM，M条负电源走线沿第一方向DR1依次排布。其中，第N条负电源走线位于第N列像素电路在第一方向DR1上的一侧，第N条负电源走线与第N列像素电路中每个像素电路电性连接，N为小于或者等于M的正整数，例如，负电源走线VSL1位于列像素电路PL1在第一方向DR1上的左侧，负电源走线VSL1与列像素电路PL1中每个像素电路电性连接。
需要进行说明的是，在本实施例中，并不限制负电源走线VSL1位于列像素电路PL1在第一方向DR1上的左侧，可以理解的是，负电源走线VSL1位于列像素电路PL1在第一方向DR1上的右侧也可以的。
在其中一个实施例中，如图2或者图3所示的显示面板还可以包括M条正电源走线，例如，正电源走线VDL1、正电源走线VDL2...以及正电源走线VDLM，M条正电源走线沿第一方向DR1依次排布。其中，第N条正电源走线位于第N列像素电路在第一方向DR1上的另一侧，第N条正电源走线与第N列像素电路中每个像素电路电性连接，例如，正电源走线VDL1位于列像素电路PL1在第一方向DR1上的右侧，正电源走线VDL1与列像素电路PL1中每个像素电路电性连接。
需要进行说明的是，在本实施例中，并不限制正电源走线VDL1位于列像素电路PL1在第一方向DR1上的右侧，可以理解的是，正电源走线VDL1位于列像素电路PL1在第一方向DR1上的左侧也可以的，只需避免正电源走线VDL1、负电源走线VSL1位于列像素电路PL1同侧的情况即可。
在其中一个实施例中，在图2或者图3所示的显示面板中，第N条负电源走线的输入端与第N条正电源走线的输入端对侧设置。例如，负电源走线VSL1的输入端位于像素电路在第二方向DR2上的上方，具体可以是显示面板的上边框区；正电源走线VDL1的输入端位于像素电路在第二方向DR2上的下方，具体可以是显示面板的下边框区。
需要进行说明的是，负电源走线VSL1的输入端位于像素电路在第二方向DR2上的下方，具体可以是显示面板的下边框区；正电源走线VDL1的输入端位于像素电路在第二方向DR2上的上方，具体可以是显示面板的上边框区。
可以理解的是，本实施例提供的显示面板，通过在一列像素电路的两侧分别配置一条负电源走线、一条正电源走线，且负电源走线的输入端与正电源走线的输入端对侧设置，例如，图2所示的显示面板中每个列像素电路均为如此配置，而图3所示的显示面板中仅奇数列像素电路或者偶数列像素电路如此配置，可以理解的是，其均可以使得正电源走线中的电压逐渐减低，而负电源走线中的电压逐渐抬高，进而减小或者消除了传输至同一列中各像素电路的电源电压差异，能够提高显示的亮度均一性。其中，该电源电压可以为电源正信号与电源负信号之间的压差。
在其中一个实施例中，显示面板设置有沿第二方向DR2依次分布的第一区域NA1、第二区域AA1以及第三区域NA2，第N条负电源走线的输入端或者第N条正电源走线的输入端中的一个位于第一区域NA1，第N条负电源走线的输入端或者第N条正电源走线的输入端中的另一个位于第三区域NA2，M列像素电路位于第二区域AA1。
需要进行说明的是，第一区域NA1可以为显示面板的上边框区或者下边框区中的一个，第三区域NA2可以为显示面板的上边框区或者下边框区中的另一个。或者，第一区域NA1也可以为显示面板的左边框区或者右边框区中的一个，第三区域NA2也可以为显示面板的左边框区或者右边框区中的另一个。可以理解的是，如此均可以配置与同一列像素电路电性连接的负电源走线的输入端、正电源走线的输入端为对侧设置。
在其中一个实施例中，第N条负电源走线、第N列像素电路以及第N条正电源走线沿第一方向DR1依次排布，或者，第N条正电源走线、第N列像素电路以及第N条负电源走线沿第一方向DR1依次排布。
例如，负电源走线VSL1、列像素电路PL1以及正电源走线VDL1沿第一方向DR1依次排布，或者，正电源走线VDL1、列像素电路PL1以及负电源走线VSL1沿第一方向DR1依次排布。可以理解的是，如此可以确保负电源走线VSL1、正电源走线VDL1分别位于列像素电路PL1在第一方向DR1上的两侧，便于负电源走线、正电源走线延伸布线至对应的列像素电路而不会出现负电源走线、正电源走线在显示面板的厚度方向上出现交叉或者重叠。
可以理解的是，在本实施例中，第N条负电源走线的输入端、第N条正电源走线的输入端分别至同一列像素电路中任一像素电路的传输路径长度相等，可以进一步确保电源正信号、电源负信号在对应的传输路径中压差保持一致，进而有利于提升显示面板的亮度均一性。
在其中一个实施例中，第N-1条负电源走线位于第N-1列像素电路在第一方向上的一侧，第N-1条负电源走线与第N-1列像素电路中每个像素电路电性连接，且N为偶数；第N-1条正电源走线位于第N-1列像素电路在第一方向上的另一侧，第N-1条正电源走线与第N-1列像素电路中每个像素电路电性连接；其中，第N-1条负电源走线的输入端与第N-1条正电源走线的输入端同侧设置。
在其中一个实施例中，如图3所示，第N+1条负电源走线位于第N+1列像素电路在第一方向DR1上的一侧，第N+1条负电源走线与第N+1列像素电路中每个像素电路电性连接，N+1小于或者等于M且N为奇数；第N+1条正电源走线位于第N+1列像素电路在第一方向DR1上的另一侧，第N+1条正电源走线与第N+1列像素电路中每个像素电路电性连接；其中，第N+1条负电源走线的输入端与第N+1条正电源走线的输入端同侧设置。
例如，与列像素电路PLM-1电性连接的负电源走线VSLM-1的输入端位于像素电路在第二方向DR2上的上方，与列像素电路PLM电性连接的负电源走线VSLM的输入端位于像素电路在第二方向DR2上的下方；而与列像素电路PLM-1电性连接的正电源走线VDLM-1的输入端、与列像素电路PLM电性连接的正电源走线VDLM的输入端均位于像素电路在第二方向DR2上的下方。
需要进行说明的是，在本实施例中，与图1所示的显示面板相比，每隔一列像素电路调整负电源走线的输入端为与对应的正电源走线的输入端为对侧设置，可以使得传输至相邻两列像素电路的电源负信号的电位的衰减能力相反，能够降低整个显示面板中各像素电路之间电源负信号的电位差别较大而产生的电流和亮度差别，进而提高了显示面板的亮度均一性。
可以理解的是，图3所示的显示面板与图2所示的显示面板相比，仅调整了部分负电源走线的输入端的设置位置，并没有如图2所示的显示面板全部调整了负电源走线的输入端的设置位置，能够以较小的改动提高显示面板的亮度均一性。
在其中一个实施例中，如图3所示，显示面板设置有沿第二方向DR2依次分布的第一区域NA1、第二区域AA1以及第三区域NA2，第N+1条负电源走线的输入端、第N+1条正电源走线的输入端均位于第一区域NA1或者第三区域NA2；M列像素电路位于第二区域AA1。
在其中一个实施例中，如图3所示，第N+1条负电源走线、第N+1列像素电路以及第N+1条正电源走线沿第一方向DR1依次排布，或者，第N+1条正电源走线、第N+1列像素电路以及第N+1条负电源走线沿第一方向DR1依次排布。
在其中一个实施例中，第N+1条负电源走线的输入端、第N+1条正电源走线的输入端分别至第N+1列像素电路中任一像素电路的传输路径长度相等。
在其中一个实施例中，第N条负电源走线、第N列像素电路、第N条正电源走线、第N+1条负电源走线、第N+1列像素电路以及第N+1条正电源走线沿第一方向DR1依次排布。
需要进行说明的是，上述实施例中的第N条负电源走线可以但不限于为负电源走线VSL1，第N条正电源走线可以但不限于为正电源走线VDL1，对应地，第N+1条负电源走线可以为负电源走线VSL2，第N+1条正电源走线可以为正电源走线VDL2。或者，第N条负电源走线可以但不限于为负电源走线VSLM-1，第N条正电源走线可以但不限于为正电源走线VDLM-1，对应地，第N+1条负电源走线可以为负电源走线VSLM，第N+1条正电源走线可以为正电源走线VDLM。
在其中一个实施例中，图1至图3中任一像素电路P10的构造可以为如图4所示，该像素电路P10可以包括晶体管T1、驱动晶体管T2、晶体管T3、存储电容Cst以及发光器件LED，驱动晶体管T2的源极/漏极中的一个接入正电源走线传输的电源正信号VDD，驱动晶体管T2的源极/漏极中的另一个与存储电容Cst的一端、晶体管T3的源极/漏极中的一个以及发光器件LED的阳极电性连接，晶体管T3的源极/漏极中的另一个接入参考电压信号Vref，晶体管T3的栅极接入感测控制信号Vsensing，发光器件LED的阴极接入负电源走线传输的电源负信号VSS，驱动晶体管T2的栅极与存储电容Cst的另一端、晶体管T1的源极/漏极中的一个电性连接，晶体管T1的源极/漏极中的另一个接入数据信号Vdata，晶体管T1的栅极接入扫描信号VSCAN。
基于图4所示的记载可知，电源正信号VDD与电源负信号VSS之间的压差会影响流经驱动晶体管T2的电流，而该电流会进一步影响发光器件LED的发光亮度。因此，为了提高显示面板的亮度均一性，有必要依照图2和/或图3所示的技术方案去控制至各像素电路的电源正信号VDD和/或电源负信号VSS的传输路径，以减小或者消除传输至不同像素电路的电源电压差异。
在其中一个实施例中，如图4所示的像素电路P10还可以包括寄生电容Cgs、寄生电容Cgs1以及寄生电容Cgs2中的至少一个，可以理解的是，这三个寄生电容均为对应晶体管的栅极与漏极或者源极生成的寄生电容。
其中，发光器件LED可以为次毫米发光二极体、微发光二极管以及有机发光二极管中的任一种。
在其中一个实施例中，本实施例提供一种显示装置，其包括上述至少一实施例中的显示面板，M条负电源走线中的至少一条用于传输电源负信号，M条正电源走线中的至少一条用于传输电源正信号。
可以理解的是，本实施例提供的显示装置，通过在一列像素电路的两侧分别配置一条负电源走线、一条正电源走线，且负电源走线的输入端与正电源走线的输入端对侧设置，可以使得正电源走线中的电压逐渐减低，而负电源走线中的电压逐渐抬高，进而减小或者消除了传输至同一列中各像素电路的电源电压差异，能够提高显示的亮度均一性。
其中，上述显示面板可以但不限于为次毫米发光二极体构造的直显面板。
需要进行说明的是，现有技术通常通过加厚和/或加粗正电源走线、负电源走线中的至少一者来为了解决电源电压的差异问题，但该解决方法会受到制程能力和布局空间的限制，改进的复杂度、难度均较大，且改进的效果也有待进一步提升。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种显示面板，包括：
    M列像素电路，所述M列像素电路沿第一方向依次排布，每列所述像素电路包括多个沿第二方向依次排布的像素电路，M为正整数；
    M条负电源走线，所述M条负电源走线沿所述第一方向依次排布，其中，第N条负电源走线位于第N列像素电路在所述第一方向上的一侧，所述第N条负电源走线与所述第N列像素电路中每个像素电路电性连接，N为小于或者等于M的正整数；以及
    M条正电源走线，所述M条正电源走线沿所述第一方向依次排布，其中，第N条正电源走线位于所述第N列像素电路在所述第一方向上的另一侧，所述第N条正电源走线与所述第N列像素电路中每个像素电路电性连接；
    其中，所述第N条负电源走线的输入端与所述第N条正电源走线的输入端对侧设置。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板设置有沿所述第二方向依次分布的第一区域、第二区域以及第三区域，所述第N条负电源走线的输入端或者所述第N条正电源走线的输入端中的一个位于所述第一区域，所述第N条负电源走线的输入端或者所述第N条正电源走线的输入端中的另一个位于所述第三区域，所述M列像素电路位于所述第二区域。
  3. 根据权利要求2所述的显示面板，其中，所述第N条负电源走线、所述第N列像素电路以及所述第N条正电源走线沿所述第一方向依次排布，或者，所述第N条正电源走线、所述第N列像素电路以及所述第N条负电源走线沿所述第一方向依次排布。
  4. 根据权利要求3所述的显示面板，其中，所述第N条负电源走线的输入端、所述第N条正电源走线的输入端分别至所述第N列像素电路中任一像素电路的传输路径长度相等。
  5. 根据权利要求1所述的显示面板，其中，第N-1条负电源走线位于第N-1列像素电路在所述第一方向上的一侧，所述第N-1条负电源走线与所述第N-1列像素电路中每个像素电路电性连接，且N为偶数；
    第N-1条正电源走线位于所述第N-1列像素电路在所述第一方向上的另一侧，所述第N-1条正电源走线与所述第N-1列像素电路中每个像素电路电性连接；
    其中，所述第N-1条负电源走线的输入端与所述第N-1条正电源走线的输入端同侧设置。
  6. 根据权利要求1所述的显示面板，其中，第N+1条负电源走线位于第N+1列像素电路在所述第一方向上的一侧，所述第N+1条负电源走线与所述第N+1列像素电路中每个像素电路电性连接，N+1小于或者等于M且N为奇数；
    第N+1条正电源走线位于所述第N+1列像素电路在所述第一方向上的另一侧，所述第N+1条正电源走线与所述第N+1列像素电路中每个像素电路电性连接；
    其中，所述第N+1条负电源走线的输入端与所述第N+1条正电源走线的输入端同侧设置。
  7. 根据权利要求6所述的显示面板，其中，所述显示面板设置有沿所述第二方向依次分布的第一区域、第二区域以及第三区域，所述第N+1条负电源走线的输入端、所述第N+1条正电源走线的输入端均位于所述第一区域或者所述第三区域；所述M列像素电路位于所述第二区域。
  8. 根据权利要求7所述的显示面板，其中，所述第N+1条负电源走线、所述第N+1列像素电路以及所述第N+1条正电源走线沿所述第一方向依次排布，或者，所述第N+1条正电源走线、所述第N+1列像素电路以及所述第N+1条负电源走线沿所述第一方向依次排布。
  9. 根据权利要求8所述的显示面板，其中，所述第N+1条负电源走线的输入端、所述第N+1条正电源走线的输入端分别至所述第N+1列像素电路中所述任一像素电路的传输路径长度相等。
  10. 根据权利要求6所述的显示面板，其中，所述第N条负电源走线、所述第N列像素电路、所述第N条正电源走线、所述第N+1条负电源走线、所述第N+1列像素电路以及所述第N+1条正电源走线沿所述第一方向依次排布。
  11. 一种显示装置，包括如权利要求1所述的显示面板，所述M条负电源走线中的至少一条用于传输电源负信号，所述M条正电源走线中的至少一条用于传输电源正信号。
  12. 根据权利要求11所述的显示装置，其中，所述显示面板设置有沿所述第二方向依次分布的第一区域、第二区域以及第三区域，所述第N条负电源走线的输入端或者所述第N条正电源走线的输入端中的一个位于所述第一区域，所述第N条负电源走线的输入端或者所述第N条正电源走线的输入端中的另一个位于所述第三区域，所述M列像素电路位于所述第二区域。
  13. 根据权利要求12所述的显示装置，其中，所述第N条负电源走线、所述第N列像素电路以及所述第N条正电源走线沿所述第一方向依次排布，或者，所述第N条正电源走线、所述第N列像素电路以及所述第N条负电源走线沿所述第一方向依次排布。
  14. 根据权利要求13所述的显示装置，其中，所述第N条负电源走线的输入端、所述第N条正电源走线的输入端分别至所述第N列像素电路中任一像素电路的传输路径长度相等。
  15. 根据权利要求11所述的显示装置，其中，第N-1条负电源走线位于第N-1列像素电路在所述第一方向上的一侧，所述第N-1条负电源走线与所述第N-1列像素电路中每个像素电路电性连接，且N为偶数；
    第N-1条正电源走线位于所述第N-1列像素电路在所述第一方向上的另一侧，所述第N-1条正电源走线与所述第N-1列像素电路中每个像素电路电性连接；
    其中，所述第N-1条负电源走线的输入端与所述第N-1条正电源走线的输入端同侧设置。
  16. 根据权利要求11所述的显示装置，其中，第N+1条负电源走线位于第N+1列像素电路在所述第一方向上的一侧，所述第N+1条负电源走线与所述第N+1列像素电路中每个像素电路电性连接，N+1小于或者等于M且N为奇数；
    第N+1条正电源走线位于所述第N+1列像素电路在所述第一方向上的另一侧，所述第N+1条正电源走线与所述第N+1列像素电路中每个像素电路电性连接；
    其中，所述第N+1条负电源走线的输入端与所述第N+1条正电源走线的输入端同侧设置。
  17. 根据权利要求16所述的显示装置，其中，所述显示面板设置有沿所述第二方向依次分布的第一区域、第二区域以及第三区域，所述第N+1条负电源走线的输入端、所述第N+1条正电源走线的输入端均位于所述第一区域或者所述第三区域；所述M列像素电路位于所述第二区域。
  18. 根据权利要求17所述的显示装置，其中，所述第N+1条负电源走线、所述第N+1列像素电路以及所述第N+1条正电源走线沿所述第一方向依次排布，或者，所述第N+1条正电源走线、所述第N+1列像素电路以及所述第N+1条负电源走线沿所述第一方向依次排布。
  19. 根据权利要求18所述的显示装置，其中，所述第N+1条负电源走线的输入端、所述第N+1条正电源走线的输入端分别至所述第N+1列像素电路中所述任一像素电路的传输路径长度相等。
  20. 根据权利要求16所述的显示装置，其中，所述第N条负电源走线、所述第N列像素电路、所述第N条正电源走线、所述第N+1条负电源走线、所述第N+1列像素电路以及所述第N+1条正电源走线沿所述第一方向依次排布。
PCT/CN2022/079222 2022-02-24 2022-03-04 显示面板及显示装置 Ceased WO2023159669A1 (zh)

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