WO2023155514A1 - 缓冲电阻的校验方法、终端和存储介质 - Google Patents

缓冲电阻的校验方法、终端和存储介质 Download PDF

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Publication number
WO2023155514A1
WO2023155514A1 PCT/CN2022/132703 CN2022132703W WO2023155514A1 WO 2023155514 A1 WO2023155514 A1 WO 2023155514A1 CN 2022132703 W CN2022132703 W CN 2022132703W WO 2023155514 A1 WO2023155514 A1 WO 2023155514A1
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Prior art keywords
power
pulse power
voltage
buffer
resistor
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PCT/CN2022/132703
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English (en)
French (fr)
Inventor
赵密
郑锐畅
童文平
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深圳市正浩创新科技股份有限公司
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Publication of WO2023155514A1 publication Critical patent/WO2023155514A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/14—Measuring resistance by measuring current or voltage obtained from a reference source
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
    • G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current

Definitions

  • the application belongs to the field of circuit technology, and in particular relates to a buffer resistance verification method, a terminal and a storage medium.
  • the AC Alternating Current, AC
  • the mains precharges the bus capacitor through the buffer resistor, and when the bus voltage rises to a stable value, the input relay is closed again, thereby solving the instantaneous relay closing problem caused by the large voltage difference between the mains voltage and the capacitor voltage. The problem of excessive inrush current.
  • a buffer resistance verification method, terminal and storage medium are provided.
  • the first aspect of the embodiment of the present application provides a buffer resistance verification method, including:
  • the power source is a power source for precharging the bus capacitor through the buffer resistor
  • the actual pulse power is used as a calibration reference parameter for the buffer resistance.
  • An electric energy parameter acquisition unit configured to acquire electric energy parameters of a power supply, the resistance value of the buffer resistor, and the capacitance value of the bus capacitor, the power source being a power source for precharging the bus capacitor through the buffer resistor;
  • a first average voltage acquisition unit configured to acquire the initial voltage value of the bus capacitor as the first average voltage of the bus capacitor in a first unit time
  • a voltage increment acquisition unit configured to acquire the voltage increment of the bus capacitance per unit time based on the electric energy parameter, the resistance value, the capacitance value and the first average voltage
  • an average voltage acquisition unit configured to acquire the average voltage of the bus capacitor at each unit time according to the first average voltage and the voltage increment
  • a pulse power acquisition unit configured to acquire the actual pulse power of the buffer resistor at the target time according to the electric energy parameter, the resistance value and the average voltage
  • a verification unit configured to use the actual pulse power as a reference parameter for verification of the buffer resistor.
  • the third aspect of the embodiments of the present application provides a terminal, including a memory, a processor, and a computer program stored in the memory and operable on the processor, and the above method is implemented when the processor executes the computer program A step of.
  • a fourth aspect of the embodiments of the present application provides a computer-readable storage medium, where the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the foregoing method are implemented.
  • the fifth aspect of the embodiments of the present application provides a computer program product, which, when the computer program product runs on a terminal, enables the terminal to execute the steps of the method.
  • FIG. 1 is a schematic diagram of an application circuit of a snubber resistor provided by an embodiment of the present application.
  • Fig. 2 is a first waveform trend diagram of bus voltage and snubber resistor current provided by the embodiment of the present application.
  • Fig. 3 is a second waveform trend diagram of bus voltage and snubber resistor current provided by the embodiment of the present application.
  • FIG. 4 is a schematic flowchart of an implementation of a method for calibrating a buffer resistance provided in an embodiment of the present application.
  • Fig. 5 is a graph showing the variation of the bus voltage with time according to the embodiment of the present application.
  • Fig. 6 is a schematic diagram of a specific implementation process for obtaining actual pulse power provided by the embodiment of the present application.
  • FIG. 7 is a schematic diagram of a test circuit provided by a manufacturer in an embodiment of the present application for testing a snubber resistor.
  • Fig. 8 is a trend diagram of the bus capacitor voltage waveform provided by the embodiment of the present application.
  • FIG. 9 is a first schematic diagram of an actual pulse power curve and a reference pulse power curve provided by an embodiment of the present application.
  • Fig. 10 is a second schematic diagram of the actual pulse power curve and the reference pulse power curve provided by the embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a buffer resistance verification device provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a terminal provided by an embodiment of the present application.
  • the AC Alternating Current, AC
  • the mains precharges the bus capacitor through the buffer resistor.
  • the input relay is closed again, so as to solve the problem that the relay is closed instantly due to the large voltage difference between the mains voltage and the capacitor voltage. The problem of excessive inrush current.
  • the simulation experiment needs to build a circuit model, set the running time, and then output the waveform of the voltage and current, and then analyze it according to the graph.
  • the simulation experiment operation is complicated and the efficiency is low, which does not meet the cost and efficiency requirements of actual production.
  • this application proposes a calibration method for buffer resistors, which can determine the actual pulse power of the buffer resistors, and then determine the pulse power margin of the buffer resistors, assist in the selection of buffer resistors, and prevent blowouts occurrence of the phenomenon.
  • Fig. 1 shows the application circuit of the snubber resistor verified in this application.
  • the snubber resistor is used in the AC-DC conversion circuit to precharge the bus capacitor to ensure that the circuit is turned on for voltage conversion after the bus capacitor is precharged to avoid the large difference between the mains voltage and the bus capacitor voltage. the inrush current.
  • the circuit includes an input relay SWITCH, a power factor correction (Power Factor Correction, PFC) circuit, a bus capacitor C, a DC/DC (Direct current/Direct current) conversion circuit, a snubber resistor R, and a full-bridge rectifier circuit.
  • the DC/DC conversion circuit may be an LLC resonant conversion circuit.
  • the AC power input (V in ) input from the AC port needs to undergo voltage conversion to supply power to the battery in the device.
  • the power supply precharges the bus capacitor through the buffer resistor.
  • VBUS bus voltage
  • I_R snubber resistor current
  • curve a is the waveform curve of the bus voltage with time, the corresponding abscissa unit is second (s), and the ordinate unit is volts (V);
  • curve b is the waveform curve of the snubber resistor current with time, and the corresponding abscissa unit is It is second (s), and the unit of ordinate is ampere (A).
  • the bus voltage needs dozens of power cycles to reach a stable value.
  • the input relay SWITCH is closed again, so as to solve the problem of excessive inrush current at the moment when the relay SWITCH is closed due to the excessive voltage difference between the power supply voltage and the capacitor voltage.
  • the PFC circuit works, so that the bus voltage is greater than the peak value of the power supply voltage, and the rectifier bridge of the branch where the snubber resistor is located is completely cut off, and under normal circumstances no current flows through the snubber resistor.
  • the above-mentioned devices may be energy storage devices such as mobile power supplies, energy storage power stations, and battery packs; the above-mentioned devices may also be other power-consuming devices with battery modules.
  • Figure 4 shows a schematic diagram of the implementation flow of a buffer resistance calibration method provided by the embodiment of the present application. This method can be applied to the terminal and can accurately determine the actual pulse power, thereby assisting the staff to check the model of the buffer resistor selection, so as to prevent the occurrence of blown phenomenon caused by the snubber resistance selected cannot meet the actual use requirements.
  • the above-mentioned terminal may be a computer, a server, or other devices with certain computing and processing capabilities.
  • the method for verifying the above buffer resistance may include the following steps S401 to S406.
  • Step S401 acquiring the power parameter of the power supply, the resistance value of the buffer resistor and the capacitance value of the bus capacitor.
  • the above-mentioned power source may be an AC power source used in the application circuit shown in FIG. 1 , and is used for precharging the bus capacitor through a buffer resistor.
  • the AC power source can be commercial power.
  • the above buffer resistors are the buffer resistors that need to be verified at present.
  • the electric energy parameters to be acquired may include parameters such as voltage peak value and voltage frequency of the power supply.
  • the electric energy parameter is the parameter of the actual power supply to be used
  • the bus capacitor is the capacitor that needs to be precharged in the circuit shown in Figure 1
  • the buffer resistor is the currently selected resistor.
  • Step S402 acquiring an initial voltage value of the bus capacitor as a first average voltage of the bus capacitor in a first unit time.
  • the initial voltage value of the bus capacitor refers to the voltage at both ends of the bus capacitor when the circuit is turned on to precharge the bus capacitor. Usually the initial voltage on the bus capacitor is 0. In other embodiments, if the pre-charging is started before the discharge of the bus capacitor is completed, the initial voltage of the bus capacitor is not zero at this time.
  • the initial voltage value of the bus capacitor can be obtained by sampling through a sampling circuit, or can be directly set by the system as a default, or a predetermined value can be input by the user through an input device.
  • the unit time is the time corresponding to one cycle for calculating the voltage increment of the bus capacitor.
  • the first unit of time is also the first unit of time.
  • the duration of each unit time may be adjusted according to actual conditions. For example, every half of the mains power cycle can be taken as a unit time, or n times half a mains power cycle can be taken as a unit time, and n can be an integer greater than 2. In this embodiment, every half cycle of mains electricity is taken as a unit time, so as to facilitate calculation and have high measurement accuracy.
  • Step S403 based on the electric energy parameter, the resistance value, the capacitance value and the first average voltage, the voltage increment of the bus capacitance per unit time is acquired.
  • the terminal can obtain the voltage increment of the bus capacitance in each unit time, and then calculate the voltage increment for each unit time according to the voltage increment for each unit time.
  • the terminal may use a voltage increment formula for calculation.
  • the expression of the voltage increment formula is:
  • V i+1 V i + ⁇ V i ;
  • V inmax is the peak value of mains voltage
  • V i is the average voltage of the i-th unit time
  • ⁇ 2 ⁇ f
  • f is the voltage frequency
  • R is the resistance value of the buffer resistor
  • C is the capacitance value of the bus capacitor
  • ⁇ V i is the i-th The voltage increment of the bus capacitor in a unit time.
  • Step S404 according to the first average voltage and the voltage increment, the average voltage of the bus capacitor in each unit time is obtained.
  • the terminal can obtain the average voltage V i per unit time.
  • Fig. 5 shows the variation curve of the bus voltage with time.
  • the waveform line in FIG. 5 is the input voltage Vin after being rectified by the full-bridge rectifier circuit. Specifically, the obtained electric energy parameters, resistance value and capacitance value are substituted into the voltage increment formula for calculation, and the terminal can obtain the voltage increment of the bus capacitance per unit time:
  • the terminal can sequentially calculate and obtain the average voltage V i of the bus capacitor in each unit time.
  • Step S405 according to the electric energy parameter, the resistance value and the average voltage, the actual pulse power of the snubber resistor at the target time is obtained.
  • the terminal needs to compare the actual pulse power with the reference pulse power to obtain the pulse power margin of the snubber resistor.
  • the reference pulse power can be obtained from the pulse power curve provided by the manufacturer, but since the pulse power in the pulse power curve provided by the manufacturer is generally defined as the power that can be sustained for a period of time, in order to facilitate comparison with the reference value, the terminal needs Obtain the average pulse power of the buffer resistor within the target time T i as the actual pulse power at the target time. That is, the actual pulse power represents the average pulse power of the snubber resistor during a period from time 0 to the target time T i .
  • the target time T i is the time selected when comparing the actual pulse power and the reference pulse power at the same time, which can be set according to the actual situation, and the number of target times can be one or more .
  • step S405 may specifically include steps S601 to S602.
  • Step S601 calculating the instantaneous average power of the snubber resistor in each unit time according to the peak voltage, voltage frequency, resistance value and the average voltage in each unit time.
  • the terminal may use an instantaneous average power calculation formula to calculate the instantaneous average power.
  • the instantaneous average power calculation formula is:
  • ⁇ t represents the duration of each unit time.
  • the buffer resistance can be calculated in the corresponding unit time
  • the instantaneous average power of:
  • Step S602 Determine the actual pulse power of the snubber resistor at the target time according to the instantaneous average power per unit time and the pulse power formula.
  • P i represents the instantaneous average power of the buffer resistance in the i-th unit time
  • T i represents the target time, corresponding to the end time of the i-th unit time
  • P AVG_i represents the actual pulse power of the buffer resistance in the target time T i .
  • Step S406 using the actual pulse power as a reference parameter for checking the buffer resistance.
  • snubber resistors have different rated power, and the rated power is a static power. But often the actual pulse power of the snubber resistor in actual use is not equal to the rated power. Therefore, use the obtained actual pulse power to verify the currently selected snubber resistors to ensure that the pulse power margin of the selected snubber resistors can meet the requirements, thereby avoiding the occurrence of burnout.
  • FIG. 7 shows a test circuit when a manufacturer tests a snubber resistor.
  • the staff will first close the 1 and 3 of the switch K, use the DC power supply V dc and the charging resistor R charge to charge the bus capacitor C to a specific voltage value, then switch the 1 and 2 of the switch K to close, and use the bus
  • the pulse power borne by the resistance to be tested is gradually attenuated. Therefore, after a time constant ⁇ , the instantaneous power will be attenuated to e -1 times of the initial pulse power. Therefore, in order to compare with the actual pulse power provided by this application in the same dimension, the terminal also needs to correct the test results provided by the manufacturer.
  • the pulse power curve provided by the manufacturer is used as the initial pulse power curve of the buffer resistor
  • the terminal can obtain the initial pulse power curve and the correction coefficient, and then use the correction coefficient to calculate the target value in the initial pulse power curve
  • the initial pulse power corresponding to the time T i is corrected to obtain the reference pulse power corresponding to the target time T i .
  • P Limit is the reference pulse power given by the original factory.
  • the actual pulse average power curve should be multiplied by a coefficient of 0.6321 on the basis of the curve provided by the manufacturer, so as to determine the resistance that can meet the power demand as the buffer resistance according to the actual pulse average power curve obtained by simulation.
  • it is necessary to build a circuit model, set the running time, and then output the waveform of voltage and current, and calculate it according to the graph. This type selection process is more complicated.
  • the verification method in this case can accurately determine the snubber resistor that can meet the needs of the actual circuit without the need for a simulation model, which can replace the simulation, but at the same time can achieve the accuracy close to the simulation.
  • the terminal can obtain the reference pulse power of the buffer resistor when the rated power is the first power, and determine the pulse power margin of the buffer resistor according to the actual pulse power and the reference pulse power, and then use the pulse power The margin is used to check the type selection of the rated power of the snubber resistor.
  • the first power can be selected according to actual conditions, for example, it can be 2W or 3W.
  • the reference pulse power can be directly provided by the manufacturer.
  • the terminal may calculate the pulse power difference between the actual pulse power and the reference pulse power at each time, and determine the pulse power margin of the snubber resistor based on the pulse power difference.
  • the pulse power difference can be used as the pulse power margin of the snubber resistor.
  • the terminal can determine whether the pulse power margin of the snubber resistor meets the margin requirement. If the pulse power margin of the snubber resistor meets the margin requirement, the terminal may determine the snubber resistor whose rated power is the first power as the target snubber resistor.
  • the target buffer resistance is the resistance that will not cause burnout due to insufficient pulse power margin after being put into use.
  • the margin requirement can be set according to the actual situation.
  • the terminal can obtain the reference pulse power of the snubber resistor when the rated power is the second power, and return to execute to determine the pulse power margin of the snubber resistor based on the actual pulse power and the reference pulse power The step of quantity; wherein, the second power is greater than the first power. If the pulse power margin calculated based on the reference pulse power of the buffer resistor when the rated power is the second power meets the margin requirement, then the buffer resistor with the rated power of the second power can be determined as the target buffer resistor to ensure that it is put into use
  • the snubber resistor is a resistor that can avoid burning out.
  • the terminal can obtain the reference pulse power of the buffer resistor when the rated power is the third power, and return to execute according to the actual pulse power and the reference pulse power. power, a step of determining the pulse power margin of the snubber resistor; wherein, the third power is smaller than the first power. If the pulse power margin calculated based on the reference pulse power of the snubber resistor when the rated power is the third power meets the margin requirement, then the snubber resistor with the rated power of the third power can be determined as the target snubber resistor so that it can be put into use The snubber resistance will not have excess margin.
  • the selected second power and third power can be selected according to the type of snubber resistors provided by the manufacturer.
  • the selected second power may be obtained by adding a first preset value to the first power.
  • the selected third power may be obtained by reducing the second preset value on the basis of the first power. Both the first preset value and the second preset value can be adjusted according to actual conditions, and the second preset value can be the same as the first preset value or smaller than the first preset value.
  • the foregoing margin requirement may be represented by a difference interval or a difference threshold that the pulse power difference needs to be in.
  • the terminal may subtract the actual pulse power from the reference pulse power to obtain the pulse power difference between the actual pulse power and the reference pulse power as the above difference interval.
  • the above difference interval may include an upper limit value and a lower limit value, wherein the lower limit value may be set to 0.
  • the terminal can confirm that the pulse power margin meets the margin requirements, and then determine the snubber resistor whose rated power is the first power as Target snubber resistor.
  • the pulse power difference is less than the lower limit, it means that the reference pulse power is less than the actual pulse power, or although the reference pulse power is greater than the actual pulse power, but the two are too close, the snubber resistance is likely to burn out due to insufficient margin.
  • the terminal can confirm that the pulse power margin is smaller than the margin requirement.
  • the terminal can confirm that the pulse power margin is greater than margin requirements.
  • the terminal may also determine the pulse power margin according to the actual pulse power and the reference pulse power in other ways.
  • the terminal can calculate the pulse power difference by making a difference between the reference pulse power and the corresponding actual pulse power at each target time, and calculate the statistics of the pulse power difference, and use the statistics as the pulse power margin of the buffer resistor.
  • the above statistic may be the average value, extremum, least square value, etc. of the pulse power difference.
  • the terminal may also generate an actual pulse power curve according to the actual pulse power at each target time, and obtain a reference pulse power curve of the reference pulse power at each target time. Then, put the actual pulse power curve and the reference pulse power curve in the same coordinate system, and determine the pulse power margin of the snubber resistor according to the positional relationship between the actual pulse power curve and the reference pulse power curve in the same coordinate system.
  • the positional relationship can represent the pulse power difference between the actual pulse power and the reference pulse power of the snubber resistor when the rated power is the first power, therefore, the terminal can be located under the reference pulse power curve when the actual pulse power curve is below the reference pulse power curve, and the two When the distance between the curves or the area enclosed by the two curves is less than or equal to the preset threshold, it is confirmed that the pulse power margin meets the margin requirement.
  • the terminal can also provide a visual interface for staff to assist in making judgments.
  • the terminal obtains the voltage increment of the bus capacitor in each unit time by obtaining the power parameter of the power supply, the resistance value of the buffer resistor, the capacitance value of the bus capacitor, and the initial voltage value, and obtains each The average voltage per unit time, and then obtain the actual pulse power compared with the reference pulse power, so that the actual pulse power can be used as the calibration reference parameter of the buffer resistor to determine the buffer resistor that can meet the actual pulse power requirements of the buffer resistor and prevent burnout.
  • the occurrence of disconnection phenomenon improves the safety of electricity use.
  • the process can be directly realized by the terminal operation, without the need for experimental simulation, which improves the efficiency and universality of the verification method.
  • the actual pulse power curve and the reference pulse power curve are shown in Figure 10. It can be seen that the actual pulse power curve is always below the reference pulse power curve, and the pulse power margin meets the margin requirements. That is to say, if the resistor selection is qualified, correspondingly, a chip resistor with a rated power of 3W can be selected as the target buffer resistor for use.
  • the temperature of the resistance shell is used as a judgment reference, the timing contactor is used to repeatedly switch the mains voltage, and the instantaneous maximum temperature of the buffer resistance is tested during the slow-start action.
  • the contactor can be set to close for 5 seconds and then open for 30 seconds.
  • test data is shown in the table below:
  • a snubber resistor with a rated power of 2W has a maximum temperature of over 200°C at the moment the mains power is turned on, and there is a certain risk of damage; while a snubber resistor with a rated power of 3W has a maximum temperature of about 150°C at the moment the mains power is turned on, there is no risk of damage. risk of damage.
  • the test results are consistent with the results given by the method provided in this application, therefore, the verification method provided by this application has high reliability.
  • the terminal can continuously calibrate resistors with different rated powers to help the staff to select the type of buffer resistor.
  • the staff only needs to select the resistor with the same model as the target buffer resistor and put it into use. Can.
  • the verification efficiency is improved, and since the support of the simulation device is not required, the verification method provided by this application is used to assist in the selection of buffer resistors, which can be adapted in different application environments.
  • FIG. 11 is a schematic structural diagram of a buffer resistance verification device 1100 provided in an embodiment of the present application, and the buffer resistance verification device 1100 is configured on a terminal.
  • the verification device 1100 of the buffer resistance may include:
  • An electric energy parameter acquisition unit 1101 configured to acquire electric energy parameters of a power supply, the resistance value of the buffer resistor, and the capacitance value of the bus capacitor, where the power source is used to precharge the bus capacitor through the buffer resistor;
  • a first average voltage acquisition unit 1102 configured to acquire the initial voltage value of the bus capacitance as the first average voltage of the bus capacitance in a first unit time
  • a voltage increment acquisition unit 1103, configured to acquire the voltage increment of the bus capacitance per unit time based on the electric energy parameter, the resistance value, the capacitance value and the first average voltage;
  • a pulse power acquisition unit 1105 configured to acquire the actual pulse power of the buffer resistor at the target time according to the electric energy parameter, the resistance value and the average voltage;
  • the verification unit 1106 uses the actual pulse power as a reference parameter for verification of the buffer resistor.
  • each unit in the verification device is used to perform corresponding steps in the method for verifying the above-mentioned buffer resistance, and its specific implementation process will not be described in detail here.
  • the specific working process of the above buffer resistor calibration device 1100 can refer to the corresponding process of the method described in FIG. 1 to FIG. 10 , which will not be repeated here.
  • FIG. 12 it is a schematic diagram of a terminal provided in the embodiment of the present application.
  • the terminal 12 may include: a processor 120 , a memory 121 , and a computer program 122 stored in the memory 121 and operable on the processor 120 , such as a buffer resistance verification program.
  • the processor 120 executes the computer program 122 , the steps in the above embodiment of the verification method for each buffer resistance are implemented, such as steps S401 to S406 shown in FIG. 4 .
  • the processor 120 executes the computer program 122, it realizes the functions of the modules/units in the above-mentioned device embodiments, for example, the power parameter acquisition unit 1101, the first average voltage acquisition unit 1102, the voltage booster shown in FIG.
  • a quantity acquisition unit 1103 an average voltage acquisition unit 1104 , a pulse power acquisition unit 1105 and a checking unit 1106 .
  • the computer program may be divided into one or more modules/units, and the one or more modules/units are stored in the memory 121 and executed by the processor 120 to complete the present application.
  • the one or more modules/units may be a series of computer program instruction segments capable of accomplishing specific functions, and the instruction segments are used to describe the execution process of the computer program in the terminal.
  • the computer program can be divided into: an electric energy parameter acquisition unit, a first average voltage acquisition unit, a voltage increment acquisition unit, an average voltage acquisition unit, a pulse power acquisition unit and a verification unit.
  • the terminal may include, but not limited to, a processor 120 and a memory 121 .
  • FIG. 12 is only an example of a terminal, and does not constitute a limitation on the terminal. It may include more or less components than those shown in the figure, or combine certain components, or different components, such as the Terminals may also include input and output devices, network access devices, buses, and so on.
  • the so-called processor 120 can be a central processing unit (Central Processing Unit, CPU), and can also be other general-purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), Off-the-shelf programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • a general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like.
  • the storage 121 may be an internal storage unit of the terminal, such as a hard disk or memory of the terminal.
  • the memory 121 can also be an external storage device of the terminal, such as a plug-in hard disk equipped on the terminal, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash memory card (Flash Card) etc.
  • the memory 121 may also include both an internal storage unit of the terminal and an external storage device.
  • the memory 121 is used to store the computer program and other programs and data required by the terminal.
  • the memory 121 can also be used to temporarily store data that has been output or will be output.
  • the disclosed device/terminal and method may be implemented in other ways.
  • the device/terminal embodiments described above are only illustrative.
  • the division of the modules or units is only a logical function division.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.
  • the integrated module/unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments in the present application can also be completed by instructing related hardware through computer programs.
  • the computer programs can be stored in a computer-readable storage medium, and the computer When the program is executed by the processor, the steps in the above-mentioned various method embodiments can be realized.
  • the computer program includes computer program code, and the computer program code may be in the form of source code, object code, executable file or some intermediate form.
  • the computer-readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a removable hard disk, a magnetic disk, an optical disk, a computer memory, and a read-only memory (Read-Only Memory, ROM) , random access memory (Random Access Memory, RAM), electric carrier signal, telecommunication signal and software distribution medium, etc.
  • ROM Read-Only Memory
  • RAM Random Access Memory
  • electric carrier signal telecommunication signal and software distribution medium, etc.

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  • Engineering & Computer Science (AREA)
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Abstract

一种缓冲电阻的校验方法、装置、终端和存储介质，涉及电路技术领域，该缓冲电阻的校验方法具体包括：获取电源的电能参数、缓冲电阻的阻值，母线电容的电容值（S401）以及初始电压值，然后获取每个单位时间内母线电容的电压增量（S403），并获取得到每个单位时间的平均电压（S404），进而获取与参考脉冲功率进行比较的实际脉冲功率，以将实际脉冲功率作为缓冲电阻的校验参考参数（S406）。该方法可以确定出能够满足缓冲电阻实际脉冲功率需求的缓冲电阻，防止烧断现象的发生，提高用电安全性。

Description

缓冲电阻的校验方法、终端和存储介质
相关申请的交叉引用
本申请要求于2022年02月15日提交中国专利局、申请号为202210137950.3、发明名称为“缓冲电阻的校验方法、装置、终端和存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请属于电路技术领域，尤其涉及一种缓冲电阻的校验方法、终端和存储介质。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成示例性技术。
在设备的输入端口上电时，交流端口输入的交流电(Alternating Current，AC)需要经过电压变换后给设备中的电池供电。AC上电时，市电通过缓冲电阻给母线电容预充电，当母线电压上升至稳定值附近时，再闭合输入继电器，从而解决因市电电压与电容电压压差过大导致的继电器闭合瞬间的冲击电流过大的问题。
实际应用中发现，AC上电时常出现缓冲电阻烧断现象，失效比例约为0.1％，因此，需要一种校验方法，能够准确地校验缓冲电阻是否可用，辅助进行电阻选型，防止烧断现象的发生。
发明内容
根据本申请的各种实施例，提供一种缓冲电阻的校验方法、终端和存储介质。
本申请实施例第一方面提供一种缓冲电阻的校验方法，包括：
获取电源的电能参数、所述缓冲电阻的阻值和母线电容的电容值；所述电源为用于通过所述缓冲电阻向所述母线电容进行预充电的电源；
获取所述母线电容的初始电压值作为所述母线电容在第一单位时间的第一平均电压；
基于所述电能参数、所述阻值、所述电容值以及所述第一平均电压，获取每个单位时间内所述母线电容的电压增量；
根据所述第一平均电压和所述电压增量，获取所述母线电容在每个所述单位时间的平均电压；
根据所述电能参数、所述阻值以及所述平均电压，获取所述缓冲电阻在目标时间的实际脉冲功率；
将所述实际脉冲功率作为所述缓冲电阻的校验参考参数。
本申请实施例第二方面提供的一种缓冲电阻的校验装置，包括：
电能参数获取单元，用于获取电源的电能参数、所述缓冲电阻的阻值和母线电容的电容值，所述电源为用于通过所述缓冲电阻向所述母线电容进行预充电的电源；
第一平均电压获取单元，用于获取所述母线电容的初始电压值作为所述母线电容在第一单位时间的第一平均电压；
电压增量获取单元，用于基于所述电能参数、所述阻值、所述电容值以及所述第一平均电压，获取每个单位时间内所述母线电容的电压增量；
平均电压获取单元，用于根据所述第一平均电压和所述电压增量，获取所述母线电容在每个所述单位时间的平均电压；
脉冲功率获取单元，用于根据所述电能参数、所述阻值以及所述平均电压，获取所述缓冲电阻在目标时间的实际脉冲功率；
校验单元，用于将所述实际脉冲功率作为所述缓冲电阻的校验参考参数。
本申请实施例第三方面提供一种终端，包括存储器、处理器以及存储在所述存储器中并可在所述处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现上述方法的步骤。
本申请实施例第四方面提供一种计算机可读存储介质，所述计算机可读存储介质存储有计算机程序，所述计算机程序被处理器执行时实现上述方法的步骤。
本申请实施例第五方面提供了一种计算机程序产品，当计算机程序产品在终端上运行时，使得终端执行时实现方法的步骤。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的缓冲电阻的应用电路示意图。
图2是本申请实施例提供的母线电压、缓冲电阻电流的第一波形趋势图。
图3是本申请实施例提供的母线电压、缓冲电阻电流的第二波形趋势图。
图4是本申请实施例提供的一种缓冲电阻的校验方法的实现流程示意图。
图5是本申请实施例提供的母线电压随时间的变化曲线图。
图6是本申请实施例提供的获取实际脉冲功率的具体实现流程示意图。
图7是本申请实施例提供的厂家对缓冲电阻进行测试的测试电路示意图。
图8是本申请实施例提供的母线电容电压波形趋势图。
图9是本申请实施例提供的实际脉冲功率曲线与参考脉冲功率曲线的第一示意图。
图10是本申请实施例提供的实际脉冲功率曲线与参考脉冲功率曲线的第二示意图。
图11是本申请实施例提供的一种缓冲电阻的校验装置的结构示意图。
图12是本申请实施例提供的终端的结构示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。基于本申请的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本申请保护。
在设备的输入端口上电时，交流端口输入的交流电(Alternating Current，AC)需要经过电压变换后给设备中的电池供电。AC上电时，市电通过缓冲电阻给母线电容预充电，当母线电压上升至稳定值附近时，再闭合输入继电器，从而解决因市电电压与电容电压的压差过大，导致继电器闭合瞬间的冲击电流过大的问题。
针对在AC上电时常出现缓冲电阻烧断现象的问题，研究发现，其初步原因定位在缓冲电阻的脉冲功率裕量不足，不能满足使用需求。具体的，在对电阻进行选型时，工作人员往往只是根据厂家提供的脉冲功率曲线来确定使用哪一型号的缓冲电阻，并不会分析所选用的缓冲电阻是否合理。因此，一旦使用的缓冲电阻选用不合理，其实际脉冲功率与厂家所提供的脉冲功率曲线不匹配，使得采用该缓冲电阻后，很容易出现缓冲电阻被烧断的问题。
在另一方面，即便需要分析选用的缓冲电阻是否合理，通常也是通过仿真实验来实现。仿真实验需要搭建电路模型，设定运行的时间，然后输出电压电 流的波形，再根据图形进行分析。仿真实验操作复杂，效率较低，并不符合实际生产的成本以及效率需求。
为了解决上述问题，本申请提出了一种缓冲电阻的校验方法，能够确定出缓冲电阻的实际脉冲功率，进而确定缓冲电阻的脉冲功率裕量，辅助进行缓冲电阻的选型，能够防止烧断现象的发生。
图1示出了本申请所校验的缓冲电阻的应用电路。该缓冲电阻应用于AC-DC的变换电路中，以对母线电容进行预充电，确保母线电容完成预充电后才开启电路进行电压变换，避免市电电压和母线电容的电压相差较大时所产生的冲击电流。电路中包括输入继电器SWITCH、功率因数校正(Power Factor Correction，PFC)电路、母线电容C以及DC/DC(Direct current/Direct current)变换电路、缓冲电阻R以及全桥整流电路。其中，DC/DC变换电路可以为LLC谐振变换电路。
在上述应用电路中，交流端口输入的AC电源输入(V in)需要经过电压变换后给设备中的电池供电。AC电源上电时，电源通过缓冲电阻给母线电容预充电。请参看图2和图3所示出的母线电压(VBUS)、缓冲电阻电流(I_R)的波形趋势图，图3为图2中时间在0.2S以内的局部放大图。其中，曲线a为母线电压随时间的波形曲线，对应的横坐标单位为秒(s)，纵坐标单位为伏特(V)；曲线b为缓冲电阻电流随时间的波形曲线，对应的横坐标单位为秒(s)，纵坐标单位为安培(A)。在母线电容的电容值较大的工况下，母线电压需要几十个电源周期才能达到稳定值。
当母线电压上升至预设的预充电电压时，再闭合输入继电器SWITCH，从而解决因电源电压与电容电压的压差过大导致的在继电器SWITCH闭合瞬间出现冲击电流过大的问题。继电器SWITCH闭合后，PFC电路工作，使得母线电压大于电源电压峰值，缓冲电阻所在支路的整流桥完全截止，则正常情况下缓冲电阻不再有电流流过。
其中，上述设备可以是移动电源、储能电站、电池包等储能设备；上述设备也可以为其他带有电池模块的用电设备。
为了说明本申请的技术方案，下面通过具体实施例来进行说明。
图4示出了本申请实施例提供的一种缓冲电阻的校验方法的实现流程示意图，该方法可以应用于终端上，能准确地确定出实际脉冲功率，从而辅助工作人员对缓冲电阻的型号进行选取，进而防止由于选用的缓冲电阻无法满足实际使用需求所引起的烧断现象的发生。
上述终端可以是计算机、服务器或其他具有一定运算处理能力的设备。
具体的，上述缓冲电阻的校验方法可以包括以下步骤S401至步骤S406。
步骤S401，获取电源的电能参数、缓冲电阻的阻值和母线电容的电容值。
在本申请的实施方式中，上述电源可以是图1所示应用电路中所使用的AC电源，用于通过缓冲电阻向母线电容进行预充电。比如，该AC电源可以为市电。上述缓冲电阻为当前需要进行校验的缓冲电阻。
其中，所需获取的电能参数可以包括电源的电压峰值和电压频率等参数。电能参数为实际需要使用的电源的参数，母线电容则为图1所示电路中的需要进行预充电的电容，缓冲电阻则为当前选用的电阻。
步骤S402，获取母线电容的初始电压值作为母线电容在第一单位时间的第一平均电压。
其中，母线电容的初始电压值是指在开启电路对母线电容进行预充电时，母线电容两端的电压。通常母线电容上的初始电压为0。在其他的实施例中，如果在母线电容还未放电结束时开启预充电，则此时母线电容的初始电压不为0。该母线电容的初始电压值可以通过采样电路进行采样获取，也可以直接由系统进行默认设置，或者由用户通过输入设备输入一个既定值。
单位时间为对母线电容的电压增量进行计算的一个周期所对应的时间。第一单位时间也即第一个单位时间。在本申请的实施方式中，每个单位时间的时长可以根据实际情况进行调整。比如，可以将每半个市电周期作为一个单位时间，也可以将n倍的半个市电周期作为一个单位时间，n可以为大于2的整数。在本实施例中，以每半个市电周期为一个单位时间，从而方便进行计算且具有较高的测量精度。
步骤S403，基于电能参数、阻值、电容值以及第一平均电压，获取每个单位时间内母线电容的电压增量。
在本申请的实施方式中，终端基于初始电压值、电能参数、阻值和电容值，可以获取母线电容在各个单位时间内的电压增量，进而根据各单位时间的电压增量计算用于与参考脉冲功率进行比较的实际脉冲功率。
具体的，上述终端在基于电能参数、阻值、电容值以及第一平均电压，获取每个单位时间内母线电容的电压增量时，可以采用电压增量公式进行计算。
在本申请的一些实施方式中，电压增量公式的表达式为：
Figure PCTCN2022132703-appb-000001
V i+1＝V i+ΔV i；
其中，
Figure PCTCN2022132703-appb-000002
且θ 2＝π-θ 1。V inmax为市电电压峰值，V i为第i个单位时间的平均电压，ω＝2πf，f为电压频率，R表示缓冲电阻的阻值，C表示母线电容的电容值，ΔV i表示第i个单位时间内母线电容的电压增 量。
并且，每个单位时间的时长为Δt，也即第i+1个单位时间t i+1＝t i+Δt。
步骤S404，根据第一平均电压和电压增量，获取母线电容在每个单位时间的平均电压。
在本申请的实施方式中，基于第一个单位时间对应的第一平均电压及获取到的第一个单位时间内母线电容的电压增量，可以计算得到第二个单位时间的第二平均电压V 2＝V 1+ΔV 1，以此类推，基于第i个单位时间的平均电压和第i个单位时间内母线电容的电压增量，可以计算得到第i+1个单位时间的平均电压V i+1＝V i+ΔV i。最终，终端可以获取到每个单位时间的平均电压V i。
以半个市电周期为一个单位时间为例，此时相邻单位时间之间的间隔
Figure PCTCN2022132703-appb-000003
Figure PCTCN2022132703-appb-000004
f为市电电压频率。图5示出了在母线电压随时间的变化曲线。图5中的波形线为经过全桥整流电路进行整流处理后的输入电压Vin。具体的，将获取的电能参数、阻值和电容值代入电压增量公式进行计算，终端可以得到每个单位时间内母线电容的电压增量：
Figure PCTCN2022132703-appb-000005
因此，根据第一平均电压V 1和计算得到的电压增量ΔV i，终端可以依次计算得到母线电容在每个单位时间的平均电压V i。
步骤S405，根据电能参数、阻值以及平均电压，获取缓冲电阻在目标时间的实际脉冲功率。
在本申请的实施方式中，终端需将实际脉冲功率与参考脉冲功率进行比较，才能够得到缓冲电阻的脉冲功率裕量。而参考脉冲功率可以通过厂家提供的脉冲功率曲线获得，但由于厂家提供的脉冲功率曲线中的脉冲功率一般定义为一段时间内可持续承受的功率，因此，为了方便与参考值进行比较，终端需要获取缓冲电阻在目标时间T i内的平均脉冲功率作为目标时间的实际脉冲功率。也即，实际脉冲功率表征了缓冲电阻从时刻0到目标时间T i这一段时间内的脉冲平均功率。
在本申请的实施方式中，目标时间T i为将同一时间的实际脉冲功率和参考脉冲功率进行比对时所选用的时间，可以根据实际情况进行设置，目标时间的数量可以为一个或多个。
具体的，如图6所示，上述步骤S405可以具体包括步骤S601至步骤S602。
步骤S601，根据电压峰值、电压频率、阻值以及各单位时间的平均电压， 计算缓冲电阻在每个单位时间内的瞬时平均功率。
具体的，终端可以采用瞬时平均功率计算公式进行计算瞬时平均功率。
在本申请的一些实施方式中，瞬时平均功率计算公式为：
Figure PCTCN2022132703-appb-000006
其中，Δt表示每个单位时间的时长。
以半个市电周期为一个单位时间为例继续进行说明，将电压峰值、电压频率、阻值以及对应单位时间的平均电压代入至瞬时平均功率计算公式，可以计算得到缓冲电阻在对应单位时间内的瞬时平均功率：
Figure PCTCN2022132703-appb-000007
步骤S602，根据每个单位时间内的瞬时平均功率和脉冲功率公式，确定缓冲电阻在目标时间的实际脉冲功率。
其中，上述脉冲功率公式可以表示为：
Figure PCTCN2022132703-appb-000008
P i表示缓冲电阻在第i个单位时间内的瞬时平均功率，T i表示目标时间，对应于第i个单位时间的结束时间，P AVG_i表示缓冲电阻在目标时间T i的实际脉冲功率。
步骤S406，将实际脉冲功率作为缓冲电阻的校验参考参数。
其中，不同型号的缓冲电阻具有不同的额定功率，这个额定功率是一个静态的功率。但是往往缓冲电阻在实际使用过程的实际脉冲功率并不会等于这额定功率。因此，利用获取到的实际脉冲功率，来对当前选用的缓冲电阻进行校验，确保选用的缓冲电阻的脉冲功率裕量能够满足需求，进而避免烧断现象的发生。
具体地，不同型号的电阻，在电阻值相同的情况下，也会存在额定功率上的差异。在传统的选型过程中，通常是直接根据这个额定功率来进行确定。但是在具体的电路工作中，在各个时间电的脉冲功率与额定值之间是会存在差异的。本案中将获取到的实际脉冲功率与厂家所提供的参考脉冲功率进行比对， 从而能够确定该缓冲电阻是否满足使用需求，是否需要选用额定功率更大的电阻等，从而避免由于缓冲电阻选用导致的烧断现象的发生。
传统的选型过程中，也可以通过仿真来进行测试。具体的，图7示出了厂家对缓冲电阻进行测试时的测试电路。测试过程中，工作人员会先将开关K的1和3闭合，利用直流电源V dc以及充电电阻R charge给母线电容C充电到特定的电压值，然后切换开关K的1和2闭合，使用母线电容C对额定功率为第一功率的待测试电阻(R Test)进行放电测试。然后定义待测电阻所能承受的最大初始峰值功率与时间常数τ＝RC之间的关系曲线为脉冲功率曲线。
而在脉冲功率的测试过程中，待测试电阻所承受的脉冲功率是逐渐衰减的，因此，经过1个时间常数τ后，瞬时功率将衰减为初始脉冲功率的e -1倍。因此，为了和本申请所提供的实际脉冲功率在同一维度上进行比对，终端还需要对厂家提供的测试结果进行修正。
在本申请的一些实施方式中，将厂家提供的脉冲功率曲线作为缓冲电阻的初始脉冲功率曲线，终端可以获取初始脉冲功率曲线，并获取修正系数，然后利用修正系数，对初始脉冲功率曲线中目标时间T i对应的初始脉冲功率进行修正，得到目标时间T i对应的参考脉冲功率。
具体的，时刻0到时刻τ之间的平均脉冲功率：
Figure PCTCN2022132703-appb-000009
P Limit是原厂给的参考脉冲功率。
因此，实际的脉冲平均功率曲线，应在厂家提供的曲线的基础上，乘以系数0.6321，从而根据仿真得到的实际脉冲平均功率曲线去确定能够满足该功率需求的电阻作为缓冲电阻。通过仿真来实现，需要搭建电路模型，设定运行的时间，然后输出电压电流的波形，根据图形来算。这种选型方式流程较为复杂。相比而言，本案中的校验方法不需要仿真模型就可以准确的确定出来能够满足实际电路需要的缓冲电阻，能够代替仿真，但同时能达到仿真接近的精度。
在本申请的一些实施方式中，终端可以获取缓冲电阻在额定功率为第一功率时的参考脉冲功率，并根据实际脉冲功率和参考脉冲功率，确定缓冲电阻的脉冲功率裕量，然后利用脉冲功率裕量进行缓冲电阻的额定功率的选型校验。
其中，第一功率可以根据实际情况进行选择，例如可以是2W或3W。
参考脉冲功率可以由厂家直接提供。
在本申请的一些实施方式中，终端可以计算各个时间下实际脉冲功率和参考脉冲功率之间的脉冲功率差，并基于脉冲功率差确定缓冲电阻的脉冲功率裕量。例如，可以将脉冲功率差作为缓冲电阻的脉冲功率裕量。
此时，终端可以判断缓冲电阻的脉冲功率裕量是否满足裕量要求。若缓冲 电阻的脉冲功率裕量满足裕量要求，终端可以将额定功率为第一功率的缓冲电阻确定为目标缓冲电阻。目标缓冲电阻即为投入使用后不会因脉冲功率裕量不足导致烧断现象问题发生的电阻。
其中，裕量要求可以根据实际情况进行设置。
若缓冲电阻的脉冲功率裕量小于裕量要求，终端可以获取缓冲电阻在额定功率为第二功率时的参考脉冲功率，并返回执行根据实际脉冲功率和参考脉冲功率，确定缓冲电阻的脉冲功率裕量的步骤；其中，第二功率大于第一功率。如果基于缓冲电阻在额定功率为第二功率时的参考脉冲功率计算得到的脉冲功率裕量满足裕量要求，则可以将额定功率为第二功率的缓冲电阻确定为目标缓冲电阻，以保障投入使用的缓冲电阻为能够避免烧断现象发生的电阻。
在本申请的一些实施方式中，若缓冲电阻的脉冲功率裕量大于裕量要求，终端可以获取缓冲电阻在额定功率为第三功率时的参考脉冲功率，并返回执行根据实际脉冲功率和参考脉冲功率，确定缓冲电阻的脉冲功率裕量的步骤；其中，第三功率小于第一功率。如果基于缓冲电阻在额定功率为第三功率时的参考脉冲功率计算得到的脉冲功率裕量满足裕量要求，则可以将额定功率为第三功率的缓冲电阻确定为目标缓冲电阻，以使投入使用的缓冲电阻不会裕量过剩。
如果脉冲功率裕量仍不满足裕量要求，则可以继续选择其他额定功率的缓冲电阻计算脉冲功率裕量，直至确定出脉冲功率裕量满足裕量要求的缓冲电阻作为目标缓冲电阻。
需要说明的是，所选择的第二功率和第三功率可以根据厂家所能提供的缓冲电阻型号进行选择。一些实施方式中，所选择的第二功率可以是在第一功率的基础上增加第一预设值得到的。同样的，所选择的第三功率可以是在第一功率的基础上减少第二预设值得到的。第一预设值和第二预设值均可以根据实际情况进行调整，第二预设值既可以与第一预设值相同，也可以小于第一预设值。
具体的，在本申请的一些实施方式中，上述裕量要求可以以脉冲功率差需要处于的差值区间或差值阈值表示。
例如，在一些实施方式中，终端可以将参考脉冲功率减去实际脉冲功率，得到实际脉冲功率和参考脉冲功率之间的脉冲功率差作为上述差值区间。相应的，上述差值区间可以包含上限值与下限值，其中，下限值可以设置为0。
当脉冲功率差大于或等于下限值，且小于或等于上限值时，则说明参考脉冲功率大于实际脉冲功率，且两者之间的差值不会过大，相应的，缓冲电阻不会因裕量不足而发生烧断现象，同时也不会因裕量过剩而造成材料的浪费，则终端可以确认脉冲功率裕量满足裕量要求，进而将额定功率为第一功率的缓冲电阻确定为目标缓冲电阻。
当脉冲功率差小于下限值，则说明参考脉冲功率小于实际脉冲功率，或者虽然参考脉冲功率大于实际脉冲功率，但两者过于接近，缓冲电阻容易因裕量不足而发生烧断现象，此时终端可以确认脉冲功率裕量小于裕量要求。
当脉冲功率差大于上限值，则说明参考脉冲功率远大于实际脉冲功率，裕量过剩，将该缓冲电阻投入使用易造成材料的浪费和成本的提高，此时终端可以确认脉冲功率裕量大于裕量要求。
需要说明的是，在本申请的实施方式中，终端还可以通过其他的方式，根据实际脉冲功率与参考脉冲功率确定脉冲功率裕量。
在一些实施方式中，终端可以将各个目标时间的参考脉冲功率和对应的实际脉冲功率作差计算脉冲功率差，并计算脉冲功率差的统计量，将统计量作为缓冲电阻的脉冲功率裕量。
例如，上述统计量可以为脉冲功率差的平均值、极值、最小二乘法值等。
另一些实施方式中，终端还可以根据各目标时间的实际脉冲功率生成实际脉冲功率曲线，并获取各目标时间的参考脉冲功率的参考脉冲功率曲线。然后，将实际脉冲功率曲线与参考脉冲功率曲线置于同一坐标系中，并根据实际脉冲功率曲线和参考脉冲功率曲线在同一坐标系中的位置关系，确定缓冲电阻的脉冲功率裕量。
其中，位置关系可以表征实际脉冲功率和缓冲电阻在额定功率为第一功率时的参考脉冲功率之间的脉冲功率差，因此，终端可以在实际脉冲功率曲线位于参考脉冲功率曲线下方，且两个曲线之间的距离或两个曲线之间所围成的面积小于或等于预设阈值时，确认脉冲功率裕量满足裕量要求。
如果实际脉冲功率曲线位于参考脉冲功率曲线上方，则可以确认脉冲功率裕量小于裕量要求。
如果实际脉冲功率曲线位于参考脉冲功率曲线下方，且两个曲线之间的距离或两个曲线之间所围成的面积大于预设阈值，则可以确认脉冲功率裕量大于裕量要求。
通过生成曲线的方式，终端还可以提供可视化的界面，供工作人员辅助进行判断。
本申请的实施方式中，终端通过获取电源的电能参数、缓冲电阻的阻值，母线电容的电容值以及初始电压值，然后获取每个单位时间内母线电容的电压增量，并获取到每个单位时间的平均电压，进而获取与参考脉冲功率进行比较的实际脉冲功率，以将实际脉冲功率作为缓冲电阻的校验参考参数，以确定出能够满足缓冲电阻实际脉冲功率需求的缓冲电阻，防止烧断现象的发生，提高了用电安全性。
同时，该过程可以直接由终端运算实现，不需要进行实验仿真，提高了校验方法的效率与普适性。
为了说明本申请所提供的校验方法的可靠性，假设缓冲电阻R＝2×200Ω(即2个电阻串联)，母线电容C＝470uF×2+22uF×2，电源为市电电压有效值265V，结合本申请所提供方法，可以得到如图8所示的母线电容电压波形。
使用额定功率为2W的贴片(Surface Mount Technology，SMD)电阻，实际脉冲功率曲线与参考脉冲功率曲线如图9所示。可以看出，实际脉冲功率曲线超过参考脉冲功率曲线，脉冲功率裕量不满足裕量要求，即缓冲电阻的选型不合格。
使用额定功率为3W的贴片电阻，实际脉冲功率曲线与参考脉冲功率曲线如图10所示，可以看出，实际脉冲功率曲线始终处于参考脉冲功率曲线下方，脉冲功率裕量满足裕量要求，即电阻选型合格，相应的，可以选择额定功率为3W的贴片电阻作为目标缓冲电阻进行使用。
由于实际电阻芯温难以测量，将电阻外壳温度作为判断参考，使用定时接触器反复投切市电电压，并测试在缓起动作时，缓冲电阻的瞬时最大温度。其中，接触器可以设置为闭合5秒，再断开30秒。
经测试，测试数据如下表所示：
电阻规格 瞬时最高温度
2W SMD 200℃
3W SMD 150℃
额定功率为2W的缓冲电阻在市电上电瞬间，最高温度超过200℃，存在一定的损坏风险；而额定功率为3W的缓冲电阻在市电上电瞬间，最高温度在150℃左右，不存在损害风险。测试结果与本申请所提供的方法给出的结果一致，因此，本申请提供的校验方法可靠性较高。
结合本申请提供的校验方式，终端可以不断地对额定功率不同的电阻进行校验，帮助工作人员进行缓冲电阻的选型，最终工作人员只需选择与目标缓冲电阻型号相同的电阻投入使用即可。相较于对每个型号的缓冲电阻分别进行仿真测试，校验效率得到了提高，并且，由于不需要仿真设备的支持，结合本申请提供的校验方法辅助进行缓冲电阻选型，可以适配于不同的应用环境中。
需要说明的是，对于前述的各方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本申请并不受所描述的动作顺序的限制，因为根据本申请，某些步骤可以采用其它顺序进行。
如图11所示为本申请实施例提供的一种缓冲电阻的校验装置1100的结构示意图，所述缓冲电阻的校验装置1100配置于终端上。
具体的，所述缓冲电阻的校验装置1100可以包括：
电能参数获取单元1101，用于获取电源的电能参数、所述缓冲电阻的阻值和母线电容的电容值，所述电源为用于通过所述缓冲电阻向所述母线电容进行预充电的电源；
第一平均电压获取单元1102，用于获取所述母线电容的初始电压值作为所述母线电容在第一单位时间的第一平均电压；
电压增量获取单元1103，用于基于所述电能参数、所述阻值、所述电容值以及所述第一平均电压，获取每个单位时间内所述母线电容的电压增量；
平均电压获取单元1104，用于根据所述第一平均电压和所述电压增量，获取所述母线电容在每个所述单位时间的平均电压；
脉冲功率获取单元1105，用于根据所述电能参数、所述阻值以及所述平均电压，获取所述缓冲电阻在目标时间的实际脉冲功率；
校验单元1106，将所述实际脉冲功率作为所述缓冲电阻的校验参考参数。
本实施例中，校验装置中各单元用于对应执行与上述缓冲电阻的校验方法中的各个步骤，其具体实施过程在此不做详述。
需要说明的是，为描述的方便和简洁，上述缓冲电阻的校验装置1100的具体工作过程，可以参考图1至图10所述方法的对应过程，在此不再赘述。
如图12所示，为本申请实施例提供的一种终端的示意图。该终端12可以包括：处理器120、存储器121以及存储在所述存储器121中并可在所述处理器120上运行的计算机程序122，例如缓冲电阻的校验程序。所述处理器120执行所述计算机程序122时实现上述各个缓冲电阻的校验方法实施例中的步骤，例如图4所示的步骤S401至S406。或者，所述处理器120执行所述计算机程序122时实现上述各装置实施例中各模块/单元的功能，例如图11所示的电能参数获取单元1101、第一平均电压获取单元1102、电压增量获取单元1103、平均电压获取单元1104、脉冲功率获取单元1105和校验单元1106。
所述计算机程序可以被分割成一个或多个模块/单元，所述一个或者多个模块/单元被存储在所述存储器121中，并由所述处理器120执行，以完成本申请。所述一个或多个模块/单元可以是能够完成特定功能的一系列计算机程序指令段，该指令段用于描述所述计算机程序在所述终端中的执行过程。
例如，所述计算机程序可以被分割成：电能参数获取单元、第一平均电压获取单元、电压增量获取单元、平均电压获取单元、脉冲功率获取单元和校验单元。
计算机程序中的各单元被处理器120执行时实现上一任意实施例提供的一种缓冲电阻的校验方法。
所述终端可包括，但不仅限于，处理器120、存储器121。本领域技术人员可以理解，图12仅仅是终端的示例，并不构成对终端的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件，例如所述终端还可以包括输入输出设备、网络接入设备、总线等。
所称处理器120可以是中央处理单元(Central Processing Unit，CPU)，还可以是其他通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现成可编程门阵列(Field-Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
所述存储器121可以是所述终端的内部存储单元，例如终端的硬盘或内存。所述存储器121也可以是所述终端的外部存储设备，例如所述终端上配备的插接式硬盘，智能存储卡(Smart Media Card，SMC)，安全数字(Secure Digital，SD)卡，闪存卡(Flash Card)等。进一步地，所述存储器121还可以既包括所述终端的内部存储单元也包括外部存储设备。所述存储器121用于存储所述计算机程序以及所述终端所需的其他程序和数据。所述存储器121还可以用于暂时地存储已经输出或者将要输出的数据。
需要说明的是，为描述的方便和简洁，上述终端的结构还可以参考方法实施例中对结构的具体描述，在此不再赘述。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，仅以上述各功能单元、模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能单元、模块完成，即将所述装置的内部结构划分成不同的功能单元或模块，以完成以上描述的全部或者部分功能。实施例中的各功能单元、模块可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中，上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。另外，各功能单元、模块的具体名称也只是为了便于相互区分，并不用于限制本申请的保护范围。上述系统中单元、模块的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述或记载的部分，可以参见其它实施例的相关描述。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示 例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对各个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在本申请所提供的实施例中，应该理解到，所揭露的装置/终端和方法，可以通过其它的方式实现。例如，以上所描述的装置/终端实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通讯连接可以是通过一些接口，装置或单元的间接耦合或通讯连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的模块/单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请实现上述实施例方法中的全部或部分流程，也可以通过计算机程序来指令相关的硬件来完成，所述的计算机程序可存储于一计算机可读存储介质中，该计算机程序在被处理器执行时，可实现上述各个方法实施例的步骤。其中，所述计算机程序包括计算机程序代码，所述计算机程序代码可以为源代码形式、对象代码形式、可执行文件或某些中间形式等。所述计算机可读介质可以包括：能够携带所述计算机程序代码的任何实体或装置、记录介质、U盘、移动硬盘、磁碟、光盘、计算机存储器、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、电载波信号、电信信号以及软件分发介质等。需要说明的是，所述计算机可读介质包含的内容可以根据司法管辖区内立法和专利实践的要求进行适当的增减，例如在某些司法管辖区，根据立法和专利实践，计算机可读介质不包括电载波信号和电信信号。
以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其 依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

Claims (10)

  1. 一种缓冲电阻的校验方法，包括：
    获取电源的电能参数、所述缓冲电阻的阻值和母线电容的电容值；所述电源为被配置为通过所述缓冲电阻向所述母线电容进行预充电的电源；
    获取所述母线电容的初始电压值作为所述母线电容在第一单位时间的第一平均电压；
    基于所述电能参数、所述阻值、所述电容值以及所述第一平均电压，获取每个单位时间内所述母线电容的电压增量；
    根据所述第一平均电压和所述电压增量，获取所述母线电容在每个所述单位时间的平均电压；
    根据所述电能参数、所述阻值以及所述平均电压，获取所述缓冲电阻在目标时间的实际脉冲功率；
    将所述实际脉冲功率作为所述缓冲电阻的校验参考参数。
  2. 如权利要求1所述的缓冲电阻的校验方法，其特征在于，所述电能参数包括所述电源的电压峰值和电压频率；
    所述基于所述电能参数、所述阻值、所述电容值以及所述第一平均电压，获取每个单位时间内所述母线电容的电压增量，采用电压增量公式进行计算；
    所述电压增量公式的表达式为：
    Figure PCTCN2022132703-appb-100001
    V i+1＝V i+ΔV i；
    其中，
    Figure PCTCN2022132703-appb-100002
    θ 2＝π-θ 1；V i表示第i个单位时间的平均电压，V inmax表示所述电压峰值，ω＝2πf，f表示所述电压频率，R表示所述缓冲电阻的阻值，C表示所述母线电容的电容值，ΔV i表示第i个单位时间内所述母线电容的电压增量。
  3. 如权利要求2所述的缓冲电阻的校验方法，其特征在于，所述根据所述电能参数、所述阻值以及所述平均电压，获取所述缓冲电阻在目标时间的实际脉冲功率，包括：
    根据所述电压峰值、所述电压频率、所述阻值以及各单位时间的平均电压，计算所述缓冲电阻在每个所述单位时间内的瞬时平均功率；
    根据每个单位时间内的瞬时平均功率和脉冲功率公式，确定所述缓冲电阻在目标时间的实际脉冲功率；
    其中，所述脉冲功率公式为：
    Figure PCTCN2022132703-appb-100003
    P i表示所述缓冲电阻在第i个单位时间内的瞬时平均功率，T i表示目标时间，P AVG_i表示所述缓冲电阻在目标时间T i的实际脉冲功率。
  4. 如权利要求3所述的缓冲电阻的校验方法，其特征在于，所述根据所述电压峰值、所述电压频率、所述阻值以及各单位时间的平均电压，计算所述缓冲电阻在每个所述单位时间内的瞬时平均功率，采用瞬时平均功率计算公式进行计算；
    所述瞬时平均功率计算公式为：
    Figure PCTCN2022132703-appb-100004
    其中，Δt表示每个所述单位时间的时长。
  5. 如权利要求1至4任意一项所述的缓冲电阻的校验方法，其特征在于，所述将所述实际脉冲功率作为所述缓冲电阻的校验参考参数，包括：
    获取所述缓冲电阻在额定功率为第一功率时的参考脉冲功率；
    根据所述实际脉冲功率和所述参考脉冲功率，确定所述缓冲电阻的脉冲功率裕量；
    利用所述脉冲功率裕量进行所述缓冲电阻的额定功率的选型校验。
  6. 如权利要求5所述的缓冲电阻的校验方法，其特征在于，所述利用所述脉冲功率裕量进行所述缓冲电阻的额定功率的选型校验，包括：
    在所述缓冲电阻的脉冲功率裕量满足裕量要求时，将额定功率为所述第一功率的缓冲电阻确定为目标缓冲电阻；
    在所述缓冲电阻的脉冲功率裕量小于所述裕量要求时，获取所述缓冲电阻在额定功率为第二功率时的参考脉冲功率；
    返回执行所述根据所述实际脉冲功率和所述参考脉冲功率，确定所述缓冲电阻的脉冲功率裕量的步骤；其中，所述第二功率大于所述第一功率。
  7. 如权利要求6所述的缓冲电阻的校验方法，其特征在于，所述利用所述脉冲功率裕量进行所述缓冲电阻的额定功率的选型校验，还包括：
    在所述缓冲电阻的脉冲功率裕量大于所述裕量要求时，获取所述缓冲电阻在额定功率为第三功率时的参考脉冲功率；
    返回执行所述根据所述实际脉冲功率和所述参考脉冲功率，确定所述缓冲电阻的脉冲功率裕量的步骤；其中，所述第三功率小于所述第一功率。
  8. 如权利要求5所述的缓冲电阻的校验方法，其特征在于，所述根据所述实际脉冲功率和所述参考脉冲功率，确定所述缓冲电阻的脉冲功率裕量，包括：
    将各个目标时间的参考脉冲功率和对应的实际脉冲功率作差计算脉冲功率差，并计算脉冲功率差的统计量，将所述统计量作为缓冲电阻的脉冲功率裕量。
  9. 一种终端，包括存储器、处理器以及存储在所述存储器中并可在所述处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现如权利要求1至7任一项所述方法的步骤。
  10. 一种计算机可读存储介质，所述计算机可读存储介质存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求1至7任一项所述方法的步骤。
PCT/CN2022/132703 2022-02-15 2022-11-18 缓冲电阻的校验方法、终端和存储介质 WO2023155514A1 (zh)

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